hardware/fertirrega_v6
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ebb76da3b04906328988c44e9eb6d689a4447910
fertirrega_v6/Fertirrega_v6/Debug/Fertirrega_v6.list
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Fertirrega_v6.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00006acc 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000084 08006bd8 08006bd8 00007bd8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08006c5c 08006c5c 00008060 2**0
CONTENTS, READONLY
4 .ARM 00000008 08006c5c 08006c5c 00007c5c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08006c64 08006c64 00008060 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08006c64 08006c64 00007c64 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08006c68 08006c68 00007c68 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000060 20000000 08006c6c 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000478 20000060 08006ccc 00008060 2**2
ALLOC
10 ._user_heap_stack 00000600 200004d8 08006ccc 000084d8 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00008060 2**0
CONTENTS, READONLY
12 .debug_info 00013c73 00000000 00000000 00008089 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003323 00000000 00000000 0001bcfc 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001290 00000000 00000000 0001f020 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000e92 00000000 00000000 000202b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001a58b 00000000 00000000 00021142 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00017dbe 00000000 00000000 0003b6cd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00095ab0 00000000 00000000 0005348b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000e8f3b 2**0
CONTENTS, READONLY
20 .debug_frame 00004ee0 00000000 00000000 000e8f80 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000ede60 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000060 .word 0x20000060
8000128: 00000000 .word 0x00000000
800012c: 08006bc0 .word 0x08006bc0
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000064 .word 0x20000064
8000148: 08006bc0 .word 0x08006bc0
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <__aeabi_dmul>:
800015c: b570 push {r4, r5, r6, lr}
800015e: f04f 0cff mov.w ip, #255 @ 0xff
8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20
800016a: bf1d ittte ne
800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000170: ea94 0f0c teqne r4, ip
8000174: ea95 0f0c teqne r5, ip
8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc>
800017c: 442c add r4, r5
800017e: ea81 0603 eor.w r6, r1, r3
8000182: ea21 514c bic.w r1, r1, ip, lsl #21
8000186: ea23 534c bic.w r3, r3, ip, lsl #21
800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12
800018e: bf18 it ne
8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4>
800019e: fba0 ce02 umull ip, lr, r0, r2
80001a2: f04f 0500 mov.w r5, #0
80001a6: fbe1 e502 umlal lr, r5, r1, r2
80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80001ae: fbe0 e503 umlal lr, r5, r0, r3
80001b2: f04f 0600 mov.w r6, #0
80001b6: fbe1 5603 umlal r5, r6, r1, r3
80001ba: f09c 0f00 teq ip, #0
80001be: bf18 it ne
80001c0: f04e 0e01 orrne.w lr, lr, #1
80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff
80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200
80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300
80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80>
80001d2: ea5f 0e4e movs.w lr, lr, lsl #1
80001d6: 416d adcs r5, r5
80001d8: eb46 0606 adc.w r6, r6, r6
80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11
80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21
80001e4: ea4f 20c5 mov.w r0, r5, lsl #11
80001e8: ea40 505e orr.w r0, r0, lr, lsr #21
80001ec: ea4f 2ece mov.w lr, lr, lsl #11
80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80001f4: bf88 it hi
80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde>
80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
8000200: bf08 it eq
8000202: ea5f 0e50 movseq.w lr, r0, lsr #1
8000206: f150 0000 adcs.w r0, r0, #0
800020a: eb41 5104 adc.w r1, r1, r4, lsl #20
800020e: bd70 pop {r4, r5, r6, pc}
8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000214: ea46 0101 orr.w r1, r6, r1
8000218: ea40 0002 orr.w r0, r0, r2
800021c: ea81 0103 eor.w r1, r1, r3
8000220: ebb4 045c subs.w r4, r4, ip, lsr #1
8000224: bfc2 ittt gt
8000226: ebd4 050c rsbsgt r5, r4, ip
800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800022e: bd70 popgt {r4, r5, r6, pc}
8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000234: f04f 0e00 mov.w lr, #0
8000238: 3c01 subs r4, #1
800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238>
800023e: f114 0f36 cmn.w r4, #54 @ 0x36
8000242: bfde ittt le
8000244: 2000 movle r0, #0
8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
800024a: bd70 pople {r4, r5, r6, pc}
800024c: f1c4 0400 rsb r4, r4, #0
8000250: 3c20 subs r4, #32
8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164>
8000254: 340c adds r4, #12
8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134>
8000258: f104 0414 add.w r4, r4, #20
800025c: f1c4 0520 rsb r5, r4, #32
8000260: fa00 f305 lsl.w r3, r0, r5
8000264: fa20 f004 lsr.w r0, r0, r4
8000268: fa01 f205 lsl.w r2, r1, r5
800026c: ea40 0002 orr.w r0, r0, r2
8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31
800027c: fa21 f604 lsr.w r6, r1, r4
8000280: eb42 0106 adc.w r1, r2, r6
8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000288: bf08 it eq
800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800028e: bd70 pop {r4, r5, r6, pc}
8000290: f1c4 040c rsb r4, r4, #12
8000294: f1c4 0520 rsb r5, r4, #32
8000298: fa00 f304 lsl.w r3, r0, r4
800029c: fa20 f005 lsr.w r0, r0, r5
80002a0: fa01 f204 lsl.w r2, r1, r4
80002a4: ea40 0002 orr.w r0, r0, r2
80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002b0: f141 0100 adc.w r1, r1, #0
80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002b8: bf08 it eq
80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002be: bd70 pop {r4, r5, r6, pc}
80002c0: f1c4 0520 rsb r5, r4, #32
80002c4: fa00 f205 lsl.w r2, r0, r5
80002c8: ea4e 0e02 orr.w lr, lr, r2
80002cc: fa20 f304 lsr.w r3, r0, r4
80002d0: fa01 f205 lsl.w r2, r1, r5
80002d4: ea43 0302 orr.w r3, r3, r2
80002d8: fa21 f004 lsr.w r0, r1, r4
80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002e0: fa21 f204 lsr.w r2, r1, r4
80002e4: ea20 0002 bic.w r0, r0, r2
80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31
80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002f0: bf08 it eq
80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002f6: bd70 pop {r4, r5, r6, pc}
80002f8: f094 0f00 teq r4, #0
80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2>
80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
8000302: 0040 lsls r0, r0, #1
8000304: eb41 0101 adc.w r1, r1, r1
8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000
800030c: bf08 it eq
800030e: 3c01 subeq r4, #1
8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6>
8000312: ea41 0106 orr.w r1, r1, r6
8000316: f095 0f00 teq r5, #0
800031a: bf18 it ne
800031c: 4770 bxne lr
800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
8000322: 0052 lsls r2, r2, #1
8000324: eb43 0303 adc.w r3, r3, r3
8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000
800032c: bf08 it eq
800032e: 3d01 subeq r5, #1
8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6>
8000332: ea43 0306 orr.w r3, r3, r6
8000336: 4770 bx lr
8000338: ea94 0f0c teq r4, ip
800033c: ea0c 5513 and.w r5, ip, r3, lsr #20
8000340: bf18 it ne
8000342: ea95 0f0c teqne r5, ip
8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206>
8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1
800034c: bf18 it ne
800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c>
8000354: ea81 0103 eor.w r1, r1, r3
8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800035c: f04f 0000 mov.w r0, #0
8000360: bd70 pop {r4, r5, r6, pc}
8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000366: bf06 itte eq
8000368: 4610 moveq r0, r2
800036a: 4619 moveq r1, r3
800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a>
8000372: ea94 0f0c teq r4, ip
8000376: d102 bne.n 800037e <__aeabi_dmul+0x222>
8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12
800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a>
800037e: ea95 0f0c teq r5, ip
8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234>
8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000388: bf1c itt ne
800038a: 4610 movne r0, r2
800038c: 4619 movne r1, r3
800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a>
8000390: ea81 0103 eor.w r1, r1, r3
8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003a0: f04f 0000 mov.w r0, #0
80003a4: bd70 pop {r4, r5, r6, pc}
80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80003ae: bd70 pop {r4, r5, r6, pc}
080003b0 <__aeabi_drsub>:
80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
80003b4: e002 b.n 80003bc <__adddf3>
80003b6: bf00 nop
080003b8 <__aeabi_dsub>:
80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
080003bc <__adddf3>:
80003bc: b530 push {r4, r5, lr}
80003be: ea4f 0441 mov.w r4, r1, lsl #1
80003c2: ea4f 0543 mov.w r5, r3, lsl #1
80003c6: ea94 0f05 teq r4, r5
80003ca: bf08 it eq
80003cc: ea90 0f02 teqeq r0, r2
80003d0: bf1f itttt ne
80003d2: ea54 0c00 orrsne.w ip, r4, r0
80003d6: ea55 0c02 orrsne.w ip, r5, r2
80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21
80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21
80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee>
80003e6: ea4f 5454 mov.w r4, r4, lsr #21
80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21
80003ee: bfb8 it lt
80003f0: 426d neglt r5, r5
80003f2: dd0c ble.n 800040e <__adddf3+0x52>
80003f4: 442c add r4, r5
80003f6: ea80 0202 eor.w r2, r0, r2
80003fa: ea81 0303 eor.w r3, r1, r3
80003fe: ea82 0000 eor.w r0, r2, r0
8000402: ea83 0101 eor.w r1, r3, r1
8000406: ea80 0202 eor.w r2, r0, r2
800040a: ea81 0303 eor.w r3, r1, r3
800040e: 2d36 cmp r5, #54 @ 0x36
8000410: bf88 it hi
8000412: bd30 pophi {r4, r5, pc}
8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000418: ea4f 3101 mov.w r1, r1, lsl #12
800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000424: d002 beq.n 800042c <__adddf3+0x70>
8000426: 4240 negs r0, r0
8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1
800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000430: ea4f 3303 mov.w r3, r3, lsl #12
8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000438: d002 beq.n 8000440 <__adddf3+0x84>
800043a: 4252 negs r2, r2
800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000440: ea94 0f05 teq r4, r5
8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da>
8000448: f1a4 0401 sub.w r4, r4, #1
800044c: f1d5 0e20 rsbs lr, r5, #32
8000450: db0d blt.n 800046e <__adddf3+0xb2>
8000452: fa02 fc0e lsl.w ip, r2, lr
8000456: fa22 f205 lsr.w r2, r2, r5
800045a: 1880 adds r0, r0, r2
800045c: f141 0100 adc.w r1, r1, #0
8000460: fa03 f20e lsl.w r2, r3, lr
8000464: 1880 adds r0, r0, r2
8000466: fa43 f305 asr.w r3, r3, r5
800046a: 4159 adcs r1, r3
800046c: e00e b.n 800048c <__adddf3+0xd0>
800046e: f1a5 0520 sub.w r5, r5, #32
8000472: f10e 0e20 add.w lr, lr, #32
8000476: 2a01 cmp r2, #1
8000478: fa03 fc0e lsl.w ip, r3, lr
800047c: bf28 it cs
800047e: f04c 0c02 orrcs.w ip, ip, #2
8000482: fa43 f305 asr.w r3, r3, r5
8000486: 18c0 adds r0, r0, r3
8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31
800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000490: d507 bpl.n 80004a2 <__adddf3+0xe6>
8000492: f04f 0e00 mov.w lr, #0
8000496: f1dc 0c00 rsbs ip, ip, #0
800049a: eb7e 0000 sbcs.w r0, lr, r0
800049e: eb6e 0101 sbc.w r1, lr, r1
80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80004a6: d31b bcc.n 80004e0 <__adddf3+0x124>
80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c>
80004ae: 0849 lsrs r1, r1, #1
80004b0: ea5f 0030 movs.w r0, r0, rrx
80004b4: ea4f 0c3c mov.w ip, ip, rrx
80004b8: f104 0401 add.w r4, r4, #1
80004bc: ea4f 5244 mov.w r2, r4, lsl #21
80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240>
80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80004cc: bf08 it eq
80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1
80004d2: f150 0000 adcs.w r0, r0, #0
80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20
80004da: ea41 0105 orr.w r1, r1, r5
80004de: bd30 pop {r4, r5, pc}
80004e0: ea5f 0c4c movs.w ip, ip, lsl #1
80004e4: 4140 adcs r0, r0
80004e6: eb41 0101 adc.w r1, r1, r1
80004ea: 3c01 subs r4, #1
80004ec: bf28 it cs
80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c>
80004f4: f091 0f00 teq r1, #0
80004f8: bf04 itt eq
80004fa: 4601 moveq r1, r0
80004fc: 2000 moveq r0, #0
80004fe: fab1 f381 clz r3, r1
8000502: bf08 it eq
8000504: 3320 addeq r3, #32
8000506: f1a3 030b sub.w r3, r3, #11
800050a: f1b3 0220 subs.w r2, r3, #32
800050e: da0c bge.n 800052a <__adddf3+0x16e>
8000510: 320c adds r2, #12
8000512: dd08 ble.n 8000526 <__adddf3+0x16a>
8000514: f102 0c14 add.w ip, r2, #20
8000518: f1c2 020c rsb r2, r2, #12
800051c: fa01 f00c lsl.w r0, r1, ip
8000520: fa21 f102 lsr.w r1, r1, r2
8000524: e00c b.n 8000540 <__adddf3+0x184>
8000526: f102 0214 add.w r2, r2, #20
800052a: bfd8 it le
800052c: f1c2 0c20 rsble ip, r2, #32
8000530: fa01 f102 lsl.w r1, r1, r2
8000534: fa20 fc0c lsr.w ip, r0, ip
8000538: bfdc itt le
800053a: ea41 010c orrle.w r1, r1, ip
800053e: 4090 lslle r0, r2
8000540: 1ae4 subs r4, r4, r3
8000542: bfa2 ittt ge
8000544: eb01 5104 addge.w r1, r1, r4, lsl #20
8000548: 4329 orrge r1, r5
800054a: bd30 popge {r4, r5, pc}
800054c: ea6f 0404 mvn.w r4, r4
8000550: 3c1f subs r4, #31
8000552: da1c bge.n 800058e <__adddf3+0x1d2>
8000554: 340c adds r4, #12
8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba>
8000558: f104 0414 add.w r4, r4, #20
800055c: f1c4 0220 rsb r2, r4, #32
8000560: fa20 f004 lsr.w r0, r0, r4
8000564: fa01 f302 lsl.w r3, r1, r2
8000568: ea40 0003 orr.w r0, r0, r3
800056c: fa21 f304 lsr.w r3, r1, r4
8000570: ea45 0103 orr.w r1, r5, r3
8000574: bd30 pop {r4, r5, pc}
8000576: f1c4 040c rsb r4, r4, #12
800057a: f1c4 0220 rsb r2, r4, #32
800057e: fa20 f002 lsr.w r0, r0, r2
8000582: fa01 f304 lsl.w r3, r1, r4
8000586: ea40 0003 orr.w r0, r0, r3
800058a: 4629 mov r1, r5
800058c: bd30 pop {r4, r5, pc}
800058e: fa21 f004 lsr.w r0, r1, r4
8000592: 4629 mov r1, r5
8000594: bd30 pop {r4, r5, pc}
8000596: f094 0f00 teq r4, #0
800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800059e: bf06 itte eq
80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
80005a4: 3401 addeq r4, #1
80005a6: 3d01 subne r5, #1
80005a8: e74e b.n 8000448 <__adddf3+0x8c>
80005aa: ea7f 5c64 mvns.w ip, r4, asr #21
80005ae: bf18 it ne
80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21
80005b4: d029 beq.n 800060a <__adddf3+0x24e>
80005b6: ea94 0f05 teq r4, r5
80005ba: bf08 it eq
80005bc: ea90 0f02 teqeq r0, r2
80005c0: d005 beq.n 80005ce <__adddf3+0x212>
80005c2: ea54 0c00 orrs.w ip, r4, r0
80005c6: bf04 itt eq
80005c8: 4619 moveq r1, r3
80005ca: 4610 moveq r0, r2
80005cc: bd30 pop {r4, r5, pc}
80005ce: ea91 0f03 teq r1, r3
80005d2: bf1e ittt ne
80005d4: 2100 movne r1, #0
80005d6: 2000 movne r0, #0
80005d8: bd30 popne {r4, r5, pc}
80005da: ea5f 5c54 movs.w ip, r4, lsr #21
80005de: d105 bne.n 80005ec <__adddf3+0x230>
80005e0: 0040 lsls r0, r0, #1
80005e2: 4149 adcs r1, r1
80005e4: bf28 it cs
80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80005ea: bd30 pop {r4, r5, pc}
80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80005f0: bf3c itt cc
80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80005f6: bd30 popcc {r4, r5, pc}
80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000604: f04f 0000 mov.w r0, #0
8000608: bd30 pop {r4, r5, pc}
800060a: ea7f 5c64 mvns.w ip, r4, asr #21
800060e: bf1a itte ne
8000610: 4619 movne r1, r3
8000612: 4610 movne r0, r2
8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000618: bf1c itt ne
800061a: 460b movne r3, r1
800061c: 4602 movne r2, r0
800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000622: bf06 itte eq
8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12
8000628: ea91 0f03 teqeq r1, r3
800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000630: bd30 pop {r4, r5, pc}
8000632: bf00 nop
08000634 <__aeabi_ui2d>:
8000634: f090 0f00 teq r0, #0
8000638: bf04 itt eq
800063a: 2100 moveq r1, #0
800063c: 4770 bxeq lr
800063e: b530 push {r4, r5, lr}
8000640: f44f 6480 mov.w r4, #1024 @ 0x400
8000644: f104 0432 add.w r4, r4, #50 @ 0x32
8000648: f04f 0500 mov.w r5, #0
800064c: f04f 0100 mov.w r1, #0
8000650: e750 b.n 80004f4 <__adddf3+0x138>
8000652: bf00 nop
08000654 <__aeabi_i2d>:
8000654: f090 0f00 teq r0, #0
8000658: bf04 itt eq
800065a: 2100 moveq r1, #0
800065c: 4770 bxeq lr
800065e: b530 push {r4, r5, lr}
8000660: f44f 6480 mov.w r4, #1024 @ 0x400
8000664: f104 0432 add.w r4, r4, #50 @ 0x32
8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800066c: bf48 it mi
800066e: 4240 negmi r0, r0
8000670: f04f 0100 mov.w r1, #0
8000674: e73e b.n 80004f4 <__adddf3+0x138>
8000676: bf00 nop
08000678 <__aeabi_f2d>:
8000678: 0042 lsls r2, r0, #1
800067a: ea4f 01e2 mov.w r1, r2, asr #3
800067e: ea4f 0131 mov.w r1, r1, rrx
8000682: ea4f 7002 mov.w r0, r2, lsl #28
8000686: bf1f itttt ne
8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000694: 4770 bxne lr
8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800069a: bf08 it eq
800069c: 4770 bxeq lr
800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000
80006a2: bf04 itt eq
80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
80006a8: 4770 bxeq lr
80006aa: b530 push {r4, r5, lr}
80006ac: f44f 7460 mov.w r4, #896 @ 0x380
80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006b8: e71c b.n 80004f4 <__adddf3+0x138>
80006ba: bf00 nop
080006bc <__aeabi_ul2d>:
80006bc: ea50 0201 orrs.w r2, r0, r1
80006c0: bf08 it eq
80006c2: 4770 bxeq lr
80006c4: b530 push {r4, r5, lr}
80006c6: f04f 0500 mov.w r5, #0
80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16>
080006cc <__aeabi_l2d>:
80006cc: ea50 0201 orrs.w r2, r0, r1
80006d0: bf08 it eq
80006d2: 4770 bxeq lr
80006d4: b530 push {r4, r5, lr}
80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16>
80006dc: 4240 negs r0, r0
80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1
80006e2: f44f 6480 mov.w r4, #1024 @ 0x400
80006e6: f104 0432 add.w r4, r4, #50 @ 0x32
80006ea: ea5f 5c91 movs.w ip, r1, lsr #22
80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6>
80006f2: f04f 0203 mov.w r2, #3
80006f6: ea5f 0cdc movs.w ip, ip, lsr #3
80006fa: bf18 it ne
80006fc: 3203 addne r2, #3
80006fe: ea5f 0cdc movs.w ip, ip, lsr #3
8000702: bf18 it ne
8000704: 3203 addne r2, #3
8000706: eb02 02dc add.w r2, r2, ip, lsr #3
800070a: f1c2 0320 rsb r3, r2, #32
800070e: fa00 fc03 lsl.w ip, r0, r3
8000712: fa20 f002 lsr.w r0, r0, r2
8000716: fa01 fe03 lsl.w lr, r1, r3
800071a: ea40 000e orr.w r0, r0, lr
800071e: fa21 f102 lsr.w r1, r1, r2
8000722: 4414 add r4, r2
8000724: e6bd b.n 80004a2 <__adddf3+0xe6>
8000726: bf00 nop
08000728 <__gedf2>:
8000728: f04f 3cff mov.w ip, #4294967295
800072c: e006 b.n 800073c <__cmpdf2+0x4>
800072e: bf00 nop
08000730 <__ledf2>:
8000730: f04f 0c01 mov.w ip, #1
8000734: e002 b.n 800073c <__cmpdf2+0x4>
8000736: bf00 nop
08000738 <__cmpdf2>:
8000738: f04f 0c01 mov.w ip, #1
800073c: f84d cd04 str.w ip, [sp, #-4]!
8000740: ea4f 0c41 mov.w ip, r1, lsl #1
8000744: ea7f 5c6c mvns.w ip, ip, asr #21
8000748: ea4f 0c43 mov.w ip, r3, lsl #1
800074c: bf18 it ne
800074e: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000752: d01b beq.n 800078c <__cmpdf2+0x54>
8000754: b001 add sp, #4
8000756: ea50 0c41 orrs.w ip, r0, r1, lsl #1
800075a: bf0c ite eq
800075c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000760: ea91 0f03 teqne r1, r3
8000764: bf02 ittt eq
8000766: ea90 0f02 teqeq r0, r2
800076a: 2000 moveq r0, #0
800076c: 4770 bxeq lr
800076e: f110 0f00 cmn.w r0, #0
8000772: ea91 0f03 teq r1, r3
8000776: bf58 it pl
8000778: 4299 cmppl r1, r3
800077a: bf08 it eq
800077c: 4290 cmpeq r0, r2
800077e: bf2c ite cs
8000780: 17d8 asrcs r0, r3, #31
8000782: ea6f 70e3 mvncc.w r0, r3, asr #31
8000786: f040 0001 orr.w r0, r0, #1
800078a: 4770 bx lr
800078c: ea4f 0c41 mov.w ip, r1, lsl #1
8000790: ea7f 5c6c mvns.w ip, ip, asr #21
8000794: d102 bne.n 800079c <__cmpdf2+0x64>
8000796: ea50 3c01 orrs.w ip, r0, r1, lsl #12
800079a: d107 bne.n 80007ac <__cmpdf2+0x74>
800079c: ea4f 0c43 mov.w ip, r3, lsl #1
80007a0: ea7f 5c6c mvns.w ip, ip, asr #21
80007a4: d1d6 bne.n 8000754 <__cmpdf2+0x1c>
80007a6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
80007aa: d0d3 beq.n 8000754 <__cmpdf2+0x1c>
80007ac: f85d 0b04 ldr.w r0, [sp], #4
80007b0: 4770 bx lr
80007b2: bf00 nop
080007b4 <__aeabi_cdrcmple>:
80007b4: 4684 mov ip, r0
80007b6: 4610 mov r0, r2
80007b8: 4662 mov r2, ip
80007ba: 468c mov ip, r1
80007bc: 4619 mov r1, r3
80007be: 4663 mov r3, ip
80007c0: e000 b.n 80007c4 <__aeabi_cdcmpeq>
80007c2: bf00 nop
080007c4 <__aeabi_cdcmpeq>:
80007c4: b501 push {r0, lr}
80007c6: f7ff ffb7 bl 8000738 <__cmpdf2>
80007ca: 2800 cmp r0, #0
80007cc: bf48 it mi
80007ce: f110 0f00 cmnmi.w r0, #0
80007d2: bd01 pop {r0, pc}
080007d4 <__aeabi_dcmpeq>:
80007d4: f84d ed08 str.w lr, [sp, #-8]!
80007d8: f7ff fff4 bl 80007c4 <__aeabi_cdcmpeq>
80007dc: bf0c ite eq
80007de: 2001 moveq r0, #1
80007e0: 2000 movne r0, #0
80007e2: f85d fb08 ldr.w pc, [sp], #8
80007e6: bf00 nop
080007e8 <__aeabi_dcmplt>:
80007e8: f84d ed08 str.w lr, [sp, #-8]!
80007ec: f7ff ffea bl 80007c4 <__aeabi_cdcmpeq>
80007f0: bf34 ite cc
80007f2: 2001 movcc r0, #1
80007f4: 2000 movcs r0, #0
80007f6: f85d fb08 ldr.w pc, [sp], #8
80007fa: bf00 nop
080007fc <__aeabi_dcmple>:
80007fc: f84d ed08 str.w lr, [sp, #-8]!
8000800: f7ff ffe0 bl 80007c4 <__aeabi_cdcmpeq>
8000804: bf94 ite ls
8000806: 2001 movls r0, #1
8000808: 2000 movhi r0, #0
800080a: f85d fb08 ldr.w pc, [sp], #8
800080e: bf00 nop
08000810 <__aeabi_dcmpge>:
8000810: f84d ed08 str.w lr, [sp, #-8]!
8000814: f7ff ffce bl 80007b4 <__aeabi_cdrcmple>
8000818: bf94 ite ls
800081a: 2001 movls r0, #1
800081c: 2000 movhi r0, #0
800081e: f85d fb08 ldr.w pc, [sp], #8
8000822: bf00 nop
08000824 <__aeabi_dcmpgt>:
8000824: f84d ed08 str.w lr, [sp, #-8]!
8000828: f7ff ffc4 bl 80007b4 <__aeabi_cdrcmple>
800082c: bf34 ite cc
800082e: 2001 movcc r0, #1
8000830: 2000 movcs r0, #0
8000832: f85d fb08 ldr.w pc, [sp], #8
8000836: bf00 nop
08000838 <__aeabi_d2iz>:
8000838: ea4f 0241 mov.w r2, r1, lsl #1
800083c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000840: d215 bcs.n 800086e <__aeabi_d2iz+0x36>
8000842: d511 bpl.n 8000868 <__aeabi_d2iz+0x30>
8000844: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000848: ebb3 5262 subs.w r2, r3, r2, asr #21
800084c: d912 bls.n 8000874 <__aeabi_d2iz+0x3c>
800084e: ea4f 23c1 mov.w r3, r1, lsl #11
8000852: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000856: ea43 5350 orr.w r3, r3, r0, lsr #21
800085a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
800085e: fa23 f002 lsr.w r0, r3, r2
8000862: bf18 it ne
8000864: 4240 negne r0, r0
8000866: 4770 bx lr
8000868: f04f 0000 mov.w r0, #0
800086c: 4770 bx lr
800086e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000872: d105 bne.n 8000880 <__aeabi_d2iz+0x48>
8000874: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000878: bf08 it eq
800087a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
800087e: 4770 bx lr
8000880: f04f 0000 mov.w r0, #0
8000884: 4770 bx lr
8000886: bf00 nop
08000888 <__aeabi_frsub>:
8000888: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
800088c: e002 b.n 8000894 <__addsf3>
800088e: bf00 nop
08000890 <__aeabi_fsub>:
8000890: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
08000894 <__addsf3>:
8000894: 0042 lsls r2, r0, #1
8000896: bf1f itttt ne
8000898: ea5f 0341 movsne.w r3, r1, lsl #1
800089c: ea92 0f03 teqne r2, r3
80008a0: ea7f 6c22 mvnsne.w ip, r2, asr #24
80008a4: ea7f 6c23 mvnsne.w ip, r3, asr #24
80008a8: d06a beq.n 8000980 <__addsf3+0xec>
80008aa: ea4f 6212 mov.w r2, r2, lsr #24
80008ae: ebd2 6313 rsbs r3, r2, r3, lsr #24
80008b2: bfc1 itttt gt
80008b4: 18d2 addgt r2, r2, r3
80008b6: 4041 eorgt r1, r0
80008b8: 4048 eorgt r0, r1
80008ba: 4041 eorgt r1, r0
80008bc: bfb8 it lt
80008be: 425b neglt r3, r3
80008c0: 2b19 cmp r3, #25
80008c2: bf88 it hi
80008c4: 4770 bxhi lr
80008c6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
80008ca: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80008ce: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
80008d2: bf18 it ne
80008d4: 4240 negne r0, r0
80008d6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80008da: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
80008de: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
80008e2: bf18 it ne
80008e4: 4249 negne r1, r1
80008e6: ea92 0f03 teq r2, r3
80008ea: d03f beq.n 800096c <__addsf3+0xd8>
80008ec: f1a2 0201 sub.w r2, r2, #1
80008f0: fa41 fc03 asr.w ip, r1, r3
80008f4: eb10 000c adds.w r0, r0, ip
80008f8: f1c3 0320 rsb r3, r3, #32
80008fc: fa01 f103 lsl.w r1, r1, r3
8000900: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
8000904: d502 bpl.n 800090c <__addsf3+0x78>
8000906: 4249 negs r1, r1
8000908: eb60 0040 sbc.w r0, r0, r0, lsl #1
800090c: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
8000910: d313 bcc.n 800093a <__addsf3+0xa6>
8000912: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
8000916: d306 bcc.n 8000926 <__addsf3+0x92>
8000918: 0840 lsrs r0, r0, #1
800091a: ea4f 0131 mov.w r1, r1, rrx
800091e: f102 0201 add.w r2, r2, #1
8000922: 2afe cmp r2, #254 @ 0xfe
8000924: d251 bcs.n 80009ca <__addsf3+0x136>
8000926: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
800092a: eb40 50c2 adc.w r0, r0, r2, lsl #23
800092e: bf08 it eq
8000930: f020 0001 biceq.w r0, r0, #1
8000934: ea40 0003 orr.w r0, r0, r3
8000938: 4770 bx lr
800093a: 0049 lsls r1, r1, #1
800093c: eb40 0000 adc.w r0, r0, r0
8000940: 3a01 subs r2, #1
8000942: bf28 it cs
8000944: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
8000948: d2ed bcs.n 8000926 <__addsf3+0x92>
800094a: fab0 fc80 clz ip, r0
800094e: f1ac 0c08 sub.w ip, ip, #8
8000952: ebb2 020c subs.w r2, r2, ip
8000956: fa00 f00c lsl.w r0, r0, ip
800095a: bfaa itet ge
800095c: eb00 50c2 addge.w r0, r0, r2, lsl #23
8000960: 4252 neglt r2, r2
8000962: 4318 orrge r0, r3
8000964: bfbc itt lt
8000966: 40d0 lsrlt r0, r2
8000968: 4318 orrlt r0, r3
800096a: 4770 bx lr
800096c: f092 0f00 teq r2, #0
8000970: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
8000974: bf06 itte eq
8000976: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
800097a: 3201 addeq r2, #1
800097c: 3b01 subne r3, #1
800097e: e7b5 b.n 80008ec <__addsf3+0x58>
8000980: ea4f 0341 mov.w r3, r1, lsl #1
8000984: ea7f 6c22 mvns.w ip, r2, asr #24
8000988: bf18 it ne
800098a: ea7f 6c23 mvnsne.w ip, r3, asr #24
800098e: d021 beq.n 80009d4 <__addsf3+0x140>
8000990: ea92 0f03 teq r2, r3
8000994: d004 beq.n 80009a0 <__addsf3+0x10c>
8000996: f092 0f00 teq r2, #0
800099a: bf08 it eq
800099c: 4608 moveq r0, r1
800099e: 4770 bx lr
80009a0: ea90 0f01 teq r0, r1
80009a4: bf1c itt ne
80009a6: 2000 movne r0, #0
80009a8: 4770 bxne lr
80009aa: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
80009ae: d104 bne.n 80009ba <__addsf3+0x126>
80009b0: 0040 lsls r0, r0, #1
80009b2: bf28 it cs
80009b4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
80009b8: 4770 bx lr
80009ba: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
80009be: bf3c itt cc
80009c0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
80009c4: 4770 bxcc lr
80009c6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
80009ca: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
80009ce: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80009d2: 4770 bx lr
80009d4: ea7f 6222 mvns.w r2, r2, asr #24
80009d8: bf16 itet ne
80009da: 4608 movne r0, r1
80009dc: ea7f 6323 mvnseq.w r3, r3, asr #24
80009e0: 4601 movne r1, r0
80009e2: 0242 lsls r2, r0, #9
80009e4: bf06 itte eq
80009e6: ea5f 2341 movseq.w r3, r1, lsl #9
80009ea: ea90 0f01 teqeq r0, r1
80009ee: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
80009f2: 4770 bx lr
080009f4 <__aeabi_ui2f>:
80009f4: f04f 0300 mov.w r3, #0
80009f8: e004 b.n 8000a04 <__aeabi_i2f+0x8>
80009fa: bf00 nop
080009fc <__aeabi_i2f>:
80009fc: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
8000a00: bf48 it mi
8000a02: 4240 negmi r0, r0
8000a04: ea5f 0c00 movs.w ip, r0
8000a08: bf08 it eq
8000a0a: 4770 bxeq lr
8000a0c: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
8000a10: 4601 mov r1, r0
8000a12: f04f 0000 mov.w r0, #0
8000a16: e01c b.n 8000a52 <__aeabi_l2f+0x2a>
08000a18 <__aeabi_ul2f>:
8000a18: ea50 0201 orrs.w r2, r0, r1
8000a1c: bf08 it eq
8000a1e: 4770 bxeq lr
8000a20: f04f 0300 mov.w r3, #0
8000a24: e00a b.n 8000a3c <__aeabi_l2f+0x14>
8000a26: bf00 nop
08000a28 <__aeabi_l2f>:
8000a28: ea50 0201 orrs.w r2, r0, r1
8000a2c: bf08 it eq
8000a2e: 4770 bxeq lr
8000a30: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
8000a34: d502 bpl.n 8000a3c <__aeabi_l2f+0x14>
8000a36: 4240 negs r0, r0
8000a38: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000a3c: ea5f 0c01 movs.w ip, r1
8000a40: bf02 ittt eq
8000a42: 4684 moveq ip, r0
8000a44: 4601 moveq r1, r0
8000a46: 2000 moveq r0, #0
8000a48: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
8000a4c: bf08 it eq
8000a4e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
8000a52: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
8000a56: fabc f28c clz r2, ip
8000a5a: 3a08 subs r2, #8
8000a5c: eba3 53c2 sub.w r3, r3, r2, lsl #23
8000a60: db10 blt.n 8000a84 <__aeabi_l2f+0x5c>
8000a62: fa01 fc02 lsl.w ip, r1, r2
8000a66: 4463 add r3, ip
8000a68: fa00 fc02 lsl.w ip, r0, r2
8000a6c: f1c2 0220 rsb r2, r2, #32
8000a70: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000a74: fa20 f202 lsr.w r2, r0, r2
8000a78: eb43 0002 adc.w r0, r3, r2
8000a7c: bf08 it eq
8000a7e: f020 0001 biceq.w r0, r0, #1
8000a82: 4770 bx lr
8000a84: f102 0220 add.w r2, r2, #32
8000a88: fa01 fc02 lsl.w ip, r1, r2
8000a8c: f1c2 0220 rsb r2, r2, #32
8000a90: ea50 004c orrs.w r0, r0, ip, lsl #1
8000a94: fa21 f202 lsr.w r2, r1, r2
8000a98: eb43 0002 adc.w r0, r3, r2
8000a9c: bf08 it eq
8000a9e: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000aa2: 4770 bx lr
08000aa4 <__aeabi_fmul>:
8000aa4: f04f 0cff mov.w ip, #255 @ 0xff
8000aa8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000aac: bf1e ittt ne
8000aae: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000ab2: ea92 0f0c teqne r2, ip
8000ab6: ea93 0f0c teqne r3, ip
8000aba: d06f beq.n 8000b9c <__aeabi_fmul+0xf8>
8000abc: 441a add r2, r3
8000abe: ea80 0c01 eor.w ip, r0, r1
8000ac2: 0240 lsls r0, r0, #9
8000ac4: bf18 it ne
8000ac6: ea5f 2141 movsne.w r1, r1, lsl #9
8000aca: d01e beq.n 8000b0a <__aeabi_fmul+0x66>
8000acc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000ad0: ea43 1050 orr.w r0, r3, r0, lsr #5
8000ad4: ea43 1151 orr.w r1, r3, r1, lsr #5
8000ad8: fba0 3101 umull r3, r1, r0, r1
8000adc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000ae0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8000ae4: bf3e ittt cc
8000ae6: 0049 lslcc r1, r1, #1
8000ae8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
8000aec: 005b lslcc r3, r3, #1
8000aee: ea40 0001 orr.w r0, r0, r1
8000af2: f162 027f sbc.w r2, r2, #127 @ 0x7f
8000af6: 2afd cmp r2, #253 @ 0xfd
8000af8: d81d bhi.n 8000b36 <__aeabi_fmul+0x92>
8000afa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8000afe: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000b02: bf08 it eq
8000b04: f020 0001 biceq.w r0, r0, #1
8000b08: 4770 bx lr
8000b0a: f090 0f00 teq r0, #0
8000b0e: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000b12: bf08 it eq
8000b14: 0249 lsleq r1, r1, #9
8000b16: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000b1a: ea40 2051 orr.w r0, r0, r1, lsr #9
8000b1e: 3a7f subs r2, #127 @ 0x7f
8000b20: bfc2 ittt gt
8000b22: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000b26: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000b2a: 4770 bxgt lr
8000b2c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000b30: f04f 0300 mov.w r3, #0
8000b34: 3a01 subs r2, #1
8000b36: dc5d bgt.n 8000bf4 <__aeabi_fmul+0x150>
8000b38: f112 0f19 cmn.w r2, #25
8000b3c: bfdc itt le
8000b3e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
8000b42: 4770 bxle lr
8000b44: f1c2 0200 rsb r2, r2, #0
8000b48: 0041 lsls r1, r0, #1
8000b4a: fa21 f102 lsr.w r1, r1, r2
8000b4e: f1c2 0220 rsb r2, r2, #32
8000b52: fa00 fc02 lsl.w ip, r0, r2
8000b56: ea5f 0031 movs.w r0, r1, rrx
8000b5a: f140 0000 adc.w r0, r0, #0
8000b5e: ea53 034c orrs.w r3, r3, ip, lsl #1
8000b62: bf08 it eq
8000b64: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000b68: 4770 bx lr
8000b6a: f092 0f00 teq r2, #0
8000b6e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000b72: bf02 ittt eq
8000b74: 0040 lsleq r0, r0, #1
8000b76: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000b7a: 3a01 subeq r2, #1
8000b7c: d0f9 beq.n 8000b72 <__aeabi_fmul+0xce>
8000b7e: ea40 000c orr.w r0, r0, ip
8000b82: f093 0f00 teq r3, #0
8000b86: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000b8a: bf02 ittt eq
8000b8c: 0049 lsleq r1, r1, #1
8000b8e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000b92: 3b01 subeq r3, #1
8000b94: d0f9 beq.n 8000b8a <__aeabi_fmul+0xe6>
8000b96: ea41 010c orr.w r1, r1, ip
8000b9a: e78f b.n 8000abc <__aeabi_fmul+0x18>
8000b9c: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000ba0: ea92 0f0c teq r2, ip
8000ba4: bf18 it ne
8000ba6: ea93 0f0c teqne r3, ip
8000baa: d00a beq.n 8000bc2 <__aeabi_fmul+0x11e>
8000bac: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000bb0: bf18 it ne
8000bb2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000bb6: d1d8 bne.n 8000b6a <__aeabi_fmul+0xc6>
8000bb8: ea80 0001 eor.w r0, r0, r1
8000bbc: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bc0: 4770 bx lr
8000bc2: f090 0f00 teq r0, #0
8000bc6: bf17 itett ne
8000bc8: f090 4f00 teqne r0, #2147483648 @ 0x80000000
8000bcc: 4608 moveq r0, r1
8000bce: f091 0f00 teqne r1, #0
8000bd2: f091 4f00 teqne r1, #2147483648 @ 0x80000000
8000bd6: d014 beq.n 8000c02 <__aeabi_fmul+0x15e>
8000bd8: ea92 0f0c teq r2, ip
8000bdc: d101 bne.n 8000be2 <__aeabi_fmul+0x13e>
8000bde: 0242 lsls r2, r0, #9
8000be0: d10f bne.n 8000c02 <__aeabi_fmul+0x15e>
8000be2: ea93 0f0c teq r3, ip
8000be6: d103 bne.n 8000bf0 <__aeabi_fmul+0x14c>
8000be8: 024b lsls r3, r1, #9
8000bea: bf18 it ne
8000bec: 4608 movne r0, r1
8000bee: d108 bne.n 8000c02 <__aeabi_fmul+0x15e>
8000bf0: ea80 0001 eor.w r0, r0, r1
8000bf4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bf8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000bfc: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c00: 4770 bx lr
8000c02: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000c06: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
8000c0a: 4770 bx lr
08000c0c <__aeabi_fdiv>:
8000c0c: f04f 0cff mov.w ip, #255 @ 0xff
8000c10: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000c14: bf1e ittt ne
8000c16: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000c1a: ea92 0f0c teqne r2, ip
8000c1e: ea93 0f0c teqne r3, ip
8000c22: d069 beq.n 8000cf8 <__aeabi_fdiv+0xec>
8000c24: eba2 0203 sub.w r2, r2, r3
8000c28: ea80 0c01 eor.w ip, r0, r1
8000c2c: 0249 lsls r1, r1, #9
8000c2e: ea4f 2040 mov.w r0, r0, lsl #9
8000c32: d037 beq.n 8000ca4 <__aeabi_fdiv+0x98>
8000c34: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8000c38: ea43 1111 orr.w r1, r3, r1, lsr #4
8000c3c: ea43 1310 orr.w r3, r3, r0, lsr #4
8000c40: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000c44: 428b cmp r3, r1
8000c46: bf38 it cc
8000c48: 005b lslcc r3, r3, #1
8000c4a: f142 027d adc.w r2, r2, #125 @ 0x7d
8000c4e: f44f 0c00 mov.w ip, #8388608 @ 0x800000
8000c52: 428b cmp r3, r1
8000c54: bf24 itt cs
8000c56: 1a5b subcs r3, r3, r1
8000c58: ea40 000c orrcs.w r0, r0, ip
8000c5c: ebb3 0f51 cmp.w r3, r1, lsr #1
8000c60: bf24 itt cs
8000c62: eba3 0351 subcs.w r3, r3, r1, lsr #1
8000c66: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000c6a: ebb3 0f91 cmp.w r3, r1, lsr #2
8000c6e: bf24 itt cs
8000c70: eba3 0391 subcs.w r3, r3, r1, lsr #2
8000c74: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000c78: ebb3 0fd1 cmp.w r3, r1, lsr #3
8000c7c: bf24 itt cs
8000c7e: eba3 03d1 subcs.w r3, r3, r1, lsr #3
8000c82: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000c86: 011b lsls r3, r3, #4
8000c88: bf18 it ne
8000c8a: ea5f 1c1c movsne.w ip, ip, lsr #4
8000c8e: d1e0 bne.n 8000c52 <__aeabi_fdiv+0x46>
8000c90: 2afd cmp r2, #253 @ 0xfd
8000c92: f63f af50 bhi.w 8000b36 <__aeabi_fmul+0x92>
8000c96: 428b cmp r3, r1
8000c98: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000c9c: bf08 it eq
8000c9e: f020 0001 biceq.w r0, r0, #1
8000ca2: 4770 bx lr
8000ca4: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000ca8: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000cac: 327f adds r2, #127 @ 0x7f
8000cae: bfc2 ittt gt
8000cb0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000cb4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000cb8: 4770 bxgt lr
8000cba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000cbe: f04f 0300 mov.w r3, #0
8000cc2: 3a01 subs r2, #1
8000cc4: e737 b.n 8000b36 <__aeabi_fmul+0x92>
8000cc6: f092 0f00 teq r2, #0
8000cca: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000cce: bf02 ittt eq
8000cd0: 0040 lsleq r0, r0, #1
8000cd2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000cd6: 3a01 subeq r2, #1
8000cd8: d0f9 beq.n 8000cce <__aeabi_fdiv+0xc2>
8000cda: ea40 000c orr.w r0, r0, ip
8000cde: f093 0f00 teq r3, #0
8000ce2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000ce6: bf02 ittt eq
8000ce8: 0049 lsleq r1, r1, #1
8000cea: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000cee: 3b01 subeq r3, #1
8000cf0: d0f9 beq.n 8000ce6 <__aeabi_fdiv+0xda>
8000cf2: ea41 010c orr.w r1, r1, ip
8000cf6: e795 b.n 8000c24 <__aeabi_fdiv+0x18>
8000cf8: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000cfc: ea92 0f0c teq r2, ip
8000d00: d108 bne.n 8000d14 <__aeabi_fdiv+0x108>
8000d02: 0242 lsls r2, r0, #9
8000d04: f47f af7d bne.w 8000c02 <__aeabi_fmul+0x15e>
8000d08: ea93 0f0c teq r3, ip
8000d0c: f47f af70 bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d10: 4608 mov r0, r1
8000d12: e776 b.n 8000c02 <__aeabi_fmul+0x15e>
8000d14: ea93 0f0c teq r3, ip
8000d18: d104 bne.n 8000d24 <__aeabi_fdiv+0x118>
8000d1a: 024b lsls r3, r1, #9
8000d1c: f43f af4c beq.w 8000bb8 <__aeabi_fmul+0x114>
8000d20: 4608 mov r0, r1
8000d22: e76e b.n 8000c02 <__aeabi_fmul+0x15e>
8000d24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000d28: bf18 it ne
8000d2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000d2e: d1ca bne.n 8000cc6 <__aeabi_fdiv+0xba>
8000d30: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
8000d34: f47f af5c bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d38: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
8000d3c: f47f af3c bne.w 8000bb8 <__aeabi_fmul+0x114>
8000d40: e75f b.n 8000c02 <__aeabi_fmul+0x15e>
8000d42: bf00 nop
08000d44 <__gesf2>:
8000d44: f04f 3cff mov.w ip, #4294967295
8000d48: e006 b.n 8000d58 <__cmpsf2+0x4>
8000d4a: bf00 nop
08000d4c <__lesf2>:
8000d4c: f04f 0c01 mov.w ip, #1
8000d50: e002 b.n 8000d58 <__cmpsf2+0x4>
8000d52: bf00 nop
08000d54 <__cmpsf2>:
8000d54: f04f 0c01 mov.w ip, #1
8000d58: f84d cd04 str.w ip, [sp, #-4]!
8000d5c: ea4f 0240 mov.w r2, r0, lsl #1
8000d60: ea4f 0341 mov.w r3, r1, lsl #1
8000d64: ea7f 6c22 mvns.w ip, r2, asr #24
8000d68: bf18 it ne
8000d6a: ea7f 6c23 mvnsne.w ip, r3, asr #24
8000d6e: d011 beq.n 8000d94 <__cmpsf2+0x40>
8000d70: b001 add sp, #4
8000d72: ea52 0c53 orrs.w ip, r2, r3, lsr #1
8000d76: bf18 it ne
8000d78: ea90 0f01 teqne r0, r1
8000d7c: bf58 it pl
8000d7e: ebb2 0003 subspl.w r0, r2, r3
8000d82: bf88 it hi
8000d84: 17c8 asrhi r0, r1, #31
8000d86: bf38 it cc
8000d88: ea6f 70e1 mvncc.w r0, r1, asr #31
8000d8c: bf18 it ne
8000d8e: f040 0001 orrne.w r0, r0, #1
8000d92: 4770 bx lr
8000d94: ea7f 6c22 mvns.w ip, r2, asr #24
8000d98: d102 bne.n 8000da0 <__cmpsf2+0x4c>
8000d9a: ea5f 2c40 movs.w ip, r0, lsl #9
8000d9e: d105 bne.n 8000dac <__cmpsf2+0x58>
8000da0: ea7f 6c23 mvns.w ip, r3, asr #24
8000da4: d1e4 bne.n 8000d70 <__cmpsf2+0x1c>
8000da6: ea5f 2c41 movs.w ip, r1, lsl #9
8000daa: d0e1 beq.n 8000d70 <__cmpsf2+0x1c>
8000dac: f85d 0b04 ldr.w r0, [sp], #4
8000db0: 4770 bx lr
8000db2: bf00 nop
08000db4 <__aeabi_cfrcmple>:
8000db4: 4684 mov ip, r0
8000db6: 4608 mov r0, r1
8000db8: 4661 mov r1, ip
8000dba: e7ff b.n 8000dbc <__aeabi_cfcmpeq>
08000dbc <__aeabi_cfcmpeq>:
8000dbc: b50f push {r0, r1, r2, r3, lr}
8000dbe: f7ff ffc9 bl 8000d54 <__cmpsf2>
8000dc2: 2800 cmp r0, #0
8000dc4: bf48 it mi
8000dc6: f110 0f00 cmnmi.w r0, #0
8000dca: bd0f pop {r0, r1, r2, r3, pc}
08000dcc <__aeabi_fcmpeq>:
8000dcc: f84d ed08 str.w lr, [sp, #-8]!
8000dd0: f7ff fff4 bl 8000dbc <__aeabi_cfcmpeq>
8000dd4: bf0c ite eq
8000dd6: 2001 moveq r0, #1
8000dd8: 2000 movne r0, #0
8000dda: f85d fb08 ldr.w pc, [sp], #8
8000dde: bf00 nop
08000de0 <__aeabi_fcmplt>:
8000de0: f84d ed08 str.w lr, [sp, #-8]!
8000de4: f7ff ffea bl 8000dbc <__aeabi_cfcmpeq>
8000de8: bf34 ite cc
8000dea: 2001 movcc r0, #1
8000dec: 2000 movcs r0, #0
8000dee: f85d fb08 ldr.w pc, [sp], #8
8000df2: bf00 nop
08000df4 <__aeabi_fcmple>:
8000df4: f84d ed08 str.w lr, [sp, #-8]!
8000df8: f7ff ffe0 bl 8000dbc <__aeabi_cfcmpeq>
8000dfc: bf94 ite ls
8000dfe: 2001 movls r0, #1
8000e00: 2000 movhi r0, #0
8000e02: f85d fb08 ldr.w pc, [sp], #8
8000e06: bf00 nop
08000e08 <__aeabi_fcmpge>:
8000e08: f84d ed08 str.w lr, [sp, #-8]!
8000e0c: f7ff ffd2 bl 8000db4 <__aeabi_cfrcmple>
8000e10: bf94 ite ls
8000e12: 2001 movls r0, #1
8000e14: 2000 movhi r0, #0
8000e16: f85d fb08 ldr.w pc, [sp], #8
8000e1a: bf00 nop
08000e1c <__aeabi_fcmpgt>:
8000e1c: f84d ed08 str.w lr, [sp, #-8]!
8000e20: f7ff ffc8 bl 8000db4 <__aeabi_cfrcmple>
8000e24: bf34 ite cc
8000e26: 2001 movcc r0, #1
8000e28: 2000 movcs r0, #0
8000e2a: f85d fb08 ldr.w pc, [sp], #8
8000e2e: bf00 nop
08000e30 <__aeabi_fcmpun>:
8000e30: ea4f 0240 mov.w r2, r0, lsl #1
8000e34: ea4f 0341 mov.w r3, r1, lsl #1
8000e38: ea7f 6c22 mvns.w ip, r2, asr #24
8000e3c: d102 bne.n 8000e44 <__aeabi_fcmpun+0x14>
8000e3e: ea5f 2c40 movs.w ip, r0, lsl #9
8000e42: d108 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e44: ea7f 6c23 mvns.w ip, r3, asr #24
8000e48: d102 bne.n 8000e50 <__aeabi_fcmpun+0x20>
8000e4a: ea5f 2c41 movs.w ip, r1, lsl #9
8000e4e: d102 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e50: f04f 0000 mov.w r0, #0
8000e54: 4770 bx lr
8000e56: f04f 0001 mov.w r0, #1
8000e5a: 4770 bx lr
08000e5c <__aeabi_f2iz>:
8000e5c: ea4f 0240 mov.w r2, r0, lsl #1
8000e60: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
8000e64: d30f bcc.n 8000e86 <__aeabi_f2iz+0x2a>
8000e66: f04f 039e mov.w r3, #158 @ 0x9e
8000e6a: ebb3 6212 subs.w r2, r3, r2, lsr #24
8000e6e: d90d bls.n 8000e8c <__aeabi_f2iz+0x30>
8000e70: ea4f 2300 mov.w r3, r0, lsl #8
8000e74: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000e78: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
8000e7c: fa23 f002 lsr.w r0, r3, r2
8000e80: bf18 it ne
8000e82: 4240 negne r0, r0
8000e84: 4770 bx lr
8000e86: f04f 0000 mov.w r0, #0
8000e8a: 4770 bx lr
8000e8c: f112 0f61 cmn.w r2, #97 @ 0x61
8000e90: d101 bne.n 8000e96 <__aeabi_f2iz+0x3a>
8000e92: 0242 lsls r2, r0, #9
8000e94: d105 bne.n 8000ea2 <__aeabi_f2iz+0x46>
8000e96: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000
8000e9a: bf08 it eq
8000e9c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000ea0: 4770 bx lr
8000ea2: f04f 0000 mov.w r0, #0
8000ea6: 4770 bx lr
08000ea8 <__aeabi_f2uiz>:
8000ea8: 0042 lsls r2, r0, #1
8000eaa: d20e bcs.n 8000eca <__aeabi_f2uiz+0x22>
8000eac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
8000eb0: d30b bcc.n 8000eca <__aeabi_f2uiz+0x22>
8000eb2: f04f 039e mov.w r3, #158 @ 0x9e
8000eb6: ebb3 6212 subs.w r2, r3, r2, lsr #24
8000eba: d409 bmi.n 8000ed0 <__aeabi_f2uiz+0x28>
8000ebc: ea4f 2300 mov.w r3, r0, lsl #8
8000ec0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000ec4: fa23 f002 lsr.w r0, r3, r2
8000ec8: 4770 bx lr
8000eca: f04f 0000 mov.w r0, #0
8000ece: 4770 bx lr
8000ed0: f112 0f61 cmn.w r2, #97 @ 0x61
8000ed4: d101 bne.n 8000eda <__aeabi_f2uiz+0x32>
8000ed6: 0242 lsls r2, r0, #9
8000ed8: d102 bne.n 8000ee0 <__aeabi_f2uiz+0x38>
8000eda: f04f 30ff mov.w r0, #4294967295
8000ede: 4770 bx lr
8000ee0: f04f 0000 mov.w r0, #0
8000ee4: 4770 bx lr
8000ee6: bf00 nop
08000ee8 <AD5934_SetRegisterValue>:
* @param numberOfBytes - Number of bytes to be written in the register
*
* @return None.
******************************************************************************/
void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
{
8000ee8: b580 push {r7, lr}
8000eea: b086 sub sp, #24
8000eec: af02 add r7, sp, #8
8000eee: 4603 mov r3, r0
8000ef0: 6039 str r1, [r7, #0]
8000ef2: 71fb strb r3, [r7, #7]
8000ef4: 4613 mov r3, r2
8000ef6: 71bb strb r3, [r7, #6]
uint8_t writeData[2] = {0, 0};
8000ef8: 2300 movs r3, #0
8000efa: 81bb strh r3, [r7, #12]
HAL_StatusTypeDef status;
union Bytes2Long AD5934_reg;
AD5934_reg.number = registerValue;
8000efc: 683b ldr r3, [r7, #0]
8000efe: 60bb str r3, [r7, #8]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f00: 2300 movs r3, #0
8000f02: 73fb strb r3, [r7, #15]
8000f04: e018 b.n 8000f38 <AD5934_SetRegisterValue+0x50>
{
writeData[0] = registerAddress - i;
8000f06: 79fa ldrb r2, [r7, #7]
8000f08: 7bfb ldrb r3, [r7, #15]
8000f0a: 1ad3 subs r3, r2, r3
8000f0c: b2db uxtb r3, r3
8000f0e: 733b strb r3, [r7, #12]
writeData[1] = AD5934_reg.bytes[i];
8000f10: 7bfb ldrb r3, [r7, #15]
8000f12: 3310 adds r3, #16
8000f14: 443b add r3, r7
8000f16: f813 3c08 ldrb.w r3, [r3, #-8]
8000f1a: 737b strb r3, [r7, #13]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000f1c: f107 020c add.w r2, r7, #12
8000f20: 2305 movs r3, #5
8000f22: 9300 str r3, [sp, #0]
8000f24: 2302 movs r3, #2
8000f26: 211a movs r1, #26
8000f28: 4807 ldr r0, [pc, #28] @ (8000f48 <AD5934_SetRegisterValue+0x60>)
8000f2a: f002 ffa3 bl 8003e74 <HAL_I2C_Master_Transmit>
8000f2e: 4603 mov r3, r0
8000f30: 73bb strb r3, [r7, #14]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f32: 7bfb ldrb r3, [r7, #15]
8000f34: 3301 adds r3, #1
8000f36: 73fb strb r3, [r7, #15]
8000f38: 7bfa ldrb r2, [r7, #15]
8000f3a: 79bb ldrb r3, [r7, #6]
8000f3c: 429a cmp r2, r3
8000f3e: d3e2 bcc.n 8000f06 <AD5934_SetRegisterValue+0x1e>
}
return;
8000f40: bf00 nop
}
8000f42: 3710 adds r7, #16
8000f44: 46bd mov sp, r7
8000f46: bd80 pop {r7, pc}
8000f48: 2000026c .word 0x2000026c
08000f4c <AD5934_GetRegisterValue>:
* @param numberOfBytes - Number of bytes to be read from the register.
*
* @return Register value.
******************************************************************************/
uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
{
8000f4c: b580 push {r7, lr}
8000f4e: b088 sub sp, #32
8000f50: af02 add r7, sp, #8
8000f52: 4603 mov r3, r0
8000f54: 460a mov r2, r1
8000f56: 71fb strb r3, [r7, #7]
8000f58: 4613 mov r3, r2
8000f5a: 71bb strb r3, [r7, #6]
uint8_t readData[1] = {0};
8000f5c: 2300 movs r3, #0
8000f5e: 753b strb r3, [r7, #20]
uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
union Bytes2Long AD5934_reg;
HAL_StatusTypeDef status;
if(numberOfBytes > 4)
8000f60: 79bb ldrb r3, [r7, #6]
8000f62: 2b04 cmp r3, #4
8000f64: d902 bls.n 8000f6c <AD5934_GetRegisterValue+0x20>
return 0xFFFFFFFF; //Overflow
8000f66: f04f 33ff mov.w r3, #4294967295
8000f6a: e031 b.n 8000fd0 <AD5934_GetRegisterValue+0x84>
AD5934_reg.number = 0;
8000f6c: 2300 movs r3, #0
8000f6e: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f70: 2300 movs r3, #0
8000f72: 75fb strb r3, [r7, #23]
8000f74: e027 b.n 8000fc6 <AD5934_GetRegisterValue+0x7a>
{
writeData[0] = AD5934_ADDR_POINTER;
8000f76: 23b0 movs r3, #176 @ 0xb0
8000f78: 743b strb r3, [r7, #16]
writeData[1] = registerAddress - i;
8000f7a: 79fa ldrb r2, [r7, #7]
8000f7c: 7dfb ldrb r3, [r7, #23]
8000f7e: 1ad3 subs r3, r2, r3
8000f80: b2db uxtb r3, r3
8000f82: 747b strb r3, [r7, #17]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000f84: f107 0210 add.w r2, r7, #16
8000f88: 2305 movs r3, #5
8000f8a: 9300 str r3, [sp, #0]
8000f8c: 2302 movs r3, #2
8000f8e: 211a movs r1, #26
8000f90: 4811 ldr r0, [pc, #68] @ (8000fd8 <AD5934_GetRegisterValue+0x8c>)
8000f92: f002 ff6f bl 8003e74 <HAL_I2C_Master_Transmit>
8000f96: 4603 mov r3, r0
8000f98: 75bb strb r3, [r7, #22]
//HAL_Delay(1);
readData[0] = 0;
8000f9a: 2300 movs r3, #0
8000f9c: 753b strb r3, [r7, #20]
status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
8000f9e: f107 0214 add.w r2, r7, #20
8000fa2: 2305 movs r3, #5
8000fa4: 9300 str r3, [sp, #0]
8000fa6: 2301 movs r3, #1
8000fa8: 211a movs r1, #26
8000faa: 480b ldr r0, [pc, #44] @ (8000fd8 <AD5934_GetRegisterValue+0x8c>)
8000fac: f003 f860 bl 8004070 <HAL_I2C_Master_Receive>
8000fb0: 4603 mov r3, r0
8000fb2: 75bb strb r3, [r7, #22]
AD5934_reg.bytes[i]=readData[0];
8000fb4: 7dfb ldrb r3, [r7, #23]
8000fb6: 7d3a ldrb r2, [r7, #20]
8000fb8: 3318 adds r3, #24
8000fba: 443b add r3, r7
8000fbc: f803 2c0c strb.w r2, [r3, #-12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000fc0: 7dfb ldrb r3, [r7, #23]
8000fc2: 3301 adds r3, #1
8000fc4: 75fb strb r3, [r7, #23]
8000fc6: 7dfa ldrb r2, [r7, #23]
8000fc8: 79bb ldrb r3, [r7, #6]
8000fca: 429a cmp r2, r3
8000fcc: d3d3 bcc.n 8000f76 <AD5934_GetRegisterValue+0x2a>
}
return AD5934_reg.number;
8000fce: 68fb ldr r3, [r7, #12]
}
8000fd0: 4618 mov r0, r3
8000fd2: 3718 adds r7, #24
8000fd4: 46bd mov sp, r7
8000fd6: bd80 pop {r7, pc}
8000fd8: 2000026c .word 0x2000026c
08000fdc <AD5934_Init>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_Init(void)
{
8000fdc: b580 push {r7, lr}
8000fde: af00 add r7, sp, #0
ADG715_ResetChannels(); // Disconnects Analog Switch on the CE / RTD / Ref Resistor
8000fe0: f000 fc18 bl 8001814 <ADG715_ResetChannels>
/************ Config Sweep******************/
// Place AD5934 in reset
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
8000fe4: 2201 movs r2, #1
8000fe6: f44f 7180 mov.w r1, #256 @ 0x100
8000fea: 2081 movs r0, #129 @ 0x81
8000fec: f7ff ff7c bl 8000ee8 <AD5934_SetRegisterValue>
// Configure starting frequency
AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_2K293HZ, 3);
8000ff0: 2203 movs r2, #3
8000ff2: 490a ldr r1, [pc, #40] @ (800101c <AD5934_Init+0x40>)
8000ff4: 2084 movs r0, #132 @ 0x84
8000ff6: f7ff ff77 bl 8000ee8 <AD5934_SetRegisterValue>
// Configure frequency increment step
AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
8000ffa: 2203 movs r2, #3
8000ffc: 2100 movs r1, #0
8000ffe: 2087 movs r0, #135 @ 0x87
8001000: f7ff ff72 bl 8000ee8 <AD5934_SetRegisterValue>
// Configure number of steps
AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
8001004: 2202 movs r2, #2
8001006: 2100 movs r1, #0
8001008: 2089 movs r0, #137 @ 0x89
800100a: f7ff ff6d bl 8000ee8 <AD5934_SetRegisterValue>
// Set 128 Settling Time
AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_64, 2);
800100e: 2202 movs r2, #2
8001010: 2140 movs r1, #64 @ 0x40
8001012: 208b movs r0, #139 @ 0x8b
8001014: f7ff ff68 bl 8000ee8 <AD5934_SetRegisterValue>
}
8001018: bf00 nop
800101a: bd80 pop {r7, pc}
800101c: 004b2314 .word 0x004b2314
08001020 <AD5934_RestartSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_RestartSweep(void)
{
8001020: b580 push {r7, lr}
8001022: af00 add r7, sp, #0
// Place AD5934 in standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8001024: 2201 movs r2, #1
8001026: 21b5 movs r1, #181 @ 0xb5
8001028: 2080 movs r0, #128 @ 0x80
800102a: f7ff ff5d bl 8000ee8 <AD5934_SetRegisterValue>
// Initialize starting frequency, Start frequency sweep, standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
800102e: 2201 movs r2, #1
8001030: 2115 movs r1, #21
8001032: 2080 movs r0, #128 @ 0x80
8001034: f7ff ff58 bl 8000ee8 <AD5934_SetRegisterValue>
// Disable Internal Reset State
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, AD5934_CONTROL_FUNCTION(AD5934_RESERVED), 1);
8001038: 2201 movs r2, #1
800103a: 2180 movs r1, #128 @ 0x80
800103c: 2081 movs r0, #129 @ 0x81
800103e: f7ff ff53 bl 8000ee8 <AD5934_SetRegisterValue>
// Configure Range Output, PGA gain andPlace AD5934 in sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8001042: 2201 movs r2, #1
8001044: 2125 movs r1, #37 @ 0x25
8001046: 2080 movs r0, #128 @ 0x80
8001048: f7ff ff4e bl 8000ee8 <AD5934_SetRegisterValue>
}
800104c: bf00 nop
800104e: bd80 pop {r7, pc}
08001050 <AD5934_Repeat_Sweep>:
* @param None.
*
* @return none.
******************************************************************************/
void AD5934_Repeat_Sweep(void)
{
8001050: b580 push {r7, lr}
8001052: af00 add r7, sp, #0
// Repeat AD5934 Sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_REPEAT_FREQ) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8001054: 2201 movs r2, #1
8001056: 2145 movs r1, #69 @ 0x45
8001058: 2080 movs r0, #128 @ 0x80
800105a: f7ff ff45 bl 8000ee8 <AD5934_SetRegisterValue>
}
800105e: bf00 nop
8001060: bd80 pop {r7, pc}
08001062 <AD5934_StopSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_StopSweep(void)
{
8001062: b580 push {r7, lr}
8001064: af00 add r7, sp, #0
// Power Down
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
// Place AD5934 in standby (instead of power down to save startup time)
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8001066: 2201 movs r2, #1
8001068: 21b5 movs r1, #181 @ 0xb5
800106a: 2080 movs r0, #128 @ 0x80
800106c: f7ff ff3c bl 8000ee8 <AD5934_SetRegisterValue>
}
8001070: bf00 nop
8001072: bd80 pop {r7, pc}
08001074 <AD5934_Calculate_Temperature>:
* @param mag_dut - Magnitude of the device under test.
*
* @return Temperature in Celsius.
******************************************************************************/
float AD5934_Calculate_Temperature(float mag_ref, float mag_dut)
{
8001074: b580 push {r7, lr}
8001076: b08a sub sp, #40 @ 0x28
8001078: af00 add r7, sp, #0
800107a: 6078 str r0, [r7, #4]
800107c: 6039 str r1, [r7, #0]
uint8_t ch_ref;
float gain_factor, impedance_dut, temperature;
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
800107e: 2180 movs r1, #128 @ 0x80
8001080: 4832 ldr r0, [pc, #200] @ (800114c <AD5934_Calculate_Temperature+0xd8>)
8001082: f002 fd6b bl 8003b5c <HAL_GPIO_ReadPin>
8001086: 4603 mov r3, r0
8001088: 2b01 cmp r3, #1
800108a: d104 bne.n 8001096 <AD5934_Calculate_Temperature+0x22>
{
ch_ref = AD5934_CH_RTD_LOW_GAIN; //PT100
800108c: 2309 movs r3, #9
800108e: 77fb strb r3, [r7, #31]
gain_factor = AD5934_GAIN_FACTOR_100R;
8001090: 4b2f ldr r3, [pc, #188] @ (8001150 <AD5934_Calculate_Temperature+0xdc>)
8001092: 627b str r3, [r7, #36] @ 0x24
8001094: e003 b.n 800109e <AD5934_Calculate_Temperature+0x2a>
}
else
{
ch_ref = AD5934_CH_RTD_MID_GAIN; //PT1000
8001096: 230a movs r3, #10
8001098: 77fb strb r3, [r7, #31]
gain_factor = AD5934_GAIN_FACTOR_1K;
800109a: 4b2e ldr r3, [pc, #184] @ (8001154 <AD5934_Calculate_Temperature+0xe0>)
800109c: 627b str r3, [r7, #36] @ 0x24
}
float ratio_mag = mag_ref / mag_dut;
800109e: 6839 ldr r1, [r7, #0]
80010a0: 6878 ldr r0, [r7, #4]
80010a2: f7ff fdb3 bl 8000c0c <__aeabi_fdiv>
80010a6: 4603 mov r3, r0
80010a8: 61bb str r3, [r7, #24]
// This correction isn't validated
/*if(ch_ref==AD5934_CH_REF100R_LOW_GAIN) // only for PT100
impedance_dut = AD5934_Linear_Correction(gain_factor * ratio_mag);
else*/
impedance_dut = gain_factor * ratio_mag;
80010aa: 69b9 ldr r1, [r7, #24]
80010ac: 6a78 ldr r0, [r7, #36] @ 0x24
80010ae: f7ff fcf9 bl 8000aa4 <__aeabi_fmul>
80010b2: 4603 mov r3, r0
80010b4: 617b str r3, [r7, #20]
// Calculate impedance ratio with the Reference Resistor
float ratio = impedance_dut / gain_factor;
80010b6: 6a79 ldr r1, [r7, #36] @ 0x24
80010b8: 6978 ldr r0, [r7, #20]
80010ba: f7ff fda7 bl 8000c0c <__aeabi_fdiv>
80010be: 4603 mov r3, r0
80010c0: 613b str r3, [r7, #16]
// Calculate impedance discriminant with the ratio
float discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio));
80010c2: 6939 ldr r1, [r7, #16]
80010c4: f04f 507e mov.w r0, #1065353216 @ 0x3f800000
80010c8: f7ff fbe2 bl 8000890 <__aeabi_fsub>
80010cc: 4603 mov r3, r0
80010ce: 4922 ldr r1, [pc, #136] @ (8001158 <AD5934_Calculate_Temperature+0xe4>)
80010d0: 4618 mov r0, r3
80010d2: f7ff fce7 bl 8000aa4 <__aeabi_fmul>
80010d6: 4603 mov r3, r0
80010d8: 4920 ldr r1, [pc, #128] @ (800115c <AD5934_Calculate_Temperature+0xe8>)
80010da: 4618 mov r0, r3
80010dc: f7ff fbda bl 8000894 <__addsf3>
80010e0: 4603 mov r3, r0
80010e2: 60fb str r3, [r7, #12]
if (discriminant >= 0.0f && impedance_dut >= gain_factor)
80010e4: f04f 0100 mov.w r1, #0
80010e8: 68f8 ldr r0, [r7, #12]
80010ea: f7ff fe8d bl 8000e08 <__aeabi_fcmpge>
80010ee: 4603 mov r3, r0
80010f0: 2b00 cmp r3, #0
80010f2: d016 beq.n 8001122 <AD5934_Calculate_Temperature+0xae>
80010f4: 6a79 ldr r1, [r7, #36] @ 0x24
80010f6: 6978 ldr r0, [r7, #20]
80010f8: f7ff fe86 bl 8000e08 <__aeabi_fcmpge>
80010fc: 4603 mov r3, r0
80010fe: 2b00 cmp r3, #0
8001100: d00f beq.n 8001122 <AD5934_Calculate_Temperature+0xae>
{
// Ramo T >= 0°C: solução quadrática exata
temperature = (-AD5934_RTD_A + sqrtf(discriminant))/(2.0f * AD5934_RTD_B);
8001102: 68f8 ldr r0, [r7, #12]
8001104: f005 fca8 bl 8006a58 <sqrtf>
8001108: 4603 mov r3, r0
800110a: 4915 ldr r1, [pc, #84] @ (8001160 <AD5934_Calculate_Temperature+0xec>)
800110c: 4618 mov r0, r3
800110e: f7ff fbbf bl 8000890 <__aeabi_fsub>
8001112: 4603 mov r3, r0
8001114: 4913 ldr r1, [pc, #76] @ (8001164 <AD5934_Calculate_Temperature+0xf0>)
8001116: 4618 mov r0, r3
8001118: f7ff fd78 bl 8000c0c <__aeabi_fdiv>
800111c: 4603 mov r3, r0
800111e: 623b str r3, [r7, #32]
8001120: e00b b.n 800113a <AD5934_Calculate_Temperature+0xc6>
}
else
{
// Ramo T < 0°C (ou discriminante inválido por ruído): aproximação linear
temperature = (ratio - 1.0f) / AD5934_RTD_ALPHA;
8001122: f04f 517e mov.w r1, #1065353216 @ 0x3f800000
8001126: 6938 ldr r0, [r7, #16]
8001128: f7ff fbb2 bl 8000890 <__aeabi_fsub>
800112c: 4603 mov r3, r0
800112e: 490e ldr r1, [pc, #56] @ (8001168 <AD5934_Calculate_Temperature+0xf4>)
8001130: 4618 mov r0, r3
8001132: f7ff fd6b bl 8000c0c <__aeabi_fdiv>
8001136: 4603 mov r3, r0
8001138: 623b str r3, [r7, #32]
}
return AD5934_Round_Float_Precision(temperature,1);
800113a: 2101 movs r1, #1
800113c: 6a38 ldr r0, [r7, #32]
800113e: f000 f851 bl 80011e4 <AD5934_Round_Float_Precision>
8001142: 4603 mov r3, r0
}
8001144: 4618 mov r0, r3
8001146: 3728 adds r7, #40 @ 0x28
8001148: 46bd mov sp, r7
800114a: bd80 pop {r7, pc}
800114c: 40010800 .word 0x40010800
8001150: 42c80000 .word 0x42c80000
8001154: 447a0000 .word 0x447a0000
8001158: 361b057f .word 0x361b057f
800115c: 37802266 .word 0x37802266
8001160: 3b801132 .word 0x3b801132
8001164: b59b057f .word 0xb59b057f
8001168: 3b7c5048 .word 0x3b7c5048
0800116c <AD5934_EC_Compensate_Magnitude_To_25C>:
* @param temperature_dut The current temperature of the DUT (Device Under Test).
*
* @return The value of the Magnitude of the dut when it in 25C.
*/
float AD5934_EC_Compensate_Magnitude_To_25C(float mag_dut, float temperature_dut)
{
800116c: b580 push {r7, lr}
800116e: b084 sub sp, #16
8001170: af00 add r7, sp, #0
8001172: 6078 str r0, [r7, #4]
8001174: 6039 str r1, [r7, #0]
float factor = 1.0f + AD5934_EC_ALPHA_PER_C * (temperature_dut - AD5934_EC_TEMP_REF_C);
8001176: 4911 ldr r1, [pc, #68] @ (80011bc <AD5934_EC_Compensate_Magnitude_To_25C+0x50>)
8001178: 6838 ldr r0, [r7, #0]
800117a: f7ff fb89 bl 8000890 <__aeabi_fsub>
800117e: 4603 mov r3, r0
8001180: 490f ldr r1, [pc, #60] @ (80011c0 <AD5934_EC_Compensate_Magnitude_To_25C+0x54>)
8001182: 4618 mov r0, r3
8001184: f7ff fc8e bl 8000aa4 <__aeabi_fmul>
8001188: 4603 mov r3, r0
800118a: f04f 517e mov.w r1, #1065353216 @ 0x3f800000
800118e: 4618 mov r0, r3
8001190: f7ff fb80 bl 8000894 <__addsf3>
8001194: 4603 mov r3, r0
8001196: 60fb str r3, [r7, #12]
if (factor < 0.1f)
8001198: 490a ldr r1, [pc, #40] @ (80011c4 <AD5934_EC_Compensate_Magnitude_To_25C+0x58>)
800119a: 68f8 ldr r0, [r7, #12]
800119c: f7ff fe20 bl 8000de0 <__aeabi_fcmplt>
80011a0: 4603 mov r3, r0
80011a2: 2b00 cmp r3, #0
80011a4: d001 beq.n 80011aa <AD5934_EC_Compensate_Magnitude_To_25C+0x3e>
factor = 0.1f;
80011a6: 4b07 ldr r3, [pc, #28] @ (80011c4 <AD5934_EC_Compensate_Magnitude_To_25C+0x58>)
80011a8: 60fb str r3, [r7, #12]
return (mag_dut / factor);
80011aa: 68f9 ldr r1, [r7, #12]
80011ac: 6878 ldr r0, [r7, #4]
80011ae: f7ff fd2d bl 8000c0c <__aeabi_fdiv>
80011b2: 4603 mov r3, r0
}
80011b4: 4618 mov r0, r3
80011b6: 3710 adds r7, #16
80011b8: 46bd mov sp, r7
80011ba: bd80 pop {r7, pc}
80011bc: 41c80000 .word 0x41c80000
80011c0: 3ca3d70a .word 0x3ca3d70a
80011c4: 3dcccccd .word 0x3dcccccd
080011c8 <AD5934_Get_Real_Imag_Numbers>:
* @param: none
*
* @return Magnitude (int16).
******************************************************************************/
uint32_t AD5934_Get_Real_Imag_Numbers(void)
{
80011c8: b580 push {r7, lr}
80011ca: b082 sub sp, #8
80011cc: af00 add r7, sp, #0
uint32_t real_imag_reg = AD5934_GetRegisterValue(AD5934_IMG_REG_LB, 4); //AD5934_ReadRegister(AD5934_REAL_REG_LB, 4); //
80011ce: 2104 movs r1, #4
80011d0: 2097 movs r0, #151 @ 0x97
80011d2: f7ff febb bl 8000f4c <AD5934_GetRegisterValue>
80011d6: 6078 str r0, [r7, #4]
return (real_imag_reg);
80011d8: 687b ldr r3, [r7, #4]
}
80011da: 4618 mov r0, r3
80011dc: 3708 adds r7, #8
80011de: 46bd mov sp, r7
80011e0: bd80 pop {r7, pc}
...
080011e4 <AD5934_Round_Float_Precision>:
* @param valor O valor float original.
* @param casas_decimais Quantidade de casas que devem permanecer após a vírgula.
* @return float O valor com as casas decimais excedentes removidas.
*/
float AD5934_Round_Float_Precision(float value, uint8_t number_of_decimals)
{
80011e4: b580 push {r7, lr}
80011e6: b084 sub sp, #16
80011e8: af00 add r7, sp, #0
80011ea: 6078 str r0, [r7, #4]
80011ec: 460b mov r3, r1
80011ee: 70fb strb r3, [r7, #3]
float multiply = 1.0f;
80011f0: f04f 537e mov.w r3, #1065353216 @ 0x3f800000
80011f4: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
80011f6: 2300 movs r3, #0
80011f8: 72fb strb r3, [r7, #11]
80011fa: e008 b.n 800120e <AD5934_Round_Float_Precision+0x2a>
multiply *= 10.0f;
80011fc: 490f ldr r1, [pc, #60] @ (800123c <AD5934_Round_Float_Precision+0x58>)
80011fe: 68f8 ldr r0, [r7, #12]
8001200: f7ff fc50 bl 8000aa4 <__aeabi_fmul>
8001204: 4603 mov r3, r0
8001206: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
8001208: 7afb ldrb r3, [r7, #11]
800120a: 3301 adds r3, #1
800120c: 72fb strb r3, [r7, #11]
800120e: 7afa ldrb r2, [r7, #11]
8001210: 78fb ldrb r3, [r7, #3]
8001212: 429a cmp r2, r3
8001214: d3f2 bcc.n 80011fc <AD5934_Round_Float_Precision+0x18>
return roundf(value * multiply) / multiply;
8001216: 68f9 ldr r1, [r7, #12]
8001218: 6878 ldr r0, [r7, #4]
800121a: f7ff fc43 bl 8000aa4 <__aeabi_fmul>
800121e: 4603 mov r3, r0
8001220: 4618 mov r0, r3
8001222: f005 fca9 bl 8006b78 <roundf>
8001226: 4603 mov r3, r0
8001228: 68f9 ldr r1, [r7, #12]
800122a: 4618 mov r0, r3
800122c: f7ff fcee bl 8000c0c <__aeabi_fdiv>
8001230: 4603 mov r3, r0
}
8001232: 4618 mov r0, r3
8001234: 3710 adds r7, #16
8001236: 46bd mov sp, r7
8001238: bd80 pop {r7, pc}
800123a: bf00 nop
800123c: 41200000 .word 0x41200000
08001240 <AD5934_Process_System>:
* @param none
*
* @return none
*/
void AD5934_Process_System(void)
{
8001240: b5b0 push {r4, r5, r7, lr}
8001242: b084 sub sp, #16
8001244: af00 add r7, sp, #0
switch (ad5934_state)
8001246: 4b95 ldr r3, [pc, #596] @ (800149c <AD5934_Process_System+0x25c>)
8001248: 781b ldrb r3, [r3, #0]
800124a: b2db uxtb r3, r3
800124c: 2b06 cmp r3, #6
800124e: f200 8121 bhi.w 8001494 <AD5934_Process_System+0x254>
8001252: a201 add r2, pc, #4 @ (adr r2, 8001258 <AD5934_Process_System+0x18>)
8001254: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001258: 08001275 .word 0x08001275
800125c: 08001295 .word 0x08001295
8001260: 080012a3 .word 0x080012a3
8001264: 080012c3 .word 0x080012c3
8001268: 08001495 .word 0x08001495
800126c: 08001495 .word 0x08001495
8001270: 080013b3 .word 0x080013b3
{
case AD5934_IDLE:
ADG715_SetChannels(current_hw_mux_connection); // Starts changing the mux channel
8001274: 4b8a ldr r3, [pc, #552] @ (80014a0 <AD5934_Process_System+0x260>)
8001276: 781b ldrb r3, [r3, #0]
8001278: 4618 mov r0, r3
800127a: f000 fad3 bl 8001824 <ADG715_SetChannels>
is_new_channel = 1; // Forces first channel
800127e: 4b89 ldr r3, [pc, #548] @ (80014a4 <AD5934_Process_System+0x264>)
8001280: 2201 movs r2, #1
8001282: 701a strb r2, [r3, #0]
state_timer = g_ms_counter;
8001284: 4b88 ldr r3, [pc, #544] @ (80014a8 <AD5934_Process_System+0x268>)
8001286: 681b ldr r3, [r3, #0]
8001288: 4a88 ldr r2, [pc, #544] @ (80014ac <AD5934_Process_System+0x26c>)
800128a: 6013 str r3, [r2, #0]
ad5934_state = AD5934_WAIT_MUX;
800128c: 4b83 ldr r3, [pc, #524] @ (800149c <AD5934_Process_System+0x25c>)
800128e: 2201 movs r2, #1
8001290: 701a strb r2, [r3, #0]
break;
8001292: e0ff b.n 8001494 <AD5934_Process_System+0x254>
case AD5934_WAIT_MUX:
//if ((g_ms_counter - state_timer) >= AD5934_SYNC_MUX_SETTLING) // Wait until AD715 Mux switch stability
//{
HAL_Delay(15);
8001294: 200f movs r0, #15
8001296: f001 fee7 bl 8003068 <HAL_Delay>
ad5934_state = AD5934_START_CONVERSION;
800129a: 4b80 ldr r3, [pc, #512] @ (800149c <AD5934_Process_System+0x25c>)
800129c: 2202 movs r2, #2
800129e: 701a strb r2, [r3, #0]
//}
break;
80012a0: e0f8 b.n 8001494 <AD5934_Process_System+0x254>
case AD5934_START_CONVERSION:
//state_timer = g_ms_counter; // Starts to count the Burst period for the sweeps
/* DECISÃO DE COMANDO: Novo canal vs Leituras sucessivas */
if (is_new_channel) // Decision: Channel Switched or Next Sample in the Burst ?
80012a2: 4b80 ldr r3, [pc, #512] @ (80014a4 <AD5934_Process_System+0x264>)
80012a4: 781b ldrb r3, [r3, #0]
80012a6: 2b00 cmp r3, #0
80012a8: d005 beq.n 80012b6 <AD5934_Process_System+0x76>
{
AD5934_RestartSweep(); // Clean some AD5934 internal registers to Re-Start Sweep
80012aa: f7ff feb9 bl 8001020 <AD5934_RestartSweep>
is_new_channel = 0; // Resets the flag to read the next Sample Burst
80012ae: 4b7d ldr r3, [pc, #500] @ (80014a4 <AD5934_Process_System+0x264>)
80012b0: 2200 movs r2, #0
80012b2: 701a strb r2, [r3, #0]
80012b4: e001 b.n 80012ba <AD5934_Process_System+0x7a>
}
else
{
AD5934_Repeat_Sweep(); // Get Sample and just repeat reading
80012b6: f7ff fecb bl 8001050 <AD5934_Repeat_Sweep>
}
ad5934_state = AD5934_WAIT_CONVERSION; // Next State
80012ba: 4b78 ldr r3, [pc, #480] @ (800149c <AD5934_Process_System+0x25c>)
80012bc: 2203 movs r2, #3
80012be: 701a strb r2, [r3, #0]
break;
80012c0: e0e8 b.n 8001494 <AD5934_Process_System+0x254>
case AD5934_WAIT_CONVERSION:
uint8_t status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1); // Check if the current converion is ready in the AD5934
80012c2: 2101 movs r1, #1
80012c4: 208f movs r0, #143 @ 0x8f
80012c6: f7ff fe41 bl 8000f4c <AD5934_GetRegisterValue>
80012ca: 4603 mov r3, r0
80012cc: 73fb strb r3, [r7, #15]
if ((status & AD5934_STATUS_DATA_VALID) != 0)
80012ce: 7bfb ldrb r3, [r7, #15]
80012d0: f003 0302 and.w r3, r3, #2
80012d4: 2b00 cmp r3, #0
80012d6: f000 80dc beq.w 8001492 <AD5934_Process_System+0x252>
{
uint32_t magnitude_int = AD5934_Get_Real_Imag_Numbers();
80012da: f7ff ff75 bl 80011c8 <AD5934_Get_Real_Imag_Numbers>
80012de: 60b8 str r0, [r7, #8]
int16_t mag_real = (int16_t)(magnitude_int>>16);
80012e0: 68bb ldr r3, [r7, #8]
80012e2: 0c1b lsrs r3, r3, #16
80012e4: 80fb strh r3, [r7, #6]
int16_t mag_imag = (int16_t)(magnitude_int & 0x0000FFFF);
80012e6: 68bb ldr r3, [r7, #8]
80012e8: 80bb strh r3, [r7, #4]
float mag_float = sqrtf(((float)mag_real * (float)mag_real) + ((float)mag_imag * (float)mag_imag));
80012ea: f9b7 3006 ldrsh.w r3, [r7, #6]
80012ee: 4618 mov r0, r3
80012f0: f7ff fb84 bl 80009fc <__aeabi_i2f>
80012f4: 4604 mov r4, r0
80012f6: f9b7 3006 ldrsh.w r3, [r7, #6]
80012fa: 4618 mov r0, r3
80012fc: f7ff fb7e bl 80009fc <__aeabi_i2f>
8001300: 4603 mov r3, r0
8001302: 4619 mov r1, r3
8001304: 4620 mov r0, r4
8001306: f7ff fbcd bl 8000aa4 <__aeabi_fmul>
800130a: 4603 mov r3, r0
800130c: 461d mov r5, r3
800130e: f9b7 3004 ldrsh.w r3, [r7, #4]
8001312: 4618 mov r0, r3
8001314: f7ff fb72 bl 80009fc <__aeabi_i2f>
8001318: 4604 mov r4, r0
800131a: f9b7 3004 ldrsh.w r3, [r7, #4]
800131e: 4618 mov r0, r3
8001320: f7ff fb6c bl 80009fc <__aeabi_i2f>
8001324: 4603 mov r3, r0
8001326: 4619 mov r1, r3
8001328: 4620 mov r0, r4
800132a: f7ff fbbb bl 8000aa4 <__aeabi_fmul>
800132e: 4603 mov r3, r0
8001330: 4619 mov r1, r3
8001332: 4628 mov r0, r5
8001334: f7ff faae bl 8000894 <__addsf3>
8001338: 4603 mov r3, r0
800133a: 4618 mov r0, r3
800133c: f005 fb8c bl 8006a58 <sqrtf>
8001340: 6038 str r0, [r7, #0]
switch (current_mux_channel)
8001342: 4b5b ldr r3, [pc, #364] @ (80014b0 <AD5934_Process_System+0x270>)
8001344: 781b ldrb r3, [r3, #0]
8001346: 2b02 cmp r3, #2
8001348: d01e beq.n 8001388 <AD5934_Process_System+0x148>
800134a: 2b02 cmp r3, #2
800134c: dc2a bgt.n 80013a4 <AD5934_Process_System+0x164>
800134e: 2b00 cmp r3, #0
8001350: d002 beq.n 8001358 <AD5934_Process_System+0x118>
8001352: 2b01 cmp r3, #1
8001354: d00e beq.n 8001374 <AD5934_Process_System+0x134>
8001356: e025 b.n 80013a4 <AD5934_Process_System+0x164>
{
case AD5934_ID_RTD:
AD5934_RTD_NewSample(mag_float);
8001358: 6838 ldr r0, [r7, #0]
800135a: f000 fa19 bl 8001790 <AD5934_RTD_NewSample>
rtd_now = mag_float;
800135e: 6838 ldr r0, [r7, #0]
8001360: f7ff fd7c bl 8000e5c <__aeabi_f2iz>
8001364: 4603 mov r3, r0
8001366: b21a sxth r2, r3
8001368: 4b52 ldr r3, [pc, #328] @ (80014b4 <AD5934_Process_System+0x274>)
800136a: 801a strh r2, [r3, #0]
rtd_now_i = mag_imag;
800136c: 4a52 ldr r2, [pc, #328] @ (80014b8 <AD5934_Process_System+0x278>)
800136e: 88bb ldrh r3, [r7, #4]
8001370: 8013 strh r3, [r2, #0]
break;
8001372: e017 b.n 80013a4 <AD5934_Process_System+0x164>
case AD5934_ID_EC:
AD5934_EC_NewSample(mag_float);
8001374: 6838 ldr r0, [r7, #0]
8001376: f000 fa19 bl 80017ac <AD5934_EC_NewSample>
ec_now = mag_real;
800137a: 4a50 ldr r2, [pc, #320] @ (80014bc <AD5934_Process_System+0x27c>)
800137c: 88fb ldrh r3, [r7, #6]
800137e: 8013 strh r3, [r2, #0]
ec_now_i = mag_imag;
8001380: 4a4f ldr r2, [pc, #316] @ (80014c0 <AD5934_Process_System+0x280>)
8001382: 88bb ldrh r3, [r7, #4]
8001384: 8013 strh r3, [r2, #0]
break;
8001386: e00d b.n 80013a4 <AD5934_Process_System+0x164>
case AD5934_ID_REF:
AD5934_Reference_NewSample(mag_float);
8001388: 6838 ldr r0, [r7, #0]
800138a: f000 fa1d bl 80017c8 <AD5934_Reference_NewSample>
ref_now = mag_float;
800138e: 6838 ldr r0, [r7, #0]
8001390: f7ff fd64 bl 8000e5c <__aeabi_f2iz>
8001394: 4603 mov r3, r0
8001396: b21a sxth r2, r3
8001398: 4b4a ldr r3, [pc, #296] @ (80014c4 <AD5934_Process_System+0x284>)
800139a: 801a strh r2, [r3, #0]
ref_now_i = mag_imag;
800139c: 4a4a ldr r2, [pc, #296] @ (80014c8 <AD5934_Process_System+0x288>)
800139e: 88bb ldrh r3, [r7, #4]
80013a0: 8013 strh r3, [r2, #0]
break;
80013a2: bf00 nop
sweep_count++;
ad5934_state = AD5934_START_CONVERSION;
}
else
{
sweep_count = 0;
80013a4: 4b49 ldr r3, [pc, #292] @ (80014cc <AD5934_Process_System+0x28c>)
80013a6: 2200 movs r2, #0
80013a8: 701a strb r2, [r3, #0]
ad5934_state = AD5934_SWITCH_MUX;
80013aa: 4b3c ldr r3, [pc, #240] @ (800149c <AD5934_Process_System+0x25c>)
80013ac: 2206 movs r2, #6
80013ae: 701a strb r2, [r3, #0]
}
}
break;
80013b0: e06f b.n 8001492 <AD5934_Process_System+0x252>
case AD5934_SWITCH_MUX:
AD5934_StopSweep(); // Put AD5934 in Standby
80013b2: f7ff fe56 bl 8001062 <AD5934_StopSweep>
current_mux_channel = (uint8_t)((current_mux_channel + 1) % 3); // Pointer to the next channel (Circular Buffer 0 to 2)
80013b6: 4b3e ldr r3, [pc, #248] @ (80014b0 <AD5934_Process_System+0x270>)
80013b8: 781b ldrb r3, [r3, #0]
80013ba: 1c5a adds r2, r3, #1
80013bc: 4b44 ldr r3, [pc, #272] @ (80014d0 <AD5934_Process_System+0x290>)
80013be: fb83 3102 smull r3, r1, r3, r2
80013c2: 17d3 asrs r3, r2, #31
80013c4: 1ac9 subs r1, r1, r3
80013c6: 460b mov r3, r1
80013c8: 005b lsls r3, r3, #1
80013ca: 440b add r3, r1
80013cc: 1ad1 subs r1, r2, r3
80013ce: b2ca uxtb r2, r1
80013d0: 4b37 ldr r3, [pc, #220] @ (80014b0 <AD5934_Process_System+0x270>)
80013d2: 701a strb r2, [r3, #0]
switch (current_mux_channel)
80013d4: 4b36 ldr r3, [pc, #216] @ (80014b0 <AD5934_Process_System+0x270>)
80013d6: 781b ldrb r3, [r3, #0]
80013d8: 2b02 cmp r3, #2
80013da: d034 beq.n 8001446 <AD5934_Process_System+0x206>
80013dc: 2b02 cmp r3, #2
80013de: dc49 bgt.n 8001474 <AD5934_Process_System+0x234>
80013e0: 2b00 cmp r3, #0
80013e2: d002 beq.n 80013ea <AD5934_Process_System+0x1aa>
80013e4: 2b01 cmp r3, #1
80013e6: d017 beq.n 8001418 <AD5934_Process_System+0x1d8>
80013e8: e044 b.n 8001474 <AD5934_Process_System+0x234>
{
case AD5934_ID_RTD:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
80013ea: 2180 movs r1, #128 @ 0x80
80013ec: 4839 ldr r0, [pc, #228] @ (80014d4 <AD5934_Process_System+0x294>)
80013ee: f002 fbb5 bl 8003b5c <HAL_GPIO_ReadPin>
80013f2: 4603 mov r3, r0
80013f4: 2b01 cmp r3, #1
80013f6: d107 bne.n 8001408 <AD5934_Process_System+0x1c8>
current_rtd_mux = current_hw_mux_connection = AD5934_CH_RTD_LOW_GAIN; //PT100
80013f8: 4b29 ldr r3, [pc, #164] @ (80014a0 <AD5934_Process_System+0x260>)
80013fa: 2209 movs r2, #9
80013fc: 701a strb r2, [r3, #0]
80013fe: 4b28 ldr r3, [pc, #160] @ (80014a0 <AD5934_Process_System+0x260>)
8001400: 781a ldrb r2, [r3, #0]
8001402: 4b35 ldr r3, [pc, #212] @ (80014d8 <AD5934_Process_System+0x298>)
8001404: 701a strb r2, [r3, #0]
else
current_rtd_mux = current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
break;
8001406: e035 b.n 8001474 <AD5934_Process_System+0x234>
current_rtd_mux = current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
8001408: 4b25 ldr r3, [pc, #148] @ (80014a0 <AD5934_Process_System+0x260>)
800140a: 220a movs r2, #10
800140c: 701a strb r2, [r3, #0]
800140e: 4b24 ldr r3, [pc, #144] @ (80014a0 <AD5934_Process_System+0x260>)
8001410: 781a ldrb r2, [r3, #0]
8001412: 4b31 ldr r3, [pc, #196] @ (80014d8 <AD5934_Process_System+0x298>)
8001414: 701a strb r2, [r3, #0]
break;
8001416: e02d b.n 8001474 <AD5934_Process_System+0x234>
case AD5934_ID_EC:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // Hardware Setup: Gain Selection (PA6)
8001418: 2140 movs r1, #64 @ 0x40
800141a: 482e ldr r0, [pc, #184] @ (80014d4 <AD5934_Process_System+0x294>)
800141c: f002 fb9e bl 8003b5c <HAL_GPIO_ReadPin>
8001420: 4603 mov r3, r0
8001422: 2b01 cmp r3, #1
8001424: d107 bne.n 8001436 <AD5934_Process_System+0x1f6>
current_ec_mux = current_hw_mux_connection = AD5934_CH_EC_HIGH_GAIN;
8001426: 4b1e ldr r3, [pc, #120] @ (80014a0 <AD5934_Process_System+0x260>)
8001428: 220e movs r2, #14
800142a: 701a strb r2, [r3, #0]
800142c: 4b1c ldr r3, [pc, #112] @ (80014a0 <AD5934_Process_System+0x260>)
800142e: 781a ldrb r2, [r3, #0]
8001430: 4b2a ldr r3, [pc, #168] @ (80014dc <AD5934_Process_System+0x29c>)
8001432: 701a strb r2, [r3, #0]
else
current_ec_mux = current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
break;
8001434: e01e b.n 8001474 <AD5934_Process_System+0x234>
current_ec_mux = current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
8001436: 4b1a ldr r3, [pc, #104] @ (80014a0 <AD5934_Process_System+0x260>)
8001438: 220d movs r2, #13
800143a: 701a strb r2, [r3, #0]
800143c: 4b18 ldr r3, [pc, #96] @ (80014a0 <AD5934_Process_System+0x260>)
800143e: 781a ldrb r2, [r3, #0]
8001440: 4b26 ldr r3, [pc, #152] @ (80014dc <AD5934_Process_System+0x29c>)
8001442: 701a strb r2, [r3, #0]
break;
8001444: e016 b.n 8001474 <AD5934_Process_System+0x234>
case AD5934_ID_REF:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
8001446: 2180 movs r1, #128 @ 0x80
8001448: 4822 ldr r0, [pc, #136] @ (80014d4 <AD5934_Process_System+0x294>)
800144a: f002 fb87 bl 8003b5c <HAL_GPIO_ReadPin>
800144e: 4603 mov r3, r0
8001450: 2b01 cmp r3, #1
8001452: d107 bne.n 8001464 <AD5934_Process_System+0x224>
current_ref_mux = current_hw_mux_connection = AD5934_CH_REF100R_LOW_GAIN; // 100 Ohms Reference Resistor
8001454: 4b12 ldr r3, [pc, #72] @ (80014a0 <AD5934_Process_System+0x260>)
8001456: 2200 movs r2, #0
8001458: 701a strb r2, [r3, #0]
800145a: 4b11 ldr r3, [pc, #68] @ (80014a0 <AD5934_Process_System+0x260>)
800145c: 781a ldrb r2, [r3, #0]
800145e: 4b20 ldr r3, [pc, #128] @ (80014e0 <AD5934_Process_System+0x2a0>)
8001460: 701a strb r2, [r3, #0]
else
current_ref_mux = current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
break;
8001462: e006 b.n 8001472 <AD5934_Process_System+0x232>
current_ref_mux = current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
8001464: 4b0e ldr r3, [pc, #56] @ (80014a0 <AD5934_Process_System+0x260>)
8001466: 2204 movs r2, #4
8001468: 701a strb r2, [r3, #0]
800146a: 4b0d ldr r3, [pc, #52] @ (80014a0 <AD5934_Process_System+0x260>)
800146c: 781a ldrb r2, [r3, #0]
800146e: 4b1c ldr r3, [pc, #112] @ (80014e0 <AD5934_Process_System+0x2a0>)
8001470: 701a strb r2, [r3, #0]
break;
8001472: bf00 nop
}
ADG715_SetChannels(current_hw_mux_connection); // Change the analog mux
8001474: 4b0a ldr r3, [pc, #40] @ (80014a0 <AD5934_Process_System+0x260>)
8001476: 781b ldrb r3, [r3, #0]
8001478: 4618 mov r0, r3
800147a: f000 f9d3 bl 8001824 <ADG715_SetChannels>
HAL_Delay(12);
800147e: 200c movs r0, #12
8001480: f001 fdf2 bl 8003068 <HAL_Delay>
is_new_channel = 1; // Channel Switched
8001484: 4b07 ldr r3, [pc, #28] @ (80014a4 <AD5934_Process_System+0x264>)
8001486: 2201 movs r2, #1
8001488: 701a strb r2, [r3, #0]
//state_timer = g_ms_counter; // Reload timer to wait for stability
//ad5934_state = AD5934_WAIT_MUX; // Next State
ad5934_state = AD5934_START_CONVERSION;
800148a: 4b04 ldr r3, [pc, #16] @ (800149c <AD5934_Process_System+0x25c>)
800148c: 2202 movs r2, #2
800148e: 701a strb r2, [r3, #0]
break;
8001490: e000 b.n 8001494 <AD5934_Process_System+0x254>
break;
8001492: bf00 nop
}
}
8001494: bf00 nop
8001496: 3710 adds r7, #16
8001498: 46bd mov sp, r7
800149a: bdb0 pop {r4, r5, r7, pc}
800149c: 2000007c .word 0x2000007c
80014a0: 20000091 .word 0x20000091
80014a4: 20000002 .word 0x20000002
80014a8: 20000084 .word 0x20000084
80014ac: 20000080 .word 0x20000080
80014b0: 20000090 .word 0x20000090
80014b4: 20000148 .word 0x20000148
80014b8: 2000014e .word 0x2000014e
80014bc: 2000014c .word 0x2000014c
80014c0: 20000152 .word 0x20000152
80014c4: 2000014a .word 0x2000014a
80014c8: 20000150 .word 0x20000150
80014cc: 20000093 .word 0x20000093
80014d0: 55555556 .word 0x55555556
80014d4: 40010800 .word 0x40010800
80014d8: 20000001 .word 0x20000001
80014dc: 20000000 .word 0x20000000
80014e0: 20000092 .word 0x20000092
080014e4 <AD5934_Sort_Array>:
/**
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
* and it avoids depending on qsort/heap allocation.
**/
void AD5934_Sort_Array(float *v, uint8_t n)
{
80014e4: b580 push {r7, lr}
80014e6: b084 sub sp, #16
80014e8: af00 add r7, sp, #0
80014ea: 6078 str r0, [r7, #4]
80014ec: 460b mov r3, r1
80014ee: 70fb strb r3, [r7, #3]
for (uint8_t i = 1; i < n; i++)
80014f0: 2301 movs r3, #1
80014f2: 73fb strb r3, [r7, #15]
80014f4: e039 b.n 800156a <AD5934_Sort_Array+0x86>
{
float key = v[i];
80014f6: 7bfb ldrb r3, [r7, #15]
80014f8: 009b lsls r3, r3, #2
80014fa: 687a ldr r2, [r7, #4]
80014fc: 4413 add r3, r2
80014fe: 681b ldr r3, [r3, #0]
8001500: 60bb str r3, [r7, #8]
int8_t j = (int8_t)i - 1;
8001502: 7bfb ldrb r3, [r7, #15]
8001504: 3b01 subs r3, #1
8001506: b2db uxtb r3, r3
8001508: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
800150a: e012 b.n 8001532 <AD5934_Sort_Array+0x4e>
{
v[j + 1] = v[j];
800150c: f997 300e ldrsb.w r3, [r7, #14]
8001510: 009b lsls r3, r3, #2
8001512: 687a ldr r2, [r7, #4]
8001514: 441a add r2, r3
8001516: f997 300e ldrsb.w r3, [r7, #14]
800151a: 3301 adds r3, #1
800151c: 009b lsls r3, r3, #2
800151e: 6879 ldr r1, [r7, #4]
8001520: 440b add r3, r1
8001522: 6812 ldr r2, [r2, #0]
8001524: 601a str r2, [r3, #0]
j--;
8001526: f997 300e ldrsb.w r3, [r7, #14]
800152a: b2db uxtb r3, r3
800152c: 3b01 subs r3, #1
800152e: b2db uxtb r3, r3
8001530: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
8001532: f997 300e ldrsb.w r3, [r7, #14]
8001536: 2b00 cmp r3, #0
8001538: db0c blt.n 8001554 <AD5934_Sort_Array+0x70>
800153a: f997 300e ldrsb.w r3, [r7, #14]
800153e: 009b lsls r3, r3, #2
8001540: 687a ldr r2, [r7, #4]
8001542: 4413 add r3, r2
8001544: 681b ldr r3, [r3, #0]
8001546: 4619 mov r1, r3
8001548: 68b8 ldr r0, [r7, #8]
800154a: f7ff fc49 bl 8000de0 <__aeabi_fcmplt>
800154e: 4603 mov r3, r0
8001550: 2b00 cmp r3, #0
8001552: d1db bne.n 800150c <AD5934_Sort_Array+0x28>
}
v[j + 1] = key;
8001554: f997 300e ldrsb.w r3, [r7, #14]
8001558: 3301 adds r3, #1
800155a: 009b lsls r3, r3, #2
800155c: 687a ldr r2, [r7, #4]
800155e: 4413 add r3, r2
8001560: 68ba ldr r2, [r7, #8]
8001562: 601a str r2, [r3, #0]
for (uint8_t i = 1; i < n; i++)
8001564: 7bfb ldrb r3, [r7, #15]
8001566: 3301 adds r3, #1
8001568: 73fb strb r3, [r7, #15]
800156a: 7bfa ldrb r2, [r7, #15]
800156c: 78fb ldrb r3, [r7, #3]
800156e: 429a cmp r2, r3
8001570: d3c1 bcc.n 80014f6 <AD5934_Sort_Array+0x12>
}
}
8001572: bf00 nop
8001574: bf00 nop
8001576: 3710 adds r7, #16
8001578: 46bd mov sp, r7
800157a: bd80 pop {r7, pc}
0800157c <AD5934_Trimmed_Mean>:
* original order is not needed), discards TRIM_COUNT values from each
* end, and averages the remainder. Sorting in place avoids a temporary
* array and removes the need for memcpy()/string.h entirely.
**/
float AD5934_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
{
800157c: b580 push {r7, lr}
800157e: b086 sub sp, #24
8001580: af00 add r7, sp, #0
8001582: 6078 str r0, [r7, #4]
8001584: 460b mov r3, r1
8001586: 70fb strb r3, [r7, #3]
8001588: 4613 mov r3, r2
800158a: 70bb strb r3, [r7, #2]
AD5934_Sort_Array(buffer, n);
800158c: 78fb ldrb r3, [r7, #3]
800158e: 4619 mov r1, r3
8001590: 6878 ldr r0, [r7, #4]
8001592: f7ff ffa7 bl 80014e4 <AD5934_Sort_Array>
uint8_t start = trim;
8001596: 78bb ldrb r3, [r7, #2]
8001598: 75fb strb r3, [r7, #23]
uint8_t end = n - trim; /* exclusive */
800159a: 78fa ldrb r2, [r7, #3]
800159c: 78bb ldrb r3, [r7, #2]
800159e: 1ad3 subs r3, r2, r3
80015a0: 75bb strb r3, [r7, #22]
if (end <= start) /* guard against a misconfigured trim value */
80015a2: 7dba ldrb r2, [r7, #22]
80015a4: 7dfb ldrb r3, [r7, #23]
80015a6: 429a cmp r2, r3
80015a8: d803 bhi.n 80015b2 <AD5934_Trimmed_Mean+0x36>
{
start = 0;
80015aa: 2300 movs r3, #0
80015ac: 75fb strb r3, [r7, #23]
end = n;
80015ae: 78fb ldrb r3, [r7, #3]
80015b0: 75bb strb r3, [r7, #22]
}
float sum = 0.0f;
80015b2: f04f 0300 mov.w r3, #0
80015b6: 613b str r3, [r7, #16]
uint8_t count = 0;
80015b8: 2300 movs r3, #0
80015ba: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
80015bc: 7dfb ldrb r3, [r7, #23]
80015be: 73bb strb r3, [r7, #14]
80015c0: e010 b.n 80015e4 <AD5934_Trimmed_Mean+0x68>
{
sum += buffer[i];
80015c2: 7bbb ldrb r3, [r7, #14]
80015c4: 009b lsls r3, r3, #2
80015c6: 687a ldr r2, [r7, #4]
80015c8: 4413 add r3, r2
80015ca: 681b ldr r3, [r3, #0]
80015cc: 4619 mov r1, r3
80015ce: 6938 ldr r0, [r7, #16]
80015d0: f7ff f960 bl 8000894 <__addsf3>
80015d4: 4603 mov r3, r0
80015d6: 613b str r3, [r7, #16]
count++;
80015d8: 7bfb ldrb r3, [r7, #15]
80015da: 3301 adds r3, #1
80015dc: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
80015de: 7bbb ldrb r3, [r7, #14]
80015e0: 3301 adds r3, #1
80015e2: 73bb strb r3, [r7, #14]
80015e4: 7bba ldrb r2, [r7, #14]
80015e6: 7dbb ldrb r3, [r7, #22]
80015e8: 429a cmp r2, r3
80015ea: d3ea bcc.n 80015c2 <AD5934_Trimmed_Mean+0x46>
}
return sum / (float)count;
80015ec: 7bfb ldrb r3, [r7, #15]
80015ee: 4618 mov r0, r3
80015f0: f7ff fa00 bl 80009f4 <__aeabi_ui2f>
80015f4: 4603 mov r3, r0
80015f6: 4619 mov r1, r3
80015f8: 6938 ldr r0, [r7, #16]
80015fa: f7ff fb07 bl 8000c0c <__aeabi_fdiv>
80015fe: 4603 mov r3, r0
}
8001600: 4618 mov r0, r3
8001602: 3718 adds r7, #24
8001604: 46bd mov sp, r7
8001606: bd80 pop {r7, pc}
08001608 <AD5934_History_Average>:
/*
* Simple average of the history buffer (stage-2 sliding window)
*/
float AD5934_History_Average(const float *hist, uint8_t n)
{
8001608: b580 push {r7, lr}
800160a: b084 sub sp, #16
800160c: af00 add r7, sp, #0
800160e: 6078 str r0, [r7, #4]
8001610: 460b mov r3, r1
8001612: 70fb strb r3, [r7, #3]
float sum = 0.0f;
8001614: f04f 0300 mov.w r3, #0
8001618: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
800161a: 2300 movs r3, #0
800161c: 72fb strb r3, [r7, #11]
800161e: e00d b.n 800163c <AD5934_History_Average+0x34>
sum += hist[i];
8001620: 7afb ldrb r3, [r7, #11]
8001622: 009b lsls r3, r3, #2
8001624: 687a ldr r2, [r7, #4]
8001626: 4413 add r3, r2
8001628: 681b ldr r3, [r3, #0]
800162a: 4619 mov r1, r3
800162c: 68f8 ldr r0, [r7, #12]
800162e: f7ff f931 bl 8000894 <__addsf3>
8001632: 4603 mov r3, r0
8001634: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
8001636: 7afb ldrb r3, [r7, #11]
8001638: 3301 adds r3, #1
800163a: 72fb strb r3, [r7, #11]
800163c: 7afa ldrb r2, [r7, #11]
800163e: 78fb ldrb r3, [r7, #3]
8001640: 429a cmp r2, r3
8001642: d3ed bcc.n 8001620 <AD5934_History_Average+0x18>
return sum / (float)n;
8001644: 78fb ldrb r3, [r7, #3]
8001646: 4618 mov r0, r3
8001648: f7ff f9d4 bl 80009f4 <__aeabi_ui2f>
800164c: 4603 mov r3, r0
800164e: 4619 mov r1, r3
8001650: 68f8 ldr r0, [r7, #12]
8001652: f7ff fadb bl 8000c0c <__aeabi_fdiv>
8001656: 4603 mov r3, r0
}
8001658: 4618 mov r0, r3
800165a: 3710 adds r7, #16
800165c: 46bd mov sp, r7
800165e: bd80 pop {r7, pc}
08001660 <AD5934_Process_Sample>:
* Common processing core: applied identically to all 3 channels.
* Receives the current raw reading and the channel's state (global
* arrays/struct).
**/
void AD5934_Process_Sample(AD5934_filter_t *ch, float raw)
{
8001660: b590 push {r4, r7, lr}
8001662: b085 sub sp, #20
8001664: af00 add r7, sp, #0
8001666: 6078 str r0, [r7, #4]
8001668: 6039 str r1, [r7, #0]
/* --- Stage 1: accumulate into the current burst --- */
ch->burst[ch->burst_index] = raw;
800166a: 687b ldr r3, [r7, #4]
800166c: 791b ldrb r3, [r3, #4]
800166e: 4619 mov r1, r3
8001670: 687b ldr r3, [r7, #4]
8001672: 683a ldr r2, [r7, #0]
8001674: f843 2021 str.w r2, [r3, r1, lsl #2]
ch->burst_index++;
8001678: 687b ldr r3, [r7, #4]
800167a: 791b ldrb r3, [r3, #4]
800167c: 3301 adds r3, #1
800167e: b2da uxtb r2, r3
8001680: 687b ldr r3, [r7, #4]
8001682: 711a strb r2, [r3, #4]
if (ch->burst_index < AD5934_BURST_SIZE)
8001684: 687b ldr r3, [r7, #4]
8001686: 791b ldrb r3, [r3, #4]
8001688: 2b00 cmp r3, #0
800168a: d075 beq.n 8001778 <AD5934_Process_Sample+0x118>
return; /* still collecting the burst, nothing else to do */
/* Burst complete: compute the trimmed mean */
float burst_result = AD5934_Trimmed_Mean(ch->burst, AD5934_BURST_SIZE, AD5934_TRIM_COUNT);
800168c: 687b ldr r3, [r7, #4]
800168e: 2200 movs r2, #0
8001690: 2101 movs r1, #1
8001692: 4618 mov r0, r3
8001694: f7ff ff72 bl 800157c <AD5934_Trimmed_Mean>
8001698: 60f8 str r0, [r7, #12]
ch->burst_index = 0; /* reset for the next burst */
800169a: 687b ldr r3, [r7, #4]
800169c: 2200 movs r2, #0
800169e: 711a strb r2, [r3, #4]
/* --- Stage 2a: rolling history / sliding window --- */
ch->history[ch->history_index] = burst_result;
80016a0: 687b ldr r3, [r7, #4]
80016a2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
80016a6: 461a mov r2, r3
80016a8: 687b ldr r3, [r7, #4]
80016aa: 3202 adds r2, #2
80016ac: 68f9 ldr r1, [r7, #12]
80016ae: f843 1022 str.w r1, [r3, r2, lsl #2]
ch->history_index = (uint8_t)((ch->history_index + 1) % AD5934_HISTORY_SIZE);
80016b2: 687b ldr r3, [r7, #4]
80016b4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
80016b8: 3301 adds r3, #1
80016ba: 425a negs r2, r3
80016bc: f003 0307 and.w r3, r3, #7
80016c0: f002 0207 and.w r2, r2, #7
80016c4: bf58 it pl
80016c6: 4253 negpl r3, r2
80016c8: b2da uxtb r2, r3
80016ca: 687b ldr r3, [r7, #4]
80016cc: f883 2028 strb.w r2, [r3, #40] @ 0x28
if (ch->history_count < AD5934_HISTORY_SIZE)
80016d0: 687b ldr r3, [r7, #4]
80016d2: f893 3029 ldrb.w r3, [r3, #41] @ 0x29
80016d6: 2b07 cmp r3, #7
80016d8: d807 bhi.n 80016ea <AD5934_Process_Sample+0x8a>
ch->history_count++;
80016da: 687b ldr r3, [r7, #4]
80016dc: f893 3029 ldrb.w r3, [r3, #41] @ 0x29
80016e0: 3301 adds r3, #1
80016e2: b2da uxtb r2, r3
80016e4: 687b ldr r3, [r7, #4]
80016e6: f883 2029 strb.w r2, [r3, #41] @ 0x29
float window_average = AD5934_History_Average(ch->history, ch->history_count);
80016ea: 687b ldr r3, [r7, #4]
80016ec: f103 0208 add.w r2, r3, #8
80016f0: 687b ldr r3, [r7, #4]
80016f2: f893 3029 ldrb.w r3, [r3, #41] @ 0x29
80016f6: 4619 mov r1, r3
80016f8: 4610 mov r0, r2
80016fa: f7ff ff85 bl 8001608 <AD5934_History_Average>
80016fe: 60b8 str r0, [r7, #8]
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
if (!ch->iir_initialized)
8001700: 687b ldr r3, [r7, #4]
8001702: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
8001706: 2b00 cmp r3, #0
8001708: d107 bne.n 800171a <AD5934_Process_Sample+0xba>
{
ch->iir_state = burst_result;
800170a: 687b ldr r3, [r7, #4]
800170c: 68fa ldr r2, [r7, #12]
800170e: 62da str r2, [r3, #44] @ 0x2c
ch->iir_initialized = 1;
8001710: 687b ldr r3, [r7, #4]
8001712: 2201 movs r2, #1
8001714: f883 2030 strb.w r2, [r3, #48] @ 0x30
8001718: e014 b.n 8001744 <AD5934_Process_Sample+0xe4>
}
else
{
ch->iir_state = AD5934_IIR_ALPHA * burst_result + (1.0f - AD5934_IIR_ALPHA) * ch->iir_state;
800171a: 4919 ldr r1, [pc, #100] @ (8001780 <AD5934_Process_Sample+0x120>)
800171c: 68f8 ldr r0, [r7, #12]
800171e: f7ff f9c1 bl 8000aa4 <__aeabi_fmul>
8001722: 4603 mov r3, r0
8001724: 461c mov r4, r3
8001726: 687b ldr r3, [r7, #4]
8001728: 6adb ldr r3, [r3, #44] @ 0x2c
800172a: 4916 ldr r1, [pc, #88] @ (8001784 <AD5934_Process_Sample+0x124>)
800172c: 4618 mov r0, r3
800172e: f7ff f9b9 bl 8000aa4 <__aeabi_fmul>
8001732: 4603 mov r3, r0
8001734: 4619 mov r1, r3
8001736: 4620 mov r0, r4
8001738: f7ff f8ac bl 8000894 <__addsf3>
800173c: 4603 mov r3, r0
800173e: 461a mov r2, r3
8001740: 687b ldr r3, [r7, #4]
8001742: 62da str r2, [r3, #44] @ 0x2c
}
/* Final output: combines the IIR state (fast response to real drift)
* with the window average (more stable, slower response). Adjust
* the weighting per channel if needed. */
ch->filtered_value = 0.65f * ch->iir_state + 0.35f * window_average;
8001744: 687b ldr r3, [r7, #4]
8001746: 6adb ldr r3, [r3, #44] @ 0x2c
8001748: 490f ldr r1, [pc, #60] @ (8001788 <AD5934_Process_Sample+0x128>)
800174a: 4618 mov r0, r3
800174c: f7ff f9aa bl 8000aa4 <__aeabi_fmul>
8001750: 4603 mov r3, r0
8001752: 461c mov r4, r3
8001754: 490d ldr r1, [pc, #52] @ (800178c <AD5934_Process_Sample+0x12c>)
8001756: 68b8 ldr r0, [r7, #8]
8001758: f7ff f9a4 bl 8000aa4 <__aeabi_fmul>
800175c: 4603 mov r3, r0
800175e: 4619 mov r1, r3
8001760: 4620 mov r0, r4
8001762: f7ff f897 bl 8000894 <__addsf3>
8001766: 4603 mov r3, r0
8001768: 461a mov r2, r3
800176a: 687b ldr r3, [r7, #4]
800176c: 635a str r2, [r3, #52] @ 0x34
//ch->filtered_value = window_average;
ch->value_valid = 1;
800176e: 687b ldr r3, [r7, #4]
8001770: 2201 movs r2, #1
8001772: f883 2038 strb.w r2, [r3, #56] @ 0x38
8001776: e000 b.n 800177a <AD5934_Process_Sample+0x11a>
return; /* still collecting the burst, nothing else to do */
8001778: bf00 nop
}
800177a: 3714 adds r7, #20
800177c: 46bd mov sp, r7
800177e: bd90 pop {r4, r7, pc}
8001780: 3dcccccd .word 0x3dcccccd
8001784: 3f666666 .word 0x3f666666
8001788: 3f266666 .word 0x3f266666
800178c: 3eb33333 .word 0x3eb33333
08001790 <AD5934_RTD_NewSample>:
/* ---------------------------------------------------------------------- */
/* Call this every time a sweep completes with the mux on the RTD
* (PT100/PT1000) channel */
void AD5934_RTD_NewSample(float raw)
{
8001790: b580 push {r7, lr}
8001792: b082 sub sp, #8
8001794: af00 add r7, sp, #0
8001796: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_rtd_filter, raw);
8001798: 6879 ldr r1, [r7, #4]
800179a: 4803 ldr r0, [pc, #12] @ (80017a8 <AD5934_RTD_NewSample+0x18>)
800179c: f7ff ff60 bl 8001660 <AD5934_Process_Sample>
}
80017a0: bf00 nop
80017a2: 3708 adds r7, #8
80017a4: 46bd mov sp, r7
80017a6: bd80 pop {r7, pc}
80017a8: 20000094 .word 0x20000094
080017ac <AD5934_EC_NewSample>:
/* Call this every time a sweep completes with the mux on the EC
* (conductivity probe) channel */
void AD5934_EC_NewSample(float raw)
{
80017ac: b580 push {r7, lr}
80017ae: b082 sub sp, #8
80017b0: af00 add r7, sp, #0
80017b2: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_ec_filter, raw);
80017b4: 6879 ldr r1, [r7, #4]
80017b6: 4803 ldr r0, [pc, #12] @ (80017c4 <AD5934_EC_NewSample+0x18>)
80017b8: f7ff ff52 bl 8001660 <AD5934_Process_Sample>
}
80017bc: bf00 nop
80017be: 3708 adds r7, #8
80017c0: 46bd mov sp, r7
80017c2: bd80 pop {r7, pc}
80017c4: 200000d0 .word 0x200000d0
080017c8 <AD5934_Reference_NewSample>:
/* Call this every time a sweep completes with the mux on the on-board
* precision reference resistor channel */
void AD5934_Reference_NewSample(float raw)
{
80017c8: b580 push {r7, lr}
80017ca: b082 sub sp, #8
80017cc: af00 add r7, sp, #0
80017ce: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_ref_filter, raw);
80017d0: 6879 ldr r1, [r7, #4]
80017d2: 4803 ldr r0, [pc, #12] @ (80017e0 <AD5934_Reference_NewSample+0x18>)
80017d4: f7ff ff44 bl 8001660 <AD5934_Process_Sample>
}
80017d8: bf00 nop
80017da: 3708 adds r7, #8
80017dc: 46bd mov sp, r7
80017de: bd80 pop {r7, pc}
80017e0: 2000010c .word 0x2000010c
080017e4 <ADG715_SetRegisterValue>:
*
* @return None.
*******************************************************************************/
void ADG715_SetRegisterValue(char value)
{
80017e4: b580 push {r7, lr}
80017e6: b086 sub sp, #24
80017e8: af02 add r7, sp, #8
80017ea: 4603 mov r3, r0
80017ec: 71fb strb r3, [r7, #7]
uint8_t writeData[1] = {value};
80017ee: 79fb ldrb r3, [r7, #7]
80017f0: 733b strb r3, [r7, #12]
HAL_StatusTypeDef status;
status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
80017f2: f107 020c add.w r2, r7, #12
80017f6: 2301 movs r3, #1
80017f8: 9300 str r3, [sp, #0]
80017fa: 2301 movs r3, #1
80017fc: 2190 movs r1, #144 @ 0x90
80017fe: 4804 ldr r0, [pc, #16] @ (8001810 <ADG715_SetRegisterValue+0x2c>)
8001800: f002 fb38 bl 8003e74 <HAL_I2C_Master_Transmit>
8001804: 4603 mov r3, r0
8001806: 73fb strb r3, [r7, #15]
return;
8001808: bf00 nop
}
800180a: 3710 adds r7, #16
800180c: 46bd mov sp, r7
800180e: bd80 pop {r7, pc}
8001810: 2000026c .word 0x2000026c
08001814 <ADG715_ResetChannels>:
*
* @return none.
******************************************************************************/
void ADG715_ResetChannels(void)
{
8001814: b580 push {r7, lr}
8001816: af00 add r7, sp, #0
ADG715_SetRegisterValue(0);
8001818: 2000 movs r0, #0
800181a: f7ff ffe3 bl 80017e4 <ADG715_SetRegisterValue>
}
800181e: bf00 nop
8001820: bd80 pop {r7, pc}
...
08001824 <ADG715_SetChannels>:
* @param: channel
*
* @return none.
******************************************************************************/
void ADG715_SetChannels(AD5934_Channel_t channel)
{
8001824: b580 push {r7, lr}
8001826: b082 sub sp, #8
8001828: af00 add r7, sp, #0
800182a: 4603 mov r3, r0
800182c: 71fb strb r3, [r7, #7]
// Garante que o índice recebido não ultrapassa os limites do vetor
if (channel >= AD5934_CH_MAX)
800182e: 79fb ldrb r3, [r7, #7]
8001830: 2b0e cmp r3, #14
8001832: d806 bhi.n 8001842 <ADG715_SetChannels+0x1e>
return;
// Envia o byte combinado via I2C (Make-before-break nativo por barramento)
ADG715_SetRegisterValue(ADG715_Channel_Map[channel]);
8001834: 79fb ldrb r3, [r7, #7]
8001836: 4a05 ldr r2, [pc, #20] @ (800184c <ADG715_SetChannels+0x28>)
8001838: 5cd3 ldrb r3, [r2, r3]
800183a: 4618 mov r0, r3
800183c: f7ff ffd2 bl 80017e4 <ADG715_SetRegisterValue>
8001840: e000 b.n 8001844 <ADG715_SetChannels+0x20>
return;
8001842: bf00 nop
}
8001844: 3708 adds r7, #8
8001846: 46bd mov sp, r7
8001848: bd80 pop {r7, pc}
800184a: bf00 nop
800184c: 08006bd8 .word 0x08006bd8
08001850 <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
8001850: b580 push {r7, lr}
8001852: b084 sub sp, #16
8001854: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8001856: 1d3b adds r3, r7, #4
8001858: 2200 movs r2, #0
800185a: 601a str r2, [r3, #0]
800185c: 605a str r2, [r3, #4]
800185e: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8001860: 4b18 ldr r3, [pc, #96] @ (80018c4 <MX_ADC1_Init+0x74>)
8001862: 4a19 ldr r2, [pc, #100] @ (80018c8 <MX_ADC1_Init+0x78>)
8001864: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001866: 4b17 ldr r3, [pc, #92] @ (80018c4 <MX_ADC1_Init+0x74>)
8001868: 2200 movs r2, #0
800186a: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
800186c: 4b15 ldr r3, [pc, #84] @ (80018c4 <MX_ADC1_Init+0x74>)
800186e: 2201 movs r2, #1
8001870: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8001872: 4b14 ldr r3, [pc, #80] @ (80018c4 <MX_ADC1_Init+0x74>)
8001874: 2200 movs r2, #0
8001876: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001878: 4b12 ldr r3, [pc, #72] @ (80018c4 <MX_ADC1_Init+0x74>)
800187a: f44f 2260 mov.w r2, #917504 @ 0xe0000
800187e: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001880: 4b10 ldr r3, [pc, #64] @ (80018c4 <MX_ADC1_Init+0x74>)
8001882: 2200 movs r2, #0
8001884: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 1;
8001886: 4b0f ldr r3, [pc, #60] @ (80018c4 <MX_ADC1_Init+0x74>)
8001888: 2201 movs r2, #1
800188a: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
800188c: 480d ldr r0, [pc, #52] @ (80018c4 <MX_ADC1_Init+0x74>)
800188e: f001 fc0f bl 80030b0 <HAL_ADC_Init>
8001892: 4603 mov r3, r0
8001894: 2b00 cmp r3, #0
8001896: d001 beq.n 800189c <MX_ADC1_Init+0x4c>
{
Error_Handler();
8001898: f001 f8fa bl 8002a90 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_0;
800189c: 2300 movs r3, #0
800189e: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80018a0: 2301 movs r3, #1
80018a2: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80018a4: 2300 movs r3, #0
80018a6: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80018a8: 1d3b adds r3, r7, #4
80018aa: 4619 mov r1, r3
80018ac: 4805 ldr r0, [pc, #20] @ (80018c4 <MX_ADC1_Init+0x74>)
80018ae: f001 fcd7 bl 8003260 <HAL_ADC_ConfigChannel>
80018b2: 4603 mov r3, r0
80018b4: 2b00 cmp r3, #0
80018b6: d001 beq.n 80018bc <MX_ADC1_Init+0x6c>
{
Error_Handler();
80018b8: f001 f8ea bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80018bc: bf00 nop
80018be: 3710 adds r7, #16
80018c0: 46bd mov sp, r7
80018c2: bd80 pop {r7, pc}
80018c4: 20000154 .word 0x20000154
80018c8: 40012400 .word 0x40012400
080018cc <MX_ADC2_Init>:
/* ADC2 init function */
void MX_ADC2_Init(void)
{
80018cc: b580 push {r7, lr}
80018ce: b084 sub sp, #16
80018d0: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80018d2: 1d3b adds r3, r7, #4
80018d4: 2200 movs r2, #0
80018d6: 601a str r2, [r3, #0]
80018d8: 605a str r2, [r3, #4]
80018da: 609a str r2, [r3, #8]
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
80018dc: 4b18 ldr r3, [pc, #96] @ (8001940 <MX_ADC2_Init+0x74>)
80018de: 4a19 ldr r2, [pc, #100] @ (8001944 <MX_ADC2_Init+0x78>)
80018e0: 601a str r2, [r3, #0]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
80018e2: 4b17 ldr r3, [pc, #92] @ (8001940 <MX_ADC2_Init+0x74>)
80018e4: 2200 movs r2, #0
80018e6: 609a str r2, [r3, #8]
hadc2.Init.ContinuousConvMode = ENABLE;
80018e8: 4b15 ldr r3, [pc, #84] @ (8001940 <MX_ADC2_Init+0x74>)
80018ea: 2201 movs r2, #1
80018ec: 731a strb r2, [r3, #12]
hadc2.Init.DiscontinuousConvMode = DISABLE;
80018ee: 4b14 ldr r3, [pc, #80] @ (8001940 <MX_ADC2_Init+0x74>)
80018f0: 2200 movs r2, #0
80018f2: 751a strb r2, [r3, #20]
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80018f4: 4b12 ldr r3, [pc, #72] @ (8001940 <MX_ADC2_Init+0x74>)
80018f6: f44f 2260 mov.w r2, #917504 @ 0xe0000
80018fa: 61da str r2, [r3, #28]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80018fc: 4b10 ldr r3, [pc, #64] @ (8001940 <MX_ADC2_Init+0x74>)
80018fe: 2200 movs r2, #0
8001900: 605a str r2, [r3, #4]
hadc2.Init.NbrOfConversion = 1;
8001902: 4b0f ldr r3, [pc, #60] @ (8001940 <MX_ADC2_Init+0x74>)
8001904: 2201 movs r2, #1
8001906: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8001908: 480d ldr r0, [pc, #52] @ (8001940 <MX_ADC2_Init+0x74>)
800190a: f001 fbd1 bl 80030b0 <HAL_ADC_Init>
800190e: 4603 mov r3, r0
8001910: 2b00 cmp r3, #0
8001912: d001 beq.n 8001918 <MX_ADC2_Init+0x4c>
{
Error_Handler();
8001914: f001 f8bc bl 8002a90 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
8001918: 2301 movs r3, #1
800191a: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
800191c: 2301 movs r3, #1
800191e: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
8001920: 2300 movs r3, #0
8001922: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8001924: 1d3b adds r3, r7, #4
8001926: 4619 mov r1, r3
8001928: 4805 ldr r0, [pc, #20] @ (8001940 <MX_ADC2_Init+0x74>)
800192a: f001 fc99 bl 8003260 <HAL_ADC_ConfigChannel>
800192e: 4603 mov r3, r0
8001930: 2b00 cmp r3, #0
8001932: d001 beq.n 8001938 <MX_ADC2_Init+0x6c>
{
Error_Handler();
8001934: f001 f8ac bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8001938: bf00 nop
800193a: 3710 adds r7, #16
800193c: 46bd mov sp, r7
800193e: bd80 pop {r7, pc}
8001940: 20000184 .word 0x20000184
8001944: 40012800 .word 0x40012800
08001948 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
8001948: b580 push {r7, lr}
800194a: b08a sub sp, #40 @ 0x28
800194c: af00 add r7, sp, #0
800194e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001950: f107 0318 add.w r3, r7, #24
8001954: 2200 movs r2, #0
8001956: 601a str r2, [r3, #0]
8001958: 605a str r2, [r3, #4]
800195a: 609a str r2, [r3, #8]
800195c: 60da str r2, [r3, #12]
if(adcHandle->Instance==ADC1)
800195e: 687b ldr r3, [r7, #4]
8001960: 681b ldr r3, [r3, #0]
8001962: 4a28 ldr r2, [pc, #160] @ (8001a04 <HAL_ADC_MspInit+0xbc>)
8001964: 4293 cmp r3, r2
8001966: d122 bne.n 80019ae <HAL_ADC_MspInit+0x66>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001968: 4b27 ldr r3, [pc, #156] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
800196a: 699b ldr r3, [r3, #24]
800196c: 4a26 ldr r2, [pc, #152] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
800196e: f443 7300 orr.w r3, r3, #512 @ 0x200
8001972: 6193 str r3, [r2, #24]
8001974: 4b24 ldr r3, [pc, #144] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
8001976: 699b ldr r3, [r3, #24]
8001978: f403 7300 and.w r3, r3, #512 @ 0x200
800197c: 617b str r3, [r7, #20]
800197e: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001980: 4b21 ldr r3, [pc, #132] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
8001982: 699b ldr r3, [r3, #24]
8001984: 4a20 ldr r2, [pc, #128] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
8001986: f043 0304 orr.w r3, r3, #4
800198a: 6193 str r3, [r2, #24]
800198c: 4b1e ldr r3, [pc, #120] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
800198e: 699b ldr r3, [r3, #24]
8001990: f003 0304 and.w r3, r3, #4
8001994: 613b str r3, [r7, #16]
8001996: 693b ldr r3, [r7, #16]
/**ADC1 GPIO Configuration
PA0-WKUP ------> ADC1_IN0
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
8001998: 2303 movs r3, #3
800199a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800199c: 2303 movs r3, #3
800199e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80019a0: f107 0318 add.w r3, r7, #24
80019a4: 4619 mov r1, r3
80019a6: 4819 ldr r0, [pc, #100] @ (8001a0c <HAL_ADC_MspInit+0xc4>)
80019a8: f001 ff54 bl 8003854 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80019ac: e026 b.n 80019fc <HAL_ADC_MspInit+0xb4>
else if(adcHandle->Instance==ADC2)
80019ae: 687b ldr r3, [r7, #4]
80019b0: 681b ldr r3, [r3, #0]
80019b2: 4a17 ldr r2, [pc, #92] @ (8001a10 <HAL_ADC_MspInit+0xc8>)
80019b4: 4293 cmp r3, r2
80019b6: d121 bne.n 80019fc <HAL_ADC_MspInit+0xb4>
__HAL_RCC_ADC2_CLK_ENABLE();
80019b8: 4b13 ldr r3, [pc, #76] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019ba: 699b ldr r3, [r3, #24]
80019bc: 4a12 ldr r2, [pc, #72] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019be: f443 6380 orr.w r3, r3, #1024 @ 0x400
80019c2: 6193 str r3, [r2, #24]
80019c4: 4b10 ldr r3, [pc, #64] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019c6: 699b ldr r3, [r3, #24]
80019c8: f403 6380 and.w r3, r3, #1024 @ 0x400
80019cc: 60fb str r3, [r7, #12]
80019ce: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80019d0: 4b0d ldr r3, [pc, #52] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019d2: 699b ldr r3, [r3, #24]
80019d4: 4a0c ldr r2, [pc, #48] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019d6: f043 0304 orr.w r3, r3, #4
80019da: 6193 str r3, [r2, #24]
80019dc: 4b0a ldr r3, [pc, #40] @ (8001a08 <HAL_ADC_MspInit+0xc0>)
80019de: 699b ldr r3, [r3, #24]
80019e0: f003 0304 and.w r3, r3, #4
80019e4: 60bb str r3, [r7, #8]
80019e6: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
80019e8: 2303 movs r3, #3
80019ea: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80019ec: 2303 movs r3, #3
80019ee: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80019f0: f107 0318 add.w r3, r7, #24
80019f4: 4619 mov r1, r3
80019f6: 4805 ldr r0, [pc, #20] @ (8001a0c <HAL_ADC_MspInit+0xc4>)
80019f8: f001 ff2c bl 8003854 <HAL_GPIO_Init>
}
80019fc: bf00 nop
80019fe: 3728 adds r7, #40 @ 0x28
8001a00: 46bd mov sp, r7
8001a02: bd80 pop {r7, pc}
8001a04: 40012400 .word 0x40012400
8001a08: 40021000 .word 0x40021000
8001a0c: 40010800 .word 0x40010800
8001a10: 40012800 .word 0x40012800
08001a14 <writeRegister>:
ADS1015_filter_t g_ph_filter = {0};
volatile ADS1015_State_t ads1015_state = ADS1015_IDLE;
// Write the register
static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
8001a14: b580 push {r7, lr}
8001a16: b086 sub sp, #24
8001a18: af02 add r7, sp, #8
8001a1a: 6078 str r0, [r7, #4]
8001a1c: 460b mov r3, r1
8001a1e: 70fb strb r3, [r7, #3]
8001a20: 4613 mov r3, r2
8001a22: 803b strh r3, [r7, #0]
uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
8001a24: 78fb ldrb r3, [r7, #3]
8001a26: 733b strb r3, [r7, #12]
8001a28: 883b ldrh r3, [r7, #0]
8001a2a: 0a1b lsrs r3, r3, #8
8001a2c: b29b uxth r3, r3
8001a2e: b2db uxtb r3, r3
8001a30: 737b strb r3, [r7, #13]
8001a32: 883b ldrh r3, [r7, #0]
8001a34: b2db uxtb r3, r3
8001a36: 73bb strb r3, [r7, #14]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 68d8 ldr r0, [r3, #12]
8001a3c: 687b ldr r3, [r7, #4]
8001a3e: 8819 ldrh r1, [r3, #0]
8001a40: f107 020c add.w r2, r7, #12
8001a44: 230a movs r3, #10
8001a46: 9300 str r3, [sp, #0]
8001a48: 2303 movs r3, #3
8001a4a: f002 fa13 bl 8003e74 <HAL_I2C_Master_Transmit>
}
8001a4e: bf00 nop
8001a50: 3710 adds r7, #16
8001a52: 46bd mov sp, r7
8001a54: bd80 pop {r7, pc}
08001a56 <readRegister>:
// Read the register
static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
8001a56: b580 push {r7, lr}
8001a58: b086 sub sp, #24
8001a5a: af02 add r7, sp, #8
8001a5c: 6078 str r0, [r7, #4]
8001a5e: 460b mov r3, r1
8001a60: 70fb strb r3, [r7, #3]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, &reg, 1, 10);
8001a62: 687b ldr r3, [r7, #4]
8001a64: 68d8 ldr r0, [r3, #12]
8001a66: 687b ldr r3, [r7, #4]
8001a68: 8819 ldrh r1, [r3, #0]
8001a6a: 1cfa adds r2, r7, #3
8001a6c: 230a movs r3, #10
8001a6e: 9300 str r3, [sp, #0]
8001a70: 2301 movs r3, #1
8001a72: f002 f9ff bl 8003e74 <HAL_I2C_Master_Transmit>
uint8_t pData[2] = { 0, 0 };
8001a76: 2300 movs r3, #0
8001a78: 81bb strh r3, [r7, #12]
HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: 68d8 ldr r0, [r3, #12]
8001a7e: 687b ldr r3, [r7, #4]
8001a80: 8819 ldrh r1, [r3, #0]
8001a82: f107 020c add.w r2, r7, #12
8001a86: 230a movs r3, #10
8001a88: 9300 str r3, [sp, #0]
8001a8a: 2302 movs r3, #2
8001a8c: f002 faf0 bl 8004070 <HAL_I2C_Master_Receive>
return ((pData[0] << 8) | pData[1]);
8001a90: 7b3b ldrb r3, [r7, #12]
8001a92: b21b sxth r3, r3
8001a94: 021b lsls r3, r3, #8
8001a96: b21a sxth r2, r3
8001a98: 7b7b ldrb r3, [r7, #13]
8001a9a: b21b sxth r3, r3
8001a9c: 4313 orrs r3, r2
8001a9e: b21b sxth r3, r3
8001aa0: b29b uxth r3, r3
}
8001aa2: 4618 mov r0, r3
8001aa4: 3710 adds r7, #16
8001aa6: 46bd mov sp, r7
8001aa8: bd80 pop {r7, pc}
...
08001aac <ADS1015_Init>:
// ADSsetGain(GAIN_EIGHT); // 8x gain +/- 0.512V 1 bit = 0.25mV 0.015625mV
// ADSsetGain(GAIN_SIXTEEN); // 16x gain +/- 0.256V 1 bit = 0.125mV 0.0078125mV
*/
// Declare an ADS1015 structure
void ADS1015_Init(void)
{
8001aac: b480 push {r7}
8001aae: af00 add r7, sp, #0
i2c_ads1015.hi2c = &hi2c1;
8001ab0: 4b09 ldr r3, [pc, #36] @ (8001ad8 <ADS1015_Init+0x2c>)
8001ab2: 4a0a ldr r2, [pc, #40] @ (8001adc <ADS1015_Init+0x30>)
8001ab4: 60da str r2, [r3, #12]
i2c_ads1015.m_i2cAddress = ADS1015_ADDR_GND; // It's Important to shift the address << 1
8001ab6: 4b08 ldr r3, [pc, #32] @ (8001ad8 <ADS1015_Init+0x2c>)
8001ab8: 2290 movs r2, #144 @ 0x90
8001aba: 801a strh r2, [r3, #0]
i2c_ads1015.m_conversionDelay = ADS1015_CONVERSIONDELAY;
8001abc: 4b06 ldr r3, [pc, #24] @ (8001ad8 <ADS1015_Init+0x2c>)
8001abe: 2204 movs r2, #4
8001ac0: 605a str r2, [r3, #4]
i2c_ads1015.m_bitShift = 4;
8001ac2: 4b05 ldr r3, [pc, #20] @ (8001ad8 <ADS1015_Init+0x2c>)
8001ac4: 2204 movs r2, #4
8001ac6: 721a strb r2, [r3, #8]
i2c_ads1015.m_gain = GAIN_FOUR; /* 4x gain +/- 1.024V 1 bit = 0.5mV 0.03125mV */
8001ac8: 4b03 ldr r3, [pc, #12] @ (8001ad8 <ADS1015_Init+0x2c>)
8001aca: f44f 62c0 mov.w r2, #1536 @ 0x600
8001ace: 815a strh r2, [r3, #10]
}
8001ad0: bf00 nop
8001ad2: 46bd mov sp, r7
8001ad4: bc80 pop {r7}
8001ad6: 4770 bx lr
8001ad8: 200001b4 .word 0x200001b4
8001adc: 20000218 .word 0x20000218
08001ae0 <ADS1015_Compress_To_IntScale>:
* @param value Valor float entre FLOAT_MIN e FLOAT_MAX
*
* @return uint16_t Valor convertido na escala de UINT16_MIN a UINT16_MAX
*/
uint16_t ADS1015_Compress_To_IntScale(float value)
{
8001ae0: b580 push {r7, lr}
8001ae2: b084 sub sp, #16
8001ae4: af00 add r7, sp, #0
8001ae6: 6078 str r0, [r7, #4]
// Verifica limites do valor de entrada
if (value < ADS1015_PH_FLOAT_SCALE_MIN)
8001ae8: 491c ldr r1, [pc, #112] @ (8001b5c <ADS1015_Compress_To_IntScale+0x7c>)
8001aea: 6878 ldr r0, [r7, #4]
8001aec: f7ff f978 bl 8000de0 <__aeabi_fcmplt>
8001af0: 4603 mov r3, r0
8001af2: 2b00 cmp r3, #0
8001af4: d001 beq.n 8001afa <ADS1015_Compress_To_IntScale+0x1a>
return ADS1015_PH_OUT_SCALE_MIN;
8001af6: 2300 movs r3, #0
8001af8: e02c b.n 8001b54 <ADS1015_Compress_To_IntScale+0x74>
else if (value > ADS1015_PH_FLOAT_SCALE_MAX)
8001afa: 4919 ldr r1, [pc, #100] @ (8001b60 <ADS1015_Compress_To_IntScale+0x80>)
8001afc: 6878 ldr r0, [r7, #4]
8001afe: f7ff f98d bl 8000e1c <__aeabi_fcmpgt>
8001b02: 4603 mov r3, r0
8001b04: 2b00 cmp r3, #0
8001b06: d002 beq.n 8001b0e <ADS1015_Compress_To_IntScale+0x2e>
return ADS1015_PH_OUT_SCALE_MAX;
8001b08: f44f 5380 mov.w r3, #4096 @ 0x1000
8001b0c: e022 b.n 8001b54 <ADS1015_Compress_To_IntScale+0x74>
// Converte o valor usando a fórmula: ((value - FLOAT_MIN) / (FLOAT_MAX - FLOAT_MIN)) * (UINT16_MAX - UINT16_MIN) + UINT16_MIN
uint16_t result = (uint16_t)(((value - ADS1015_PH_FLOAT_SCALE_MIN) / (ADS1015_PH_FLOAT_SCALE_MAX - ADS1015_PH_FLOAT_SCALE_MIN)) * ((float)ADS1015_PH_OUT_SCALE_MAX - (float)ADS1015_PH_OUT_SCALE_MIN) + (float)ADS1015_PH_OUT_SCALE_MIN);
8001b0e: 4913 ldr r1, [pc, #76] @ (8001b5c <ADS1015_Compress_To_IntScale+0x7c>)
8001b10: 6878 ldr r0, [r7, #4]
8001b12: f7fe febd bl 8000890 <__aeabi_fsub>
8001b16: 4603 mov r3, r0
8001b18: 4912 ldr r1, [pc, #72] @ (8001b64 <ADS1015_Compress_To_IntScale+0x84>)
8001b1a: 4618 mov r0, r3
8001b1c: f7ff f876 bl 8000c0c <__aeabi_fdiv>
8001b20: 4603 mov r3, r0
8001b22: f04f 418b mov.w r1, #1166016512 @ 0x45800000
8001b26: 4618 mov r0, r3
8001b28: f7fe ffbc bl 8000aa4 <__aeabi_fmul>
8001b2c: 4603 mov r3, r0
8001b2e: f04f 0100 mov.w r1, #0
8001b32: 4618 mov r0, r3
8001b34: f7fe feae bl 8000894 <__addsf3>
8001b38: 4603 mov r3, r0
8001b3a: 4618 mov r0, r3
8001b3c: f7ff f9b4 bl 8000ea8 <__aeabi_f2uiz>
8001b40: 4603 mov r3, r0
8001b42: 81fb strh r3, [r7, #14]
// Garante que o resultado não exceda o limite superior
if (result > ADS1015_PH_OUT_SCALE_MAX)
8001b44: 89fb ldrh r3, [r7, #14]
8001b46: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8001b4a: d902 bls.n 8001b52 <ADS1015_Compress_To_IntScale+0x72>
return (ADS1015_PH_OUT_SCALE_MAX);
8001b4c: f44f 5380 mov.w r3, #4096 @ 0x1000
8001b50: e000 b.n 8001b54 <ADS1015_Compress_To_IntScale+0x74>
return result;
8001b52: 89fb ldrh r3, [r7, #14]
}
8001b54: 4618 mov r0, r3
8001b56: 3710 adds r7, #16
8001b58: 46bd mov sp, r7
8001b5a: bd80 pop {r7, pc}
8001b5c: 447a0000 .word 0x447a0000
8001b60: 453b8000 .word 0x453b8000
8001b64: 44fa0000 .word 0x44fa0000
08001b68 <ADS1015_Process_System>:
void ADS1015_Process_System(void)
{
8001b68: b580 push {r7, lr}
8001b6a: b082 sub sp, #8
8001b6c: af00 add r7, sp, #0
static uint32_t state_timer = 0;
static uint32_t sample_count = 0;
uint16_t config_reg = 0;
8001b6e: 2300 movs r3, #0
8001b70: 80fb strh r3, [r7, #6]
switch (ads1015_state)
8001b72: 4b3d ldr r3, [pc, #244] @ (8001c68 <ADS1015_Process_System+0x100>)
8001b74: 781b ldrb r3, [r3, #0]
8001b76: b2db uxtb r3, r3
8001b78: 2b04 cmp r3, #4
8001b7a: d870 bhi.n 8001c5e <ADS1015_Process_System+0xf6>
8001b7c: a201 add r2, pc, #4 @ (adr r2, 8001b84 <ADS1015_Process_System+0x1c>)
8001b7e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001b82: bf00 nop
8001b84: 08001b99 .word 0x08001b99
8001b88: 08001ba7 .word 0x08001ba7
8001b8c: 08001bc3 .word 0x08001bc3
8001b90: 08001bed .word 0x08001bed
8001b94: 08001c43 .word 0x08001c43
{
case ADS1015_IDLE:
sample_count = 0;
8001b98: 4b34 ldr r3, [pc, #208] @ (8001c6c <ADS1015_Process_System+0x104>)
8001b9a: 2200 movs r2, #0
8001b9c: 601a str r2, [r3, #0]
ads1015_state = ADS1015_START_CONVERSION;
8001b9e: 4b32 ldr r3, [pc, #200] @ (8001c68 <ADS1015_Process_System+0x100>)
8001ba0: 2201 movs r2, #1
8001ba2: 701a strb r2, [r3, #0]
break;
8001ba4: e05b b.n 8001c5e <ADS1015_Process_System+0xf6>
case ADS1015_START_CONVERSION:
state_timer = g_ms_counter;
8001ba6: 4b32 ldr r3, [pc, #200] @ (8001c70 <ADS1015_Process_System+0x108>)
8001ba8: 681b ldr r3, [r3, #0]
8001baa: 4a32 ldr r2, [pc, #200] @ (8001c74 <ADS1015_Process_System+0x10c>)
8001bac: 6013 str r3, [r2, #0]
/* Escreve no Config Register (P[1:0]=01b) com OS=1 para
* iniciar a conversão single-shot. O bit OS só tem efeito
* quando o dispositivo está em power-down (seção 7.4.2.1) */
// Write config register to the ADC
writeRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG, ADS1015_CONFIG_START_SINGLE);
8001bae: f248 7203 movw r2, #34563 @ 0x8703
8001bb2: 2101 movs r1, #1
8001bb4: 4830 ldr r0, [pc, #192] @ (8001c78 <ADS1015_Process_System+0x110>)
8001bb6: f7ff ff2d bl 8001a14 <writeRegister>
ads1015_state = ADS1015_WAIT_CONVERSION;
8001bba: 4b2b ldr r3, [pc, #172] @ (8001c68 <ADS1015_Process_System+0x100>)
8001bbc: 2202 movs r2, #2
8001bbe: 701a strb r2, [r3, #0]
break;
8001bc0: e04d b.n 8001c5e <ADS1015_Process_System+0xf6>
* 0b = dispositivo ainda convertendo
* 1b = conversão concluída, dado pronto no Conversion Register
* (Tabela 8-4, descrição do bit OS)
*/
config_reg = readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG);
8001bc2: 2101 movs r1, #1
8001bc4: 482c ldr r0, [pc, #176] @ (8001c78 <ADS1015_Process_System+0x110>)
8001bc6: f7ff ff46 bl 8001a56 <readRegister>
8001bca: 4603 mov r3, r0
8001bcc: 80fb strh r3, [r7, #6]
if (((config_reg & ADS1015_REG_CONFIG_OS_SINGLE) != 0) && (g_ms_counter - state_timer)>ADS1015_TIME_PER_SAMPLE)
8001bce: f9b7 3006 ldrsh.w r3, [r7, #6]
8001bd2: 2b00 cmp r3, #0
8001bd4: da40 bge.n 8001c58 <ADS1015_Process_System+0xf0>
8001bd6: 4b26 ldr r3, [pc, #152] @ (8001c70 <ADS1015_Process_System+0x108>)
8001bd8: 681a ldr r2, [r3, #0]
8001bda: 4b26 ldr r3, [pc, #152] @ (8001c74 <ADS1015_Process_System+0x10c>)
8001bdc: 681b ldr r3, [r3, #0]
8001bde: 1ad3 subs r3, r2, r3
8001be0: 2b09 cmp r3, #9
8001be2: d939 bls.n 8001c58 <ADS1015_Process_System+0xf0>
{
ads1015_state = ADS1015_READ_DATA;
8001be4: 4b20 ldr r3, [pc, #128] @ (8001c68 <ADS1015_Process_System+0x100>)
8001be6: 2203 movs r2, #3
8001be8: 701a strb r2, [r3, #0]
}
// (opcional) tratar timeout comparando g_ms_counter - state_timer
// Datasheet: conversão single-cycle, tempo = 1/DR (ex: 1600SPS ≈ 625µs)
break;
8001bea: e035 b.n 8001c58 <ADS1015_Process_System+0xf0>
case ADS1015_READ_DATA:
{
/* Muda o Address Pointer para o Conversion Register (P[1:0]=00b)
* e lê os 16 bits. Dado é 12 bits em complemento de 2,
* left-justified em D[15:4]; D[3:0] sempre lê 0h (Tabela 8-3) */
int16_t raw = (int16_t)readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONVERT);
8001bec: 2100 movs r1, #0
8001bee: 4822 ldr r0, [pc, #136] @ (8001c78 <ADS1015_Process_System+0x110>)
8001bf0: f7ff ff31 bl 8001a56 <readRegister>
8001bf4: 4603 mov r3, r0
8001bf6: 80bb strh r3, [r7, #4]
raw >>= 4; // remove os 4 bits reservados (D[3:0]), resultado = 12 bits signed
8001bf8: f9b7 3004 ldrsh.w r3, [r7, #4]
8001bfc: 111b asrs r3, r3, #4
8001bfe: 80bb strh r3, [r7, #4]
float value = (float)(2048 - raw); // ((float)raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX; // usa FSR configurado no PGA
8001c00: f9b7 3004 ldrsh.w r3, [r7, #4]
8001c04: f5c3 6300 rsb r3, r3, #2048 @ 0x800
8001c08: 4618 mov r0, r3
8001c0a: f7fe fef7 bl 80009fc <__aeabi_i2f>
8001c0e: 4603 mov r3, r0
8001c10: 603b str r3, [r7, #0]
ADS1015_pH_NewSample(value);
8001c12: 6838 ldr r0, [r7, #0]
8001c14: f000 f98c bl 8001f30 <ADS1015_pH_NewSample>
sample_count++;
8001c18: 4b14 ldr r3, [pc, #80] @ (8001c6c <ADS1015_Process_System+0x104>)
8001c1a: 681b ldr r3, [r3, #0]
8001c1c: 3301 adds r3, #1
8001c1e: 4a13 ldr r2, [pc, #76] @ (8001c6c <ADS1015_Process_System+0x104>)
8001c20: 6013 str r3, [r2, #0]
if (sample_count >= ADS1015_BURST_SIZE)
8001c22: 4b12 ldr r3, [pc, #72] @ (8001c6c <ADS1015_Process_System+0x104>)
8001c24: 681b ldr r3, [r3, #0]
8001c26: 2b04 cmp r3, #4
8001c28: d903 bls.n 8001c32 <ADS1015_Process_System+0xca>
{
ads1015_state = ADS1015_IDLE;
8001c2a: 4b0f ldr r3, [pc, #60] @ (8001c68 <ADS1015_Process_System+0x100>)
8001c2c: 2200 movs r2, #0
8001c2e: 701a strb r2, [r3, #0]
{
state_timer = g_ms_counter;
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
}
}
break;
8001c30: e015 b.n 8001c5e <ADS1015_Process_System+0xf6>
state_timer = g_ms_counter;
8001c32: 4b0f ldr r3, [pc, #60] @ (8001c70 <ADS1015_Process_System+0x108>)
8001c34: 681b ldr r3, [r3, #0]
8001c36: 4a0f ldr r2, [pc, #60] @ (8001c74 <ADS1015_Process_System+0x10c>)
8001c38: 6013 str r3, [r2, #0]
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
8001c3a: 4b0b ldr r3, [pc, #44] @ (8001c68 <ADS1015_Process_System+0x100>)
8001c3c: 2204 movs r2, #4
8001c3e: 701a strb r2, [r3, #0]
break;
8001c40: e00d b.n 8001c5e <ADS1015_Process_System+0xf6>
case ADS1015_WAIT_NEXT_SAMPLE:
if ((g_ms_counter - state_timer) >= ADS1015_TIME_PER_SAMPLE)
8001c42: 4b0b ldr r3, [pc, #44] @ (8001c70 <ADS1015_Process_System+0x108>)
8001c44: 681a ldr r2, [r3, #0]
8001c46: 4b0b ldr r3, [pc, #44] @ (8001c74 <ADS1015_Process_System+0x10c>)
8001c48: 681b ldr r3, [r3, #0]
8001c4a: 1ad3 subs r3, r2, r3
8001c4c: 2b08 cmp r3, #8
8001c4e: d905 bls.n 8001c5c <ADS1015_Process_System+0xf4>
{
ads1015_state = ADS1015_START_CONVERSION;
8001c50: 4b05 ldr r3, [pc, #20] @ (8001c68 <ADS1015_Process_System+0x100>)
8001c52: 2201 movs r2, #1
8001c54: 701a strb r2, [r3, #0]
}
break;
8001c56: e001 b.n 8001c5c <ADS1015_Process_System+0xf4>
break;
8001c58: bf00 nop
8001c5a: e000 b.n 8001c5e <ADS1015_Process_System+0xf6>
break;
8001c5c: bf00 nop
}
}
8001c5e: bf00 nop
8001c60: 3708 adds r7, #8
8001c62: 46bd mov sp, r7
8001c64: bd80 pop {r7, pc}
8001c66: bf00 nop
8001c68: 20000204 .word 0x20000204
8001c6c: 20000208 .word 0x20000208
8001c70: 20000084 .word 0x20000084
8001c74: 2000020c .word 0x2000020c
8001c78: 200001b4 .word 0x200001b4
08001c7c <ADS1015_Sort_Array>:
/**
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
* and it avoids depending on qsort/heap allocation.
**/
void ADS1015_Sort_Array(float *v, uint8_t n)
{
8001c7c: b580 push {r7, lr}
8001c7e: b084 sub sp, #16
8001c80: af00 add r7, sp, #0
8001c82: 6078 str r0, [r7, #4]
8001c84: 460b mov r3, r1
8001c86: 70fb strb r3, [r7, #3]
for (uint8_t i = 1; i < n; i++)
8001c88: 2301 movs r3, #1
8001c8a: 73fb strb r3, [r7, #15]
8001c8c: e039 b.n 8001d02 <ADS1015_Sort_Array+0x86>
{
float key = v[i];
8001c8e: 7bfb ldrb r3, [r7, #15]
8001c90: 009b lsls r3, r3, #2
8001c92: 687a ldr r2, [r7, #4]
8001c94: 4413 add r3, r2
8001c96: 681b ldr r3, [r3, #0]
8001c98: 60bb str r3, [r7, #8]
int8_t j = (int8_t)i - 1;
8001c9a: 7bfb ldrb r3, [r7, #15]
8001c9c: 3b01 subs r3, #1
8001c9e: b2db uxtb r3, r3
8001ca0: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
8001ca2: e012 b.n 8001cca <ADS1015_Sort_Array+0x4e>
{
v[j + 1] = v[j];
8001ca4: f997 300e ldrsb.w r3, [r7, #14]
8001ca8: 009b lsls r3, r3, #2
8001caa: 687a ldr r2, [r7, #4]
8001cac: 441a add r2, r3
8001cae: f997 300e ldrsb.w r3, [r7, #14]
8001cb2: 3301 adds r3, #1
8001cb4: 009b lsls r3, r3, #2
8001cb6: 6879 ldr r1, [r7, #4]
8001cb8: 440b add r3, r1
8001cba: 6812 ldr r2, [r2, #0]
8001cbc: 601a str r2, [r3, #0]
j--;
8001cbe: f997 300e ldrsb.w r3, [r7, #14]
8001cc2: b2db uxtb r3, r3
8001cc4: 3b01 subs r3, #1
8001cc6: b2db uxtb r3, r3
8001cc8: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
8001cca: f997 300e ldrsb.w r3, [r7, #14]
8001cce: 2b00 cmp r3, #0
8001cd0: db0c blt.n 8001cec <ADS1015_Sort_Array+0x70>
8001cd2: f997 300e ldrsb.w r3, [r7, #14]
8001cd6: 009b lsls r3, r3, #2
8001cd8: 687a ldr r2, [r7, #4]
8001cda: 4413 add r3, r2
8001cdc: 681b ldr r3, [r3, #0]
8001cde: 4619 mov r1, r3
8001ce0: 68b8 ldr r0, [r7, #8]
8001ce2: f7ff f87d bl 8000de0 <__aeabi_fcmplt>
8001ce6: 4603 mov r3, r0
8001ce8: 2b00 cmp r3, #0
8001cea: d1db bne.n 8001ca4 <ADS1015_Sort_Array+0x28>
}
v[j + 1] = key;
8001cec: f997 300e ldrsb.w r3, [r7, #14]
8001cf0: 3301 adds r3, #1
8001cf2: 009b lsls r3, r3, #2
8001cf4: 687a ldr r2, [r7, #4]
8001cf6: 4413 add r3, r2
8001cf8: 68ba ldr r2, [r7, #8]
8001cfa: 601a str r2, [r3, #0]
for (uint8_t i = 1; i < n; i++)
8001cfc: 7bfb ldrb r3, [r7, #15]
8001cfe: 3301 adds r3, #1
8001d00: 73fb strb r3, [r7, #15]
8001d02: 7bfa ldrb r2, [r7, #15]
8001d04: 78fb ldrb r3, [r7, #3]
8001d06: 429a cmp r2, r3
8001d08: d3c1 bcc.n 8001c8e <ADS1015_Sort_Array+0x12>
}
}
8001d0a: bf00 nop
8001d0c: bf00 nop
8001d0e: 3710 adds r7, #16
8001d10: 46bd mov sp, r7
8001d12: bd80 pop {r7, pc}
08001d14 <ADS1015_Trimmed_Mean>:
* original order is not needed), discards TRIM_COUNT values from each
* end, and averages the remainder. Sorting in place avoids a temporary
* array and removes the need for memcpy()/string.h entirely.
**/
float ADS1015_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
{
8001d14: b580 push {r7, lr}
8001d16: b086 sub sp, #24
8001d18: af00 add r7, sp, #0
8001d1a: 6078 str r0, [r7, #4]
8001d1c: 460b mov r3, r1
8001d1e: 70fb strb r3, [r7, #3]
8001d20: 4613 mov r3, r2
8001d22: 70bb strb r3, [r7, #2]
ADS1015_Sort_Array(buffer, n);
8001d24: 78fb ldrb r3, [r7, #3]
8001d26: 4619 mov r1, r3
8001d28: 6878 ldr r0, [r7, #4]
8001d2a: f7ff ffa7 bl 8001c7c <ADS1015_Sort_Array>
uint8_t start = trim;
8001d2e: 78bb ldrb r3, [r7, #2]
8001d30: 75fb strb r3, [r7, #23]
uint8_t end = n - trim; /* exclusive */
8001d32: 78fa ldrb r2, [r7, #3]
8001d34: 78bb ldrb r3, [r7, #2]
8001d36: 1ad3 subs r3, r2, r3
8001d38: 75bb strb r3, [r7, #22]
if (end <= start) /* guard against a misconfigured trim value */
8001d3a: 7dba ldrb r2, [r7, #22]
8001d3c: 7dfb ldrb r3, [r7, #23]
8001d3e: 429a cmp r2, r3
8001d40: d803 bhi.n 8001d4a <ADS1015_Trimmed_Mean+0x36>
{
start = 0;
8001d42: 2300 movs r3, #0
8001d44: 75fb strb r3, [r7, #23]
end = n;
8001d46: 78fb ldrb r3, [r7, #3]
8001d48: 75bb strb r3, [r7, #22]
}
float sum = 0.0f;
8001d4a: f04f 0300 mov.w r3, #0
8001d4e: 613b str r3, [r7, #16]
uint8_t count = 0;
8001d50: 2300 movs r3, #0
8001d52: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001d54: 7dfb ldrb r3, [r7, #23]
8001d56: 73bb strb r3, [r7, #14]
8001d58: e010 b.n 8001d7c <ADS1015_Trimmed_Mean+0x68>
{
sum += buffer[i];
8001d5a: 7bbb ldrb r3, [r7, #14]
8001d5c: 009b lsls r3, r3, #2
8001d5e: 687a ldr r2, [r7, #4]
8001d60: 4413 add r3, r2
8001d62: 681b ldr r3, [r3, #0]
8001d64: 4619 mov r1, r3
8001d66: 6938 ldr r0, [r7, #16]
8001d68: f7fe fd94 bl 8000894 <__addsf3>
8001d6c: 4603 mov r3, r0
8001d6e: 613b str r3, [r7, #16]
count++;
8001d70: 7bfb ldrb r3, [r7, #15]
8001d72: 3301 adds r3, #1
8001d74: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001d76: 7bbb ldrb r3, [r7, #14]
8001d78: 3301 adds r3, #1
8001d7a: 73bb strb r3, [r7, #14]
8001d7c: 7bba ldrb r2, [r7, #14]
8001d7e: 7dbb ldrb r3, [r7, #22]
8001d80: 429a cmp r2, r3
8001d82: d3ea bcc.n 8001d5a <ADS1015_Trimmed_Mean+0x46>
}
return sum / (float)count;
8001d84: 7bfb ldrb r3, [r7, #15]
8001d86: 4618 mov r0, r3
8001d88: f7fe fe34 bl 80009f4 <__aeabi_ui2f>
8001d8c: 4603 mov r3, r0
8001d8e: 4619 mov r1, r3
8001d90: 6938 ldr r0, [r7, #16]
8001d92: f7fe ff3b bl 8000c0c <__aeabi_fdiv>
8001d96: 4603 mov r3, r0
}
8001d98: 4618 mov r0, r3
8001d9a: 3718 adds r7, #24
8001d9c: 46bd mov sp, r7
8001d9e: bd80 pop {r7, pc}
08001da0 <ADS1015_History_Average>:
/*
* Simple average of the history buffer (stage-2 sliding window)
*/
float ADS1015_History_Average(const float *hist, uint8_t n)
{
8001da0: b580 push {r7, lr}
8001da2: b084 sub sp, #16
8001da4: af00 add r7, sp, #0
8001da6: 6078 str r0, [r7, #4]
8001da8: 460b mov r3, r1
8001daa: 70fb strb r3, [r7, #3]
float sum = 0.0f;
8001dac: f04f 0300 mov.w r3, #0
8001db0: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
8001db2: 2300 movs r3, #0
8001db4: 72fb strb r3, [r7, #11]
8001db6: e00d b.n 8001dd4 <ADS1015_History_Average+0x34>
sum += hist[i];
8001db8: 7afb ldrb r3, [r7, #11]
8001dba: 009b lsls r3, r3, #2
8001dbc: 687a ldr r2, [r7, #4]
8001dbe: 4413 add r3, r2
8001dc0: 681b ldr r3, [r3, #0]
8001dc2: 4619 mov r1, r3
8001dc4: 68f8 ldr r0, [r7, #12]
8001dc6: f7fe fd65 bl 8000894 <__addsf3>
8001dca: 4603 mov r3, r0
8001dcc: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
8001dce: 7afb ldrb r3, [r7, #11]
8001dd0: 3301 adds r3, #1
8001dd2: 72fb strb r3, [r7, #11]
8001dd4: 7afa ldrb r2, [r7, #11]
8001dd6: 78fb ldrb r3, [r7, #3]
8001dd8: 429a cmp r2, r3
8001dda: d3ed bcc.n 8001db8 <ADS1015_History_Average+0x18>
return sum / (float)n;
8001ddc: 78fb ldrb r3, [r7, #3]
8001dde: 4618 mov r0, r3
8001de0: f7fe fe08 bl 80009f4 <__aeabi_ui2f>
8001de4: 4603 mov r3, r0
8001de6: 4619 mov r1, r3
8001de8: 68f8 ldr r0, [r7, #12]
8001dea: f7fe ff0f bl 8000c0c <__aeabi_fdiv>
8001dee: 4603 mov r3, r0
}
8001df0: 4618 mov r0, r3
8001df2: 3710 adds r7, #16
8001df4: 46bd mov sp, r7
8001df6: bd80 pop {r7, pc}
08001df8 <ADS1015_Process_Sample>:
* Common processing core: applied identically to all 3 channels.
* Receives the current raw reading and the channel's state (global
* arrays/struct).
**/
void ADS1015_Process_Sample(ADS1015_filter_t *ch, float raw)
{
8001df8: b590 push {r4, r7, lr}
8001dfa: b085 sub sp, #20
8001dfc: af00 add r7, sp, #0
8001dfe: 6078 str r0, [r7, #4]
8001e00: 6039 str r1, [r7, #0]
/* --- Stage 1: accumulate into the current burst --- */
ch->burst[ch->burst_index] = raw;
8001e02: 687b ldr r3, [r7, #4]
8001e04: 7d1b ldrb r3, [r3, #20]
8001e06: 4619 mov r1, r3
8001e08: 687b ldr r3, [r7, #4]
8001e0a: 683a ldr r2, [r7, #0]
8001e0c: f843 2021 str.w r2, [r3, r1, lsl #2]
ch->burst_index++;
8001e10: 687b ldr r3, [r7, #4]
8001e12: 7d1b ldrb r3, [r3, #20]
8001e14: 3301 adds r3, #1
8001e16: b2da uxtb r2, r3
8001e18: 687b ldr r3, [r7, #4]
8001e1a: 751a strb r2, [r3, #20]
if (ch->burst_index < ADS1015_BURST_SIZE)
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 7d1b ldrb r3, [r3, #20]
8001e20: 2b04 cmp r3, #4
8001e22: d97a bls.n 8001f1a <ADS1015_Process_Sample+0x122>
return; /* still collecting the burst, nothing else to do */
/* Burst complete: compute the trimmed mean */
float burst_result = ADS1015_Trimmed_Mean(ch->burst, ADS1015_BURST_SIZE, ADS1015_TRIM_COUNT);
8001e24: 687b ldr r3, [r7, #4]
8001e26: 2201 movs r2, #1
8001e28: 2105 movs r1, #5
8001e2a: 4618 mov r0, r3
8001e2c: f7ff ff72 bl 8001d14 <ADS1015_Trimmed_Mean>
8001e30: 60f8 str r0, [r7, #12]
ch->burst_index = 0; /* reset for the next burst */
8001e32: 687b ldr r3, [r7, #4]
8001e34: 2200 movs r2, #0
8001e36: 751a strb r2, [r3, #20]
/* --- Stage 2a: rolling history / sliding window --- */
ch->history[ch->history_index] = burst_result;
8001e38: 687b ldr r3, [r7, #4]
8001e3a: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
8001e3e: 461a mov r2, r3
8001e40: 687b ldr r3, [r7, #4]
8001e42: 3206 adds r2, #6
8001e44: 68f9 ldr r1, [r7, #12]
8001e46: f843 1022 str.w r1, [r3, r2, lsl #2]
ch->history_index = (uint8_t)((ch->history_index + 1) % ADS1015_HISTORY_SIZE);
8001e4a: 687b ldr r3, [r7, #4]
8001e4c: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
8001e50: 1c5a adds r2, r3, #1
8001e52: 4b34 ldr r3, [pc, #208] @ (8001f24 <ADS1015_Process_Sample+0x12c>)
8001e54: fb83 1302 smull r1, r3, r3, r2
8001e58: 1059 asrs r1, r3, #1
8001e5a: 17d3 asrs r3, r2, #31
8001e5c: 1ac9 subs r1, r1, r3
8001e5e: 460b mov r3, r1
8001e60: 009b lsls r3, r3, #2
8001e62: 440b add r3, r1
8001e64: 1ad1 subs r1, r2, r3
8001e66: b2ca uxtb r2, r1
8001e68: 687b ldr r3, [r7, #4]
8001e6a: f883 202c strb.w r2, [r3, #44] @ 0x2c
if (ch->history_count < ADS1015_HISTORY_SIZE)
8001e6e: 687b ldr r3, [r7, #4]
8001e70: f893 302d ldrb.w r3, [r3, #45] @ 0x2d
8001e74: 2b04 cmp r3, #4
8001e76: d807 bhi.n 8001e88 <ADS1015_Process_Sample+0x90>
ch->history_count++;
8001e78: 687b ldr r3, [r7, #4]
8001e7a: f893 302d ldrb.w r3, [r3, #45] @ 0x2d
8001e7e: 3301 adds r3, #1
8001e80: b2da uxtb r2, r3
8001e82: 687b ldr r3, [r7, #4]
8001e84: f883 202d strb.w r2, [r3, #45] @ 0x2d
float window_average = ADS1015_History_Average(ch->history, ch->history_count);
8001e88: 687b ldr r3, [r7, #4]
8001e8a: f103 0218 add.w r2, r3, #24
8001e8e: 687b ldr r3, [r7, #4]
8001e90: f893 302d ldrb.w r3, [r3, #45] @ 0x2d
8001e94: 4619 mov r1, r3
8001e96: 4610 mov r0, r2
8001e98: f7ff ff82 bl 8001da0 <ADS1015_History_Average>
8001e9c: 60b8 str r0, [r7, #8]
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
if (!ch->iir_initialized)
8001e9e: 687b ldr r3, [r7, #4]
8001ea0: f893 3034 ldrb.w r3, [r3, #52] @ 0x34
8001ea4: 2b00 cmp r3, #0
8001ea6: d107 bne.n 8001eb8 <ADS1015_Process_Sample+0xc0>
{
ch->iir_state = burst_result;
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 68fa ldr r2, [r7, #12]
8001eac: 631a str r2, [r3, #48] @ 0x30
ch->iir_initialized = 1;
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 2201 movs r2, #1
8001eb2: f883 2034 strb.w r2, [r3, #52] @ 0x34
8001eb6: e014 b.n 8001ee2 <ADS1015_Process_Sample+0xea>
}
else
{
ch->iir_state = ADS1015_IIR_ALPHA * burst_result + (1.0f - ADS1015_IIR_ALPHA) * ch->iir_state;
8001eb8: 491b ldr r1, [pc, #108] @ (8001f28 <ADS1015_Process_Sample+0x130>)
8001eba: 68f8 ldr r0, [r7, #12]
8001ebc: f7fe fdf2 bl 8000aa4 <__aeabi_fmul>
8001ec0: 4603 mov r3, r0
8001ec2: 461c mov r4, r3
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 6b1b ldr r3, [r3, #48] @ 0x30
8001ec8: 4918 ldr r1, [pc, #96] @ (8001f2c <ADS1015_Process_Sample+0x134>)
8001eca: 4618 mov r0, r3
8001ecc: f7fe fdea bl 8000aa4 <__aeabi_fmul>
8001ed0: 4603 mov r3, r0
8001ed2: 4619 mov r1, r3
8001ed4: 4620 mov r0, r4
8001ed6: f7fe fcdd bl 8000894 <__addsf3>
8001eda: 4603 mov r3, r0
8001edc: 461a mov r2, r3
8001ede: 687b ldr r3, [r7, #4]
8001ee0: 631a str r2, [r3, #48] @ 0x30
}
/* Final output: combines the IIR state (fast response to real drift)
* with the window average (more stable, slower response). Adjust
* the weighting per channel if needed. */
ch->filtered_value = 0.5f * ch->iir_state + 0.5f * window_average;
8001ee2: 687b ldr r3, [r7, #4]
8001ee4: 6b1b ldr r3, [r3, #48] @ 0x30
8001ee6: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
8001eea: 4618 mov r0, r3
8001eec: f7fe fdda bl 8000aa4 <__aeabi_fmul>
8001ef0: 4603 mov r3, r0
8001ef2: 461c mov r4, r3
8001ef4: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
8001ef8: 68b8 ldr r0, [r7, #8]
8001efa: f7fe fdd3 bl 8000aa4 <__aeabi_fmul>
8001efe: 4603 mov r3, r0
8001f00: 4619 mov r1, r3
8001f02: 4620 mov r0, r4
8001f04: f7fe fcc6 bl 8000894 <__addsf3>
8001f08: 4603 mov r3, r0
8001f0a: 461a mov r2, r3
8001f0c: 687b ldr r3, [r7, #4]
8001f0e: 639a str r2, [r3, #56] @ 0x38
ch->value_valid = 1;
8001f10: 687b ldr r3, [r7, #4]
8001f12: 2201 movs r2, #1
8001f14: f883 203c strb.w r2, [r3, #60] @ 0x3c
8001f18: e000 b.n 8001f1c <ADS1015_Process_Sample+0x124>
return; /* still collecting the burst, nothing else to do */
8001f1a: bf00 nop
}
8001f1c: 3714 adds r7, #20
8001f1e: 46bd mov sp, r7
8001f20: bd90 pop {r4, r7, pc}
8001f22: bf00 nop
8001f24: 66666667 .word 0x66666667
8001f28: 3f0ccccd .word 0x3f0ccccd
8001f2c: 3ee66666 .word 0x3ee66666
08001f30 <ADS1015_pH_NewSample>:
/* PUBLIC FUNCTIONS - ONE PER CHANNEL */
/* ---------------------------------------------------------------------- */
void ADS1015_pH_NewSample(float raw)
{
8001f30: b580 push {r7, lr}
8001f32: b082 sub sp, #8
8001f34: af00 add r7, sp, #0
8001f36: 6078 str r0, [r7, #4]
ADS1015_Process_Sample(&g_ph_filter, raw);
8001f38: 6879 ldr r1, [r7, #4]
8001f3a: 4803 ldr r0, [pc, #12] @ (8001f48 <ADS1015_pH_NewSample+0x18>)
8001f3c: f7ff ff5c bl 8001df8 <ADS1015_Process_Sample>
}
8001f40: bf00 nop
8001f42: 3708 adds r7, #8
8001f44: 46bd mov sp, r7
8001f46: bd80 pop {r7, pc}
8001f48: 200001c4 .word 0x200001c4
08001f4c <digital_outputs_init>:
* @brief Initializes the GPIO hardware and sets initial states.
* @note This function replaces the handle-based init.
* @retval None
*/
void digital_outputs_init(void)
{
8001f4c: b580 push {r7, lr}
8001f4e: b086 sub sp, #24
8001f50: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001f52: 1d3b adds r3, r7, #4
8001f54: 2200 movs r2, #0
8001f56: 601a str r2, [r3, #0]
8001f58: 605a str r2, [r3, #4]
8001f5a: 609a str r2, [r3, #8]
8001f5c: 60da str r2, [r3, #12]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001f5e: 2300 movs r3, #0
8001f60: 617b str r3, [r7, #20]
8001f62: e029 b.n 8001fb8 <digital_outputs_init+0x6c>
GPIO_InitStruct.Pin = output_pins[i].pin;
8001f64: 4a18 ldr r2, [pc, #96] @ (8001fc8 <digital_outputs_init+0x7c>)
8001f66: 697b ldr r3, [r7, #20]
8001f68: 00db lsls r3, r3, #3
8001f6a: 4413 add r3, r2
8001f6c: 889b ldrh r3, [r3, #4]
8001f6e: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain
8001f70: 2311 movs r3, #17
8001f72: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f74: 2300 movs r3, #0
8001f76: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f78: 2302 movs r3, #2
8001f7a: 613b str r3, [r7, #16]
HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
8001f7c: 4a12 ldr r2, [pc, #72] @ (8001fc8 <digital_outputs_init+0x7c>)
8001f7e: 697b ldr r3, [r7, #20]
8001f80: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8001f84: 1d3a adds r2, r7, #4
8001f86: 4611 mov r1, r2
8001f88: 4618 mov r0, r3
8001f8a: f001 fc63 bl 8003854 <HAL_GPIO_Init>
// Force initial state to LOW (Reset)
HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_SET);
8001f8e: 4a0e ldr r2, [pc, #56] @ (8001fc8 <digital_outputs_init+0x7c>)
8001f90: 697b ldr r3, [r7, #20]
8001f92: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8001f96: 4a0c ldr r2, [pc, #48] @ (8001fc8 <digital_outputs_init+0x7c>)
8001f98: 697b ldr r3, [r7, #20]
8001f9a: 00db lsls r3, r3, #3
8001f9c: 4413 add r3, r2
8001f9e: 889b ldrh r3, [r3, #4]
8001fa0: 2201 movs r2, #1
8001fa2: 4619 mov r1, r3
8001fa4: f001 fdf1 bl 8003b8a <HAL_GPIO_WritePin>
pin_states[i] = 0;
8001fa8: 4a08 ldr r2, [pc, #32] @ (8001fcc <digital_outputs_init+0x80>)
8001faa: 697b ldr r3, [r7, #20]
8001fac: 4413 add r3, r2
8001fae: 2200 movs r2, #0
8001fb0: 701a strb r2, [r3, #0]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001fb2: 697b ldr r3, [r7, #20]
8001fb4: 3301 adds r3, #1
8001fb6: 617b str r3, [r7, #20]
8001fb8: 697b ldr r3, [r7, #20]
8001fba: 2b07 cmp r3, #7
8001fbc: ddd2 ble.n 8001f64 <digital_outputs_init+0x18>
}
}
8001fbe: bf00 nop
8001fc0: bf00 nop
8001fc2: 3718 adds r7, #24
8001fc4: 46bd mov sp, r7
8001fc6: bd80 pop {r7, pc}
8001fc8: 08006be8 .word 0x08006be8
8001fcc: 20000210 .word 0x20000210
08001fd0 <digital_outputs_set_state>:
* @param pin Index of the pin (0 to OUTPUT_PINS_COUNT-1)
* @param state Desired state (0 = LOW, 1 = HIGH)
* @retval None
*/
void digital_outputs_set_state(digital_output_pin_t pin, uint8_t state)
{
8001fd0: b580 push {r7, lr}
8001fd2: b084 sub sp, #16
8001fd4: af00 add r7, sp, #0
8001fd6: 4603 mov r3, r0
8001fd8: 460a mov r2, r1
8001fda: 71fb strb r3, [r7, #7]
8001fdc: 4613 mov r3, r2
8001fde: 71bb strb r3, [r7, #6]
if (pin >= OUTPUT_PINS_COUNT) {
8001fe0: 79fb ldrb r3, [r7, #7]
8001fe2: 2b07 cmp r3, #7
8001fe4: d823 bhi.n 800202e <digital_outputs_set_state+0x5e>
return; // Simple boundary protection
}
GPIO_TypeDef* port = output_pins[pin].port;
8001fe6: 79fb ldrb r3, [r7, #7]
8001fe8: 4a13 ldr r2, [pc, #76] @ (8002038 <digital_outputs_set_state+0x68>)
8001fea: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8001fee: 60fb str r3, [r7, #12]
uint16_t pin_mask = output_pins[pin].pin;
8001ff0: 79fb ldrb r3, [r7, #7]
8001ff2: 4a11 ldr r2, [pc, #68] @ (8002038 <digital_outputs_set_state+0x68>)
8001ff4: 00db lsls r3, r3, #3
8001ff6: 4413 add r3, r2
8001ff8: 889b ldrh r3, [r3, #4]
8001ffa: 817b strh r3, [r7, #10]
if (state) {
8001ffc: 79bb ldrb r3, [r7, #6]
8001ffe: 2b00 cmp r3, #0
8002000: d00a beq.n 8002018 <digital_outputs_set_state+0x48>
HAL_GPIO_WritePin(port, pin_mask, GPIO_PIN_RESET);
8002002: 897b ldrh r3, [r7, #10]
8002004: 2200 movs r2, #0
8002006: 4619 mov r1, r3
8002008: 68f8 ldr r0, [r7, #12]
800200a: f001 fdbe bl 8003b8a <HAL_GPIO_WritePin>
pin_states[pin] = 1;
800200e: 79fb ldrb r3, [r7, #7]
8002010: 4a0a ldr r2, [pc, #40] @ (800203c <digital_outputs_set_state+0x6c>)
8002012: 2101 movs r1, #1
8002014: 54d1 strb r1, [r2, r3]
8002016: e00b b.n 8002030 <digital_outputs_set_state+0x60>
} else {
HAL_GPIO_WritePin(port, pin_mask, GPIO_PIN_SET);
8002018: 897b ldrh r3, [r7, #10]
800201a: 2201 movs r2, #1
800201c: 4619 mov r1, r3
800201e: 68f8 ldr r0, [r7, #12]
8002020: f001 fdb3 bl 8003b8a <HAL_GPIO_WritePin>
pin_states[pin] = 0;
8002024: 79fb ldrb r3, [r7, #7]
8002026: 4a05 ldr r2, [pc, #20] @ (800203c <digital_outputs_set_state+0x6c>)
8002028: 2100 movs r1, #0
800202a: 54d1 strb r1, [r2, r3]
800202c: e000 b.n 8002030 <digital_outputs_set_state+0x60>
return; // Simple boundary protection
800202e: bf00 nop
}
}
8002030: 3710 adds r7, #16
8002032: 46bd mov sp, r7
8002034: bd80 pop {r7, pc}
8002036: bf00 nop
8002038: 08006be8 .word 0x08006be8
800203c: 20000210 .word 0x20000210
08002040 <digital_outputs_toggle>:
* @brief Toggles the state of a specific output pin.
* @param pin Index of the pin
* @retval None
*/
void digital_outputs_toggle(digital_output_pin_t pin)
{
8002040: b580 push {r7, lr}
8002042: b084 sub sp, #16
8002044: af00 add r7, sp, #0
8002046: 4603 mov r3, r0
8002048: 71fb strb r3, [r7, #7]
if (pin < OUTPUT_PINS_COUNT) {
800204a: 79fb ldrb r3, [r7, #7]
800204c: 2b07 cmp r3, #7
800204e: d80e bhi.n 800206e <digital_outputs_toggle+0x2e>
// Simple toggle logic using the internal state array
uint8_t new_state = !pin_states[pin];
8002050: 79fb ldrb r3, [r7, #7]
8002052: 4a09 ldr r2, [pc, #36] @ (8002078 <digital_outputs_toggle+0x38>)
8002054: 5cd3 ldrb r3, [r2, r3]
8002056: 2b00 cmp r3, #0
8002058: bf0c ite eq
800205a: 2301 moveq r3, #1
800205c: 2300 movne r3, #0
800205e: b2db uxtb r3, r3
8002060: 73fb strb r3, [r7, #15]
digital_outputs_set_state(pin, new_state);
8002062: 7bfa ldrb r2, [r7, #15]
8002064: 79fb ldrb r3, [r7, #7]
8002066: 4611 mov r1, r2
8002068: 4618 mov r0, r3
800206a: f7ff ffb1 bl 8001fd0 <digital_outputs_set_state>
}
}
800206e: bf00 nop
8002070: 3710 adds r7, #16
8002072: 46bd mov sp, r7
8002074: bd80 pop {r7, pc}
8002076: bf00 nop
8002078: 20000210 .word 0x20000210
0800207c <MX_GPIO_Init>:
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
800207c: b580 push {r7, lr}
800207e: b088 sub sp, #32
8002080: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002082: f107 0310 add.w r3, r7, #16
8002086: 2200 movs r2, #0
8002088: 601a str r2, [r3, #0]
800208a: 605a str r2, [r3, #4]
800208c: 609a str r2, [r3, #8]
800208e: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8002090: 4b46 ldr r3, [pc, #280] @ (80021ac <MX_GPIO_Init+0x130>)
8002092: 699b ldr r3, [r3, #24]
8002094: 4a45 ldr r2, [pc, #276] @ (80021ac <MX_GPIO_Init+0x130>)
8002096: f043 0310 orr.w r3, r3, #16
800209a: 6193 str r3, [r2, #24]
800209c: 4b43 ldr r3, [pc, #268] @ (80021ac <MX_GPIO_Init+0x130>)
800209e: 699b ldr r3, [r3, #24]
80020a0: f003 0310 and.w r3, r3, #16
80020a4: 60fb str r3, [r7, #12]
80020a6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
80020a8: 4b40 ldr r3, [pc, #256] @ (80021ac <MX_GPIO_Init+0x130>)
80020aa: 699b ldr r3, [r3, #24]
80020ac: 4a3f ldr r2, [pc, #252] @ (80021ac <MX_GPIO_Init+0x130>)
80020ae: f043 0320 orr.w r3, r3, #32
80020b2: 6193 str r3, [r2, #24]
80020b4: 4b3d ldr r3, [pc, #244] @ (80021ac <MX_GPIO_Init+0x130>)
80020b6: 699b ldr r3, [r3, #24]
80020b8: f003 0320 and.w r3, r3, #32
80020bc: 60bb str r3, [r7, #8]
80020be: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80020c0: 4b3a ldr r3, [pc, #232] @ (80021ac <MX_GPIO_Init+0x130>)
80020c2: 699b ldr r3, [r3, #24]
80020c4: 4a39 ldr r2, [pc, #228] @ (80021ac <MX_GPIO_Init+0x130>)
80020c6: f043 0304 orr.w r3, r3, #4
80020ca: 6193 str r3, [r2, #24]
80020cc: 4b37 ldr r3, [pc, #220] @ (80021ac <MX_GPIO_Init+0x130>)
80020ce: 699b ldr r3, [r3, #24]
80020d0: f003 0304 and.w r3, r3, #4
80020d4: 607b str r3, [r7, #4]
80020d6: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80020d8: 4b34 ldr r3, [pc, #208] @ (80021ac <MX_GPIO_Init+0x130>)
80020da: 699b ldr r3, [r3, #24]
80020dc: 4a33 ldr r2, [pc, #204] @ (80021ac <MX_GPIO_Init+0x130>)
80020de: f043 0308 orr.w r3, r3, #8
80020e2: 6193 str r3, [r2, #24]
80020e4: 4b31 ldr r3, [pc, #196] @ (80021ac <MX_GPIO_Init+0x130>)
80020e6: 699b ldr r3, [r3, #24]
80020e8: f003 0308 and.w r3, r3, #8
80020ec: 603b str r3, [r7, #0]
80020ee: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
80020f0: 2200 movs r2, #0
80020f2: f44f 4160 mov.w r1, #57344 @ 0xe000
80020f6: 482e ldr r0, [pc, #184] @ (80021b0 <MX_GPIO_Init+0x134>)
80020f8: f001 fd47 bl 8003b8a <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
80020fc: 2200 movs r2, #0
80020fe: f240 3137 movw r1, #823 @ 0x337
8002102: 482c ldr r0, [pc, #176] @ (80021b4 <MX_GPIO_Init+0x138>)
8002104: f001 fd41 bl 8003b8a <HAL_GPIO_WritePin>
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
8002108: 2200 movs r2, #0
800210a: f44f 5180 mov.w r1, #4096 @ 0x1000
800210e: 482a ldr r0, [pc, #168] @ (80021b8 <MX_GPIO_Init+0x13c>)
8002110: f001 fd3b bl 8003b8a <HAL_GPIO_WritePin>
/*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
8002114: f44f 4360 mov.w r3, #57344 @ 0xe000
8002118: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
800211a: 2311 movs r3, #17
800211c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800211e: 2300 movs r3, #0
8002120: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002122: 2302 movs r3, #2
8002124: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8002126: f107 0310 add.w r3, r7, #16
800212a: 4619 mov r1, r3
800212c: 4820 ldr r0, [pc, #128] @ (80021b0 <MX_GPIO_Init+0x134>)
800212e: f001 fb91 bl 8003854 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
PG_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
8002132: f648 13fc movw r3, #35324 @ 0x89fc
8002136: 613b str r3, [r7, #16]
|SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
|PG_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002138: 2300 movs r3, #0
800213a: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800213c: 2301 movs r3, #1
800213e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002140: f107 0310 add.w r3, r7, #16
8002144: 4619 mov r1, r3
8002146: 481c ldr r0, [pc, #112] @ (80021b8 <MX_GPIO_Init+0x13c>)
8002148: f001 fb84 bl 8003854 <HAL_GPIO_Init>
/*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
800214c: f240 3337 movw r3, #823 @ 0x337
8002150: 613b str r3, [r7, #16]
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8002152: 2311 movs r3, #17
8002154: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002156: 2300 movs r3, #0
8002158: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800215a: 2302 movs r3, #2
800215c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800215e: f107 0310 add.w r3, r7, #16
8002162: 4619 mov r1, r3
8002164: 4813 ldr r0, [pc, #76] @ (80021b4 <MX_GPIO_Init+0x138>)
8002166: f001 fb75 bl 8003854 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin
Calib_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin
800216a: f24f 0308 movw r3, #61448 @ 0xf008
800216e: 613b str r3, [r7, #16]
|Calib_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002170: 2300 movs r3, #0
8002172: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002174: 2301 movs r3, #1
8002176: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002178: f107 0310 add.w r3, r7, #16
800217c: 4619 mov r1, r3
800217e: 480d ldr r0, [pc, #52] @ (80021b4 <MX_GPIO_Init+0x138>)
8002180: f001 fb68 bl 8003854 <HAL_GPIO_Init>
/*Configure GPIO pin : TX_EN_RS485_Pin */
GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
8002184: f44f 5380 mov.w r3, #4096 @ 0x1000
8002188: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800218a: 2301 movs r3, #1
800218c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800218e: 2300 movs r3, #0
8002190: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002192: 2302 movs r3, #2
8002194: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
8002196: f107 0310 add.w r3, r7, #16
800219a: 4619 mov r1, r3
800219c: 4806 ldr r0, [pc, #24] @ (80021b8 <MX_GPIO_Init+0x13c>)
800219e: f001 fb59 bl 8003854 <HAL_GPIO_Init>
}
80021a2: bf00 nop
80021a4: 3720 adds r7, #32
80021a6: 46bd mov sp, r7
80021a8: bd80 pop {r7, pc}
80021aa: bf00 nop
80021ac: 40021000 .word 0x40021000
80021b0: 40011000 .word 0x40011000
80021b4: 40010c00 .word 0x40010c00
80021b8: 40010800 .word 0x40010800
080021bc <MX_I2C1_Init>:
I2C_HandleTypeDef hi2c1;
I2C_HandleTypeDef hi2c2;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
80021bc: b580 push {r7, lr}
80021be: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
80021c0: 4b12 ldr r3, [pc, #72] @ (800220c <MX_I2C1_Init+0x50>)
80021c2: 4a13 ldr r2, [pc, #76] @ (8002210 <MX_I2C1_Init+0x54>)
80021c4: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
80021c6: 4b11 ldr r3, [pc, #68] @ (800220c <MX_I2C1_Init+0x50>)
80021c8: 4a12 ldr r2, [pc, #72] @ (8002214 <MX_I2C1_Init+0x58>)
80021ca: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
80021cc: 4b0f ldr r3, [pc, #60] @ (800220c <MX_I2C1_Init+0x50>)
80021ce: 2200 movs r2, #0
80021d0: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
80021d2: 4b0e ldr r3, [pc, #56] @ (800220c <MX_I2C1_Init+0x50>)
80021d4: 2200 movs r2, #0
80021d6: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80021d8: 4b0c ldr r3, [pc, #48] @ (800220c <MX_I2C1_Init+0x50>)
80021da: f44f 4280 mov.w r2, #16384 @ 0x4000
80021de: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80021e0: 4b0a ldr r3, [pc, #40] @ (800220c <MX_I2C1_Init+0x50>)
80021e2: 2200 movs r2, #0
80021e4: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
80021e6: 4b09 ldr r3, [pc, #36] @ (800220c <MX_I2C1_Init+0x50>)
80021e8: 2200 movs r2, #0
80021ea: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80021ec: 4b07 ldr r3, [pc, #28] @ (800220c <MX_I2C1_Init+0x50>)
80021ee: 2200 movs r2, #0
80021f0: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80021f2: 4b06 ldr r3, [pc, #24] @ (800220c <MX_I2C1_Init+0x50>)
80021f4: 2200 movs r2, #0
80021f6: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
80021f8: 4804 ldr r0, [pc, #16] @ (800220c <MX_I2C1_Init+0x50>)
80021fa: f001 fcf7 bl 8003bec <HAL_I2C_Init>
80021fe: 4603 mov r3, r0
8002200: 2b00 cmp r3, #0
8002202: d001 beq.n 8002208 <MX_I2C1_Init+0x4c>
{
Error_Handler();
8002204: f000 fc44 bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8002208: bf00 nop
800220a: bd80 pop {r7, pc}
800220c: 20000218 .word 0x20000218
8002210: 40005400 .word 0x40005400
8002214: 000186a0 .word 0x000186a0
08002218 <MX_I2C2_Init>:
/* I2C2 init function */
void MX_I2C2_Init(void)
{
8002218: b580 push {r7, lr}
800221a: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
800221c: 4b12 ldr r3, [pc, #72] @ (8002268 <MX_I2C2_Init+0x50>)
800221e: 4a13 ldr r2, [pc, #76] @ (800226c <MX_I2C2_Init+0x54>)
8002220: 601a str r2, [r3, #0]
hi2c2.Init.ClockSpeed = 100000;
8002222: 4b11 ldr r3, [pc, #68] @ (8002268 <MX_I2C2_Init+0x50>)
8002224: 4a12 ldr r2, [pc, #72] @ (8002270 <MX_I2C2_Init+0x58>)
8002226: 605a str r2, [r3, #4]
hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
8002228: 4b0f ldr r3, [pc, #60] @ (8002268 <MX_I2C2_Init+0x50>)
800222a: 2200 movs r2, #0
800222c: 609a str r2, [r3, #8]
hi2c2.Init.OwnAddress1 = 0;
800222e: 4b0e ldr r3, [pc, #56] @ (8002268 <MX_I2C2_Init+0x50>)
8002230: 2200 movs r2, #0
8002232: 60da str r2, [r3, #12]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8002234: 4b0c ldr r3, [pc, #48] @ (8002268 <MX_I2C2_Init+0x50>)
8002236: f44f 4280 mov.w r2, #16384 @ 0x4000
800223a: 611a str r2, [r3, #16]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800223c: 4b0a ldr r3, [pc, #40] @ (8002268 <MX_I2C2_Init+0x50>)
800223e: 2200 movs r2, #0
8002240: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2 = 0;
8002242: 4b09 ldr r3, [pc, #36] @ (8002268 <MX_I2C2_Init+0x50>)
8002244: 2200 movs r2, #0
8002246: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8002248: 4b07 ldr r3, [pc, #28] @ (8002268 <MX_I2C2_Init+0x50>)
800224a: 2200 movs r2, #0
800224c: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800224e: 4b06 ldr r3, [pc, #24] @ (8002268 <MX_I2C2_Init+0x50>)
8002250: 2200 movs r2, #0
8002252: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
8002254: 4804 ldr r0, [pc, #16] @ (8002268 <MX_I2C2_Init+0x50>)
8002256: f001 fcc9 bl 8003bec <HAL_I2C_Init>
800225a: 4603 mov r3, r0
800225c: 2b00 cmp r3, #0
800225e: d001 beq.n 8002264 <MX_I2C2_Init+0x4c>
{
Error_Handler();
8002260: f000 fc16 bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
8002264: bf00 nop
8002266: bd80 pop {r7, pc}
8002268: 2000026c .word 0x2000026c
800226c: 40005800 .word 0x40005800
8002270: 000186a0 .word 0x000186a0
08002274 <HAL_I2C_MspInit>:
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
8002274: b580 push {r7, lr}
8002276: b08a sub sp, #40 @ 0x28
8002278: af00 add r7, sp, #0
800227a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800227c: f107 0318 add.w r3, r7, #24
8002280: 2200 movs r2, #0
8002282: 601a str r2, [r3, #0]
8002284: 605a str r2, [r3, #4]
8002286: 609a str r2, [r3, #8]
8002288: 60da str r2, [r3, #12]
if(i2cHandle->Instance==I2C1)
800228a: 687b ldr r3, [r7, #4]
800228c: 681b ldr r3, [r3, #0]
800228e: 4a2b ldr r2, [pc, #172] @ (800233c <HAL_I2C_MspInit+0xc8>)
8002290: 4293 cmp r3, r2
8002292: d124 bne.n 80022de <HAL_I2C_MspInit+0x6a>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8002294: 4b2a ldr r3, [pc, #168] @ (8002340 <HAL_I2C_MspInit+0xcc>)
8002296: 699b ldr r3, [r3, #24]
8002298: 4a29 ldr r2, [pc, #164] @ (8002340 <HAL_I2C_MspInit+0xcc>)
800229a: f043 0308 orr.w r3, r3, #8
800229e: 6193 str r3, [r2, #24]
80022a0: 4b27 ldr r3, [pc, #156] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022a2: 699b ldr r3, [r3, #24]
80022a4: f003 0308 and.w r3, r3, #8
80022a8: 617b str r3, [r7, #20]
80022aa: 697b ldr r3, [r7, #20]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
80022ac: 23c0 movs r3, #192 @ 0xc0
80022ae: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80022b0: 2312 movs r3, #18
80022b2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80022b4: 2302 movs r3, #2
80022b6: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80022b8: f107 0318 add.w r3, r7, #24
80022bc: 4619 mov r1, r3
80022be: 4821 ldr r0, [pc, #132] @ (8002344 <HAL_I2C_MspInit+0xd0>)
80022c0: f001 fac8 bl 8003854 <HAL_GPIO_Init>
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
80022c4: 4b1e ldr r3, [pc, #120] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022c6: 69db ldr r3, [r3, #28]
80022c8: 4a1d ldr r2, [pc, #116] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022ca: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
80022ce: 61d3 str r3, [r2, #28]
80022d0: 4b1b ldr r3, [pc, #108] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022d2: 69db ldr r3, [r3, #28]
80022d4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80022d8: 613b str r3, [r7, #16]
80022da: 693b ldr r3, [r7, #16]
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
}
80022dc: e029 b.n 8002332 <HAL_I2C_MspInit+0xbe>
else if(i2cHandle->Instance==I2C2)
80022de: 687b ldr r3, [r7, #4]
80022e0: 681b ldr r3, [r3, #0]
80022e2: 4a19 ldr r2, [pc, #100] @ (8002348 <HAL_I2C_MspInit+0xd4>)
80022e4: 4293 cmp r3, r2
80022e6: d124 bne.n 8002332 <HAL_I2C_MspInit+0xbe>
__HAL_RCC_GPIOB_CLK_ENABLE();
80022e8: 4b15 ldr r3, [pc, #84] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022ea: 699b ldr r3, [r3, #24]
80022ec: 4a14 ldr r2, [pc, #80] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022ee: f043 0308 orr.w r3, r3, #8
80022f2: 6193 str r3, [r2, #24]
80022f4: 4b12 ldr r3, [pc, #72] @ (8002340 <HAL_I2C_MspInit+0xcc>)
80022f6: 699b ldr r3, [r3, #24]
80022f8: f003 0308 and.w r3, r3, #8
80022fc: 60fb str r3, [r7, #12]
80022fe: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
8002300: f44f 6340 mov.w r3, #3072 @ 0xc00
8002304: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8002306: 2312 movs r3, #18
8002308: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800230a: 2302 movs r3, #2
800230c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800230e: f107 0318 add.w r3, r7, #24
8002312: 4619 mov r1, r3
8002314: 480b ldr r0, [pc, #44] @ (8002344 <HAL_I2C_MspInit+0xd0>)
8002316: f001 fa9d bl 8003854 <HAL_GPIO_Init>
__HAL_RCC_I2C2_CLK_ENABLE();
800231a: 4b09 ldr r3, [pc, #36] @ (8002340 <HAL_I2C_MspInit+0xcc>)
800231c: 69db ldr r3, [r3, #28]
800231e: 4a08 ldr r2, [pc, #32] @ (8002340 <HAL_I2C_MspInit+0xcc>)
8002320: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002324: 61d3 str r3, [r2, #28]
8002326: 4b06 ldr r3, [pc, #24] @ (8002340 <HAL_I2C_MspInit+0xcc>)
8002328: 69db ldr r3, [r3, #28]
800232a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800232e: 60bb str r3, [r7, #8]
8002330: 68bb ldr r3, [r7, #8]
}
8002332: bf00 nop
8002334: 3728 adds r7, #40 @ 0x28
8002336: 46bd mov sp, r7
8002338: bd80 pop {r7, pc}
800233a: bf00 nop
800233c: 40005400 .word 0x40005400
8002340: 40021000 .word 0x40021000
8002344: 40010c00 .word 0x40010c00
8002348: 40005800 .word 0x40005800
0800234c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800234c: b5b0 push {r4, r5, r7, lr}
800234e: b08e sub sp, #56 @ 0x38
8002350: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
uint8_t tempString[15] = {0};
8002352: f107 0308 add.w r3, r7, #8
8002356: 2200 movs r2, #0
8002358: 601a str r2, [r3, #0]
800235a: 605a str r2, [r3, #4]
800235c: 609a str r2, [r3, #8]
800235e: f8c3 200b str.w r2, [r3, #11]
uint8_t averages = 0;
8002362: 2300 movs r3, #0
8002364: f887 3033 strb.w r3, [r7, #51] @ 0x33
uint8_t newline = '\n';
8002368: 230a movs r3, #10
800236a: 71fb strb r3, [r7, #7]
// Variables for timing
uint32_t previous_millis_green = 0;
800236c: 2300 movs r3, #0
800236e: 637b str r3, [r7, #52] @ 0x34
uint32_t previous_millis_red = 0;
8002370: 2300 movs r3, #0
8002372: 62fb str r3, [r7, #44] @ 0x2c
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8002374: f000 fe16 bl 8002fa4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8002378: f000 f942 bl 8002600 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800237c: f7ff fe7e bl 800207c <MX_GPIO_Init>
MX_ADC1_Init();
8002380: f7ff fa66 bl 8001850 <MX_ADC1_Init>
MX_ADC2_Init();
8002384: f7ff faa2 bl 80018cc <MX_ADC2_Init>
MX_I2C1_Init();
8002388: f7ff ff18 bl 80021bc <MX_I2C1_Init>
MX_I2C2_Init();
800238c: f7ff ff44 bl 8002218 <MX_I2C2_Init>
MX_USART1_UART_Init();
8002390: f000 fd64 bl 8002e5c <MX_USART1_UART_Init>
MX_TIM3_Init();
8002394: f000 fcee bl 8002d74 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
HAL_TIM_Base_Start_IT(&htim3);
8002398: 488e ldr r0, [pc, #568] @ (80025d4 <main+0x288>)
800239a: f003 f973 bl 8005684 <HAL_TIM_Base_Start_IT>
//AD5934_MovingAvg_Init (&g_rtd_filter);
//AD5934_MovingAvg_Init (&g_ref_filter);
//AD5934_MovingAvg_Init (&g_ec_filter);
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off
800239e: 2201 movs r2, #1
80023a0: 2110 movs r1, #16
80023a2: 488d ldr r0, [pc, #564] @ (80025d8 <main+0x28c>)
80023a4: f001 fbf1 bl 8003b8a <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off
80023a8: 2201 movs r2, #1
80023aa: 2120 movs r1, #32
80023ac: 488a ldr r0, [pc, #552] @ (80025d8 <main+0x28c>)
80023ae: f001 fbec bl 8003b8a <HAL_GPIO_WritePin>
digital_outputs_init();
80023b2: f7ff fdcb bl 8001f4c <digital_outputs_init>
rs485_init();
80023b6: f000 fb7d bl 8002ab4 <rs485_init>
ADG715_ResetChannels();
80023ba: f7ff fa2b bl 8001814 <ADG715_ResetChannels>
ADS1015_Init(); // Initializes pH Measurement
80023be: f7ff fb75 bl 8001aac <ADS1015_Init>
AD5934_Init(); // Initializes CE and RTD Measurement
80023c2: f7fe fe0b bl 8000fdc <AD5934_Init>
averages++;
}
}
}
*/
digital_outputs_toggle(0);
80023c6: 2000 movs r0, #0
80023c8: f7ff fe3a bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(1);
80023cc: 2001 movs r0, #1
80023ce: f7ff fe37 bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(2);
80023d2: 2002 movs r0, #2
80023d4: f7ff fe34 bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(3);
80023d8: 2003 movs r0, #3
80023da: f7ff fe31 bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(4);
80023de: 2004 movs r0, #4
80023e0: f7ff fe2e bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(5);
80023e4: 2005 movs r0, #5
80023e6: f7ff fe2b bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(6);
80023ea: 2006 movs r0, #6
80023ec: f7ff fe28 bl 8002040 <digital_outputs_toggle>
digital_outputs_toggle(7);
80023f0: 2007 movs r0, #7
80023f2: f7ff fe25 bl 8002040 <digital_outputs_toggle>
while (1)
{
AD5934_Process_System();
80023f6: f7fe ff23 bl 8001240 <AD5934_Process_System>
ADS1015_Process_System();
80023fa: f7ff fbb5 bl 8001b68 <ADS1015_Process_System>
current_millis = g_ms_counter;
80023fe: 4b77 ldr r3, [pc, #476] @ (80025dc <main+0x290>)
8002400: 681b ldr r3, [r3, #0]
8002402: 62bb str r3, [r7, #40] @ 0x28
if((current_millis % 500) == 0) // Send data each 100ms
8002404: 6aba ldr r2, [r7, #40] @ 0x28
8002406: 4b76 ldr r3, [pc, #472] @ (80025e0 <main+0x294>)
8002408: fba3 1302 umull r1, r3, r3, r2
800240c: 095b lsrs r3, r3, #5
800240e: f44f 71fa mov.w r1, #500 @ 0x1f4
8002412: fb01 f303 mul.w r3, r1, r3
8002416: 1ad3 subs r3, r2, r3
8002418: 2b00 cmp r3, #0
800241a: f040 80cc bne.w 80025b6 <main+0x26a>
{
//if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms
//{
mag_reference = g_ref_filter.filtered_value;
800241e: 4b71 ldr r3, [pc, #452] @ (80025e4 <main+0x298>)
8002420: 6b5b ldr r3, [r3, #52] @ 0x34
8002422: 627b str r3, [r7, #36] @ 0x24
//reference_resistor = g_ref_filter.filtered_value;
//uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, current_ref_mux);
//intToStr(reference_final, tempString);
//ref_final = g_ref_filter.filtered_value;
FloatToString(tempString, mag_reference);
8002424: 6a78 ldr r0, [r7, #36] @ 0x24
8002426: f7fe f927 bl 8000678 <__aeabi_f2d>
800242a: 4602 mov r2, r0
800242c: 460b mov r3, r1
800242e: f107 0108 add.w r1, r7, #8
8002432: 4608 mov r0, r1
8002434: f000 f934 bl 80026a0 <FloatToString>
//Convert2Hex(ref_now, tempString);
//intToStr(ref_now, tempString);
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
8002438: f107 0308 add.w r3, r7, #8
800243c: 4618 mov r0, r3
800243e: f7fd fe85 bl 800014c <strlen>
8002442: 4603 mov r3, r0
8002444: b29a uxth r2, r3
8002446: f107 0308 add.w r3, r7, #8
800244a: 4611 mov r1, r2
800244c: 4618 mov r0, r3
800244e: f000 fb5d bl 8002b0c <rs485_send_broadcast>
//intToStr(ref_now_i, tempString);
//rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
rs485_send_broadcast(&newline, 1);
8002452: 1dfb adds r3, r7, #7
8002454: 2101 movs r1, #1
8002456: 4618 mov r0, r3
8002458: f000 fb58 bl 8002b0c <rs485_send_broadcast>
//}
//if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C
//{
//mag_rtd = (float)rtd_now;
mag_rtd = g_rtd_filter.filtered_value;
800245c: 4b62 ldr r3, [pc, #392] @ (80025e8 <main+0x29c>)
800245e: 6b5b ldr r3, [r3, #52] @ 0x34
8002460: 623b str r3, [r7, #32]
//mag_rtd = sqrtf((g_rtd_real_filter.average * g_rtd_real_filter.average)+(g_rtd_imag_filter.average * g_rtd_imag_filter.average));
//mag_rtd = sqrtf(((float)rtd_now * (float)rtd_now) + ((float)rtd_now_i * (float)rtd_now_i));
//temperature_RTD = AD5934_Calculate_Temperature(mag_reference, mag_rtd);
temperature_RTD = AD5934_Calculate_Temperature(mag_reference,mag_rtd);// AD5934_GetImpedance(mag_reference,mag_rtd);//
8002462: 6a39 ldr r1, [r7, #32]
8002464: 6a78 ldr r0, [r7, #36] @ 0x24
8002466: f7fe fe05 bl 8001074 <AD5934_Calculate_Temperature>
800246a: 4603 mov r3, r0
800246c: 4a5f ldr r2, [pc, #380] @ (80025ec <main+0x2a0>)
800246e: 6013 str r3, [r2, #0]
//uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, current_rtd_mux);
//uint16_t rtd_final = AD5934_Compress_To_IntScale(temperature_RTD, current_rtd_mux);
//intToStr(rtd_final, tempString);
//float rtd_final = g_rtd_filter.filtered_value; //g_rtd_filter.filtered_value;
FloatToString(tempString, temperature_RTD);
8002470: 4b5e ldr r3, [pc, #376] @ (80025ec <main+0x2a0>)
8002472: 681b ldr r3, [r3, #0]
8002474: 4618 mov r0, r3
8002476: f7fe f8ff bl 8000678 <__aeabi_f2d>
800247a: 4602 mov r2, r0
800247c: 460b mov r3, r1
800247e: f107 0108 add.w r1, r7, #8
8002482: 4608 mov r0, r1
8002484: f000 f90c bl 80026a0 <FloatToString>
//Convert2Hex(rtd_now, tempString);
//intToStr(rtd_now, tempString);
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
8002488: f107 0308 add.w r3, r7, #8
800248c: 4618 mov r0, r3
800248e: f7fd fe5d bl 800014c <strlen>
8002492: 4603 mov r3, r0
8002494: b29a uxth r2, r3
8002496: f107 0308 add.w r3, r7, #8
800249a: 4611 mov r1, r2
800249c: 4618 mov r0, r3
800249e: f000 fb35 bl 8002b0c <rs485_send_broadcast>
//Convert2Hex(rtd_now_i, tempString);
//intToStr(rtd_now_i, tempString);
//rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
rs485_send_broadcast(&newline, 1);
80024a2: 1dfb adds r3, r7, #7
80024a4: 2101 movs r1, #1
80024a6: 4618 mov r0, r3
80024a8: f000 fb30 bl 8002b0c <rs485_send_broadcast>
}*/
//if (g_ec_filter.value_valid) // EC
//{
//mag_ec = sqrtf((g_ec_real_filter.filtered_value * g_ec_real_filter.filtered_value)+(g_ec_imag_filter.filtered_value * g_ec_imag_filter.filtered_value));
mag_ec = sqrtf(((float)ec_now * (float)ec_now) + ((float)ec_now_i * (float)ec_now_i));
80024ac: 4b50 ldr r3, [pc, #320] @ (80025f0 <main+0x2a4>)
80024ae: f9b3 3000 ldrsh.w r3, [r3]
80024b2: 4618 mov r0, r3
80024b4: f7fe faa2 bl 80009fc <__aeabi_i2f>
80024b8: 4604 mov r4, r0
80024ba: 4b4d ldr r3, [pc, #308] @ (80025f0 <main+0x2a4>)
80024bc: f9b3 3000 ldrsh.w r3, [r3]
80024c0: 4618 mov r0, r3
80024c2: f7fe fa9b bl 80009fc <__aeabi_i2f>
80024c6: 4603 mov r3, r0
80024c8: 4619 mov r1, r3
80024ca: 4620 mov r0, r4
80024cc: f7fe faea bl 8000aa4 <__aeabi_fmul>
80024d0: 4603 mov r3, r0
80024d2: 461d mov r5, r3
80024d4: 4b47 ldr r3, [pc, #284] @ (80025f4 <main+0x2a8>)
80024d6: f9b3 3000 ldrsh.w r3, [r3]
80024da: 4618 mov r0, r3
80024dc: f7fe fa8e bl 80009fc <__aeabi_i2f>
80024e0: 4604 mov r4, r0
80024e2: 4b44 ldr r3, [pc, #272] @ (80025f4 <main+0x2a8>)
80024e4: f9b3 3000 ldrsh.w r3, [r3]
80024e8: 4618 mov r0, r3
80024ea: f7fe fa87 bl 80009fc <__aeabi_i2f>
80024ee: 4603 mov r3, r0
80024f0: 4619 mov r1, r3
80024f2: 4620 mov r0, r4
80024f4: f7fe fad6 bl 8000aa4 <__aeabi_fmul>
80024f8: 4603 mov r3, r0
80024fa: 4619 mov r1, r3
80024fc: 4628 mov r0, r5
80024fe: f7fe f9c9 bl 8000894 <__addsf3>
8002502: 4603 mov r3, r0
8002504: 4618 mov r0, r3
8002506: f004 faa7 bl 8006a58 <sqrtf>
800250a: 61f8 str r0, [r7, #28]
thermal_compensaded_EC = AD5934_EC_Compensate_Magnitude_To_25C(mag_ec, temperature_RTD);
800250c: 4b37 ldr r3, [pc, #220] @ (80025ec <main+0x2a0>)
800250e: 681b ldr r3, [r3, #0]
8002510: 4619 mov r1, r3
8002512: 69f8 ldr r0, [r7, #28]
8002514: f7fe fe2a bl 800116c <AD5934_EC_Compensate_Magnitude_To_25C>
8002518: 4603 mov r3, r0
800251a: 4a37 ldr r2, [pc, #220] @ (80025f8 <main+0x2ac>)
800251c: 6013 str r3, [r2, #0]
//uint16_t ec_final = AD5934_Compress_To_IntScale(thermal_compensaded_EC, current_ec_mux);
//intToStr(ec_now, tempString);
// float ec_final = g_ec_filter.filtered_value;
FloatToString(tempString, mag_ec);
800251e: 69f8 ldr r0, [r7, #28]
8002520: f7fe f8aa bl 8000678 <__aeabi_f2d>
8002524: 4602 mov r2, r0
8002526: 460b mov r3, r1
8002528: f107 0108 add.w r1, r7, #8
800252c: 4608 mov r0, r1
800252e: f000 f8b7 bl 80026a0 <FloatToString>
//Convert2Hex((ec_now+0x80008000), tempString);
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
8002532: f107 0308 add.w r3, r7, #8
8002536: 4618 mov r0, r3
8002538: f7fd fe08 bl 800014c <strlen>
800253c: 4603 mov r3, r0
800253e: b29a uxth r2, r3
8002540: f107 0308 add.w r3, r7, #8
8002544: 4611 mov r1, r2
8002546: 4618 mov r0, r3
8002548: f000 fae0 bl 8002b0c <rs485_send_broadcast>
//intToStr(ec_now_i, tempString);
//rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
rs485_send_broadcast(&newline, 1);
800254c: 1dfb adds r3, r7, #7
800254e: 2101 movs r1, #1
8002550: 4618 mov r0, r3
8002552: f000 fadb bl 8002b0c <rs485_send_broadcast>
//}
if (g_ph_filter.value_valid) // pH
8002556: 4b29 ldr r3, [pc, #164] @ (80025fc <main+0x2b0>)
8002558: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800255c: 2b00 cmp r3, #0
800255e: d025 beq.n 80025ac <main+0x260>
{
uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value);
8002560: 4b26 ldr r3, [pc, #152] @ (80025fc <main+0x2b0>)
8002562: 6b9b ldr r3, [r3, #56] @ 0x38
8002564: 4618 mov r0, r3
8002566: f7ff fabb bl 8001ae0 <ADS1015_Compress_To_IntScale>
800256a: 4603 mov r3, r0
800256c: 837b strh r3, [r7, #26]
intToStr(ph_final, tempString);
800256e: f9b7 301a ldrsh.w r3, [r7, #26]
8002572: f107 0208 add.w r2, r7, #8
8002576: 4611 mov r1, r2
8002578: 4618 mov r0, r3
800257a: f000 f9a5 bl 80028c8 <intToStr>
//float ph_final = g_ph_filter.filtered_value;
//FloatToString(tempString, ph_final);
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
800257e: f107 0308 add.w r3, r7, #8
8002582: 4618 mov r0, r3
8002584: f7fd fde2 bl 800014c <strlen>
8002588: 4603 mov r3, r0
800258a: b29a uxth r2, r3
800258c: f107 0308 add.w r3, r7, #8
8002590: 4611 mov r1, r2
8002592: 4618 mov r0, r3
8002594: f000 faba bl 8002b0c <rs485_send_broadcast>
rs485_send_broadcast(&newline, 1);
8002598: 1dfb adds r3, r7, #7
800259a: 2101 movs r1, #1
800259c: 4618 mov r0, r3
800259e: f000 fab5 bl 8002b0c <rs485_send_broadcast>
rs485_send_broadcast(&newline, 1);
80025a2: 1dfb adds r3, r7, #7
80025a4: 2101 movs r1, #1
80025a6: 4618 mov r0, r3
80025a8: f000 fab0 bl 8002b0c <rs485_send_broadcast>
}
rs485_send_broadcast(&newline, 1);
80025ac: 1dfb adds r3, r7, #7
80025ae: 2101 movs r1, #1
80025b0: 4618 mov r0, r3
80025b2: f000 faab bl 8002b0c <rs485_send_broadcast>
}
// Piscar LED verde em PB4 a cada 1 segundo
if ((current_millis - previous_millis_green) >= 1000)
80025b6: 6aba ldr r2, [r7, #40] @ 0x28
80025b8: 6b7b ldr r3, [r7, #52] @ 0x34
80025ba: 1ad3 subs r3, r2, r3
80025bc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
80025c0: f4ff af19 bcc.w 80023f6 <main+0xaa>
{
previous_millis_green = current_millis;
80025c4: 6abb ldr r3, [r7, #40] @ 0x28
80025c6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4);
80025c8: 2110 movs r1, #16
80025ca: 4803 ldr r0, [pc, #12] @ (80025d8 <main+0x28c>)
80025cc: f001 faf5 bl 8003bba <HAL_GPIO_TogglePin>
AD5934_Process_System();
80025d0: e711 b.n 80023f6 <main+0xaa>
80025d2: bf00 nop
80025d4: 2000030c .word 0x2000030c
80025d8: 40010c00 .word 0x40010c00
80025dc: 20000084 .word 0x20000084
80025e0: 10624dd3 .word 0x10624dd3
80025e4: 2000010c .word 0x2000010c
80025e8: 20000094 .word 0x20000094
80025ec: 20000088 .word 0x20000088
80025f0: 2000014c .word 0x2000014c
80025f4: 20000152 .word 0x20000152
80025f8: 2000008c .word 0x2000008c
80025fc: 200001c4 .word 0x200001c4
08002600 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8002600: b580 push {r7, lr}
8002602: b094 sub sp, #80 @ 0x50
8002604: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8002606: f107 0328 add.w r3, r7, #40 @ 0x28
800260a: 2228 movs r2, #40 @ 0x28
800260c: 2100 movs r1, #0
800260e: 4618 mov r0, r3
8002610: f004 f9f0 bl 80069f4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8002614: f107 0314 add.w r3, r7, #20
8002618: 2200 movs r2, #0
800261a: 601a str r2, [r3, #0]
800261c: 605a str r2, [r3, #4]
800261e: 609a str r2, [r3, #8]
8002620: 60da str r2, [r3, #12]
8002622: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8002624: 1d3b adds r3, r7, #4
8002626: 2200 movs r2, #0
8002628: 601a str r2, [r3, #0]
800262a: 605a str r2, [r3, #4]
800262c: 609a str r2, [r3, #8]
800262e: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8002630: 2301 movs r3, #1
8002632: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8002634: f44f 3380 mov.w r3, #65536 @ 0x10000
8002638: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800263a: 2300 movs r3, #0
800263c: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800263e: f107 0328 add.w r3, r7, #40 @ 0x28
8002642: 4618 mov r0, r3
8002644: f002 fb06 bl 8004c54 <HAL_RCC_OscConfig>
8002648: 4603 mov r3, r0
800264a: 2b00 cmp r3, #0
800264c: d001 beq.n 8002652 <SystemClock_Config+0x52>
{
Error_Handler();
800264e: f000 fa1f bl 8002a90 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8002652: 230f movs r3, #15
8002654: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
8002656: 2301 movs r3, #1
8002658: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800265a: 2300 movs r3, #0
800265c: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800265e: 2300 movs r3, #0
8002660: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8002662: 2300 movs r3, #0
8002664: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8002666: f107 0314 add.w r3, r7, #20
800266a: 2100 movs r1, #0
800266c: 4618 mov r0, r3
800266e: f002 fd73 bl 8005158 <HAL_RCC_ClockConfig>
8002672: 4603 mov r3, r0
8002674: 2b00 cmp r3, #0
8002676: d001 beq.n 800267c <SystemClock_Config+0x7c>
{
Error_Handler();
8002678: f000 fa0a bl 8002a90 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
800267c: 2302 movs r3, #2
800267e: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
8002680: f44f 4340 mov.w r3, #49152 @ 0xc000
8002684: 60fb str r3, [r7, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002686: 1d3b adds r3, r7, #4
8002688: 4618 mov r0, r3
800268a: f002 fef5 bl 8005478 <HAL_RCCEx_PeriphCLKConfig>
800268e: 4603 mov r3, r0
8002690: 2b00 cmp r3, #0
8002692: d001 beq.n 8002698 <SystemClock_Config+0x98>
{
Error_Handler();
8002694: f000 f9fc bl 8002a90 <Error_Handler>
}
}
8002698: bf00 nop
800269a: 3750 adds r7, #80 @ 0x50
800269c: 46bd mov sp, r7
800269e: bd80 pop {r7, pc}
080026a0 <FloatToString>:
* @param val - value to be converted
*
* @return None.
*******************************************************************************/
void FloatToString(uint8_t *buf, double val)
{
80026a0: b5b0 push {r4, r5, r7, lr}
80026a2: b096 sub sp, #88 @ 0x58
80026a4: af00 add r7, sp, #0
80026a6: 60f8 str r0, [r7, #12]
80026a8: e9c7 2300 strd r2, r3, [r7]
char temp[20]; // Buffer auxiliar para construção segura
int i = 0;
80026ac: 2300 movs r3, #0
80026ae: 657b str r3, [r7, #84] @ 0x54
// 1. Tratar sinal negativo
if (val < 0) {
80026b0: f04f 0200 mov.w r2, #0
80026b4: f04f 0300 mov.w r3, #0
80026b8: e9d7 0100 ldrd r0, r1, [r7]
80026bc: f7fe f894 bl 80007e8 <__aeabi_dcmplt>
80026c0: 4603 mov r3, r0
80026c2: 2b00 cmp r3, #0
80026c4: d00d beq.n 80026e2 <FloatToString+0x42>
temp[i++] = '-';
80026c6: 6d7b ldr r3, [r7, #84] @ 0x54
80026c8: 1c5a adds r2, r3, #1
80026ca: 657a str r2, [r7, #84] @ 0x54
80026cc: 3358 adds r3, #88 @ 0x58
80026ce: 443b add r3, r7
80026d0: 222d movs r2, #45 @ 0x2d
80026d2: f803 2c30 strb.w r2, [r3, #-48]
val = -val;
80026d6: 683c ldr r4, [r7, #0]
80026d8: 687b ldr r3, [r7, #4]
80026da: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000
80026de: e9c7 4500 strd r4, r5, [r7]
}
// 2. Separar parte inteira e fracionária
long intPart = (long)val;
80026e2: e9d7 0100 ldrd r0, r1, [r7]
80026e6: f7fe f8a7 bl 8000838 <__aeabi_d2iz>
80026ea: 4603 mov r3, r0
80026ec: 653b str r3, [r7, #80] @ 0x50
// Multiplicamos por 1000 para obter 3 casas decimais fixas
int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
80026ee: 6d38 ldr r0, [r7, #80] @ 0x50
80026f0: f7fd ffb0 bl 8000654 <__aeabi_i2d>
80026f4: 4602 mov r2, r0
80026f6: 460b mov r3, r1
80026f8: e9d7 0100 ldrd r0, r1, [r7]
80026fc: f7fd fe5c bl 80003b8 <__aeabi_dsub>
8002700: 4602 mov r2, r0
8002702: 460b mov r3, r1
8002704: 4610 mov r0, r2
8002706: 4619 mov r1, r3
8002708: f04f 0200 mov.w r2, #0
800270c: 4b6a ldr r3, [pc, #424] @ (80028b8 <FloatToString+0x218>)
800270e: f7fd fd25 bl 800015c <__aeabi_dmul>
8002712: 4602 mov r2, r0
8002714: 460b mov r3, r1
8002716: 4610 mov r0, r2
8002718: 4619 mov r1, r3
800271a: f04f 0200 mov.w r2, #0
800271e: 4b67 ldr r3, [pc, #412] @ (80028bc <FloatToString+0x21c>)
8002720: f7fd fe4c bl 80003bc <__adddf3>
8002724: 4602 mov r2, r0
8002726: 460b mov r3, r1
8002728: 4610 mov r0, r2
800272a: 4619 mov r1, r3
800272c: f7fe f884 bl 8000838 <__aeabi_d2iz>
8002730: 4603 mov r3, r0
8002732: 63fb str r3, [r7, #60] @ 0x3c
// 3. Converter a parte inteira para o buffer temp
// Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
char intRev[12];
int j = 0;
8002734: 2300 movs r3, #0
8002736: 64fb str r3, [r7, #76] @ 0x4c
if (intPart == 0) {
8002738: 6d3b ldr r3, [r7, #80] @ 0x50
800273a: 2b00 cmp r3, #0
800273c: d126 bne.n 800278c <FloatToString+0xec>
intRev[j++] = '0';
800273e: 6cfb ldr r3, [r7, #76] @ 0x4c
8002740: 1c5a adds r2, r3, #1
8002742: 64fa str r2, [r7, #76] @ 0x4c
8002744: 3358 adds r3, #88 @ 0x58
8002746: 443b add r3, r7
8002748: 2230 movs r2, #48 @ 0x30
800274a: f803 2c3c strb.w r2, [r3, #-60]
800274e: e020 b.n 8002792 <FloatToString+0xf2>
} else {
while (intPart > 0) {
intRev[j++] = (intPart % 10) + '0';
8002750: 6d3a ldr r2, [r7, #80] @ 0x50
8002752: 4b5b ldr r3, [pc, #364] @ (80028c0 <FloatToString+0x220>)
8002754: fb83 1302 smull r1, r3, r3, r2
8002758: 1099 asrs r1, r3, #2
800275a: 17d3 asrs r3, r2, #31
800275c: 1ac9 subs r1, r1, r3
800275e: 460b mov r3, r1
8002760: 009b lsls r3, r3, #2
8002762: 440b add r3, r1
8002764: 005b lsls r3, r3, #1
8002766: 1ad1 subs r1, r2, r3
8002768: b2ca uxtb r2, r1
800276a: 6cfb ldr r3, [r7, #76] @ 0x4c
800276c: 1c59 adds r1, r3, #1
800276e: 64f9 str r1, [r7, #76] @ 0x4c
8002770: 3230 adds r2, #48 @ 0x30
8002772: b2d2 uxtb r2, r2
8002774: 3358 adds r3, #88 @ 0x58
8002776: 443b add r3, r7
8002778: f803 2c3c strb.w r2, [r3, #-60]
intPart /= 10;
800277c: 6d3b ldr r3, [r7, #80] @ 0x50
800277e: 4a50 ldr r2, [pc, #320] @ (80028c0 <FloatToString+0x220>)
8002780: fb82 1203 smull r1, r2, r2, r3
8002784: 1092 asrs r2, r2, #2
8002786: 17db asrs r3, r3, #31
8002788: 1ad3 subs r3, r2, r3
800278a: 653b str r3, [r7, #80] @ 0x50
while (intPart > 0) {
800278c: 6d3b ldr r3, [r7, #80] @ 0x50
800278e: 2b00 cmp r3, #0
8002790: dcde bgt.n 8002750 <FloatToString+0xb0>
}
}
// Inverter a parte inteira de volta para o buffer principal
for (int k = j - 1; k >= 0; k--) {
8002792: 6cfb ldr r3, [r7, #76] @ 0x4c
8002794: 3b01 subs r3, #1
8002796: 64bb str r3, [r7, #72] @ 0x48
8002798: e00e b.n 80027b8 <FloatToString+0x118>
temp[i++] = intRev[k];
800279a: 6d7b ldr r3, [r7, #84] @ 0x54
800279c: 1c5a adds r2, r3, #1
800279e: 657a str r2, [r7, #84] @ 0x54
80027a0: f107 011c add.w r1, r7, #28
80027a4: 6cba ldr r2, [r7, #72] @ 0x48
80027a6: 440a add r2, r1
80027a8: 7812 ldrb r2, [r2, #0]
80027aa: 3358 adds r3, #88 @ 0x58
80027ac: 443b add r3, r7
80027ae: f803 2c30 strb.w r2, [r3, #-48]
for (int k = j - 1; k >= 0; k--) {
80027b2: 6cbb ldr r3, [r7, #72] @ 0x48
80027b4: 3b01 subs r3, #1
80027b6: 64bb str r3, [r7, #72] @ 0x48
80027b8: 6cbb ldr r3, [r7, #72] @ 0x48
80027ba: 2b00 cmp r3, #0
80027bc: daed bge.n 800279a <FloatToString+0xfa>
}
// 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
temp[i++] = '.';
80027be: 6d7b ldr r3, [r7, #84] @ 0x54
80027c0: 1c5a adds r2, r3, #1
80027c2: 657a str r2, [r7, #84] @ 0x54
80027c4: 3358 adds r3, #88 @ 0x58
80027c6: 443b add r3, r7
80027c8: 222e movs r2, #46 @ 0x2e
80027ca: f803 2c30 strb.w r2, [r3, #-48]
// Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
int fracBuffer[3];
fracBuffer[2] = fracPart % 10; // Unidade
80027ce: 6bf9 ldr r1, [r7, #60] @ 0x3c
80027d0: 4b3b ldr r3, [pc, #236] @ (80028c0 <FloatToString+0x220>)
80027d2: fb83 2301 smull r2, r3, r3, r1
80027d6: 109a asrs r2, r3, #2
80027d8: 17cb asrs r3, r1, #31
80027da: 1ad2 subs r2, r2, r3
80027dc: 4613 mov r3, r2
80027de: 009b lsls r3, r3, #2
80027e0: 4413 add r3, r2
80027e2: 005b lsls r3, r3, #1
80027e4: 1aca subs r2, r1, r3
80027e6: 61ba str r2, [r7, #24]
fracBuffer[1] = (fracPart / 10) % 10; // Dezena
80027e8: 6bfb ldr r3, [r7, #60] @ 0x3c
80027ea: 4a35 ldr r2, [pc, #212] @ (80028c0 <FloatToString+0x220>)
80027ec: fb82 1203 smull r1, r2, r2, r3
80027f0: 1092 asrs r2, r2, #2
80027f2: 17db asrs r3, r3, #31
80027f4: 1ad1 subs r1, r2, r3
80027f6: 4b32 ldr r3, [pc, #200] @ (80028c0 <FloatToString+0x220>)
80027f8: fb83 2301 smull r2, r3, r3, r1
80027fc: 109a asrs r2, r3, #2
80027fe: 17cb asrs r3, r1, #31
8002800: 1ad2 subs r2, r2, r3
8002802: 4613 mov r3, r2
8002804: 009b lsls r3, r3, #2
8002806: 4413 add r3, r2
8002808: 005b lsls r3, r3, #1
800280a: 1aca subs r2, r1, r3
800280c: 617a str r2, [r7, #20]
fracBuffer[0] = (fracPart / 100) % 10; // Centena
800280e: 6bfb ldr r3, [r7, #60] @ 0x3c
8002810: 4a2c ldr r2, [pc, #176] @ (80028c4 <FloatToString+0x224>)
8002812: fb82 1203 smull r1, r2, r2, r3
8002816: 1152 asrs r2, r2, #5
8002818: 17db asrs r3, r3, #31
800281a: 1ad1 subs r1, r2, r3
800281c: 4b28 ldr r3, [pc, #160] @ (80028c0 <FloatToString+0x220>)
800281e: fb83 2301 smull r2, r3, r3, r1
8002822: 109a asrs r2, r3, #2
8002824: 17cb asrs r3, r1, #31
8002826: 1ad2 subs r2, r2, r3
8002828: 4613 mov r3, r2
800282a: 009b lsls r3, r3, #2
800282c: 4413 add r3, r2
800282e: 005b lsls r3, r3, #1
8002830: 1aca subs r2, r1, r3
8002832: 613a str r2, [r7, #16]
for (int k = 0; k <= 2; k++) {
8002834: 2300 movs r3, #0
8002836: 647b str r3, [r7, #68] @ 0x44
8002838: e012 b.n 8002860 <FloatToString+0x1c0>
temp[i++] = fracBuffer[k] + '0';
800283a: 6c7b ldr r3, [r7, #68] @ 0x44
800283c: 009b lsls r3, r3, #2
800283e: 3358 adds r3, #88 @ 0x58
8002840: 443b add r3, r7
8002842: f853 3c48 ldr.w r3, [r3, #-72]
8002846: b2da uxtb r2, r3
8002848: 6d7b ldr r3, [r7, #84] @ 0x54
800284a: 1c59 adds r1, r3, #1
800284c: 6579 str r1, [r7, #84] @ 0x54
800284e: 3230 adds r2, #48 @ 0x30
8002850: b2d2 uxtb r2, r2
8002852: 3358 adds r3, #88 @ 0x58
8002854: 443b add r3, r7
8002856: f803 2c30 strb.w r2, [r3, #-48]
for (int k = 0; k <= 2; k++) {
800285a: 6c7b ldr r3, [r7, #68] @ 0x44
800285c: 3301 adds r3, #1
800285e: 647b str r3, [r7, #68] @ 0x44
8002860: 6c7b ldr r3, [r7, #68] @ 0x44
8002862: 2b02 cmp r3, #2
8002864: dde9 ble.n 800283a <FloatToString+0x19a>
}
// 5. Finalizar a string com o caractere nulo
temp[i] = '\0';
8002866: f107 0228 add.w r2, r7, #40 @ 0x28
800286a: 6d7b ldr r3, [r7, #84] @ 0x54
800286c: 4413 add r3, r2
800286e: 2200 movs r2, #0
8002870: 701a strb r2, [r3, #0]
// 6. Copiar para o buffer de destino final (sem risco de lixo)
int destIdx = 0;
8002872: 2300 movs r3, #0
8002874: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
8002876: e00b b.n 8002890 <FloatToString+0x1f0>
buf[destIdx] = temp[destIdx];
8002878: 6c3b ldr r3, [r7, #64] @ 0x40
800287a: 68fa ldr r2, [r7, #12]
800287c: 4413 add r3, r2
800287e: f107 0128 add.w r1, r7, #40 @ 0x28
8002882: 6c3a ldr r2, [r7, #64] @ 0x40
8002884: 440a add r2, r1
8002886: 7812 ldrb r2, [r2, #0]
8002888: 701a strb r2, [r3, #0]
destIdx++;
800288a: 6c3b ldr r3, [r7, #64] @ 0x40
800288c: 3301 adds r3, #1
800288e: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
8002890: f107 0228 add.w r2, r7, #40 @ 0x28
8002894: 6c3b ldr r3, [r7, #64] @ 0x40
8002896: 4413 add r3, r2
8002898: 781b ldrb r3, [r3, #0]
800289a: 2b00 cmp r3, #0
800289c: d002 beq.n 80028a4 <FloatToString+0x204>
800289e: 6c3b ldr r3, [r7, #64] @ 0x40
80028a0: 2b0e cmp r3, #14
80028a2: dde9 ble.n 8002878 <FloatToString+0x1d8>
}
buf[destIdx] = '\0';
80028a4: 6c3b ldr r3, [r7, #64] @ 0x40
80028a6: 68fa ldr r2, [r7, #12]
80028a8: 4413 add r3, r2
80028aa: 2200 movs r2, #0
80028ac: 701a strb r2, [r3, #0]
}
80028ae: bf00 nop
80028b0: 3758 adds r7, #88 @ 0x58
80028b2: 46bd mov sp, r7
80028b4: bdb0 pop {r4, r5, r7, pc}
80028b6: bf00 nop
80028b8: 408f4000 .word 0x408f4000
80028bc: 3fe00000 .word 0x3fe00000
80028c0: 66666667 .word 0x66666667
80028c4: 51eb851f .word 0x51eb851f
080028c8 <intToStr>:
void intToStr(int16_t N, uint8_t *str)
{
80028c8: b480 push {r7}
80028ca: b087 sub sp, #28
80028cc: af00 add r7, sp, #0
80028ce: 4603 mov r3, r0
80028d0: 6039 str r1, [r7, #0]
80028d2: 80fb strh r3, [r7, #6]
int16_t i = 0;
80028d4: 2300 movs r3, #0
80028d6: 82fb strh r3, [r7, #22]
int16_t sign = N;
80028d8: 88fb ldrh r3, [r7, #6]
80028da: 823b strh r3, [r7, #16]
uint8_t max_len = 15; // Tamanho máximo do buffer
80028dc: 230f movs r3, #15
80028de: 73fb strb r3, [r7, #15]
uint8_t width = 4; // mínimo 4 caracteres
80028e0: 2304 movs r3, #4
80028e2: 757b strb r3, [r7, #21]
// Trata o caso do número zero isoladamente
if (N == 0)
80028e4: f9b7 3006 ldrsh.w r3, [r7, #6]
80028e8: 2b00 cmp r3, #0
80028ea: d127 bne.n 800293c <intToStr+0x74>
{
// Preenche com zeros à esquerda até atingir a largura desejada
while (width > 1 && i < (max_len - 1))
80028ec: e00c b.n 8002908 <intToStr+0x40>
{
str[i++] = '0';
80028ee: f9b7 2016 ldrsh.w r2, [r7, #22]
80028f2: b293 uxth r3, r2
80028f4: 3301 adds r3, #1
80028f6: b29b uxth r3, r3
80028f8: 82fb strh r3, [r7, #22]
80028fa: 683b ldr r3, [r7, #0]
80028fc: 4413 add r3, r2
80028fe: 2230 movs r2, #48 @ 0x30
8002900: 701a strb r2, [r3, #0]
width--;
8002902: 7d7b ldrb r3, [r7, #21]
8002904: 3b01 subs r3, #1
8002906: 757b strb r3, [r7, #21]
while (width > 1 && i < (max_len - 1))
8002908: 7d7b ldrb r3, [r7, #21]
800290a: 2b01 cmp r3, #1
800290c: d905 bls.n 800291a <intToStr+0x52>
800290e: f9b7 2016 ldrsh.w r2, [r7, #22]
8002912: 7bfb ldrb r3, [r7, #15]
8002914: 3b01 subs r3, #1
8002916: 429a cmp r2, r3
8002918: dbe9 blt.n 80028ee <intToStr+0x26>
}
str[i++] = '0';
800291a: f9b7 2016 ldrsh.w r2, [r7, #22]
800291e: b293 uxth r3, r2
8002920: 3301 adds r3, #1
8002922: b29b uxth r3, r3
8002924: 82fb strh r3, [r7, #22]
8002926: 683b ldr r3, [r7, #0]
8002928: 4413 add r3, r2
800292a: 2230 movs r2, #48 @ 0x30
800292c: 701a strb r2, [r3, #0]
str[i] = '\0';
800292e: f9b7 3016 ldrsh.w r3, [r7, #22]
8002932: 683a ldr r2, [r7, #0]
8002934: 4413 add r3, r2
8002936: 2200 movs r2, #0
8002938: 701a strb r2, [r3, #0]
return;
800293a: e08a b.n 8002a52 <intToStr+0x18a>
}
if (N < 0)
800293c: f9b7 3006 ldrsh.w r3, [r7, #6]
8002940: 2b00 cmp r3, #0
8002942: da2d bge.n 80029a0 <intToStr+0xd8>
N = -N;
8002944: 88fb ldrh r3, [r7, #6]
8002946: 425b negs r3, r3
8002948: b29b uxth r3, r3
800294a: 80fb strh r3, [r7, #6]
// Extração dos dígitos
while (N > 0)
800294c: e028 b.n 80029a0 <intToStr+0xd8>
{
if (i >= (max_len - 1))
800294e: f9b7 2016 ldrsh.w r2, [r7, #22]
8002952: 7bfb ldrb r3, [r7, #15]
8002954: 3b01 subs r3, #1
8002956: 429a cmp r2, r3
8002958: da27 bge.n 80029aa <intToStr+0xe2>
break; // Proteção de estouro
str[i++] = (N % 10) + '0';
800295a: f9b7 2006 ldrsh.w r2, [r7, #6]
800295e: 4b3f ldr r3, [pc, #252] @ (8002a5c <intToStr+0x194>)
8002960: fb83 1302 smull r1, r3, r3, r2
8002964: 1099 asrs r1, r3, #2
8002966: 17d3 asrs r3, r2, #31
8002968: 1ac9 subs r1, r1, r3
800296a: 460b mov r3, r1
800296c: 009b lsls r3, r3, #2
800296e: 440b add r3, r1
8002970: 005b lsls r3, r3, #1
8002972: 1ad3 subs r3, r2, r3
8002974: b21b sxth r3, r3
8002976: b2da uxtb r2, r3
8002978: f9b7 1016 ldrsh.w r1, [r7, #22]
800297c: b28b uxth r3, r1
800297e: 3301 adds r3, #1
8002980: b29b uxth r3, r3
8002982: 82fb strh r3, [r7, #22]
8002984: 683b ldr r3, [r7, #0]
8002986: 440b add r3, r1
8002988: 3230 adds r2, #48 @ 0x30
800298a: b2d2 uxtb r2, r2
800298c: 701a strb r2, [r3, #0]
N /= 10;
800298e: f9b7 3006 ldrsh.w r3, [r7, #6]
8002992: 4a32 ldr r2, [pc, #200] @ (8002a5c <intToStr+0x194>)
8002994: fb82 1203 smull r1, r2, r2, r3
8002998: 1092 asrs r2, r2, #2
800299a: 17db asrs r3, r3, #31
800299c: 1ad3 subs r3, r2, r3
800299e: 80fb strh r3, [r7, #6]
while (N > 0)
80029a0: f9b7 3006 ldrsh.w r3, [r7, #6]
80029a4: 2b00 cmp r3, #0
80029a6: dcd2 bgt.n 800294e <intToStr+0x86>
80029a8: e000 b.n 80029ac <intToStr+0xe4>
break; // Proteção de estouro
80029aa: bf00 nop
}
// Adiciona o sinal de menos se necessário
if (sign < 0)
80029ac: f9b7 3010 ldrsh.w r3, [r7, #16]
80029b0: 2b00 cmp r3, #0
80029b2: da1a bge.n 80029ea <intToStr+0x122>
{
if (i < (max_len - 1))
80029b4: f9b7 2016 ldrsh.w r2, [r7, #22]
80029b8: 7bfb ldrb r3, [r7, #15]
80029ba: 3b01 subs r3, #1
80029bc: 429a cmp r2, r3
80029be: da14 bge.n 80029ea <intToStr+0x122>
str[i++] = '-';
80029c0: f9b7 2016 ldrsh.w r2, [r7, #22]
80029c4: b293 uxth r3, r2
80029c6: 3301 adds r3, #1
80029c8: b29b uxth r3, r3
80029ca: 82fb strh r3, [r7, #22]
80029cc: 683b ldr r3, [r7, #0]
80029ce: 4413 add r3, r2
80029d0: 222d movs r2, #45 @ 0x2d
80029d2: 701a strb r2, [r3, #0]
}
// Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal)
while (i < width && i < (max_len - 1))
80029d4: e009 b.n 80029ea <intToStr+0x122>
{
str[i++] = '0';
80029d6: f9b7 2016 ldrsh.w r2, [r7, #22]
80029da: b293 uxth r3, r2
80029dc: 3301 adds r3, #1
80029de: b29b uxth r3, r3
80029e0: 82fb strh r3, [r7, #22]
80029e2: 683b ldr r3, [r7, #0]
80029e4: 4413 add r3, r2
80029e6: 2230 movs r2, #48 @ 0x30
80029e8: 701a strb r2, [r3, #0]
while (i < width && i < (max_len - 1))
80029ea: f9b7 2016 ldrsh.w r2, [r7, #22]
80029ee: 7d7b ldrb r3, [r7, #21]
80029f0: 429a cmp r2, r3
80029f2: da05 bge.n 8002a00 <intToStr+0x138>
80029f4: f9b7 2016 ldrsh.w r2, [r7, #22]
80029f8: 7bfb ldrb r3, [r7, #15]
80029fa: 3b01 subs r3, #1
80029fc: 429a cmp r2, r3
80029fe: dbea blt.n 80029d6 <intToStr+0x10e>
}
str[i] = '\0';
8002a00: f9b7 3016 ldrsh.w r3, [r7, #22]
8002a04: 683a ldr r2, [r7, #0]
8002a06: 4413 add r3, r2
8002a08: 2200 movs r2, #0
8002a0a: 701a strb r2, [r3, #0]
// Inverte a string para colocar na ordem correta
for (uint8_t j = 0, k = i - 1; j < k; j++, k--)
8002a0c: 2300 movs r3, #0
8002a0e: 753b strb r3, [r7, #20]
8002a10: 8afb ldrh r3, [r7, #22]
8002a12: b2db uxtb r3, r3
8002a14: 3b01 subs r3, #1
8002a16: 74fb strb r3, [r7, #19]
8002a18: e017 b.n 8002a4a <intToStr+0x182>
{
uint8_t temp = str[j];
8002a1a: 7d3b ldrb r3, [r7, #20]
8002a1c: 683a ldr r2, [r7, #0]
8002a1e: 4413 add r3, r2
8002a20: 781b ldrb r3, [r3, #0]
8002a22: 73bb strb r3, [r7, #14]
str[j] = str[k];
8002a24: 7cfb ldrb r3, [r7, #19]
8002a26: 683a ldr r2, [r7, #0]
8002a28: 441a add r2, r3
8002a2a: 7d3b ldrb r3, [r7, #20]
8002a2c: 6839 ldr r1, [r7, #0]
8002a2e: 440b add r3, r1
8002a30: 7812 ldrb r2, [r2, #0]
8002a32: 701a strb r2, [r3, #0]
str[k] = temp;
8002a34: 7cfb ldrb r3, [r7, #19]
8002a36: 683a ldr r2, [r7, #0]
8002a38: 4413 add r3, r2
8002a3a: 7bba ldrb r2, [r7, #14]
8002a3c: 701a strb r2, [r3, #0]
for (uint8_t j = 0, k = i - 1; j < k; j++, k--)
8002a3e: 7d3b ldrb r3, [r7, #20]
8002a40: 3301 adds r3, #1
8002a42: 753b strb r3, [r7, #20]
8002a44: 7cfb ldrb r3, [r7, #19]
8002a46: 3b01 subs r3, #1
8002a48: 74fb strb r3, [r7, #19]
8002a4a: 7d3a ldrb r2, [r7, #20]
8002a4c: 7cfb ldrb r3, [r7, #19]
8002a4e: 429a cmp r2, r3
8002a50: d3e3 bcc.n 8002a1a <intToStr+0x152>
}
}
8002a52: 371c adds r7, #28
8002a54: 46bd mov sp, r7
8002a56: bc80 pop {r7}
8002a58: 4770 bx lr
8002a5a: bf00 nop
8002a5c: 66666667 .word 0x66666667
08002a60 <HAL_TIM_PeriodElapsedCallback>:
}
/* TIM3 Timer Interrupt */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002a60: b480 push {r7}
8002a62: b083 sub sp, #12
8002a64: af00 add r7, sp, #0
8002a66: 6078 str r0, [r7, #4]
if (htim->Instance == TIM3)
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 681b ldr r3, [r3, #0]
8002a6c: 4a06 ldr r2, [pc, #24] @ (8002a88 <HAL_TIM_PeriodElapsedCallback+0x28>)
8002a6e: 4293 cmp r3, r2
8002a70: d104 bne.n 8002a7c <HAL_TIM_PeriodElapsedCallback+0x1c>
{
g_ms_counter++; /* Relógio global do sistema */
8002a72: 4b06 ldr r3, [pc, #24] @ (8002a8c <HAL_TIM_PeriodElapsedCallback+0x2c>)
8002a74: 681b ldr r3, [r3, #0]
8002a76: 3301 adds r3, #1
8002a78: 4a04 ldr r2, [pc, #16] @ (8002a8c <HAL_TIM_PeriodElapsedCallback+0x2c>)
8002a7a: 6013 str r3, [r2, #0]
}
}
8002a7c: bf00 nop
8002a7e: 370c adds r7, #12
8002a80: 46bd mov sp, r7
8002a82: bc80 pop {r7}
8002a84: 4770 bx lr
8002a86: bf00 nop
8002a88: 40000400 .word 0x40000400
8002a8c: 20000084 .word 0x20000084
08002a90 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8002a90: b480 push {r7}
8002a92: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002a94: b672 cpsid i
}
8002a96: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8002a98: bf00 nop
8002a9a: e7fd b.n 8002a98 <Error_Handler+0x8>
08002a9c <LL_GPIO_ReadInputPort>:
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
8002a9c: b480 push {r7}
8002a9e: b083 sub sp, #12
8002aa0: af00 add r7, sp, #0
8002aa2: 6078 str r0, [r7, #4]
return (READ_REG(GPIOx->IDR));
8002aa4: 687b ldr r3, [r7, #4]
8002aa6: 689b ldr r3, [r3, #8]
}
8002aa8: 4618 mov r0, r3
8002aaa: 370c adds r7, #12
8002aac: 46bd mov sp, r7
8002aae: bc80 pop {r7}
8002ab0: 4770 bx lr
...
08002ab4 <rs485_init>:
/**
* @brief Initializes the RS-485 driver.
* @note This function configures GPIOs for address detection and USART1 for communication.
*/
void rs485_init(void)
{
8002ab4: b580 push {r7, lr}
8002ab6: af00 add r7, sp, #0
/* Configure GPIOs for address detection */
rs485_configure_gpio_address();
8002ab8: f000 f864 bl 8002b84 <rs485_configure_gpio_address>
/* Configure USART1 for RS-485 communication */
rs485_configure_usart1();
8002abc: f000 f8a8 bl 8002c10 <rs485_configure_usart1>
/* Get the current device address from GPIOs */
device_address.full_address = rs485_get_address();
8002ac0: f000 f808 bl 8002ad4 <rs485_get_address>
8002ac4: 4603 mov r3, r0
8002ac6: 461a mov r2, r3
8002ac8: 4b01 ldr r3, [pc, #4] @ (8002ad0 <rs485_init+0x1c>)
8002aca: 709a strb r2, [r3, #2]
}
8002acc: bf00 nop
8002ace: bd80 pop {r7, pc}
8002ad0: 200002c0 .word 0x200002c0
08002ad4 <rs485_get_address>:
/**
* @brief Gets the current device address from GPIOs.
* @return The 8-bit device address.
*/
uint8_t rs485_get_address(void)
{
8002ad4: b598 push {r3, r4, r7, lr}
8002ad6: af00 add r7, sp, #0
return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
8002ad8: 480a ldr r0, [pc, #40] @ (8002b04 <rs485_get_address+0x30>)
8002ada: f7ff ffdf bl 8002a9c <LL_GPIO_ReadInputPort>
8002ade: 4603 mov r3, r0
8002ae0: 0a1b lsrs r3, r3, #8
8002ae2: b2db uxtb r3, r3
8002ae4: f023 030f bic.w r3, r3, #15
8002ae8: b2dc uxtb r4, r3
8002aea: 4807 ldr r0, [pc, #28] @ (8002b08 <rs485_get_address+0x34>)
8002aec: f7ff ffd6 bl 8002a9c <LL_GPIO_ReadInputPort>
8002af0: 4603 mov r3, r0
8002af2: 089b lsrs r3, r3, #2
8002af4: b2db uxtb r3, r3
8002af6: f003 030f and.w r3, r3, #15
8002afa: b2db uxtb r3, r3
8002afc: 4323 orrs r3, r4
8002afe: b2db uxtb r3, r3
}
8002b00: 4618 mov r0, r3
8002b02: bd98 pop {r3, r4, r7, pc}
8002b04: 40010c00 .word 0x40010c00
8002b08: 40010800 .word 0x40010800
08002b0c <rs485_send_broadcast>:
* @param data Pointer to the data buffer.
* @param length Number of bytes to send.
* @retval HAL_OK on success, otherwise error code.
*/
HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
{
8002b0c: b580 push {r7, lr}
8002b0e: b084 sub sp, #16
8002b10: af00 add r7, sp, #0
8002b12: 6078 str r0, [r7, #4]
8002b14: 460b mov r3, r1
8002b16: 807b strh r3, [r7, #2]
/* Enable transmission mode */
rs485_enable_tx();
8002b18: f000 f81c bl 8002b54 <rs485_enable_tx>
/* Send the broadcast address (0x00) first */
uint8_t broadcast_address = 0x00;
8002b1c: 2300 movs r3, #0
8002b1e: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
8002b20: f107 010e add.w r1, r7, #14
8002b24: f04f 33ff mov.w r3, #4294967295
8002b28: 2201 movs r2, #1
8002b2a: 4809 ldr r0, [pc, #36] @ (8002b50 <rs485_send_broadcast+0x44>)
8002b2c: f003 f99c bl 8005e68 <HAL_UART_Transmit>
/* Send the data */
HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
8002b30: 887a ldrh r2, [r7, #2]
8002b32: f04f 33ff mov.w r3, #4294967295
8002b36: 6879 ldr r1, [r7, #4]
8002b38: 4805 ldr r0, [pc, #20] @ (8002b50 <rs485_send_broadcast+0x44>)
8002b3a: f003 f995 bl 8005e68 <HAL_UART_Transmit>
8002b3e: 4603 mov r3, r0
8002b40: 73fb strb r3, [r7, #15]
/* Disable transmission mode after sending */
rs485_disable_tx();
8002b42: f000 f813 bl 8002b6c <rs485_disable_tx>
return status;
8002b46: 7bfb ldrb r3, [r7, #15]
}
8002b48: 4618 mov r0, r3
8002b4a: 3710 adds r7, #16
8002b4c: 46bd mov sp, r7
8002b4e: bd80 pop {r7, pc}
8002b50: 200002c4 .word 0x200002c4
08002b54 <rs485_enable_tx>:
/**
* @brief Enables transmission mode on RS-485 transceiver.
*/
void rs485_enable_tx(void)
{
8002b54: b580 push {r7, lr}
8002b56: af00 add r7, sp, #0
/* Set TX EN pin high to enable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
8002b58: 2201 movs r2, #1
8002b5a: f44f 5180 mov.w r1, #4096 @ 0x1000
8002b5e: 4802 ldr r0, [pc, #8] @ (8002b68 <rs485_enable_tx+0x14>)
8002b60: f001 f813 bl 8003b8a <HAL_GPIO_WritePin>
}
8002b64: bf00 nop
8002b66: bd80 pop {r7, pc}
8002b68: 40010800 .word 0x40010800
08002b6c <rs485_disable_tx>:
/**
* @brief Disables transmission mode on RS-485 transceiver.
*/
void rs485_disable_tx(void)
{
8002b6c: b580 push {r7, lr}
8002b6e: af00 add r7, sp, #0
/* Set TX EN pin low to disable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
8002b70: 2200 movs r2, #0
8002b72: f44f 5180 mov.w r1, #4096 @ 0x1000
8002b76: 4802 ldr r0, [pc, #8] @ (8002b80 <rs485_disable_tx+0x14>)
8002b78: f001 f807 bl 8003b8a <HAL_GPIO_WritePin>
}
8002b7c: bf00 nop
8002b7e: bd80 pop {r7, pc}
8002b80: 40010800 .word 0x40010800
08002b84 <rs485_configure_gpio_address>:
/**
* @brief Configures GPIOs for address detection.
*/
static void rs485_configure_gpio_address(void)
{
8002b84: b580 push {r7, lr}
8002b86: b086 sub sp, #24
8002b88: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002b8a: f107 0308 add.w r3, r7, #8
8002b8e: 2200 movs r2, #0
8002b90: 601a str r2, [r3, #0]
8002b92: 605a str r2, [r3, #4]
8002b94: 609a str r2, [r3, #8]
8002b96: 60da str r2, [r3, #12]
/* Enable clock for GPIOA and GPIOB */
__HAL_RCC_GPIOA_CLK_ENABLE();
8002b98: 4b1a ldr r3, [pc, #104] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002b9a: 699b ldr r3, [r3, #24]
8002b9c: 4a19 ldr r2, [pc, #100] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002b9e: f043 0304 orr.w r3, r3, #4
8002ba2: 6193 str r3, [r2, #24]
8002ba4: 4b17 ldr r3, [pc, #92] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002ba6: 699b ldr r3, [r3, #24]
8002ba8: f003 0304 and.w r3, r3, #4
8002bac: 607b str r3, [r7, #4]
8002bae: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002bb0: 4b14 ldr r3, [pc, #80] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002bb2: 699b ldr r3, [r3, #24]
8002bb4: 4a13 ldr r2, [pc, #76] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002bb6: f043 0308 orr.w r3, r3, #8
8002bba: 6193 str r3, [r2, #24]
8002bbc: 4b11 ldr r3, [pc, #68] @ (8002c04 <rs485_configure_gpio_address+0x80>)
8002bbe: 699b ldr r3, [r3, #24]
8002bc0: f003 0308 and.w r3, r3, #8
8002bc4: 603b str r3, [r7, #0]
8002bc6: 683b ldr r3, [r7, #0]
/* Configure PA2-PA5 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
8002bc8: 233c movs r3, #60 @ 0x3c
8002bca: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002bcc: 2300 movs r3, #0
8002bce: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002bd0: 2301 movs r3, #1
8002bd2: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002bd4: f107 0308 add.w r3, r7, #8
8002bd8: 4619 mov r1, r3
8002bda: 480b ldr r0, [pc, #44] @ (8002c08 <rs485_configure_gpio_address+0x84>)
8002bdc: f000 fe3a bl 8003854 <HAL_GPIO_Init>
/* Configure PB12-PB15 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
8002be0: f44f 4370 mov.w r3, #61440 @ 0xf000
8002be4: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002be6: 2300 movs r3, #0
8002be8: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002bea: 2301 movs r3, #1
8002bec: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002bee: f107 0308 add.w r3, r7, #8
8002bf2: 4619 mov r1, r3
8002bf4: 4805 ldr r0, [pc, #20] @ (8002c0c <rs485_configure_gpio_address+0x88>)
8002bf6: f000 fe2d bl 8003854 <HAL_GPIO_Init>
}
8002bfa: bf00 nop
8002bfc: 3718 adds r7, #24
8002bfe: 46bd mov sp, r7
8002c00: bd80 pop {r7, pc}
8002c02: bf00 nop
8002c04: 40021000 .word 0x40021000
8002c08: 40010800 .word 0x40010800
8002c0c: 40010c00 .word 0x40010c00
08002c10 <rs485_configure_usart1>:
/**
* @brief Configures USART1 for RS-485 communication.
*/
static void rs485_configure_usart1(void)
{
8002c10: b580 push {r7, lr}
8002c12: b082 sub sp, #8
8002c14: af00 add r7, sp, #0
/* Enable clock for USART1 */
__HAL_RCC_USART1_CLK_ENABLE();
8002c16: 4b18 ldr r3, [pc, #96] @ (8002c78 <rs485_configure_usart1+0x68>)
8002c18: 699b ldr r3, [r3, #24]
8002c1a: 4a17 ldr r2, [pc, #92] @ (8002c78 <rs485_configure_usart1+0x68>)
8002c1c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002c20: 6193 str r3, [r2, #24]
8002c22: 4b15 ldr r3, [pc, #84] @ (8002c78 <rs485_configure_usart1+0x68>)
8002c24: 699b ldr r3, [r3, #24]
8002c26: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002c2a: 607b str r3, [r7, #4]
8002c2c: 687b ldr r3, [r7, #4]
huart1.Instance = USART1;
8002c2e: 4b13 ldr r3, [pc, #76] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c30: 4a13 ldr r2, [pc, #76] @ (8002c80 <rs485_configure_usart1+0x70>)
8002c32: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */
8002c34: 4b11 ldr r3, [pc, #68] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c36: f44f 5216 mov.w r2, #9600 @ 0x2580
8002c3a: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002c3c: 4b0f ldr r3, [pc, #60] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c3e: 2200 movs r2, #0
8002c40: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002c42: 4b0e ldr r3, [pc, #56] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c44: 2200 movs r2, #0
8002c46: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8002c48: 4b0c ldr r3, [pc, #48] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c4a: 2200 movs r2, #0
8002c4c: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002c4e: 4b0b ldr r3, [pc, #44] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c50: 220c movs r2, #12
8002c52: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
8002c54: 4b09 ldr r3, [pc, #36] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c56: 2200 movs r2, #0
8002c58: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8002c5a: 4b08 ldr r3, [pc, #32] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c5c: 2200 movs r2, #0
8002c5e: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002c60: 4806 ldr r0, [pc, #24] @ (8002c7c <rs485_configure_usart1+0x6c>)
8002c62: f003 f8b1 bl 8005dc8 <HAL_UART_Init>
8002c66: 4603 mov r3, r0
8002c68: 2b00 cmp r3, #0
8002c6a: d001 beq.n 8002c70 <rs485_configure_usart1+0x60>
{
/* Initialization Error */
while(1);
8002c6c: bf00 nop
8002c6e: e7fd b.n 8002c6c <rs485_configure_usart1+0x5c>
}
}
8002c70: bf00 nop
8002c72: 3708 adds r7, #8
8002c74: 46bd mov sp, r7
8002c76: bd80 pop {r7, pc}
8002c78: 40021000 .word 0x40021000
8002c7c: 200002c4 .word 0x200002c4
8002c80: 40013800 .word 0x40013800
08002c84 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8002c84: b480 push {r7}
8002c86: b085 sub sp, #20
8002c88: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8002c8a: 4b15 ldr r3, [pc, #84] @ (8002ce0 <HAL_MspInit+0x5c>)
8002c8c: 699b ldr r3, [r3, #24]
8002c8e: 4a14 ldr r2, [pc, #80] @ (8002ce0 <HAL_MspInit+0x5c>)
8002c90: f043 0301 orr.w r3, r3, #1
8002c94: 6193 str r3, [r2, #24]
8002c96: 4b12 ldr r3, [pc, #72] @ (8002ce0 <HAL_MspInit+0x5c>)
8002c98: 699b ldr r3, [r3, #24]
8002c9a: f003 0301 and.w r3, r3, #1
8002c9e: 60bb str r3, [r7, #8]
8002ca0: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8002ca2: 4b0f ldr r3, [pc, #60] @ (8002ce0 <HAL_MspInit+0x5c>)
8002ca4: 69db ldr r3, [r3, #28]
8002ca6: 4a0e ldr r2, [pc, #56] @ (8002ce0 <HAL_MspInit+0x5c>)
8002ca8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002cac: 61d3 str r3, [r2, #28]
8002cae: 4b0c ldr r3, [pc, #48] @ (8002ce0 <HAL_MspInit+0x5c>)
8002cb0: 69db ldr r3, [r3, #28]
8002cb2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002cb6: 607b str r3, [r7, #4]
8002cb8: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8002cba: 4b0a ldr r3, [pc, #40] @ (8002ce4 <HAL_MspInit+0x60>)
8002cbc: 685b ldr r3, [r3, #4]
8002cbe: 60fb str r3, [r7, #12]
8002cc0: 68fb ldr r3, [r7, #12]
8002cc2: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
8002cc6: 60fb str r3, [r7, #12]
8002cc8: 68fb ldr r3, [r7, #12]
8002cca: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002cce: 60fb str r3, [r7, #12]
8002cd0: 4a04 ldr r2, [pc, #16] @ (8002ce4 <HAL_MspInit+0x60>)
8002cd2: 68fb ldr r3, [r7, #12]
8002cd4: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8002cd6: bf00 nop
8002cd8: 3714 adds r7, #20
8002cda: 46bd mov sp, r7
8002cdc: bc80 pop {r7}
8002cde: 4770 bx lr
8002ce0: 40021000 .word 0x40021000
8002ce4: 40010000 .word 0x40010000
08002ce8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8002ce8: b480 push {r7}
8002cea: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8002cec: bf00 nop
8002cee: e7fd b.n 8002cec <NMI_Handler+0x4>
08002cf0 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8002cf0: b480 push {r7}
8002cf2: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8002cf4: bf00 nop
8002cf6: e7fd b.n 8002cf4 <HardFault_Handler+0x4>
08002cf8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8002cf8: b480 push {r7}
8002cfa: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8002cfc: bf00 nop
8002cfe: e7fd b.n 8002cfc <MemManage_Handler+0x4>
08002d00 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8002d00: b480 push {r7}
8002d02: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8002d04: bf00 nop
8002d06: e7fd b.n 8002d04 <BusFault_Handler+0x4>
08002d08 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8002d08: b480 push {r7}
8002d0a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8002d0c: bf00 nop
8002d0e: e7fd b.n 8002d0c <UsageFault_Handler+0x4>
08002d10 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8002d10: b480 push {r7}
8002d12: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8002d14: bf00 nop
8002d16: 46bd mov sp, r7
8002d18: bc80 pop {r7}
8002d1a: 4770 bx lr
08002d1c <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8002d1c: b480 push {r7}
8002d1e: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8002d20: bf00 nop
8002d22: 46bd mov sp, r7
8002d24: bc80 pop {r7}
8002d26: 4770 bx lr
08002d28 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8002d28: b480 push {r7}
8002d2a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8002d2c: bf00 nop
8002d2e: 46bd mov sp, r7
8002d30: bc80 pop {r7}
8002d32: 4770 bx lr
08002d34 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002d34: b580 push {r7, lr}
8002d36: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002d38: f000 f97a bl 8003030 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8002d3c: bf00 nop
8002d3e: bd80 pop {r7, pc}
08002d40 <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
8002d40: b580 push {r7, lr}
8002d42: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
8002d44: 4802 ldr r0, [pc, #8] @ (8002d50 <TIM3_IRQHandler+0x10>)
8002d46: f002 fcef bl 8005728 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
8002d4a: bf00 nop
8002d4c: bd80 pop {r7, pc}
8002d4e: bf00 nop
8002d50: 2000030c .word 0x2000030c
08002d54 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8002d54: b580 push {r7, lr}
8002d56: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8002d58: 4802 ldr r0, [pc, #8] @ (8002d64 <USART1_IRQHandler+0x10>)
8002d5a: f003 f911 bl 8005f80 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8002d5e: bf00 nop
8002d60: bd80 pop {r7, pc}
8002d62: bf00 nop
8002d64: 20000354 .word 0x20000354
08002d68 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8002d68: b480 push {r7}
8002d6a: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8002d6c: bf00 nop
8002d6e: 46bd mov sp, r7
8002d70: bc80 pop {r7}
8002d72: 4770 bx lr
08002d74 <MX_TIM3_Init>:
TIM_HandleTypeDef htim3;
/* TIM3 init function */
void MX_TIM3_Init(void)
{
8002d74: b580 push {r7, lr}
8002d76: b086 sub sp, #24
8002d78: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8002d7a: f107 0308 add.w r3, r7, #8
8002d7e: 2200 movs r2, #0
8002d80: 601a str r2, [r3, #0]
8002d82: 605a str r2, [r3, #4]
8002d84: 609a str r2, [r3, #8]
8002d86: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8002d88: 463b mov r3, r7
8002d8a: 2200 movs r2, #0
8002d8c: 601a str r2, [r3, #0]
8002d8e: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8002d90: 4b1d ldr r3, [pc, #116] @ (8002e08 <MX_TIM3_Init+0x94>)
8002d92: 4a1e ldr r2, [pc, #120] @ (8002e0c <MX_TIM3_Init+0x98>)
8002d94: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 2;
8002d96: 4b1c ldr r3, [pc, #112] @ (8002e08 <MX_TIM3_Init+0x94>)
8002d98: 2202 movs r2, #2
8002d9a: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8002d9c: 4b1a ldr r3, [pc, #104] @ (8002e08 <MX_TIM3_Init+0x94>)
8002d9e: 2200 movs r2, #0
8002da0: 609a str r2, [r3, #8]
htim3.Init.Period = 999;
8002da2: 4b19 ldr r3, [pc, #100] @ (8002e08 <MX_TIM3_Init+0x94>)
8002da4: f240 32e7 movw r2, #999 @ 0x3e7
8002da8: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8002daa: 4b17 ldr r3, [pc, #92] @ (8002e08 <MX_TIM3_Init+0x94>)
8002dac: 2200 movs r2, #0
8002dae: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
8002db0: 4b15 ldr r3, [pc, #84] @ (8002e08 <MX_TIM3_Init+0x94>)
8002db2: 2280 movs r2, #128 @ 0x80
8002db4: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8002db6: 4814 ldr r0, [pc, #80] @ (8002e08 <MX_TIM3_Init+0x94>)
8002db8: f002 fc14 bl 80055e4 <HAL_TIM_Base_Init>
8002dbc: 4603 mov r3, r0
8002dbe: 2b00 cmp r3, #0
8002dc0: d001 beq.n 8002dc6 <MX_TIM3_Init+0x52>
{
Error_Handler();
8002dc2: f7ff fe65 bl 8002a90 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8002dc6: f44f 5380 mov.w r3, #4096 @ 0x1000
8002dca: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8002dcc: f107 0308 add.w r3, r7, #8
8002dd0: 4619 mov r1, r3
8002dd2: 480d ldr r0, [pc, #52] @ (8002e08 <MX_TIM3_Init+0x94>)
8002dd4: f002 fd98 bl 8005908 <HAL_TIM_ConfigClockSource>
8002dd8: 4603 mov r3, r0
8002dda: 2b00 cmp r3, #0
8002ddc: d001 beq.n 8002de2 <MX_TIM3_Init+0x6e>
{
Error_Handler();
8002dde: f7ff fe57 bl 8002a90 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8002de2: 2300 movs r3, #0
8002de4: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8002de6: 2300 movs r3, #0
8002de8: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8002dea: 463b mov r3, r7
8002dec: 4619 mov r1, r3
8002dee: 4806 ldr r0, [pc, #24] @ (8002e08 <MX_TIM3_Init+0x94>)
8002df0: f002 ff7a bl 8005ce8 <HAL_TIMEx_MasterConfigSynchronization>
8002df4: 4603 mov r3, r0
8002df6: 2b00 cmp r3, #0
8002df8: d001 beq.n 8002dfe <MX_TIM3_Init+0x8a>
{
Error_Handler();
8002dfa: f7ff fe49 bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
8002dfe: bf00 nop
8002e00: 3718 adds r7, #24
8002e02: 46bd mov sp, r7
8002e04: bd80 pop {r7, pc}
8002e06: bf00 nop
8002e08: 2000030c .word 0x2000030c
8002e0c: 40000400 .word 0x40000400
08002e10 <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
8002e10: b580 push {r7, lr}
8002e12: b084 sub sp, #16
8002e14: af00 add r7, sp, #0
8002e16: 6078 str r0, [r7, #4]
if(tim_baseHandle->Instance==TIM3)
8002e18: 687b ldr r3, [r7, #4]
8002e1a: 681b ldr r3, [r3, #0]
8002e1c: 4a0d ldr r2, [pc, #52] @ (8002e54 <HAL_TIM_Base_MspInit+0x44>)
8002e1e: 4293 cmp r3, r2
8002e20: d113 bne.n 8002e4a <HAL_TIM_Base_MspInit+0x3a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
8002e22: 4b0d ldr r3, [pc, #52] @ (8002e58 <HAL_TIM_Base_MspInit+0x48>)
8002e24: 69db ldr r3, [r3, #28]
8002e26: 4a0c ldr r2, [pc, #48] @ (8002e58 <HAL_TIM_Base_MspInit+0x48>)
8002e28: f043 0302 orr.w r3, r3, #2
8002e2c: 61d3 str r3, [r2, #28]
8002e2e: 4b0a ldr r3, [pc, #40] @ (8002e58 <HAL_TIM_Base_MspInit+0x48>)
8002e30: 69db ldr r3, [r3, #28]
8002e32: f003 0302 and.w r3, r3, #2
8002e36: 60fb str r3, [r7, #12]
8002e38: 68fb ldr r3, [r7, #12]
/* TIM3 interrupt Init */
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
8002e3a: 2200 movs r2, #0
8002e3c: 2100 movs r1, #0
8002e3e: 201d movs r0, #29
8002e40: f000 fc1f bl 8003682 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
8002e44: 201d movs r0, #29
8002e46: f000 fc38 bl 80036ba <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
8002e4a: bf00 nop
8002e4c: 3710 adds r7, #16
8002e4e: 46bd mov sp, r7
8002e50: bd80 pop {r7, pc}
8002e52: bf00 nop
8002e54: 40000400 .word 0x40000400
8002e58: 40021000 .word 0x40021000
08002e5c <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8002e5c: b580 push {r7, lr}
8002e5e: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8002e60: 4b11 ldr r3, [pc, #68] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e62: 4a12 ldr r2, [pc, #72] @ (8002eac <MX_USART1_UART_Init+0x50>)
8002e64: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8002e66: 4b10 ldr r3, [pc, #64] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e68: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8002e6c: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002e6e: 4b0e ldr r3, [pc, #56] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e70: 2200 movs r2, #0
8002e72: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002e74: 4b0c ldr r3, [pc, #48] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e76: 2200 movs r2, #0
8002e78: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8002e7a: 4b0b ldr r3, [pc, #44] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e7c: 2200 movs r2, #0
8002e7e: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002e80: 4b09 ldr r3, [pc, #36] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e82: 220c movs r2, #12
8002e84: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8002e86: 4b08 ldr r3, [pc, #32] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e88: 2200 movs r2, #0
8002e8a: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8002e8c: 4b06 ldr r3, [pc, #24] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e8e: 2200 movs r2, #0
8002e90: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002e92: 4805 ldr r0, [pc, #20] @ (8002ea8 <MX_USART1_UART_Init+0x4c>)
8002e94: f002 ff98 bl 8005dc8 <HAL_UART_Init>
8002e98: 4603 mov r3, r0
8002e9a: 2b00 cmp r3, #0
8002e9c: d001 beq.n 8002ea2 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8002e9e: f7ff fdf7 bl 8002a90 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8002ea2: bf00 nop
8002ea4: bd80 pop {r7, pc}
8002ea6: bf00 nop
8002ea8: 20000354 .word 0x20000354
8002eac: 40013800 .word 0x40013800
08002eb0 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8002eb0: b580 push {r7, lr}
8002eb2: b088 sub sp, #32
8002eb4: af00 add r7, sp, #0
8002eb6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002eb8: f107 0310 add.w r3, r7, #16
8002ebc: 2200 movs r2, #0
8002ebe: 601a str r2, [r3, #0]
8002ec0: 605a str r2, [r3, #4]
8002ec2: 609a str r2, [r3, #8]
8002ec4: 60da str r2, [r3, #12]
if(uartHandle->Instance==USART1)
8002ec6: 687b ldr r3, [r7, #4]
8002ec8: 681b ldr r3, [r3, #0]
8002eca: 4a20 ldr r2, [pc, #128] @ (8002f4c <HAL_UART_MspInit+0x9c>)
8002ecc: 4293 cmp r3, r2
8002ece: d139 bne.n 8002f44 <HAL_UART_MspInit+0x94>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8002ed0: 4b1f ldr r3, [pc, #124] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002ed2: 699b ldr r3, [r3, #24]
8002ed4: 4a1e ldr r2, [pc, #120] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002ed6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002eda: 6193 str r3, [r2, #24]
8002edc: 4b1c ldr r3, [pc, #112] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002ede: 699b ldr r3, [r3, #24]
8002ee0: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002ee4: 60fb str r3, [r7, #12]
8002ee6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8002ee8: 4b19 ldr r3, [pc, #100] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002eea: 699b ldr r3, [r3, #24]
8002eec: 4a18 ldr r2, [pc, #96] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002eee: f043 0304 orr.w r3, r3, #4
8002ef2: 6193 str r3, [r2, #24]
8002ef4: 4b16 ldr r3, [pc, #88] @ (8002f50 <HAL_UART_MspInit+0xa0>)
8002ef6: 699b ldr r3, [r3, #24]
8002ef8: f003 0304 and.w r3, r3, #4
8002efc: 60bb str r3, [r7, #8]
8002efe: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = TX_RS485_Pin;
8002f00: f44f 7300 mov.w r3, #512 @ 0x200
8002f04: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8002f06: 2302 movs r3, #2
8002f08: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
8002f0a: 2301 movs r3, #1
8002f0c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
8002f0e: f107 0310 add.w r3, r7, #16
8002f12: 4619 mov r1, r3
8002f14: 480f ldr r0, [pc, #60] @ (8002f54 <HAL_UART_MspInit+0xa4>)
8002f16: f000 fc9d bl 8003854 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RX_RS485_Pin;
8002f1a: f44f 6380 mov.w r3, #1024 @ 0x400
8002f1e: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002f20: 2300 movs r3, #0
8002f22: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002f24: 2300 movs r3, #0
8002f26: 61bb str r3, [r7, #24]
HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
8002f28: f107 0310 add.w r3, r7, #16
8002f2c: 4619 mov r1, r3
8002f2e: 4809 ldr r0, [pc, #36] @ (8002f54 <HAL_UART_MspInit+0xa4>)
8002f30: f000 fc90 bl 8003854 <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8002f34: 2200 movs r2, #0
8002f36: 2100 movs r1, #0
8002f38: 2025 movs r0, #37 @ 0x25
8002f3a: f000 fba2 bl 8003682 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8002f3e: 2025 movs r0, #37 @ 0x25
8002f40: f000 fbbb bl 80036ba <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8002f44: bf00 nop
8002f46: 3720 adds r7, #32
8002f48: 46bd mov sp, r7
8002f4a: bd80 pop {r7, pc}
8002f4c: 40013800 .word 0x40013800
8002f50: 40021000 .word 0x40021000
8002f54: 40010800 .word 0x40010800
08002f58 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8002f58: f7ff ff06 bl 8002d68 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8002f5c: 480b ldr r0, [pc, #44] @ (8002f8c <LoopFillZerobss+0xe>)
ldr r1, =_edata
8002f5e: 490c ldr r1, [pc, #48] @ (8002f90 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8002f60: 4a0c ldr r2, [pc, #48] @ (8002f94 <LoopFillZerobss+0x16>)
movs r3, #0
8002f62: 2300 movs r3, #0
b LoopCopyDataInit
8002f64: e002 b.n 8002f6c <LoopCopyDataInit>
08002f66 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8002f66: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8002f68: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8002f6a: 3304 adds r3, #4
08002f6c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002f6c: 18c4 adds r4, r0, r3
cmp r4, r1
8002f6e: 428c cmp r4, r1
bcc CopyDataInit
8002f70: d3f9 bcc.n 8002f66 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8002f72: 4a09 ldr r2, [pc, #36] @ (8002f98 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8002f74: 4c09 ldr r4, [pc, #36] @ (8002f9c <LoopFillZerobss+0x1e>)
movs r3, #0
8002f76: 2300 movs r3, #0
b LoopFillZerobss
8002f78: e001 b.n 8002f7e <LoopFillZerobss>
08002f7a <FillZerobss>:
FillZerobss:
str r3, [r2]
8002f7a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002f7c: 3204 adds r2, #4
08002f7e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002f7e: 42a2 cmp r2, r4
bcc FillZerobss
8002f80: d3fb bcc.n 8002f7a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8002f82: f003 fd45 bl 8006a10 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8002f86: f7ff f9e1 bl 800234c <main>
bx lr
8002f8a: 4770 bx lr
ldr r0, =_sdata
8002f8c: 20000000 .word 0x20000000
ldr r1, =_edata
8002f90: 20000060 .word 0x20000060
ldr r2, =_sidata
8002f94: 08006c6c .word 0x08006c6c
ldr r2, =_sbss
8002f98: 20000060 .word 0x20000060
ldr r4, =_ebss
8002f9c: 200004d8 .word 0x200004d8
08002fa0 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002fa0: e7fe b.n 8002fa0 <ADC1_2_IRQHandler>
...
08002fa4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8002fa4: b580 push {r7, lr}
8002fa6: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002fa8: 4b08 ldr r3, [pc, #32] @ (8002fcc <HAL_Init+0x28>)
8002faa: 681b ldr r3, [r3, #0]
8002fac: 4a07 ldr r2, [pc, #28] @ (8002fcc <HAL_Init+0x28>)
8002fae: f043 0310 orr.w r3, r3, #16
8002fb2: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8002fb4: 2003 movs r0, #3
8002fb6: f000 fb59 bl 800366c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002fba: 200f movs r0, #15
8002fbc: f000 f808 bl 8002fd0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002fc0: f7ff fe60 bl 8002c84 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8002fc4: 2300 movs r3, #0
}
8002fc6: 4618 mov r0, r3
8002fc8: bd80 pop {r7, pc}
8002fca: bf00 nop
8002fcc: 40022000 .word 0x40022000
08002fd0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002fd0: b580 push {r7, lr}
8002fd2: b082 sub sp, #8
8002fd4: af00 add r7, sp, #0
8002fd6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002fd8: 4b12 ldr r3, [pc, #72] @ (8003024 <HAL_InitTick+0x54>)
8002fda: 681a ldr r2, [r3, #0]
8002fdc: 4b12 ldr r3, [pc, #72] @ (8003028 <HAL_InitTick+0x58>)
8002fde: 781b ldrb r3, [r3, #0]
8002fe0: 4619 mov r1, r3
8002fe2: f44f 737a mov.w r3, #1000 @ 0x3e8
8002fe6: fbb3 f3f1 udiv r3, r3, r1
8002fea: fbb2 f3f3 udiv r3, r2, r3
8002fee: 4618 mov r0, r3
8002ff0: f000 fb71 bl 80036d6 <HAL_SYSTICK_Config>
8002ff4: 4603 mov r3, r0
8002ff6: 2b00 cmp r3, #0
8002ff8: d001 beq.n 8002ffe <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002ffa: 2301 movs r3, #1
8002ffc: e00e b.n 800301c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002ffe: 687b ldr r3, [r7, #4]
8003000: 2b0f cmp r3, #15
8003002: d80a bhi.n 800301a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8003004: 2200 movs r2, #0
8003006: 6879 ldr r1, [r7, #4]
8003008: f04f 30ff mov.w r0, #4294967295
800300c: f000 fb39 bl 8003682 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8003010: 4a06 ldr r2, [pc, #24] @ (800302c <HAL_InitTick+0x5c>)
8003012: 687b ldr r3, [r7, #4]
8003014: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8003016: 2300 movs r3, #0
8003018: e000 b.n 800301c <HAL_InitTick+0x4c>
return HAL_ERROR;
800301a: 2301 movs r3, #1
}
800301c: 4618 mov r0, r3
800301e: 3708 adds r7, #8
8003020: 46bd mov sp, r7
8003022: bd80 pop {r7, pc}
8003024: 20000004 .word 0x20000004
8003028: 2000000c .word 0x2000000c
800302c: 20000008 .word 0x20000008
08003030 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8003030: b480 push {r7}
8003032: af00 add r7, sp, #0
uwTick += uwTickFreq;
8003034: 4b05 ldr r3, [pc, #20] @ (800304c <HAL_IncTick+0x1c>)
8003036: 781b ldrb r3, [r3, #0]
8003038: 461a mov r2, r3
800303a: 4b05 ldr r3, [pc, #20] @ (8003050 <HAL_IncTick+0x20>)
800303c: 681b ldr r3, [r3, #0]
800303e: 4413 add r3, r2
8003040: 4a03 ldr r2, [pc, #12] @ (8003050 <HAL_IncTick+0x20>)
8003042: 6013 str r3, [r2, #0]
}
8003044: bf00 nop
8003046: 46bd mov sp, r7
8003048: bc80 pop {r7}
800304a: 4770 bx lr
800304c: 2000000c .word 0x2000000c
8003050: 2000039c .word 0x2000039c
08003054 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8003054: b480 push {r7}
8003056: af00 add r7, sp, #0
return uwTick;
8003058: 4b02 ldr r3, [pc, #8] @ (8003064 <HAL_GetTick+0x10>)
800305a: 681b ldr r3, [r3, #0]
}
800305c: 4618 mov r0, r3
800305e: 46bd mov sp, r7
8003060: bc80 pop {r7}
8003062: 4770 bx lr
8003064: 2000039c .word 0x2000039c
08003068 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8003068: b580 push {r7, lr}
800306a: b084 sub sp, #16
800306c: af00 add r7, sp, #0
800306e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8003070: f7ff fff0 bl 8003054 <HAL_GetTick>
8003074: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8003076: 687b ldr r3, [r7, #4]
8003078: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
800307a: 68fb ldr r3, [r7, #12]
800307c: f1b3 3fff cmp.w r3, #4294967295
8003080: d005 beq.n 800308e <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8003082: 4b0a ldr r3, [pc, #40] @ (80030ac <HAL_Delay+0x44>)
8003084: 781b ldrb r3, [r3, #0]
8003086: 461a mov r2, r3
8003088: 68fb ldr r3, [r7, #12]
800308a: 4413 add r3, r2
800308c: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800308e: bf00 nop
8003090: f7ff ffe0 bl 8003054 <HAL_GetTick>
8003094: 4602 mov r2, r0
8003096: 68bb ldr r3, [r7, #8]
8003098: 1ad3 subs r3, r2, r3
800309a: 68fa ldr r2, [r7, #12]
800309c: 429a cmp r2, r3
800309e: d8f7 bhi.n 8003090 <HAL_Delay+0x28>
{
}
}
80030a0: bf00 nop
80030a2: bf00 nop
80030a4: 3710 adds r7, #16
80030a6: 46bd mov sp, r7
80030a8: bd80 pop {r7, pc}
80030aa: bf00 nop
80030ac: 2000000c .word 0x2000000c
080030b0 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80030b0: b580 push {r7, lr}
80030b2: b086 sub sp, #24
80030b4: af00 add r7, sp, #0
80030b6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80030b8: 2300 movs r3, #0
80030ba: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
80030bc: 2300 movs r3, #0
80030be: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
80030c0: 2300 movs r3, #0
80030c2: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
80030c4: 2300 movs r3, #0
80030c6: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
80030c8: 687b ldr r3, [r7, #4]
80030ca: 2b00 cmp r3, #0
80030cc: d101 bne.n 80030d2 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
80030ce: 2301 movs r3, #1
80030d0: e0be b.n 8003250 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80030d2: 687b ldr r3, [r7, #4]
80030d4: 689b ldr r3, [r3, #8]
80030d6: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
80030d8: 687b ldr r3, [r7, #4]
80030da: 6a9b ldr r3, [r3, #40] @ 0x28
80030dc: 2b00 cmp r3, #0
80030de: d109 bne.n 80030f4 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80030e0: 687b ldr r3, [r7, #4]
80030e2: 2200 movs r2, #0
80030e4: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80030e6: 687b ldr r3, [r7, #4]
80030e8: 2200 movs r2, #0
80030ea: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80030ee: 6878 ldr r0, [r7, #4]
80030f0: f7fe fc2a bl 8001948 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
80030f4: 6878 ldr r0, [r7, #4]
80030f6: f000 f9ab bl 8003450 <ADC_ConversionStop_Disable>
80030fa: 4603 mov r3, r0
80030fc: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
80030fe: 687b ldr r3, [r7, #4]
8003100: 6a9b ldr r3, [r3, #40] @ 0x28
8003102: f003 0310 and.w r3, r3, #16
8003106: 2b00 cmp r3, #0
8003108: f040 8099 bne.w 800323e <HAL_ADC_Init+0x18e>
800310c: 7dfb ldrb r3, [r7, #23]
800310e: 2b00 cmp r3, #0
8003110: f040 8095 bne.w 800323e <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003114: 687b ldr r3, [r7, #4]
8003116: 6a9b ldr r3, [r3, #40] @ 0x28
8003118: f423 5388 bic.w r3, r3, #4352 @ 0x1100
800311c: f023 0302 bic.w r3, r3, #2
8003120: f043 0202 orr.w r2, r3, #2
8003124: 687b ldr r3, [r7, #4]
8003126: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8003128: 687b ldr r3, [r7, #4]
800312a: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
800312c: 687b ldr r3, [r7, #4]
800312e: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8003130: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8003132: 687b ldr r3, [r7, #4]
8003134: 7b1b ldrb r3, [r3, #12]
8003136: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8003138: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
800313a: 68ba ldr r2, [r7, #8]
800313c: 4313 orrs r3, r2
800313e: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8003140: 687b ldr r3, [r7, #4]
8003142: 689b ldr r3, [r3, #8]
8003144: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003148: d003 beq.n 8003152 <HAL_ADC_Init+0xa2>
800314a: 687b ldr r3, [r7, #4]
800314c: 689b ldr r3, [r3, #8]
800314e: 2b01 cmp r3, #1
8003150: d102 bne.n 8003158 <HAL_ADC_Init+0xa8>
8003152: f44f 7380 mov.w r3, #256 @ 0x100
8003156: e000 b.n 800315a <HAL_ADC_Init+0xaa>
8003158: 2300 movs r3, #0
800315a: 693a ldr r2, [r7, #16]
800315c: 4313 orrs r3, r2
800315e: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8003160: 687b ldr r3, [r7, #4]
8003162: 7d1b ldrb r3, [r3, #20]
8003164: 2b01 cmp r3, #1
8003166: d119 bne.n 800319c <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8003168: 687b ldr r3, [r7, #4]
800316a: 7b1b ldrb r3, [r3, #12]
800316c: 2b00 cmp r3, #0
800316e: d109 bne.n 8003184 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8003170: 687b ldr r3, [r7, #4]
8003172: 699b ldr r3, [r3, #24]
8003174: 3b01 subs r3, #1
8003176: 035a lsls r2, r3, #13
8003178: 693b ldr r3, [r7, #16]
800317a: 4313 orrs r3, r2
800317c: f443 6300 orr.w r3, r3, #2048 @ 0x800
8003180: 613b str r3, [r7, #16]
8003182: e00b b.n 800319c <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003184: 687b ldr r3, [r7, #4]
8003186: 6a9b ldr r3, [r3, #40] @ 0x28
8003188: f043 0220 orr.w r2, r3, #32
800318c: 687b ldr r3, [r7, #4]
800318e: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003190: 687b ldr r3, [r7, #4]
8003192: 6adb ldr r3, [r3, #44] @ 0x2c
8003194: f043 0201 orr.w r2, r3, #1
8003198: 687b ldr r3, [r7, #4]
800319a: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
800319c: 687b ldr r3, [r7, #4]
800319e: 681b ldr r3, [r3, #0]
80031a0: 685b ldr r3, [r3, #4]
80031a2: f423 4169 bic.w r1, r3, #59648 @ 0xe900
80031a6: 687b ldr r3, [r7, #4]
80031a8: 681b ldr r3, [r3, #0]
80031aa: 693a ldr r2, [r7, #16]
80031ac: 430a orrs r2, r1
80031ae: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
80031b0: 687b ldr r3, [r7, #4]
80031b2: 681b ldr r3, [r3, #0]
80031b4: 689a ldr r2, [r3, #8]
80031b6: 4b28 ldr r3, [pc, #160] @ (8003258 <HAL_ADC_Init+0x1a8>)
80031b8: 4013 ands r3, r2
80031ba: 687a ldr r2, [r7, #4]
80031bc: 6812 ldr r2, [r2, #0]
80031be: 68b9 ldr r1, [r7, #8]
80031c0: 430b orrs r3, r1
80031c2: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
80031c4: 687b ldr r3, [r7, #4]
80031c6: 689b ldr r3, [r3, #8]
80031c8: f5b3 7f80 cmp.w r3, #256 @ 0x100
80031cc: d003 beq.n 80031d6 <HAL_ADC_Init+0x126>
80031ce: 687b ldr r3, [r7, #4]
80031d0: 689b ldr r3, [r3, #8]
80031d2: 2b01 cmp r3, #1
80031d4: d104 bne.n 80031e0 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
80031d6: 687b ldr r3, [r7, #4]
80031d8: 691b ldr r3, [r3, #16]
80031da: 3b01 subs r3, #1
80031dc: 051b lsls r3, r3, #20
80031de: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
80031e0: 687b ldr r3, [r7, #4]
80031e2: 681b ldr r3, [r3, #0]
80031e4: 6adb ldr r3, [r3, #44] @ 0x2c
80031e6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
80031ea: 687b ldr r3, [r7, #4]
80031ec: 681b ldr r3, [r3, #0]
80031ee: 68fa ldr r2, [r7, #12]
80031f0: 430a orrs r2, r1
80031f2: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
80031f4: 687b ldr r3, [r7, #4]
80031f6: 681b ldr r3, [r3, #0]
80031f8: 689a ldr r2, [r3, #8]
80031fa: 4b18 ldr r3, [pc, #96] @ (800325c <HAL_ADC_Init+0x1ac>)
80031fc: 4013 ands r3, r2
80031fe: 68ba ldr r2, [r7, #8]
8003200: 429a cmp r2, r3
8003202: d10b bne.n 800321c <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8003204: 687b ldr r3, [r7, #4]
8003206: 2200 movs r2, #0
8003208: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800320a: 687b ldr r3, [r7, #4]
800320c: 6a9b ldr r3, [r3, #40] @ 0x28
800320e: f023 0303 bic.w r3, r3, #3
8003212: f043 0201 orr.w r2, r3, #1
8003216: 687b ldr r3, [r7, #4]
8003218: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800321a: e018 b.n 800324e <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800321c: 687b ldr r3, [r7, #4]
800321e: 6a9b ldr r3, [r3, #40] @ 0x28
8003220: f023 0312 bic.w r3, r3, #18
8003224: f043 0210 orr.w r2, r3, #16
8003228: 687b ldr r3, [r7, #4]
800322a: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800322c: 687b ldr r3, [r7, #4]
800322e: 6adb ldr r3, [r3, #44] @ 0x2c
8003230: f043 0201 orr.w r2, r3, #1
8003234: 687b ldr r3, [r7, #4]
8003236: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8003238: 2301 movs r3, #1
800323a: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800323c: e007 b.n 800324e <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800323e: 687b ldr r3, [r7, #4]
8003240: 6a9b ldr r3, [r3, #40] @ 0x28
8003242: f043 0210 orr.w r2, r3, #16
8003246: 687b ldr r3, [r7, #4]
8003248: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800324a: 2301 movs r3, #1
800324c: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800324e: 7dfb ldrb r3, [r7, #23]
}
8003250: 4618 mov r0, r3
8003252: 3718 adds r7, #24
8003254: 46bd mov sp, r7
8003256: bd80 pop {r7, pc}
8003258: ffe1f7fd .word 0xffe1f7fd
800325c: ff1f0efe .word 0xff1f0efe
08003260 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8003260: b480 push {r7}
8003262: b085 sub sp, #20
8003264: af00 add r7, sp, #0
8003266: 6078 str r0, [r7, #4]
8003268: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800326a: 2300 movs r3, #0
800326c: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
800326e: 2300 movs r3, #0
8003270: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8003272: 687b ldr r3, [r7, #4]
8003274: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8003278: 2b01 cmp r3, #1
800327a: d101 bne.n 8003280 <HAL_ADC_ConfigChannel+0x20>
800327c: 2302 movs r3, #2
800327e: e0dc b.n 800343a <HAL_ADC_ConfigChannel+0x1da>
8003280: 687b ldr r3, [r7, #4]
8003282: 2201 movs r2, #1
8003284: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
8003288: 683b ldr r3, [r7, #0]
800328a: 685b ldr r3, [r3, #4]
800328c: 2b06 cmp r3, #6
800328e: d81c bhi.n 80032ca <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8003290: 687b ldr r3, [r7, #4]
8003292: 681b ldr r3, [r3, #0]
8003294: 6b59 ldr r1, [r3, #52] @ 0x34
8003296: 683b ldr r3, [r7, #0]
8003298: 685a ldr r2, [r3, #4]
800329a: 4613 mov r3, r2
800329c: 009b lsls r3, r3, #2
800329e: 4413 add r3, r2
80032a0: 3b05 subs r3, #5
80032a2: 221f movs r2, #31
80032a4: fa02 f303 lsl.w r3, r2, r3
80032a8: 43db mvns r3, r3
80032aa: 4019 ands r1, r3
80032ac: 683b ldr r3, [r7, #0]
80032ae: 6818 ldr r0, [r3, #0]
80032b0: 683b ldr r3, [r7, #0]
80032b2: 685a ldr r2, [r3, #4]
80032b4: 4613 mov r3, r2
80032b6: 009b lsls r3, r3, #2
80032b8: 4413 add r3, r2
80032ba: 3b05 subs r3, #5
80032bc: fa00 f203 lsl.w r2, r0, r3
80032c0: 687b ldr r3, [r7, #4]
80032c2: 681b ldr r3, [r3, #0]
80032c4: 430a orrs r2, r1
80032c6: 635a str r2, [r3, #52] @ 0x34
80032c8: e03c b.n 8003344 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
80032ca: 683b ldr r3, [r7, #0]
80032cc: 685b ldr r3, [r3, #4]
80032ce: 2b0c cmp r3, #12
80032d0: d81c bhi.n 800330c <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
80032d2: 687b ldr r3, [r7, #4]
80032d4: 681b ldr r3, [r3, #0]
80032d6: 6b19 ldr r1, [r3, #48] @ 0x30
80032d8: 683b ldr r3, [r7, #0]
80032da: 685a ldr r2, [r3, #4]
80032dc: 4613 mov r3, r2
80032de: 009b lsls r3, r3, #2
80032e0: 4413 add r3, r2
80032e2: 3b23 subs r3, #35 @ 0x23
80032e4: 221f movs r2, #31
80032e6: fa02 f303 lsl.w r3, r2, r3
80032ea: 43db mvns r3, r3
80032ec: 4019 ands r1, r3
80032ee: 683b ldr r3, [r7, #0]
80032f0: 6818 ldr r0, [r3, #0]
80032f2: 683b ldr r3, [r7, #0]
80032f4: 685a ldr r2, [r3, #4]
80032f6: 4613 mov r3, r2
80032f8: 009b lsls r3, r3, #2
80032fa: 4413 add r3, r2
80032fc: 3b23 subs r3, #35 @ 0x23
80032fe: fa00 f203 lsl.w r2, r0, r3
8003302: 687b ldr r3, [r7, #4]
8003304: 681b ldr r3, [r3, #0]
8003306: 430a orrs r2, r1
8003308: 631a str r2, [r3, #48] @ 0x30
800330a: e01b b.n 8003344 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
800330c: 687b ldr r3, [r7, #4]
800330e: 681b ldr r3, [r3, #0]
8003310: 6ad9 ldr r1, [r3, #44] @ 0x2c
8003312: 683b ldr r3, [r7, #0]
8003314: 685a ldr r2, [r3, #4]
8003316: 4613 mov r3, r2
8003318: 009b lsls r3, r3, #2
800331a: 4413 add r3, r2
800331c: 3b41 subs r3, #65 @ 0x41
800331e: 221f movs r2, #31
8003320: fa02 f303 lsl.w r3, r2, r3
8003324: 43db mvns r3, r3
8003326: 4019 ands r1, r3
8003328: 683b ldr r3, [r7, #0]
800332a: 6818 ldr r0, [r3, #0]
800332c: 683b ldr r3, [r7, #0]
800332e: 685a ldr r2, [r3, #4]
8003330: 4613 mov r3, r2
8003332: 009b lsls r3, r3, #2
8003334: 4413 add r3, r2
8003336: 3b41 subs r3, #65 @ 0x41
8003338: fa00 f203 lsl.w r2, r0, r3
800333c: 687b ldr r3, [r7, #4]
800333e: 681b ldr r3, [r3, #0]
8003340: 430a orrs r2, r1
8003342: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8003344: 683b ldr r3, [r7, #0]
8003346: 681b ldr r3, [r3, #0]
8003348: 2b09 cmp r3, #9
800334a: d91c bls.n 8003386 <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
800334c: 687b ldr r3, [r7, #4]
800334e: 681b ldr r3, [r3, #0]
8003350: 68d9 ldr r1, [r3, #12]
8003352: 683b ldr r3, [r7, #0]
8003354: 681a ldr r2, [r3, #0]
8003356: 4613 mov r3, r2
8003358: 005b lsls r3, r3, #1
800335a: 4413 add r3, r2
800335c: 3b1e subs r3, #30
800335e: 2207 movs r2, #7
8003360: fa02 f303 lsl.w r3, r2, r3
8003364: 43db mvns r3, r3
8003366: 4019 ands r1, r3
8003368: 683b ldr r3, [r7, #0]
800336a: 6898 ldr r0, [r3, #8]
800336c: 683b ldr r3, [r7, #0]
800336e: 681a ldr r2, [r3, #0]
8003370: 4613 mov r3, r2
8003372: 005b lsls r3, r3, #1
8003374: 4413 add r3, r2
8003376: 3b1e subs r3, #30
8003378: fa00 f203 lsl.w r2, r0, r3
800337c: 687b ldr r3, [r7, #4]
800337e: 681b ldr r3, [r3, #0]
8003380: 430a orrs r2, r1
8003382: 60da str r2, [r3, #12]
8003384: e019 b.n 80033ba <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
8003386: 687b ldr r3, [r7, #4]
8003388: 681b ldr r3, [r3, #0]
800338a: 6919 ldr r1, [r3, #16]
800338c: 683b ldr r3, [r7, #0]
800338e: 681a ldr r2, [r3, #0]
8003390: 4613 mov r3, r2
8003392: 005b lsls r3, r3, #1
8003394: 4413 add r3, r2
8003396: 2207 movs r2, #7
8003398: fa02 f303 lsl.w r3, r2, r3
800339c: 43db mvns r3, r3
800339e: 4019 ands r1, r3
80033a0: 683b ldr r3, [r7, #0]
80033a2: 6898 ldr r0, [r3, #8]
80033a4: 683b ldr r3, [r7, #0]
80033a6: 681a ldr r2, [r3, #0]
80033a8: 4613 mov r3, r2
80033aa: 005b lsls r3, r3, #1
80033ac: 4413 add r3, r2
80033ae: fa00 f203 lsl.w r2, r0, r3
80033b2: 687b ldr r3, [r7, #4]
80033b4: 681b ldr r3, [r3, #0]
80033b6: 430a orrs r2, r1
80033b8: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80033ba: 683b ldr r3, [r7, #0]
80033bc: 681b ldr r3, [r3, #0]
80033be: 2b10 cmp r3, #16
80033c0: d003 beq.n 80033ca <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
80033c2: 683b ldr r3, [r7, #0]
80033c4: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80033c6: 2b11 cmp r3, #17
80033c8: d132 bne.n 8003430 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
80033ca: 687b ldr r3, [r7, #4]
80033cc: 681b ldr r3, [r3, #0]
80033ce: 4a1d ldr r2, [pc, #116] @ (8003444 <HAL_ADC_ConfigChannel+0x1e4>)
80033d0: 4293 cmp r3, r2
80033d2: d125 bne.n 8003420 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
80033d4: 687b ldr r3, [r7, #4]
80033d6: 681b ldr r3, [r3, #0]
80033d8: 689b ldr r3, [r3, #8]
80033da: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80033de: 2b00 cmp r3, #0
80033e0: d126 bne.n 8003430 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
80033e2: 687b ldr r3, [r7, #4]
80033e4: 681b ldr r3, [r3, #0]
80033e6: 689a ldr r2, [r3, #8]
80033e8: 687b ldr r3, [r7, #4]
80033ea: 681b ldr r3, [r3, #0]
80033ec: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
80033f0: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80033f2: 683b ldr r3, [r7, #0]
80033f4: 681b ldr r3, [r3, #0]
80033f6: 2b10 cmp r3, #16
80033f8: d11a bne.n 8003430 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
80033fa: 4b13 ldr r3, [pc, #76] @ (8003448 <HAL_ADC_ConfigChannel+0x1e8>)
80033fc: 681b ldr r3, [r3, #0]
80033fe: 4a13 ldr r2, [pc, #76] @ (800344c <HAL_ADC_ConfigChannel+0x1ec>)
8003400: fba2 2303 umull r2, r3, r2, r3
8003404: 0c9a lsrs r2, r3, #18
8003406: 4613 mov r3, r2
8003408: 009b lsls r3, r3, #2
800340a: 4413 add r3, r2
800340c: 005b lsls r3, r3, #1
800340e: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003410: e002 b.n 8003418 <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8003412: 68bb ldr r3, [r7, #8]
8003414: 3b01 subs r3, #1
8003416: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003418: 68bb ldr r3, [r7, #8]
800341a: 2b00 cmp r3, #0
800341c: d1f9 bne.n 8003412 <HAL_ADC_ConfigChannel+0x1b2>
800341e: e007 b.n 8003430 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003420: 687b ldr r3, [r7, #4]
8003422: 6a9b ldr r3, [r3, #40] @ 0x28
8003424: f043 0220 orr.w r2, r3, #32
8003428: 687b ldr r3, [r7, #4]
800342a: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800342c: 2301 movs r3, #1
800342e: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003430: 687b ldr r3, [r7, #4]
8003432: 2200 movs r2, #0
8003434: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
8003438: 7bfb ldrb r3, [r7, #15]
}
800343a: 4618 mov r0, r3
800343c: 3714 adds r7, #20
800343e: 46bd mov sp, r7
8003440: bc80 pop {r7}
8003442: 4770 bx lr
8003444: 40012400 .word 0x40012400
8003448: 20000004 .word 0x20000004
800344c: 431bde83 .word 0x431bde83
08003450 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8003450: b580 push {r7, lr}
8003452: b084 sub sp, #16
8003454: af00 add r7, sp, #0
8003456: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8003458: 2300 movs r3, #0
800345a: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
800345c: 687b ldr r3, [r7, #4]
800345e: 681b ldr r3, [r3, #0]
8003460: 689b ldr r3, [r3, #8]
8003462: f003 0301 and.w r3, r3, #1
8003466: 2b01 cmp r3, #1
8003468: d12e bne.n 80034c8 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
800346a: 687b ldr r3, [r7, #4]
800346c: 681b ldr r3, [r3, #0]
800346e: 689a ldr r2, [r3, #8]
8003470: 687b ldr r3, [r7, #4]
8003472: 681b ldr r3, [r3, #0]
8003474: f022 0201 bic.w r2, r2, #1
8003478: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
800347a: f7ff fdeb bl 8003054 <HAL_GetTick>
800347e: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8003480: e01b b.n 80034ba <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8003482: f7ff fde7 bl 8003054 <HAL_GetTick>
8003486: 4602 mov r2, r0
8003488: 68fb ldr r3, [r7, #12]
800348a: 1ad3 subs r3, r2, r3
800348c: 2b02 cmp r3, #2
800348e: d914 bls.n 80034ba <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8003490: 687b ldr r3, [r7, #4]
8003492: 681b ldr r3, [r3, #0]
8003494: 689b ldr r3, [r3, #8]
8003496: f003 0301 and.w r3, r3, #1
800349a: 2b01 cmp r3, #1
800349c: d10d bne.n 80034ba <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800349e: 687b ldr r3, [r7, #4]
80034a0: 6a9b ldr r3, [r3, #40] @ 0x28
80034a2: f043 0210 orr.w r2, r3, #16
80034a6: 687b ldr r3, [r7, #4]
80034a8: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80034aa: 687b ldr r3, [r7, #4]
80034ac: 6adb ldr r3, [r3, #44] @ 0x2c
80034ae: f043 0201 orr.w r2, r3, #1
80034b2: 687b ldr r3, [r7, #4]
80034b4: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
80034b6: 2301 movs r3, #1
80034b8: e007 b.n 80034ca <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
80034ba: 687b ldr r3, [r7, #4]
80034bc: 681b ldr r3, [r3, #0]
80034be: 689b ldr r3, [r3, #8]
80034c0: f003 0301 and.w r3, r3, #1
80034c4: 2b01 cmp r3, #1
80034c6: d0dc beq.n 8003482 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
80034c8: 2300 movs r3, #0
}
80034ca: 4618 mov r0, r3
80034cc: 3710 adds r7, #16
80034ce: 46bd mov sp, r7
80034d0: bd80 pop {r7, pc}
...
080034d4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80034d4: b480 push {r7}
80034d6: b085 sub sp, #20
80034d8: af00 add r7, sp, #0
80034da: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80034dc: 687b ldr r3, [r7, #4]
80034de: f003 0307 and.w r3, r3, #7
80034e2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80034e4: 4b0c ldr r3, [pc, #48] @ (8003518 <__NVIC_SetPriorityGrouping+0x44>)
80034e6: 68db ldr r3, [r3, #12]
80034e8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80034ea: 68ba ldr r2, [r7, #8]
80034ec: f64f 03ff movw r3, #63743 @ 0xf8ff
80034f0: 4013 ands r3, r2
80034f2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80034f4: 68fb ldr r3, [r7, #12]
80034f6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80034f8: 68bb ldr r3, [r7, #8]
80034fa: 4313 orrs r3, r2
reg_value = (reg_value |
80034fc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003500: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003504: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8003506: 4a04 ldr r2, [pc, #16] @ (8003518 <__NVIC_SetPriorityGrouping+0x44>)
8003508: 68bb ldr r3, [r7, #8]
800350a: 60d3 str r3, [r2, #12]
}
800350c: bf00 nop
800350e: 3714 adds r7, #20
8003510: 46bd mov sp, r7
8003512: bc80 pop {r7}
8003514: 4770 bx lr
8003516: bf00 nop
8003518: e000ed00 .word 0xe000ed00
0800351c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800351c: b480 push {r7}
800351e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003520: 4b04 ldr r3, [pc, #16] @ (8003534 <__NVIC_GetPriorityGrouping+0x18>)
8003522: 68db ldr r3, [r3, #12]
8003524: 0a1b lsrs r3, r3, #8
8003526: f003 0307 and.w r3, r3, #7
}
800352a: 4618 mov r0, r3
800352c: 46bd mov sp, r7
800352e: bc80 pop {r7}
8003530: 4770 bx lr
8003532: bf00 nop
8003534: e000ed00 .word 0xe000ed00
08003538 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003538: b480 push {r7}
800353a: b083 sub sp, #12
800353c: af00 add r7, sp, #0
800353e: 4603 mov r3, r0
8003540: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003542: f997 3007 ldrsb.w r3, [r7, #7]
8003546: 2b00 cmp r3, #0
8003548: db0b blt.n 8003562 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800354a: 79fb ldrb r3, [r7, #7]
800354c: f003 021f and.w r2, r3, #31
8003550: 4906 ldr r1, [pc, #24] @ (800356c <__NVIC_EnableIRQ+0x34>)
8003552: f997 3007 ldrsb.w r3, [r7, #7]
8003556: 095b lsrs r3, r3, #5
8003558: 2001 movs r0, #1
800355a: fa00 f202 lsl.w r2, r0, r2
800355e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8003562: bf00 nop
8003564: 370c adds r7, #12
8003566: 46bd mov sp, r7
8003568: bc80 pop {r7}
800356a: 4770 bx lr
800356c: e000e100 .word 0xe000e100
08003570 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003570: b480 push {r7}
8003572: b083 sub sp, #12
8003574: af00 add r7, sp, #0
8003576: 4603 mov r3, r0
8003578: 6039 str r1, [r7, #0]
800357a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800357c: f997 3007 ldrsb.w r3, [r7, #7]
8003580: 2b00 cmp r3, #0
8003582: db0a blt.n 800359a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003584: 683b ldr r3, [r7, #0]
8003586: b2da uxtb r2, r3
8003588: 490c ldr r1, [pc, #48] @ (80035bc <__NVIC_SetPriority+0x4c>)
800358a: f997 3007 ldrsb.w r3, [r7, #7]
800358e: 0112 lsls r2, r2, #4
8003590: b2d2 uxtb r2, r2
8003592: 440b add r3, r1
8003594: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003598: e00a b.n 80035b0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800359a: 683b ldr r3, [r7, #0]
800359c: b2da uxtb r2, r3
800359e: 4908 ldr r1, [pc, #32] @ (80035c0 <__NVIC_SetPriority+0x50>)
80035a0: 79fb ldrb r3, [r7, #7]
80035a2: f003 030f and.w r3, r3, #15
80035a6: 3b04 subs r3, #4
80035a8: 0112 lsls r2, r2, #4
80035aa: b2d2 uxtb r2, r2
80035ac: 440b add r3, r1
80035ae: 761a strb r2, [r3, #24]
}
80035b0: bf00 nop
80035b2: 370c adds r7, #12
80035b4: 46bd mov sp, r7
80035b6: bc80 pop {r7}
80035b8: 4770 bx lr
80035ba: bf00 nop
80035bc: e000e100 .word 0xe000e100
80035c0: e000ed00 .word 0xe000ed00
080035c4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80035c4: b480 push {r7}
80035c6: b089 sub sp, #36 @ 0x24
80035c8: af00 add r7, sp, #0
80035ca: 60f8 str r0, [r7, #12]
80035cc: 60b9 str r1, [r7, #8]
80035ce: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80035d0: 68fb ldr r3, [r7, #12]
80035d2: f003 0307 and.w r3, r3, #7
80035d6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80035d8: 69fb ldr r3, [r7, #28]
80035da: f1c3 0307 rsb r3, r3, #7
80035de: 2b04 cmp r3, #4
80035e0: bf28 it cs
80035e2: 2304 movcs r3, #4
80035e4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80035e6: 69fb ldr r3, [r7, #28]
80035e8: 3304 adds r3, #4
80035ea: 2b06 cmp r3, #6
80035ec: d902 bls.n 80035f4 <NVIC_EncodePriority+0x30>
80035ee: 69fb ldr r3, [r7, #28]
80035f0: 3b03 subs r3, #3
80035f2: e000 b.n 80035f6 <NVIC_EncodePriority+0x32>
80035f4: 2300 movs r3, #0
80035f6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80035f8: f04f 32ff mov.w r2, #4294967295
80035fc: 69bb ldr r3, [r7, #24]
80035fe: fa02 f303 lsl.w r3, r2, r3
8003602: 43da mvns r2, r3
8003604: 68bb ldr r3, [r7, #8]
8003606: 401a ands r2, r3
8003608: 697b ldr r3, [r7, #20]
800360a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800360c: f04f 31ff mov.w r1, #4294967295
8003610: 697b ldr r3, [r7, #20]
8003612: fa01 f303 lsl.w r3, r1, r3
8003616: 43d9 mvns r1, r3
8003618: 687b ldr r3, [r7, #4]
800361a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800361c: 4313 orrs r3, r2
);
}
800361e: 4618 mov r0, r3
8003620: 3724 adds r7, #36 @ 0x24
8003622: 46bd mov sp, r7
8003624: bc80 pop {r7}
8003626: 4770 bx lr
08003628 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003628: b580 push {r7, lr}
800362a: b082 sub sp, #8
800362c: af00 add r7, sp, #0
800362e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003630: 687b ldr r3, [r7, #4]
8003632: 3b01 subs r3, #1
8003634: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003638: d301 bcc.n 800363e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800363a: 2301 movs r3, #1
800363c: e00f b.n 800365e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800363e: 4a0a ldr r2, [pc, #40] @ (8003668 <SysTick_Config+0x40>)
8003640: 687b ldr r3, [r7, #4]
8003642: 3b01 subs r3, #1
8003644: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8003646: 210f movs r1, #15
8003648: f04f 30ff mov.w r0, #4294967295
800364c: f7ff ff90 bl 8003570 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003650: 4b05 ldr r3, [pc, #20] @ (8003668 <SysTick_Config+0x40>)
8003652: 2200 movs r2, #0
8003654: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8003656: 4b04 ldr r3, [pc, #16] @ (8003668 <SysTick_Config+0x40>)
8003658: 2207 movs r2, #7
800365a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800365c: 2300 movs r3, #0
}
800365e: 4618 mov r0, r3
8003660: 3708 adds r7, #8
8003662: 46bd mov sp, r7
8003664: bd80 pop {r7, pc}
8003666: bf00 nop
8003668: e000e010 .word 0xe000e010
0800366c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800366c: b580 push {r7, lr}
800366e: b082 sub sp, #8
8003670: af00 add r7, sp, #0
8003672: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003674: 6878 ldr r0, [r7, #4]
8003676: f7ff ff2d bl 80034d4 <__NVIC_SetPriorityGrouping>
}
800367a: bf00 nop
800367c: 3708 adds r7, #8
800367e: 46bd mov sp, r7
8003680: bd80 pop {r7, pc}
08003682 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003682: b580 push {r7, lr}
8003684: b086 sub sp, #24
8003686: af00 add r7, sp, #0
8003688: 4603 mov r3, r0
800368a: 60b9 str r1, [r7, #8]
800368c: 607a str r2, [r7, #4]
800368e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8003690: 2300 movs r3, #0
8003692: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003694: f7ff ff42 bl 800351c <__NVIC_GetPriorityGrouping>
8003698: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800369a: 687a ldr r2, [r7, #4]
800369c: 68b9 ldr r1, [r7, #8]
800369e: 6978 ldr r0, [r7, #20]
80036a0: f7ff ff90 bl 80035c4 <NVIC_EncodePriority>
80036a4: 4602 mov r2, r0
80036a6: f997 300f ldrsb.w r3, [r7, #15]
80036aa: 4611 mov r1, r2
80036ac: 4618 mov r0, r3
80036ae: f7ff ff5f bl 8003570 <__NVIC_SetPriority>
}
80036b2: bf00 nop
80036b4: 3718 adds r7, #24
80036b6: 46bd mov sp, r7
80036b8: bd80 pop {r7, pc}
080036ba <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80036ba: b580 push {r7, lr}
80036bc: b082 sub sp, #8
80036be: af00 add r7, sp, #0
80036c0: 4603 mov r3, r0
80036c2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80036c4: f997 3007 ldrsb.w r3, [r7, #7]
80036c8: 4618 mov r0, r3
80036ca: f7ff ff35 bl 8003538 <__NVIC_EnableIRQ>
}
80036ce: bf00 nop
80036d0: 3708 adds r7, #8
80036d2: 46bd mov sp, r7
80036d4: bd80 pop {r7, pc}
080036d6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80036d6: b580 push {r7, lr}
80036d8: b082 sub sp, #8
80036da: af00 add r7, sp, #0
80036dc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80036de: 6878 ldr r0, [r7, #4]
80036e0: f7ff ffa2 bl 8003628 <SysTick_Config>
80036e4: 4603 mov r3, r0
}
80036e6: 4618 mov r0, r3
80036e8: 3708 adds r7, #8
80036ea: 46bd mov sp, r7
80036ec: bd80 pop {r7, pc}
080036ee <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
80036ee: b480 push {r7}
80036f0: b085 sub sp, #20
80036f2: af00 add r7, sp, #0
80036f4: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80036f6: 2300 movs r3, #0
80036f8: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
80036fa: 687b ldr r3, [r7, #4]
80036fc: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003700: b2db uxtb r3, r3
8003702: 2b02 cmp r3, #2
8003704: d008 beq.n 8003718 <HAL_DMA_Abort+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003706: 687b ldr r3, [r7, #4]
8003708: 2204 movs r2, #4
800370a: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800370c: 687b ldr r3, [r7, #4]
800370e: 2200 movs r2, #0
8003710: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8003714: 2301 movs r3, #1
8003716: e020 b.n 800375a <HAL_DMA_Abort+0x6c>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003718: 687b ldr r3, [r7, #4]
800371a: 681b ldr r3, [r3, #0]
800371c: 681a ldr r2, [r3, #0]
800371e: 687b ldr r3, [r7, #4]
8003720: 681b ldr r3, [r3, #0]
8003722: f022 020e bic.w r2, r2, #14
8003726: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003728: 687b ldr r3, [r7, #4]
800372a: 681b ldr r3, [r3, #0]
800372c: 681a ldr r2, [r3, #0]
800372e: 687b ldr r3, [r7, #4]
8003730: 681b ldr r3, [r3, #0]
8003732: f022 0201 bic.w r2, r2, #1
8003736: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8003738: 687b ldr r3, [r7, #4]
800373a: 6c1a ldr r2, [r3, #64] @ 0x40
800373c: 687b ldr r3, [r7, #4]
800373e: 6bdb ldr r3, [r3, #60] @ 0x3c
8003740: 2101 movs r1, #1
8003742: fa01 f202 lsl.w r2, r1, r2
8003746: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003748: 687b ldr r3, [r7, #4]
800374a: 2201 movs r2, #1
800374c: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003750: 687b ldr r3, [r7, #4]
8003752: 2200 movs r2, #0
8003754: f883 2020 strb.w r2, [r3, #32]
return status;
8003758: 7bfb ldrb r3, [r7, #15]
}
800375a: 4618 mov r0, r3
800375c: 3714 adds r7, #20
800375e: 46bd mov sp, r7
8003760: bc80 pop {r7}
8003762: 4770 bx lr
08003764 <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8003764: b580 push {r7, lr}
8003766: b084 sub sp, #16
8003768: af00 add r7, sp, #0
800376a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800376c: 2300 movs r3, #0
800376e: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8003770: 687b ldr r3, [r7, #4]
8003772: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003776: b2db uxtb r3, r3
8003778: 2b02 cmp r3, #2
800377a: d005 beq.n 8003788 <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800377c: 687b ldr r3, [r7, #4]
800377e: 2204 movs r2, #4
8003780: 639a str r2, [r3, #56] @ 0x38
status = HAL_ERROR;
8003782: 2301 movs r3, #1
8003784: 73fb strb r3, [r7, #15]
8003786: e051 b.n 800382c <HAL_DMA_Abort_IT+0xc8>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003788: 687b ldr r3, [r7, #4]
800378a: 681b ldr r3, [r3, #0]
800378c: 681a ldr r2, [r3, #0]
800378e: 687b ldr r3, [r7, #4]
8003790: 681b ldr r3, [r3, #0]
8003792: f022 020e bic.w r2, r2, #14
8003796: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003798: 687b ldr r3, [r7, #4]
800379a: 681b ldr r3, [r3, #0]
800379c: 681a ldr r2, [r3, #0]
800379e: 687b ldr r3, [r7, #4]
80037a0: 681b ldr r3, [r3, #0]
80037a2: f022 0201 bic.w r2, r2, #1
80037a6: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
80037a8: 687b ldr r3, [r7, #4]
80037aa: 681b ldr r3, [r3, #0]
80037ac: 4a22 ldr r2, [pc, #136] @ (8003838 <HAL_DMA_Abort_IT+0xd4>)
80037ae: 4293 cmp r3, r2
80037b0: d029 beq.n 8003806 <HAL_DMA_Abort_IT+0xa2>
80037b2: 687b ldr r3, [r7, #4]
80037b4: 681b ldr r3, [r3, #0]
80037b6: 4a21 ldr r2, [pc, #132] @ (800383c <HAL_DMA_Abort_IT+0xd8>)
80037b8: 4293 cmp r3, r2
80037ba: d022 beq.n 8003802 <HAL_DMA_Abort_IT+0x9e>
80037bc: 687b ldr r3, [r7, #4]
80037be: 681b ldr r3, [r3, #0]
80037c0: 4a1f ldr r2, [pc, #124] @ (8003840 <HAL_DMA_Abort_IT+0xdc>)
80037c2: 4293 cmp r3, r2
80037c4: d01a beq.n 80037fc <HAL_DMA_Abort_IT+0x98>
80037c6: 687b ldr r3, [r7, #4]
80037c8: 681b ldr r3, [r3, #0]
80037ca: 4a1e ldr r2, [pc, #120] @ (8003844 <HAL_DMA_Abort_IT+0xe0>)
80037cc: 4293 cmp r3, r2
80037ce: d012 beq.n 80037f6 <HAL_DMA_Abort_IT+0x92>
80037d0: 687b ldr r3, [r7, #4]
80037d2: 681b ldr r3, [r3, #0]
80037d4: 4a1c ldr r2, [pc, #112] @ (8003848 <HAL_DMA_Abort_IT+0xe4>)
80037d6: 4293 cmp r3, r2
80037d8: d00a beq.n 80037f0 <HAL_DMA_Abort_IT+0x8c>
80037da: 687b ldr r3, [r7, #4]
80037dc: 681b ldr r3, [r3, #0]
80037de: 4a1b ldr r2, [pc, #108] @ (800384c <HAL_DMA_Abort_IT+0xe8>)
80037e0: 4293 cmp r3, r2
80037e2: d102 bne.n 80037ea <HAL_DMA_Abort_IT+0x86>
80037e4: f44f 1380 mov.w r3, #1048576 @ 0x100000
80037e8: e00e b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
80037ea: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80037ee: e00b b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
80037f0: f44f 3380 mov.w r3, #65536 @ 0x10000
80037f4: e008 b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
80037f6: f44f 5380 mov.w r3, #4096 @ 0x1000
80037fa: e005 b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
80037fc: f44f 7380 mov.w r3, #256 @ 0x100
8003800: e002 b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
8003802: 2310 movs r3, #16
8003804: e000 b.n 8003808 <HAL_DMA_Abort_IT+0xa4>
8003806: 2301 movs r3, #1
8003808: 4a11 ldr r2, [pc, #68] @ (8003850 <HAL_DMA_Abort_IT+0xec>)
800380a: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800380c: 687b ldr r3, [r7, #4]
800380e: 2201 movs r2, #1
8003810: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003814: 687b ldr r3, [r7, #4]
8003816: 2200 movs r2, #0
8003818: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
800381c: 687b ldr r3, [r7, #4]
800381e: 6b5b ldr r3, [r3, #52] @ 0x34
8003820: 2b00 cmp r3, #0
8003822: d003 beq.n 800382c <HAL_DMA_Abort_IT+0xc8>
{
hdma->XferAbortCallback(hdma);
8003824: 687b ldr r3, [r7, #4]
8003826: 6b5b ldr r3, [r3, #52] @ 0x34
8003828: 6878 ldr r0, [r7, #4]
800382a: 4798 blx r3
}
}
return status;
800382c: 7bfb ldrb r3, [r7, #15]
}
800382e: 4618 mov r0, r3
8003830: 3710 adds r7, #16
8003832: 46bd mov sp, r7
8003834: bd80 pop {r7, pc}
8003836: bf00 nop
8003838: 40020008 .word 0x40020008
800383c: 4002001c .word 0x4002001c
8003840: 40020030 .word 0x40020030
8003844: 40020044 .word 0x40020044
8003848: 40020058 .word 0x40020058
800384c: 4002006c .word 0x4002006c
8003850: 40020000 .word 0x40020000
08003854 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003854: b480 push {r7}
8003856: b08b sub sp, #44 @ 0x2c
8003858: af00 add r7, sp, #0
800385a: 6078 str r0, [r7, #4]
800385c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800385e: 2300 movs r3, #0
8003860: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8003862: 2300 movs r3, #0
8003864: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003866: e169 b.n 8003b3c <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8003868: 2201 movs r2, #1
800386a: 6a7b ldr r3, [r7, #36] @ 0x24
800386c: fa02 f303 lsl.w r3, r2, r3
8003870: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8003872: 683b ldr r3, [r7, #0]
8003874: 681b ldr r3, [r3, #0]
8003876: 69fa ldr r2, [r7, #28]
8003878: 4013 ands r3, r2
800387a: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
800387c: 69ba ldr r2, [r7, #24]
800387e: 69fb ldr r3, [r7, #28]
8003880: 429a cmp r2, r3
8003882: f040 8158 bne.w 8003b36 <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8003886: 683b ldr r3, [r7, #0]
8003888: 685b ldr r3, [r3, #4]
800388a: 4a9a ldr r2, [pc, #616] @ (8003af4 <HAL_GPIO_Init+0x2a0>)
800388c: 4293 cmp r3, r2
800388e: d05e beq.n 800394e <HAL_GPIO_Init+0xfa>
8003890: 4a98 ldr r2, [pc, #608] @ (8003af4 <HAL_GPIO_Init+0x2a0>)
8003892: 4293 cmp r3, r2
8003894: d875 bhi.n 8003982 <HAL_GPIO_Init+0x12e>
8003896: 4a98 ldr r2, [pc, #608] @ (8003af8 <HAL_GPIO_Init+0x2a4>)
8003898: 4293 cmp r3, r2
800389a: d058 beq.n 800394e <HAL_GPIO_Init+0xfa>
800389c: 4a96 ldr r2, [pc, #600] @ (8003af8 <HAL_GPIO_Init+0x2a4>)
800389e: 4293 cmp r3, r2
80038a0: d86f bhi.n 8003982 <HAL_GPIO_Init+0x12e>
80038a2: 4a96 ldr r2, [pc, #600] @ (8003afc <HAL_GPIO_Init+0x2a8>)
80038a4: 4293 cmp r3, r2
80038a6: d052 beq.n 800394e <HAL_GPIO_Init+0xfa>
80038a8: 4a94 ldr r2, [pc, #592] @ (8003afc <HAL_GPIO_Init+0x2a8>)
80038aa: 4293 cmp r3, r2
80038ac: d869 bhi.n 8003982 <HAL_GPIO_Init+0x12e>
80038ae: 4a94 ldr r2, [pc, #592] @ (8003b00 <HAL_GPIO_Init+0x2ac>)
80038b0: 4293 cmp r3, r2
80038b2: d04c beq.n 800394e <HAL_GPIO_Init+0xfa>
80038b4: 4a92 ldr r2, [pc, #584] @ (8003b00 <HAL_GPIO_Init+0x2ac>)
80038b6: 4293 cmp r3, r2
80038b8: d863 bhi.n 8003982 <HAL_GPIO_Init+0x12e>
80038ba: 4a92 ldr r2, [pc, #584] @ (8003b04 <HAL_GPIO_Init+0x2b0>)
80038bc: 4293 cmp r3, r2
80038be: d046 beq.n 800394e <HAL_GPIO_Init+0xfa>
80038c0: 4a90 ldr r2, [pc, #576] @ (8003b04 <HAL_GPIO_Init+0x2b0>)
80038c2: 4293 cmp r3, r2
80038c4: d85d bhi.n 8003982 <HAL_GPIO_Init+0x12e>
80038c6: 2b12 cmp r3, #18
80038c8: d82a bhi.n 8003920 <HAL_GPIO_Init+0xcc>
80038ca: 2b12 cmp r3, #18
80038cc: d859 bhi.n 8003982 <HAL_GPIO_Init+0x12e>
80038ce: a201 add r2, pc, #4 @ (adr r2, 80038d4 <HAL_GPIO_Init+0x80>)
80038d0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80038d4: 0800394f .word 0x0800394f
80038d8: 08003929 .word 0x08003929
80038dc: 0800393b .word 0x0800393b
80038e0: 0800397d .word 0x0800397d
80038e4: 08003983 .word 0x08003983
80038e8: 08003983 .word 0x08003983
80038ec: 08003983 .word 0x08003983
80038f0: 08003983 .word 0x08003983
80038f4: 08003983 .word 0x08003983
80038f8: 08003983 .word 0x08003983
80038fc: 08003983 .word 0x08003983
8003900: 08003983 .word 0x08003983
8003904: 08003983 .word 0x08003983
8003908: 08003983 .word 0x08003983
800390c: 08003983 .word 0x08003983
8003910: 08003983 .word 0x08003983
8003914: 08003983 .word 0x08003983
8003918: 08003931 .word 0x08003931
800391c: 08003945 .word 0x08003945
8003920: 4a79 ldr r2, [pc, #484] @ (8003b08 <HAL_GPIO_Init+0x2b4>)
8003922: 4293 cmp r3, r2
8003924: d013 beq.n 800394e <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8003926: e02c b.n 8003982 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8003928: 683b ldr r3, [r7, #0]
800392a: 68db ldr r3, [r3, #12]
800392c: 623b str r3, [r7, #32]
break;
800392e: e029 b.n 8003984 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003930: 683b ldr r3, [r7, #0]
8003932: 68db ldr r3, [r3, #12]
8003934: 3304 adds r3, #4
8003936: 623b str r3, [r7, #32]
break;
8003938: e024 b.n 8003984 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800393a: 683b ldr r3, [r7, #0]
800393c: 68db ldr r3, [r3, #12]
800393e: 3308 adds r3, #8
8003940: 623b str r3, [r7, #32]
break;
8003942: e01f b.n 8003984 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8003944: 683b ldr r3, [r7, #0]
8003946: 68db ldr r3, [r3, #12]
8003948: 330c adds r3, #12
800394a: 623b str r3, [r7, #32]
break;
800394c: e01a b.n 8003984 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
800394e: 683b ldr r3, [r7, #0]
8003950: 689b ldr r3, [r3, #8]
8003952: 2b00 cmp r3, #0
8003954: d102 bne.n 800395c <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8003956: 2304 movs r3, #4
8003958: 623b str r3, [r7, #32]
break;
800395a: e013 b.n 8003984 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
800395c: 683b ldr r3, [r7, #0]
800395e: 689b ldr r3, [r3, #8]
8003960: 2b01 cmp r3, #1
8003962: d105 bne.n 8003970 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003964: 2308 movs r3, #8
8003966: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8003968: 687b ldr r3, [r7, #4]
800396a: 69fa ldr r2, [r7, #28]
800396c: 611a str r2, [r3, #16]
break;
800396e: e009 b.n 8003984 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003970: 2308 movs r3, #8
8003972: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8003974: 687b ldr r3, [r7, #4]
8003976: 69fa ldr r2, [r7, #28]
8003978: 615a str r2, [r3, #20]
break;
800397a: e003 b.n 8003984 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
800397c: 2300 movs r3, #0
800397e: 623b str r3, [r7, #32]
break;
8003980: e000 b.n 8003984 <HAL_GPIO_Init+0x130>
break;
8003982: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8003984: 69bb ldr r3, [r7, #24]
8003986: 2bff cmp r3, #255 @ 0xff
8003988: d801 bhi.n 800398e <HAL_GPIO_Init+0x13a>
800398a: 687b ldr r3, [r7, #4]
800398c: e001 b.n 8003992 <HAL_GPIO_Init+0x13e>
800398e: 687b ldr r3, [r7, #4]
8003990: 3304 adds r3, #4
8003992: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8003994: 69bb ldr r3, [r7, #24]
8003996: 2bff cmp r3, #255 @ 0xff
8003998: d802 bhi.n 80039a0 <HAL_GPIO_Init+0x14c>
800399a: 6a7b ldr r3, [r7, #36] @ 0x24
800399c: 009b lsls r3, r3, #2
800399e: e002 b.n 80039a6 <HAL_GPIO_Init+0x152>
80039a0: 6a7b ldr r3, [r7, #36] @ 0x24
80039a2: 3b08 subs r3, #8
80039a4: 009b lsls r3, r3, #2
80039a6: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80039a8: 697b ldr r3, [r7, #20]
80039aa: 681a ldr r2, [r3, #0]
80039ac: 210f movs r1, #15
80039ae: 693b ldr r3, [r7, #16]
80039b0: fa01 f303 lsl.w r3, r1, r3
80039b4: 43db mvns r3, r3
80039b6: 401a ands r2, r3
80039b8: 6a39 ldr r1, [r7, #32]
80039ba: 693b ldr r3, [r7, #16]
80039bc: fa01 f303 lsl.w r3, r1, r3
80039c0: 431a orrs r2, r3
80039c2: 697b ldr r3, [r7, #20]
80039c4: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80039c6: 683b ldr r3, [r7, #0]
80039c8: 685b ldr r3, [r3, #4]
80039ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80039ce: 2b00 cmp r3, #0
80039d0: f000 80b1 beq.w 8003b36 <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80039d4: 4b4d ldr r3, [pc, #308] @ (8003b0c <HAL_GPIO_Init+0x2b8>)
80039d6: 699b ldr r3, [r3, #24]
80039d8: 4a4c ldr r2, [pc, #304] @ (8003b0c <HAL_GPIO_Init+0x2b8>)
80039da: f043 0301 orr.w r3, r3, #1
80039de: 6193 str r3, [r2, #24]
80039e0: 4b4a ldr r3, [pc, #296] @ (8003b0c <HAL_GPIO_Init+0x2b8>)
80039e2: 699b ldr r3, [r3, #24]
80039e4: f003 0301 and.w r3, r3, #1
80039e8: 60bb str r3, [r7, #8]
80039ea: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
80039ec: 4a48 ldr r2, [pc, #288] @ (8003b10 <HAL_GPIO_Init+0x2bc>)
80039ee: 6a7b ldr r3, [r7, #36] @ 0x24
80039f0: 089b lsrs r3, r3, #2
80039f2: 3302 adds r3, #2
80039f4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80039f8: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
80039fa: 6a7b ldr r3, [r7, #36] @ 0x24
80039fc: f003 0303 and.w r3, r3, #3
8003a00: 009b lsls r3, r3, #2
8003a02: 220f movs r2, #15
8003a04: fa02 f303 lsl.w r3, r2, r3
8003a08: 43db mvns r3, r3
8003a0a: 68fa ldr r2, [r7, #12]
8003a0c: 4013 ands r3, r2
8003a0e: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003a10: 687b ldr r3, [r7, #4]
8003a12: 4a40 ldr r2, [pc, #256] @ (8003b14 <HAL_GPIO_Init+0x2c0>)
8003a14: 4293 cmp r3, r2
8003a16: d013 beq.n 8003a40 <HAL_GPIO_Init+0x1ec>
8003a18: 687b ldr r3, [r7, #4]
8003a1a: 4a3f ldr r2, [pc, #252] @ (8003b18 <HAL_GPIO_Init+0x2c4>)
8003a1c: 4293 cmp r3, r2
8003a1e: d00d beq.n 8003a3c <HAL_GPIO_Init+0x1e8>
8003a20: 687b ldr r3, [r7, #4]
8003a22: 4a3e ldr r2, [pc, #248] @ (8003b1c <HAL_GPIO_Init+0x2c8>)
8003a24: 4293 cmp r3, r2
8003a26: d007 beq.n 8003a38 <HAL_GPIO_Init+0x1e4>
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 4a3d ldr r2, [pc, #244] @ (8003b20 <HAL_GPIO_Init+0x2cc>)
8003a2c: 4293 cmp r3, r2
8003a2e: d101 bne.n 8003a34 <HAL_GPIO_Init+0x1e0>
8003a30: 2303 movs r3, #3
8003a32: e006 b.n 8003a42 <HAL_GPIO_Init+0x1ee>
8003a34: 2304 movs r3, #4
8003a36: e004 b.n 8003a42 <HAL_GPIO_Init+0x1ee>
8003a38: 2302 movs r3, #2
8003a3a: e002 b.n 8003a42 <HAL_GPIO_Init+0x1ee>
8003a3c: 2301 movs r3, #1
8003a3e: e000 b.n 8003a42 <HAL_GPIO_Init+0x1ee>
8003a40: 2300 movs r3, #0
8003a42: 6a7a ldr r2, [r7, #36] @ 0x24
8003a44: f002 0203 and.w r2, r2, #3
8003a48: 0092 lsls r2, r2, #2
8003a4a: 4093 lsls r3, r2
8003a4c: 68fa ldr r2, [r7, #12]
8003a4e: 4313 orrs r3, r2
8003a50: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8003a52: 492f ldr r1, [pc, #188] @ (8003b10 <HAL_GPIO_Init+0x2bc>)
8003a54: 6a7b ldr r3, [r7, #36] @ 0x24
8003a56: 089b lsrs r3, r3, #2
8003a58: 3302 adds r3, #2
8003a5a: 68fa ldr r2, [r7, #12]
8003a5c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003a60: 683b ldr r3, [r7, #0]
8003a62: 685b ldr r3, [r3, #4]
8003a64: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003a68: 2b00 cmp r3, #0
8003a6a: d006 beq.n 8003a7a <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8003a6c: 4b2d ldr r3, [pc, #180] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a6e: 689a ldr r2, [r3, #8]
8003a70: 492c ldr r1, [pc, #176] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a72: 69bb ldr r3, [r7, #24]
8003a74: 4313 orrs r3, r2
8003a76: 608b str r3, [r1, #8]
8003a78: e006 b.n 8003a88 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8003a7a: 4b2a ldr r3, [pc, #168] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a7c: 689a ldr r2, [r3, #8]
8003a7e: 69bb ldr r3, [r7, #24]
8003a80: 43db mvns r3, r3
8003a82: 4928 ldr r1, [pc, #160] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a84: 4013 ands r3, r2
8003a86: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8003a88: 683b ldr r3, [r7, #0]
8003a8a: 685b ldr r3, [r3, #4]
8003a8c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003a90: 2b00 cmp r3, #0
8003a92: d006 beq.n 8003aa2 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
8003a94: 4b23 ldr r3, [pc, #140] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a96: 68da ldr r2, [r3, #12]
8003a98: 4922 ldr r1, [pc, #136] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003a9a: 69bb ldr r3, [r7, #24]
8003a9c: 4313 orrs r3, r2
8003a9e: 60cb str r3, [r1, #12]
8003aa0: e006 b.n 8003ab0 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8003aa2: 4b20 ldr r3, [pc, #128] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003aa4: 68da ldr r2, [r3, #12]
8003aa6: 69bb ldr r3, [r7, #24]
8003aa8: 43db mvns r3, r3
8003aaa: 491e ldr r1, [pc, #120] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003aac: 4013 ands r3, r2
8003aae: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8003ab0: 683b ldr r3, [r7, #0]
8003ab2: 685b ldr r3, [r3, #4]
8003ab4: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003ab8: 2b00 cmp r3, #0
8003aba: d006 beq.n 8003aca <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8003abc: 4b19 ldr r3, [pc, #100] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003abe: 685a ldr r2, [r3, #4]
8003ac0: 4918 ldr r1, [pc, #96] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003ac2: 69bb ldr r3, [r7, #24]
8003ac4: 4313 orrs r3, r2
8003ac6: 604b str r3, [r1, #4]
8003ac8: e006 b.n 8003ad8 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8003aca: 4b16 ldr r3, [pc, #88] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003acc: 685a ldr r2, [r3, #4]
8003ace: 69bb ldr r3, [r7, #24]
8003ad0: 43db mvns r3, r3
8003ad2: 4914 ldr r1, [pc, #80] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003ad4: 4013 ands r3, r2
8003ad6: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8003ad8: 683b ldr r3, [r7, #0]
8003ada: 685b ldr r3, [r3, #4]
8003adc: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003ae0: 2b00 cmp r3, #0
8003ae2: d021 beq.n 8003b28 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8003ae4: 4b0f ldr r3, [pc, #60] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003ae6: 681a ldr r2, [r3, #0]
8003ae8: 490e ldr r1, [pc, #56] @ (8003b24 <HAL_GPIO_Init+0x2d0>)
8003aea: 69bb ldr r3, [r7, #24]
8003aec: 4313 orrs r3, r2
8003aee: 600b str r3, [r1, #0]
8003af0: e021 b.n 8003b36 <HAL_GPIO_Init+0x2e2>
8003af2: bf00 nop
8003af4: 10320000 .word 0x10320000
8003af8: 10310000 .word 0x10310000
8003afc: 10220000 .word 0x10220000
8003b00: 10210000 .word 0x10210000
8003b04: 10120000 .word 0x10120000
8003b08: 10110000 .word 0x10110000
8003b0c: 40021000 .word 0x40021000
8003b10: 40010000 .word 0x40010000
8003b14: 40010800 .word 0x40010800
8003b18: 40010c00 .word 0x40010c00
8003b1c: 40011000 .word 0x40011000
8003b20: 40011400 .word 0x40011400
8003b24: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8003b28: 4b0b ldr r3, [pc, #44] @ (8003b58 <HAL_GPIO_Init+0x304>)
8003b2a: 681a ldr r2, [r3, #0]
8003b2c: 69bb ldr r3, [r7, #24]
8003b2e: 43db mvns r3, r3
8003b30: 4909 ldr r1, [pc, #36] @ (8003b58 <HAL_GPIO_Init+0x304>)
8003b32: 4013 ands r3, r2
8003b34: 600b str r3, [r1, #0]
}
}
}
position++;
8003b36: 6a7b ldr r3, [r7, #36] @ 0x24
8003b38: 3301 adds r3, #1
8003b3a: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003b3c: 683b ldr r3, [r7, #0]
8003b3e: 681a ldr r2, [r3, #0]
8003b40: 6a7b ldr r3, [r7, #36] @ 0x24
8003b42: fa22 f303 lsr.w r3, r2, r3
8003b46: 2b00 cmp r3, #0
8003b48: f47f ae8e bne.w 8003868 <HAL_GPIO_Init+0x14>
}
}
8003b4c: bf00 nop
8003b4e: bf00 nop
8003b50: 372c adds r7, #44 @ 0x2c
8003b52: 46bd mov sp, r7
8003b54: bc80 pop {r7}
8003b56: 4770 bx lr
8003b58: 40010400 .word 0x40010400
08003b5c <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003b5c: b480 push {r7}
8003b5e: b085 sub sp, #20
8003b60: af00 add r7, sp, #0
8003b62: 6078 str r0, [r7, #4]
8003b64: 460b mov r3, r1
8003b66: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8003b68: 687b ldr r3, [r7, #4]
8003b6a: 689a ldr r2, [r3, #8]
8003b6c: 887b ldrh r3, [r7, #2]
8003b6e: 4013 ands r3, r2
8003b70: 2b00 cmp r3, #0
8003b72: d002 beq.n 8003b7a <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8003b74: 2301 movs r3, #1
8003b76: 73fb strb r3, [r7, #15]
8003b78: e001 b.n 8003b7e <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8003b7a: 2300 movs r3, #0
8003b7c: 73fb strb r3, [r7, #15]
}
return bitstatus;
8003b7e: 7bfb ldrb r3, [r7, #15]
}
8003b80: 4618 mov r0, r3
8003b82: 3714 adds r7, #20
8003b84: 46bd mov sp, r7
8003b86: bc80 pop {r7}
8003b88: 4770 bx lr
08003b8a <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003b8a: b480 push {r7}
8003b8c: b083 sub sp, #12
8003b8e: af00 add r7, sp, #0
8003b90: 6078 str r0, [r7, #4]
8003b92: 460b mov r3, r1
8003b94: 807b strh r3, [r7, #2]
8003b96: 4613 mov r3, r2
8003b98: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003b9a: 787b ldrb r3, [r7, #1]
8003b9c: 2b00 cmp r3, #0
8003b9e: d003 beq.n 8003ba8 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8003ba0: 887a ldrh r2, [r7, #2]
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8003ba6: e003 b.n 8003bb0 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8003ba8: 887b ldrh r3, [r7, #2]
8003baa: 041a lsls r2, r3, #16
8003bac: 687b ldr r3, [r7, #4]
8003bae: 611a str r2, [r3, #16]
}
8003bb0: bf00 nop
8003bb2: 370c adds r7, #12
8003bb4: 46bd mov sp, r7
8003bb6: bc80 pop {r7}
8003bb8: 4770 bx lr
08003bba <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003bba: b480 push {r7}
8003bbc: b085 sub sp, #20
8003bbe: af00 add r7, sp, #0
8003bc0: 6078 str r0, [r7, #4]
8003bc2: 460b mov r3, r1
8003bc4: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8003bc6: 687b ldr r3, [r7, #4]
8003bc8: 68db ldr r3, [r3, #12]
8003bca: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8003bcc: 887a ldrh r2, [r7, #2]
8003bce: 68fb ldr r3, [r7, #12]
8003bd0: 4013 ands r3, r2
8003bd2: 041a lsls r2, r3, #16
8003bd4: 68fb ldr r3, [r7, #12]
8003bd6: 43d9 mvns r1, r3
8003bd8: 887b ldrh r3, [r7, #2]
8003bda: 400b ands r3, r1
8003bdc: 431a orrs r2, r3
8003bde: 687b ldr r3, [r7, #4]
8003be0: 611a str r2, [r3, #16]
}
8003be2: bf00 nop
8003be4: 3714 adds r7, #20
8003be6: 46bd mov sp, r7
8003be8: bc80 pop {r7}
8003bea: 4770 bx lr
08003bec <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003bec: b580 push {r7, lr}
8003bee: b084 sub sp, #16
8003bf0: af00 add r7, sp, #0
8003bf2: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003bf4: 687b ldr r3, [r7, #4]
8003bf6: 2b00 cmp r3, #0
8003bf8: d101 bne.n 8003bfe <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8003bfa: 2301 movs r3, #1
8003bfc: e12b b.n 8003e56 <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003bfe: 687b ldr r3, [r7, #4]
8003c00: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003c04: b2db uxtb r3, r3
8003c06: 2b00 cmp r3, #0
8003c08: d106 bne.n 8003c18 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8003c0a: 687b ldr r3, [r7, #4]
8003c0c: 2200 movs r2, #0
8003c0e: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003c12: 6878 ldr r0, [r7, #4]
8003c14: f7fe fb2e bl 8002274 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8003c18: 687b ldr r3, [r7, #4]
8003c1a: 2224 movs r2, #36 @ 0x24
8003c1c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003c20: 687b ldr r3, [r7, #4]
8003c22: 681b ldr r3, [r3, #0]
8003c24: 681a ldr r2, [r3, #0]
8003c26: 687b ldr r3, [r7, #4]
8003c28: 681b ldr r3, [r3, #0]
8003c2a: f022 0201 bic.w r2, r2, #1
8003c2e: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003c30: 687b ldr r3, [r7, #4]
8003c32: 681b ldr r3, [r3, #0]
8003c34: 681a ldr r2, [r3, #0]
8003c36: 687b ldr r3, [r7, #4]
8003c38: 681b ldr r3, [r3, #0]
8003c3a: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003c3e: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003c40: 687b ldr r3, [r7, #4]
8003c42: 681b ldr r3, [r3, #0]
8003c44: 681a ldr r2, [r3, #0]
8003c46: 687b ldr r3, [r7, #4]
8003c48: 681b ldr r3, [r3, #0]
8003c4a: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003c4e: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003c50: f001 fbcc bl 80053ec <HAL_RCC_GetPCLK1Freq>
8003c54: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
8003c56: 687b ldr r3, [r7, #4]
8003c58: 685b ldr r3, [r3, #4]
8003c5a: 4a81 ldr r2, [pc, #516] @ (8003e60 <HAL_I2C_Init+0x274>)
8003c5c: 4293 cmp r3, r2
8003c5e: d807 bhi.n 8003c70 <HAL_I2C_Init+0x84>
8003c60: 68fb ldr r3, [r7, #12]
8003c62: 4a80 ldr r2, [pc, #512] @ (8003e64 <HAL_I2C_Init+0x278>)
8003c64: 4293 cmp r3, r2
8003c66: bf94 ite ls
8003c68: 2301 movls r3, #1
8003c6a: 2300 movhi r3, #0
8003c6c: b2db uxtb r3, r3
8003c6e: e006 b.n 8003c7e <HAL_I2C_Init+0x92>
8003c70: 68fb ldr r3, [r7, #12]
8003c72: 4a7d ldr r2, [pc, #500] @ (8003e68 <HAL_I2C_Init+0x27c>)
8003c74: 4293 cmp r3, r2
8003c76: bf94 ite ls
8003c78: 2301 movls r3, #1
8003c7a: 2300 movhi r3, #0
8003c7c: b2db uxtb r3, r3
8003c7e: 2b00 cmp r3, #0
8003c80: d001 beq.n 8003c86 <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003c82: 2301 movs r3, #1
8003c84: e0e7 b.n 8003e56 <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
8003c86: 68fb ldr r3, [r7, #12]
8003c88: 4a78 ldr r2, [pc, #480] @ (8003e6c <HAL_I2C_Init+0x280>)
8003c8a: fba2 2303 umull r2, r3, r2, r3
8003c8e: 0c9b lsrs r3, r3, #18
8003c90: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
8003c92: 687b ldr r3, [r7, #4]
8003c94: 681b ldr r3, [r3, #0]
8003c96: 685b ldr r3, [r3, #4]
8003c98: f023 013f bic.w r1, r3, #63 @ 0x3f
8003c9c: 687b ldr r3, [r7, #4]
8003c9e: 681b ldr r3, [r3, #0]
8003ca0: 68ba ldr r2, [r7, #8]
8003ca2: 430a orrs r2, r1
8003ca4: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
8003ca6: 687b ldr r3, [r7, #4]
8003ca8: 681b ldr r3, [r3, #0]
8003caa: 6a1b ldr r3, [r3, #32]
8003cac: f023 013f bic.w r1, r3, #63 @ 0x3f
8003cb0: 687b ldr r3, [r7, #4]
8003cb2: 685b ldr r3, [r3, #4]
8003cb4: 4a6a ldr r2, [pc, #424] @ (8003e60 <HAL_I2C_Init+0x274>)
8003cb6: 4293 cmp r3, r2
8003cb8: d802 bhi.n 8003cc0 <HAL_I2C_Init+0xd4>
8003cba: 68bb ldr r3, [r7, #8]
8003cbc: 3301 adds r3, #1
8003cbe: e009 b.n 8003cd4 <HAL_I2C_Init+0xe8>
8003cc0: 68bb ldr r3, [r7, #8]
8003cc2: f44f 7296 mov.w r2, #300 @ 0x12c
8003cc6: fb02 f303 mul.w r3, r2, r3
8003cca: 4a69 ldr r2, [pc, #420] @ (8003e70 <HAL_I2C_Init+0x284>)
8003ccc: fba2 2303 umull r2, r3, r2, r3
8003cd0: 099b lsrs r3, r3, #6
8003cd2: 3301 adds r3, #1
8003cd4: 687a ldr r2, [r7, #4]
8003cd6: 6812 ldr r2, [r2, #0]
8003cd8: 430b orrs r3, r1
8003cda: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8003cdc: 687b ldr r3, [r7, #4]
8003cde: 681b ldr r3, [r3, #0]
8003ce0: 69db ldr r3, [r3, #28]
8003ce2: f423 424f bic.w r2, r3, #52992 @ 0xcf00
8003ce6: f022 02ff bic.w r2, r2, #255 @ 0xff
8003cea: 687b ldr r3, [r7, #4]
8003cec: 685b ldr r3, [r3, #4]
8003cee: 495c ldr r1, [pc, #368] @ (8003e60 <HAL_I2C_Init+0x274>)
8003cf0: 428b cmp r3, r1
8003cf2: d819 bhi.n 8003d28 <HAL_I2C_Init+0x13c>
8003cf4: 68fb ldr r3, [r7, #12]
8003cf6: 1e59 subs r1, r3, #1
8003cf8: 687b ldr r3, [r7, #4]
8003cfa: 685b ldr r3, [r3, #4]
8003cfc: 005b lsls r3, r3, #1
8003cfe: fbb1 f3f3 udiv r3, r1, r3
8003d02: 1c59 adds r1, r3, #1
8003d04: f640 73fc movw r3, #4092 @ 0xffc
8003d08: 400b ands r3, r1
8003d0a: 2b00 cmp r3, #0
8003d0c: d00a beq.n 8003d24 <HAL_I2C_Init+0x138>
8003d0e: 68fb ldr r3, [r7, #12]
8003d10: 1e59 subs r1, r3, #1
8003d12: 687b ldr r3, [r7, #4]
8003d14: 685b ldr r3, [r3, #4]
8003d16: 005b lsls r3, r3, #1
8003d18: fbb1 f3f3 udiv r3, r1, r3
8003d1c: 3301 adds r3, #1
8003d1e: f3c3 030b ubfx r3, r3, #0, #12
8003d22: e051 b.n 8003dc8 <HAL_I2C_Init+0x1dc>
8003d24: 2304 movs r3, #4
8003d26: e04f b.n 8003dc8 <HAL_I2C_Init+0x1dc>
8003d28: 687b ldr r3, [r7, #4]
8003d2a: 689b ldr r3, [r3, #8]
8003d2c: 2b00 cmp r3, #0
8003d2e: d111 bne.n 8003d54 <HAL_I2C_Init+0x168>
8003d30: 68fb ldr r3, [r7, #12]
8003d32: 1e58 subs r0, r3, #1
8003d34: 687b ldr r3, [r7, #4]
8003d36: 6859 ldr r1, [r3, #4]
8003d38: 460b mov r3, r1
8003d3a: 005b lsls r3, r3, #1
8003d3c: 440b add r3, r1
8003d3e: fbb0 f3f3 udiv r3, r0, r3
8003d42: 3301 adds r3, #1
8003d44: f3c3 030b ubfx r3, r3, #0, #12
8003d48: 2b00 cmp r3, #0
8003d4a: bf0c ite eq
8003d4c: 2301 moveq r3, #1
8003d4e: 2300 movne r3, #0
8003d50: b2db uxtb r3, r3
8003d52: e012 b.n 8003d7a <HAL_I2C_Init+0x18e>
8003d54: 68fb ldr r3, [r7, #12]
8003d56: 1e58 subs r0, r3, #1
8003d58: 687b ldr r3, [r7, #4]
8003d5a: 6859 ldr r1, [r3, #4]
8003d5c: 460b mov r3, r1
8003d5e: 009b lsls r3, r3, #2
8003d60: 440b add r3, r1
8003d62: 0099 lsls r1, r3, #2
8003d64: 440b add r3, r1
8003d66: fbb0 f3f3 udiv r3, r0, r3
8003d6a: 3301 adds r3, #1
8003d6c: f3c3 030b ubfx r3, r3, #0, #12
8003d70: 2b00 cmp r3, #0
8003d72: bf0c ite eq
8003d74: 2301 moveq r3, #1
8003d76: 2300 movne r3, #0
8003d78: b2db uxtb r3, r3
8003d7a: 2b00 cmp r3, #0
8003d7c: d001 beq.n 8003d82 <HAL_I2C_Init+0x196>
8003d7e: 2301 movs r3, #1
8003d80: e022 b.n 8003dc8 <HAL_I2C_Init+0x1dc>
8003d82: 687b ldr r3, [r7, #4]
8003d84: 689b ldr r3, [r3, #8]
8003d86: 2b00 cmp r3, #0
8003d88: d10e bne.n 8003da8 <HAL_I2C_Init+0x1bc>
8003d8a: 68fb ldr r3, [r7, #12]
8003d8c: 1e58 subs r0, r3, #1
8003d8e: 687b ldr r3, [r7, #4]
8003d90: 6859 ldr r1, [r3, #4]
8003d92: 460b mov r3, r1
8003d94: 005b lsls r3, r3, #1
8003d96: 440b add r3, r1
8003d98: fbb0 f3f3 udiv r3, r0, r3
8003d9c: 3301 adds r3, #1
8003d9e: f3c3 030b ubfx r3, r3, #0, #12
8003da2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8003da6: e00f b.n 8003dc8 <HAL_I2C_Init+0x1dc>
8003da8: 68fb ldr r3, [r7, #12]
8003daa: 1e58 subs r0, r3, #1
8003dac: 687b ldr r3, [r7, #4]
8003dae: 6859 ldr r1, [r3, #4]
8003db0: 460b mov r3, r1
8003db2: 009b lsls r3, r3, #2
8003db4: 440b add r3, r1
8003db6: 0099 lsls r1, r3, #2
8003db8: 440b add r3, r1
8003dba: fbb0 f3f3 udiv r3, r0, r3
8003dbe: 3301 adds r3, #1
8003dc0: f3c3 030b ubfx r3, r3, #0, #12
8003dc4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8003dc8: 6879 ldr r1, [r7, #4]
8003dca: 6809 ldr r1, [r1, #0]
8003dcc: 4313 orrs r3, r2
8003dce: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8003dd0: 687b ldr r3, [r7, #4]
8003dd2: 681b ldr r3, [r3, #0]
8003dd4: 681b ldr r3, [r3, #0]
8003dd6: f023 01c0 bic.w r1, r3, #192 @ 0xc0
8003dda: 687b ldr r3, [r7, #4]
8003ddc: 69da ldr r2, [r3, #28]
8003dde: 687b ldr r3, [r7, #4]
8003de0: 6a1b ldr r3, [r3, #32]
8003de2: 431a orrs r2, r3
8003de4: 687b ldr r3, [r7, #4]
8003de6: 681b ldr r3, [r3, #0]
8003de8: 430a orrs r2, r1
8003dea: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8003dec: 687b ldr r3, [r7, #4]
8003dee: 681b ldr r3, [r3, #0]
8003df0: 689b ldr r3, [r3, #8]
8003df2: f423 4303 bic.w r3, r3, #33536 @ 0x8300
8003df6: f023 03ff bic.w r3, r3, #255 @ 0xff
8003dfa: 687a ldr r2, [r7, #4]
8003dfc: 6911 ldr r1, [r2, #16]
8003dfe: 687a ldr r2, [r7, #4]
8003e00: 68d2 ldr r2, [r2, #12]
8003e02: 4311 orrs r1, r2
8003e04: 687a ldr r2, [r7, #4]
8003e06: 6812 ldr r2, [r2, #0]
8003e08: 430b orrs r3, r1
8003e0a: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
8003e0c: 687b ldr r3, [r7, #4]
8003e0e: 681b ldr r3, [r3, #0]
8003e10: 68db ldr r3, [r3, #12]
8003e12: f023 01ff bic.w r1, r3, #255 @ 0xff
8003e16: 687b ldr r3, [r7, #4]
8003e18: 695a ldr r2, [r3, #20]
8003e1a: 687b ldr r3, [r7, #4]
8003e1c: 699b ldr r3, [r3, #24]
8003e1e: 431a orrs r2, r3
8003e20: 687b ldr r3, [r7, #4]
8003e22: 681b ldr r3, [r3, #0]
8003e24: 430a orrs r2, r1
8003e26: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003e28: 687b ldr r3, [r7, #4]
8003e2a: 681b ldr r3, [r3, #0]
8003e2c: 681a ldr r2, [r3, #0]
8003e2e: 687b ldr r3, [r7, #4]
8003e30: 681b ldr r3, [r3, #0]
8003e32: f042 0201 orr.w r2, r2, #1
8003e36: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003e38: 687b ldr r3, [r7, #4]
8003e3a: 2200 movs r2, #0
8003e3c: 641a str r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_READY;
8003e3e: 687b ldr r3, [r7, #4]
8003e40: 2220 movs r2, #32
8003e42: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
8003e46: 687b ldr r3, [r7, #4]
8003e48: 2200 movs r2, #0
8003e4a: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8003e4c: 687b ldr r3, [r7, #4]
8003e4e: 2200 movs r2, #0
8003e50: f883 203e strb.w r2, [r3, #62] @ 0x3e
return HAL_OK;
8003e54: 2300 movs r3, #0
}
8003e56: 4618 mov r0, r3
8003e58: 3710 adds r7, #16
8003e5a: 46bd mov sp, r7
8003e5c: bd80 pop {r7, pc}
8003e5e: bf00 nop
8003e60: 000186a0 .word 0x000186a0
8003e64: 001e847f .word 0x001e847f
8003e68: 003d08ff .word 0x003d08ff
8003e6c: 431bde83 .word 0x431bde83
8003e70: 10624dd3 .word 0x10624dd3
08003e74 <HAL_I2C_Master_Transmit>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003e74: b580 push {r7, lr}
8003e76: b088 sub sp, #32
8003e78: af02 add r7, sp, #8
8003e7a: 60f8 str r0, [r7, #12]
8003e7c: 607a str r2, [r7, #4]
8003e7e: 461a mov r2, r3
8003e80: 460b mov r3, r1
8003e82: 817b strh r3, [r7, #10]
8003e84: 4613 mov r3, r2
8003e86: 813b strh r3, [r7, #8]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
8003e88: f7ff f8e4 bl 8003054 <HAL_GetTick>
8003e8c: 6178 str r0, [r7, #20]
if (hi2c->State == HAL_I2C_STATE_READY)
8003e8e: 68fb ldr r3, [r7, #12]
8003e90: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003e94: b2db uxtb r3, r3
8003e96: 2b20 cmp r3, #32
8003e98: f040 80e0 bne.w 800405c <HAL_I2C_Master_Transmit+0x1e8>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
8003e9c: 697b ldr r3, [r7, #20]
8003e9e: 9300 str r3, [sp, #0]
8003ea0: 2319 movs r3, #25
8003ea2: 2201 movs r2, #1
8003ea4: 4970 ldr r1, [pc, #448] @ (8004068 <HAL_I2C_Master_Transmit+0x1f4>)
8003ea6: 68f8 ldr r0, [r7, #12]
8003ea8: f000 fc9e bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
8003eac: 4603 mov r3, r0
8003eae: 2b00 cmp r3, #0
8003eb0: d001 beq.n 8003eb6 <HAL_I2C_Master_Transmit+0x42>
{
return HAL_BUSY;
8003eb2: 2302 movs r3, #2
8003eb4: e0d3 b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8003eb6: 68fb ldr r3, [r7, #12]
8003eb8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8003ebc: 2b01 cmp r3, #1
8003ebe: d101 bne.n 8003ec4 <HAL_I2C_Master_Transmit+0x50>
8003ec0: 2302 movs r3, #2
8003ec2: e0cc b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
8003ec4: 68fb ldr r3, [r7, #12]
8003ec6: 2201 movs r2, #1
8003ec8: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
8003ecc: 68fb ldr r3, [r7, #12]
8003ece: 681b ldr r3, [r3, #0]
8003ed0: 681b ldr r3, [r3, #0]
8003ed2: f003 0301 and.w r3, r3, #1
8003ed6: 2b01 cmp r3, #1
8003ed8: d007 beq.n 8003eea <HAL_I2C_Master_Transmit+0x76>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003eda: 68fb ldr r3, [r7, #12]
8003edc: 681b ldr r3, [r3, #0]
8003ede: 681a ldr r2, [r3, #0]
8003ee0: 68fb ldr r3, [r7, #12]
8003ee2: 681b ldr r3, [r3, #0]
8003ee4: f042 0201 orr.w r2, r2, #1
8003ee8: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8003eea: 68fb ldr r3, [r7, #12]
8003eec: 681b ldr r3, [r3, #0]
8003eee: 681a ldr r2, [r3, #0]
8003ef0: 68fb ldr r3, [r7, #12]
8003ef2: 681b ldr r3, [r3, #0]
8003ef4: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003ef8: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8003efa: 68fb ldr r3, [r7, #12]
8003efc: 2221 movs r2, #33 @ 0x21
8003efe: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8003f02: 68fb ldr r3, [r7, #12]
8003f04: 2210 movs r2, #16
8003f06: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003f0a: 68fb ldr r3, [r7, #12]
8003f0c: 2200 movs r2, #0
8003f0e: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8003f10: 68fb ldr r3, [r7, #12]
8003f12: 687a ldr r2, [r7, #4]
8003f14: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8003f16: 68fb ldr r3, [r7, #12]
8003f18: 893a ldrh r2, [r7, #8]
8003f1a: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8003f1c: 68fb ldr r3, [r7, #12]
8003f1e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003f20: b29a uxth r2, r3
8003f22: 68fb ldr r3, [r7, #12]
8003f24: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8003f26: 68fb ldr r3, [r7, #12]
8003f28: 4a50 ldr r2, [pc, #320] @ (800406c <HAL_I2C_Master_Transmit+0x1f8>)
8003f2a: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
8003f2c: 8979 ldrh r1, [r7, #10]
8003f2e: 697b ldr r3, [r7, #20]
8003f30: 6a3a ldr r2, [r7, #32]
8003f32: 68f8 ldr r0, [r7, #12]
8003f34: f000 fb08 bl 8004548 <I2C_MasterRequestWrite>
8003f38: 4603 mov r3, r0
8003f3a: 2b00 cmp r3, #0
8003f3c: d001 beq.n 8003f42 <HAL_I2C_Master_Transmit+0xce>
{
return HAL_ERROR;
8003f3e: 2301 movs r3, #1
8003f40: e08d b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003f42: 2300 movs r3, #0
8003f44: 613b str r3, [r7, #16]
8003f46: 68fb ldr r3, [r7, #12]
8003f48: 681b ldr r3, [r3, #0]
8003f4a: 695b ldr r3, [r3, #20]
8003f4c: 613b str r3, [r7, #16]
8003f4e: 68fb ldr r3, [r7, #12]
8003f50: 681b ldr r3, [r3, #0]
8003f52: 699b ldr r3, [r3, #24]
8003f54: 613b str r3, [r7, #16]
8003f56: 693b ldr r3, [r7, #16]
while (hi2c->XferSize > 0U)
8003f58: e066 b.n 8004028 <HAL_I2C_Master_Transmit+0x1b4>
{
/* Wait until TXE flag is set */
if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003f5a: 697a ldr r2, [r7, #20]
8003f5c: 6a39 ldr r1, [r7, #32]
8003f5e: 68f8 ldr r0, [r7, #12]
8003f60: f000 fd5c bl 8004a1c <I2C_WaitOnTXEFlagUntilTimeout>
8003f64: 4603 mov r3, r0
8003f66: 2b00 cmp r3, #0
8003f68: d00d beq.n 8003f86 <HAL_I2C_Master_Transmit+0x112>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
8003f6a: 68fb ldr r3, [r7, #12]
8003f6c: 6c1b ldr r3, [r3, #64] @ 0x40
8003f6e: 2b04 cmp r3, #4
8003f70: d107 bne.n 8003f82 <HAL_I2C_Master_Transmit+0x10e>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003f72: 68fb ldr r3, [r7, #12]
8003f74: 681b ldr r3, [r3, #0]
8003f76: 681a ldr r2, [r3, #0]
8003f78: 68fb ldr r3, [r7, #12]
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: f442 7200 orr.w r2, r2, #512 @ 0x200
8003f80: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8003f82: 2301 movs r3, #1
8003f84: e06b b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
}
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003f86: 68fb ldr r3, [r7, #12]
8003f88: 6a5b ldr r3, [r3, #36] @ 0x24
8003f8a: 781a ldrb r2, [r3, #0]
8003f8c: 68fb ldr r3, [r7, #12]
8003f8e: 681b ldr r3, [r3, #0]
8003f90: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003f92: 68fb ldr r3, [r7, #12]
8003f94: 6a5b ldr r3, [r3, #36] @ 0x24
8003f96: 1c5a adds r2, r3, #1
8003f98: 68fb ldr r3, [r7, #12]
8003f9a: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003f9c: 68fb ldr r3, [r7, #12]
8003f9e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003fa0: b29b uxth r3, r3
8003fa2: 3b01 subs r3, #1
8003fa4: b29a uxth r2, r3
8003fa6: 68fb ldr r3, [r7, #12]
8003fa8: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8003faa: 68fb ldr r3, [r7, #12]
8003fac: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fae: 3b01 subs r3, #1
8003fb0: b29a uxth r2, r3
8003fb2: 68fb ldr r3, [r7, #12]
8003fb4: 851a strh r2, [r3, #40] @ 0x28
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
8003fb6: 68fb ldr r3, [r7, #12]
8003fb8: 681b ldr r3, [r3, #0]
8003fba: 695b ldr r3, [r3, #20]
8003fbc: f003 0304 and.w r3, r3, #4
8003fc0: 2b04 cmp r3, #4
8003fc2: d11b bne.n 8003ffc <HAL_I2C_Master_Transmit+0x188>
8003fc4: 68fb ldr r3, [r7, #12]
8003fc6: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fc8: 2b00 cmp r3, #0
8003fca: d017 beq.n 8003ffc <HAL_I2C_Master_Transmit+0x188>
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003fcc: 68fb ldr r3, [r7, #12]
8003fce: 6a5b ldr r3, [r3, #36] @ 0x24
8003fd0: 781a ldrb r2, [r3, #0]
8003fd2: 68fb ldr r3, [r7, #12]
8003fd4: 681b ldr r3, [r3, #0]
8003fd6: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003fd8: 68fb ldr r3, [r7, #12]
8003fda: 6a5b ldr r3, [r3, #36] @ 0x24
8003fdc: 1c5a adds r2, r3, #1
8003fde: 68fb ldr r3, [r7, #12]
8003fe0: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003fe2: 68fb ldr r3, [r7, #12]
8003fe4: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003fe6: b29b uxth r3, r3
8003fe8: 3b01 subs r3, #1
8003fea: b29a uxth r2, r3
8003fec: 68fb ldr r3, [r7, #12]
8003fee: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8003ff0: 68fb ldr r3, [r7, #12]
8003ff2: 8d1b ldrh r3, [r3, #40] @ 0x28
8003ff4: 3b01 subs r3, #1
8003ff6: b29a uxth r2, r3
8003ff8: 68fb ldr r3, [r7, #12]
8003ffa: 851a strh r2, [r3, #40] @ 0x28
}
/* Wait until BTF flag is set */
if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003ffc: 697a ldr r2, [r7, #20]
8003ffe: 6a39 ldr r1, [r7, #32]
8004000: 68f8 ldr r0, [r7, #12]
8004002: f000 fd53 bl 8004aac <I2C_WaitOnBTFFlagUntilTimeout>
8004006: 4603 mov r3, r0
8004008: 2b00 cmp r3, #0
800400a: d00d beq.n 8004028 <HAL_I2C_Master_Transmit+0x1b4>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
800400c: 68fb ldr r3, [r7, #12]
800400e: 6c1b ldr r3, [r3, #64] @ 0x40
8004010: 2b04 cmp r3, #4
8004012: d107 bne.n 8004024 <HAL_I2C_Master_Transmit+0x1b0>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004014: 68fb ldr r3, [r7, #12]
8004016: 681b ldr r3, [r3, #0]
8004018: 681a ldr r2, [r3, #0]
800401a: 68fb ldr r3, [r7, #12]
800401c: 681b ldr r3, [r3, #0]
800401e: f442 7200 orr.w r2, r2, #512 @ 0x200
8004022: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8004024: 2301 movs r3, #1
8004026: e01a b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
while (hi2c->XferSize > 0U)
8004028: 68fb ldr r3, [r7, #12]
800402a: 8d1b ldrh r3, [r3, #40] @ 0x28
800402c: 2b00 cmp r3, #0
800402e: d194 bne.n 8003f5a <HAL_I2C_Master_Transmit+0xe6>
}
}
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004030: 68fb ldr r3, [r7, #12]
8004032: 681b ldr r3, [r3, #0]
8004034: 681a ldr r2, [r3, #0]
8004036: 68fb ldr r3, [r7, #12]
8004038: 681b ldr r3, [r3, #0]
800403a: f442 7200 orr.w r2, r2, #512 @ 0x200
800403e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8004040: 68fb ldr r3, [r7, #12]
8004042: 2220 movs r2, #32
8004044: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004048: 68fb ldr r3, [r7, #12]
800404a: 2200 movs r2, #0
800404c: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004050: 68fb ldr r3, [r7, #12]
8004052: 2200 movs r2, #0
8004054: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8004058: 2300 movs r3, #0
800405a: e000 b.n 800405e <HAL_I2C_Master_Transmit+0x1ea>
}
else
{
return HAL_BUSY;
800405c: 2302 movs r3, #2
}
}
800405e: 4618 mov r0, r3
8004060: 3718 adds r7, #24
8004062: 46bd mov sp, r7
8004064: bd80 pop {r7, pc}
8004066: bf00 nop
8004068: 00100002 .word 0x00100002
800406c: ffff0000 .word 0xffff0000
08004070 <HAL_I2C_Master_Receive>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8004070: b580 push {r7, lr}
8004072: b08c sub sp, #48 @ 0x30
8004074: af02 add r7, sp, #8
8004076: 60f8 str r0, [r7, #12]
8004078: 607a str r2, [r7, #4]
800407a: 461a mov r2, r3
800407c: 460b mov r3, r1
800407e: 817b strh r3, [r7, #10]
8004080: 4613 mov r3, r2
8004082: 813b strh r3, [r7, #8]
__IO uint32_t count = 0U;
8004084: 2300 movs r3, #0
8004086: 623b str r3, [r7, #32]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
8004088: f7fe ffe4 bl 8003054 <HAL_GetTick>
800408c: 6278 str r0, [r7, #36] @ 0x24
if (hi2c->State == HAL_I2C_STATE_READY)
800408e: 68fb ldr r3, [r7, #12]
8004090: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004094: b2db uxtb r3, r3
8004096: 2b20 cmp r3, #32
8004098: f040 824b bne.w 8004532 <HAL_I2C_Master_Receive+0x4c2>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
800409c: 6a7b ldr r3, [r7, #36] @ 0x24
800409e: 9300 str r3, [sp, #0]
80040a0: 2319 movs r3, #25
80040a2: 2201 movs r2, #1
80040a4: 497f ldr r1, [pc, #508] @ (80042a4 <HAL_I2C_Master_Receive+0x234>)
80040a6: 68f8 ldr r0, [r7, #12]
80040a8: f000 fb9e bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
80040ac: 4603 mov r3, r0
80040ae: 2b00 cmp r3, #0
80040b0: d001 beq.n 80040b6 <HAL_I2C_Master_Receive+0x46>
{
return HAL_BUSY;
80040b2: 2302 movs r3, #2
80040b4: e23e b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80040b6: 68fb ldr r3, [r7, #12]
80040b8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80040bc: 2b01 cmp r3, #1
80040be: d101 bne.n 80040c4 <HAL_I2C_Master_Receive+0x54>
80040c0: 2302 movs r3, #2
80040c2: e237 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
80040c4: 68fb ldr r3, [r7, #12]
80040c6: 2201 movs r2, #1
80040c8: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
80040cc: 68fb ldr r3, [r7, #12]
80040ce: 681b ldr r3, [r3, #0]
80040d0: 681b ldr r3, [r3, #0]
80040d2: f003 0301 and.w r3, r3, #1
80040d6: 2b01 cmp r3, #1
80040d8: d007 beq.n 80040ea <HAL_I2C_Master_Receive+0x7a>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80040da: 68fb ldr r3, [r7, #12]
80040dc: 681b ldr r3, [r3, #0]
80040de: 681a ldr r2, [r3, #0]
80040e0: 68fb ldr r3, [r7, #12]
80040e2: 681b ldr r3, [r3, #0]
80040e4: f042 0201 orr.w r2, r2, #1
80040e8: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
80040ea: 68fb ldr r3, [r7, #12]
80040ec: 681b ldr r3, [r3, #0]
80040ee: 681a ldr r2, [r3, #0]
80040f0: 68fb ldr r3, [r7, #12]
80040f2: 681b ldr r3, [r3, #0]
80040f4: f422 6200 bic.w r2, r2, #2048 @ 0x800
80040f8: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80040fa: 68fb ldr r3, [r7, #12]
80040fc: 2222 movs r2, #34 @ 0x22
80040fe: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8004102: 68fb ldr r3, [r7, #12]
8004104: 2210 movs r2, #16
8004106: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800410a: 68fb ldr r3, [r7, #12]
800410c: 2200 movs r2, #0
800410e: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8004110: 68fb ldr r3, [r7, #12]
8004112: 687a ldr r2, [r7, #4]
8004114: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8004116: 68fb ldr r3, [r7, #12]
8004118: 893a ldrh r2, [r7, #8]
800411a: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
800411c: 68fb ldr r3, [r7, #12]
800411e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004120: b29a uxth r2, r3
8004122: 68fb ldr r3, [r7, #12]
8004124: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8004126: 68fb ldr r3, [r7, #12]
8004128: 4a5f ldr r2, [pc, #380] @ (80042a8 <HAL_I2C_Master_Receive+0x238>)
800412a: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
800412c: 8979 ldrh r1, [r7, #10]
800412e: 6a7b ldr r3, [r7, #36] @ 0x24
8004130: 6b3a ldr r2, [r7, #48] @ 0x30
8004132: 68f8 ldr r0, [r7, #12]
8004134: f000 fa8a bl 800464c <I2C_MasterRequestRead>
8004138: 4603 mov r3, r0
800413a: 2b00 cmp r3, #0
800413c: d001 beq.n 8004142 <HAL_I2C_Master_Receive+0xd2>
{
return HAL_ERROR;
800413e: 2301 movs r3, #1
8004140: e1f8 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
if (hi2c->XferSize == 0U)
8004142: 68fb ldr r3, [r7, #12]
8004144: 8d1b ldrh r3, [r3, #40] @ 0x28
8004146: 2b00 cmp r3, #0
8004148: d113 bne.n 8004172 <HAL_I2C_Master_Receive+0x102>
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
800414a: 2300 movs r3, #0
800414c: 61fb str r3, [r7, #28]
800414e: 68fb ldr r3, [r7, #12]
8004150: 681b ldr r3, [r3, #0]
8004152: 695b ldr r3, [r3, #20]
8004154: 61fb str r3, [r7, #28]
8004156: 68fb ldr r3, [r7, #12]
8004158: 681b ldr r3, [r3, #0]
800415a: 699b ldr r3, [r3, #24]
800415c: 61fb str r3, [r7, #28]
800415e: 69fb ldr r3, [r7, #28]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004160: 68fb ldr r3, [r7, #12]
8004162: 681b ldr r3, [r3, #0]
8004164: 681a ldr r2, [r3, #0]
8004166: 68fb ldr r3, [r7, #12]
8004168: 681b ldr r3, [r3, #0]
800416a: f442 7200 orr.w r2, r2, #512 @ 0x200
800416e: 601a str r2, [r3, #0]
8004170: e1cc b.n 800450c <HAL_I2C_Master_Receive+0x49c>
}
else if (hi2c->XferSize == 1U)
8004172: 68fb ldr r3, [r7, #12]
8004174: 8d1b ldrh r3, [r3, #40] @ 0x28
8004176: 2b01 cmp r3, #1
8004178: d11e bne.n 80041b8 <HAL_I2C_Master_Receive+0x148>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
800417a: 68fb ldr r3, [r7, #12]
800417c: 681b ldr r3, [r3, #0]
800417e: 681a ldr r2, [r3, #0]
8004180: 68fb ldr r3, [r7, #12]
8004182: 681b ldr r3, [r3, #0]
8004184: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004188: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
800418a: b672 cpsid i
}
800418c: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
800418e: 2300 movs r3, #0
8004190: 61bb str r3, [r7, #24]
8004192: 68fb ldr r3, [r7, #12]
8004194: 681b ldr r3, [r3, #0]
8004196: 695b ldr r3, [r3, #20]
8004198: 61bb str r3, [r7, #24]
800419a: 68fb ldr r3, [r7, #12]
800419c: 681b ldr r3, [r3, #0]
800419e: 699b ldr r3, [r3, #24]
80041a0: 61bb str r3, [r7, #24]
80041a2: 69bb ldr r3, [r7, #24]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80041a4: 68fb ldr r3, [r7, #12]
80041a6: 681b ldr r3, [r3, #0]
80041a8: 681a ldr r2, [r3, #0]
80041aa: 68fb ldr r3, [r7, #12]
80041ac: 681b ldr r3, [r3, #0]
80041ae: f442 7200 orr.w r2, r2, #512 @ 0x200
80041b2: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
80041b4: b662 cpsie i
}
80041b6: e035 b.n 8004224 <HAL_I2C_Master_Receive+0x1b4>
/* Re-enable IRQs */
__enable_irq();
}
else if (hi2c->XferSize == 2U)
80041b8: 68fb ldr r3, [r7, #12]
80041ba: 8d1b ldrh r3, [r3, #40] @ 0x28
80041bc: 2b02 cmp r3, #2
80041be: d11e bne.n 80041fe <HAL_I2C_Master_Receive+0x18e>
{
/* Enable Pos */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
80041c0: 68fb ldr r3, [r7, #12]
80041c2: 681b ldr r3, [r3, #0]
80041c4: 681a ldr r2, [r3, #0]
80041c6: 68fb ldr r3, [r7, #12]
80041c8: 681b ldr r3, [r3, #0]
80041ca: f442 6200 orr.w r2, r2, #2048 @ 0x800
80041ce: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
80041d0: b672 cpsid i
}
80041d2: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80041d4: 2300 movs r3, #0
80041d6: 617b str r3, [r7, #20]
80041d8: 68fb ldr r3, [r7, #12]
80041da: 681b ldr r3, [r3, #0]
80041dc: 695b ldr r3, [r3, #20]
80041de: 617b str r3, [r7, #20]
80041e0: 68fb ldr r3, [r7, #12]
80041e2: 681b ldr r3, [r3, #0]
80041e4: 699b ldr r3, [r3, #24]
80041e6: 617b str r3, [r7, #20]
80041e8: 697b ldr r3, [r7, #20]
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80041ea: 68fb ldr r3, [r7, #12]
80041ec: 681b ldr r3, [r3, #0]
80041ee: 681a ldr r2, [r3, #0]
80041f0: 68fb ldr r3, [r7, #12]
80041f2: 681b ldr r3, [r3, #0]
80041f4: f422 6280 bic.w r2, r2, #1024 @ 0x400
80041f8: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
80041fa: b662 cpsie i
}
80041fc: e012 b.n 8004224 <HAL_I2C_Master_Receive+0x1b4>
__enable_irq();
}
else
{
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80041fe: 68fb ldr r3, [r7, #12]
8004200: 681b ldr r3, [r3, #0]
8004202: 681a ldr r2, [r3, #0]
8004204: 68fb ldr r3, [r7, #12]
8004206: 681b ldr r3, [r3, #0]
8004208: f442 6280 orr.w r2, r2, #1024 @ 0x400
800420c: 601a str r2, [r3, #0]
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
800420e: 2300 movs r3, #0
8004210: 613b str r3, [r7, #16]
8004212: 68fb ldr r3, [r7, #12]
8004214: 681b ldr r3, [r3, #0]
8004216: 695b ldr r3, [r3, #20]
8004218: 613b str r3, [r7, #16]
800421a: 68fb ldr r3, [r7, #12]
800421c: 681b ldr r3, [r3, #0]
800421e: 699b ldr r3, [r3, #24]
8004220: 613b str r3, [r7, #16]
8004222: 693b ldr r3, [r7, #16]
}
while (hi2c->XferSize > 0U)
8004224: e172 b.n 800450c <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize <= 3U)
8004226: 68fb ldr r3, [r7, #12]
8004228: 8d1b ldrh r3, [r3, #40] @ 0x28
800422a: 2b03 cmp r3, #3
800422c: f200 811f bhi.w 800446e <HAL_I2C_Master_Receive+0x3fe>
{
/* One byte */
if (hi2c->XferSize == 1U)
8004230: 68fb ldr r3, [r7, #12]
8004232: 8d1b ldrh r3, [r3, #40] @ 0x28
8004234: 2b01 cmp r3, #1
8004236: d123 bne.n 8004280 <HAL_I2C_Master_Receive+0x210>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004238: 6a7a ldr r2, [r7, #36] @ 0x24
800423a: 6b39 ldr r1, [r7, #48] @ 0x30
800423c: 68f8 ldr r0, [r7, #12]
800423e: f000 fc7d bl 8004b3c <I2C_WaitOnRXNEFlagUntilTimeout>
8004242: 4603 mov r3, r0
8004244: 2b00 cmp r3, #0
8004246: d001 beq.n 800424c <HAL_I2C_Master_Receive+0x1dc>
{
return HAL_ERROR;
8004248: 2301 movs r3, #1
800424a: e173 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800424c: 68fb ldr r3, [r7, #12]
800424e: 681b ldr r3, [r3, #0]
8004250: 691a ldr r2, [r3, #16]
8004252: 68fb ldr r3, [r7, #12]
8004254: 6a5b ldr r3, [r3, #36] @ 0x24
8004256: b2d2 uxtb r2, r2
8004258: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800425a: 68fb ldr r3, [r7, #12]
800425c: 6a5b ldr r3, [r3, #36] @ 0x24
800425e: 1c5a adds r2, r3, #1
8004260: 68fb ldr r3, [r7, #12]
8004262: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004264: 68fb ldr r3, [r7, #12]
8004266: 8d1b ldrh r3, [r3, #40] @ 0x28
8004268: 3b01 subs r3, #1
800426a: b29a uxth r2, r3
800426c: 68fb ldr r3, [r7, #12]
800426e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004270: 68fb ldr r3, [r7, #12]
8004272: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004274: b29b uxth r3, r3
8004276: 3b01 subs r3, #1
8004278: b29a uxth r2, r3
800427a: 68fb ldr r3, [r7, #12]
800427c: 855a strh r2, [r3, #42] @ 0x2a
800427e: e145 b.n 800450c <HAL_I2C_Master_Receive+0x49c>
}
/* Two bytes */
else if (hi2c->XferSize == 2U)
8004280: 68fb ldr r3, [r7, #12]
8004282: 8d1b ldrh r3, [r3, #40] @ 0x28
8004284: 2b02 cmp r3, #2
8004286: d152 bne.n 800432e <HAL_I2C_Master_Receive+0x2be>
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
8004288: 6a7b ldr r3, [r7, #36] @ 0x24
800428a: 9300 str r3, [sp, #0]
800428c: 6b3b ldr r3, [r7, #48] @ 0x30
800428e: 2200 movs r2, #0
8004290: 4906 ldr r1, [pc, #24] @ (80042ac <HAL_I2C_Master_Receive+0x23c>)
8004292: 68f8 ldr r0, [r7, #12]
8004294: f000 faa8 bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
8004298: 4603 mov r3, r0
800429a: 2b00 cmp r3, #0
800429c: d008 beq.n 80042b0 <HAL_I2C_Master_Receive+0x240>
{
return HAL_ERROR;
800429e: 2301 movs r3, #1
80042a0: e148 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
80042a2: bf00 nop
80042a4: 00100002 .word 0x00100002
80042a8: ffff0000 .word 0xffff0000
80042ac: 00010004 .word 0x00010004
__ASM volatile ("cpsid i" : : : "memory");
80042b0: b672 cpsid i
}
80042b2: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80042b4: 68fb ldr r3, [r7, #12]
80042b6: 681b ldr r3, [r3, #0]
80042b8: 681a ldr r2, [r3, #0]
80042ba: 68fb ldr r3, [r7, #12]
80042bc: 681b ldr r3, [r3, #0]
80042be: f442 7200 orr.w r2, r2, #512 @ 0x200
80042c2: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80042c4: 68fb ldr r3, [r7, #12]
80042c6: 681b ldr r3, [r3, #0]
80042c8: 691a ldr r2, [r3, #16]
80042ca: 68fb ldr r3, [r7, #12]
80042cc: 6a5b ldr r3, [r3, #36] @ 0x24
80042ce: b2d2 uxtb r2, r2
80042d0: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80042d2: 68fb ldr r3, [r7, #12]
80042d4: 6a5b ldr r3, [r3, #36] @ 0x24
80042d6: 1c5a adds r2, r3, #1
80042d8: 68fb ldr r3, [r7, #12]
80042da: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80042dc: 68fb ldr r3, [r7, #12]
80042de: 8d1b ldrh r3, [r3, #40] @ 0x28
80042e0: 3b01 subs r3, #1
80042e2: b29a uxth r2, r3
80042e4: 68fb ldr r3, [r7, #12]
80042e6: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80042e8: 68fb ldr r3, [r7, #12]
80042ea: 8d5b ldrh r3, [r3, #42] @ 0x2a
80042ec: b29b uxth r3, r3
80042ee: 3b01 subs r3, #1
80042f0: b29a uxth r2, r3
80042f2: 68fb ldr r3, [r7, #12]
80042f4: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
80042f6: b662 cpsie i
}
80042f8: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80042fa: 68fb ldr r3, [r7, #12]
80042fc: 681b ldr r3, [r3, #0]
80042fe: 691a ldr r2, [r3, #16]
8004300: 68fb ldr r3, [r7, #12]
8004302: 6a5b ldr r3, [r3, #36] @ 0x24
8004304: b2d2 uxtb r2, r2
8004306: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004308: 68fb ldr r3, [r7, #12]
800430a: 6a5b ldr r3, [r3, #36] @ 0x24
800430c: 1c5a adds r2, r3, #1
800430e: 68fb ldr r3, [r7, #12]
8004310: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004312: 68fb ldr r3, [r7, #12]
8004314: 8d1b ldrh r3, [r3, #40] @ 0x28
8004316: 3b01 subs r3, #1
8004318: b29a uxth r2, r3
800431a: 68fb ldr r3, [r7, #12]
800431c: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
800431e: 68fb ldr r3, [r7, #12]
8004320: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004322: b29b uxth r3, r3
8004324: 3b01 subs r3, #1
8004326: b29a uxth r2, r3
8004328: 68fb ldr r3, [r7, #12]
800432a: 855a strh r2, [r3, #42] @ 0x2a
800432c: e0ee b.n 800450c <HAL_I2C_Master_Receive+0x49c>
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
800432e: 6a7b ldr r3, [r7, #36] @ 0x24
8004330: 9300 str r3, [sp, #0]
8004332: 6b3b ldr r3, [r7, #48] @ 0x30
8004334: 2200 movs r2, #0
8004336: 4981 ldr r1, [pc, #516] @ (800453c <HAL_I2C_Master_Receive+0x4cc>)
8004338: 68f8 ldr r0, [r7, #12]
800433a: f000 fa55 bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
800433e: 4603 mov r3, r0
8004340: 2b00 cmp r3, #0
8004342: d001 beq.n 8004348 <HAL_I2C_Master_Receive+0x2d8>
{
return HAL_ERROR;
8004344: 2301 movs r3, #1
8004346: e0f5 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004348: 68fb ldr r3, [r7, #12]
800434a: 681b ldr r3, [r3, #0]
800434c: 681a ldr r2, [r3, #0]
800434e: 68fb ldr r3, [r7, #12]
8004350: 681b ldr r3, [r3, #0]
8004352: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004356: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8004358: b672 cpsid i
}
800435a: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800435c: 68fb ldr r3, [r7, #12]
800435e: 681b ldr r3, [r3, #0]
8004360: 691a ldr r2, [r3, #16]
8004362: 68fb ldr r3, [r7, #12]
8004364: 6a5b ldr r3, [r3, #36] @ 0x24
8004366: b2d2 uxtb r2, r2
8004368: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800436a: 68fb ldr r3, [r7, #12]
800436c: 6a5b ldr r3, [r3, #36] @ 0x24
800436e: 1c5a adds r2, r3, #1
8004370: 68fb ldr r3, [r7, #12]
8004372: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004374: 68fb ldr r3, [r7, #12]
8004376: 8d1b ldrh r3, [r3, #40] @ 0x28
8004378: 3b01 subs r3, #1
800437a: b29a uxth r2, r3
800437c: 68fb ldr r3, [r7, #12]
800437e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004380: 68fb ldr r3, [r7, #12]
8004382: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004384: b29b uxth r3, r3
8004386: 3b01 subs r3, #1
8004388: b29a uxth r2, r3
800438a: 68fb ldr r3, [r7, #12]
800438c: 855a strh r2, [r3, #42] @ 0x2a
/* Wait until BTF flag is set */
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
800438e: 4b6c ldr r3, [pc, #432] @ (8004540 <HAL_I2C_Master_Receive+0x4d0>)
8004390: 681b ldr r3, [r3, #0]
8004392: 08db lsrs r3, r3, #3
8004394: 4a6b ldr r2, [pc, #428] @ (8004544 <HAL_I2C_Master_Receive+0x4d4>)
8004396: fba2 2303 umull r2, r3, r2, r3
800439a: 0a1a lsrs r2, r3, #8
800439c: 4613 mov r3, r2
800439e: 009b lsls r3, r3, #2
80043a0: 4413 add r3, r2
80043a2: 00da lsls r2, r3, #3
80043a4: 1ad3 subs r3, r2, r3
80043a6: 623b str r3, [r7, #32]
do
{
count--;
80043a8: 6a3b ldr r3, [r7, #32]
80043aa: 3b01 subs r3, #1
80043ac: 623b str r3, [r7, #32]
if (count == 0U)
80043ae: 6a3b ldr r3, [r7, #32]
80043b0: 2b00 cmp r3, #0
80043b2: d118 bne.n 80043e6 <HAL_I2C_Master_Receive+0x376>
{
hi2c->PreviousState = I2C_STATE_NONE;
80043b4: 68fb ldr r3, [r7, #12]
80043b6: 2200 movs r2, #0
80043b8: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80043ba: 68fb ldr r3, [r7, #12]
80043bc: 2220 movs r2, #32
80043be: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80043c2: 68fb ldr r3, [r7, #12]
80043c4: 2200 movs r2, #0
80043c6: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80043ca: 68fb ldr r3, [r7, #12]
80043cc: 6c1b ldr r3, [r3, #64] @ 0x40
80043ce: f043 0220 orr.w r2, r3, #32
80043d2: 68fb ldr r3, [r7, #12]
80043d4: 641a str r2, [r3, #64] @ 0x40
__ASM volatile ("cpsie i" : : : "memory");
80043d6: b662 cpsie i
}
80043d8: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80043da: 68fb ldr r3, [r7, #12]
80043dc: 2200 movs r2, #0
80043de: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80043e2: 2301 movs r3, #1
80043e4: e0a6 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
80043e6: 68fb ldr r3, [r7, #12]
80043e8: 681b ldr r3, [r3, #0]
80043ea: 695b ldr r3, [r3, #20]
80043ec: f003 0304 and.w r3, r3, #4
80043f0: 2b04 cmp r3, #4
80043f2: d1d9 bne.n 80043a8 <HAL_I2C_Master_Receive+0x338>
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80043f4: 68fb ldr r3, [r7, #12]
80043f6: 681b ldr r3, [r3, #0]
80043f8: 681a ldr r2, [r3, #0]
80043fa: 68fb ldr r3, [r7, #12]
80043fc: 681b ldr r3, [r3, #0]
80043fe: f442 7200 orr.w r2, r2, #512 @ 0x200
8004402: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004404: 68fb ldr r3, [r7, #12]
8004406: 681b ldr r3, [r3, #0]
8004408: 691a ldr r2, [r3, #16]
800440a: 68fb ldr r3, [r7, #12]
800440c: 6a5b ldr r3, [r3, #36] @ 0x24
800440e: b2d2 uxtb r2, r2
8004410: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004412: 68fb ldr r3, [r7, #12]
8004414: 6a5b ldr r3, [r3, #36] @ 0x24
8004416: 1c5a adds r2, r3, #1
8004418: 68fb ldr r3, [r7, #12]
800441a: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800441c: 68fb ldr r3, [r7, #12]
800441e: 8d1b ldrh r3, [r3, #40] @ 0x28
8004420: 3b01 subs r3, #1
8004422: b29a uxth r2, r3
8004424: 68fb ldr r3, [r7, #12]
8004426: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004428: 68fb ldr r3, [r7, #12]
800442a: 8d5b ldrh r3, [r3, #42] @ 0x2a
800442c: b29b uxth r3, r3
800442e: 3b01 subs r3, #1
8004430: b29a uxth r2, r3
8004432: 68fb ldr r3, [r7, #12]
8004434: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
8004436: b662 cpsie i
}
8004438: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800443a: 68fb ldr r3, [r7, #12]
800443c: 681b ldr r3, [r3, #0]
800443e: 691a ldr r2, [r3, #16]
8004440: 68fb ldr r3, [r7, #12]
8004442: 6a5b ldr r3, [r3, #36] @ 0x24
8004444: b2d2 uxtb r2, r2
8004446: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004448: 68fb ldr r3, [r7, #12]
800444a: 6a5b ldr r3, [r3, #36] @ 0x24
800444c: 1c5a adds r2, r3, #1
800444e: 68fb ldr r3, [r7, #12]
8004450: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004452: 68fb ldr r3, [r7, #12]
8004454: 8d1b ldrh r3, [r3, #40] @ 0x28
8004456: 3b01 subs r3, #1
8004458: b29a uxth r2, r3
800445a: 68fb ldr r3, [r7, #12]
800445c: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
800445e: 68fb ldr r3, [r7, #12]
8004460: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004462: b29b uxth r3, r3
8004464: 3b01 subs r3, #1
8004466: b29a uxth r2, r3
8004468: 68fb ldr r3, [r7, #12]
800446a: 855a strh r2, [r3, #42] @ 0x2a
800446c: e04e b.n 800450c <HAL_I2C_Master_Receive+0x49c>
}
}
else
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800446e: 6a7a ldr r2, [r7, #36] @ 0x24
8004470: 6b39 ldr r1, [r7, #48] @ 0x30
8004472: 68f8 ldr r0, [r7, #12]
8004474: f000 fb62 bl 8004b3c <I2C_WaitOnRXNEFlagUntilTimeout>
8004478: 4603 mov r3, r0
800447a: 2b00 cmp r3, #0
800447c: d001 beq.n 8004482 <HAL_I2C_Master_Receive+0x412>
{
return HAL_ERROR;
800447e: 2301 movs r3, #1
8004480: e058 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004482: 68fb ldr r3, [r7, #12]
8004484: 681b ldr r3, [r3, #0]
8004486: 691a ldr r2, [r3, #16]
8004488: 68fb ldr r3, [r7, #12]
800448a: 6a5b ldr r3, [r3, #36] @ 0x24
800448c: b2d2 uxtb r2, r2
800448e: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004490: 68fb ldr r3, [r7, #12]
8004492: 6a5b ldr r3, [r3, #36] @ 0x24
8004494: 1c5a adds r2, r3, #1
8004496: 68fb ldr r3, [r7, #12]
8004498: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800449a: 68fb ldr r3, [r7, #12]
800449c: 8d1b ldrh r3, [r3, #40] @ 0x28
800449e: 3b01 subs r3, #1
80044a0: b29a uxth r2, r3
80044a2: 68fb ldr r3, [r7, #12]
80044a4: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80044a6: 68fb ldr r3, [r7, #12]
80044a8: 8d5b ldrh r3, [r3, #42] @ 0x2a
80044aa: b29b uxth r3, r3
80044ac: 3b01 subs r3, #1
80044ae: b29a uxth r2, r3
80044b0: 68fb ldr r3, [r7, #12]
80044b2: 855a strh r2, [r3, #42] @ 0x2a
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
80044b4: 68fb ldr r3, [r7, #12]
80044b6: 681b ldr r3, [r3, #0]
80044b8: 695b ldr r3, [r3, #20]
80044ba: f003 0304 and.w r3, r3, #4
80044be: 2b04 cmp r3, #4
80044c0: d124 bne.n 800450c <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize == 3U)
80044c2: 68fb ldr r3, [r7, #12]
80044c4: 8d1b ldrh r3, [r3, #40] @ 0x28
80044c6: 2b03 cmp r3, #3
80044c8: d107 bne.n 80044da <HAL_I2C_Master_Receive+0x46a>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80044ca: 68fb ldr r3, [r7, #12]
80044cc: 681b ldr r3, [r3, #0]
80044ce: 681a ldr r2, [r3, #0]
80044d0: 68fb ldr r3, [r7, #12]
80044d2: 681b ldr r3, [r3, #0]
80044d4: f422 6280 bic.w r2, r2, #1024 @ 0x400
80044d8: 601a str r2, [r3, #0]
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80044da: 68fb ldr r3, [r7, #12]
80044dc: 681b ldr r3, [r3, #0]
80044de: 691a ldr r2, [r3, #16]
80044e0: 68fb ldr r3, [r7, #12]
80044e2: 6a5b ldr r3, [r3, #36] @ 0x24
80044e4: b2d2 uxtb r2, r2
80044e6: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80044e8: 68fb ldr r3, [r7, #12]
80044ea: 6a5b ldr r3, [r3, #36] @ 0x24
80044ec: 1c5a adds r2, r3, #1
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80044f2: 68fb ldr r3, [r7, #12]
80044f4: 8d1b ldrh r3, [r3, #40] @ 0x28
80044f6: 3b01 subs r3, #1
80044f8: b29a uxth r2, r3
80044fa: 68fb ldr r3, [r7, #12]
80044fc: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80044fe: 68fb ldr r3, [r7, #12]
8004500: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004502: b29b uxth r3, r3
8004504: 3b01 subs r3, #1
8004506: b29a uxth r2, r3
8004508: 68fb ldr r3, [r7, #12]
800450a: 855a strh r2, [r3, #42] @ 0x2a
while (hi2c->XferSize > 0U)
800450c: 68fb ldr r3, [r7, #12]
800450e: 8d1b ldrh r3, [r3, #40] @ 0x28
8004510: 2b00 cmp r3, #0
8004512: f47f ae88 bne.w 8004226 <HAL_I2C_Master_Receive+0x1b6>
}
}
}
hi2c->State = HAL_I2C_STATE_READY;
8004516: 68fb ldr r3, [r7, #12]
8004518: 2220 movs r2, #32
800451a: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
800451e: 68fb ldr r3, [r7, #12]
8004520: 2200 movs r2, #0
8004522: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004526: 68fb ldr r3, [r7, #12]
8004528: 2200 movs r2, #0
800452a: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
800452e: 2300 movs r3, #0
8004530: e000 b.n 8004534 <HAL_I2C_Master_Receive+0x4c4>
}
else
{
return HAL_BUSY;
8004532: 2302 movs r3, #2
}
}
8004534: 4618 mov r0, r3
8004536: 3728 adds r7, #40 @ 0x28
8004538: 46bd mov sp, r7
800453a: bd80 pop {r7, pc}
800453c: 00010004 .word 0x00010004
8004540: 20000004 .word 0x20000004
8004544: 14f8b589 .word 0x14f8b589
08004548 <I2C_MasterRequestWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
8004548: b580 push {r7, lr}
800454a: b088 sub sp, #32
800454c: af02 add r7, sp, #8
800454e: 60f8 str r0, [r7, #12]
8004550: 607a str r2, [r7, #4]
8004552: 603b str r3, [r7, #0]
8004554: 460b mov r3, r1
8004556: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
8004558: 68fb ldr r3, [r7, #12]
800455a: 6adb ldr r3, [r3, #44] @ 0x2c
800455c: 617b str r3, [r7, #20]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
800455e: 697b ldr r3, [r7, #20]
8004560: 2b08 cmp r3, #8
8004562: d006 beq.n 8004572 <I2C_MasterRequestWrite+0x2a>
8004564: 697b ldr r3, [r7, #20]
8004566: 2b01 cmp r3, #1
8004568: d003 beq.n 8004572 <I2C_MasterRequestWrite+0x2a>
800456a: 697b ldr r3, [r7, #20]
800456c: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004570: d108 bne.n 8004584 <I2C_MasterRequestWrite+0x3c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004572: 68fb ldr r3, [r7, #12]
8004574: 681b ldr r3, [r3, #0]
8004576: 681a ldr r2, [r3, #0]
8004578: 68fb ldr r3, [r7, #12]
800457a: 681b ldr r3, [r3, #0]
800457c: f442 7280 orr.w r2, r2, #256 @ 0x100
8004580: 601a str r2, [r3, #0]
8004582: e00b b.n 800459c <I2C_MasterRequestWrite+0x54>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
8004584: 68fb ldr r3, [r7, #12]
8004586: 6b1b ldr r3, [r3, #48] @ 0x30
8004588: 2b12 cmp r3, #18
800458a: d107 bne.n 800459c <I2C_MasterRequestWrite+0x54>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800458c: 68fb ldr r3, [r7, #12]
800458e: 681b ldr r3, [r3, #0]
8004590: 681a ldr r2, [r3, #0]
8004592: 68fb ldr r3, [r7, #12]
8004594: 681b ldr r3, [r3, #0]
8004596: f442 7280 orr.w r2, r2, #256 @ 0x100
800459a: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
800459c: 683b ldr r3, [r7, #0]
800459e: 9300 str r3, [sp, #0]
80045a0: 687b ldr r3, [r7, #4]
80045a2: 2200 movs r2, #0
80045a4: f04f 1101 mov.w r1, #65537 @ 0x10001
80045a8: 68f8 ldr r0, [r7, #12]
80045aa: f000 f91d bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
80045ae: 4603 mov r3, r0
80045b0: 2b00 cmp r3, #0
80045b2: d00d beq.n 80045d0 <I2C_MasterRequestWrite+0x88>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80045b4: 68fb ldr r3, [r7, #12]
80045b6: 681b ldr r3, [r3, #0]
80045b8: 681b ldr r3, [r3, #0]
80045ba: f403 7380 and.w r3, r3, #256 @ 0x100
80045be: f5b3 7f80 cmp.w r3, #256 @ 0x100
80045c2: d103 bne.n 80045cc <I2C_MasterRequestWrite+0x84>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80045c4: 68fb ldr r3, [r7, #12]
80045c6: f44f 7200 mov.w r2, #512 @ 0x200
80045ca: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80045cc: 2303 movs r3, #3
80045ce: e035 b.n 800463c <I2C_MasterRequestWrite+0xf4>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80045d0: 68fb ldr r3, [r7, #12]
80045d2: 691b ldr r3, [r3, #16]
80045d4: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80045d8: d108 bne.n 80045ec <I2C_MasterRequestWrite+0xa4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
80045da: 897b ldrh r3, [r7, #10]
80045dc: b2db uxtb r3, r3
80045de: 461a mov r2, r3
80045e0: 68fb ldr r3, [r7, #12]
80045e2: 681b ldr r3, [r3, #0]
80045e4: f002 02fe and.w r2, r2, #254 @ 0xfe
80045e8: 611a str r2, [r3, #16]
80045ea: e01b b.n 8004624 <I2C_MasterRequestWrite+0xdc>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
80045ec: 897b ldrh r3, [r7, #10]
80045ee: 11db asrs r3, r3, #7
80045f0: b2db uxtb r3, r3
80045f2: f003 0306 and.w r3, r3, #6
80045f6: b2db uxtb r3, r3
80045f8: f063 030f orn r3, r3, #15
80045fc: b2da uxtb r2, r3
80045fe: 68fb ldr r3, [r7, #12]
8004600: 681b ldr r3, [r3, #0]
8004602: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
8004604: 683b ldr r3, [r7, #0]
8004606: 687a ldr r2, [r7, #4]
8004608: 490e ldr r1, [pc, #56] @ (8004644 <I2C_MasterRequestWrite+0xfc>)
800460a: 68f8 ldr r0, [r7, #12]
800460c: f000 f966 bl 80048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004610: 4603 mov r3, r0
8004612: 2b00 cmp r3, #0
8004614: d001 beq.n 800461a <I2C_MasterRequestWrite+0xd2>
{
return HAL_ERROR;
8004616: 2301 movs r3, #1
8004618: e010 b.n 800463c <I2C_MasterRequestWrite+0xf4>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
800461a: 897b ldrh r3, [r7, #10]
800461c: b2da uxtb r2, r3
800461e: 68fb ldr r3, [r7, #12]
8004620: 681b ldr r3, [r3, #0]
8004622: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
8004624: 683b ldr r3, [r7, #0]
8004626: 687a ldr r2, [r7, #4]
8004628: 4907 ldr r1, [pc, #28] @ (8004648 <I2C_MasterRequestWrite+0x100>)
800462a: 68f8 ldr r0, [r7, #12]
800462c: f000 f956 bl 80048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004630: 4603 mov r3, r0
8004632: 2b00 cmp r3, #0
8004634: d001 beq.n 800463a <I2C_MasterRequestWrite+0xf2>
{
return HAL_ERROR;
8004636: 2301 movs r3, #1
8004638: e000 b.n 800463c <I2C_MasterRequestWrite+0xf4>
}
return HAL_OK;
800463a: 2300 movs r3, #0
}
800463c: 4618 mov r0, r3
800463e: 3718 adds r7, #24
8004640: 46bd mov sp, r7
8004642: bd80 pop {r7, pc}
8004644: 00010008 .word 0x00010008
8004648: 00010002 .word 0x00010002
0800464c <I2C_MasterRequestRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
800464c: b580 push {r7, lr}
800464e: b088 sub sp, #32
8004650: af02 add r7, sp, #8
8004652: 60f8 str r0, [r7, #12]
8004654: 607a str r2, [r7, #4]
8004656: 603b str r3, [r7, #0]
8004658: 460b mov r3, r1
800465a: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
800465c: 68fb ldr r3, [r7, #12]
800465e: 6adb ldr r3, [r3, #44] @ 0x2c
8004660: 617b str r3, [r7, #20]
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004662: 68fb ldr r3, [r7, #12]
8004664: 681b ldr r3, [r3, #0]
8004666: 681a ldr r2, [r3, #0]
8004668: 68fb ldr r3, [r7, #12]
800466a: 681b ldr r3, [r3, #0]
800466c: f442 6280 orr.w r2, r2, #1024 @ 0x400
8004670: 601a str r2, [r3, #0]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
8004672: 697b ldr r3, [r7, #20]
8004674: 2b08 cmp r3, #8
8004676: d006 beq.n 8004686 <I2C_MasterRequestRead+0x3a>
8004678: 697b ldr r3, [r7, #20]
800467a: 2b01 cmp r3, #1
800467c: d003 beq.n 8004686 <I2C_MasterRequestRead+0x3a>
800467e: 697b ldr r3, [r7, #20]
8004680: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004684: d108 bne.n 8004698 <I2C_MasterRequestRead+0x4c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004686: 68fb ldr r3, [r7, #12]
8004688: 681b ldr r3, [r3, #0]
800468a: 681a ldr r2, [r3, #0]
800468c: 68fb ldr r3, [r7, #12]
800468e: 681b ldr r3, [r3, #0]
8004690: f442 7280 orr.w r2, r2, #256 @ 0x100
8004694: 601a str r2, [r3, #0]
8004696: e00b b.n 80046b0 <I2C_MasterRequestRead+0x64>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
8004698: 68fb ldr r3, [r7, #12]
800469a: 6b1b ldr r3, [r3, #48] @ 0x30
800469c: 2b11 cmp r3, #17
800469e: d107 bne.n 80046b0 <I2C_MasterRequestRead+0x64>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80046a0: 68fb ldr r3, [r7, #12]
80046a2: 681b ldr r3, [r3, #0]
80046a4: 681a ldr r2, [r3, #0]
80046a6: 68fb ldr r3, [r7, #12]
80046a8: 681b ldr r3, [r3, #0]
80046aa: f442 7280 orr.w r2, r2, #256 @ 0x100
80046ae: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
80046b0: 683b ldr r3, [r7, #0]
80046b2: 9300 str r3, [sp, #0]
80046b4: 687b ldr r3, [r7, #4]
80046b6: 2200 movs r2, #0
80046b8: f04f 1101 mov.w r1, #65537 @ 0x10001
80046bc: 68f8 ldr r0, [r7, #12]
80046be: f000 f893 bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
80046c2: 4603 mov r3, r0
80046c4: 2b00 cmp r3, #0
80046c6: d00d beq.n 80046e4 <I2C_MasterRequestRead+0x98>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80046c8: 68fb ldr r3, [r7, #12]
80046ca: 681b ldr r3, [r3, #0]
80046cc: 681b ldr r3, [r3, #0]
80046ce: f403 7380 and.w r3, r3, #256 @ 0x100
80046d2: f5b3 7f80 cmp.w r3, #256 @ 0x100
80046d6: d103 bne.n 80046e0 <I2C_MasterRequestRead+0x94>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80046d8: 68fb ldr r3, [r7, #12]
80046da: f44f 7200 mov.w r2, #512 @ 0x200
80046de: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80046e0: 2303 movs r3, #3
80046e2: e079 b.n 80047d8 <I2C_MasterRequestRead+0x18c>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80046e4: 68fb ldr r3, [r7, #12]
80046e6: 691b ldr r3, [r3, #16]
80046e8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80046ec: d108 bne.n 8004700 <I2C_MasterRequestRead+0xb4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
80046ee: 897b ldrh r3, [r7, #10]
80046f0: b2db uxtb r3, r3
80046f2: f043 0301 orr.w r3, r3, #1
80046f6: b2da uxtb r2, r3
80046f8: 68fb ldr r3, [r7, #12]
80046fa: 681b ldr r3, [r3, #0]
80046fc: 611a str r2, [r3, #16]
80046fe: e05f b.n 80047c0 <I2C_MasterRequestRead+0x174>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004700: 897b ldrh r3, [r7, #10]
8004702: 11db asrs r3, r3, #7
8004704: b2db uxtb r3, r3
8004706: f003 0306 and.w r3, r3, #6
800470a: b2db uxtb r3, r3
800470c: f063 030f orn r3, r3, #15
8004710: b2da uxtb r2, r3
8004712: 68fb ldr r3, [r7, #12]
8004714: 681b ldr r3, [r3, #0]
8004716: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
8004718: 683b ldr r3, [r7, #0]
800471a: 687a ldr r2, [r7, #4]
800471c: 4930 ldr r1, [pc, #192] @ (80047e0 <I2C_MasterRequestRead+0x194>)
800471e: 68f8 ldr r0, [r7, #12]
8004720: f000 f8dc bl 80048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004724: 4603 mov r3, r0
8004726: 2b00 cmp r3, #0
8004728: d001 beq.n 800472e <I2C_MasterRequestRead+0xe2>
{
return HAL_ERROR;
800472a: 2301 movs r3, #1
800472c: e054 b.n 80047d8 <I2C_MasterRequestRead+0x18c>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
800472e: 897b ldrh r3, [r7, #10]
8004730: b2da uxtb r2, r3
8004732: 68fb ldr r3, [r7, #12]
8004734: 681b ldr r3, [r3, #0]
8004736: 611a str r2, [r3, #16]
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
8004738: 683b ldr r3, [r7, #0]
800473a: 687a ldr r2, [r7, #4]
800473c: 4929 ldr r1, [pc, #164] @ (80047e4 <I2C_MasterRequestRead+0x198>)
800473e: 68f8 ldr r0, [r7, #12]
8004740: f000 f8cc bl 80048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004744: 4603 mov r3, r0
8004746: 2b00 cmp r3, #0
8004748: d001 beq.n 800474e <I2C_MasterRequestRead+0x102>
{
return HAL_ERROR;
800474a: 2301 movs r3, #1
800474c: e044 b.n 80047d8 <I2C_MasterRequestRead+0x18c>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
800474e: 2300 movs r3, #0
8004750: 613b str r3, [r7, #16]
8004752: 68fb ldr r3, [r7, #12]
8004754: 681b ldr r3, [r3, #0]
8004756: 695b ldr r3, [r3, #20]
8004758: 613b str r3, [r7, #16]
800475a: 68fb ldr r3, [r7, #12]
800475c: 681b ldr r3, [r3, #0]
800475e: 699b ldr r3, [r3, #24]
8004760: 613b str r3, [r7, #16]
8004762: 693b ldr r3, [r7, #16]
/* Generate Restart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004764: 68fb ldr r3, [r7, #12]
8004766: 681b ldr r3, [r3, #0]
8004768: 681a ldr r2, [r3, #0]
800476a: 68fb ldr r3, [r7, #12]
800476c: 681b ldr r3, [r3, #0]
800476e: f442 7280 orr.w r2, r2, #256 @ 0x100
8004772: 601a str r2, [r3, #0]
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
8004774: 683b ldr r3, [r7, #0]
8004776: 9300 str r3, [sp, #0]
8004778: 687b ldr r3, [r7, #4]
800477a: 2200 movs r2, #0
800477c: f04f 1101 mov.w r1, #65537 @ 0x10001
8004780: 68f8 ldr r0, [r7, #12]
8004782: f000 f831 bl 80047e8 <I2C_WaitOnFlagUntilTimeout>
8004786: 4603 mov r3, r0
8004788: 2b00 cmp r3, #0
800478a: d00d beq.n 80047a8 <I2C_MasterRequestRead+0x15c>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
800478c: 68fb ldr r3, [r7, #12]
800478e: 681b ldr r3, [r3, #0]
8004790: 681b ldr r3, [r3, #0]
8004792: f403 7380 and.w r3, r3, #256 @ 0x100
8004796: f5b3 7f80 cmp.w r3, #256 @ 0x100
800479a: d103 bne.n 80047a4 <I2C_MasterRequestRead+0x158>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
800479c: 68fb ldr r3, [r7, #12]
800479e: f44f 7200 mov.w r2, #512 @ 0x200
80047a2: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80047a4: 2303 movs r3, #3
80047a6: e017 b.n 80047d8 <I2C_MasterRequestRead+0x18c>
}
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
80047a8: 897b ldrh r3, [r7, #10]
80047aa: 11db asrs r3, r3, #7
80047ac: b2db uxtb r3, r3
80047ae: f003 0306 and.w r3, r3, #6
80047b2: b2db uxtb r3, r3
80047b4: f063 030e orn r3, r3, #14
80047b8: b2da uxtb r2, r3
80047ba: 68fb ldr r3, [r7, #12]
80047bc: 681b ldr r3, [r3, #0]
80047be: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
80047c0: 683b ldr r3, [r7, #0]
80047c2: 687a ldr r2, [r7, #4]
80047c4: 4907 ldr r1, [pc, #28] @ (80047e4 <I2C_MasterRequestRead+0x198>)
80047c6: 68f8 ldr r0, [r7, #12]
80047c8: f000 f888 bl 80048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>
80047cc: 4603 mov r3, r0
80047ce: 2b00 cmp r3, #0
80047d0: d001 beq.n 80047d6 <I2C_MasterRequestRead+0x18a>
{
return HAL_ERROR;
80047d2: 2301 movs r3, #1
80047d4: e000 b.n 80047d8 <I2C_MasterRequestRead+0x18c>
}
return HAL_OK;
80047d6: 2300 movs r3, #0
}
80047d8: 4618 mov r0, r3
80047da: 3718 adds r7, #24
80047dc: 46bd mov sp, r7
80047de: bd80 pop {r7, pc}
80047e0: 00010008 .word 0x00010008
80047e4: 00010002 .word 0x00010002
080047e8 <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
80047e8: b580 push {r7, lr}
80047ea: b084 sub sp, #16
80047ec: af00 add r7, sp, #0
80047ee: 60f8 str r0, [r7, #12]
80047f0: 60b9 str r1, [r7, #8]
80047f2: 603b str r3, [r7, #0]
80047f4: 4613 mov r3, r2
80047f6: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80047f8: e048 b.n 800488c <I2C_WaitOnFlagUntilTimeout+0xa4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80047fa: 683b ldr r3, [r7, #0]
80047fc: f1b3 3fff cmp.w r3, #4294967295
8004800: d044 beq.n 800488c <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004802: f7fe fc27 bl 8003054 <HAL_GetTick>
8004806: 4602 mov r2, r0
8004808: 69bb ldr r3, [r7, #24]
800480a: 1ad3 subs r3, r2, r3
800480c: 683a ldr r2, [r7, #0]
800480e: 429a cmp r2, r3
8004810: d302 bcc.n 8004818 <I2C_WaitOnFlagUntilTimeout+0x30>
8004812: 683b ldr r3, [r7, #0]
8004814: 2b00 cmp r3, #0
8004816: d139 bne.n 800488c <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
8004818: 68bb ldr r3, [r7, #8]
800481a: 0c1b lsrs r3, r3, #16
800481c: b2db uxtb r3, r3
800481e: 2b01 cmp r3, #1
8004820: d10d bne.n 800483e <I2C_WaitOnFlagUntilTimeout+0x56>
8004822: 68fb ldr r3, [r7, #12]
8004824: 681b ldr r3, [r3, #0]
8004826: 695b ldr r3, [r3, #20]
8004828: 43da mvns r2, r3
800482a: 68bb ldr r3, [r7, #8]
800482c: 4013 ands r3, r2
800482e: b29b uxth r3, r3
8004830: 2b00 cmp r3, #0
8004832: bf0c ite eq
8004834: 2301 moveq r3, #1
8004836: 2300 movne r3, #0
8004838: b2db uxtb r3, r3
800483a: 461a mov r2, r3
800483c: e00c b.n 8004858 <I2C_WaitOnFlagUntilTimeout+0x70>
800483e: 68fb ldr r3, [r7, #12]
8004840: 681b ldr r3, [r3, #0]
8004842: 699b ldr r3, [r3, #24]
8004844: 43da mvns r2, r3
8004846: 68bb ldr r3, [r7, #8]
8004848: 4013 ands r3, r2
800484a: b29b uxth r3, r3
800484c: 2b00 cmp r3, #0
800484e: bf0c ite eq
8004850: 2301 moveq r3, #1
8004852: 2300 movne r3, #0
8004854: b2db uxtb r3, r3
8004856: 461a mov r2, r3
8004858: 79fb ldrb r3, [r7, #7]
800485a: 429a cmp r2, r3
800485c: d116 bne.n 800488c <I2C_WaitOnFlagUntilTimeout+0xa4>
{
hi2c->PreviousState = I2C_STATE_NONE;
800485e: 68fb ldr r3, [r7, #12]
8004860: 2200 movs r2, #0
8004862: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004864: 68fb ldr r3, [r7, #12]
8004866: 2220 movs r2, #32
8004868: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
800486c: 68fb ldr r3, [r7, #12]
800486e: 2200 movs r2, #0
8004870: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004874: 68fb ldr r3, [r7, #12]
8004876: 6c1b ldr r3, [r3, #64] @ 0x40
8004878: f043 0220 orr.w r2, r3, #32
800487c: 68fb ldr r3, [r7, #12]
800487e: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004880: 68fb ldr r3, [r7, #12]
8004882: 2200 movs r2, #0
8004884: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004888: 2301 movs r3, #1
800488a: e023 b.n 80048d4 <I2C_WaitOnFlagUntilTimeout+0xec>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
800488c: 68bb ldr r3, [r7, #8]
800488e: 0c1b lsrs r3, r3, #16
8004890: b2db uxtb r3, r3
8004892: 2b01 cmp r3, #1
8004894: d10d bne.n 80048b2 <I2C_WaitOnFlagUntilTimeout+0xca>
8004896: 68fb ldr r3, [r7, #12]
8004898: 681b ldr r3, [r3, #0]
800489a: 695b ldr r3, [r3, #20]
800489c: 43da mvns r2, r3
800489e: 68bb ldr r3, [r7, #8]
80048a0: 4013 ands r3, r2
80048a2: b29b uxth r3, r3
80048a4: 2b00 cmp r3, #0
80048a6: bf0c ite eq
80048a8: 2301 moveq r3, #1
80048aa: 2300 movne r3, #0
80048ac: b2db uxtb r3, r3
80048ae: 461a mov r2, r3
80048b0: e00c b.n 80048cc <I2C_WaitOnFlagUntilTimeout+0xe4>
80048b2: 68fb ldr r3, [r7, #12]
80048b4: 681b ldr r3, [r3, #0]
80048b6: 699b ldr r3, [r3, #24]
80048b8: 43da mvns r2, r3
80048ba: 68bb ldr r3, [r7, #8]
80048bc: 4013 ands r3, r2
80048be: b29b uxth r3, r3
80048c0: 2b00 cmp r3, #0
80048c2: bf0c ite eq
80048c4: 2301 moveq r3, #1
80048c6: 2300 movne r3, #0
80048c8: b2db uxtb r3, r3
80048ca: 461a mov r2, r3
80048cc: 79fb ldrb r3, [r7, #7]
80048ce: 429a cmp r2, r3
80048d0: d093 beq.n 80047fa <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80048d2: 2300 movs r3, #0
}
80048d4: 4618 mov r0, r3
80048d6: 3710 adds r7, #16
80048d8: 46bd mov sp, r7
80048da: bd80 pop {r7, pc}
080048dc <I2C_WaitOnMasterAddressFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
80048dc: b580 push {r7, lr}
80048de: b084 sub sp, #16
80048e0: af00 add r7, sp, #0
80048e2: 60f8 str r0, [r7, #12]
80048e4: 60b9 str r1, [r7, #8]
80048e6: 607a str r2, [r7, #4]
80048e8: 603b str r3, [r7, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
80048ea: e071 b.n 80049d0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
80048ec: 68fb ldr r3, [r7, #12]
80048ee: 681b ldr r3, [r3, #0]
80048f0: 695b ldr r3, [r3, #20]
80048f2: f403 6380 and.w r3, r3, #1024 @ 0x400
80048f6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80048fa: d123 bne.n 8004944 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80048fc: 68fb ldr r3, [r7, #12]
80048fe: 681b ldr r3, [r3, #0]
8004900: 681a ldr r2, [r3, #0]
8004902: 68fb ldr r3, [r7, #12]
8004904: 681b ldr r3, [r3, #0]
8004906: f442 7200 orr.w r2, r2, #512 @ 0x200
800490a: 601a str r2, [r3, #0]
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800490c: 68fb ldr r3, [r7, #12]
800490e: 681b ldr r3, [r3, #0]
8004910: f46f 6280 mvn.w r2, #1024 @ 0x400
8004914: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004916: 68fb ldr r3, [r7, #12]
8004918: 2200 movs r2, #0
800491a: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
800491c: 68fb ldr r3, [r7, #12]
800491e: 2220 movs r2, #32
8004920: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004924: 68fb ldr r3, [r7, #12]
8004926: 2200 movs r2, #0
8004928: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800492c: 68fb ldr r3, [r7, #12]
800492e: 6c1b ldr r3, [r3, #64] @ 0x40
8004930: f043 0204 orr.w r2, r3, #4
8004934: 68fb ldr r3, [r7, #12]
8004936: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004938: 68fb ldr r3, [r7, #12]
800493a: 2200 movs r2, #0
800493c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004940: 2301 movs r3, #1
8004942: e067 b.n 8004a14 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004944: 687b ldr r3, [r7, #4]
8004946: f1b3 3fff cmp.w r3, #4294967295
800494a: d041 beq.n 80049d0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800494c: f7fe fb82 bl 8003054 <HAL_GetTick>
8004950: 4602 mov r2, r0
8004952: 683b ldr r3, [r7, #0]
8004954: 1ad3 subs r3, r2, r3
8004956: 687a ldr r2, [r7, #4]
8004958: 429a cmp r2, r3
800495a: d302 bcc.n 8004962 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
800495c: 687b ldr r3, [r7, #4]
800495e: 2b00 cmp r3, #0
8004960: d136 bne.n 80049d0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
8004962: 68bb ldr r3, [r7, #8]
8004964: 0c1b lsrs r3, r3, #16
8004966: b2db uxtb r3, r3
8004968: 2b01 cmp r3, #1
800496a: d10c bne.n 8004986 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
800496c: 68fb ldr r3, [r7, #12]
800496e: 681b ldr r3, [r3, #0]
8004970: 695b ldr r3, [r3, #20]
8004972: 43da mvns r2, r3
8004974: 68bb ldr r3, [r7, #8]
8004976: 4013 ands r3, r2
8004978: b29b uxth r3, r3
800497a: 2b00 cmp r3, #0
800497c: bf14 ite ne
800497e: 2301 movne r3, #1
8004980: 2300 moveq r3, #0
8004982: b2db uxtb r3, r3
8004984: e00b b.n 800499e <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
8004986: 68fb ldr r3, [r7, #12]
8004988: 681b ldr r3, [r3, #0]
800498a: 699b ldr r3, [r3, #24]
800498c: 43da mvns r2, r3
800498e: 68bb ldr r3, [r7, #8]
8004990: 4013 ands r3, r2
8004992: b29b uxth r3, r3
8004994: 2b00 cmp r3, #0
8004996: bf14 ite ne
8004998: 2301 movne r3, #1
800499a: 2300 moveq r3, #0
800499c: b2db uxtb r3, r3
800499e: 2b00 cmp r3, #0
80049a0: d016 beq.n 80049d0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
hi2c->PreviousState = I2C_STATE_NONE;
80049a2: 68fb ldr r3, [r7, #12]
80049a4: 2200 movs r2, #0
80049a6: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80049a8: 68fb ldr r3, [r7, #12]
80049aa: 2220 movs r2, #32
80049ac: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80049b0: 68fb ldr r3, [r7, #12]
80049b2: 2200 movs r2, #0
80049b4: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80049b8: 68fb ldr r3, [r7, #12]
80049ba: 6c1b ldr r3, [r3, #64] @ 0x40
80049bc: f043 0220 orr.w r2, r3, #32
80049c0: 68fb ldr r3, [r7, #12]
80049c2: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80049c4: 68fb ldr r3, [r7, #12]
80049c6: 2200 movs r2, #0
80049c8: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80049cc: 2301 movs r3, #1
80049ce: e021 b.n 8004a14 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
80049d0: 68bb ldr r3, [r7, #8]
80049d2: 0c1b lsrs r3, r3, #16
80049d4: b2db uxtb r3, r3
80049d6: 2b01 cmp r3, #1
80049d8: d10c bne.n 80049f4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
80049da: 68fb ldr r3, [r7, #12]
80049dc: 681b ldr r3, [r3, #0]
80049de: 695b ldr r3, [r3, #20]
80049e0: 43da mvns r2, r3
80049e2: 68bb ldr r3, [r7, #8]
80049e4: 4013 ands r3, r2
80049e6: b29b uxth r3, r3
80049e8: 2b00 cmp r3, #0
80049ea: bf14 ite ne
80049ec: 2301 movne r3, #1
80049ee: 2300 moveq r3, #0
80049f0: b2db uxtb r3, r3
80049f2: e00b b.n 8004a0c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
80049f4: 68fb ldr r3, [r7, #12]
80049f6: 681b ldr r3, [r3, #0]
80049f8: 699b ldr r3, [r3, #24]
80049fa: 43da mvns r2, r3
80049fc: 68bb ldr r3, [r7, #8]
80049fe: 4013 ands r3, r2
8004a00: b29b uxth r3, r3
8004a02: 2b00 cmp r3, #0
8004a04: bf14 ite ne
8004a06: 2301 movne r3, #1
8004a08: 2300 moveq r3, #0
8004a0a: b2db uxtb r3, r3
8004a0c: 2b00 cmp r3, #0
8004a0e: f47f af6d bne.w 80048ec <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
}
}
}
}
return HAL_OK;
8004a12: 2300 movs r3, #0
}
8004a14: 4618 mov r0, r3
8004a16: 3710 adds r7, #16
8004a18: 46bd mov sp, r7
8004a1a: bd80 pop {r7, pc}
08004a1c <I2C_WaitOnTXEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004a1c: b580 push {r7, lr}
8004a1e: b084 sub sp, #16
8004a20: af00 add r7, sp, #0
8004a22: 60f8 str r0, [r7, #12]
8004a24: 60b9 str r1, [r7, #8]
8004a26: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004a28: e034 b.n 8004a94 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004a2a: 68f8 ldr r0, [r7, #12]
8004a2c: f000 f8e3 bl 8004bf6 <I2C_IsAcknowledgeFailed>
8004a30: 4603 mov r3, r0
8004a32: 2b00 cmp r3, #0
8004a34: d001 beq.n 8004a3a <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004a36: 2301 movs r3, #1
8004a38: e034 b.n 8004aa4 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004a3a: 68bb ldr r3, [r7, #8]
8004a3c: f1b3 3fff cmp.w r3, #4294967295
8004a40: d028 beq.n 8004a94 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004a42: f7fe fb07 bl 8003054 <HAL_GetTick>
8004a46: 4602 mov r2, r0
8004a48: 687b ldr r3, [r7, #4]
8004a4a: 1ad3 subs r3, r2, r3
8004a4c: 68ba ldr r2, [r7, #8]
8004a4e: 429a cmp r2, r3
8004a50: d302 bcc.n 8004a58 <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
8004a52: 68bb ldr r3, [r7, #8]
8004a54: 2b00 cmp r3, #0
8004a56: d11d bne.n 8004a94 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
8004a58: 68fb ldr r3, [r7, #12]
8004a5a: 681b ldr r3, [r3, #0]
8004a5c: 695b ldr r3, [r3, #20]
8004a5e: f003 0380 and.w r3, r3, #128 @ 0x80
8004a62: 2b80 cmp r3, #128 @ 0x80
8004a64: d016 beq.n 8004a94 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004a66: 68fb ldr r3, [r7, #12]
8004a68: 2200 movs r2, #0
8004a6a: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004a6c: 68fb ldr r3, [r7, #12]
8004a6e: 2220 movs r2, #32
8004a70: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004a74: 68fb ldr r3, [r7, #12]
8004a76: 2200 movs r2, #0
8004a78: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004a7c: 68fb ldr r3, [r7, #12]
8004a7e: 6c1b ldr r3, [r3, #64] @ 0x40
8004a80: f043 0220 orr.w r2, r3, #32
8004a84: 68fb ldr r3, [r7, #12]
8004a86: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004a88: 68fb ldr r3, [r7, #12]
8004a8a: 2200 movs r2, #0
8004a8c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004a90: 2301 movs r3, #1
8004a92: e007 b.n 8004aa4 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004a94: 68fb ldr r3, [r7, #12]
8004a96: 681b ldr r3, [r3, #0]
8004a98: 695b ldr r3, [r3, #20]
8004a9a: f003 0380 and.w r3, r3, #128 @ 0x80
8004a9e: 2b80 cmp r3, #128 @ 0x80
8004aa0: d1c3 bne.n 8004a2a <I2C_WaitOnTXEFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004aa2: 2300 movs r3, #0
}
8004aa4: 4618 mov r0, r3
8004aa6: 3710 adds r7, #16
8004aa8: 46bd mov sp, r7
8004aaa: bd80 pop {r7, pc}
08004aac <I2C_WaitOnBTFFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004aac: b580 push {r7, lr}
8004aae: b084 sub sp, #16
8004ab0: af00 add r7, sp, #0
8004ab2: 60f8 str r0, [r7, #12]
8004ab4: 60b9 str r1, [r7, #8]
8004ab6: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004ab8: e034 b.n 8004b24 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004aba: 68f8 ldr r0, [r7, #12]
8004abc: f000 f89b bl 8004bf6 <I2C_IsAcknowledgeFailed>
8004ac0: 4603 mov r3, r0
8004ac2: 2b00 cmp r3, #0
8004ac4: d001 beq.n 8004aca <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004ac6: 2301 movs r3, #1
8004ac8: e034 b.n 8004b34 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004aca: 68bb ldr r3, [r7, #8]
8004acc: f1b3 3fff cmp.w r3, #4294967295
8004ad0: d028 beq.n 8004b24 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004ad2: f7fe fabf bl 8003054 <HAL_GetTick>
8004ad6: 4602 mov r2, r0
8004ad8: 687b ldr r3, [r7, #4]
8004ada: 1ad3 subs r3, r2, r3
8004adc: 68ba ldr r2, [r7, #8]
8004ade: 429a cmp r2, r3
8004ae0: d302 bcc.n 8004ae8 <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
8004ae2: 68bb ldr r3, [r7, #8]
8004ae4: 2b00 cmp r3, #0
8004ae6: d11d bne.n 8004b24 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
8004ae8: 68fb ldr r3, [r7, #12]
8004aea: 681b ldr r3, [r3, #0]
8004aec: 695b ldr r3, [r3, #20]
8004aee: f003 0304 and.w r3, r3, #4
8004af2: 2b04 cmp r3, #4
8004af4: d016 beq.n 8004b24 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004af6: 68fb ldr r3, [r7, #12]
8004af8: 2200 movs r2, #0
8004afa: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004afc: 68fb ldr r3, [r7, #12]
8004afe: 2220 movs r2, #32
8004b00: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004b04: 68fb ldr r3, [r7, #12]
8004b06: 2200 movs r2, #0
8004b08: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004b0c: 68fb ldr r3, [r7, #12]
8004b0e: 6c1b ldr r3, [r3, #64] @ 0x40
8004b10: f043 0220 orr.w r2, r3, #32
8004b14: 68fb ldr r3, [r7, #12]
8004b16: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004b18: 68fb ldr r3, [r7, #12]
8004b1a: 2200 movs r2, #0
8004b1c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004b20: 2301 movs r3, #1
8004b22: e007 b.n 8004b34 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004b24: 68fb ldr r3, [r7, #12]
8004b26: 681b ldr r3, [r3, #0]
8004b28: 695b ldr r3, [r3, #20]
8004b2a: f003 0304 and.w r3, r3, #4
8004b2e: 2b04 cmp r3, #4
8004b30: d1c3 bne.n 8004aba <I2C_WaitOnBTFFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004b32: 2300 movs r3, #0
}
8004b34: 4618 mov r0, r3
8004b36: 3710 adds r7, #16
8004b38: 46bd mov sp, r7
8004b3a: bd80 pop {r7, pc}
08004b3c <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004b3c: b580 push {r7, lr}
8004b3e: b084 sub sp, #16
8004b40: af00 add r7, sp, #0
8004b42: 60f8 str r0, [r7, #12]
8004b44: 60b9 str r1, [r7, #8]
8004b46: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004b48: e049 b.n 8004bde <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
8004b4a: 68fb ldr r3, [r7, #12]
8004b4c: 681b ldr r3, [r3, #0]
8004b4e: 695b ldr r3, [r3, #20]
8004b50: f003 0310 and.w r3, r3, #16
8004b54: 2b10 cmp r3, #16
8004b56: d119 bne.n 8004b8c <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8004b58: 68fb ldr r3, [r7, #12]
8004b5a: 681b ldr r3, [r3, #0]
8004b5c: f06f 0210 mvn.w r2, #16
8004b60: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004b62: 68fb ldr r3, [r7, #12]
8004b64: 2200 movs r2, #0
8004b66: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004b68: 68fb ldr r3, [r7, #12]
8004b6a: 2220 movs r2, #32
8004b6c: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004b70: 68fb ldr r3, [r7, #12]
8004b72: 2200 movs r2, #0
8004b74: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
8004b78: 68fb ldr r3, [r7, #12]
8004b7a: 6c1a ldr r2, [r3, #64] @ 0x40
8004b7c: 68fb ldr r3, [r7, #12]
8004b7e: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 2200 movs r2, #0
8004b84: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004b88: 2301 movs r3, #1
8004b8a: e030 b.n 8004bee <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004b8c: f7fe fa62 bl 8003054 <HAL_GetTick>
8004b90: 4602 mov r2, r0
8004b92: 687b ldr r3, [r7, #4]
8004b94: 1ad3 subs r3, r2, r3
8004b96: 68ba ldr r2, [r7, #8]
8004b98: 429a cmp r2, r3
8004b9a: d302 bcc.n 8004ba2 <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
8004b9c: 68bb ldr r3, [r7, #8]
8004b9e: 2b00 cmp r3, #0
8004ba0: d11d bne.n 8004bde <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
8004ba2: 68fb ldr r3, [r7, #12]
8004ba4: 681b ldr r3, [r3, #0]
8004ba6: 695b ldr r3, [r3, #20]
8004ba8: f003 0340 and.w r3, r3, #64 @ 0x40
8004bac: 2b40 cmp r3, #64 @ 0x40
8004bae: d016 beq.n 8004bde <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004bb0: 68fb ldr r3, [r7, #12]
8004bb2: 2200 movs r2, #0
8004bb4: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004bb6: 68fb ldr r3, [r7, #12]
8004bb8: 2220 movs r2, #32
8004bba: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004bbe: 68fb ldr r3, [r7, #12]
8004bc0: 2200 movs r2, #0
8004bc2: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004bc6: 68fb ldr r3, [r7, #12]
8004bc8: 6c1b ldr r3, [r3, #64] @ 0x40
8004bca: f043 0220 orr.w r2, r3, #32
8004bce: 68fb ldr r3, [r7, #12]
8004bd0: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004bd2: 68fb ldr r3, [r7, #12]
8004bd4: 2200 movs r2, #0
8004bd6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004bda: 2301 movs r3, #1
8004bdc: e007 b.n 8004bee <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004bde: 68fb ldr r3, [r7, #12]
8004be0: 681b ldr r3, [r3, #0]
8004be2: 695b ldr r3, [r3, #20]
8004be4: f003 0340 and.w r3, r3, #64 @ 0x40
8004be8: 2b40 cmp r3, #64 @ 0x40
8004bea: d1ae bne.n 8004b4a <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8004bec: 2300 movs r3, #0
}
8004bee: 4618 mov r0, r3
8004bf0: 3710 adds r7, #16
8004bf2: 46bd mov sp, r7
8004bf4: bd80 pop {r7, pc}
08004bf6 <I2C_IsAcknowledgeFailed>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
8004bf6: b480 push {r7}
8004bf8: b083 sub sp, #12
8004bfa: af00 add r7, sp, #0
8004bfc: 6078 str r0, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004bfe: 687b ldr r3, [r7, #4]
8004c00: 681b ldr r3, [r3, #0]
8004c02: 695b ldr r3, [r3, #20]
8004c04: f403 6380 and.w r3, r3, #1024 @ 0x400
8004c08: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004c0c: d11b bne.n 8004c46 <I2C_IsAcknowledgeFailed+0x50>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004c0e: 687b ldr r3, [r7, #4]
8004c10: 681b ldr r3, [r3, #0]
8004c12: f46f 6280 mvn.w r2, #1024 @ 0x400
8004c16: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004c18: 687b ldr r3, [r7, #4]
8004c1a: 2200 movs r2, #0
8004c1c: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004c1e: 687b ldr r3, [r7, #4]
8004c20: 2220 movs r2, #32
8004c22: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004c26: 687b ldr r3, [r7, #4]
8004c28: 2200 movs r2, #0
8004c2a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004c2e: 687b ldr r3, [r7, #4]
8004c30: 6c1b ldr r3, [r3, #64] @ 0x40
8004c32: f043 0204 orr.w r2, r3, #4
8004c36: 687b ldr r3, [r7, #4]
8004c38: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004c3a: 687b ldr r3, [r7, #4]
8004c3c: 2200 movs r2, #0
8004c3e: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004c42: 2301 movs r3, #1
8004c44: e000 b.n 8004c48 <I2C_IsAcknowledgeFailed+0x52>
}
return HAL_OK;
8004c46: 2300 movs r3, #0
}
8004c48: 4618 mov r0, r3
8004c4a: 370c adds r7, #12
8004c4c: 46bd mov sp, r7
8004c4e: bc80 pop {r7}
8004c50: 4770 bx lr
...
08004c54 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004c54: b580 push {r7, lr}
8004c56: b086 sub sp, #24
8004c58: af00 add r7, sp, #0
8004c5a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004c5c: 687b ldr r3, [r7, #4]
8004c5e: 2b00 cmp r3, #0
8004c60: d101 bne.n 8004c66 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8004c62: 2301 movs r3, #1
8004c64: e272 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8004c66: 687b ldr r3, [r7, #4]
8004c68: 681b ldr r3, [r3, #0]
8004c6a: f003 0301 and.w r3, r3, #1
8004c6e: 2b00 cmp r3, #0
8004c70: f000 8087 beq.w 8004d82 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8004c74: 4b92 ldr r3, [pc, #584] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004c76: 685b ldr r3, [r3, #4]
8004c78: f003 030c and.w r3, r3, #12
8004c7c: 2b04 cmp r3, #4
8004c7e: d00c beq.n 8004c9a <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8004c80: 4b8f ldr r3, [pc, #572] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004c82: 685b ldr r3, [r3, #4]
8004c84: f003 030c and.w r3, r3, #12
8004c88: 2b08 cmp r3, #8
8004c8a: d112 bne.n 8004cb2 <HAL_RCC_OscConfig+0x5e>
8004c8c: 4b8c ldr r3, [pc, #560] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004c8e: 685b ldr r3, [r3, #4]
8004c90: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004c94: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004c98: d10b bne.n 8004cb2 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004c9a: 4b89 ldr r3, [pc, #548] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004c9c: 681b ldr r3, [r3, #0]
8004c9e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004ca2: 2b00 cmp r3, #0
8004ca4: d06c beq.n 8004d80 <HAL_RCC_OscConfig+0x12c>
8004ca6: 687b ldr r3, [r7, #4]
8004ca8: 685b ldr r3, [r3, #4]
8004caa: 2b00 cmp r3, #0
8004cac: d168 bne.n 8004d80 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8004cae: 2301 movs r3, #1
8004cb0: e24c b.n 800514c <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8004cb2: 687b ldr r3, [r7, #4]
8004cb4: 685b ldr r3, [r3, #4]
8004cb6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004cba: d106 bne.n 8004cca <HAL_RCC_OscConfig+0x76>
8004cbc: 4b80 ldr r3, [pc, #512] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cbe: 681b ldr r3, [r3, #0]
8004cc0: 4a7f ldr r2, [pc, #508] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cc2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004cc6: 6013 str r3, [r2, #0]
8004cc8: e02e b.n 8004d28 <HAL_RCC_OscConfig+0xd4>
8004cca: 687b ldr r3, [r7, #4]
8004ccc: 685b ldr r3, [r3, #4]
8004cce: 2b00 cmp r3, #0
8004cd0: d10c bne.n 8004cec <HAL_RCC_OscConfig+0x98>
8004cd2: 4b7b ldr r3, [pc, #492] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cd4: 681b ldr r3, [r3, #0]
8004cd6: 4a7a ldr r2, [pc, #488] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cd8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004cdc: 6013 str r3, [r2, #0]
8004cde: 4b78 ldr r3, [pc, #480] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004ce0: 681b ldr r3, [r3, #0]
8004ce2: 4a77 ldr r2, [pc, #476] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004ce4: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004ce8: 6013 str r3, [r2, #0]
8004cea: e01d b.n 8004d28 <HAL_RCC_OscConfig+0xd4>
8004cec: 687b ldr r3, [r7, #4]
8004cee: 685b ldr r3, [r3, #4]
8004cf0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004cf4: d10c bne.n 8004d10 <HAL_RCC_OscConfig+0xbc>
8004cf6: 4b72 ldr r3, [pc, #456] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cf8: 681b ldr r3, [r3, #0]
8004cfa: 4a71 ldr r2, [pc, #452] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004cfc: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8004d00: 6013 str r3, [r2, #0]
8004d02: 4b6f ldr r3, [pc, #444] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d04: 681b ldr r3, [r3, #0]
8004d06: 4a6e ldr r2, [pc, #440] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d08: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004d0c: 6013 str r3, [r2, #0]
8004d0e: e00b b.n 8004d28 <HAL_RCC_OscConfig+0xd4>
8004d10: 4b6b ldr r3, [pc, #428] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d12: 681b ldr r3, [r3, #0]
8004d14: 4a6a ldr r2, [pc, #424] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d16: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004d1a: 6013 str r3, [r2, #0]
8004d1c: 4b68 ldr r3, [pc, #416] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d1e: 681b ldr r3, [r3, #0]
8004d20: 4a67 ldr r2, [pc, #412] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d22: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004d26: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8004d28: 687b ldr r3, [r7, #4]
8004d2a: 685b ldr r3, [r3, #4]
8004d2c: 2b00 cmp r3, #0
8004d2e: d013 beq.n 8004d58 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004d30: f7fe f990 bl 8003054 <HAL_GetTick>
8004d34: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004d36: e008 b.n 8004d4a <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004d38: f7fe f98c bl 8003054 <HAL_GetTick>
8004d3c: 4602 mov r2, r0
8004d3e: 693b ldr r3, [r7, #16]
8004d40: 1ad3 subs r3, r2, r3
8004d42: 2b64 cmp r3, #100 @ 0x64
8004d44: d901 bls.n 8004d4a <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8004d46: 2303 movs r3, #3
8004d48: e200 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004d4a: 4b5d ldr r3, [pc, #372] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d4c: 681b ldr r3, [r3, #0]
8004d4e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004d52: 2b00 cmp r3, #0
8004d54: d0f0 beq.n 8004d38 <HAL_RCC_OscConfig+0xe4>
8004d56: e014 b.n 8004d82 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004d58: f7fe f97c bl 8003054 <HAL_GetTick>
8004d5c: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004d5e: e008 b.n 8004d72 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004d60: f7fe f978 bl 8003054 <HAL_GetTick>
8004d64: 4602 mov r2, r0
8004d66: 693b ldr r3, [r7, #16]
8004d68: 1ad3 subs r3, r2, r3
8004d6a: 2b64 cmp r3, #100 @ 0x64
8004d6c: d901 bls.n 8004d72 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8004d6e: 2303 movs r3, #3
8004d70: e1ec b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004d72: 4b53 ldr r3, [pc, #332] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d74: 681b ldr r3, [r3, #0]
8004d76: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004d7a: 2b00 cmp r3, #0
8004d7c: d1f0 bne.n 8004d60 <HAL_RCC_OscConfig+0x10c>
8004d7e: e000 b.n 8004d82 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004d80: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8004d82: 687b ldr r3, [r7, #4]
8004d84: 681b ldr r3, [r3, #0]
8004d86: f003 0302 and.w r3, r3, #2
8004d8a: 2b00 cmp r3, #0
8004d8c: d063 beq.n 8004e56 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8004d8e: 4b4c ldr r3, [pc, #304] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d90: 685b ldr r3, [r3, #4]
8004d92: f003 030c and.w r3, r3, #12
8004d96: 2b00 cmp r3, #0
8004d98: d00b beq.n 8004db2 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8004d9a: 4b49 ldr r3, [pc, #292] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004d9c: 685b ldr r3, [r3, #4]
8004d9e: f003 030c and.w r3, r3, #12
8004da2: 2b08 cmp r3, #8
8004da4: d11c bne.n 8004de0 <HAL_RCC_OscConfig+0x18c>
8004da6: 4b46 ldr r3, [pc, #280] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004da8: 685b ldr r3, [r3, #4]
8004daa: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004dae: 2b00 cmp r3, #0
8004db0: d116 bne.n 8004de0 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8004db2: 4b43 ldr r3, [pc, #268] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004db4: 681b ldr r3, [r3, #0]
8004db6: f003 0302 and.w r3, r3, #2
8004dba: 2b00 cmp r3, #0
8004dbc: d005 beq.n 8004dca <HAL_RCC_OscConfig+0x176>
8004dbe: 687b ldr r3, [r7, #4]
8004dc0: 691b ldr r3, [r3, #16]
8004dc2: 2b01 cmp r3, #1
8004dc4: d001 beq.n 8004dca <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8004dc6: 2301 movs r3, #1
8004dc8: e1c0 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004dca: 4b3d ldr r3, [pc, #244] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004dcc: 681b ldr r3, [r3, #0]
8004dce: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8004dd2: 687b ldr r3, [r7, #4]
8004dd4: 695b ldr r3, [r3, #20]
8004dd6: 00db lsls r3, r3, #3
8004dd8: 4939 ldr r1, [pc, #228] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004dda: 4313 orrs r3, r2
8004ddc: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8004dde: e03a b.n 8004e56 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8004de0: 687b ldr r3, [r7, #4]
8004de2: 691b ldr r3, [r3, #16]
8004de4: 2b00 cmp r3, #0
8004de6: d020 beq.n 8004e2a <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8004de8: 4b36 ldr r3, [pc, #216] @ (8004ec4 <HAL_RCC_OscConfig+0x270>)
8004dea: 2201 movs r2, #1
8004dec: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004dee: f7fe f931 bl 8003054 <HAL_GetTick>
8004df2: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004df4: e008 b.n 8004e08 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004df6: f7fe f92d bl 8003054 <HAL_GetTick>
8004dfa: 4602 mov r2, r0
8004dfc: 693b ldr r3, [r7, #16]
8004dfe: 1ad3 subs r3, r2, r3
8004e00: 2b02 cmp r3, #2
8004e02: d901 bls.n 8004e08 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8004e04: 2303 movs r3, #3
8004e06: e1a1 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004e08: 4b2d ldr r3, [pc, #180] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004e0a: 681b ldr r3, [r3, #0]
8004e0c: f003 0302 and.w r3, r3, #2
8004e10: 2b00 cmp r3, #0
8004e12: d0f0 beq.n 8004df6 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004e14: 4b2a ldr r3, [pc, #168] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004e16: 681b ldr r3, [r3, #0]
8004e18: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8004e1c: 687b ldr r3, [r7, #4]
8004e1e: 695b ldr r3, [r3, #20]
8004e20: 00db lsls r3, r3, #3
8004e22: 4927 ldr r1, [pc, #156] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004e24: 4313 orrs r3, r2
8004e26: 600b str r3, [r1, #0]
8004e28: e015 b.n 8004e56 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8004e2a: 4b26 ldr r3, [pc, #152] @ (8004ec4 <HAL_RCC_OscConfig+0x270>)
8004e2c: 2200 movs r2, #0
8004e2e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004e30: f7fe f910 bl 8003054 <HAL_GetTick>
8004e34: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8004e36: e008 b.n 8004e4a <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004e38: f7fe f90c bl 8003054 <HAL_GetTick>
8004e3c: 4602 mov r2, r0
8004e3e: 693b ldr r3, [r7, #16]
8004e40: 1ad3 subs r3, r2, r3
8004e42: 2b02 cmp r3, #2
8004e44: d901 bls.n 8004e4a <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8004e46: 2303 movs r3, #3
8004e48: e180 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8004e4a: 4b1d ldr r3, [pc, #116] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004e4c: 681b ldr r3, [r3, #0]
8004e4e: f003 0302 and.w r3, r3, #2
8004e52: 2b00 cmp r3, #0
8004e54: d1f0 bne.n 8004e38 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8004e56: 687b ldr r3, [r7, #4]
8004e58: 681b ldr r3, [r3, #0]
8004e5a: f003 0308 and.w r3, r3, #8
8004e5e: 2b00 cmp r3, #0
8004e60: d03a beq.n 8004ed8 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8004e62: 687b ldr r3, [r7, #4]
8004e64: 699b ldr r3, [r3, #24]
8004e66: 2b00 cmp r3, #0
8004e68: d019 beq.n 8004e9e <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8004e6a: 4b17 ldr r3, [pc, #92] @ (8004ec8 <HAL_RCC_OscConfig+0x274>)
8004e6c: 2201 movs r2, #1
8004e6e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004e70: f7fe f8f0 bl 8003054 <HAL_GetTick>
8004e74: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8004e76: e008 b.n 8004e8a <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8004e78: f7fe f8ec bl 8003054 <HAL_GetTick>
8004e7c: 4602 mov r2, r0
8004e7e: 693b ldr r3, [r7, #16]
8004e80: 1ad3 subs r3, r2, r3
8004e82: 2b02 cmp r3, #2
8004e84: d901 bls.n 8004e8a <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8004e86: 2303 movs r3, #3
8004e88: e160 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8004e8a: 4b0d ldr r3, [pc, #52] @ (8004ec0 <HAL_RCC_OscConfig+0x26c>)
8004e8c: 6a5b ldr r3, [r3, #36] @ 0x24
8004e8e: f003 0302 and.w r3, r3, #2
8004e92: 2b00 cmp r3, #0
8004e94: d0f0 beq.n 8004e78 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8004e96: 2001 movs r0, #1
8004e98: f000 fad0 bl 800543c <RCC_Delay>
8004e9c: e01c b.n 8004ed8 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8004e9e: 4b0a ldr r3, [pc, #40] @ (8004ec8 <HAL_RCC_OscConfig+0x274>)
8004ea0: 2200 movs r2, #0
8004ea2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004ea4: f7fe f8d6 bl 8003054 <HAL_GetTick>
8004ea8: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8004eaa: e00f b.n 8004ecc <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8004eac: f7fe f8d2 bl 8003054 <HAL_GetTick>
8004eb0: 4602 mov r2, r0
8004eb2: 693b ldr r3, [r7, #16]
8004eb4: 1ad3 subs r3, r2, r3
8004eb6: 2b02 cmp r3, #2
8004eb8: d908 bls.n 8004ecc <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8004eba: 2303 movs r3, #3
8004ebc: e146 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
8004ebe: bf00 nop
8004ec0: 40021000 .word 0x40021000
8004ec4: 42420000 .word 0x42420000
8004ec8: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8004ecc: 4b92 ldr r3, [pc, #584] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004ece: 6a5b ldr r3, [r3, #36] @ 0x24
8004ed0: f003 0302 and.w r3, r3, #2
8004ed4: 2b00 cmp r3, #0
8004ed6: d1e9 bne.n 8004eac <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8004ed8: 687b ldr r3, [r7, #4]
8004eda: 681b ldr r3, [r3, #0]
8004edc: f003 0304 and.w r3, r3, #4
8004ee0: 2b00 cmp r3, #0
8004ee2: f000 80a6 beq.w 8005032 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8004ee6: 2300 movs r3, #0
8004ee8: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8004eea: 4b8b ldr r3, [pc, #556] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004eec: 69db ldr r3, [r3, #28]
8004eee: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004ef2: 2b00 cmp r3, #0
8004ef4: d10d bne.n 8004f12 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004ef6: 4b88 ldr r3, [pc, #544] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004ef8: 69db ldr r3, [r3, #28]
8004efa: 4a87 ldr r2, [pc, #540] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004efc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004f00: 61d3 str r3, [r2, #28]
8004f02: 4b85 ldr r3, [pc, #532] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f04: 69db ldr r3, [r3, #28]
8004f06: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004f0a: 60bb str r3, [r7, #8]
8004f0c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004f0e: 2301 movs r3, #1
8004f10: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f12: 4b82 ldr r3, [pc, #520] @ (800511c <HAL_RCC_OscConfig+0x4c8>)
8004f14: 681b ldr r3, [r3, #0]
8004f16: f403 7380 and.w r3, r3, #256 @ 0x100
8004f1a: 2b00 cmp r3, #0
8004f1c: d118 bne.n 8004f50 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8004f1e: 4b7f ldr r3, [pc, #508] @ (800511c <HAL_RCC_OscConfig+0x4c8>)
8004f20: 681b ldr r3, [r3, #0]
8004f22: 4a7e ldr r2, [pc, #504] @ (800511c <HAL_RCC_OscConfig+0x4c8>)
8004f24: f443 7380 orr.w r3, r3, #256 @ 0x100
8004f28: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004f2a: f7fe f893 bl 8003054 <HAL_GetTick>
8004f2e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f30: e008 b.n 8004f44 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004f32: f7fe f88f bl 8003054 <HAL_GetTick>
8004f36: 4602 mov r2, r0
8004f38: 693b ldr r3, [r7, #16]
8004f3a: 1ad3 subs r3, r2, r3
8004f3c: 2b64 cmp r3, #100 @ 0x64
8004f3e: d901 bls.n 8004f44 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8004f40: 2303 movs r3, #3
8004f42: e103 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f44: 4b75 ldr r3, [pc, #468] @ (800511c <HAL_RCC_OscConfig+0x4c8>)
8004f46: 681b ldr r3, [r3, #0]
8004f48: f403 7380 and.w r3, r3, #256 @ 0x100
8004f4c: 2b00 cmp r3, #0
8004f4e: d0f0 beq.n 8004f32 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8004f50: 687b ldr r3, [r7, #4]
8004f52: 68db ldr r3, [r3, #12]
8004f54: 2b01 cmp r3, #1
8004f56: d106 bne.n 8004f66 <HAL_RCC_OscConfig+0x312>
8004f58: 4b6f ldr r3, [pc, #444] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f5a: 6a1b ldr r3, [r3, #32]
8004f5c: 4a6e ldr r2, [pc, #440] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f5e: f043 0301 orr.w r3, r3, #1
8004f62: 6213 str r3, [r2, #32]
8004f64: e02d b.n 8004fc2 <HAL_RCC_OscConfig+0x36e>
8004f66: 687b ldr r3, [r7, #4]
8004f68: 68db ldr r3, [r3, #12]
8004f6a: 2b00 cmp r3, #0
8004f6c: d10c bne.n 8004f88 <HAL_RCC_OscConfig+0x334>
8004f6e: 4b6a ldr r3, [pc, #424] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f70: 6a1b ldr r3, [r3, #32]
8004f72: 4a69 ldr r2, [pc, #420] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f74: f023 0301 bic.w r3, r3, #1
8004f78: 6213 str r3, [r2, #32]
8004f7a: 4b67 ldr r3, [pc, #412] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f7c: 6a1b ldr r3, [r3, #32]
8004f7e: 4a66 ldr r2, [pc, #408] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f80: f023 0304 bic.w r3, r3, #4
8004f84: 6213 str r3, [r2, #32]
8004f86: e01c b.n 8004fc2 <HAL_RCC_OscConfig+0x36e>
8004f88: 687b ldr r3, [r7, #4]
8004f8a: 68db ldr r3, [r3, #12]
8004f8c: 2b05 cmp r3, #5
8004f8e: d10c bne.n 8004faa <HAL_RCC_OscConfig+0x356>
8004f90: 4b61 ldr r3, [pc, #388] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f92: 6a1b ldr r3, [r3, #32]
8004f94: 4a60 ldr r2, [pc, #384] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f96: f043 0304 orr.w r3, r3, #4
8004f9a: 6213 str r3, [r2, #32]
8004f9c: 4b5e ldr r3, [pc, #376] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004f9e: 6a1b ldr r3, [r3, #32]
8004fa0: 4a5d ldr r2, [pc, #372] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fa2: f043 0301 orr.w r3, r3, #1
8004fa6: 6213 str r3, [r2, #32]
8004fa8: e00b b.n 8004fc2 <HAL_RCC_OscConfig+0x36e>
8004faa: 4b5b ldr r3, [pc, #364] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fac: 6a1b ldr r3, [r3, #32]
8004fae: 4a5a ldr r2, [pc, #360] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fb0: f023 0301 bic.w r3, r3, #1
8004fb4: 6213 str r3, [r2, #32]
8004fb6: 4b58 ldr r3, [pc, #352] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fb8: 6a1b ldr r3, [r3, #32]
8004fba: 4a57 ldr r2, [pc, #348] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fbc: f023 0304 bic.w r3, r3, #4
8004fc0: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8004fc2: 687b ldr r3, [r7, #4]
8004fc4: 68db ldr r3, [r3, #12]
8004fc6: 2b00 cmp r3, #0
8004fc8: d015 beq.n 8004ff6 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004fca: f7fe f843 bl 8003054 <HAL_GetTick>
8004fce: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004fd0: e00a b.n 8004fe8 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004fd2: f7fe f83f bl 8003054 <HAL_GetTick>
8004fd6: 4602 mov r2, r0
8004fd8: 693b ldr r3, [r7, #16]
8004fda: 1ad3 subs r3, r2, r3
8004fdc: f241 3288 movw r2, #5000 @ 0x1388
8004fe0: 4293 cmp r3, r2
8004fe2: d901 bls.n 8004fe8 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8004fe4: 2303 movs r3, #3
8004fe6: e0b1 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004fe8: 4b4b ldr r3, [pc, #300] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8004fea: 6a1b ldr r3, [r3, #32]
8004fec: f003 0302 and.w r3, r3, #2
8004ff0: 2b00 cmp r3, #0
8004ff2: d0ee beq.n 8004fd2 <HAL_RCC_OscConfig+0x37e>
8004ff4: e014 b.n 8005020 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004ff6: f7fe f82d bl 8003054 <HAL_GetTick>
8004ffa: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004ffc: e00a b.n 8005014 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004ffe: f7fe f829 bl 8003054 <HAL_GetTick>
8005002: 4602 mov r2, r0
8005004: 693b ldr r3, [r7, #16]
8005006: 1ad3 subs r3, r2, r3
8005008: f241 3288 movw r2, #5000 @ 0x1388
800500c: 4293 cmp r3, r2
800500e: d901 bls.n 8005014 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8005010: 2303 movs r3, #3
8005012: e09b b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8005014: 4b40 ldr r3, [pc, #256] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005016: 6a1b ldr r3, [r3, #32]
8005018: f003 0302 and.w r3, r3, #2
800501c: 2b00 cmp r3, #0
800501e: d1ee bne.n 8004ffe <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005020: 7dfb ldrb r3, [r7, #23]
8005022: 2b01 cmp r3, #1
8005024: d105 bne.n 8005032 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005026: 4b3c ldr r3, [pc, #240] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005028: 69db ldr r3, [r3, #28]
800502a: 4a3b ldr r2, [pc, #236] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
800502c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005030: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8005032: 687b ldr r3, [r7, #4]
8005034: 69db ldr r3, [r3, #28]
8005036: 2b00 cmp r3, #0
8005038: f000 8087 beq.w 800514a <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800503c: 4b36 ldr r3, [pc, #216] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
800503e: 685b ldr r3, [r3, #4]
8005040: f003 030c and.w r3, r3, #12
8005044: 2b08 cmp r3, #8
8005046: d061 beq.n 800510c <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8005048: 687b ldr r3, [r7, #4]
800504a: 69db ldr r3, [r3, #28]
800504c: 2b02 cmp r3, #2
800504e: d146 bne.n 80050de <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8005050: 4b33 ldr r3, [pc, #204] @ (8005120 <HAL_RCC_OscConfig+0x4cc>)
8005052: 2200 movs r2, #0
8005054: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005056: f7fd fffd bl 8003054 <HAL_GetTick>
800505a: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800505c: e008 b.n 8005070 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800505e: f7fd fff9 bl 8003054 <HAL_GetTick>
8005062: 4602 mov r2, r0
8005064: 693b ldr r3, [r7, #16]
8005066: 1ad3 subs r3, r2, r3
8005068: 2b02 cmp r3, #2
800506a: d901 bls.n 8005070 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
800506c: 2303 movs r3, #3
800506e: e06d b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005070: 4b29 ldr r3, [pc, #164] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005072: 681b ldr r3, [r3, #0]
8005074: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005078: 2b00 cmp r3, #0
800507a: d1f0 bne.n 800505e <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
800507c: 687b ldr r3, [r7, #4]
800507e: 6a1b ldr r3, [r3, #32]
8005080: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8005084: d108 bne.n 8005098 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8005086: 4b24 ldr r3, [pc, #144] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005088: 685b ldr r3, [r3, #4]
800508a: f423 3200 bic.w r2, r3, #131072 @ 0x20000
800508e: 687b ldr r3, [r7, #4]
8005090: 689b ldr r3, [r3, #8]
8005092: 4921 ldr r1, [pc, #132] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005094: 4313 orrs r3, r2
8005096: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8005098: 4b1f ldr r3, [pc, #124] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
800509a: 685b ldr r3, [r3, #4]
800509c: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
80050a0: 687b ldr r3, [r7, #4]
80050a2: 6a19 ldr r1, [r3, #32]
80050a4: 687b ldr r3, [r7, #4]
80050a6: 6a5b ldr r3, [r3, #36] @ 0x24
80050a8: 430b orrs r3, r1
80050aa: 491b ldr r1, [pc, #108] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
80050ac: 4313 orrs r3, r2
80050ae: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80050b0: 4b1b ldr r3, [pc, #108] @ (8005120 <HAL_RCC_OscConfig+0x4cc>)
80050b2: 2201 movs r2, #1
80050b4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80050b6: f7fd ffcd bl 8003054 <HAL_GetTick>
80050ba: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80050bc: e008 b.n 80050d0 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80050be: f7fd ffc9 bl 8003054 <HAL_GetTick>
80050c2: 4602 mov r2, r0
80050c4: 693b ldr r3, [r7, #16]
80050c6: 1ad3 subs r3, r2, r3
80050c8: 2b02 cmp r3, #2
80050ca: d901 bls.n 80050d0 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
80050cc: 2303 movs r3, #3
80050ce: e03d b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80050d0: 4b11 ldr r3, [pc, #68] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
80050d2: 681b ldr r3, [r3, #0]
80050d4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80050d8: 2b00 cmp r3, #0
80050da: d0f0 beq.n 80050be <HAL_RCC_OscConfig+0x46a>
80050dc: e035 b.n 800514a <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80050de: 4b10 ldr r3, [pc, #64] @ (8005120 <HAL_RCC_OscConfig+0x4cc>)
80050e0: 2200 movs r2, #0
80050e2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80050e4: f7fd ffb6 bl 8003054 <HAL_GetTick>
80050e8: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80050ea: e008 b.n 80050fe <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80050ec: f7fd ffb2 bl 8003054 <HAL_GetTick>
80050f0: 4602 mov r2, r0
80050f2: 693b ldr r3, [r7, #16]
80050f4: 1ad3 subs r3, r2, r3
80050f6: 2b02 cmp r3, #2
80050f8: d901 bls.n 80050fe <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
80050fa: 2303 movs r3, #3
80050fc: e026 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80050fe: 4b06 ldr r3, [pc, #24] @ (8005118 <HAL_RCC_OscConfig+0x4c4>)
8005100: 681b ldr r3, [r3, #0]
8005102: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005106: 2b00 cmp r3, #0
8005108: d1f0 bne.n 80050ec <HAL_RCC_OscConfig+0x498>
800510a: e01e b.n 800514a <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800510c: 687b ldr r3, [r7, #4]
800510e: 69db ldr r3, [r3, #28]
8005110: 2b01 cmp r3, #1
8005112: d107 bne.n 8005124 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8005114: 2301 movs r3, #1
8005116: e019 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
8005118: 40021000 .word 0x40021000
800511c: 40007000 .word 0x40007000
8005120: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8005124: 4b0b ldr r3, [pc, #44] @ (8005154 <HAL_RCC_OscConfig+0x500>)
8005126: 685b ldr r3, [r3, #4]
8005128: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800512a: 68fb ldr r3, [r7, #12]
800512c: f403 3280 and.w r2, r3, #65536 @ 0x10000
8005130: 687b ldr r3, [r7, #4]
8005132: 6a1b ldr r3, [r3, #32]
8005134: 429a cmp r2, r3
8005136: d106 bne.n 8005146 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8005138: 68fb ldr r3, [r7, #12]
800513a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
800513e: 687b ldr r3, [r7, #4]
8005140: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8005142: 429a cmp r2, r3
8005144: d001 beq.n 800514a <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
8005146: 2301 movs r3, #1
8005148: e000 b.n 800514c <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
800514a: 2300 movs r3, #0
}
800514c: 4618 mov r0, r3
800514e: 3718 adds r7, #24
8005150: 46bd mov sp, r7
8005152: bd80 pop {r7, pc}
8005154: 40021000 .word 0x40021000
08005158 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8005158: b580 push {r7, lr}
800515a: b084 sub sp, #16
800515c: af00 add r7, sp, #0
800515e: 6078 str r0, [r7, #4]
8005160: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8005162: 687b ldr r3, [r7, #4]
8005164: 2b00 cmp r3, #0
8005166: d101 bne.n 800516c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8005168: 2301 movs r3, #1
800516a: e0d0 b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800516c: 4b6a ldr r3, [pc, #424] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
800516e: 681b ldr r3, [r3, #0]
8005170: f003 0307 and.w r3, r3, #7
8005174: 683a ldr r2, [r7, #0]
8005176: 429a cmp r2, r3
8005178: d910 bls.n 800519c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800517a: 4b67 ldr r3, [pc, #412] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
800517c: 681b ldr r3, [r3, #0]
800517e: f023 0207 bic.w r2, r3, #7
8005182: 4965 ldr r1, [pc, #404] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
8005184: 683b ldr r3, [r7, #0]
8005186: 4313 orrs r3, r2
8005188: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800518a: 4b63 ldr r3, [pc, #396] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
800518c: 681b ldr r3, [r3, #0]
800518e: f003 0307 and.w r3, r3, #7
8005192: 683a ldr r2, [r7, #0]
8005194: 429a cmp r2, r3
8005196: d001 beq.n 800519c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8005198: 2301 movs r3, #1
800519a: e0b8 b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800519c: 687b ldr r3, [r7, #4]
800519e: 681b ldr r3, [r3, #0]
80051a0: f003 0302 and.w r3, r3, #2
80051a4: 2b00 cmp r3, #0
80051a6: d020 beq.n 80051ea <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80051a8: 687b ldr r3, [r7, #4]
80051aa: 681b ldr r3, [r3, #0]
80051ac: f003 0304 and.w r3, r3, #4
80051b0: 2b00 cmp r3, #0
80051b2: d005 beq.n 80051c0 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80051b4: 4b59 ldr r3, [pc, #356] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051b6: 685b ldr r3, [r3, #4]
80051b8: 4a58 ldr r2, [pc, #352] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051ba: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80051be: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80051c0: 687b ldr r3, [r7, #4]
80051c2: 681b ldr r3, [r3, #0]
80051c4: f003 0308 and.w r3, r3, #8
80051c8: 2b00 cmp r3, #0
80051ca: d005 beq.n 80051d8 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80051cc: 4b53 ldr r3, [pc, #332] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051ce: 685b ldr r3, [r3, #4]
80051d0: 4a52 ldr r2, [pc, #328] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051d2: f443 5360 orr.w r3, r3, #14336 @ 0x3800
80051d6: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80051d8: 4b50 ldr r3, [pc, #320] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051da: 685b ldr r3, [r3, #4]
80051dc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80051e0: 687b ldr r3, [r7, #4]
80051e2: 689b ldr r3, [r3, #8]
80051e4: 494d ldr r1, [pc, #308] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80051e6: 4313 orrs r3, r2
80051e8: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80051ea: 687b ldr r3, [r7, #4]
80051ec: 681b ldr r3, [r3, #0]
80051ee: f003 0301 and.w r3, r3, #1
80051f2: 2b00 cmp r3, #0
80051f4: d040 beq.n 8005278 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80051f6: 687b ldr r3, [r7, #4]
80051f8: 685b ldr r3, [r3, #4]
80051fa: 2b01 cmp r3, #1
80051fc: d107 bne.n 800520e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80051fe: 4b47 ldr r3, [pc, #284] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005200: 681b ldr r3, [r3, #0]
8005202: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005206: 2b00 cmp r3, #0
8005208: d115 bne.n 8005236 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800520a: 2301 movs r3, #1
800520c: e07f b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800520e: 687b ldr r3, [r7, #4]
8005210: 685b ldr r3, [r3, #4]
8005212: 2b02 cmp r3, #2
8005214: d107 bne.n 8005226 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005216: 4b41 ldr r3, [pc, #260] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005218: 681b ldr r3, [r3, #0]
800521a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800521e: 2b00 cmp r3, #0
8005220: d109 bne.n 8005236 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8005222: 2301 movs r3, #1
8005224: e073 b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005226: 4b3d ldr r3, [pc, #244] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005228: 681b ldr r3, [r3, #0]
800522a: f003 0302 and.w r3, r3, #2
800522e: 2b00 cmp r3, #0
8005230: d101 bne.n 8005236 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8005232: 2301 movs r3, #1
8005234: e06b b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8005236: 4b39 ldr r3, [pc, #228] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005238: 685b ldr r3, [r3, #4]
800523a: f023 0203 bic.w r2, r3, #3
800523e: 687b ldr r3, [r7, #4]
8005240: 685b ldr r3, [r3, #4]
8005242: 4936 ldr r1, [pc, #216] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005244: 4313 orrs r3, r2
8005246: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005248: f7fd ff04 bl 8003054 <HAL_GetTick>
800524c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800524e: e00a b.n 8005266 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8005250: f7fd ff00 bl 8003054 <HAL_GetTick>
8005254: 4602 mov r2, r0
8005256: 68fb ldr r3, [r7, #12]
8005258: 1ad3 subs r3, r2, r3
800525a: f241 3288 movw r2, #5000 @ 0x1388
800525e: 4293 cmp r3, r2
8005260: d901 bls.n 8005266 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8005262: 2303 movs r3, #3
8005264: e053 b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8005266: 4b2d ldr r3, [pc, #180] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
8005268: 685b ldr r3, [r3, #4]
800526a: f003 020c and.w r2, r3, #12
800526e: 687b ldr r3, [r7, #4]
8005270: 685b ldr r3, [r3, #4]
8005272: 009b lsls r3, r3, #2
8005274: 429a cmp r2, r3
8005276: d1eb bne.n 8005250 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8005278: 4b27 ldr r3, [pc, #156] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
800527a: 681b ldr r3, [r3, #0]
800527c: f003 0307 and.w r3, r3, #7
8005280: 683a ldr r2, [r7, #0]
8005282: 429a cmp r2, r3
8005284: d210 bcs.n 80052a8 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8005286: 4b24 ldr r3, [pc, #144] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
8005288: 681b ldr r3, [r3, #0]
800528a: f023 0207 bic.w r2, r3, #7
800528e: 4922 ldr r1, [pc, #136] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
8005290: 683b ldr r3, [r7, #0]
8005292: 4313 orrs r3, r2
8005294: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8005296: 4b20 ldr r3, [pc, #128] @ (8005318 <HAL_RCC_ClockConfig+0x1c0>)
8005298: 681b ldr r3, [r3, #0]
800529a: f003 0307 and.w r3, r3, #7
800529e: 683a ldr r2, [r7, #0]
80052a0: 429a cmp r2, r3
80052a2: d001 beq.n 80052a8 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80052a4: 2301 movs r3, #1
80052a6: e032 b.n 800530e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80052a8: 687b ldr r3, [r7, #4]
80052aa: 681b ldr r3, [r3, #0]
80052ac: f003 0304 and.w r3, r3, #4
80052b0: 2b00 cmp r3, #0
80052b2: d008 beq.n 80052c6 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80052b4: 4b19 ldr r3, [pc, #100] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80052b6: 685b ldr r3, [r3, #4]
80052b8: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80052bc: 687b ldr r3, [r7, #4]
80052be: 68db ldr r3, [r3, #12]
80052c0: 4916 ldr r1, [pc, #88] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80052c2: 4313 orrs r3, r2
80052c4: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80052c6: 687b ldr r3, [r7, #4]
80052c8: 681b ldr r3, [r3, #0]
80052ca: f003 0308 and.w r3, r3, #8
80052ce: 2b00 cmp r3, #0
80052d0: d009 beq.n 80052e6 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
80052d2: 4b12 ldr r3, [pc, #72] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80052d4: 685b ldr r3, [r3, #4]
80052d6: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80052da: 687b ldr r3, [r7, #4]
80052dc: 691b ldr r3, [r3, #16]
80052de: 00db lsls r3, r3, #3
80052e0: 490e ldr r1, [pc, #56] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80052e2: 4313 orrs r3, r2
80052e4: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80052e6: f000 f821 bl 800532c <HAL_RCC_GetSysClockFreq>
80052ea: 4602 mov r2, r0
80052ec: 4b0b ldr r3, [pc, #44] @ (800531c <HAL_RCC_ClockConfig+0x1c4>)
80052ee: 685b ldr r3, [r3, #4]
80052f0: 091b lsrs r3, r3, #4
80052f2: f003 030f and.w r3, r3, #15
80052f6: 490a ldr r1, [pc, #40] @ (8005320 <HAL_RCC_ClockConfig+0x1c8>)
80052f8: 5ccb ldrb r3, [r1, r3]
80052fa: fa22 f303 lsr.w r3, r2, r3
80052fe: 4a09 ldr r2, [pc, #36] @ (8005324 <HAL_RCC_ClockConfig+0x1cc>)
8005300: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8005302: 4b09 ldr r3, [pc, #36] @ (8005328 <HAL_RCC_ClockConfig+0x1d0>)
8005304: 681b ldr r3, [r3, #0]
8005306: 4618 mov r0, r3
8005308: f7fd fe62 bl 8002fd0 <HAL_InitTick>
return HAL_OK;
800530c: 2300 movs r3, #0
}
800530e: 4618 mov r0, r3
8005310: 3710 adds r7, #16
8005312: 46bd mov sp, r7
8005314: bd80 pop {r7, pc}
8005316: bf00 nop
8005318: 40022000 .word 0x40022000
800531c: 40021000 .word 0x40021000
8005320: 08006c28 .word 0x08006c28
8005324: 20000004 .word 0x20000004
8005328: 20000008 .word 0x20000008
0800532c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800532c: b480 push {r7}
800532e: b087 sub sp, #28
8005330: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8005332: 2300 movs r3, #0
8005334: 60fb str r3, [r7, #12]
8005336: 2300 movs r3, #0
8005338: 60bb str r3, [r7, #8]
800533a: 2300 movs r3, #0
800533c: 617b str r3, [r7, #20]
800533e: 2300 movs r3, #0
8005340: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
8005342: 2300 movs r3, #0
8005344: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8005346: 4b1e ldr r3, [pc, #120] @ (80053c0 <HAL_RCC_GetSysClockFreq+0x94>)
8005348: 685b ldr r3, [r3, #4]
800534a: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800534c: 68fb ldr r3, [r7, #12]
800534e: f003 030c and.w r3, r3, #12
8005352: 2b04 cmp r3, #4
8005354: d002 beq.n 800535c <HAL_RCC_GetSysClockFreq+0x30>
8005356: 2b08 cmp r3, #8
8005358: d003 beq.n 8005362 <HAL_RCC_GetSysClockFreq+0x36>
800535a: e027 b.n 80053ac <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800535c: 4b19 ldr r3, [pc, #100] @ (80053c4 <HAL_RCC_GetSysClockFreq+0x98>)
800535e: 613b str r3, [r7, #16]
break;
8005360: e027 b.n 80053b2 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8005362: 68fb ldr r3, [r7, #12]
8005364: 0c9b lsrs r3, r3, #18
8005366: f003 030f and.w r3, r3, #15
800536a: 4a17 ldr r2, [pc, #92] @ (80053c8 <HAL_RCC_GetSysClockFreq+0x9c>)
800536c: 5cd3 ldrb r3, [r2, r3]
800536e: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8005370: 68fb ldr r3, [r7, #12]
8005372: f403 3380 and.w r3, r3, #65536 @ 0x10000
8005376: 2b00 cmp r3, #0
8005378: d010 beq.n 800539c <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
800537a: 4b11 ldr r3, [pc, #68] @ (80053c0 <HAL_RCC_GetSysClockFreq+0x94>)
800537c: 685b ldr r3, [r3, #4]
800537e: 0c5b lsrs r3, r3, #17
8005380: f003 0301 and.w r3, r3, #1
8005384: 4a11 ldr r2, [pc, #68] @ (80053cc <HAL_RCC_GetSysClockFreq+0xa0>)
8005386: 5cd3 ldrb r3, [r2, r3]
8005388: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
800538a: 687b ldr r3, [r7, #4]
800538c: 4a0d ldr r2, [pc, #52] @ (80053c4 <HAL_RCC_GetSysClockFreq+0x98>)
800538e: fb03 f202 mul.w r2, r3, r2
8005392: 68bb ldr r3, [r7, #8]
8005394: fbb2 f3f3 udiv r3, r2, r3
8005398: 617b str r3, [r7, #20]
800539a: e004 b.n 80053a6 <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
800539c: 687b ldr r3, [r7, #4]
800539e: 4a0c ldr r2, [pc, #48] @ (80053d0 <HAL_RCC_GetSysClockFreq+0xa4>)
80053a0: fb02 f303 mul.w r3, r2, r3
80053a4: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
80053a6: 697b ldr r3, [r7, #20]
80053a8: 613b str r3, [r7, #16]
break;
80053aa: e002 b.n 80053b2 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80053ac: 4b09 ldr r3, [pc, #36] @ (80053d4 <HAL_RCC_GetSysClockFreq+0xa8>)
80053ae: 613b str r3, [r7, #16]
break;
80053b0: bf00 nop
}
}
return sysclockfreq;
80053b2: 693b ldr r3, [r7, #16]
}
80053b4: 4618 mov r0, r3
80053b6: 371c adds r7, #28
80053b8: 46bd mov sp, r7
80053ba: bc80 pop {r7}
80053bc: 4770 bx lr
80053be: bf00 nop
80053c0: 40021000 .word 0x40021000
80053c4: 00b71b00 .word 0x00b71b00
80053c8: 08006c40 .word 0x08006c40
80053cc: 08006c50 .word 0x08006c50
80053d0: 003d0900 .word 0x003d0900
80053d4: 007a1200 .word 0x007a1200
080053d8 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80053d8: b480 push {r7}
80053da: af00 add r7, sp, #0
return SystemCoreClock;
80053dc: 4b02 ldr r3, [pc, #8] @ (80053e8 <HAL_RCC_GetHCLKFreq+0x10>)
80053de: 681b ldr r3, [r3, #0]
}
80053e0: 4618 mov r0, r3
80053e2: 46bd mov sp, r7
80053e4: bc80 pop {r7}
80053e6: 4770 bx lr
80053e8: 20000004 .word 0x20000004
080053ec <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80053ec: b580 push {r7, lr}
80053ee: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
80053f0: f7ff fff2 bl 80053d8 <HAL_RCC_GetHCLKFreq>
80053f4: 4602 mov r2, r0
80053f6: 4b05 ldr r3, [pc, #20] @ (800540c <HAL_RCC_GetPCLK1Freq+0x20>)
80053f8: 685b ldr r3, [r3, #4]
80053fa: 0a1b lsrs r3, r3, #8
80053fc: f003 0307 and.w r3, r3, #7
8005400: 4903 ldr r1, [pc, #12] @ (8005410 <HAL_RCC_GetPCLK1Freq+0x24>)
8005402: 5ccb ldrb r3, [r1, r3]
8005404: fa22 f303 lsr.w r3, r2, r3
}
8005408: 4618 mov r0, r3
800540a: bd80 pop {r7, pc}
800540c: 40021000 .word 0x40021000
8005410: 08006c38 .word 0x08006c38
08005414 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8005414: b580 push {r7, lr}
8005416: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8005418: f7ff ffde bl 80053d8 <HAL_RCC_GetHCLKFreq>
800541c: 4602 mov r2, r0
800541e: 4b05 ldr r3, [pc, #20] @ (8005434 <HAL_RCC_GetPCLK2Freq+0x20>)
8005420: 685b ldr r3, [r3, #4]
8005422: 0adb lsrs r3, r3, #11
8005424: f003 0307 and.w r3, r3, #7
8005428: 4903 ldr r1, [pc, #12] @ (8005438 <HAL_RCC_GetPCLK2Freq+0x24>)
800542a: 5ccb ldrb r3, [r1, r3]
800542c: fa22 f303 lsr.w r3, r2, r3
}
8005430: 4618 mov r0, r3
8005432: bd80 pop {r7, pc}
8005434: 40021000 .word 0x40021000
8005438: 08006c38 .word 0x08006c38
0800543c <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
800543c: b480 push {r7}
800543e: b085 sub sp, #20
8005440: af00 add r7, sp, #0
8005442: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8005444: 4b0a ldr r3, [pc, #40] @ (8005470 <RCC_Delay+0x34>)
8005446: 681b ldr r3, [r3, #0]
8005448: 4a0a ldr r2, [pc, #40] @ (8005474 <RCC_Delay+0x38>)
800544a: fba2 2303 umull r2, r3, r2, r3
800544e: 0a5b lsrs r3, r3, #9
8005450: 687a ldr r2, [r7, #4]
8005452: fb02 f303 mul.w r3, r2, r3
8005456: 60fb str r3, [r7, #12]
do
{
__NOP();
8005458: bf00 nop
}
while (Delay --);
800545a: 68fb ldr r3, [r7, #12]
800545c: 1e5a subs r2, r3, #1
800545e: 60fa str r2, [r7, #12]
8005460: 2b00 cmp r3, #0
8005462: d1f9 bne.n 8005458 <RCC_Delay+0x1c>
}
8005464: bf00 nop
8005466: bf00 nop
8005468: 3714 adds r7, #20
800546a: 46bd mov sp, r7
800546c: bc80 pop {r7}
800546e: 4770 bx lr
8005470: 20000004 .word 0x20000004
8005474: 10624dd3 .word 0x10624dd3
08005478 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8005478: b580 push {r7, lr}
800547a: b086 sub sp, #24
800547c: af00 add r7, sp, #0
800547e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8005480: 2300 movs r3, #0
8005482: 613b str r3, [r7, #16]
8005484: 2300 movs r3, #0
8005486: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8005488: 687b ldr r3, [r7, #4]
800548a: 681b ldr r3, [r3, #0]
800548c: f003 0301 and.w r3, r3, #1
8005490: 2b00 cmp r3, #0
8005492: d07d beq.n 8005590 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8005494: 2300 movs r3, #0
8005496: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8005498: 4b4f ldr r3, [pc, #316] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800549a: 69db ldr r3, [r3, #28]
800549c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80054a0: 2b00 cmp r3, #0
80054a2: d10d bne.n 80054c0 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
80054a4: 4b4c ldr r3, [pc, #304] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054a6: 69db ldr r3, [r3, #28]
80054a8: 4a4b ldr r2, [pc, #300] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054aa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80054ae: 61d3 str r3, [r2, #28]
80054b0: 4b49 ldr r3, [pc, #292] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054b2: 69db ldr r3, [r3, #28]
80054b4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80054b8: 60bb str r3, [r7, #8]
80054ba: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80054bc: 2301 movs r3, #1
80054be: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054c0: 4b46 ldr r3, [pc, #280] @ (80055dc <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054c2: 681b ldr r3, [r3, #0]
80054c4: f403 7380 and.w r3, r3, #256 @ 0x100
80054c8: 2b00 cmp r3, #0
80054ca: d118 bne.n 80054fe <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80054cc: 4b43 ldr r3, [pc, #268] @ (80055dc <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054ce: 681b ldr r3, [r3, #0]
80054d0: 4a42 ldr r2, [pc, #264] @ (80055dc <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054d2: f443 7380 orr.w r3, r3, #256 @ 0x100
80054d6: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80054d8: f7fd fdbc bl 8003054 <HAL_GetTick>
80054dc: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054de: e008 b.n 80054f2 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80054e0: f7fd fdb8 bl 8003054 <HAL_GetTick>
80054e4: 4602 mov r2, r0
80054e6: 693b ldr r3, [r7, #16]
80054e8: 1ad3 subs r3, r2, r3
80054ea: 2b64 cmp r3, #100 @ 0x64
80054ec: d901 bls.n 80054f2 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
80054ee: 2303 movs r3, #3
80054f0: e06d b.n 80055ce <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054f2: 4b3a ldr r3, [pc, #232] @ (80055dc <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054f4: 681b ldr r3, [r3, #0]
80054f6: f403 7380 and.w r3, r3, #256 @ 0x100
80054fa: 2b00 cmp r3, #0
80054fc: d0f0 beq.n 80054e0 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
80054fe: 4b36 ldr r3, [pc, #216] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005500: 6a1b ldr r3, [r3, #32]
8005502: f403 7340 and.w r3, r3, #768 @ 0x300
8005506: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8005508: 68fb ldr r3, [r7, #12]
800550a: 2b00 cmp r3, #0
800550c: d02e beq.n 800556c <HAL_RCCEx_PeriphCLKConfig+0xf4>
800550e: 687b ldr r3, [r7, #4]
8005510: 685b ldr r3, [r3, #4]
8005512: f403 7340 and.w r3, r3, #768 @ 0x300
8005516: 68fa ldr r2, [r7, #12]
8005518: 429a cmp r2, r3
800551a: d027 beq.n 800556c <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
800551c: 4b2e ldr r3, [pc, #184] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800551e: 6a1b ldr r3, [r3, #32]
8005520: f423 7340 bic.w r3, r3, #768 @ 0x300
8005524: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8005526: 4b2e ldr r3, [pc, #184] @ (80055e0 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005528: 2201 movs r2, #1
800552a: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
800552c: 4b2c ldr r3, [pc, #176] @ (80055e0 <HAL_RCCEx_PeriphCLKConfig+0x168>)
800552e: 2200 movs r2, #0
8005530: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8005532: 4a29 ldr r2, [pc, #164] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005534: 68fb ldr r3, [r7, #12]
8005536: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8005538: 68fb ldr r3, [r7, #12]
800553a: f003 0301 and.w r3, r3, #1
800553e: 2b00 cmp r3, #0
8005540: d014 beq.n 800556c <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005542: f7fd fd87 bl 8003054 <HAL_GetTick>
8005546: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005548: e00a b.n 8005560 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800554a: f7fd fd83 bl 8003054 <HAL_GetTick>
800554e: 4602 mov r2, r0
8005550: 693b ldr r3, [r7, #16]
8005552: 1ad3 subs r3, r2, r3
8005554: f241 3288 movw r2, #5000 @ 0x1388
8005558: 4293 cmp r3, r2
800555a: d901 bls.n 8005560 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
800555c: 2303 movs r3, #3
800555e: e036 b.n 80055ce <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005560: 4b1d ldr r3, [pc, #116] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005562: 6a1b ldr r3, [r3, #32]
8005564: f003 0302 and.w r3, r3, #2
8005568: 2b00 cmp r3, #0
800556a: d0ee beq.n 800554a <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800556c: 4b1a ldr r3, [pc, #104] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800556e: 6a1b ldr r3, [r3, #32]
8005570: f423 7240 bic.w r2, r3, #768 @ 0x300
8005574: 687b ldr r3, [r7, #4]
8005576: 685b ldr r3, [r3, #4]
8005578: 4917 ldr r1, [pc, #92] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800557a: 4313 orrs r3, r2
800557c: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
800557e: 7dfb ldrb r3, [r7, #23]
8005580: 2b01 cmp r3, #1
8005582: d105 bne.n 8005590 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005584: 4b14 ldr r3, [pc, #80] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005586: 69db ldr r3, [r3, #28]
8005588: 4a13 ldr r2, [pc, #76] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800558a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800558e: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8005590: 687b ldr r3, [r7, #4]
8005592: 681b ldr r3, [r3, #0]
8005594: f003 0302 and.w r3, r3, #2
8005598: 2b00 cmp r3, #0
800559a: d008 beq.n 80055ae <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
800559c: 4b0e ldr r3, [pc, #56] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800559e: 685b ldr r3, [r3, #4]
80055a0: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80055a4: 687b ldr r3, [r7, #4]
80055a6: 689b ldr r3, [r3, #8]
80055a8: 490b ldr r1, [pc, #44] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055aa: 4313 orrs r3, r2
80055ac: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80055ae: 687b ldr r3, [r7, #4]
80055b0: 681b ldr r3, [r3, #0]
80055b2: f003 0310 and.w r3, r3, #16
80055b6: 2b00 cmp r3, #0
80055b8: d008 beq.n 80055cc <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80055ba: 4b07 ldr r3, [pc, #28] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055bc: 685b ldr r3, [r3, #4]
80055be: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
80055c2: 687b ldr r3, [r7, #4]
80055c4: 68db ldr r3, [r3, #12]
80055c6: 4904 ldr r1, [pc, #16] @ (80055d8 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055c8: 4313 orrs r3, r2
80055ca: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
80055cc: 2300 movs r3, #0
}
80055ce: 4618 mov r0, r3
80055d0: 3718 adds r7, #24
80055d2: 46bd mov sp, r7
80055d4: bd80 pop {r7, pc}
80055d6: bf00 nop
80055d8: 40021000 .word 0x40021000
80055dc: 40007000 .word 0x40007000
80055e0: 42420440 .word 0x42420440
080055e4 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80055e4: b580 push {r7, lr}
80055e6: b082 sub sp, #8
80055e8: af00 add r7, sp, #0
80055ea: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80055ec: 687b ldr r3, [r7, #4]
80055ee: 2b00 cmp r3, #0
80055f0: d101 bne.n 80055f6 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80055f2: 2301 movs r3, #1
80055f4: e041 b.n 800567a <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80055f6: 687b ldr r3, [r7, #4]
80055f8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80055fc: b2db uxtb r3, r3
80055fe: 2b00 cmp r3, #0
8005600: d106 bne.n 8005610 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005602: 687b ldr r3, [r7, #4]
8005604: 2200 movs r2, #0
8005606: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800560a: 6878 ldr r0, [r7, #4]
800560c: f7fd fc00 bl 8002e10 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005610: 687b ldr r3, [r7, #4]
8005612: 2202 movs r2, #2
8005614: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005618: 687b ldr r3, [r7, #4]
800561a: 681a ldr r2, [r3, #0]
800561c: 687b ldr r3, [r7, #4]
800561e: 3304 adds r3, #4
8005620: 4619 mov r1, r3
8005622: 4610 mov r0, r2
8005624: f000 fa5c bl 8005ae0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005628: 687b ldr r3, [r7, #4]
800562a: 2201 movs r2, #1
800562c: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005630: 687b ldr r3, [r7, #4]
8005632: 2201 movs r2, #1
8005634: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005638: 687b ldr r3, [r7, #4]
800563a: 2201 movs r2, #1
800563c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005640: 687b ldr r3, [r7, #4]
8005642: 2201 movs r2, #1
8005644: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005648: 687b ldr r3, [r7, #4]
800564a: 2201 movs r2, #1
800564c: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005650: 687b ldr r3, [r7, #4]
8005652: 2201 movs r2, #1
8005654: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005658: 687b ldr r3, [r7, #4]
800565a: 2201 movs r2, #1
800565c: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005660: 687b ldr r3, [r7, #4]
8005662: 2201 movs r2, #1
8005664: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005668: 687b ldr r3, [r7, #4]
800566a: 2201 movs r2, #1
800566c: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005670: 687b ldr r3, [r7, #4]
8005672: 2201 movs r2, #1
8005674: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005678: 2300 movs r3, #0
}
800567a: 4618 mov r0, r3
800567c: 3708 adds r7, #8
800567e: 46bd mov sp, r7
8005680: bd80 pop {r7, pc}
...
08005684 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8005684: b480 push {r7}
8005686: b085 sub sp, #20
8005688: af00 add r7, sp, #0
800568a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
800568c: 687b ldr r3, [r7, #4]
800568e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005692: b2db uxtb r3, r3
8005694: 2b01 cmp r3, #1
8005696: d001 beq.n 800569c <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8005698: 2301 movs r3, #1
800569a: e03a b.n 8005712 <HAL_TIM_Base_Start_IT+0x8e>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800569c: 687b ldr r3, [r7, #4]
800569e: 2202 movs r2, #2
80056a0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
80056a4: 687b ldr r3, [r7, #4]
80056a6: 681b ldr r3, [r3, #0]
80056a8: 68da ldr r2, [r3, #12]
80056aa: 687b ldr r3, [r7, #4]
80056ac: 681b ldr r3, [r3, #0]
80056ae: f042 0201 orr.w r2, r2, #1
80056b2: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80056b4: 687b ldr r3, [r7, #4]
80056b6: 681b ldr r3, [r3, #0]
80056b8: 4a18 ldr r2, [pc, #96] @ (800571c <HAL_TIM_Base_Start_IT+0x98>)
80056ba: 4293 cmp r3, r2
80056bc: d00e beq.n 80056dc <HAL_TIM_Base_Start_IT+0x58>
80056be: 687b ldr r3, [r7, #4]
80056c0: 681b ldr r3, [r3, #0]
80056c2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80056c6: d009 beq.n 80056dc <HAL_TIM_Base_Start_IT+0x58>
80056c8: 687b ldr r3, [r7, #4]
80056ca: 681b ldr r3, [r3, #0]
80056cc: 4a14 ldr r2, [pc, #80] @ (8005720 <HAL_TIM_Base_Start_IT+0x9c>)
80056ce: 4293 cmp r3, r2
80056d0: d004 beq.n 80056dc <HAL_TIM_Base_Start_IT+0x58>
80056d2: 687b ldr r3, [r7, #4]
80056d4: 681b ldr r3, [r3, #0]
80056d6: 4a13 ldr r2, [pc, #76] @ (8005724 <HAL_TIM_Base_Start_IT+0xa0>)
80056d8: 4293 cmp r3, r2
80056da: d111 bne.n 8005700 <HAL_TIM_Base_Start_IT+0x7c>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80056dc: 687b ldr r3, [r7, #4]
80056de: 681b ldr r3, [r3, #0]
80056e0: 689b ldr r3, [r3, #8]
80056e2: f003 0307 and.w r3, r3, #7
80056e6: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80056e8: 68fb ldr r3, [r7, #12]
80056ea: 2b06 cmp r3, #6
80056ec: d010 beq.n 8005710 <HAL_TIM_Base_Start_IT+0x8c>
{
__HAL_TIM_ENABLE(htim);
80056ee: 687b ldr r3, [r7, #4]
80056f0: 681b ldr r3, [r3, #0]
80056f2: 681a ldr r2, [r3, #0]
80056f4: 687b ldr r3, [r7, #4]
80056f6: 681b ldr r3, [r3, #0]
80056f8: f042 0201 orr.w r2, r2, #1
80056fc: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80056fe: e007 b.n 8005710 <HAL_TIM_Base_Start_IT+0x8c>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8005700: 687b ldr r3, [r7, #4]
8005702: 681b ldr r3, [r3, #0]
8005704: 681a ldr r2, [r3, #0]
8005706: 687b ldr r3, [r7, #4]
8005708: 681b ldr r3, [r3, #0]
800570a: f042 0201 orr.w r2, r2, #1
800570e: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8005710: 2300 movs r3, #0
}
8005712: 4618 mov r0, r3
8005714: 3714 adds r7, #20
8005716: 46bd mov sp, r7
8005718: bc80 pop {r7}
800571a: 4770 bx lr
800571c: 40012c00 .word 0x40012c00
8005720: 40000400 .word 0x40000400
8005724: 40000800 .word 0x40000800
08005728 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8005728: b580 push {r7, lr}
800572a: b084 sub sp, #16
800572c: af00 add r7, sp, #0
800572e: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8005730: 687b ldr r3, [r7, #4]
8005732: 681b ldr r3, [r3, #0]
8005734: 68db ldr r3, [r3, #12]
8005736: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8005738: 687b ldr r3, [r7, #4]
800573a: 681b ldr r3, [r3, #0]
800573c: 691b ldr r3, [r3, #16]
800573e: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8005740: 68bb ldr r3, [r7, #8]
8005742: f003 0302 and.w r3, r3, #2
8005746: 2b00 cmp r3, #0
8005748: d020 beq.n 800578c <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800574a: 68fb ldr r3, [r7, #12]
800574c: f003 0302 and.w r3, r3, #2
8005750: 2b00 cmp r3, #0
8005752: d01b beq.n 800578c <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8005754: 687b ldr r3, [r7, #4]
8005756: 681b ldr r3, [r3, #0]
8005758: f06f 0202 mvn.w r2, #2
800575c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
800575e: 687b ldr r3, [r7, #4]
8005760: 2201 movs r2, #1
8005762: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8005764: 687b ldr r3, [r7, #4]
8005766: 681b ldr r3, [r3, #0]
8005768: 699b ldr r3, [r3, #24]
800576a: f003 0303 and.w r3, r3, #3
800576e: 2b00 cmp r3, #0
8005770: d003 beq.n 800577a <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005772: 6878 ldr r0, [r7, #4]
8005774: f000 f998 bl 8005aa8 <HAL_TIM_IC_CaptureCallback>
8005778: e005 b.n 8005786 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800577a: 6878 ldr r0, [r7, #4]
800577c: f000 f98b bl 8005a96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005780: 6878 ldr r0, [r7, #4]
8005782: f000 f99a bl 8005aba <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005786: 687b ldr r3, [r7, #4]
8005788: 2200 movs r2, #0
800578a: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
800578c: 68bb ldr r3, [r7, #8]
800578e: f003 0304 and.w r3, r3, #4
8005792: 2b00 cmp r3, #0
8005794: d020 beq.n 80057d8 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8005796: 68fb ldr r3, [r7, #12]
8005798: f003 0304 and.w r3, r3, #4
800579c: 2b00 cmp r3, #0
800579e: d01b beq.n 80057d8 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80057a0: 687b ldr r3, [r7, #4]
80057a2: 681b ldr r3, [r3, #0]
80057a4: f06f 0204 mvn.w r2, #4
80057a8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80057aa: 687b ldr r3, [r7, #4]
80057ac: 2202 movs r2, #2
80057ae: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80057b0: 687b ldr r3, [r7, #4]
80057b2: 681b ldr r3, [r3, #0]
80057b4: 699b ldr r3, [r3, #24]
80057b6: f403 7340 and.w r3, r3, #768 @ 0x300
80057ba: 2b00 cmp r3, #0
80057bc: d003 beq.n 80057c6 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80057be: 6878 ldr r0, [r7, #4]
80057c0: f000 f972 bl 8005aa8 <HAL_TIM_IC_CaptureCallback>
80057c4: e005 b.n 80057d2 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80057c6: 6878 ldr r0, [r7, #4]
80057c8: f000 f965 bl 8005a96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80057cc: 6878 ldr r0, [r7, #4]
80057ce: f000 f974 bl 8005aba <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80057d2: 687b ldr r3, [r7, #4]
80057d4: 2200 movs r2, #0
80057d6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80057d8: 68bb ldr r3, [r7, #8]
80057da: f003 0308 and.w r3, r3, #8
80057de: 2b00 cmp r3, #0
80057e0: d020 beq.n 8005824 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80057e2: 68fb ldr r3, [r7, #12]
80057e4: f003 0308 and.w r3, r3, #8
80057e8: 2b00 cmp r3, #0
80057ea: d01b beq.n 8005824 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80057ec: 687b ldr r3, [r7, #4]
80057ee: 681b ldr r3, [r3, #0]
80057f0: f06f 0208 mvn.w r2, #8
80057f4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80057f6: 687b ldr r3, [r7, #4]
80057f8: 2204 movs r2, #4
80057fa: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
80057fc: 687b ldr r3, [r7, #4]
80057fe: 681b ldr r3, [r3, #0]
8005800: 69db ldr r3, [r3, #28]
8005802: f003 0303 and.w r3, r3, #3
8005806: 2b00 cmp r3, #0
8005808: d003 beq.n 8005812 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800580a: 6878 ldr r0, [r7, #4]
800580c: f000 f94c bl 8005aa8 <HAL_TIM_IC_CaptureCallback>
8005810: e005 b.n 800581e <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005812: 6878 ldr r0, [r7, #4]
8005814: f000 f93f bl 8005a96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005818: 6878 ldr r0, [r7, #4]
800581a: f000 f94e bl 8005aba <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800581e: 687b ldr r3, [r7, #4]
8005820: 2200 movs r2, #0
8005822: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8005824: 68bb ldr r3, [r7, #8]
8005826: f003 0310 and.w r3, r3, #16
800582a: 2b00 cmp r3, #0
800582c: d020 beq.n 8005870 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
800582e: 68fb ldr r3, [r7, #12]
8005830: f003 0310 and.w r3, r3, #16
8005834: 2b00 cmp r3, #0
8005836: d01b beq.n 8005870 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8005838: 687b ldr r3, [r7, #4]
800583a: 681b ldr r3, [r3, #0]
800583c: f06f 0210 mvn.w r2, #16
8005840: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8005842: 687b ldr r3, [r7, #4]
8005844: 2208 movs r2, #8
8005846: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8005848: 687b ldr r3, [r7, #4]
800584a: 681b ldr r3, [r3, #0]
800584c: 69db ldr r3, [r3, #28]
800584e: f403 7340 and.w r3, r3, #768 @ 0x300
8005852: 2b00 cmp r3, #0
8005854: d003 beq.n 800585e <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005856: 6878 ldr r0, [r7, #4]
8005858: f000 f926 bl 8005aa8 <HAL_TIM_IC_CaptureCallback>
800585c: e005 b.n 800586a <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800585e: 6878 ldr r0, [r7, #4]
8005860: f000 f919 bl 8005a96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005864: 6878 ldr r0, [r7, #4]
8005866: f000 f928 bl 8005aba <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800586a: 687b ldr r3, [r7, #4]
800586c: 2200 movs r2, #0
800586e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8005870: 68bb ldr r3, [r7, #8]
8005872: f003 0301 and.w r3, r3, #1
8005876: 2b00 cmp r3, #0
8005878: d00c beq.n 8005894 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800587a: 68fb ldr r3, [r7, #12]
800587c: f003 0301 and.w r3, r3, #1
8005880: 2b00 cmp r3, #0
8005882: d007 beq.n 8005894 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8005884: 687b ldr r3, [r7, #4]
8005886: 681b ldr r3, [r3, #0]
8005888: f06f 0201 mvn.w r2, #1
800588c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
800588e: 6878 ldr r0, [r7, #4]
8005890: f7fd f8e6 bl 8002a60 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
8005894: 68bb ldr r3, [r7, #8]
8005896: f003 0380 and.w r3, r3, #128 @ 0x80
800589a: 2b00 cmp r3, #0
800589c: d00c beq.n 80058b8 <HAL_TIM_IRQHandler+0x190>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800589e: 68fb ldr r3, [r7, #12]
80058a0: f003 0380 and.w r3, r3, #128 @ 0x80
80058a4: 2b00 cmp r3, #0
80058a6: d007 beq.n 80058b8 <HAL_TIM_IRQHandler+0x190>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
80058a8: 687b ldr r3, [r7, #4]
80058aa: 681b ldr r3, [r3, #0]
80058ac: f06f 0280 mvn.w r2, #128 @ 0x80
80058b0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80058b2: 6878 ldr r0, [r7, #4]
80058b4: f000 fa7f bl 8005db6 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80058b8: 68bb ldr r3, [r7, #8]
80058ba: f003 0340 and.w r3, r3, #64 @ 0x40
80058be: 2b00 cmp r3, #0
80058c0: d00c beq.n 80058dc <HAL_TIM_IRQHandler+0x1b4>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80058c2: 68fb ldr r3, [r7, #12]
80058c4: f003 0340 and.w r3, r3, #64 @ 0x40
80058c8: 2b00 cmp r3, #0
80058ca: d007 beq.n 80058dc <HAL_TIM_IRQHandler+0x1b4>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80058cc: 687b ldr r3, [r7, #4]
80058ce: 681b ldr r3, [r3, #0]
80058d0: f06f 0240 mvn.w r2, #64 @ 0x40
80058d4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80058d6: 6878 ldr r0, [r7, #4]
80058d8: f000 f8f8 bl 8005acc <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80058dc: 68bb ldr r3, [r7, #8]
80058de: f003 0320 and.w r3, r3, #32
80058e2: 2b00 cmp r3, #0
80058e4: d00c beq.n 8005900 <HAL_TIM_IRQHandler+0x1d8>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80058e6: 68fb ldr r3, [r7, #12]
80058e8: f003 0320 and.w r3, r3, #32
80058ec: 2b00 cmp r3, #0
80058ee: d007 beq.n 8005900 <HAL_TIM_IRQHandler+0x1d8>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
80058f0: 687b ldr r3, [r7, #4]
80058f2: 681b ldr r3, [r3, #0]
80058f4: f06f 0220 mvn.w r2, #32
80058f8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80058fa: 6878 ldr r0, [r7, #4]
80058fc: f000 fa52 bl 8005da4 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8005900: bf00 nop
8005902: 3710 adds r7, #16
8005904: 46bd mov sp, r7
8005906: bd80 pop {r7, pc}
08005908 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8005908: b580 push {r7, lr}
800590a: b084 sub sp, #16
800590c: af00 add r7, sp, #0
800590e: 6078 str r0, [r7, #4]
8005910: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8005912: 2300 movs r3, #0
8005914: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8005916: 687b ldr r3, [r7, #4]
8005918: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800591c: 2b01 cmp r3, #1
800591e: d101 bne.n 8005924 <HAL_TIM_ConfigClockSource+0x1c>
8005920: 2302 movs r3, #2
8005922: e0b4 b.n 8005a8e <HAL_TIM_ConfigClockSource+0x186>
8005924: 687b ldr r3, [r7, #4]
8005926: 2201 movs r2, #1
8005928: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800592c: 687b ldr r3, [r7, #4]
800592e: 2202 movs r2, #2
8005930: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8005934: 687b ldr r3, [r7, #4]
8005936: 681b ldr r3, [r3, #0]
8005938: 689b ldr r3, [r3, #8]
800593a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
800593c: 68bb ldr r3, [r7, #8]
800593e: f023 0377 bic.w r3, r3, #119 @ 0x77
8005942: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005944: 68bb ldr r3, [r7, #8]
8005946: f423 437f bic.w r3, r3, #65280 @ 0xff00
800594a: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
800594c: 687b ldr r3, [r7, #4]
800594e: 681b ldr r3, [r3, #0]
8005950: 68ba ldr r2, [r7, #8]
8005952: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005954: 683b ldr r3, [r7, #0]
8005956: 681b ldr r3, [r3, #0]
8005958: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800595c: d03e beq.n 80059dc <HAL_TIM_ConfigClockSource+0xd4>
800595e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005962: f200 8087 bhi.w 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
8005966: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800596a: f000 8086 beq.w 8005a7a <HAL_TIM_ConfigClockSource+0x172>
800596e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005972: d87f bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
8005974: 2b70 cmp r3, #112 @ 0x70
8005976: d01a beq.n 80059ae <HAL_TIM_ConfigClockSource+0xa6>
8005978: 2b70 cmp r3, #112 @ 0x70
800597a: d87b bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
800597c: 2b60 cmp r3, #96 @ 0x60
800597e: d050 beq.n 8005a22 <HAL_TIM_ConfigClockSource+0x11a>
8005980: 2b60 cmp r3, #96 @ 0x60
8005982: d877 bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
8005984: 2b50 cmp r3, #80 @ 0x50
8005986: d03c beq.n 8005a02 <HAL_TIM_ConfigClockSource+0xfa>
8005988: 2b50 cmp r3, #80 @ 0x50
800598a: d873 bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
800598c: 2b40 cmp r3, #64 @ 0x40
800598e: d058 beq.n 8005a42 <HAL_TIM_ConfigClockSource+0x13a>
8005990: 2b40 cmp r3, #64 @ 0x40
8005992: d86f bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
8005994: 2b30 cmp r3, #48 @ 0x30
8005996: d064 beq.n 8005a62 <HAL_TIM_ConfigClockSource+0x15a>
8005998: 2b30 cmp r3, #48 @ 0x30
800599a: d86b bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
800599c: 2b20 cmp r3, #32
800599e: d060 beq.n 8005a62 <HAL_TIM_ConfigClockSource+0x15a>
80059a0: 2b20 cmp r3, #32
80059a2: d867 bhi.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
80059a4: 2b00 cmp r3, #0
80059a6: d05c beq.n 8005a62 <HAL_TIM_ConfigClockSource+0x15a>
80059a8: 2b10 cmp r3, #16
80059aa: d05a beq.n 8005a62 <HAL_TIM_ConfigClockSource+0x15a>
80059ac: e062 b.n 8005a74 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80059ae: 687b ldr r3, [r7, #4]
80059b0: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80059b2: 683b ldr r3, [r7, #0]
80059b4: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80059b6: 683b ldr r3, [r7, #0]
80059b8: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80059ba: 683b ldr r3, [r7, #0]
80059bc: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80059be: f000 f974 bl 8005caa <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80059c2: 687b ldr r3, [r7, #4]
80059c4: 681b ldr r3, [r3, #0]
80059c6: 689b ldr r3, [r3, #8]
80059c8: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80059ca: 68bb ldr r3, [r7, #8]
80059cc: f043 0377 orr.w r3, r3, #119 @ 0x77
80059d0: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80059d2: 687b ldr r3, [r7, #4]
80059d4: 681b ldr r3, [r3, #0]
80059d6: 68ba ldr r2, [r7, #8]
80059d8: 609a str r2, [r3, #8]
break;
80059da: e04f b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80059dc: 687b ldr r3, [r7, #4]
80059de: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80059e0: 683b ldr r3, [r7, #0]
80059e2: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80059e4: 683b ldr r3, [r7, #0]
80059e6: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80059e8: 683b ldr r3, [r7, #0]
80059ea: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80059ec: f000 f95d bl 8005caa <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
80059f0: 687b ldr r3, [r7, #4]
80059f2: 681b ldr r3, [r3, #0]
80059f4: 689a ldr r2, [r3, #8]
80059f6: 687b ldr r3, [r7, #4]
80059f8: 681b ldr r3, [r3, #0]
80059fa: f442 4280 orr.w r2, r2, #16384 @ 0x4000
80059fe: 609a str r2, [r3, #8]
break;
8005a00: e03c b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005a02: 687b ldr r3, [r7, #4]
8005a04: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005a06: 683b ldr r3, [r7, #0]
8005a08: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8005a0a: 683b ldr r3, [r7, #0]
8005a0c: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005a0e: 461a mov r2, r3
8005a10: f000 f8d4 bl 8005bbc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8005a14: 687b ldr r3, [r7, #4]
8005a16: 681b ldr r3, [r3, #0]
8005a18: 2150 movs r1, #80 @ 0x50
8005a1a: 4618 mov r0, r3
8005a1c: f000 f92b bl 8005c76 <TIM_ITRx_SetConfig>
break;
8005a20: e02c b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8005a22: 687b ldr r3, [r7, #4]
8005a24: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005a26: 683b ldr r3, [r7, #0]
8005a28: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8005a2a: 683b ldr r3, [r7, #0]
8005a2c: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8005a2e: 461a mov r2, r3
8005a30: f000 f8f2 bl 8005c18 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8005a34: 687b ldr r3, [r7, #4]
8005a36: 681b ldr r3, [r3, #0]
8005a38: 2160 movs r1, #96 @ 0x60
8005a3a: 4618 mov r0, r3
8005a3c: f000 f91b bl 8005c76 <TIM_ITRx_SetConfig>
break;
8005a40: e01c b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005a42: 687b ldr r3, [r7, #4]
8005a44: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005a46: 683b ldr r3, [r7, #0]
8005a48: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8005a4a: 683b ldr r3, [r7, #0]
8005a4c: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005a4e: 461a mov r2, r3
8005a50: f000 f8b4 bl 8005bbc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8005a54: 687b ldr r3, [r7, #4]
8005a56: 681b ldr r3, [r3, #0]
8005a58: 2140 movs r1, #64 @ 0x40
8005a5a: 4618 mov r0, r3
8005a5c: f000 f90b bl 8005c76 <TIM_ITRx_SetConfig>
break;
8005a60: e00c b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8005a62: 687b ldr r3, [r7, #4]
8005a64: 681a ldr r2, [r3, #0]
8005a66: 683b ldr r3, [r7, #0]
8005a68: 681b ldr r3, [r3, #0]
8005a6a: 4619 mov r1, r3
8005a6c: 4610 mov r0, r2
8005a6e: f000 f902 bl 8005c76 <TIM_ITRx_SetConfig>
break;
8005a72: e003 b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8005a74: 2301 movs r3, #1
8005a76: 73fb strb r3, [r7, #15]
break;
8005a78: e000 b.n 8005a7c <HAL_TIM_ConfigClockSource+0x174>
break;
8005a7a: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8005a7c: 687b ldr r3, [r7, #4]
8005a7e: 2201 movs r2, #1
8005a80: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005a84: 687b ldr r3, [r7, #4]
8005a86: 2200 movs r2, #0
8005a88: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8005a8c: 7bfb ldrb r3, [r7, #15]
}
8005a8e: 4618 mov r0, r3
8005a90: 3710 adds r7, #16
8005a92: 46bd mov sp, r7
8005a94: bd80 pop {r7, pc}
08005a96 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8005a96: b480 push {r7}
8005a98: b083 sub sp, #12
8005a9a: af00 add r7, sp, #0
8005a9c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8005a9e: bf00 nop
8005aa0: 370c adds r7, #12
8005aa2: 46bd mov sp, r7
8005aa4: bc80 pop {r7}
8005aa6: 4770 bx lr
08005aa8 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8005aa8: b480 push {r7}
8005aaa: b083 sub sp, #12
8005aac: af00 add r7, sp, #0
8005aae: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8005ab0: bf00 nop
8005ab2: 370c adds r7, #12
8005ab4: 46bd mov sp, r7
8005ab6: bc80 pop {r7}
8005ab8: 4770 bx lr
08005aba <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8005aba: b480 push {r7}
8005abc: b083 sub sp, #12
8005abe: af00 add r7, sp, #0
8005ac0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8005ac2: bf00 nop
8005ac4: 370c adds r7, #12
8005ac6: 46bd mov sp, r7
8005ac8: bc80 pop {r7}
8005aca: 4770 bx lr
08005acc <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8005acc: b480 push {r7}
8005ace: b083 sub sp, #12
8005ad0: af00 add r7, sp, #0
8005ad2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8005ad4: bf00 nop
8005ad6: 370c adds r7, #12
8005ad8: 46bd mov sp, r7
8005ada: bc80 pop {r7}
8005adc: 4770 bx lr
...
08005ae0 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8005ae0: b480 push {r7}
8005ae2: b085 sub sp, #20
8005ae4: af00 add r7, sp, #0
8005ae6: 6078 str r0, [r7, #4]
8005ae8: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8005aea: 687b ldr r3, [r7, #4]
8005aec: 681b ldr r3, [r3, #0]
8005aee: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8005af0: 687b ldr r3, [r7, #4]
8005af2: 4a2f ldr r2, [pc, #188] @ (8005bb0 <TIM_Base_SetConfig+0xd0>)
8005af4: 4293 cmp r3, r2
8005af6: d00b beq.n 8005b10 <TIM_Base_SetConfig+0x30>
8005af8: 687b ldr r3, [r7, #4]
8005afa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005afe: d007 beq.n 8005b10 <TIM_Base_SetConfig+0x30>
8005b00: 687b ldr r3, [r7, #4]
8005b02: 4a2c ldr r2, [pc, #176] @ (8005bb4 <TIM_Base_SetConfig+0xd4>)
8005b04: 4293 cmp r3, r2
8005b06: d003 beq.n 8005b10 <TIM_Base_SetConfig+0x30>
8005b08: 687b ldr r3, [r7, #4]
8005b0a: 4a2b ldr r2, [pc, #172] @ (8005bb8 <TIM_Base_SetConfig+0xd8>)
8005b0c: 4293 cmp r3, r2
8005b0e: d108 bne.n 8005b22 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8005b10: 68fb ldr r3, [r7, #12]
8005b12: f023 0370 bic.w r3, r3, #112 @ 0x70
8005b16: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8005b18: 683b ldr r3, [r7, #0]
8005b1a: 685b ldr r3, [r3, #4]
8005b1c: 68fa ldr r2, [r7, #12]
8005b1e: 4313 orrs r3, r2
8005b20: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8005b22: 687b ldr r3, [r7, #4]
8005b24: 4a22 ldr r2, [pc, #136] @ (8005bb0 <TIM_Base_SetConfig+0xd0>)
8005b26: 4293 cmp r3, r2
8005b28: d00b beq.n 8005b42 <TIM_Base_SetConfig+0x62>
8005b2a: 687b ldr r3, [r7, #4]
8005b2c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005b30: d007 beq.n 8005b42 <TIM_Base_SetConfig+0x62>
8005b32: 687b ldr r3, [r7, #4]
8005b34: 4a1f ldr r2, [pc, #124] @ (8005bb4 <TIM_Base_SetConfig+0xd4>)
8005b36: 4293 cmp r3, r2
8005b38: d003 beq.n 8005b42 <TIM_Base_SetConfig+0x62>
8005b3a: 687b ldr r3, [r7, #4]
8005b3c: 4a1e ldr r2, [pc, #120] @ (8005bb8 <TIM_Base_SetConfig+0xd8>)
8005b3e: 4293 cmp r3, r2
8005b40: d108 bne.n 8005b54 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8005b42: 68fb ldr r3, [r7, #12]
8005b44: f423 7340 bic.w r3, r3, #768 @ 0x300
8005b48: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8005b4a: 683b ldr r3, [r7, #0]
8005b4c: 68db ldr r3, [r3, #12]
8005b4e: 68fa ldr r2, [r7, #12]
8005b50: 4313 orrs r3, r2
8005b52: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8005b54: 68fb ldr r3, [r7, #12]
8005b56: f023 0280 bic.w r2, r3, #128 @ 0x80
8005b5a: 683b ldr r3, [r7, #0]
8005b5c: 695b ldr r3, [r3, #20]
8005b5e: 4313 orrs r3, r2
8005b60: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8005b62: 687b ldr r3, [r7, #4]
8005b64: 68fa ldr r2, [r7, #12]
8005b66: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8005b68: 683b ldr r3, [r7, #0]
8005b6a: 689a ldr r2, [r3, #8]
8005b6c: 687b ldr r3, [r7, #4]
8005b6e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8005b70: 683b ldr r3, [r7, #0]
8005b72: 681a ldr r2, [r3, #0]
8005b74: 687b ldr r3, [r7, #4]
8005b76: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8005b78: 687b ldr r3, [r7, #4]
8005b7a: 4a0d ldr r2, [pc, #52] @ (8005bb0 <TIM_Base_SetConfig+0xd0>)
8005b7c: 4293 cmp r3, r2
8005b7e: d103 bne.n 8005b88 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005b80: 683b ldr r3, [r7, #0]
8005b82: 691a ldr r2, [r3, #16]
8005b84: 687b ldr r3, [r7, #4]
8005b86: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8005b88: 687b ldr r3, [r7, #4]
8005b8a: 2201 movs r2, #1
8005b8c: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8005b8e: 687b ldr r3, [r7, #4]
8005b90: 691b ldr r3, [r3, #16]
8005b92: f003 0301 and.w r3, r3, #1
8005b96: 2b00 cmp r3, #0
8005b98: d005 beq.n 8005ba6 <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8005b9a: 687b ldr r3, [r7, #4]
8005b9c: 691b ldr r3, [r3, #16]
8005b9e: f023 0201 bic.w r2, r3, #1
8005ba2: 687b ldr r3, [r7, #4]
8005ba4: 611a str r2, [r3, #16]
}
}
8005ba6: bf00 nop
8005ba8: 3714 adds r7, #20
8005baa: 46bd mov sp, r7
8005bac: bc80 pop {r7}
8005bae: 4770 bx lr
8005bb0: 40012c00 .word 0x40012c00
8005bb4: 40000400 .word 0x40000400
8005bb8: 40000800 .word 0x40000800
08005bbc <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005bbc: b480 push {r7}
8005bbe: b087 sub sp, #28
8005bc0: af00 add r7, sp, #0
8005bc2: 60f8 str r0, [r7, #12]
8005bc4: 60b9 str r1, [r7, #8]
8005bc6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8005bc8: 68fb ldr r3, [r7, #12]
8005bca: 6a1b ldr r3, [r3, #32]
8005bcc: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8005bce: 68fb ldr r3, [r7, #12]
8005bd0: 6a1b ldr r3, [r3, #32]
8005bd2: f023 0201 bic.w r2, r3, #1
8005bd6: 68fb ldr r3, [r7, #12]
8005bd8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005bda: 68fb ldr r3, [r7, #12]
8005bdc: 699b ldr r3, [r3, #24]
8005bde: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8005be0: 693b ldr r3, [r7, #16]
8005be2: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8005be6: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8005be8: 687b ldr r3, [r7, #4]
8005bea: 011b lsls r3, r3, #4
8005bec: 693a ldr r2, [r7, #16]
8005bee: 4313 orrs r3, r2
8005bf0: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8005bf2: 697b ldr r3, [r7, #20]
8005bf4: f023 030a bic.w r3, r3, #10
8005bf8: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8005bfa: 697a ldr r2, [r7, #20]
8005bfc: 68bb ldr r3, [r7, #8]
8005bfe: 4313 orrs r3, r2
8005c00: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8005c02: 68fb ldr r3, [r7, #12]
8005c04: 693a ldr r2, [r7, #16]
8005c06: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005c08: 68fb ldr r3, [r7, #12]
8005c0a: 697a ldr r2, [r7, #20]
8005c0c: 621a str r2, [r3, #32]
}
8005c0e: bf00 nop
8005c10: 371c adds r7, #28
8005c12: 46bd mov sp, r7
8005c14: bc80 pop {r7}
8005c16: 4770 bx lr
08005c18 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005c18: b480 push {r7}
8005c1a: b087 sub sp, #28
8005c1c: af00 add r7, sp, #0
8005c1e: 60f8 str r0, [r7, #12]
8005c20: 60b9 str r1, [r7, #8]
8005c22: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8005c24: 68fb ldr r3, [r7, #12]
8005c26: 6a1b ldr r3, [r3, #32]
8005c28: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8005c2a: 68fb ldr r3, [r7, #12]
8005c2c: 6a1b ldr r3, [r3, #32]
8005c2e: f023 0210 bic.w r2, r3, #16
8005c32: 68fb ldr r3, [r7, #12]
8005c34: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005c36: 68fb ldr r3, [r7, #12]
8005c38: 699b ldr r3, [r3, #24]
8005c3a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8005c3c: 693b ldr r3, [r7, #16]
8005c3e: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8005c42: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8005c44: 687b ldr r3, [r7, #4]
8005c46: 031b lsls r3, r3, #12
8005c48: 693a ldr r2, [r7, #16]
8005c4a: 4313 orrs r3, r2
8005c4c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8005c4e: 697b ldr r3, [r7, #20]
8005c50: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8005c54: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8005c56: 68bb ldr r3, [r7, #8]
8005c58: 011b lsls r3, r3, #4
8005c5a: 697a ldr r2, [r7, #20]
8005c5c: 4313 orrs r3, r2
8005c5e: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8005c60: 68fb ldr r3, [r7, #12]
8005c62: 693a ldr r2, [r7, #16]
8005c64: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005c66: 68fb ldr r3, [r7, #12]
8005c68: 697a ldr r2, [r7, #20]
8005c6a: 621a str r2, [r3, #32]
}
8005c6c: bf00 nop
8005c6e: 371c adds r7, #28
8005c70: 46bd mov sp, r7
8005c72: bc80 pop {r7}
8005c74: 4770 bx lr
08005c76 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8005c76: b480 push {r7}
8005c78: b085 sub sp, #20
8005c7a: af00 add r7, sp, #0
8005c7c: 6078 str r0, [r7, #4]
8005c7e: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8005c80: 687b ldr r3, [r7, #4]
8005c82: 689b ldr r3, [r3, #8]
8005c84: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8005c86: 68fb ldr r3, [r7, #12]
8005c88: f023 0370 bic.w r3, r3, #112 @ 0x70
8005c8c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8005c8e: 683a ldr r2, [r7, #0]
8005c90: 68fb ldr r3, [r7, #12]
8005c92: 4313 orrs r3, r2
8005c94: f043 0307 orr.w r3, r3, #7
8005c98: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005c9a: 687b ldr r3, [r7, #4]
8005c9c: 68fa ldr r2, [r7, #12]
8005c9e: 609a str r2, [r3, #8]
}
8005ca0: bf00 nop
8005ca2: 3714 adds r7, #20
8005ca4: 46bd mov sp, r7
8005ca6: bc80 pop {r7}
8005ca8: 4770 bx lr
08005caa <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8005caa: b480 push {r7}
8005cac: b087 sub sp, #28
8005cae: af00 add r7, sp, #0
8005cb0: 60f8 str r0, [r7, #12]
8005cb2: 60b9 str r1, [r7, #8]
8005cb4: 607a str r2, [r7, #4]
8005cb6: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8005cb8: 68fb ldr r3, [r7, #12]
8005cba: 689b ldr r3, [r3, #8]
8005cbc: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005cbe: 697b ldr r3, [r7, #20]
8005cc0: f423 437f bic.w r3, r3, #65280 @ 0xff00
8005cc4: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8005cc6: 683b ldr r3, [r7, #0]
8005cc8: 021a lsls r2, r3, #8
8005cca: 687b ldr r3, [r7, #4]
8005ccc: 431a orrs r2, r3
8005cce: 68bb ldr r3, [r7, #8]
8005cd0: 4313 orrs r3, r2
8005cd2: 697a ldr r2, [r7, #20]
8005cd4: 4313 orrs r3, r2
8005cd6: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005cd8: 68fb ldr r3, [r7, #12]
8005cda: 697a ldr r2, [r7, #20]
8005cdc: 609a str r2, [r3, #8]
}
8005cde: bf00 nop
8005ce0: 371c adds r7, #28
8005ce2: 46bd mov sp, r7
8005ce4: bc80 pop {r7}
8005ce6: 4770 bx lr
08005ce8 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8005ce8: b480 push {r7}
8005cea: b085 sub sp, #20
8005cec: af00 add r7, sp, #0
8005cee: 6078 str r0, [r7, #4]
8005cf0: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005cf2: 687b ldr r3, [r7, #4]
8005cf4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005cf8: 2b01 cmp r3, #1
8005cfa: d101 bne.n 8005d00 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8005cfc: 2302 movs r3, #2
8005cfe: e046 b.n 8005d8e <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8005d00: 687b ldr r3, [r7, #4]
8005d02: 2201 movs r2, #1
8005d04: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8005d08: 687b ldr r3, [r7, #4]
8005d0a: 2202 movs r2, #2
8005d0c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005d10: 687b ldr r3, [r7, #4]
8005d12: 681b ldr r3, [r3, #0]
8005d14: 685b ldr r3, [r3, #4]
8005d16: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8005d18: 687b ldr r3, [r7, #4]
8005d1a: 681b ldr r3, [r3, #0]
8005d1c: 689b ldr r3, [r3, #8]
8005d1e: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005d20: 68fb ldr r3, [r7, #12]
8005d22: f023 0370 bic.w r3, r3, #112 @ 0x70
8005d26: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8005d28: 683b ldr r3, [r7, #0]
8005d2a: 681b ldr r3, [r3, #0]
8005d2c: 68fa ldr r2, [r7, #12]
8005d2e: 4313 orrs r3, r2
8005d30: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8005d32: 687b ldr r3, [r7, #4]
8005d34: 681b ldr r3, [r3, #0]
8005d36: 68fa ldr r2, [r7, #12]
8005d38: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005d3a: 687b ldr r3, [r7, #4]
8005d3c: 681b ldr r3, [r3, #0]
8005d3e: 4a16 ldr r2, [pc, #88] @ (8005d98 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8005d40: 4293 cmp r3, r2
8005d42: d00e beq.n 8005d62 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8005d44: 687b ldr r3, [r7, #4]
8005d46: 681b ldr r3, [r3, #0]
8005d48: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005d4c: d009 beq.n 8005d62 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8005d4e: 687b ldr r3, [r7, #4]
8005d50: 681b ldr r3, [r3, #0]
8005d52: 4a12 ldr r2, [pc, #72] @ (8005d9c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8005d54: 4293 cmp r3, r2
8005d56: d004 beq.n 8005d62 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8005d58: 687b ldr r3, [r7, #4]
8005d5a: 681b ldr r3, [r3, #0]
8005d5c: 4a10 ldr r2, [pc, #64] @ (8005da0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8005d5e: 4293 cmp r3, r2
8005d60: d10c bne.n 8005d7c <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005d62: 68bb ldr r3, [r7, #8]
8005d64: f023 0380 bic.w r3, r3, #128 @ 0x80
8005d68: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005d6a: 683b ldr r3, [r7, #0]
8005d6c: 685b ldr r3, [r3, #4]
8005d6e: 68ba ldr r2, [r7, #8]
8005d70: 4313 orrs r3, r2
8005d72: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005d74: 687b ldr r3, [r7, #4]
8005d76: 681b ldr r3, [r3, #0]
8005d78: 68ba ldr r2, [r7, #8]
8005d7a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005d7c: 687b ldr r3, [r7, #4]
8005d7e: 2201 movs r2, #1
8005d80: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005d84: 687b ldr r3, [r7, #4]
8005d86: 2200 movs r2, #0
8005d88: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005d8c: 2300 movs r3, #0
}
8005d8e: 4618 mov r0, r3
8005d90: 3714 adds r7, #20
8005d92: 46bd mov sp, r7
8005d94: bc80 pop {r7}
8005d96: 4770 bx lr
8005d98: 40012c00 .word 0x40012c00
8005d9c: 40000400 .word 0x40000400
8005da0: 40000800 .word 0x40000800
08005da4 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8005da4: b480 push {r7}
8005da6: b083 sub sp, #12
8005da8: af00 add r7, sp, #0
8005daa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8005dac: bf00 nop
8005dae: 370c adds r7, #12
8005db0: 46bd mov sp, r7
8005db2: bc80 pop {r7}
8005db4: 4770 bx lr
08005db6 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8005db6: b480 push {r7}
8005db8: b083 sub sp, #12
8005dba: af00 add r7, sp, #0
8005dbc: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8005dbe: bf00 nop
8005dc0: 370c adds r7, #12
8005dc2: 46bd mov sp, r7
8005dc4: bc80 pop {r7}
8005dc6: 4770 bx lr
08005dc8 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005dc8: b580 push {r7, lr}
8005dca: b082 sub sp, #8
8005dcc: af00 add r7, sp, #0
8005dce: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005dd0: 687b ldr r3, [r7, #4]
8005dd2: 2b00 cmp r3, #0
8005dd4: d101 bne.n 8005dda <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8005dd6: 2301 movs r3, #1
8005dd8: e042 b.n 8005e60 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
8005dda: 687b ldr r3, [r7, #4]
8005ddc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005de0: b2db uxtb r3, r3
8005de2: 2b00 cmp r3, #0
8005de4: d106 bne.n 8005df4 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8005de6: 687b ldr r3, [r7, #4]
8005de8: 2200 movs r2, #0
8005dea: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005dee: 6878 ldr r0, [r7, #4]
8005df0: f7fd f85e bl 8002eb0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8005df4: 687b ldr r3, [r7, #4]
8005df6: 2224 movs r2, #36 @ 0x24
8005df8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8005dfc: 687b ldr r3, [r7, #4]
8005dfe: 681b ldr r3, [r3, #0]
8005e00: 68da ldr r2, [r3, #12]
8005e02: 687b ldr r3, [r7, #4]
8005e04: 681b ldr r3, [r3, #0]
8005e06: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8005e0a: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8005e0c: 6878 ldr r0, [r7, #4]
8005e0e: f000 fd63 bl 80068d8 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005e12: 687b ldr r3, [r7, #4]
8005e14: 681b ldr r3, [r3, #0]
8005e16: 691a ldr r2, [r3, #16]
8005e18: 687b ldr r3, [r7, #4]
8005e1a: 681b ldr r3, [r3, #0]
8005e1c: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005e20: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005e22: 687b ldr r3, [r7, #4]
8005e24: 681b ldr r3, [r3, #0]
8005e26: 695a ldr r2, [r3, #20]
8005e28: 687b ldr r3, [r7, #4]
8005e2a: 681b ldr r3, [r3, #0]
8005e2c: f022 022a bic.w r2, r2, #42 @ 0x2a
8005e30: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8005e32: 687b ldr r3, [r7, #4]
8005e34: 681b ldr r3, [r3, #0]
8005e36: 68da ldr r2, [r3, #12]
8005e38: 687b ldr r3, [r7, #4]
8005e3a: 681b ldr r3, [r3, #0]
8005e3c: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8005e40: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005e42: 687b ldr r3, [r7, #4]
8005e44: 2200 movs r2, #0
8005e46: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
8005e48: 687b ldr r3, [r7, #4]
8005e4a: 2220 movs r2, #32
8005e4c: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8005e50: 687b ldr r3, [r7, #4]
8005e52: 2220 movs r2, #32
8005e54: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005e58: 687b ldr r3, [r7, #4]
8005e5a: 2200 movs r2, #0
8005e5c: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8005e5e: 2300 movs r3, #0
}
8005e60: 4618 mov r0, r3
8005e62: 3708 adds r7, #8
8005e64: 46bd mov sp, r7
8005e66: bd80 pop {r7, pc}
08005e68 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8005e68: b580 push {r7, lr}
8005e6a: b08a sub sp, #40 @ 0x28
8005e6c: af02 add r7, sp, #8
8005e6e: 60f8 str r0, [r7, #12]
8005e70: 60b9 str r1, [r7, #8]
8005e72: 603b str r3, [r7, #0]
8005e74: 4613 mov r3, r2
8005e76: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8005e78: 2300 movs r3, #0
8005e7a: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8005e7c: 68fb ldr r3, [r7, #12]
8005e7e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005e82: b2db uxtb r3, r3
8005e84: 2b20 cmp r3, #32
8005e86: d175 bne.n 8005f74 <HAL_UART_Transmit+0x10c>
{
if ((pData == NULL) || (Size == 0U))
8005e88: 68bb ldr r3, [r7, #8]
8005e8a: 2b00 cmp r3, #0
8005e8c: d002 beq.n 8005e94 <HAL_UART_Transmit+0x2c>
8005e8e: 88fb ldrh r3, [r7, #6]
8005e90: 2b00 cmp r3, #0
8005e92: d101 bne.n 8005e98 <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
8005e94: 2301 movs r3, #1
8005e96: e06e b.n 8005f76 <HAL_UART_Transmit+0x10e>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005e98: 68fb ldr r3, [r7, #12]
8005e9a: 2200 movs r2, #0
8005e9c: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_BUSY_TX;
8005e9e: 68fb ldr r3, [r7, #12]
8005ea0: 2221 movs r2, #33 @ 0x21
8005ea2: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8005ea6: f7fd f8d5 bl 8003054 <HAL_GetTick>
8005eaa: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8005eac: 68fb ldr r3, [r7, #12]
8005eae: 88fa ldrh r2, [r7, #6]
8005eb0: 849a strh r2, [r3, #36] @ 0x24
huart->TxXferCount = Size;
8005eb2: 68fb ldr r3, [r7, #12]
8005eb4: 88fa ldrh r2, [r7, #6]
8005eb6: 84da strh r2, [r3, #38] @ 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005eb8: 68fb ldr r3, [r7, #12]
8005eba: 689b ldr r3, [r3, #8]
8005ebc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005ec0: d108 bne.n 8005ed4 <HAL_UART_Transmit+0x6c>
8005ec2: 68fb ldr r3, [r7, #12]
8005ec4: 691b ldr r3, [r3, #16]
8005ec6: 2b00 cmp r3, #0
8005ec8: d104 bne.n 8005ed4 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
8005eca: 2300 movs r3, #0
8005ecc: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8005ece: 68bb ldr r3, [r7, #8]
8005ed0: 61bb str r3, [r7, #24]
8005ed2: e003 b.n 8005edc <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8005ed4: 68bb ldr r3, [r7, #8]
8005ed6: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8005ed8: 2300 movs r3, #0
8005eda: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8005edc: e02e b.n 8005f3c <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8005ede: 683b ldr r3, [r7, #0]
8005ee0: 9300 str r3, [sp, #0]
8005ee2: 697b ldr r3, [r7, #20]
8005ee4: 2200 movs r2, #0
8005ee6: 2180 movs r1, #128 @ 0x80
8005ee8: 68f8 ldr r0, [r7, #12]
8005eea: f000 fb01 bl 80064f0 <UART_WaitOnFlagUntilTimeout>
8005eee: 4603 mov r3, r0
8005ef0: 2b00 cmp r3, #0
8005ef2: d005 beq.n 8005f00 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8005ef4: 68fb ldr r3, [r7, #12]
8005ef6: 2220 movs r2, #32
8005ef8: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005efc: 2303 movs r3, #3
8005efe: e03a b.n 8005f76 <HAL_UART_Transmit+0x10e>
}
if (pdata8bits == NULL)
8005f00: 69fb ldr r3, [r7, #28]
8005f02: 2b00 cmp r3, #0
8005f04: d10b bne.n 8005f1e <HAL_UART_Transmit+0xb6>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8005f06: 69bb ldr r3, [r7, #24]
8005f08: 881b ldrh r3, [r3, #0]
8005f0a: 461a mov r2, r3
8005f0c: 68fb ldr r3, [r7, #12]
8005f0e: 681b ldr r3, [r3, #0]
8005f10: f3c2 0208 ubfx r2, r2, #0, #9
8005f14: 605a str r2, [r3, #4]
pdata16bits++;
8005f16: 69bb ldr r3, [r7, #24]
8005f18: 3302 adds r3, #2
8005f1a: 61bb str r3, [r7, #24]
8005f1c: e007 b.n 8005f2e <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8005f1e: 69fb ldr r3, [r7, #28]
8005f20: 781a ldrb r2, [r3, #0]
8005f22: 68fb ldr r3, [r7, #12]
8005f24: 681b ldr r3, [r3, #0]
8005f26: 605a str r2, [r3, #4]
pdata8bits++;
8005f28: 69fb ldr r3, [r7, #28]
8005f2a: 3301 adds r3, #1
8005f2c: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8005f2e: 68fb ldr r3, [r7, #12]
8005f30: 8cdb ldrh r3, [r3, #38] @ 0x26
8005f32: b29b uxth r3, r3
8005f34: 3b01 subs r3, #1
8005f36: b29a uxth r2, r3
8005f38: 68fb ldr r3, [r7, #12]
8005f3a: 84da strh r2, [r3, #38] @ 0x26
while (huart->TxXferCount > 0U)
8005f3c: 68fb ldr r3, [r7, #12]
8005f3e: 8cdb ldrh r3, [r3, #38] @ 0x26
8005f40: b29b uxth r3, r3
8005f42: 2b00 cmp r3, #0
8005f44: d1cb bne.n 8005ede <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8005f46: 683b ldr r3, [r7, #0]
8005f48: 9300 str r3, [sp, #0]
8005f4a: 697b ldr r3, [r7, #20]
8005f4c: 2200 movs r2, #0
8005f4e: 2140 movs r1, #64 @ 0x40
8005f50: 68f8 ldr r0, [r7, #12]
8005f52: f000 facd bl 80064f0 <UART_WaitOnFlagUntilTimeout>
8005f56: 4603 mov r3, r0
8005f58: 2b00 cmp r3, #0
8005f5a: d005 beq.n 8005f68 <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8005f5c: 68fb ldr r3, [r7, #12]
8005f5e: 2220 movs r2, #32
8005f60: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005f64: 2303 movs r3, #3
8005f66: e006 b.n 8005f76 <HAL_UART_Transmit+0x10e>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8005f68: 68fb ldr r3, [r7, #12]
8005f6a: 2220 movs r2, #32
8005f6c: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_OK;
8005f70: 2300 movs r3, #0
8005f72: e000 b.n 8005f76 <HAL_UART_Transmit+0x10e>
}
else
{
return HAL_BUSY;
8005f74: 2302 movs r3, #2
}
}
8005f76: 4618 mov r0, r3
8005f78: 3720 adds r7, #32
8005f7a: 46bd mov sp, r7
8005f7c: bd80 pop {r7, pc}
...
08005f80 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8005f80: b580 push {r7, lr}
8005f82: b0ba sub sp, #232 @ 0xe8
8005f84: af00 add r7, sp, #0
8005f86: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
8005f88: 687b ldr r3, [r7, #4]
8005f8a: 681b ldr r3, [r3, #0]
8005f8c: 681b ldr r3, [r3, #0]
8005f8e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8005f92: 687b ldr r3, [r7, #4]
8005f94: 681b ldr r3, [r3, #0]
8005f96: 68db ldr r3, [r3, #12]
8005f98: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8005f9c: 687b ldr r3, [r7, #4]
8005f9e: 681b ldr r3, [r3, #0]
8005fa0: 695b ldr r3, [r3, #20]
8005fa2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags = 0x00U;
8005fa6: 2300 movs r3, #0
8005fa8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
uint32_t dmarequest = 0x00U;
8005fac: 2300 movs r3, #0
8005fae: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
8005fb2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005fb6: f003 030f and.w r3, r3, #15
8005fba: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == RESET)
8005fbe: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005fc2: 2b00 cmp r3, #0
8005fc4: d10f bne.n 8005fe6 <HAL_UART_IRQHandler+0x66>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8005fc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005fca: f003 0320 and.w r3, r3, #32
8005fce: 2b00 cmp r3, #0
8005fd0: d009 beq.n 8005fe6 <HAL_UART_IRQHandler+0x66>
8005fd2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005fd6: f003 0320 and.w r3, r3, #32
8005fda: 2b00 cmp r3, #0
8005fdc: d003 beq.n 8005fe6 <HAL_UART_IRQHandler+0x66>
{
UART_Receive_IT(huart);
8005fde: 6878 ldr r0, [r7, #4]
8005fe0: f000 fbbc bl 800675c <UART_Receive_IT>
return;
8005fe4: e25b b.n 800649e <HAL_UART_IRQHandler+0x51e>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
8005fe6: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005fea: 2b00 cmp r3, #0
8005fec: f000 80de beq.w 80061ac <HAL_UART_IRQHandler+0x22c>
8005ff0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005ff4: f003 0301 and.w r3, r3, #1
8005ff8: 2b00 cmp r3, #0
8005ffa: d106 bne.n 800600a <HAL_UART_IRQHandler+0x8a>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8005ffc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006000: f403 7390 and.w r3, r3, #288 @ 0x120
8006004: 2b00 cmp r3, #0
8006006: f000 80d1 beq.w 80061ac <HAL_UART_IRQHandler+0x22c>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
800600a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800600e: f003 0301 and.w r3, r3, #1
8006012: 2b00 cmp r3, #0
8006014: d00b beq.n 800602e <HAL_UART_IRQHandler+0xae>
8006016: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800601a: f403 7380 and.w r3, r3, #256 @ 0x100
800601e: 2b00 cmp r3, #0
8006020: d005 beq.n 800602e <HAL_UART_IRQHandler+0xae>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
8006022: 687b ldr r3, [r7, #4]
8006024: 6c5b ldr r3, [r3, #68] @ 0x44
8006026: f043 0201 orr.w r2, r3, #1
800602a: 687b ldr r3, [r7, #4]
800602c: 645a str r2, [r3, #68] @ 0x44
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
800602e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006032: f003 0304 and.w r3, r3, #4
8006036: 2b00 cmp r3, #0
8006038: d00b beq.n 8006052 <HAL_UART_IRQHandler+0xd2>
800603a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800603e: f003 0301 and.w r3, r3, #1
8006042: 2b00 cmp r3, #0
8006044: d005 beq.n 8006052 <HAL_UART_IRQHandler+0xd2>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
8006046: 687b ldr r3, [r7, #4]
8006048: 6c5b ldr r3, [r3, #68] @ 0x44
800604a: f043 0202 orr.w r2, r3, #2
800604e: 687b ldr r3, [r7, #4]
8006050: 645a str r2, [r3, #68] @ 0x44
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8006052: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006056: f003 0302 and.w r3, r3, #2
800605a: 2b00 cmp r3, #0
800605c: d00b beq.n 8006076 <HAL_UART_IRQHandler+0xf6>
800605e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006062: f003 0301 and.w r3, r3, #1
8006066: 2b00 cmp r3, #0
8006068: d005 beq.n 8006076 <HAL_UART_IRQHandler+0xf6>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
800606a: 687b ldr r3, [r7, #4]
800606c: 6c5b ldr r3, [r3, #68] @ 0x44
800606e: f043 0204 orr.w r2, r3, #4
8006072: 687b ldr r3, [r7, #4]
8006074: 645a str r2, [r3, #68] @ 0x44
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
8006076: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800607a: f003 0308 and.w r3, r3, #8
800607e: 2b00 cmp r3, #0
8006080: d011 beq.n 80060a6 <HAL_UART_IRQHandler+0x126>
8006082: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006086: f003 0320 and.w r3, r3, #32
800608a: 2b00 cmp r3, #0
800608c: d105 bne.n 800609a <HAL_UART_IRQHandler+0x11a>
|| ((cr3its & USART_CR3_EIE) != RESET)))
800608e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006092: f003 0301 and.w r3, r3, #1
8006096: 2b00 cmp r3, #0
8006098: d005 beq.n 80060a6 <HAL_UART_IRQHandler+0x126>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
800609a: 687b ldr r3, [r7, #4]
800609c: 6c5b ldr r3, [r3, #68] @ 0x44
800609e: f043 0208 orr.w r2, r3, #8
80060a2: 687b ldr r3, [r7, #4]
80060a4: 645a str r2, [r3, #68] @ 0x44
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
80060a6: 687b ldr r3, [r7, #4]
80060a8: 6c5b ldr r3, [r3, #68] @ 0x44
80060aa: 2b00 cmp r3, #0
80060ac: f000 81f2 beq.w 8006494 <HAL_UART_IRQHandler+0x514>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
80060b0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80060b4: f003 0320 and.w r3, r3, #32
80060b8: 2b00 cmp r3, #0
80060ba: d008 beq.n 80060ce <HAL_UART_IRQHandler+0x14e>
80060bc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80060c0: f003 0320 and.w r3, r3, #32
80060c4: 2b00 cmp r3, #0
80060c6: d002 beq.n 80060ce <HAL_UART_IRQHandler+0x14e>
{
UART_Receive_IT(huart);
80060c8: 6878 ldr r0, [r7, #4]
80060ca: f000 fb47 bl 800675c <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
80060ce: 687b ldr r3, [r7, #4]
80060d0: 681b ldr r3, [r3, #0]
80060d2: 695b ldr r3, [r3, #20]
80060d4: f003 0340 and.w r3, r3, #64 @ 0x40
80060d8: 2b00 cmp r3, #0
80060da: bf14 ite ne
80060dc: 2301 movne r3, #1
80060de: 2300 moveq r3, #0
80060e0: b2db uxtb r3, r3
80060e2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
80060e6: 687b ldr r3, [r7, #4]
80060e8: 6c5b ldr r3, [r3, #68] @ 0x44
80060ea: f003 0308 and.w r3, r3, #8
80060ee: 2b00 cmp r3, #0
80060f0: d103 bne.n 80060fa <HAL_UART_IRQHandler+0x17a>
80060f2: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
80060f6: 2b00 cmp r3, #0
80060f8: d04f beq.n 800619a <HAL_UART_IRQHandler+0x21a>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
80060fa: 6878 ldr r0, [r7, #4]
80060fc: f000 fa51 bl 80065a2 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006100: 687b ldr r3, [r7, #4]
8006102: 681b ldr r3, [r3, #0]
8006104: 695b ldr r3, [r3, #20]
8006106: f003 0340 and.w r3, r3, #64 @ 0x40
800610a: 2b00 cmp r3, #0
800610c: d041 beq.n 8006192 <HAL_UART_IRQHandler+0x212>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800610e: 687b ldr r3, [r7, #4]
8006110: 681b ldr r3, [r3, #0]
8006112: 3314 adds r3, #20
8006114: f8c7 309c str.w r3, [r7, #156] @ 0x9c
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006118: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800611c: e853 3f00 ldrex r3, [r3]
8006120: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8006124: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8006128: f023 0340 bic.w r3, r3, #64 @ 0x40
800612c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8006130: 687b ldr r3, [r7, #4]
8006132: 681b ldr r3, [r3, #0]
8006134: 3314 adds r3, #20
8006136: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
800613a: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
800613e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006142: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
8006146: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
800614a: e841 2300 strex r3, r2, [r1]
800614e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8006152: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8006156: 2b00 cmp r3, #0
8006158: d1d9 bne.n 800610e <HAL_UART_IRQHandler+0x18e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
800615a: 687b ldr r3, [r7, #4]
800615c: 6bdb ldr r3, [r3, #60] @ 0x3c
800615e: 2b00 cmp r3, #0
8006160: d013 beq.n 800618a <HAL_UART_IRQHandler+0x20a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8006162: 687b ldr r3, [r7, #4]
8006164: 6bdb ldr r3, [r3, #60] @ 0x3c
8006166: 4a7e ldr r2, [pc, #504] @ (8006360 <HAL_UART_IRQHandler+0x3e0>)
8006168: 635a str r2, [r3, #52] @ 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
800616a: 687b ldr r3, [r7, #4]
800616c: 6bdb ldr r3, [r3, #60] @ 0x3c
800616e: 4618 mov r0, r3
8006170: f7fd faf8 bl 8003764 <HAL_DMA_Abort_IT>
8006174: 4603 mov r3, r0
8006176: 2b00 cmp r3, #0
8006178: d016 beq.n 80061a8 <HAL_UART_IRQHandler+0x228>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
800617a: 687b ldr r3, [r7, #4]
800617c: 6bdb ldr r3, [r3, #60] @ 0x3c
800617e: 6b5b ldr r3, [r3, #52] @ 0x34
8006180: 687a ldr r2, [r7, #4]
8006182: 6bd2 ldr r2, [r2, #60] @ 0x3c
8006184: 4610 mov r0, r2
8006186: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006188: e00e b.n 80061a8 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800618a: 6878 ldr r0, [r7, #4]
800618c: f000 f99c bl 80064c8 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006190: e00a b.n 80061a8 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006192: 6878 ldr r0, [r7, #4]
8006194: f000 f998 bl 80064c8 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006198: e006 b.n 80061a8 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800619a: 6878 ldr r0, [r7, #4]
800619c: f000 f994 bl 80064c8 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80061a0: 687b ldr r3, [r7, #4]
80061a2: 2200 movs r2, #0
80061a4: 645a str r2, [r3, #68] @ 0x44
}
}
return;
80061a6: e175 b.n 8006494 <HAL_UART_IRQHandler+0x514>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80061a8: bf00 nop
return;
80061aa: e173 b.n 8006494 <HAL_UART_IRQHandler+0x514>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80061ac: 687b ldr r3, [r7, #4]
80061ae: 6b1b ldr r3, [r3, #48] @ 0x30
80061b0: 2b01 cmp r3, #1
80061b2: f040 814f bne.w 8006454 <HAL_UART_IRQHandler+0x4d4>
&& ((isrflags & USART_SR_IDLE) != 0U)
80061b6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80061ba: f003 0310 and.w r3, r3, #16
80061be: 2b00 cmp r3, #0
80061c0: f000 8148 beq.w 8006454 <HAL_UART_IRQHandler+0x4d4>
&& ((cr1its & USART_SR_IDLE) != 0U))
80061c4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80061c8: f003 0310 and.w r3, r3, #16
80061cc: 2b00 cmp r3, #0
80061ce: f000 8141 beq.w 8006454 <HAL_UART_IRQHandler+0x4d4>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
80061d2: 2300 movs r3, #0
80061d4: 60bb str r3, [r7, #8]
80061d6: 687b ldr r3, [r7, #4]
80061d8: 681b ldr r3, [r3, #0]
80061da: 681b ldr r3, [r3, #0]
80061dc: 60bb str r3, [r7, #8]
80061de: 687b ldr r3, [r7, #4]
80061e0: 681b ldr r3, [r3, #0]
80061e2: 685b ldr r3, [r3, #4]
80061e4: 60bb str r3, [r7, #8]
80061e6: 68bb ldr r3, [r7, #8]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80061e8: 687b ldr r3, [r7, #4]
80061ea: 681b ldr r3, [r3, #0]
80061ec: 695b ldr r3, [r3, #20]
80061ee: f003 0340 and.w r3, r3, #64 @ 0x40
80061f2: 2b00 cmp r3, #0
80061f4: f000 80b6 beq.w 8006364 <HAL_UART_IRQHandler+0x3e4>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
80061f8: 687b ldr r3, [r7, #4]
80061fa: 6bdb ldr r3, [r3, #60] @ 0x3c
80061fc: 681b ldr r3, [r3, #0]
80061fe: 685b ldr r3, [r3, #4]
8006200: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
8006204: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8006208: 2b00 cmp r3, #0
800620a: f000 8145 beq.w 8006498 <HAL_UART_IRQHandler+0x518>
&& (nb_remaining_rx_data < huart->RxXferSize))
800620e: 687b ldr r3, [r7, #4]
8006210: 8d9b ldrh r3, [r3, #44] @ 0x2c
8006212: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006216: 429a cmp r2, r3
8006218: f080 813e bcs.w 8006498 <HAL_UART_IRQHandler+0x518>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
800621c: 687b ldr r3, [r7, #4]
800621e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006222: 85da strh r2, [r3, #46] @ 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8006224: 687b ldr r3, [r7, #4]
8006226: 6bdb ldr r3, [r3, #60] @ 0x3c
8006228: 699b ldr r3, [r3, #24]
800622a: 2b20 cmp r3, #32
800622c: f000 8088 beq.w 8006340 <HAL_UART_IRQHandler+0x3c0>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006230: 687b ldr r3, [r7, #4]
8006232: 681b ldr r3, [r3, #0]
8006234: 330c adds r3, #12
8006236: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800623a: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800623e: e853 3f00 ldrex r3, [r3]
8006242: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8006246: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800624a: f423 7380 bic.w r3, r3, #256 @ 0x100
800624e: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8006252: 687b ldr r3, [r7, #4]
8006254: 681b ldr r3, [r3, #0]
8006256: 330c adds r3, #12
8006258: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
800625c: f8c7 2094 str.w r2, [r7, #148] @ 0x94
8006260: f8c7 3090 str.w r3, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006264: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8006268: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
800626c: e841 2300 strex r3, r2, [r1]
8006270: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
8006274: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006278: 2b00 cmp r3, #0
800627a: d1d9 bne.n 8006230 <HAL_UART_IRQHandler+0x2b0>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800627c: 687b ldr r3, [r7, #4]
800627e: 681b ldr r3, [r3, #0]
8006280: 3314 adds r3, #20
8006282: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006284: 6f7b ldr r3, [r7, #116] @ 0x74
8006286: e853 3f00 ldrex r3, [r3]
800628a: 673b str r3, [r7, #112] @ 0x70
return(result);
800628c: 6f3b ldr r3, [r7, #112] @ 0x70
800628e: f023 0301 bic.w r3, r3, #1
8006292: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8006296: 687b ldr r3, [r7, #4]
8006298: 681b ldr r3, [r3, #0]
800629a: 3314 adds r3, #20
800629c: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
80062a0: f8c7 2080 str.w r2, [r7, #128] @ 0x80
80062a4: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80062a6: 6ff9 ldr r1, [r7, #124] @ 0x7c
80062a8: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
80062ac: e841 2300 strex r3, r2, [r1]
80062b0: 67bb str r3, [r7, #120] @ 0x78
return(result);
80062b2: 6fbb ldr r3, [r7, #120] @ 0x78
80062b4: 2b00 cmp r3, #0
80062b6: d1e1 bne.n 800627c <HAL_UART_IRQHandler+0x2fc>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80062b8: 687b ldr r3, [r7, #4]
80062ba: 681b ldr r3, [r3, #0]
80062bc: 3314 adds r3, #20
80062be: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80062c0: 6e3b ldr r3, [r7, #96] @ 0x60
80062c2: e853 3f00 ldrex r3, [r3]
80062c6: 65fb str r3, [r7, #92] @ 0x5c
return(result);
80062c8: 6dfb ldr r3, [r7, #92] @ 0x5c
80062ca: f023 0340 bic.w r3, r3, #64 @ 0x40
80062ce: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
80062d2: 687b ldr r3, [r7, #4]
80062d4: 681b ldr r3, [r3, #0]
80062d6: 3314 adds r3, #20
80062d8: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
80062dc: 66fa str r2, [r7, #108] @ 0x6c
80062de: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80062e0: 6eb9 ldr r1, [r7, #104] @ 0x68
80062e2: 6efa ldr r2, [r7, #108] @ 0x6c
80062e4: e841 2300 strex r3, r2, [r1]
80062e8: 667b str r3, [r7, #100] @ 0x64
return(result);
80062ea: 6e7b ldr r3, [r7, #100] @ 0x64
80062ec: 2b00 cmp r3, #0
80062ee: d1e3 bne.n 80062b8 <HAL_UART_IRQHandler+0x338>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80062f0: 687b ldr r3, [r7, #4]
80062f2: 2220 movs r2, #32
80062f4: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80062f8: 687b ldr r3, [r7, #4]
80062fa: 2200 movs r2, #0
80062fc: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80062fe: 687b ldr r3, [r7, #4]
8006300: 681b ldr r3, [r3, #0]
8006302: 330c adds r3, #12
8006304: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006306: 6cfb ldr r3, [r7, #76] @ 0x4c
8006308: e853 3f00 ldrex r3, [r3]
800630c: 64bb str r3, [r7, #72] @ 0x48
return(result);
800630e: 6cbb ldr r3, [r7, #72] @ 0x48
8006310: f023 0310 bic.w r3, r3, #16
8006314: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8006318: 687b ldr r3, [r7, #4]
800631a: 681b ldr r3, [r3, #0]
800631c: 330c adds r3, #12
800631e: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
8006322: 65ba str r2, [r7, #88] @ 0x58
8006324: 657b str r3, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006326: 6d79 ldr r1, [r7, #84] @ 0x54
8006328: 6dba ldr r2, [r7, #88] @ 0x58
800632a: e841 2300 strex r3, r2, [r1]
800632e: 653b str r3, [r7, #80] @ 0x50
return(result);
8006330: 6d3b ldr r3, [r7, #80] @ 0x50
8006332: 2b00 cmp r3, #0
8006334: d1e3 bne.n 80062fe <HAL_UART_IRQHandler+0x37e>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8006336: 687b ldr r3, [r7, #4]
8006338: 6bdb ldr r3, [r3, #60] @ 0x3c
800633a: 4618 mov r0, r3
800633c: f7fd f9d7 bl 80036ee <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006340: 687b ldr r3, [r7, #4]
8006342: 2202 movs r2, #2
8006344: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8006346: 687b ldr r3, [r7, #4]
8006348: 8d9a ldrh r2, [r3, #44] @ 0x2c
800634a: 687b ldr r3, [r7, #4]
800634c: 8ddb ldrh r3, [r3, #46] @ 0x2e
800634e: b29b uxth r3, r3
8006350: 1ad3 subs r3, r2, r3
8006352: b29b uxth r3, r3
8006354: 4619 mov r1, r3
8006356: 6878 ldr r0, [r7, #4]
8006358: f000 f8bf bl 80064da <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
800635c: e09c b.n 8006498 <HAL_UART_IRQHandler+0x518>
800635e: bf00 nop
8006360: 08006667 .word 0x08006667
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8006364: 687b ldr r3, [r7, #4]
8006366: 8d9a ldrh r2, [r3, #44] @ 0x2c
8006368: 687b ldr r3, [r7, #4]
800636a: 8ddb ldrh r3, [r3, #46] @ 0x2e
800636c: b29b uxth r3, r3
800636e: 1ad3 subs r3, r2, r3
8006370: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8006374: 687b ldr r3, [r7, #4]
8006376: 8ddb ldrh r3, [r3, #46] @ 0x2e
8006378: b29b uxth r3, r3
800637a: 2b00 cmp r3, #0
800637c: f000 808e beq.w 800649c <HAL_UART_IRQHandler+0x51c>
&& (nb_rx_data > 0U))
8006380: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006384: 2b00 cmp r3, #0
8006386: f000 8089 beq.w 800649c <HAL_UART_IRQHandler+0x51c>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800638a: 687b ldr r3, [r7, #4]
800638c: 681b ldr r3, [r3, #0]
800638e: 330c adds r3, #12
8006390: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006392: 6bbb ldr r3, [r7, #56] @ 0x38
8006394: e853 3f00 ldrex r3, [r3]
8006398: 637b str r3, [r7, #52] @ 0x34
return(result);
800639a: 6b7b ldr r3, [r7, #52] @ 0x34
800639c: f423 7390 bic.w r3, r3, #288 @ 0x120
80063a0: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
80063a4: 687b ldr r3, [r7, #4]
80063a6: 681b ldr r3, [r3, #0]
80063a8: 330c adds r3, #12
80063aa: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
80063ae: 647a str r2, [r7, #68] @ 0x44
80063b0: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80063b2: 6c39 ldr r1, [r7, #64] @ 0x40
80063b4: 6c7a ldr r2, [r7, #68] @ 0x44
80063b6: e841 2300 strex r3, r2, [r1]
80063ba: 63fb str r3, [r7, #60] @ 0x3c
return(result);
80063bc: 6bfb ldr r3, [r7, #60] @ 0x3c
80063be: 2b00 cmp r3, #0
80063c0: d1e3 bne.n 800638a <HAL_UART_IRQHandler+0x40a>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80063c2: 687b ldr r3, [r7, #4]
80063c4: 681b ldr r3, [r3, #0]
80063c6: 3314 adds r3, #20
80063c8: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80063ca: 6a7b ldr r3, [r7, #36] @ 0x24
80063cc: e853 3f00 ldrex r3, [r3]
80063d0: 623b str r3, [r7, #32]
return(result);
80063d2: 6a3b ldr r3, [r7, #32]
80063d4: f023 0301 bic.w r3, r3, #1
80063d8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
80063dc: 687b ldr r3, [r7, #4]
80063de: 681b ldr r3, [r3, #0]
80063e0: 3314 adds r3, #20
80063e2: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
80063e6: 633a str r2, [r7, #48] @ 0x30
80063e8: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80063ea: 6af9 ldr r1, [r7, #44] @ 0x2c
80063ec: 6b3a ldr r2, [r7, #48] @ 0x30
80063ee: e841 2300 strex r3, r2, [r1]
80063f2: 62bb str r3, [r7, #40] @ 0x28
return(result);
80063f4: 6abb ldr r3, [r7, #40] @ 0x28
80063f6: 2b00 cmp r3, #0
80063f8: d1e3 bne.n 80063c2 <HAL_UART_IRQHandler+0x442>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80063fa: 687b ldr r3, [r7, #4]
80063fc: 2220 movs r2, #32
80063fe: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006402: 687b ldr r3, [r7, #4]
8006404: 2200 movs r2, #0
8006406: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006408: 687b ldr r3, [r7, #4]
800640a: 681b ldr r3, [r3, #0]
800640c: 330c adds r3, #12
800640e: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006410: 693b ldr r3, [r7, #16]
8006412: e853 3f00 ldrex r3, [r3]
8006416: 60fb str r3, [r7, #12]
return(result);
8006418: 68fb ldr r3, [r7, #12]
800641a: f023 0310 bic.w r3, r3, #16
800641e: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8006422: 687b ldr r3, [r7, #4]
8006424: 681b ldr r3, [r3, #0]
8006426: 330c adds r3, #12
8006428: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
800642c: 61fa str r2, [r7, #28]
800642e: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006430: 69b9 ldr r1, [r7, #24]
8006432: 69fa ldr r2, [r7, #28]
8006434: e841 2300 strex r3, r2, [r1]
8006438: 617b str r3, [r7, #20]
return(result);
800643a: 697b ldr r3, [r7, #20]
800643c: 2b00 cmp r3, #0
800643e: d1e3 bne.n 8006408 <HAL_UART_IRQHandler+0x488>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006440: 687b ldr r3, [r7, #4]
8006442: 2202 movs r2, #2
8006444: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8006446: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
800644a: 4619 mov r1, r3
800644c: 6878 ldr r0, [r7, #4]
800644e: f000 f844 bl 80064da <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8006452: e023 b.n 800649c <HAL_UART_IRQHandler+0x51c>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
8006454: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006458: f003 0380 and.w r3, r3, #128 @ 0x80
800645c: 2b00 cmp r3, #0
800645e: d009 beq.n 8006474 <HAL_UART_IRQHandler+0x4f4>
8006460: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006464: f003 0380 and.w r3, r3, #128 @ 0x80
8006468: 2b00 cmp r3, #0
800646a: d003 beq.n 8006474 <HAL_UART_IRQHandler+0x4f4>
{
UART_Transmit_IT(huart);
800646c: 6878 ldr r0, [r7, #4]
800646e: f000 f90e bl 800668e <UART_Transmit_IT>
return;
8006472: e014 b.n 800649e <HAL_UART_IRQHandler+0x51e>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
8006474: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006478: f003 0340 and.w r3, r3, #64 @ 0x40
800647c: 2b00 cmp r3, #0
800647e: d00e beq.n 800649e <HAL_UART_IRQHandler+0x51e>
8006480: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006484: f003 0340 and.w r3, r3, #64 @ 0x40
8006488: 2b00 cmp r3, #0
800648a: d008 beq.n 800649e <HAL_UART_IRQHandler+0x51e>
{
UART_EndTransmit_IT(huart);
800648c: 6878 ldr r0, [r7, #4]
800648e: f000 f94d bl 800672c <UART_EndTransmit_IT>
return;
8006492: e004 b.n 800649e <HAL_UART_IRQHandler+0x51e>
return;
8006494: bf00 nop
8006496: e002 b.n 800649e <HAL_UART_IRQHandler+0x51e>
return;
8006498: bf00 nop
800649a: e000 b.n 800649e <HAL_UART_IRQHandler+0x51e>
return;
800649c: bf00 nop
}
}
800649e: 37e8 adds r7, #232 @ 0xe8
80064a0: 46bd mov sp, r7
80064a2: bd80 pop {r7, pc}
080064a4 <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
80064a4: b480 push {r7}
80064a6: b083 sub sp, #12
80064a8: af00 add r7, sp, #0
80064aa: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
80064ac: bf00 nop
80064ae: 370c adds r7, #12
80064b0: 46bd mov sp, r7
80064b2: bc80 pop {r7}
80064b4: 4770 bx lr
080064b6 <HAL_UART_RxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
80064b6: b480 push {r7}
80064b8: b083 sub sp, #12
80064ba: af00 add r7, sp, #0
80064bc: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
80064be: bf00 nop
80064c0: 370c adds r7, #12
80064c2: 46bd mov sp, r7
80064c4: bc80 pop {r7}
80064c6: 4770 bx lr
080064c8 <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
80064c8: b480 push {r7}
80064ca: b083 sub sp, #12
80064cc: af00 add r7, sp, #0
80064ce: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
80064d0: bf00 nop
80064d2: 370c adds r7, #12
80064d4: 46bd mov sp, r7
80064d6: bc80 pop {r7}
80064d8: 4770 bx lr
080064da <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
80064da: b480 push {r7}
80064dc: b083 sub sp, #12
80064de: af00 add r7, sp, #0
80064e0: 6078 str r0, [r7, #4]
80064e2: 460b mov r3, r1
80064e4: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
80064e6: bf00 nop
80064e8: 370c adds r7, #12
80064ea: 46bd mov sp, r7
80064ec: bc80 pop {r7}
80064ee: 4770 bx lr
080064f0 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80064f0: b580 push {r7, lr}
80064f2: b086 sub sp, #24
80064f4: af00 add r7, sp, #0
80064f6: 60f8 str r0, [r7, #12]
80064f8: 60b9 str r1, [r7, #8]
80064fa: 603b str r3, [r7, #0]
80064fc: 4613 mov r3, r2
80064fe: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8006500: e03b b.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8006502: 6a3b ldr r3, [r7, #32]
8006504: f1b3 3fff cmp.w r3, #4294967295
8006508: d037 beq.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800650a: f7fc fda3 bl 8003054 <HAL_GetTick>
800650e: 4602 mov r2, r0
8006510: 683b ldr r3, [r7, #0]
8006512: 1ad3 subs r3, r2, r3
8006514: 6a3a ldr r2, [r7, #32]
8006516: 429a cmp r2, r3
8006518: d302 bcc.n 8006520 <UART_WaitOnFlagUntilTimeout+0x30>
800651a: 6a3b ldr r3, [r7, #32]
800651c: 2b00 cmp r3, #0
800651e: d101 bne.n 8006524 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8006520: 2303 movs r3, #3
8006522: e03a b.n 800659a <UART_WaitOnFlagUntilTimeout+0xaa>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8006524: 68fb ldr r3, [r7, #12]
8006526: 681b ldr r3, [r3, #0]
8006528: 68db ldr r3, [r3, #12]
800652a: f003 0304 and.w r3, r3, #4
800652e: 2b00 cmp r3, #0
8006530: d023 beq.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
8006532: 68bb ldr r3, [r7, #8]
8006534: 2b80 cmp r3, #128 @ 0x80
8006536: d020 beq.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
8006538: 68bb ldr r3, [r7, #8]
800653a: 2b40 cmp r3, #64 @ 0x40
800653c: d01d beq.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
800653e: 68fb ldr r3, [r7, #12]
8006540: 681b ldr r3, [r3, #0]
8006542: 681b ldr r3, [r3, #0]
8006544: f003 0308 and.w r3, r3, #8
8006548: 2b08 cmp r3, #8
800654a: d116 bne.n 800657a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_OREFLAG(huart);
800654c: 2300 movs r3, #0
800654e: 617b str r3, [r7, #20]
8006550: 68fb ldr r3, [r7, #12]
8006552: 681b ldr r3, [r3, #0]
8006554: 681b ldr r3, [r3, #0]
8006556: 617b str r3, [r7, #20]
8006558: 68fb ldr r3, [r7, #12]
800655a: 681b ldr r3, [r3, #0]
800655c: 685b ldr r3, [r3, #4]
800655e: 617b str r3, [r7, #20]
8006560: 697b ldr r3, [r7, #20]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8006562: 68f8 ldr r0, [r7, #12]
8006564: f000 f81d bl 80065a2 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8006568: 68fb ldr r3, [r7, #12]
800656a: 2208 movs r2, #8
800656c: 645a str r2, [r3, #68] @ 0x44
/* Process Unlocked */
__HAL_UNLOCK(huart);
800656e: 68fb ldr r3, [r7, #12]
8006570: 2200 movs r2, #0
8006572: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8006576: 2301 movs r3, #1
8006578: e00f b.n 800659a <UART_WaitOnFlagUntilTimeout+0xaa>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800657a: 68fb ldr r3, [r7, #12]
800657c: 681b ldr r3, [r3, #0]
800657e: 681a ldr r2, [r3, #0]
8006580: 68bb ldr r3, [r7, #8]
8006582: 4013 ands r3, r2
8006584: 68ba ldr r2, [r7, #8]
8006586: 429a cmp r2, r3
8006588: bf0c ite eq
800658a: 2301 moveq r3, #1
800658c: 2300 movne r3, #0
800658e: b2db uxtb r3, r3
8006590: 461a mov r2, r3
8006592: 79fb ldrb r3, [r7, #7]
8006594: 429a cmp r2, r3
8006596: d0b4 beq.n 8006502 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8006598: 2300 movs r3, #0
}
800659a: 4618 mov r0, r3
800659c: 3718 adds r7, #24
800659e: 46bd mov sp, r7
80065a0: bd80 pop {r7, pc}
080065a2 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80065a2: b480 push {r7}
80065a4: b095 sub sp, #84 @ 0x54
80065a6: af00 add r7, sp, #0
80065a8: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80065aa: 687b ldr r3, [r7, #4]
80065ac: 681b ldr r3, [r3, #0]
80065ae: 330c adds r3, #12
80065b0: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80065b2: 6b7b ldr r3, [r7, #52] @ 0x34
80065b4: e853 3f00 ldrex r3, [r3]
80065b8: 633b str r3, [r7, #48] @ 0x30
return(result);
80065ba: 6b3b ldr r3, [r7, #48] @ 0x30
80065bc: f423 7390 bic.w r3, r3, #288 @ 0x120
80065c0: 64fb str r3, [r7, #76] @ 0x4c
80065c2: 687b ldr r3, [r7, #4]
80065c4: 681b ldr r3, [r3, #0]
80065c6: 330c adds r3, #12
80065c8: 6cfa ldr r2, [r7, #76] @ 0x4c
80065ca: 643a str r2, [r7, #64] @ 0x40
80065cc: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80065ce: 6bf9 ldr r1, [r7, #60] @ 0x3c
80065d0: 6c3a ldr r2, [r7, #64] @ 0x40
80065d2: e841 2300 strex r3, r2, [r1]
80065d6: 63bb str r3, [r7, #56] @ 0x38
return(result);
80065d8: 6bbb ldr r3, [r7, #56] @ 0x38
80065da: 2b00 cmp r3, #0
80065dc: d1e5 bne.n 80065aa <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80065de: 687b ldr r3, [r7, #4]
80065e0: 681b ldr r3, [r3, #0]
80065e2: 3314 adds r3, #20
80065e4: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80065e6: 6a3b ldr r3, [r7, #32]
80065e8: e853 3f00 ldrex r3, [r3]
80065ec: 61fb str r3, [r7, #28]
return(result);
80065ee: 69fb ldr r3, [r7, #28]
80065f0: f023 0301 bic.w r3, r3, #1
80065f4: 64bb str r3, [r7, #72] @ 0x48
80065f6: 687b ldr r3, [r7, #4]
80065f8: 681b ldr r3, [r3, #0]
80065fa: 3314 adds r3, #20
80065fc: 6cba ldr r2, [r7, #72] @ 0x48
80065fe: 62fa str r2, [r7, #44] @ 0x2c
8006600: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006602: 6ab9 ldr r1, [r7, #40] @ 0x28
8006604: 6afa ldr r2, [r7, #44] @ 0x2c
8006606: e841 2300 strex r3, r2, [r1]
800660a: 627b str r3, [r7, #36] @ 0x24
return(result);
800660c: 6a7b ldr r3, [r7, #36] @ 0x24
800660e: 2b00 cmp r3, #0
8006610: d1e5 bne.n 80065de <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006612: 687b ldr r3, [r7, #4]
8006614: 6b1b ldr r3, [r3, #48] @ 0x30
8006616: 2b01 cmp r3, #1
8006618: d119 bne.n 800664e <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800661a: 687b ldr r3, [r7, #4]
800661c: 681b ldr r3, [r3, #0]
800661e: 330c adds r3, #12
8006620: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006622: 68fb ldr r3, [r7, #12]
8006624: e853 3f00 ldrex r3, [r3]
8006628: 60bb str r3, [r7, #8]
return(result);
800662a: 68bb ldr r3, [r7, #8]
800662c: f023 0310 bic.w r3, r3, #16
8006630: 647b str r3, [r7, #68] @ 0x44
8006632: 687b ldr r3, [r7, #4]
8006634: 681b ldr r3, [r3, #0]
8006636: 330c adds r3, #12
8006638: 6c7a ldr r2, [r7, #68] @ 0x44
800663a: 61ba str r2, [r7, #24]
800663c: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800663e: 6979 ldr r1, [r7, #20]
8006640: 69ba ldr r2, [r7, #24]
8006642: e841 2300 strex r3, r2, [r1]
8006646: 613b str r3, [r7, #16]
return(result);
8006648: 693b ldr r3, [r7, #16]
800664a: 2b00 cmp r3, #0
800664c: d1e5 bne.n 800661a <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800664e: 687b ldr r3, [r7, #4]
8006650: 2220 movs r2, #32
8006652: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006656: 687b ldr r3, [r7, #4]
8006658: 2200 movs r2, #0
800665a: 631a str r2, [r3, #48] @ 0x30
}
800665c: bf00 nop
800665e: 3754 adds r7, #84 @ 0x54
8006660: 46bd mov sp, r7
8006662: bc80 pop {r7}
8006664: 4770 bx lr
08006666 <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8006666: b580 push {r7, lr}
8006668: b084 sub sp, #16
800666a: af00 add r7, sp, #0
800666c: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800666e: 687b ldr r3, [r7, #4]
8006670: 6a5b ldr r3, [r3, #36] @ 0x24
8006672: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8006674: 68fb ldr r3, [r7, #12]
8006676: 2200 movs r2, #0
8006678: 85da strh r2, [r3, #46] @ 0x2e
huart->TxXferCount = 0x00U;
800667a: 68fb ldr r3, [r7, #12]
800667c: 2200 movs r2, #0
800667e: 84da strh r2, [r3, #38] @ 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006680: 68f8 ldr r0, [r7, #12]
8006682: f7ff ff21 bl 80064c8 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006686: bf00 nop
8006688: 3710 adds r7, #16
800668a: 46bd mov sp, r7
800668c: bd80 pop {r7, pc}
0800668e <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
800668e: b480 push {r7}
8006690: b085 sub sp, #20
8006692: af00 add r7, sp, #0
8006694: 6078 str r0, [r7, #4]
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8006696: 687b ldr r3, [r7, #4]
8006698: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800669c: b2db uxtb r3, r3
800669e: 2b21 cmp r3, #33 @ 0x21
80066a0: d13e bne.n 8006720 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80066a2: 687b ldr r3, [r7, #4]
80066a4: 689b ldr r3, [r3, #8]
80066a6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80066aa: d114 bne.n 80066d6 <UART_Transmit_IT+0x48>
80066ac: 687b ldr r3, [r7, #4]
80066ae: 691b ldr r3, [r3, #16]
80066b0: 2b00 cmp r3, #0
80066b2: d110 bne.n 80066d6 <UART_Transmit_IT+0x48>
{
tmp = (const uint16_t *) huart->pTxBuffPtr;
80066b4: 687b ldr r3, [r7, #4]
80066b6: 6a1b ldr r3, [r3, #32]
80066b8: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
80066ba: 68fb ldr r3, [r7, #12]
80066bc: 881b ldrh r3, [r3, #0]
80066be: 461a mov r2, r3
80066c0: 687b ldr r3, [r7, #4]
80066c2: 681b ldr r3, [r3, #0]
80066c4: f3c2 0208 ubfx r2, r2, #0, #9
80066c8: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
80066ca: 687b ldr r3, [r7, #4]
80066cc: 6a1b ldr r3, [r3, #32]
80066ce: 1c9a adds r2, r3, #2
80066d0: 687b ldr r3, [r7, #4]
80066d2: 621a str r2, [r3, #32]
80066d4: e008 b.n 80066e8 <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
80066d6: 687b ldr r3, [r7, #4]
80066d8: 6a1b ldr r3, [r3, #32]
80066da: 1c59 adds r1, r3, #1
80066dc: 687a ldr r2, [r7, #4]
80066de: 6211 str r1, [r2, #32]
80066e0: 781a ldrb r2, [r3, #0]
80066e2: 687b ldr r3, [r7, #4]
80066e4: 681b ldr r3, [r3, #0]
80066e6: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
80066e8: 687b ldr r3, [r7, #4]
80066ea: 8cdb ldrh r3, [r3, #38] @ 0x26
80066ec: b29b uxth r3, r3
80066ee: 3b01 subs r3, #1
80066f0: b29b uxth r3, r3
80066f2: 687a ldr r2, [r7, #4]
80066f4: 4619 mov r1, r3
80066f6: 84d1 strh r1, [r2, #38] @ 0x26
80066f8: 2b00 cmp r3, #0
80066fa: d10f bne.n 800671c <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
80066fc: 687b ldr r3, [r7, #4]
80066fe: 681b ldr r3, [r3, #0]
8006700: 68da ldr r2, [r3, #12]
8006702: 687b ldr r3, [r7, #4]
8006704: 681b ldr r3, [r3, #0]
8006706: f022 0280 bic.w r2, r2, #128 @ 0x80
800670a: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
800670c: 687b ldr r3, [r7, #4]
800670e: 681b ldr r3, [r3, #0]
8006710: 68da ldr r2, [r3, #12]
8006712: 687b ldr r3, [r7, #4]
8006714: 681b ldr r3, [r3, #0]
8006716: f042 0240 orr.w r2, r2, #64 @ 0x40
800671a: 60da str r2, [r3, #12]
}
return HAL_OK;
800671c: 2300 movs r3, #0
800671e: e000 b.n 8006722 <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
8006720: 2302 movs r3, #2
}
}
8006722: 4618 mov r0, r3
8006724: 3714 adds r7, #20
8006726: 46bd mov sp, r7
8006728: bc80 pop {r7}
800672a: 4770 bx lr
0800672c <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
800672c: b580 push {r7, lr}
800672e: b082 sub sp, #8
8006730: af00 add r7, sp, #0
8006732: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
8006734: 687b ldr r3, [r7, #4]
8006736: 681b ldr r3, [r3, #0]
8006738: 68da ldr r2, [r3, #12]
800673a: 687b ldr r3, [r7, #4]
800673c: 681b ldr r3, [r3, #0]
800673e: f022 0240 bic.w r2, r2, #64 @ 0x40
8006742: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006744: 687b ldr r3, [r7, #4]
8006746: 2220 movs r2, #32
8006748: f883 2041 strb.w r2, [r3, #65] @ 0x41
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
800674c: 6878 ldr r0, [r7, #4]
800674e: f7ff fea9 bl 80064a4 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8006752: 2300 movs r3, #0
}
8006754: 4618 mov r0, r3
8006756: 3708 adds r7, #8
8006758: 46bd mov sp, r7
800675a: bd80 pop {r7, pc}
0800675c <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
800675c: b580 push {r7, lr}
800675e: b08c sub sp, #48 @ 0x30
8006760: af00 add r7, sp, #0
8006762: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006764: 687b ldr r3, [r7, #4]
8006766: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800676a: b2db uxtb r3, r3
800676c: 2b22 cmp r3, #34 @ 0x22
800676e: f040 80ae bne.w 80068ce <UART_Receive_IT+0x172>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8006772: 687b ldr r3, [r7, #4]
8006774: 689b ldr r3, [r3, #8]
8006776: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800677a: d117 bne.n 80067ac <UART_Receive_IT+0x50>
800677c: 687b ldr r3, [r7, #4]
800677e: 691b ldr r3, [r3, #16]
8006780: 2b00 cmp r3, #0
8006782: d113 bne.n 80067ac <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
8006784: 2300 movs r3, #0
8006786: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
8006788: 687b ldr r3, [r7, #4]
800678a: 6a9b ldr r3, [r3, #40] @ 0x28
800678c: 62bb str r3, [r7, #40] @ 0x28
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
800678e: 687b ldr r3, [r7, #4]
8006790: 681b ldr r3, [r3, #0]
8006792: 685b ldr r3, [r3, #4]
8006794: b29b uxth r3, r3
8006796: f3c3 0308 ubfx r3, r3, #0, #9
800679a: b29a uxth r2, r3
800679c: 6abb ldr r3, [r7, #40] @ 0x28
800679e: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
80067a0: 687b ldr r3, [r7, #4]
80067a2: 6a9b ldr r3, [r3, #40] @ 0x28
80067a4: 1c9a adds r2, r3, #2
80067a6: 687b ldr r3, [r7, #4]
80067a8: 629a str r2, [r3, #40] @ 0x28
80067aa: e026 b.n 80067fa <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
80067ac: 687b ldr r3, [r7, #4]
80067ae: 6a9b ldr r3, [r3, #40] @ 0x28
80067b0: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = NULL;
80067b2: 2300 movs r3, #0
80067b4: 62bb str r3, [r7, #40] @ 0x28
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80067b6: 687b ldr r3, [r7, #4]
80067b8: 689b ldr r3, [r3, #8]
80067ba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80067be: d007 beq.n 80067d0 <UART_Receive_IT+0x74>
80067c0: 687b ldr r3, [r7, #4]
80067c2: 689b ldr r3, [r3, #8]
80067c4: 2b00 cmp r3, #0
80067c6: d10a bne.n 80067de <UART_Receive_IT+0x82>
80067c8: 687b ldr r3, [r7, #4]
80067ca: 691b ldr r3, [r3, #16]
80067cc: 2b00 cmp r3, #0
80067ce: d106 bne.n 80067de <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80067d0: 687b ldr r3, [r7, #4]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 685b ldr r3, [r3, #4]
80067d6: b2da uxtb r2, r3
80067d8: 6afb ldr r3, [r7, #44] @ 0x2c
80067da: 701a strb r2, [r3, #0]
80067dc: e008 b.n 80067f0 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
80067de: 687b ldr r3, [r7, #4]
80067e0: 681b ldr r3, [r3, #0]
80067e2: 685b ldr r3, [r3, #4]
80067e4: b2db uxtb r3, r3
80067e6: f003 037f and.w r3, r3, #127 @ 0x7f
80067ea: b2da uxtb r2, r3
80067ec: 6afb ldr r3, [r7, #44] @ 0x2c
80067ee: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
80067f0: 687b ldr r3, [r7, #4]
80067f2: 6a9b ldr r3, [r3, #40] @ 0x28
80067f4: 1c5a adds r2, r3, #1
80067f6: 687b ldr r3, [r7, #4]
80067f8: 629a str r2, [r3, #40] @ 0x28
}
if (--huart->RxXferCount == 0U)
80067fa: 687b ldr r3, [r7, #4]
80067fc: 8ddb ldrh r3, [r3, #46] @ 0x2e
80067fe: b29b uxth r3, r3
8006800: 3b01 subs r3, #1
8006802: b29b uxth r3, r3
8006804: 687a ldr r2, [r7, #4]
8006806: 4619 mov r1, r3
8006808: 85d1 strh r1, [r2, #46] @ 0x2e
800680a: 2b00 cmp r3, #0
800680c: d15d bne.n 80068ca <UART_Receive_IT+0x16e>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
800680e: 687b ldr r3, [r7, #4]
8006810: 681b ldr r3, [r3, #0]
8006812: 68da ldr r2, [r3, #12]
8006814: 687b ldr r3, [r7, #4]
8006816: 681b ldr r3, [r3, #0]
8006818: f022 0220 bic.w r2, r2, #32
800681c: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
800681e: 687b ldr r3, [r7, #4]
8006820: 681b ldr r3, [r3, #0]
8006822: 68da ldr r2, [r3, #12]
8006824: 687b ldr r3, [r7, #4]
8006826: 681b ldr r3, [r3, #0]
8006828: f422 7280 bic.w r2, r2, #256 @ 0x100
800682c: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
800682e: 687b ldr r3, [r7, #4]
8006830: 681b ldr r3, [r3, #0]
8006832: 695a ldr r2, [r3, #20]
8006834: 687b ldr r3, [r7, #4]
8006836: 681b ldr r3, [r3, #0]
8006838: f022 0201 bic.w r2, r2, #1
800683c: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800683e: 687b ldr r3, [r7, #4]
8006840: 2220 movs r2, #32
8006842: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8006846: 687b ldr r3, [r7, #4]
8006848: 2200 movs r2, #0
800684a: 635a str r2, [r3, #52] @ 0x34
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800684c: 687b ldr r3, [r7, #4]
800684e: 6b1b ldr r3, [r3, #48] @ 0x30
8006850: 2b01 cmp r3, #1
8006852: d135 bne.n 80068c0 <UART_Receive_IT+0x164>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006854: 687b ldr r3, [r7, #4]
8006856: 2200 movs r2, #0
8006858: 631a str r2, [r3, #48] @ 0x30
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800685a: 687b ldr r3, [r7, #4]
800685c: 681b ldr r3, [r3, #0]
800685e: 330c adds r3, #12
8006860: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006862: 697b ldr r3, [r7, #20]
8006864: e853 3f00 ldrex r3, [r3]
8006868: 613b str r3, [r7, #16]
return(result);
800686a: 693b ldr r3, [r7, #16]
800686c: f023 0310 bic.w r3, r3, #16
8006870: 627b str r3, [r7, #36] @ 0x24
8006872: 687b ldr r3, [r7, #4]
8006874: 681b ldr r3, [r3, #0]
8006876: 330c adds r3, #12
8006878: 6a7a ldr r2, [r7, #36] @ 0x24
800687a: 623a str r2, [r7, #32]
800687c: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800687e: 69f9 ldr r1, [r7, #28]
8006880: 6a3a ldr r2, [r7, #32]
8006882: e841 2300 strex r3, r2, [r1]
8006886: 61bb str r3, [r7, #24]
return(result);
8006888: 69bb ldr r3, [r7, #24]
800688a: 2b00 cmp r3, #0
800688c: d1e5 bne.n 800685a <UART_Receive_IT+0xfe>
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
800688e: 687b ldr r3, [r7, #4]
8006890: 681b ldr r3, [r3, #0]
8006892: 681b ldr r3, [r3, #0]
8006894: f003 0310 and.w r3, r3, #16
8006898: 2b10 cmp r3, #16
800689a: d10a bne.n 80068b2 <UART_Receive_IT+0x156>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
800689c: 2300 movs r3, #0
800689e: 60fb str r3, [r7, #12]
80068a0: 687b ldr r3, [r7, #4]
80068a2: 681b ldr r3, [r3, #0]
80068a4: 681b ldr r3, [r3, #0]
80068a6: 60fb str r3, [r7, #12]
80068a8: 687b ldr r3, [r7, #4]
80068aa: 681b ldr r3, [r3, #0]
80068ac: 685b ldr r3, [r3, #4]
80068ae: 60fb str r3, [r7, #12]
80068b0: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80068b2: 687b ldr r3, [r7, #4]
80068b4: 8d9b ldrh r3, [r3, #44] @ 0x2c
80068b6: 4619 mov r1, r3
80068b8: 6878 ldr r0, [r7, #4]
80068ba: f7ff fe0e bl 80064da <HAL_UARTEx_RxEventCallback>
80068be: e002 b.n 80068c6 <UART_Receive_IT+0x16a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
80068c0: 6878 ldr r0, [r7, #4]
80068c2: f7ff fdf8 bl 80064b6 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
80068c6: 2300 movs r3, #0
80068c8: e002 b.n 80068d0 <UART_Receive_IT+0x174>
}
return HAL_OK;
80068ca: 2300 movs r3, #0
80068cc: e000 b.n 80068d0 <UART_Receive_IT+0x174>
}
else
{
return HAL_BUSY;
80068ce: 2302 movs r3, #2
}
}
80068d0: 4618 mov r0, r3
80068d2: 3730 adds r7, #48 @ 0x30
80068d4: 46bd mov sp, r7
80068d6: bd80 pop {r7, pc}
080068d8 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
80068d8: b580 push {r7, lr}
80068da: b084 sub sp, #16
80068dc: af00 add r7, sp, #0
80068de: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80068e0: 687b ldr r3, [r7, #4]
80068e2: 681b ldr r3, [r3, #0]
80068e4: 691b ldr r3, [r3, #16]
80068e6: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80068ea: 687b ldr r3, [r7, #4]
80068ec: 68da ldr r2, [r3, #12]
80068ee: 687b ldr r3, [r7, #4]
80068f0: 681b ldr r3, [r3, #0]
80068f2: 430a orrs r2, r1
80068f4: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
80068f6: 687b ldr r3, [r7, #4]
80068f8: 689a ldr r2, [r3, #8]
80068fa: 687b ldr r3, [r7, #4]
80068fc: 691b ldr r3, [r3, #16]
80068fe: 431a orrs r2, r3
8006900: 687b ldr r3, [r7, #4]
8006902: 695b ldr r3, [r3, #20]
8006904: 4313 orrs r3, r2
8006906: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
8006908: 687b ldr r3, [r7, #4]
800690a: 681b ldr r3, [r3, #0]
800690c: 68db ldr r3, [r3, #12]
800690e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8006912: f023 030c bic.w r3, r3, #12
8006916: 687a ldr r2, [r7, #4]
8006918: 6812 ldr r2, [r2, #0]
800691a: 68b9 ldr r1, [r7, #8]
800691c: 430b orrs r3, r1
800691e: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8006920: 687b ldr r3, [r7, #4]
8006922: 681b ldr r3, [r3, #0]
8006924: 695b ldr r3, [r3, #20]
8006926: f423 7140 bic.w r1, r3, #768 @ 0x300
800692a: 687b ldr r3, [r7, #4]
800692c: 699a ldr r2, [r3, #24]
800692e: 687b ldr r3, [r7, #4]
8006930: 681b ldr r3, [r3, #0]
8006932: 430a orrs r2, r1
8006934: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
8006936: 687b ldr r3, [r7, #4]
8006938: 681b ldr r3, [r3, #0]
800693a: 4a2c ldr r2, [pc, #176] @ (80069ec <UART_SetConfig+0x114>)
800693c: 4293 cmp r3, r2
800693e: d103 bne.n 8006948 <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8006940: f7fe fd68 bl 8005414 <HAL_RCC_GetPCLK2Freq>
8006944: 60f8 str r0, [r7, #12]
8006946: e002 b.n 800694e <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8006948: f7fe fd50 bl 80053ec <HAL_RCC_GetPCLK1Freq>
800694c: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
800694e: 68fa ldr r2, [r7, #12]
8006950: 4613 mov r3, r2
8006952: 009b lsls r3, r3, #2
8006954: 4413 add r3, r2
8006956: 009a lsls r2, r3, #2
8006958: 441a add r2, r3
800695a: 687b ldr r3, [r7, #4]
800695c: 685b ldr r3, [r3, #4]
800695e: 009b lsls r3, r3, #2
8006960: fbb2 f3f3 udiv r3, r2, r3
8006964: 4a22 ldr r2, [pc, #136] @ (80069f0 <UART_SetConfig+0x118>)
8006966: fba2 2303 umull r2, r3, r2, r3
800696a: 095b lsrs r3, r3, #5
800696c: 0119 lsls r1, r3, #4
800696e: 68fa ldr r2, [r7, #12]
8006970: 4613 mov r3, r2
8006972: 009b lsls r3, r3, #2
8006974: 4413 add r3, r2
8006976: 009a lsls r2, r3, #2
8006978: 441a add r2, r3
800697a: 687b ldr r3, [r7, #4]
800697c: 685b ldr r3, [r3, #4]
800697e: 009b lsls r3, r3, #2
8006980: fbb2 f2f3 udiv r2, r2, r3
8006984: 4b1a ldr r3, [pc, #104] @ (80069f0 <UART_SetConfig+0x118>)
8006986: fba3 0302 umull r0, r3, r3, r2
800698a: 095b lsrs r3, r3, #5
800698c: 2064 movs r0, #100 @ 0x64
800698e: fb00 f303 mul.w r3, r0, r3
8006992: 1ad3 subs r3, r2, r3
8006994: 011b lsls r3, r3, #4
8006996: 3332 adds r3, #50 @ 0x32
8006998: 4a15 ldr r2, [pc, #84] @ (80069f0 <UART_SetConfig+0x118>)
800699a: fba2 2303 umull r2, r3, r2, r3
800699e: 095b lsrs r3, r3, #5
80069a0: f003 03f0 and.w r3, r3, #240 @ 0xf0
80069a4: 4419 add r1, r3
80069a6: 68fa ldr r2, [r7, #12]
80069a8: 4613 mov r3, r2
80069aa: 009b lsls r3, r3, #2
80069ac: 4413 add r3, r2
80069ae: 009a lsls r2, r3, #2
80069b0: 441a add r2, r3
80069b2: 687b ldr r3, [r7, #4]
80069b4: 685b ldr r3, [r3, #4]
80069b6: 009b lsls r3, r3, #2
80069b8: fbb2 f2f3 udiv r2, r2, r3
80069bc: 4b0c ldr r3, [pc, #48] @ (80069f0 <UART_SetConfig+0x118>)
80069be: fba3 0302 umull r0, r3, r3, r2
80069c2: 095b lsrs r3, r3, #5
80069c4: 2064 movs r0, #100 @ 0x64
80069c6: fb00 f303 mul.w r3, r0, r3
80069ca: 1ad3 subs r3, r2, r3
80069cc: 011b lsls r3, r3, #4
80069ce: 3332 adds r3, #50 @ 0x32
80069d0: 4a07 ldr r2, [pc, #28] @ (80069f0 <UART_SetConfig+0x118>)
80069d2: fba2 2303 umull r2, r3, r2, r3
80069d6: 095b lsrs r3, r3, #5
80069d8: f003 020f and.w r2, r3, #15
80069dc: 687b ldr r3, [r7, #4]
80069de: 681b ldr r3, [r3, #0]
80069e0: 440a add r2, r1
80069e2: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
80069e4: bf00 nop
80069e6: 3710 adds r7, #16
80069e8: 46bd mov sp, r7
80069ea: bd80 pop {r7, pc}
80069ec: 40013800 .word 0x40013800
80069f0: 51eb851f .word 0x51eb851f
080069f4 <memset>:
80069f4: 4603 mov r3, r0
80069f6: 4402 add r2, r0
80069f8: 4293 cmp r3, r2
80069fa: d100 bne.n 80069fe <memset+0xa>
80069fc: 4770 bx lr
80069fe: f803 1b01 strb.w r1, [r3], #1
8006a02: e7f9 b.n 80069f8 <memset+0x4>
08006a04 <__errno>:
8006a04: 4b01 ldr r3, [pc, #4] @ (8006a0c <__errno+0x8>)
8006a06: 6818 ldr r0, [r3, #0]
8006a08: 4770 bx lr
8006a0a: bf00 nop
8006a0c: 20000010 .word 0x20000010
08006a10 <__libc_init_array>:
8006a10: b570 push {r4, r5, r6, lr}
8006a12: 2600 movs r6, #0
8006a14: 4d0c ldr r5, [pc, #48] @ (8006a48 <__libc_init_array+0x38>)
8006a16: 4b0d ldr r3, [pc, #52] @ (8006a4c <__libc_init_array+0x3c>)
8006a18: 1b5b subs r3, r3, r5
8006a1a: 109c asrs r4, r3, #2
8006a1c: 42a6 cmp r6, r4
8006a1e: d109 bne.n 8006a34 <__libc_init_array+0x24>
8006a20: 2600 movs r6, #0
8006a22: f000 f8cd bl 8006bc0 <_init>
8006a26: 4d0a ldr r5, [pc, #40] @ (8006a50 <__libc_init_array+0x40>)
8006a28: 4b0a ldr r3, [pc, #40] @ (8006a54 <__libc_init_array+0x44>)
8006a2a: 1b5b subs r3, r3, r5
8006a2c: 109c asrs r4, r3, #2
8006a2e: 42a6 cmp r6, r4
8006a30: d105 bne.n 8006a3e <__libc_init_array+0x2e>
8006a32: bd70 pop {r4, r5, r6, pc}
8006a34: f855 3b04 ldr.w r3, [r5], #4
8006a38: 4798 blx r3
8006a3a: 3601 adds r6, #1
8006a3c: e7ee b.n 8006a1c <__libc_init_array+0xc>
8006a3e: f855 3b04 ldr.w r3, [r5], #4
8006a42: 4798 blx r3
8006a44: 3601 adds r6, #1
8006a46: e7f2 b.n 8006a2e <__libc_init_array+0x1e>
8006a48: 08006c64 .word 0x08006c64
8006a4c: 08006c64 .word 0x08006c64
8006a50: 08006c64 .word 0x08006c64
8006a54: 08006c68 .word 0x08006c68
08006a58 <sqrtf>:
8006a58: b538 push {r3, r4, r5, lr}
8006a5a: 4604 mov r4, r0
8006a5c: f000 f81a bl 8006a94 <__ieee754_sqrtf>
8006a60: 4621 mov r1, r4
8006a62: 4605 mov r5, r0
8006a64: 4620 mov r0, r4
8006a66: f7fa f9e3 bl 8000e30 <__aeabi_fcmpun>
8006a6a: b920 cbnz r0, 8006a76 <sqrtf+0x1e>
8006a6c: 4620 mov r0, r4
8006a6e: 2100 movs r1, #0
8006a70: f7fa f9b6 bl 8000de0 <__aeabi_fcmplt>
8006a74: b908 cbnz r0, 8006a7a <sqrtf+0x22>
8006a76: 4628 mov r0, r5
8006a78: bd38 pop {r3, r4, r5, pc}
8006a7a: f7ff ffc3 bl 8006a04 <__errno>
8006a7e: 2221 movs r2, #33 @ 0x21
8006a80: 4603 mov r3, r0
8006a82: 2100 movs r1, #0
8006a84: 601a str r2, [r3, #0]
8006a86: 4608 mov r0, r1
8006a88: f7fa f8c0 bl 8000c0c <__aeabi_fdiv>
8006a8c: 4605 mov r5, r0
8006a8e: 4628 mov r0, r5
8006a90: bd38 pop {r3, r4, r5, pc}
8006a92: bf00 nop
08006a94 <__ieee754_sqrtf>:
8006a94: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000
8006a98: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000
8006a9c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8006aa0: 4604 mov r4, r0
8006aa2: d24f bcs.n 8006b44 <__ieee754_sqrtf+0xb0>
8006aa4: 2a00 cmp r2, #0
8006aa6: d04b beq.n 8006b40 <__ieee754_sqrtf+0xac>
8006aa8: 2800 cmp r0, #0
8006aaa: 4603 mov r3, r0
8006aac: db54 blt.n 8006b58 <__ieee754_sqrtf+0xc4>
8006aae: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000
8006ab2: d14f bne.n 8006b54 <__ieee754_sqrtf+0xc0>
8006ab4: 005b lsls r3, r3, #1
8006ab6: 0218 lsls r0, r3, #8
8006ab8: 4611 mov r1, r2
8006aba: f102 0201 add.w r2, r2, #1
8006abe: d5f9 bpl.n 8006ab4 <__ieee754_sqrtf+0x20>
8006ac0: 4249 negs r1, r1
8006ac2: 2400 movs r4, #0
8006ac4: f3c3 0216 ubfx r2, r3, #0, #23
8006ac8: f1a1 057f sub.w r5, r1, #127 @ 0x7f
8006acc: 07cb lsls r3, r1, #31
8006ace: f04f 0e19 mov.w lr, #25
8006ad2: f04f 7c80 mov.w ip, #16777216 @ 0x1000000
8006ad6: 4621 mov r1, r4
8006ad8: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8006adc: bf58 it pl
8006ade: 0052 lslpl r2, r2, #1
8006ae0: 106d asrs r5, r5, #1
8006ae2: 0052 lsls r2, r2, #1
8006ae4: eb01 030c add.w r3, r1, ip
8006ae8: 4293 cmp r3, r2
8006aea: bfcf iteee gt
8006aec: 4613 movgt r3, r2
8006aee: eb03 010c addle.w r1, r3, ip
8006af2: 4464 addle r4, ip
8006af4: 1ad3 suble r3, r2, r3
8006af6: f1be 0e01 subs.w lr, lr, #1
8006afa: ea4f 0243 mov.w r2, r3, lsl #1
8006afe: ea4f 0c5c mov.w ip, ip, lsr #1
8006b02: d1ef bne.n 8006ae4 <__ieee754_sqrtf+0x50>
8006b04: b1bb cbz r3, 8006b36 <__ieee754_sqrtf+0xa2>
8006b06: 4e1a ldr r6, [pc, #104] @ (8006b70 <__ieee754_sqrtf+0xdc>)
8006b08: 4f1a ldr r7, [pc, #104] @ (8006b74 <__ieee754_sqrtf+0xe0>)
8006b0a: 6830 ldr r0, [r6, #0]
8006b0c: 6839 ldr r1, [r7, #0]
8006b0e: f7f9 febf bl 8000890 <__aeabi_fsub>
8006b12: f8d6 8000 ldr.w r8, [r6]
8006b16: 4601 mov r1, r0
8006b18: 4640 mov r0, r8
8006b1a: f7fa f96b bl 8000df4 <__aeabi_fcmple>
8006b1e: b150 cbz r0, 8006b36 <__ieee754_sqrtf+0xa2>
8006b20: 6830 ldr r0, [r6, #0]
8006b22: 6839 ldr r1, [r7, #0]
8006b24: f7f9 feb6 bl 8000894 <__addsf3>
8006b28: 6836 ldr r6, [r6, #0]
8006b2a: 4601 mov r1, r0
8006b2c: 4630 mov r0, r6
8006b2e: f7fa f957 bl 8000de0 <__aeabi_fcmplt>
8006b32: b1c8 cbz r0, 8006b68 <__ieee754_sqrtf+0xd4>
8006b34: 3402 adds r4, #2
8006b36: 1060 asrs r0, r4, #1
8006b38: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000
8006b3c: eb00 50c5 add.w r0, r0, r5, lsl #23
8006b40: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006b44: 4601 mov r1, r0
8006b46: f7f9 ffad bl 8000aa4 <__aeabi_fmul>
8006b4a: 4621 mov r1, r4
8006b4c: f7f9 fea2 bl 8000894 <__addsf3>
8006b50: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006b54: 15c1 asrs r1, r0, #23
8006b56: e7b4 b.n 8006ac2 <__ieee754_sqrtf+0x2e>
8006b58: 4601 mov r1, r0
8006b5a: f7f9 fe99 bl 8000890 <__aeabi_fsub>
8006b5e: 4601 mov r1, r0
8006b60: f7fa f854 bl 8000c0c <__aeabi_fdiv>
8006b64: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006b68: 3401 adds r4, #1
8006b6a: f024 0401 bic.w r4, r4, #1
8006b6e: e7e2 b.n 8006b36 <__ieee754_sqrtf+0xa2>
8006b70: 08006c58 .word 0x08006c58
8006b74: 08006c54 .word 0x08006c54
08006b78 <roundf>:
8006b78: b508 push {r3, lr}
8006b7a: f3c0 53c7 ubfx r3, r0, #23, #8
8006b7e: 3b7f subs r3, #127 @ 0x7f
8006b80: 2b16 cmp r3, #22
8006b82: 4601 mov r1, r0
8006b84: dc0e bgt.n 8006ba4 <roundf+0x2c>
8006b86: 2b00 cmp r3, #0
8006b88: 4602 mov r2, r0
8006b8a: db10 blt.n 8006bae <roundf+0x36>
8006b8c: 480b ldr r0, [pc, #44] @ (8006bbc <roundf+0x44>)
8006b8e: 4118 asrs r0, r3
8006b90: 4201 tst r1, r0
8006b92: d005 beq.n 8006ba0 <roundf+0x28>
8006b94: f44f 0180 mov.w r1, #4194304 @ 0x400000
8006b98: 4119 asrs r1, r3
8006b9a: 4411 add r1, r2
8006b9c: ea21 0100 bic.w r1, r1, r0
8006ba0: 4608 mov r0, r1
8006ba2: bd08 pop {r3, pc}
8006ba4: 2b80 cmp r3, #128 @ 0x80
8006ba6: d1fb bne.n 8006ba0 <roundf+0x28>
8006ba8: f7f9 fe74 bl 8000894 <__addsf3>
8006bac: bd08 pop {r3, pc}
8006bae: 3301 adds r3, #1
8006bb0: f000 4100 and.w r1, r0, #2147483648 @ 0x80000000
8006bb4: d1f4 bne.n 8006ba0 <roundf+0x28>
8006bb6: f041 517e orr.w r1, r1, #1065353216 @ 0x3f800000
8006bba: e7f1 b.n 8006ba0 <roundf+0x28>
8006bbc: 007fffff .word 0x007fffff
08006bc0 <_init>:
8006bc0: b5f8 push {r3, r4, r5, r6, r7, lr}
8006bc2: bf00 nop
8006bc4: bcf8 pop {r3, r4, r5, r6, r7}
8006bc6: bc08 pop {r3}
8006bc8: 469e mov lr, r3
8006bca: 4770 bx lr
08006bcc <_fini>:
8006bcc: b5f8 push {r3, r4, r5, r6, r7, lr}
8006bce: bf00 nop
8006bd0: bcf8 pop {r3, r4, r5, r6, r7}
8006bd2: bc08 pop {r3}
8006bd4: 469e mov lr, r3
8006bd6: 4770 bx lr
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