: /** * @brief The application entry point. * @retval int */ int main(void) { 800234c: b5b0 push {r4, r5, r7, lr} 800234e: b08e sub sp, #56 @ 0x38 8002350: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ uint8_t tempString[15] = {0}; 8002352: f107 0308 add.w r3, r7, #8 8002356: 2200 movs r2, #0 8002358: 601a str r2, [r3, #0] 800235a: 605a str r2, [r3, #4] 800235c: 609a str r2, [r3, #8] 800235e: f8c3 200b str.w r2, [r3, #11] uint8_t averages = 0; 8002362: 2300 movs r3, #0 8002364: f887 3033 strb.w r3, [r7, #51] @ 0x33 uint8_t newline = '\n'; 8002368: 230a movs r3, #10 800236a: 71fb strb r3, [r7, #7] // Variables for timing uint32_t previous_millis_green = 0; 800236c: 2300 movs r3, #0 800236e: 637b str r3, [r7, #52] @ 0x34 uint32_t previous_millis_red = 0; 8002370: 2300 movs r3, #0 8002372: 62fb str r3, [r7, #44] @ 0x2c /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8002374: f000 fe16 bl 8002fa4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8002378: f000 f942 bl 8002600 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800237c: f7ff fe7e bl 800207c MX_ADC1_Init(); 8002380: f7ff fa66 bl 8001850 MX_ADC2_Init(); 8002384: f7ff faa2 bl 80018cc MX_I2C1_Init(); 8002388: f7ff ff18 bl 80021bc MX_I2C2_Init(); 800238c: f7ff ff44 bl 8002218 MX_USART1_UART_Init(); 8002390: f000 fd64 bl 8002e5c MX_TIM3_Init(); 8002394: f000 fcee bl 8002d74 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim3); 8002398: 488e ldr r0, [pc, #568] @ (80025d4 ) 800239a: f003 f973 bl 8005684 //AD5934_MovingAvg_Init (&g_rtd_filter); //AD5934_MovingAvg_Init (&g_ref_filter); //AD5934_MovingAvg_Init (&g_ec_filter); HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off 800239e: 2201 movs r2, #1 80023a0: 2110 movs r1, #16 80023a2: 488d ldr r0, [pc, #564] @ (80025d8 ) 80023a4: f001 fbf1 bl 8003b8a HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off 80023a8: 2201 movs r2, #1 80023aa: 2120 movs r1, #32 80023ac: 488a ldr r0, [pc, #552] @ (80025d8 ) 80023ae: f001 fbec bl 8003b8a digital_outputs_init(); 80023b2: f7ff fdcb bl 8001f4c rs485_init(); 80023b6: f000 fb7d bl 8002ab4 ADG715_ResetChannels(); 80023ba: f7ff fa2b bl 8001814 ADS1015_Init(); // Initializes pH Measurement 80023be: f7ff fb75 bl 8001aac AD5934_Init(); // Initializes CE and RTD Measurement 80023c2: f7fe fe0b bl 8000fdc averages++; } } } */ digital_outputs_toggle(0); 80023c6: 2000 movs r0, #0 80023c8: f7ff fe3a bl 8002040 digital_outputs_toggle(1); 80023cc: 2001 movs r0, #1 80023ce: f7ff fe37 bl 8002040 digital_outputs_toggle(2); 80023d2: 2002 movs r0, #2 80023d4: f7ff fe34 bl 8002040 digital_outputs_toggle(3); 80023d8: 2003 movs r0, #3 80023da: f7ff fe31 bl 8002040 digital_outputs_toggle(4); 80023de: 2004 movs r0, #4 80023e0: f7ff fe2e bl 8002040 digital_outputs_toggle(5); 80023e4: 2005 movs r0, #5 80023e6: f7ff fe2b bl 8002040 digital_outputs_toggle(6); 80023ea: 2006 movs r0, #6 80023ec: f7ff fe28 bl 8002040 digital_outputs_toggle(7); 80023f0: 2007 movs r0, #7 80023f2: f7ff fe25 bl 8002040 while (1) { AD5934_Process_System(); 80023f6: f7fe ff23 bl 8001240 ADS1015_Process_System(); 80023fa: f7ff fbb5 bl 8001b68 current_millis = g_ms_counter; 80023fe: 4b77 ldr r3, [pc, #476] @ (80025dc ) 8002400: 681b ldr r3, [r3, #0] 8002402: 62bb str r3, [r7, #40] @ 0x28 if((current_millis % 500) == 0) // Send data each 100ms 8002404: 6aba ldr r2, [r7, #40] @ 0x28 8002406: 4b76 ldr r3, [pc, #472] @ (80025e0 ) 8002408: fba3 1302 umull r1, r3, r3, r2 800240c: 095b lsrs r3, r3, #5 800240e: f44f 71fa mov.w r1, #500 @ 0x1f4 8002412: fb01 f303 mul.w r3, r1, r3 8002416: 1ad3 subs r3, r2, r3 8002418: 2b00 cmp r3, #0 800241a: f040 80cc bne.w 80025b6 { //if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms //{ mag_reference = g_ref_filter.filtered_value; 800241e: 4b71 ldr r3, [pc, #452] @ (80025e4 ) 8002420: 6b5b ldr r3, [r3, #52] @ 0x34 8002422: 627b str r3, [r7, #36] @ 0x24 //reference_resistor = g_ref_filter.filtered_value; //uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, current_ref_mux); //intToStr(reference_final, tempString); //ref_final = g_ref_filter.filtered_value; FloatToString(tempString, mag_reference); 8002424: 6a78 ldr r0, [r7, #36] @ 0x24 8002426: f7fe f927 bl 8000678 <__aeabi_f2d> 800242a: 4602 mov r2, r0 800242c: 460b mov r3, r1 800242e: f107 0108 add.w r1, r7, #8 8002432: 4608 mov r0, r1 8002434: f000 f934 bl 80026a0 //Convert2Hex(ref_now, tempString); //intToStr(ref_now, tempString); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8002438: f107 0308 add.w r3, r7, #8 800243c: 4618 mov r0, r3 800243e: f7fd fe85 bl 800014c 8002442: 4603 mov r3, r0 8002444: b29a uxth r2, r3 8002446: f107 0308 add.w r3, r7, #8 800244a: 4611 mov r1, r2 800244c: 4618 mov r0, r3 800244e: f000 fb5d bl 8002b0c //intToStr(ref_now_i, tempString); //rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); rs485_send_broadcast(&newline, 1); 8002452: 1dfb adds r3, r7, #7 8002454: 2101 movs r1, #1 8002456: 4618 mov r0, r3 8002458: f000 fb58 bl 8002b0c //} //if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C //{ //mag_rtd = (float)rtd_now; mag_rtd = g_rtd_filter.filtered_value; 800245c: 4b62 ldr r3, [pc, #392] @ (80025e8 ) 800245e: 6b5b ldr r3, [r3, #52] @ 0x34 8002460: 623b str r3, [r7, #32] //mag_rtd = sqrtf((g_rtd_real_filter.average * g_rtd_real_filter.average)+(g_rtd_imag_filter.average * g_rtd_imag_filter.average)); //mag_rtd = sqrtf(((float)rtd_now * (float)rtd_now) + ((float)rtd_now_i * (float)rtd_now_i)); //temperature_RTD = AD5934_Calculate_Temperature(mag_reference, mag_rtd); temperature_RTD = AD5934_Calculate_Temperature(mag_reference,mag_rtd);// AD5934_GetImpedance(mag_reference,mag_rtd);// 8002462: 6a39 ldr r1, [r7, #32] 8002464: 6a78 ldr r0, [r7, #36] @ 0x24 8002466: f7fe fe05 bl 8001074 800246a: 4603 mov r3, r0 800246c: 4a5f ldr r2, [pc, #380] @ (80025ec ) 800246e: 6013 str r3, [r2, #0] //uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, current_rtd_mux); //uint16_t rtd_final = AD5934_Compress_To_IntScale(temperature_RTD, current_rtd_mux); //intToStr(rtd_final, tempString); //float rtd_final = g_rtd_filter.filtered_value; //g_rtd_filter.filtered_value; FloatToString(tempString, temperature_RTD); 8002470: 4b5e ldr r3, [pc, #376] @ (80025ec ) 8002472: 681b ldr r3, [r3, #0] 8002474: 4618 mov r0, r3 8002476: f7fe f8ff bl 8000678 <__aeabi_f2d> 800247a: 4602 mov r2, r0 800247c: 460b mov r3, r1 800247e: f107 0108 add.w r1, r7, #8 8002482: 4608 mov r0, r1 8002484: f000 f90c bl 80026a0 //Convert2Hex(rtd_now, tempString); //intToStr(rtd_now, tempString); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8002488: f107 0308 add.w r3, r7, #8 800248c: 4618 mov r0, r3 800248e: f7fd fe5d bl 800014c 8002492: 4603 mov r3, r0 8002494: b29a uxth r2, r3 8002496: f107 0308 add.w r3, r7, #8 800249a: 4611 mov r1, r2 800249c: 4618 mov r0, r3 800249e: f000 fb35 bl 8002b0c //Convert2Hex(rtd_now_i, tempString); //intToStr(rtd_now_i, tempString); //rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); rs485_send_broadcast(&newline, 1); 80024a2: 1dfb adds r3, r7, #7 80024a4: 2101 movs r1, #1 80024a6: 4618 mov r0, r3 80024a8: f000 fb30 bl 8002b0c }*/ //if (g_ec_filter.value_valid) // EC //{ //mag_ec = sqrtf((g_ec_real_filter.filtered_value * g_ec_real_filter.filtered_value)+(g_ec_imag_filter.filtered_value * g_ec_imag_filter.filtered_value)); mag_ec = sqrtf(((float)ec_now * (float)ec_now) + ((float)ec_now_i * (float)ec_now_i)); 80024ac: 4b50 ldr r3, [pc, #320] @ (80025f0 ) 80024ae: f9b3 3000 ldrsh.w r3, [r3] 80024b2: 4618 mov r0, r3 80024b4: f7fe faa2 bl 80009fc <__aeabi_i2f> 80024b8: 4604 mov r4, r0 80024ba: 4b4d ldr r3, [pc, #308] @ (80025f0 ) 80024bc: f9b3 3000 ldrsh.w r3, [r3] 80024c0: 4618 mov r0, r3 80024c2: f7fe fa9b bl 80009fc <__aeabi_i2f> 80024c6: 4603 mov r3, r0 80024c8: 4619 mov r1, r3 80024ca: 4620 mov r0, r4 80024cc: f7fe faea bl 8000aa4 <__aeabi_fmul> 80024d0: 4603 mov r3, r0 80024d2: 461d mov r5, r3 80024d4: 4b47 ldr r3, [pc, #284] @ (80025f4 ) 80024d6: f9b3 3000 ldrsh.w r3, [r3] 80024da: 4618 mov r0, r3 80024dc: f7fe fa8e bl 80009fc <__aeabi_i2f> 80024e0: 4604 mov r4, r0 80024e2: 4b44 ldr r3, [pc, #272] @ (80025f4 ) 80024e4: f9b3 3000 ldrsh.w r3, [r3] 80024e8: 4618 mov r0, r3 80024ea: f7fe fa87 bl 80009fc <__aeabi_i2f> 80024ee: 4603 mov r3, r0 80024f0: 4619 mov r1, r3 80024f2: 4620 mov r0, r4 80024f4: f7fe fad6 bl 8000aa4 <__aeabi_fmul> 80024f8: 4603 mov r3, r0 80024fa: 4619 mov r1, r3 80024fc: 4628 mov r0, r5 80024fe: f7fe f9c9 bl 8000894 <__addsf3> 8002502: 4603 mov r3, r0 8002504: 4618 mov r0, r3 8002506: f004 faa7 bl 8006a58 800250a: 61f8 str r0, [r7, #28] thermal_compensaded_EC = AD5934_EC_Compensate_Magnitude_To_25C(mag_ec, temperature_RTD); 800250c: 4b37 ldr r3, [pc, #220] @ (80025ec ) 800250e: 681b ldr r3, [r3, #0] 8002510: 4619 mov r1, r3 8002512: 69f8 ldr r0, [r7, #28] 8002514: f7fe fe2a bl 800116c 8002518: 4603 mov r3, r0 800251a: 4a37 ldr r2, [pc, #220] @ (80025f8 ) 800251c: 6013 str r3, [r2, #0] //uint16_t ec_final = AD5934_Compress_To_IntScale(thermal_compensaded_EC, current_ec_mux); //intToStr(ec_now, tempString); // float ec_final = g_ec_filter.filtered_value; FloatToString(tempString, mag_ec); 800251e: 69f8 ldr r0, [r7, #28] 8002520: f7fe f8aa bl 8000678 <__aeabi_f2d> 8002524: 4602 mov r2, r0 8002526: 460b mov r3, r1 8002528: f107 0108 add.w r1, r7, #8 800252c: 4608 mov r0, r1 800252e: f000 f8b7 bl 80026a0 //Convert2Hex((ec_now+0x80008000), tempString); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8002532: f107 0308 add.w r3, r7, #8 8002536: 4618 mov r0, r3 8002538: f7fd fe08 bl 800014c 800253c: 4603 mov r3, r0 800253e: b29a uxth r2, r3 8002540: f107 0308 add.w r3, r7, #8 8002544: 4611 mov r1, r2 8002546: 4618 mov r0, r3 8002548: f000 fae0 bl 8002b0c //intToStr(ec_now_i, tempString); //rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); rs485_send_broadcast(&newline, 1); 800254c: 1dfb adds r3, r7, #7 800254e: 2101 movs r1, #1 8002550: 4618 mov r0, r3 8002552: f000 fadb bl 8002b0c //} if (g_ph_filter.value_valid) // pH 8002556: 4b29 ldr r3, [pc, #164] @ (80025fc ) 8002558: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800255c: 2b00 cmp r3, #0 800255e: d025 beq.n 80025ac { uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value); 8002560: 4b26 ldr r3, [pc, #152] @ (80025fc ) 8002562: 6b9b ldr r3, [r3, #56] @ 0x38 8002564: 4618 mov r0, r3 8002566: f7ff fabb bl 8001ae0 800256a: 4603 mov r3, r0 800256c: 837b strh r3, [r7, #26] intToStr(ph_final, tempString); 800256e: f9b7 301a ldrsh.w r3, [r7, #26] 8002572: f107 0208 add.w r2, r7, #8 8002576: 4611 mov r1, r2 8002578: 4618 mov r0, r3 800257a: f000 f9a5 bl 80028c8 //float ph_final = g_ph_filter.filtered_value; //FloatToString(tempString, ph_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 800257e: f107 0308 add.w r3, r7, #8 8002582: 4618 mov r0, r3 8002584: f7fd fde2 bl 800014c 8002588: 4603 mov r3, r0 800258a: b29a uxth r2, r3 800258c: f107 0308 add.w r3, r7, #8 8002590: 4611 mov r1, r2 8002592: 4618 mov r0, r3 8002594: f000 faba bl 8002b0c rs485_send_broadcast(&newline, 1); 8002598: 1dfb adds r3, r7, #7 800259a: 2101 movs r1, #1 800259c: 4618 mov r0, r3 800259e: f000 fab5 bl 8002b0c rs485_send_broadcast(&newline, 1); 80025a2: 1dfb adds r3, r7, #7 80025a4: 2101 movs r1, #1 80025a6: 4618 mov r0, r3 80025a8: f000 fab0 bl 8002b0c } rs485_send_broadcast(&newline, 1); 80025ac: 1dfb adds r3, r7, #7 80025ae: 2101 movs r1, #1 80025b0: 4618 mov r0, r3 80025b2: f000 faab bl 8002b0c } // Piscar LED verde em PB4 a cada 1 segundo if ((current_millis - previous_millis_green) >= 1000) 80025b6: 6aba ldr r2, [r7, #40] @ 0x28 80025b8: 6b7b ldr r3, [r7, #52] @ 0x34 80025ba: 1ad3 subs r3, r2, r3 80025bc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80025c0: f4ff af19 bcc.w 80023f6 { previous_millis_green = current_millis; 80025c4: 6abb ldr r3, [r7, #40] @ 0x28 80025c6: 637b str r3, [r7, #52] @ 0x34 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4); 80025c8: 2110 movs r1, #16 80025ca: 4803 ldr r0, [pc, #12] @ (80025d8 ) 80025cc: f001 faf5 bl 8003bba AD5934_Process_System(); 80025d0: e711 b.n 80023f6 80025d2: bf00 nop 80025d4: 2000030c .word 0x2000030c 80025d8: 40010c00 .word 0x40010c00 80025dc: 20000084 .word 0x20000084 80025e0: 10624dd3 .word 0x10624dd3 80025e4: 2000010c .word 0x2000010c 80025e8: 20000094 .word 0x20000094 80025ec: 20000088 .word 0x20000088 80025f0: 2000014c .word 0x2000014c 80025f4: 20000152 .word 0x20000152 80025f8: 2000008c .word 0x2000008c 80025fc: 200001c4 .word 0x200001c4 08002600 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8002600: b580 push {r7, lr} 8002602: b094 sub sp, #80 @ 0x50 8002604: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8002606: f107 0328 add.w r3, r7, #40 @ 0x28 800260a: 2228 movs r2, #40 @ 0x28 800260c: 2100 movs r1, #0 800260e: 4618 mov r0, r3 8002610: f004 f9f0 bl 80069f4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8002614: f107 0314 add.w r3, r7, #20 8002618: 2200 movs r2, #0 800261a: 601a str r2, [r3, #0] 800261c: 605a str r2, [r3, #4] 800261e: 609a str r2, [r3, #8] 8002620: 60da str r2, [r3, #12] 8002622: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8002624: 1d3b adds r3, r7, #4 8002626: 2200 movs r2, #0 8002628: 601a str r2, [r3, #0] 800262a: 605a str r2, [r3, #4] 800262c: 609a str r2, [r3, #8] 800262e: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8002630: 2301 movs r3, #1 8002632: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8002634: f44f 3380 mov.w r3, #65536 @ 0x10000 8002638: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 800263a: 2300 movs r3, #0 800263c: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800263e: f107 0328 add.w r3, r7, #40 @ 0x28 8002642: 4618 mov r0, r3 8002644: f002 fb06 bl 8004c54 8002648: 4603 mov r3, r0 800264a: 2b00 cmp r3, #0 800264c: d001 beq.n 8002652 { Error_Handler(); 800264e: f000 fa1f bl 8002a90 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8002652: 230f movs r3, #15 8002654: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8002656: 2301 movs r3, #1 8002658: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800265a: 2300 movs r3, #0 800265c: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800265e: 2300 movs r3, #0 8002660: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8002662: 2300 movs r3, #0 8002664: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8002666: f107 0314 add.w r3, r7, #20 800266a: 2100 movs r1, #0 800266c: 4618 mov r0, r3 800266e: f002 fd73 bl 8005158 8002672: 4603 mov r3, r0 8002674: 2b00 cmp r3, #0 8002676: d001 beq.n 800267c { Error_Handler(); 8002678: f000 fa0a bl 8002a90 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 800267c: 2302 movs r3, #2 800267e: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 8002680: f44f 4340 mov.w r3, #49152 @ 0xc000 8002684: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8002686: 1d3b adds r3, r7, #4 8002688: 4618 mov r0, r3 800268a: f002 fef5 bl 8005478 800268e: 4603 mov r3, r0 8002690: 2b00 cmp r3, #0 8002692: d001 beq.n 8002698 { Error_Handler(); 8002694: f000 f9fc bl 8002a90 } } 8002698: bf00 nop 800269a: 3750 adds r7, #80 @ 0x50 800269c: 46bd mov sp, r7 800269e: bd80 pop {r7, pc} 080026a0 : * @param val - value to be converted * * @return None. *******************************************************************************/ void FloatToString(uint8_t *buf, double val) { 80026a0: b5b0 push {r4, r5, r7, lr} 80026a2: b096 sub sp, #88 @ 0x58 80026a4: af00 add r7, sp, #0 80026a6: 60f8 str r0, [r7, #12] 80026a8: e9c7 2300 strd r2, r3, [r7] char temp[20]; // Buffer auxiliar para construção segura int i = 0; 80026ac: 2300 movs r3, #0 80026ae: 657b str r3, [r7, #84] @ 0x54 // 1. Tratar sinal negativo if (val < 0) { 80026b0: f04f 0200 mov.w r2, #0 80026b4: f04f 0300 mov.w r3, #0 80026b8: e9d7 0100 ldrd r0, r1, [r7] 80026bc: f7fe f894 bl 80007e8 <__aeabi_dcmplt> 80026c0: 4603 mov r3, r0 80026c2: 2b00 cmp r3, #0 80026c4: d00d beq.n 80026e2 temp[i++] = '-'; 80026c6: 6d7b ldr r3, [r7, #84] @ 0x54 80026c8: 1c5a adds r2, r3, #1 80026ca: 657a str r2, [r7, #84] @ 0x54 80026cc: 3358 adds r3, #88 @ 0x58 80026ce: 443b add r3, r7 80026d0: 222d movs r2, #45 @ 0x2d 80026d2: f803 2c30 strb.w r2, [r3, #-48] val = -val; 80026d6: 683c ldr r4, [r7, #0] 80026d8: 687b ldr r3, [r7, #4] 80026da: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000 80026de: e9c7 4500 strd r4, r5, [r7] } // 2. Separar parte inteira e fracionária long intPart = (long)val; 80026e2: e9d7 0100 ldrd r0, r1, [r7] 80026e6: f7fe f8a7 bl 8000838 <__aeabi_d2iz> 80026ea: 4603 mov r3, r0 80026ec: 653b str r3, [r7, #80] @ 0x50 // Multiplicamos por 1000 para obter 3 casas decimais fixas int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5); 80026ee: 6d38 ldr r0, [r7, #80] @ 0x50 80026f0: f7fd ffb0 bl 8000654 <__aeabi_i2d> 80026f4: 4602 mov r2, r0 80026f6: 460b mov r3, r1 80026f8: e9d7 0100 ldrd r0, r1, [r7] 80026fc: f7fd fe5c bl 80003b8 <__aeabi_dsub> 8002700: 4602 mov r2, r0 8002702: 460b mov r3, r1 8002704: 4610 mov r0, r2 8002706: 4619 mov r1, r3 8002708: f04f 0200 mov.w r2, #0 800270c: 4b6a ldr r3, [pc, #424] @ (80028b8 ) 800270e: f7fd fd25 bl 800015c <__aeabi_dmul> 8002712: 4602 mov r2, r0 8002714: 460b mov r3, r1 8002716: 4610 mov r0, r2 8002718: 4619 mov r1, r3 800271a: f04f 0200 mov.w r2, #0 800271e: 4b67 ldr r3, [pc, #412] @ (80028bc ) 8002720: f7fd fe4c bl 80003bc <__adddf3> 8002724: 4602 mov r2, r0 8002726: 460b mov r3, r1 8002728: 4610 mov r0, r2 800272a: 4619 mov r1, r3 800272c: f7fe f884 bl 8000838 <__aeabi_d2iz> 8002730: 4603 mov r3, r0 8002732: 63fb str r3, [r7, #60] @ 0x3c // 3. Converter a parte inteira para o buffer temp // Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro char intRev[12]; int j = 0; 8002734: 2300 movs r3, #0 8002736: 64fb str r3, [r7, #76] @ 0x4c if (intPart == 0) { 8002738: 6d3b ldr r3, [r7, #80] @ 0x50 800273a: 2b00 cmp r3, #0 800273c: d126 bne.n 800278c intRev[j++] = '0'; 800273e: 6cfb ldr r3, [r7, #76] @ 0x4c 8002740: 1c5a adds r2, r3, #1 8002742: 64fa str r2, [r7, #76] @ 0x4c 8002744: 3358 adds r3, #88 @ 0x58 8002746: 443b add r3, r7 8002748: 2230 movs r2, #48 @ 0x30 800274a: f803 2c3c strb.w r2, [r3, #-60] 800274e: e020 b.n 8002792 } else { while (intPart > 0) { intRev[j++] = (intPart % 10) + '0'; 8002750: 6d3a ldr r2, [r7, #80] @ 0x50 8002752: 4b5b ldr r3, [pc, #364] @ (80028c0 ) 8002754: fb83 1302 smull r1, r3, r3, r2 8002758: 1099 asrs r1, r3, #2 800275a: 17d3 asrs r3, r2, #31 800275c: 1ac9 subs r1, r1, r3 800275e: 460b mov r3, r1 8002760: 009b lsls r3, r3, #2 8002762: 440b add r3, r1 8002764: 005b lsls r3, r3, #1 8002766: 1ad1 subs r1, r2, r3 8002768: b2ca uxtb r2, r1 800276a: 6cfb ldr r3, [r7, #76] @ 0x4c 800276c: 1c59 adds r1, r3, #1 800276e: 64f9 str r1, [r7, #76] @ 0x4c 8002770: 3230 adds r2, #48 @ 0x30 8002772: b2d2 uxtb r2, r2 8002774: 3358 adds r3, #88 @ 0x58 8002776: 443b add r3, r7 8002778: f803 2c3c strb.w r2, [r3, #-60] intPart /= 10; 800277c: 6d3b ldr r3, [r7, #80] @ 0x50 800277e: 4a50 ldr r2, [pc, #320] @ (80028c0 ) 8002780: fb82 1203 smull r1, r2, r2, r3 8002784: 1092 asrs r2, r2, #2 8002786: 17db asrs r3, r3, #31 8002788: 1ad3 subs r3, r2, r3 800278a: 653b str r3, [r7, #80] @ 0x50 while (intPart > 0) { 800278c: 6d3b ldr r3, [r7, #80] @ 0x50 800278e: 2b00 cmp r3, #0 8002790: dcde bgt.n 8002750 } } // Inverter a parte inteira de volta para o buffer principal for (int k = j - 1; k >= 0; k--) { 8002792: 6cfb ldr r3, [r7, #76] @ 0x4c 8002794: 3b01 subs r3, #1 8002796: 64bb str r3, [r7, #72] @ 0x48 8002798: e00e b.n 80027b8 temp[i++] = intRev[k]; 800279a: 6d7b ldr r3, [r7, #84] @ 0x54 800279c: 1c5a adds r2, r3, #1 800279e: 657a str r2, [r7, #84] @ 0x54 80027a0: f107 011c add.w r1, r7, #28 80027a4: 6cba ldr r2, [r7, #72] @ 0x48 80027a6: 440a add r2, r1 80027a8: 7812 ldrb r2, [r2, #0] 80027aa: 3358 adds r3, #88 @ 0x58 80027ac: 443b add r3, r7 80027ae: f803 2c30 strb.w r2, [r3, #-48] for (int k = j - 1; k >= 0; k--) { 80027b2: 6cbb ldr r3, [r7, #72] @ 0x48 80027b4: 3b01 subs r3, #1 80027b6: 64bb str r3, [r7, #72] @ 0x48 80027b8: 6cbb ldr r3, [r7, #72] @ 0x48 80027ba: 2b00 cmp r3, #0 80027bc: daed bge.n 800279a } // 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas) temp[i++] = '.'; 80027be: 6d7b ldr r3, [r7, #84] @ 0x54 80027c0: 1c5a adds r2, r3, #1 80027c2: 657a str r2, [r7, #84] @ 0x54 80027c4: 3358 adds r3, #88 @ 0x58 80027c6: 443b add r3, r7 80027c8: 222e movs r2, #46 @ 0x2e 80027ca: f803 2c30 strb.w r2, [r3, #-48] // Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5) int fracBuffer[3]; fracBuffer[2] = fracPart % 10; // Unidade 80027ce: 6bf9 ldr r1, [r7, #60] @ 0x3c 80027d0: 4b3b ldr r3, [pc, #236] @ (80028c0 ) 80027d2: fb83 2301 smull r2, r3, r3, r1 80027d6: 109a asrs r2, r3, #2 80027d8: 17cb asrs r3, r1, #31 80027da: 1ad2 subs r2, r2, r3 80027dc: 4613 mov r3, r2 80027de: 009b lsls r3, r3, #2 80027e0: 4413 add r3, r2 80027e2: 005b lsls r3, r3, #1 80027e4: 1aca subs r2, r1, r3 80027e6: 61ba str r2, [r7, #24] fracBuffer[1] = (fracPart / 10) % 10; // Dezena 80027e8: 6bfb ldr r3, [r7, #60] @ 0x3c 80027ea: 4a35 ldr r2, [pc, #212] @ (80028c0 ) 80027ec: fb82 1203 smull r1, r2, r2, r3 80027f0: 1092 asrs r2, r2, #2 80027f2: 17db asrs r3, r3, #31 80027f4: 1ad1 subs r1, r2, r3 80027f6: 4b32 ldr r3, [pc, #200] @ (80028c0 ) 80027f8: fb83 2301 smull r2, r3, r3, r1 80027fc: 109a asrs r2, r3, #2 80027fe: 17cb asrs r3, r1, #31 8002800: 1ad2 subs r2, r2, r3 8002802: 4613 mov r3, r2 8002804: 009b lsls r3, r3, #2 8002806: 4413 add r3, r2 8002808: 005b lsls r3, r3, #1 800280a: 1aca subs r2, r1, r3 800280c: 617a str r2, [r7, #20] fracBuffer[0] = (fracPart / 100) % 10; // Centena 800280e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002810: 4a2c ldr r2, [pc, #176] @ (80028c4 ) 8002812: fb82 1203 smull r1, r2, r2, r3 8002816: 1152 asrs r2, r2, #5 8002818: 17db asrs r3, r3, #31 800281a: 1ad1 subs r1, r2, r3 800281c: 4b28 ldr r3, [pc, #160] @ (80028c0 ) 800281e: fb83 2301 smull r2, r3, r3, r1 8002822: 109a asrs r2, r3, #2 8002824: 17cb asrs r3, r1, #31 8002826: 1ad2 subs r2, r2, r3 8002828: 4613 mov r3, r2 800282a: 009b lsls r3, r3, #2 800282c: 4413 add r3, r2 800282e: 005b lsls r3, r3, #1 8002830: 1aca subs r2, r1, r3 8002832: 613a str r2, [r7, #16] for (int k = 0; k <= 2; k++) { 8002834: 2300 movs r3, #0 8002836: 647b str r3, [r7, #68] @ 0x44 8002838: e012 b.n 8002860 temp[i++] = fracBuffer[k] + '0'; 800283a: 6c7b ldr r3, [r7, #68] @ 0x44 800283c: 009b lsls r3, r3, #2 800283e: 3358 adds r3, #88 @ 0x58 8002840: 443b add r3, r7 8002842: f853 3c48 ldr.w r3, [r3, #-72] 8002846: b2da uxtb r2, r3 8002848: 6d7b ldr r3, [r7, #84] @ 0x54 800284a: 1c59 adds r1, r3, #1 800284c: 6579 str r1, [r7, #84] @ 0x54 800284e: 3230 adds r2, #48 @ 0x30 8002850: b2d2 uxtb r2, r2 8002852: 3358 adds r3, #88 @ 0x58 8002854: 443b add r3, r7 8002856: f803 2c30 strb.w r2, [r3, #-48] for (int k = 0; k <= 2; k++) { 800285a: 6c7b ldr r3, [r7, #68] @ 0x44 800285c: 3301 adds r3, #1 800285e: 647b str r3, [r7, #68] @ 0x44 8002860: 6c7b ldr r3, [r7, #68] @ 0x44 8002862: 2b02 cmp r3, #2 8002864: dde9 ble.n 800283a } // 5. Finalizar a string com o caractere nulo temp[i] = '\0'; 8002866: f107 0228 add.w r2, r7, #40 @ 0x28 800286a: 6d7b ldr r3, [r7, #84] @ 0x54 800286c: 4413 add r3, r2 800286e: 2200 movs r2, #0 8002870: 701a strb r2, [r3, #0] // 6. Copiar para o buffer de destino final (sem risco de lixo) int destIdx = 0; 8002872: 2300 movs r3, #0 8002874: 643b str r3, [r7, #64] @ 0x40 while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança 8002876: e00b b.n 8002890 buf[destIdx] = temp[destIdx]; 8002878: 6c3b ldr r3, [r7, #64] @ 0x40 800287a: 68fa ldr r2, [r7, #12] 800287c: 4413 add r3, r2 800287e: f107 0128 add.w r1, r7, #40 @ 0x28 8002882: 6c3a ldr r2, [r7, #64] @ 0x40 8002884: 440a add r2, r1 8002886: 7812 ldrb r2, [r2, #0] 8002888: 701a strb r2, [r3, #0] destIdx++; 800288a: 6c3b ldr r3, [r7, #64] @ 0x40 800288c: 3301 adds r3, #1 800288e: 643b str r3, [r7, #64] @ 0x40 while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança 8002890: f107 0228 add.w r2, r7, #40 @ 0x28 8002894: 6c3b ldr r3, [r7, #64] @ 0x40 8002896: 4413 add r3, r2 8002898: 781b ldrb r3, [r3, #0] 800289a: 2b00 cmp r3, #0 800289c: d002 beq.n 80028a4 800289e: 6c3b ldr r3, [r7, #64] @ 0x40 80028a0: 2b0e cmp r3, #14 80028a2: dde9 ble.n 8002878 } buf[destIdx] = '\0'; 80028a4: 6c3b ldr r3, [r7, #64] @ 0x40 80028a6: 68fa ldr r2, [r7, #12] 80028a8: 4413 add r3, r2 80028aa: 2200 movs r2, #0 80028ac: 701a strb r2, [r3, #0] } 80028ae: bf00 nop 80028b0: 3758 adds r7, #88 @ 0x58 80028b2: 46bd mov sp, r7 80028b4: bdb0 pop {r4, r5, r7, pc} 80028b6: bf00 nop 80028b8: 408f4000 .word 0x408f4000 80028bc: 3fe00000 .word 0x3fe00000 80028c0: 66666667 .word 0x66666667 80028c4: 51eb851f .word 0x51eb851f 080028c8 : void intToStr(int16_t N, uint8_t *str) { 80028c8: b480 push {r7} 80028ca: b087 sub sp, #28 80028cc: af00 add r7, sp, #0 80028ce: 4603 mov r3, r0 80028d0: 6039 str r1, [r7, #0] 80028d2: 80fb strh r3, [r7, #6] int16_t i = 0; 80028d4: 2300 movs r3, #0 80028d6: 82fb strh r3, [r7, #22] int16_t sign = N; 80028d8: 88fb ldrh r3, [r7, #6] 80028da: 823b strh r3, [r7, #16] uint8_t max_len = 15; // Tamanho máximo do buffer 80028dc: 230f movs r3, #15 80028de: 73fb strb r3, [r7, #15] uint8_t width = 4; // mínimo 4 caracteres 80028e0: 2304 movs r3, #4 80028e2: 757b strb r3, [r7, #21] // Trata o caso do número zero isoladamente if (N == 0) 80028e4: f9b7 3006 ldrsh.w r3, [r7, #6] 80028e8: 2b00 cmp r3, #0 80028ea: d127 bne.n 800293c { // Preenche com zeros à esquerda até atingir a largura desejada while (width > 1 && i < (max_len - 1)) 80028ec: e00c b.n 8002908 { str[i++] = '0'; 80028ee: f9b7 2016 ldrsh.w r2, [r7, #22] 80028f2: b293 uxth r3, r2 80028f4: 3301 adds r3, #1 80028f6: b29b uxth r3, r3 80028f8: 82fb strh r3, [r7, #22] 80028fa: 683b ldr r3, [r7, #0] 80028fc: 4413 add r3, r2 80028fe: 2230 movs r2, #48 @ 0x30 8002900: 701a strb r2, [r3, #0] width--; 8002902: 7d7b ldrb r3, [r7, #21] 8002904: 3b01 subs r3, #1 8002906: 757b strb r3, [r7, #21] while (width > 1 && i < (max_len - 1)) 8002908: 7d7b ldrb r3, [r7, #21] 800290a: 2b01 cmp r3, #1 800290c: d905 bls.n 800291a 800290e: f9b7 2016 ldrsh.w r2, [r7, #22] 8002912: 7bfb ldrb r3, [r7, #15] 8002914: 3b01 subs r3, #1 8002916: 429a cmp r2, r3 8002918: dbe9 blt.n 80028ee } str[i++] = '0'; 800291a: f9b7 2016 ldrsh.w r2, [r7, #22] 800291e: b293 uxth r3, r2 8002920: 3301 adds r3, #1 8002922: b29b uxth r3, r3 8002924: 82fb strh r3, [r7, #22] 8002926: 683b ldr r3, [r7, #0] 8002928: 4413 add r3, r2 800292a: 2230 movs r2, #48 @ 0x30 800292c: 701a strb r2, [r3, #0] str[i] = '\0'; 800292e: f9b7 3016 ldrsh.w r3, [r7, #22] 8002932: 683a ldr r2, [r7, #0] 8002934: 4413 add r3, r2 8002936: 2200 movs r2, #0 8002938: 701a strb r2, [r3, #0] return; 800293a: e08a b.n 8002a52 } if (N < 0) 800293c: f9b7 3006 ldrsh.w r3, [r7, #6] 8002940: 2b00 cmp r3, #0 8002942: da2d bge.n 80029a0 N = -N; 8002944: 88fb ldrh r3, [r7, #6] 8002946: 425b negs r3, r3 8002948: b29b uxth r3, r3 800294a: 80fb strh r3, [r7, #6] // Extração dos dígitos while (N > 0) 800294c: e028 b.n 80029a0 { if (i >= (max_len - 1)) 800294e: f9b7 2016 ldrsh.w r2, [r7, #22] 8002952: 7bfb ldrb r3, [r7, #15] 8002954: 3b01 subs r3, #1 8002956: 429a cmp r2, r3 8002958: da27 bge.n 80029aa break; // Proteção de estouro str[i++] = (N % 10) + '0'; 800295a: f9b7 2006 ldrsh.w r2, [r7, #6] 800295e: 4b3f ldr r3, [pc, #252] @ (8002a5c ) 8002960: fb83 1302 smull r1, r3, r3, r2 8002964: 1099 asrs r1, r3, #2 8002966: 17d3 asrs r3, r2, #31 8002968: 1ac9 subs r1, r1, r3 800296a: 460b mov r3, r1 800296c: 009b lsls r3, r3, #2 800296e: 440b add r3, r1 8002970: 005b lsls r3, r3, #1 8002972: 1ad3 subs r3, r2, r3 8002974: b21b sxth r3, r3 8002976: b2da uxtb r2, r3 8002978: f9b7 1016 ldrsh.w r1, [r7, #22] 800297c: b28b uxth r3, r1 800297e: 3301 adds r3, #1 8002980: b29b uxth r3, r3 8002982: 82fb strh r3, [r7, #22] 8002984: 683b ldr r3, [r7, #0] 8002986: 440b add r3, r1 8002988: 3230 adds r2, #48 @ 0x30 800298a: b2d2 uxtb r2, r2 800298c: 701a strb r2, [r3, #0] N /= 10; 800298e: f9b7 3006 ldrsh.w r3, [r7, #6] 8002992: 4a32 ldr r2, [pc, #200] @ (8002a5c ) 8002994: fb82 1203 smull r1, r2, r2, r3 8002998: 1092 asrs r2, r2, #2 800299a: 17db asrs r3, r3, #31 800299c: 1ad3 subs r3, r2, r3 800299e: 80fb strh r3, [r7, #6] while (N > 0) 80029a0: f9b7 3006 ldrsh.w r3, [r7, #6] 80029a4: 2b00 cmp r3, #0 80029a6: dcd2 bgt.n 800294e 80029a8: e000 b.n 80029ac break; // Proteção de estouro 80029aa: bf00 nop } // Adiciona o sinal de menos se necessário if (sign < 0) 80029ac: f9b7 3010 ldrsh.w r3, [r7, #16] 80029b0: 2b00 cmp r3, #0 80029b2: da1a bge.n 80029ea { if (i < (max_len - 1)) 80029b4: f9b7 2016 ldrsh.w r2, [r7, #22] 80029b8: 7bfb ldrb r3, [r7, #15] 80029ba: 3b01 subs r3, #1 80029bc: 429a cmp r2, r3 80029be: da14 bge.n 80029ea str[i++] = '-'; 80029c0: f9b7 2016 ldrsh.w r2, [r7, #22] 80029c4: b293 uxth r3, r2 80029c6: 3301 adds r3, #1 80029c8: b29b uxth r3, r3 80029ca: 82fb strh r3, [r7, #22] 80029cc: 683b ldr r3, [r7, #0] 80029ce: 4413 add r3, r2 80029d0: 222d movs r2, #45 @ 0x2d 80029d2: 701a strb r2, [r3, #0] } // Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal) while (i < width && i < (max_len - 1)) 80029d4: e009 b.n 80029ea { str[i++] = '0'; 80029d6: f9b7 2016 ldrsh.w r2, [r7, #22] 80029da: b293 uxth r3, r2 80029dc: 3301 adds r3, #1 80029de: b29b uxth r3, r3 80029e0: 82fb strh r3, [r7, #22] 80029e2: 683b ldr r3, [r7, #0] 80029e4: 4413 add r3, r2 80029e6: 2230 movs r2, #48 @ 0x30 80029e8: 701a strb r2, [r3, #0] while (i < width && i < (max_len - 1)) 80029ea: f9b7 2016 ldrsh.w r2, [r7, #22] 80029ee: 7d7b ldrb r3, [r7, #21] 80029f0: 429a cmp r2, r3 80029f2: da05 bge.n 8002a00 80029f4: f9b7 2016 ldrsh.w r2, [r7, #22] 80029f8: 7bfb ldrb r3, [r7, #15] 80029fa: 3b01 subs r3, #1 80029fc: 429a cmp r2, r3 80029fe: dbea blt.n 80029d6 } str[i] = '\0'; 8002a00: f9b7 3016 ldrsh.w r3, [r7, #22] 8002a04: 683a ldr r2, [r7, #0] 8002a06: 4413 add r3, r2 8002a08: 2200 movs r2, #0 8002a0a: 701a strb r2, [r3, #0] // Inverte a string para colocar na ordem correta for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002a0c: 2300 movs r3, #0 8002a0e: 753b strb r3, [r7, #20] 8002a10: 8afb ldrh r3, [r7, #22] 8002a12: b2db uxtb r3, r3 8002a14: 3b01 subs r3, #1 8002a16: 74fb strb r3, [r7, #19] 8002a18: e017 b.n 8002a4a { uint8_t temp = str[j]; 8002a1a: 7d3b ldrb r3, [r7, #20] 8002a1c: 683a ldr r2, [r7, #0] 8002a1e: 4413 add r3, r2 8002a20: 781b ldrb r3, [r3, #0] 8002a22: 73bb strb r3, [r7, #14] str[j] = str[k]; 8002a24: 7cfb ldrb r3, [r7, #19] 8002a26: 683a ldr r2, [r7, #0] 8002a28: 441a add r2, r3 8002a2a: 7d3b ldrb r3, [r7, #20] 8002a2c: 6839 ldr r1, [r7, #0] 8002a2e: 440b add r3, r1 8002a30: 7812 ldrb r2, [r2, #0] 8002a32: 701a strb r2, [r3, #0] str[k] = temp; 8002a34: 7cfb ldrb r3, [r7, #19] 8002a36: 683a ldr r2, [r7, #0] 8002a38: 4413 add r3, r2 8002a3a: 7bba ldrb r2, [r7, #14] 8002a3c: 701a strb r2, [r3, #0] for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002a3e: 7d3b ldrb r3, [r7, #20] 8002a40: 3301 adds r3, #1 8002a42: 753b strb r3, [r7, #20] 8002a44: 7cfb ldrb r3, [r7, #19] 8002a46: 3b01 subs r3, #1 8002a48: 74fb strb r3, [r7, #19] 8002a4a: 7d3a ldrb r2, [r7, #20] 8002a4c: 7cfb ldrb r3, [r7, #19] 8002a4e: 429a cmp r2, r3 8002a50: d3e3 bcc.n 8002a1a } } 8002a52: 371c adds r7, #28 8002a54: 46bd mov sp, r7 8002a56: bc80 pop {r7} 8002a58: 4770 bx lr 8002a5a: bf00 nop 8002a5c: 66666667 .word 0x66666667 08002a60 : } /* TIM3 Timer Interrupt */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8002a60: b480 push {r7} 8002a62: b083 sub sp, #12 8002a64: af00 add r7, sp, #0 8002a66: 6078 str r0, [r7, #4] if (htim->Instance == TIM3) 8002a68: 687b ldr r3, [r7, #4] 8002a6a: 681b ldr r3, [r3, #0] 8002a6c: 4a06 ldr r2, [pc, #24] @ (8002a88 ) 8002a6e: 4293 cmp r3, r2 8002a70: d104 bne.n 8002a7c { g_ms_counter++; /* Relógio global do sistema */ 8002a72: 4b06 ldr r3, [pc, #24] @ (8002a8c ) 8002a74: 681b ldr r3, [r3, #0] 8002a76: 3301 adds r3, #1 8002a78: 4a04 ldr r2, [pc, #16] @ (8002a8c ) 8002a7a: 6013 str r3, [r2, #0] } } 8002a7c: bf00 nop 8002a7e: 370c adds r7, #12 8002a80: 46bd mov sp, r7 8002a82: bc80 pop {r7} 8002a84: 4770 bx lr 8002a86: bf00 nop 8002a88: 40000400 .word 0x40000400 8002a8c: 20000084 .word 0x20000084 08002a90 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002a90: b480 push {r7} 8002a92: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8002a94: b672 cpsid i } 8002a96: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8002a98: bf00 nop 8002a9a: e7fd b.n 8002a98 08002a9c : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 8002a9c: b480 push {r7} 8002a9e: b083 sub sp, #12 8002aa0: af00 add r7, sp, #0 8002aa2: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 8002aa4: 687b ldr r3, [r7, #4] 8002aa6: 689b ldr r3, [r3, #8] } 8002aa8: 4618 mov r0, r3 8002aaa: 370c adds r7, #12 8002aac: 46bd mov sp, r7 8002aae: bc80 pop {r7} 8002ab0: 4770 bx lr ... 08002ab4 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 8002ab4: b580 push {r7, lr} 8002ab6: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 8002ab8: f000 f864 bl 8002b84 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 8002abc: f000 f8a8 bl 8002c10 /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 8002ac0: f000 f808 bl 8002ad4 8002ac4: 4603 mov r3, r0 8002ac6: 461a mov r2, r3 8002ac8: 4b01 ldr r3, [pc, #4] @ (8002ad0 ) 8002aca: 709a strb r2, [r3, #2] } 8002acc: bf00 nop 8002ace: bd80 pop {r7, pc} 8002ad0: 200002c0 .word 0x200002c0 08002ad4 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 8002ad4: b598 push {r3, r4, r7, lr} 8002ad6: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 8002ad8: 480a ldr r0, [pc, #40] @ (8002b04 ) 8002ada: f7ff ffdf bl 8002a9c 8002ade: 4603 mov r3, r0 8002ae0: 0a1b lsrs r3, r3, #8 8002ae2: b2db uxtb r3, r3 8002ae4: f023 030f bic.w r3, r3, #15 8002ae8: b2dc uxtb r4, r3 8002aea: 4807 ldr r0, [pc, #28] @ (8002b08 ) 8002aec: f7ff ffd6 bl 8002a9c 8002af0: 4603 mov r3, r0 8002af2: 089b lsrs r3, r3, #2 8002af4: b2db uxtb r3, r3 8002af6: f003 030f and.w r3, r3, #15 8002afa: b2db uxtb r3, r3 8002afc: 4323 orrs r3, r4 8002afe: b2db uxtb r3, r3 } 8002b00: 4618 mov r0, r3 8002b02: bd98 pop {r3, r4, r7, pc} 8002b04: 40010c00 .word 0x40010c00 8002b08: 40010800 .word 0x40010800 08002b0c : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 8002b0c: b580 push {r7, lr} 8002b0e: b084 sub sp, #16 8002b10: af00 add r7, sp, #0 8002b12: 6078 str r0, [r7, #4] 8002b14: 460b mov r3, r1 8002b16: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 8002b18: f000 f81c bl 8002b54 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 8002b1c: 2300 movs r3, #0 8002b1e: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8002b20: f107 010e add.w r1, r7, #14 8002b24: f04f 33ff mov.w r3, #4294967295 8002b28: 2201 movs r2, #1 8002b2a: 4809 ldr r0, [pc, #36] @ (8002b50 ) 8002b2c: f003 f99c bl 8005e68 /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 8002b30: 887a ldrh r2, [r7, #2] 8002b32: f04f 33ff mov.w r3, #4294967295 8002b36: 6879 ldr r1, [r7, #4] 8002b38: 4805 ldr r0, [pc, #20] @ (8002b50 ) 8002b3a: f003 f995 bl 8005e68 8002b3e: 4603 mov r3, r0 8002b40: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 8002b42: f000 f813 bl 8002b6c return status; 8002b46: 7bfb ldrb r3, [r7, #15] } 8002b48: 4618 mov r0, r3 8002b4a: 3710 adds r7, #16 8002b4c: 46bd mov sp, r7 8002b4e: bd80 pop {r7, pc} 8002b50: 200002c4 .word 0x200002c4 08002b54 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 8002b54: b580 push {r7, lr} 8002b56: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 8002b58: 2201 movs r2, #1 8002b5a: f44f 5180 mov.w r1, #4096 @ 0x1000 8002b5e: 4802 ldr r0, [pc, #8] @ (8002b68 ) 8002b60: f001 f813 bl 8003b8a } 8002b64: bf00 nop 8002b66: bd80 pop {r7, pc} 8002b68: 40010800 .word 0x40010800 08002b6c : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 8002b6c: b580 push {r7, lr} 8002b6e: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 8002b70: 2200 movs r2, #0 8002b72: f44f 5180 mov.w r1, #4096 @ 0x1000 8002b76: 4802 ldr r0, [pc, #8] @ (8002b80 ) 8002b78: f001 f807 bl 8003b8a } 8002b7c: bf00 nop 8002b7e: bd80 pop {r7, pc} 8002b80: 40010800 .word 0x40010800 08002b84 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 8002b84: b580 push {r7, lr} 8002b86: b086 sub sp, #24 8002b88: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002b8a: f107 0308 add.w r3, r7, #8 8002b8e: 2200 movs r2, #0 8002b90: 601a str r2, [r3, #0] 8002b92: 605a str r2, [r3, #4] 8002b94: 609a str r2, [r3, #8] 8002b96: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002b98: 4b1a ldr r3, [pc, #104] @ (8002c04 ) 8002b9a: 699b ldr r3, [r3, #24] 8002b9c: 4a19 ldr r2, [pc, #100] @ (8002c04 ) 8002b9e: f043 0304 orr.w r3, r3, #4 8002ba2: 6193 str r3, [r2, #24] 8002ba4: 4b17 ldr r3, [pc, #92] @ (8002c04 ) 8002ba6: 699b ldr r3, [r3, #24] 8002ba8: f003 0304 and.w r3, r3, #4 8002bac: 607b str r3, [r7, #4] 8002bae: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002bb0: 4b14 ldr r3, [pc, #80] @ (8002c04 ) 8002bb2: 699b ldr r3, [r3, #24] 8002bb4: 4a13 ldr r2, [pc, #76] @ (8002c04 ) 8002bb6: f043 0308 orr.w r3, r3, #8 8002bba: 6193 str r3, [r2, #24] 8002bbc: 4b11 ldr r3, [pc, #68] @ (8002c04 ) 8002bbe: 699b ldr r3, [r3, #24] 8002bc0: f003 0308 and.w r3, r3, #8 8002bc4: 603b str r3, [r7, #0] 8002bc6: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 8002bc8: 233c movs r3, #60 @ 0x3c 8002bca: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002bcc: 2300 movs r3, #0 8002bce: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002bd0: 2301 movs r3, #1 8002bd2: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002bd4: f107 0308 add.w r3, r7, #8 8002bd8: 4619 mov r1, r3 8002bda: 480b ldr r0, [pc, #44] @ (8002c08 ) 8002bdc: f000 fe3a bl 8003854 /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 8002be0: f44f 4370 mov.w r3, #61440 @ 0xf000 8002be4: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002be6: 2300 movs r3, #0 8002be8: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002bea: 2301 movs r3, #1 8002bec: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002bee: f107 0308 add.w r3, r7, #8 8002bf2: 4619 mov r1, r3 8002bf4: 4805 ldr r0, [pc, #20] @ (8002c0c ) 8002bf6: f000 fe2d bl 8003854 } 8002bfa: bf00 nop 8002bfc: 3718 adds r7, #24 8002bfe: 46bd mov sp, r7 8002c00: bd80 pop {r7, pc} 8002c02: bf00 nop 8002c04: 40021000 .word 0x40021000 8002c08: 40010800 .word 0x40010800 8002c0c: 40010c00 .word 0x40010c00 08002c10 : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 8002c10: b580 push {r7, lr} 8002c12: b082 sub sp, #8 8002c14: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 8002c16: 4b18 ldr r3, [pc, #96] @ (8002c78 ) 8002c18: 699b ldr r3, [r3, #24] 8002c1a: 4a17 ldr r2, [pc, #92] @ (8002c78 ) 8002c1c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002c20: 6193 str r3, [r2, #24] 8002c22: 4b15 ldr r3, [pc, #84] @ (8002c78 ) 8002c24: 699b ldr r3, [r3, #24] 8002c26: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002c2a: 607b str r3, [r7, #4] 8002c2c: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 8002c2e: 4b13 ldr r3, [pc, #76] @ (8002c7c ) 8002c30: 4a13 ldr r2, [pc, #76] @ (8002c80 ) 8002c32: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002c34: 4b11 ldr r3, [pc, #68] @ (8002c7c ) 8002c36: f44f 5216 mov.w r2, #9600 @ 0x2580 8002c3a: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002c3c: 4b0f ldr r3, [pc, #60] @ (8002c7c ) 8002c3e: 2200 movs r2, #0 8002c40: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002c42: 4b0e ldr r3, [pc, #56] @ (8002c7c ) 8002c44: 2200 movs r2, #0 8002c46: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002c48: 4b0c ldr r3, [pc, #48] @ (8002c7c ) 8002c4a: 2200 movs r2, #0 8002c4c: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002c4e: 4b0b ldr r3, [pc, #44] @ (8002c7c ) 8002c50: 220c movs r2, #12 8002c52: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 8002c54: 4b09 ldr r3, [pc, #36] @ (8002c7c ) 8002c56: 2200 movs r2, #0 8002c58: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002c5a: 4b08 ldr r3, [pc, #32] @ (8002c7c ) 8002c5c: 2200 movs r2, #0 8002c5e: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002c60: 4806 ldr r0, [pc, #24] @ (8002c7c ) 8002c62: f003 f8b1 bl 8005dc8 8002c66: 4603 mov r3, r0 8002c68: 2b00 cmp r3, #0 8002c6a: d001 beq.n 8002c70 { /* Initialization Error */ while(1); 8002c6c: bf00 nop 8002c6e: e7fd b.n 8002c6c } } 8002c70: bf00 nop 8002c72: 3708 adds r7, #8 8002c74: 46bd mov sp, r7 8002c76: bd80 pop {r7, pc} 8002c78: 40021000 .word 0x40021000 8002c7c: 200002c4 .word 0x200002c4 8002c80: 40013800 .word 0x40013800 08002c84 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002c84: b480 push {r7} 8002c86: b085 sub sp, #20 8002c88: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8002c8a: 4b15 ldr r3, [pc, #84] @ (8002ce0 ) 8002c8c: 699b ldr r3, [r3, #24] 8002c8e: 4a14 ldr r2, [pc, #80] @ (8002ce0 ) 8002c90: f043 0301 orr.w r3, r3, #1 8002c94: 6193 str r3, [r2, #24] 8002c96: 4b12 ldr r3, [pc, #72] @ (8002ce0 ) 8002c98: 699b ldr r3, [r3, #24] 8002c9a: f003 0301 and.w r3, r3, #1 8002c9e: 60bb str r3, [r7, #8] 8002ca0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8002ca2: 4b0f ldr r3, [pc, #60] @ (8002ce0 ) 8002ca4: 69db ldr r3, [r3, #28] 8002ca6: 4a0e ldr r2, [pc, #56] @ (8002ce0 ) 8002ca8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8002cac: 61d3 str r3, [r2, #28] 8002cae: 4b0c ldr r3, [pc, #48] @ (8002ce0 ) 8002cb0: 69db ldr r3, [r3, #28] 8002cb2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002cb6: 607b str r3, [r7, #4] 8002cb8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8002cba: 4b0a ldr r3, [pc, #40] @ (8002ce4 ) 8002cbc: 685b ldr r3, [r3, #4] 8002cbe: 60fb str r3, [r7, #12] 8002cc0: 68fb ldr r3, [r7, #12] 8002cc2: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 8002cc6: 60fb str r3, [r7, #12] 8002cc8: 68fb ldr r3, [r7, #12] 8002cca: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8002cce: 60fb str r3, [r7, #12] 8002cd0: 4a04 ldr r2, [pc, #16] @ (8002ce4 ) 8002cd2: 68fb ldr r3, [r7, #12] 8002cd4: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002cd6: bf00 nop 8002cd8: 3714 adds r7, #20 8002cda: 46bd mov sp, r7 8002cdc: bc80 pop {r7} 8002cde: 4770 bx lr 8002ce0: 40021000 .word 0x40021000 8002ce4: 40010000 .word 0x40010000 08002ce8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8002ce8: b480 push {r7} 8002cea: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8002cec: bf00 nop 8002cee: e7fd b.n 8002cec 08002cf0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002cf0: b480 push {r7} 8002cf2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002cf4: bf00 nop 8002cf6: e7fd b.n 8002cf4 08002cf8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002cf8: b480 push {r7} 8002cfa: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8002cfc: bf00 nop 8002cfe: e7fd b.n 8002cfc 08002d00 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8002d00: b480 push {r7} 8002d02: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002d04: bf00 nop 8002d06: e7fd b.n 8002d04 08002d08 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002d08: b480 push {r7} 8002d0a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002d0c: bf00 nop 8002d0e: e7fd b.n 8002d0c 08002d10 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002d10: b480 push {r7} 8002d12: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002d14: bf00 nop 8002d16: 46bd mov sp, r7 8002d18: bc80 pop {r7} 8002d1a: 4770 bx lr 08002d1c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002d1c: b480 push {r7} 8002d1e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002d20: bf00 nop 8002d22: 46bd mov sp, r7 8002d24: bc80 pop {r7} 8002d26: 4770 bx lr 08002d28 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002d28: b480 push {r7} 8002d2a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002d2c: bf00 nop 8002d2e: 46bd mov sp, r7 8002d30: bc80 pop {r7} 8002d32: 4770 bx lr 08002d34 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002d34: b580 push {r7, lr} 8002d36: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002d38: f000 f97a bl 8003030 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002d3c: bf00 nop 8002d3e: bd80 pop {r7, pc} 08002d40 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8002d40: b580 push {r7, lr} 8002d42: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002d44: 4802 ldr r0, [pc, #8] @ (8002d50 ) 8002d46: f002 fcef bl 8005728 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 8002d4a: bf00 nop 8002d4c: bd80 pop {r7, pc} 8002d4e: bf00 nop 8002d50: 2000030c .word 0x2000030c 08002d54 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8002d54: b580 push {r7, lr} 8002d56: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8002d58: 4802 ldr r0, [pc, #8] @ (8002d64 ) 8002d5a: f003 f911 bl 8005f80 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8002d5e: bf00 nop 8002d60: bd80 pop {r7, pc} 8002d62: bf00 nop 8002d64: 20000354 .word 0x20000354 08002d68 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002d68: b480 push {r7} 8002d6a: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002d6c: bf00 nop 8002d6e: 46bd mov sp, r7 8002d70: bc80 pop {r7} 8002d72: 4770 bx lr 08002d74 : TIM_HandleTypeDef htim3; /* TIM3 init function */ void MX_TIM3_Init(void) { 8002d74: b580 push {r7, lr} 8002d76: b086 sub sp, #24 8002d78: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8002d7a: f107 0308 add.w r3, r7, #8 8002d7e: 2200 movs r2, #0 8002d80: 601a str r2, [r3, #0] 8002d82: 605a str r2, [r3, #4] 8002d84: 609a str r2, [r3, #8] 8002d86: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8002d88: 463b mov r3, r7 8002d8a: 2200 movs r2, #0 8002d8c: 601a str r2, [r3, #0] 8002d8e: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8002d90: 4b1d ldr r3, [pc, #116] @ (8002e08 ) 8002d92: 4a1e ldr r2, [pc, #120] @ (8002e0c ) 8002d94: 601a str r2, [r3, #0] htim3.Init.Prescaler = 2; 8002d96: 4b1c ldr r3, [pc, #112] @ (8002e08 ) 8002d98: 2202 movs r2, #2 8002d9a: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8002d9c: 4b1a ldr r3, [pc, #104] @ (8002e08 ) 8002d9e: 2200 movs r2, #0 8002da0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8002da2: 4b19 ldr r3, [pc, #100] @ (8002e08 ) 8002da4: f240 32e7 movw r2, #999 @ 0x3e7 8002da8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002daa: 4b17 ldr r3, [pc, #92] @ (8002e08 ) 8002dac: 2200 movs r2, #0 8002dae: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8002db0: 4b15 ldr r3, [pc, #84] @ (8002e08 ) 8002db2: 2280 movs r2, #128 @ 0x80 8002db4: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8002db6: 4814 ldr r0, [pc, #80] @ (8002e08 ) 8002db8: f002 fc14 bl 80055e4 8002dbc: 4603 mov r3, r0 8002dbe: 2b00 cmp r3, #0 8002dc0: d001 beq.n 8002dc6 { Error_Handler(); 8002dc2: f7ff fe65 bl 8002a90 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002dc6: f44f 5380 mov.w r3, #4096 @ 0x1000 8002dca: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8002dcc: f107 0308 add.w r3, r7, #8 8002dd0: 4619 mov r1, r3 8002dd2: 480d ldr r0, [pc, #52] @ (8002e08 ) 8002dd4: f002 fd98 bl 8005908 8002dd8: 4603 mov r3, r0 8002dda: 2b00 cmp r3, #0 8002ddc: d001 beq.n 8002de2 { Error_Handler(); 8002dde: f7ff fe57 bl 8002a90 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8002de2: 2300 movs r3, #0 8002de4: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8002de6: 2300 movs r3, #0 8002de8: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8002dea: 463b mov r3, r7 8002dec: 4619 mov r1, r3 8002dee: 4806 ldr r0, [pc, #24] @ (8002e08 ) 8002df0: f002 ff7a bl 8005ce8 8002df4: 4603 mov r3, r0 8002df6: 2b00 cmp r3, #0 8002df8: d001 beq.n 8002dfe { Error_Handler(); 8002dfa: f7ff fe49 bl 8002a90 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8002dfe: bf00 nop 8002e00: 3718 adds r7, #24 8002e02: 46bd mov sp, r7 8002e04: bd80 pop {r7, pc} 8002e06: bf00 nop 8002e08: 2000030c .word 0x2000030c 8002e0c: 40000400 .word 0x40000400 08002e10 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8002e10: b580 push {r7, lr} 8002e12: b084 sub sp, #16 8002e14: af00 add r7, sp, #0 8002e16: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 681b ldr r3, [r3, #0] 8002e1c: 4a0d ldr r2, [pc, #52] @ (8002e54 ) 8002e1e: 4293 cmp r3, r2 8002e20: d113 bne.n 8002e4a { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8002e22: 4b0d ldr r3, [pc, #52] @ (8002e58 ) 8002e24: 69db ldr r3, [r3, #28] 8002e26: 4a0c ldr r2, [pc, #48] @ (8002e58 ) 8002e28: f043 0302 orr.w r3, r3, #2 8002e2c: 61d3 str r3, [r2, #28] 8002e2e: 4b0a ldr r3, [pc, #40] @ (8002e58 ) 8002e30: 69db ldr r3, [r3, #28] 8002e32: f003 0302 and.w r3, r3, #2 8002e36: 60fb str r3, [r7, #12] 8002e38: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 8002e3a: 2200 movs r2, #0 8002e3c: 2100 movs r1, #0 8002e3e: 201d movs r0, #29 8002e40: f000 fc1f bl 8003682 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002e44: 201d movs r0, #29 8002e46: f000 fc38 bl 80036ba /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8002e4a: bf00 nop 8002e4c: 3710 adds r7, #16 8002e4e: 46bd mov sp, r7 8002e50: bd80 pop {r7, pc} 8002e52: bf00 nop 8002e54: 40000400 .word 0x40000400 8002e58: 40021000 .word 0x40021000 08002e5c : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 8002e5c: b580 push {r7, lr} 8002e5e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8002e60: 4b11 ldr r3, [pc, #68] @ (8002ea8 ) 8002e62: 4a12 ldr r2, [pc, #72] @ (8002eac ) 8002e64: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8002e66: 4b10 ldr r3, [pc, #64] @ (8002ea8 ) 8002e68: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8002e6c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002e6e: 4b0e ldr r3, [pc, #56] @ (8002ea8 ) 8002e70: 2200 movs r2, #0 8002e72: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002e74: 4b0c ldr r3, [pc, #48] @ (8002ea8 ) 8002e76: 2200 movs r2, #0 8002e78: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002e7a: 4b0b ldr r3, [pc, #44] @ (8002ea8 ) 8002e7c: 2200 movs r2, #0 8002e7e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002e80: 4b09 ldr r3, [pc, #36] @ (8002ea8 ) 8002e82: 220c movs r2, #12 8002e84: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8002e86: 4b08 ldr r3, [pc, #32] @ (8002ea8 ) 8002e88: 2200 movs r2, #0 8002e8a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002e8c: 4b06 ldr r3, [pc, #24] @ (8002ea8 ) 8002e8e: 2200 movs r2, #0 8002e90: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002e92: 4805 ldr r0, [pc, #20] @ (8002ea8 ) 8002e94: f002 ff98 bl 8005dc8 8002e98: 4603 mov r3, r0 8002e9a: 2b00 cmp r3, #0 8002e9c: d001 beq.n 8002ea2 { Error_Handler(); 8002e9e: f7ff fdf7 bl 8002a90 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8002ea2: bf00 nop 8002ea4: bd80 pop {r7, pc} 8002ea6: bf00 nop 8002ea8: 20000354 .word 0x20000354 8002eac: 40013800 .word 0x40013800 08002eb0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8002eb0: b580 push {r7, lr} 8002eb2: b088 sub sp, #32 8002eb4: af00 add r7, sp, #0 8002eb6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002eb8: f107 0310 add.w r3, r7, #16 8002ebc: 2200 movs r2, #0 8002ebe: 601a str r2, [r3, #0] 8002ec0: 605a str r2, [r3, #4] 8002ec2: 609a str r2, [r3, #8] 8002ec4: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 8002ec6: 687b ldr r3, [r7, #4] 8002ec8: 681b ldr r3, [r3, #0] 8002eca: 4a20 ldr r2, [pc, #128] @ (8002f4c ) 8002ecc: 4293 cmp r3, r2 8002ece: d139 bne.n 8002f44 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8002ed0: 4b1f ldr r3, [pc, #124] @ (8002f50 ) 8002ed2: 699b ldr r3, [r3, #24] 8002ed4: 4a1e ldr r2, [pc, #120] @ (8002f50 ) 8002ed6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002eda: 6193 str r3, [r2, #24] 8002edc: 4b1c ldr r3, [pc, #112] @ (8002f50 ) 8002ede: 699b ldr r3, [r3, #24] 8002ee0: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002ee4: 60fb str r3, [r7, #12] 8002ee6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002ee8: 4b19 ldr r3, [pc, #100] @ (8002f50 ) 8002eea: 699b ldr r3, [r3, #24] 8002eec: 4a18 ldr r2, [pc, #96] @ (8002f50 ) 8002eee: f043 0304 orr.w r3, r3, #4 8002ef2: 6193 str r3, [r2, #24] 8002ef4: 4b16 ldr r3, [pc, #88] @ (8002f50 ) 8002ef6: 699b ldr r3, [r3, #24] 8002ef8: f003 0304 and.w r3, r3, #4 8002efc: 60bb str r3, [r7, #8] 8002efe: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 8002f00: f44f 7300 mov.w r3, #512 @ 0x200 8002f04: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002f06: 2302 movs r3, #2 8002f08: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8002f0a: 2301 movs r3, #1 8002f0c: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 8002f0e: f107 0310 add.w r3, r7, #16 8002f12: 4619 mov r1, r3 8002f14: 480f ldr r0, [pc, #60] @ (8002f54 ) 8002f16: f000 fc9d bl 8003854 GPIO_InitStruct.Pin = RX_RS485_Pin; 8002f1a: f44f 6380 mov.w r3, #1024 @ 0x400 8002f1e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002f20: 2300 movs r3, #0 8002f22: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002f24: 2300 movs r3, #0 8002f26: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 8002f28: f107 0310 add.w r3, r7, #16 8002f2c: 4619 mov r1, r3 8002f2e: 4809 ldr r0, [pc, #36] @ (8002f54 ) 8002f30: f000 fc90 bl 8003854 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8002f34: 2200 movs r2, #0 8002f36: 2100 movs r1, #0 8002f38: 2025 movs r0, #37 @ 0x25 8002f3a: f000 fba2 bl 8003682 HAL_NVIC_EnableIRQ(USART1_IRQn); 8002f3e: 2025 movs r0, #37 @ 0x25 8002f40: f000 fbbb bl 80036ba /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002f44: bf00 nop 8002f46: 3720 adds r7, #32 8002f48: 46bd mov sp, r7 8002f4a: bd80 pop {r7, pc} 8002f4c: 40013800 .word 0x40013800 8002f50: 40021000 .word 0x40021000 8002f54: 40010800 .word 0x40010800 08002f58 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8002f58: f7ff ff06 bl 8002d68 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002f5c: 480b ldr r0, [pc, #44] @ (8002f8c ) ldr r1, =_edata 8002f5e: 490c ldr r1, [pc, #48] @ (8002f90 ) ldr r2, =_sidata 8002f60: 4a0c ldr r2, [pc, #48] @ (8002f94 ) movs r3, #0 8002f62: 2300 movs r3, #0 b LoopCopyDataInit 8002f64: e002 b.n 8002f6c 08002f66 : CopyDataInit: ldr r4, [r2, r3] 8002f66: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002f68: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002f6a: 3304 adds r3, #4 08002f6c : LoopCopyDataInit: adds r4, r0, r3 8002f6c: 18c4 adds r4, r0, r3 cmp r4, r1 8002f6e: 428c cmp r4, r1 bcc CopyDataInit 8002f70: d3f9 bcc.n 8002f66 /* Zero fill the bss segment. */ ldr r2, =_sbss 8002f72: 4a09 ldr r2, [pc, #36] @ (8002f98 ) ldr r4, =_ebss 8002f74: 4c09 ldr r4, [pc, #36] @ (8002f9c ) movs r3, #0 8002f76: 2300 movs r3, #0 b LoopFillZerobss 8002f78: e001 b.n 8002f7e 08002f7a : FillZerobss: str r3, [r2] 8002f7a: 6013 str r3, [r2, #0] adds r2, r2, #4 8002f7c: 3204 adds r2, #4 08002f7e : LoopFillZerobss: cmp r2, r4 8002f7e: 42a2 cmp r2, r4 bcc FillZerobss 8002f80: d3fb bcc.n 8002f7a /* Call static constructors */ bl __libc_init_array 8002f82: f003 fd45 bl 8006a10 <__libc_init_array> /* Call the application's entry point.*/ bl main 8002f86: f7ff f9e1 bl 800234c

bx lr 8002f8a: 4770 bx lr ldr r0, =_sdata 8002f8c: 20000000 .word 0x20000000 ldr r1, =_edata 8002f90: 20000060 .word 0x20000060 ldr r2, =_sidata 8002f94: 08006c6c .word 0x08006c6c ldr r2, =_sbss 8002f98: 20000060 .word 0x20000060 ldr r4, =_ebss 8002f9c: 200004d8 .word 0x200004d8 08002fa0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002fa0: e7fe b.n 8002fa0 ... 08002fa4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002fa4: b580 push {r7, lr} 8002fa6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002fa8: 4b08 ldr r3, [pc, #32] @ (8002fcc ) 8002faa: 681b ldr r3, [r3, #0] 8002fac: 4a07 ldr r2, [pc, #28] @ (8002fcc ) 8002fae: f043 0310 orr.w r3, r3, #16 8002fb2: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002fb4: 2003 movs r0, #3 8002fb6: f000 fb59 bl 800366c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002fba: 200f movs r0, #15 8002fbc: f000 f808 bl 8002fd0 /* Init the low level hardware */ HAL_MspInit(); 8002fc0: f7ff fe60 bl 8002c84 /* Return function status */ return HAL_OK; 8002fc4: 2300 movs r3, #0 } 8002fc6: 4618 mov r0, r3 8002fc8: bd80 pop {r7, pc} 8002fca: bf00 nop 8002fcc: 40022000 .word 0x40022000 08002fd0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8002fd0: b580 push {r7, lr} 8002fd2: b082 sub sp, #8 8002fd4: af00 add r7, sp, #0 8002fd6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8002fd8: 4b12 ldr r3, [pc, #72] @ (8003024 ) 8002fda: 681a ldr r2, [r3, #0] 8002fdc: 4b12 ldr r3, [pc, #72] @ (8003028 ) 8002fde: 781b ldrb r3, [r3, #0] 8002fe0: 4619 mov r1, r3 8002fe2: f44f 737a mov.w r3, #1000 @ 0x3e8 8002fe6: fbb3 f3f1 udiv r3, r3, r1 8002fea: fbb2 f3f3 udiv r3, r2, r3 8002fee: 4618 mov r0, r3 8002ff0: f000 fb71 bl 80036d6 8002ff4: 4603 mov r3, r0 8002ff6: 2b00 cmp r3, #0 8002ff8: d001 beq.n 8002ffe { return HAL_ERROR; 8002ffa: 2301 movs r3, #1 8002ffc: e00e b.n 800301c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8002ffe: 687b ldr r3, [r7, #4] 8003000: 2b0f cmp r3, #15 8003002: d80a bhi.n 800301a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8003004: 2200 movs r2, #0 8003006: 6879 ldr r1, [r7, #4] 8003008: f04f 30ff mov.w r0, #4294967295 800300c: f000 fb39 bl 8003682 uwTickPrio = TickPriority; 8003010: 4a06 ldr r2, [pc, #24] @ (800302c ) 8003012: 687b ldr r3, [r7, #4] 8003014: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8003016: 2300 movs r3, #0 8003018: e000 b.n 800301c return HAL_ERROR; 800301a: 2301 movs r3, #1 } 800301c: 4618 mov r0, r3 800301e: 3708 adds r7, #8 8003020: 46bd mov sp, r7 8003022: bd80 pop {r7, pc} 8003024: 20000004 .word 0x20000004 8003028: 2000000c .word 0x2000000c 800302c: 20000008 .word 0x20000008 08003030 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8003030: b480 push {r7} 8003032: af00 add r7, sp, #0 uwTick += uwTickFreq; 8003034: 4b05 ldr r3, [pc, #20] @ (800304c ) 8003036: 781b ldrb r3, [r3, #0] 8003038: 461a mov r2, r3 800303a: 4b05 ldr r3, [pc, #20] @ (8003050 ) 800303c: 681b ldr r3, [r3, #0] 800303e: 4413 add r3, r2 8003040: 4a03 ldr r2, [pc, #12] @ (8003050 ) 8003042: 6013 str r3, [r2, #0] } 8003044: bf00 nop 8003046: 46bd mov sp, r7 8003048: bc80 pop {r7} 800304a: 4770 bx lr 800304c: 2000000c .word 0x2000000c 8003050: 2000039c .word 0x2000039c 08003054 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8003054: b480 push {r7} 8003056: af00 add r7, sp, #0 return uwTick; 8003058: 4b02 ldr r3, [pc, #8] @ (8003064 ) 800305a: 681b ldr r3, [r3, #0] } 800305c: 4618 mov r0, r3 800305e: 46bd mov sp, r7 8003060: bc80 pop {r7} 8003062: 4770 bx lr 8003064: 2000039c .word 0x2000039c 08003068 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8003068: b580 push {r7, lr} 800306a: b084 sub sp, #16 800306c: af00 add r7, sp, #0 800306e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8003070: f7ff fff0 bl 8003054 8003074: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8003076: 687b ldr r3, [r7, #4] 8003078: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800307a: 68fb ldr r3, [r7, #12] 800307c: f1b3 3fff cmp.w r3, #4294967295 8003080: d005 beq.n 800308e { wait += (uint32_t)(uwTickFreq); 8003082: 4b0a ldr r3, [pc, #40] @ (80030ac ) 8003084: 781b ldrb r3, [r3, #0] 8003086: 461a mov r2, r3 8003088: 68fb ldr r3, [r7, #12] 800308a: 4413 add r3, r2 800308c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800308e: bf00 nop 8003090: f7ff ffe0 bl 8003054 8003094: 4602 mov r2, r0 8003096: 68bb ldr r3, [r7, #8] 8003098: 1ad3 subs r3, r2, r3 800309a: 68fa ldr r2, [r7, #12] 800309c: 429a cmp r2, r3 800309e: d8f7 bhi.n 8003090 { } } 80030a0: bf00 nop 80030a2: bf00 nop 80030a4: 3710 adds r7, #16 80030a6: 46bd mov sp, r7 80030a8: bd80 pop {r7, pc} 80030aa: bf00 nop 80030ac: 2000000c .word 0x2000000c 080030b0 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80030b0: b580 push {r7, lr} 80030b2: b086 sub sp, #24 80030b4: af00 add r7, sp, #0 80030b6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80030b8: 2300 movs r3, #0 80030ba: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 80030bc: 2300 movs r3, #0 80030be: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 80030c0: 2300 movs r3, #0 80030c2: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 80030c4: 2300 movs r3, #0 80030c6: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 80030c8: 687b ldr r3, [r7, #4] 80030ca: 2b00 cmp r3, #0 80030cc: d101 bne.n 80030d2 { return HAL_ERROR; 80030ce: 2301 movs r3, #1 80030d0: e0be b.n 8003250 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80030d2: 687b ldr r3, [r7, #4] 80030d4: 689b ldr r3, [r3, #8] 80030d6: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80030d8: 687b ldr r3, [r7, #4] 80030da: 6a9b ldr r3, [r3, #40] @ 0x28 80030dc: 2b00 cmp r3, #0 80030de: d109 bne.n 80030f4 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 80030e0: 687b ldr r3, [r7, #4] 80030e2: 2200 movs r2, #0 80030e4: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 80030e6: 687b ldr r3, [r7, #4] 80030e8: 2200 movs r2, #0 80030ea: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80030ee: 6878 ldr r0, [r7, #4] 80030f0: f7fe fc2a bl 8001948 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80030f4: 6878 ldr r0, [r7, #4] 80030f6: f000 f9ab bl 8003450 80030fa: 4603 mov r3, r0 80030fc: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80030fe: 687b ldr r3, [r7, #4] 8003100: 6a9b ldr r3, [r3, #40] @ 0x28 8003102: f003 0310 and.w r3, r3, #16 8003106: 2b00 cmp r3, #0 8003108: f040 8099 bne.w 800323e 800310c: 7dfb ldrb r3, [r7, #23] 800310e: 2b00 cmp r3, #0 8003110: f040 8095 bne.w 800323e (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003114: 687b ldr r3, [r7, #4] 8003116: 6a9b ldr r3, [r3, #40] @ 0x28 8003118: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800311c: f023 0302 bic.w r3, r3, #2 8003120: f043 0202 orr.w r2, r3, #2 8003124: 687b ldr r3, [r7, #4] 8003126: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8003128: 687b ldr r3, [r7, #4] 800312a: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800312c: 687b ldr r3, [r7, #4] 800312e: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8003130: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8003132: 687b ldr r3, [r7, #4] 8003134: 7b1b ldrb r3, [r3, #12] 8003136: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8003138: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800313a: 68ba ldr r2, [r7, #8] 800313c: 4313 orrs r3, r2 800313e: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8003140: 687b ldr r3, [r7, #4] 8003142: 689b ldr r3, [r3, #8] 8003144: f5b3 7f80 cmp.w r3, #256 @ 0x100 8003148: d003 beq.n 8003152 800314a: 687b ldr r3, [r7, #4] 800314c: 689b ldr r3, [r3, #8] 800314e: 2b01 cmp r3, #1 8003150: d102 bne.n 8003158 8003152: f44f 7380 mov.w r3, #256 @ 0x100 8003156: e000 b.n 800315a 8003158: 2300 movs r3, #0 800315a: 693a ldr r2, [r7, #16] 800315c: 4313 orrs r3, r2 800315e: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8003160: 687b ldr r3, [r7, #4] 8003162: 7d1b ldrb r3, [r3, #20] 8003164: 2b01 cmp r3, #1 8003166: d119 bne.n 800319c { if (hadc->Init.ContinuousConvMode == DISABLE) 8003168: 687b ldr r3, [r7, #4] 800316a: 7b1b ldrb r3, [r3, #12] 800316c: 2b00 cmp r3, #0 800316e: d109 bne.n 8003184 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8003170: 687b ldr r3, [r7, #4] 8003172: 699b ldr r3, [r3, #24] 8003174: 3b01 subs r3, #1 8003176: 035a lsls r2, r3, #13 8003178: 693b ldr r3, [r7, #16] 800317a: 4313 orrs r3, r2 800317c: f443 6300 orr.w r3, r3, #2048 @ 0x800 8003180: 613b str r3, [r7, #16] 8003182: e00b b.n 800319c { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003184: 687b ldr r3, [r7, #4] 8003186: 6a9b ldr r3, [r3, #40] @ 0x28 8003188: f043 0220 orr.w r2, r3, #32 800318c: 687b ldr r3, [r7, #4] 800318e: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003190: 687b ldr r3, [r7, #4] 8003192: 6adb ldr r3, [r3, #44] @ 0x2c 8003194: f043 0201 orr.w r2, r3, #1 8003198: 687b ldr r3, [r7, #4] 800319a: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800319c: 687b ldr r3, [r7, #4] 800319e: 681b ldr r3, [r3, #0] 80031a0: 685b ldr r3, [r3, #4] 80031a2: f423 4169 bic.w r1, r3, #59648 @ 0xe900 80031a6: 687b ldr r3, [r7, #4] 80031a8: 681b ldr r3, [r3, #0] 80031aa: 693a ldr r2, [r7, #16] 80031ac: 430a orrs r2, r1 80031ae: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80031b0: 687b ldr r3, [r7, #4] 80031b2: 681b ldr r3, [r3, #0] 80031b4: 689a ldr r2, [r3, #8] 80031b6: 4b28 ldr r3, [pc, #160] @ (8003258 ) 80031b8: 4013 ands r3, r2 80031ba: 687a ldr r2, [r7, #4] 80031bc: 6812 ldr r2, [r2, #0] 80031be: 68b9 ldr r1, [r7, #8] 80031c0: 430b orrs r3, r1 80031c2: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 80031c4: 687b ldr r3, [r7, #4] 80031c6: 689b ldr r3, [r3, #8] 80031c8: f5b3 7f80 cmp.w r3, #256 @ 0x100 80031cc: d003 beq.n 80031d6 80031ce: 687b ldr r3, [r7, #4] 80031d0: 689b ldr r3, [r3, #8] 80031d2: 2b01 cmp r3, #1 80031d4: d104 bne.n 80031e0 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 80031d6: 687b ldr r3, [r7, #4] 80031d8: 691b ldr r3, [r3, #16] 80031da: 3b01 subs r3, #1 80031dc: 051b lsls r3, r3, #20 80031de: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 80031e0: 687b ldr r3, [r7, #4] 80031e2: 681b ldr r3, [r3, #0] 80031e4: 6adb ldr r3, [r3, #44] @ 0x2c 80031e6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 80031ea: 687b ldr r3, [r7, #4] 80031ec: 681b ldr r3, [r3, #0] 80031ee: 68fa ldr r2, [r7, #12] 80031f0: 430a orrs r2, r1 80031f2: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80031f4: 687b ldr r3, [r7, #4] 80031f6: 681b ldr r3, [r3, #0] 80031f8: 689a ldr r2, [r3, #8] 80031fa: 4b18 ldr r3, [pc, #96] @ (800325c ) 80031fc: 4013 ands r3, r2 80031fe: 68ba ldr r2, [r7, #8] 8003200: 429a cmp r2, r3 8003202: d10b bne.n 800321c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8003204: 687b ldr r3, [r7, #4] 8003206: 2200 movs r2, #0 8003208: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800320a: 687b ldr r3, [r7, #4] 800320c: 6a9b ldr r3, [r3, #40] @ 0x28 800320e: f023 0303 bic.w r3, r3, #3 8003212: f043 0201 orr.w r2, r3, #1 8003216: 687b ldr r3, [r7, #4] 8003218: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800321a: e018 b.n 800324e HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800321c: 687b ldr r3, [r7, #4] 800321e: 6a9b ldr r3, [r3, #40] @ 0x28 8003220: f023 0312 bic.w r3, r3, #18 8003224: f043 0210 orr.w r2, r3, #16 8003228: 687b ldr r3, [r7, #4] 800322a: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800322c: 687b ldr r3, [r7, #4] 800322e: 6adb ldr r3, [r3, #44] @ 0x2c 8003230: f043 0201 orr.w r2, r3, #1 8003234: 687b ldr r3, [r7, #4] 8003236: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8003238: 2301 movs r3, #1 800323a: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800323c: e007 b.n 800324e } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800323e: 687b ldr r3, [r7, #4] 8003240: 6a9b ldr r3, [r3, #40] @ 0x28 8003242: f043 0210 orr.w r2, r3, #16 8003246: 687b ldr r3, [r7, #4] 8003248: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800324a: 2301 movs r3, #1 800324c: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800324e: 7dfb ldrb r3, [r7, #23] } 8003250: 4618 mov r0, r3 8003252: 3718 adds r7, #24 8003254: 46bd mov sp, r7 8003256: bd80 pop {r7, pc} 8003258: ffe1f7fd .word 0xffe1f7fd 800325c: ff1f0efe .word 0xff1f0efe 08003260 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8003260: b480 push {r7} 8003262: b085 sub sp, #20 8003264: af00 add r7, sp, #0 8003266: 6078 str r0, [r7, #4] 8003268: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800326a: 2300 movs r3, #0 800326c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800326e: 2300 movs r3, #0 8003270: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8003272: 687b ldr r3, [r7, #4] 8003274: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8003278: 2b01 cmp r3, #1 800327a: d101 bne.n 8003280 800327c: 2302 movs r3, #2 800327e: e0dc b.n 800343a 8003280: 687b ldr r3, [r7, #4] 8003282: 2201 movs r2, #1 8003284: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8003288: 683b ldr r3, [r7, #0] 800328a: 685b ldr r3, [r3, #4] 800328c: 2b06 cmp r3, #6 800328e: d81c bhi.n 80032ca { MODIFY_REG(hadc->Instance->SQR3 , 8003290: 687b ldr r3, [r7, #4] 8003292: 681b ldr r3, [r3, #0] 8003294: 6b59 ldr r1, [r3, #52] @ 0x34 8003296: 683b ldr r3, [r7, #0] 8003298: 685a ldr r2, [r3, #4] 800329a: 4613 mov r3, r2 800329c: 009b lsls r3, r3, #2 800329e: 4413 add r3, r2 80032a0: 3b05 subs r3, #5 80032a2: 221f movs r2, #31 80032a4: fa02 f303 lsl.w r3, r2, r3 80032a8: 43db mvns r3, r3 80032aa: 4019 ands r1, r3 80032ac: 683b ldr r3, [r7, #0] 80032ae: 6818 ldr r0, [r3, #0] 80032b0: 683b ldr r3, [r7, #0] 80032b2: 685a ldr r2, [r3, #4] 80032b4: 4613 mov r3, r2 80032b6: 009b lsls r3, r3, #2 80032b8: 4413 add r3, r2 80032ba: 3b05 subs r3, #5 80032bc: fa00 f203 lsl.w r2, r0, r3 80032c0: 687b ldr r3, [r7, #4] 80032c2: 681b ldr r3, [r3, #0] 80032c4: 430a orrs r2, r1 80032c6: 635a str r2, [r3, #52] @ 0x34 80032c8: e03c b.n 8003344 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80032ca: 683b ldr r3, [r7, #0] 80032cc: 685b ldr r3, [r3, #4] 80032ce: 2b0c cmp r3, #12 80032d0: d81c bhi.n 800330c { MODIFY_REG(hadc->Instance->SQR2 , 80032d2: 687b ldr r3, [r7, #4] 80032d4: 681b ldr r3, [r3, #0] 80032d6: 6b19 ldr r1, [r3, #48] @ 0x30 80032d8: 683b ldr r3, [r7, #0] 80032da: 685a ldr r2, [r3, #4] 80032dc: 4613 mov r3, r2 80032de: 009b lsls r3, r3, #2 80032e0: 4413 add r3, r2 80032e2: 3b23 subs r3, #35 @ 0x23 80032e4: 221f movs r2, #31 80032e6: fa02 f303 lsl.w r3, r2, r3 80032ea: 43db mvns r3, r3 80032ec: 4019 ands r1, r3 80032ee: 683b ldr r3, [r7, #0] 80032f0: 6818 ldr r0, [r3, #0] 80032f2: 683b ldr r3, [r7, #0] 80032f4: 685a ldr r2, [r3, #4] 80032f6: 4613 mov r3, r2 80032f8: 009b lsls r3, r3, #2 80032fa: 4413 add r3, r2 80032fc: 3b23 subs r3, #35 @ 0x23 80032fe: fa00 f203 lsl.w r2, r0, r3 8003302: 687b ldr r3, [r7, #4] 8003304: 681b ldr r3, [r3, #0] 8003306: 430a orrs r2, r1 8003308: 631a str r2, [r3, #48] @ 0x30 800330a: e01b b.n 8003344 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800330c: 687b ldr r3, [r7, #4] 800330e: 681b ldr r3, [r3, #0] 8003310: 6ad9 ldr r1, [r3, #44] @ 0x2c 8003312: 683b ldr r3, [r7, #0] 8003314: 685a ldr r2, [r3, #4] 8003316: 4613 mov r3, r2 8003318: 009b lsls r3, r3, #2 800331a: 4413 add r3, r2 800331c: 3b41 subs r3, #65 @ 0x41 800331e: 221f movs r2, #31 8003320: fa02 f303 lsl.w r3, r2, r3 8003324: 43db mvns r3, r3 8003326: 4019 ands r1, r3 8003328: 683b ldr r3, [r7, #0] 800332a: 6818 ldr r0, [r3, #0] 800332c: 683b ldr r3, [r7, #0] 800332e: 685a ldr r2, [r3, #4] 8003330: 4613 mov r3, r2 8003332: 009b lsls r3, r3, #2 8003334: 4413 add r3, r2 8003336: 3b41 subs r3, #65 @ 0x41 8003338: fa00 f203 lsl.w r2, r0, r3 800333c: 687b ldr r3, [r7, #4] 800333e: 681b ldr r3, [r3, #0] 8003340: 430a orrs r2, r1 8003342: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8003344: 683b ldr r3, [r7, #0] 8003346: 681b ldr r3, [r3, #0] 8003348: 2b09 cmp r3, #9 800334a: d91c bls.n 8003386 { MODIFY_REG(hadc->Instance->SMPR1 , 800334c: 687b ldr r3, [r7, #4] 800334e: 681b ldr r3, [r3, #0] 8003350: 68d9 ldr r1, [r3, #12] 8003352: 683b ldr r3, [r7, #0] 8003354: 681a ldr r2, [r3, #0] 8003356: 4613 mov r3, r2 8003358: 005b lsls r3, r3, #1 800335a: 4413 add r3, r2 800335c: 3b1e subs r3, #30 800335e: 2207 movs r2, #7 8003360: fa02 f303 lsl.w r3, r2, r3 8003364: 43db mvns r3, r3 8003366: 4019 ands r1, r3 8003368: 683b ldr r3, [r7, #0] 800336a: 6898 ldr r0, [r3, #8] 800336c: 683b ldr r3, [r7, #0] 800336e: 681a ldr r2, [r3, #0] 8003370: 4613 mov r3, r2 8003372: 005b lsls r3, r3, #1 8003374: 4413 add r3, r2 8003376: 3b1e subs r3, #30 8003378: fa00 f203 lsl.w r2, r0, r3 800337c: 687b ldr r3, [r7, #4] 800337e: 681b ldr r3, [r3, #0] 8003380: 430a orrs r2, r1 8003382: 60da str r2, [r3, #12] 8003384: e019 b.n 80033ba ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8003386: 687b ldr r3, [r7, #4] 8003388: 681b ldr r3, [r3, #0] 800338a: 6919 ldr r1, [r3, #16] 800338c: 683b ldr r3, [r7, #0] 800338e: 681a ldr r2, [r3, #0] 8003390: 4613 mov r3, r2 8003392: 005b lsls r3, r3, #1 8003394: 4413 add r3, r2 8003396: 2207 movs r2, #7 8003398: fa02 f303 lsl.w r3, r2, r3 800339c: 43db mvns r3, r3 800339e: 4019 ands r1, r3 80033a0: 683b ldr r3, [r7, #0] 80033a2: 6898 ldr r0, [r3, #8] 80033a4: 683b ldr r3, [r7, #0] 80033a6: 681a ldr r2, [r3, #0] 80033a8: 4613 mov r3, r2 80033aa: 005b lsls r3, r3, #1 80033ac: 4413 add r3, r2 80033ae: fa00 f203 lsl.w r2, r0, r3 80033b2: 687b ldr r3, [r7, #4] 80033b4: 681b ldr r3, [r3, #0] 80033b6: 430a orrs r2, r1 80033b8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80033ba: 683b ldr r3, [r7, #0] 80033bc: 681b ldr r3, [r3, #0] 80033be: 2b10 cmp r3, #16 80033c0: d003 beq.n 80033ca (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80033c2: 683b ldr r3, [r7, #0] 80033c4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80033c6: 2b11 cmp r3, #17 80033c8: d132 bne.n 8003430 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80033ca: 687b ldr r3, [r7, #4] 80033cc: 681b ldr r3, [r3, #0] 80033ce: 4a1d ldr r2, [pc, #116] @ (8003444 ) 80033d0: 4293 cmp r3, r2 80033d2: d125 bne.n 8003420 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80033d4: 687b ldr r3, [r7, #4] 80033d6: 681b ldr r3, [r3, #0] 80033d8: 689b ldr r3, [r3, #8] 80033da: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80033de: 2b00 cmp r3, #0 80033e0: d126 bne.n 8003430 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80033e2: 687b ldr r3, [r7, #4] 80033e4: 681b ldr r3, [r3, #0] 80033e6: 689a ldr r2, [r3, #8] 80033e8: 687b ldr r3, [r7, #4] 80033ea: 681b ldr r3, [r3, #0] 80033ec: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 80033f0: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 80033f2: 683b ldr r3, [r7, #0] 80033f4: 681b ldr r3, [r3, #0] 80033f6: 2b10 cmp r3, #16 80033f8: d11a bne.n 8003430 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 80033fa: 4b13 ldr r3, [pc, #76] @ (8003448 ) 80033fc: 681b ldr r3, [r3, #0] 80033fe: 4a13 ldr r2, [pc, #76] @ (800344c ) 8003400: fba2 2303 umull r2, r3, r2, r3 8003404: 0c9a lsrs r2, r3, #18 8003406: 4613 mov r3, r2 8003408: 009b lsls r3, r3, #2 800340a: 4413 add r3, r2 800340c: 005b lsls r3, r3, #1 800340e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8003410: e002 b.n 8003418 { wait_loop_index--; 8003412: 68bb ldr r3, [r7, #8] 8003414: 3b01 subs r3, #1 8003416: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8003418: 68bb ldr r3, [r7, #8] 800341a: 2b00 cmp r3, #0 800341c: d1f9 bne.n 8003412 800341e: e007 b.n 8003430 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003420: 687b ldr r3, [r7, #4] 8003422: 6a9b ldr r3, [r3, #40] @ 0x28 8003424: f043 0220 orr.w r2, r3, #32 8003428: 687b ldr r3, [r7, #4] 800342a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800342c: 2301 movs r3, #1 800342e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8003430: 687b ldr r3, [r7, #4] 8003432: 2200 movs r2, #0 8003434: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8003438: 7bfb ldrb r3, [r7, #15] } 800343a: 4618 mov r0, r3 800343c: 3714 adds r7, #20 800343e: 46bd mov sp, r7 8003440: bc80 pop {r7} 8003442: 4770 bx lr 8003444: 40012400 .word 0x40012400 8003448: 20000004 .word 0x20000004 800344c: 431bde83 .word 0x431bde83 08003450 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8003450: b580 push {r7, lr} 8003452: b084 sub sp, #16 8003454: af00 add r7, sp, #0 8003456: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003458: 2300 movs r3, #0 800345a: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800345c: 687b ldr r3, [r7, #4] 800345e: 681b ldr r3, [r3, #0] 8003460: 689b ldr r3, [r3, #8] 8003462: f003 0301 and.w r3, r3, #1 8003466: 2b01 cmp r3, #1 8003468: d12e bne.n 80034c8 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800346a: 687b ldr r3, [r7, #4] 800346c: 681b ldr r3, [r3, #0] 800346e: 689a ldr r2, [r3, #8] 8003470: 687b ldr r3, [r7, #4] 8003472: 681b ldr r3, [r3, #0] 8003474: f022 0201 bic.w r2, r2, #1 8003478: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800347a: f7ff fdeb bl 8003054 800347e: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8003480: e01b b.n 80034ba { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8003482: f7ff fde7 bl 8003054 8003486: 4602 mov r2, r0 8003488: 68fb ldr r3, [r7, #12] 800348a: 1ad3 subs r3, r2, r3 800348c: 2b02 cmp r3, #2 800348e: d914 bls.n 80034ba { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8003490: 687b ldr r3, [r7, #4] 8003492: 681b ldr r3, [r3, #0] 8003494: 689b ldr r3, [r3, #8] 8003496: f003 0301 and.w r3, r3, #1 800349a: 2b01 cmp r3, #1 800349c: d10d bne.n 80034ba { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800349e: 687b ldr r3, [r7, #4] 80034a0: 6a9b ldr r3, [r3, #40] @ 0x28 80034a2: f043 0210 orr.w r2, r3, #16 80034a6: 687b ldr r3, [r7, #4] 80034a8: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80034aa: 687b ldr r3, [r7, #4] 80034ac: 6adb ldr r3, [r3, #44] @ 0x2c 80034ae: f043 0201 orr.w r2, r3, #1 80034b2: 687b ldr r3, [r7, #4] 80034b4: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 80034b6: 2301 movs r3, #1 80034b8: e007 b.n 80034ca while(ADC_IS_ENABLE(hadc) != RESET) 80034ba: 687b ldr r3, [r7, #4] 80034bc: 681b ldr r3, [r3, #0] 80034be: 689b ldr r3, [r3, #8] 80034c0: f003 0301 and.w r3, r3, #1 80034c4: 2b01 cmp r3, #1 80034c6: d0dc beq.n 8003482 } } } /* Return HAL status */ return HAL_OK; 80034c8: 2300 movs r3, #0 } 80034ca: 4618 mov r0, r3 80034cc: 3710 adds r7, #16 80034ce: 46bd mov sp, r7 80034d0: bd80 pop {r7, pc} ... 080034d4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80034d4: b480 push {r7} 80034d6: b085 sub sp, #20 80034d8: af00 add r7, sp, #0 80034da: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80034dc: 687b ldr r3, [r7, #4] 80034de: f003 0307 and.w r3, r3, #7 80034e2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80034e4: 4b0c ldr r3, [pc, #48] @ (8003518 <__NVIC_SetPriorityGrouping+0x44>) 80034e6: 68db ldr r3, [r3, #12] 80034e8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80034ea: 68ba ldr r2, [r7, #8] 80034ec: f64f 03ff movw r3, #63743 @ 0xf8ff 80034f0: 4013 ands r3, r2 80034f2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80034f4: 68fb ldr r3, [r7, #12] 80034f6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80034f8: 68bb ldr r3, [r7, #8] 80034fa: 4313 orrs r3, r2 reg_value = (reg_value | 80034fc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8003500: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003504: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8003506: 4a04 ldr r2, [pc, #16] @ (8003518 <__NVIC_SetPriorityGrouping+0x44>) 8003508: 68bb ldr r3, [r7, #8] 800350a: 60d3 str r3, [r2, #12] } 800350c: bf00 nop 800350e: 3714 adds r7, #20 8003510: 46bd mov sp, r7 8003512: bc80 pop {r7} 8003514: 4770 bx lr 8003516: bf00 nop 8003518: e000ed00 .word 0xe000ed00 0800351c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800351c: b480 push {r7} 800351e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8003520: 4b04 ldr r3, [pc, #16] @ (8003534 <__NVIC_GetPriorityGrouping+0x18>) 8003522: 68db ldr r3, [r3, #12] 8003524: 0a1b lsrs r3, r3, #8 8003526: f003 0307 and.w r3, r3, #7 } 800352a: 4618 mov r0, r3 800352c: 46bd mov sp, r7 800352e: bc80 pop {r7} 8003530: 4770 bx lr 8003532: bf00 nop 8003534: e000ed00 .word 0xe000ed00 08003538 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8003538: b480 push {r7} 800353a: b083 sub sp, #12 800353c: af00 add r7, sp, #0 800353e: 4603 mov r3, r0 8003540: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003542: f997 3007 ldrsb.w r3, [r7, #7] 8003546: 2b00 cmp r3, #0 8003548: db0b blt.n 8003562 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800354a: 79fb ldrb r3, [r7, #7] 800354c: f003 021f and.w r2, r3, #31 8003550: 4906 ldr r1, [pc, #24] @ (800356c <__NVIC_EnableIRQ+0x34>) 8003552: f997 3007 ldrsb.w r3, [r7, #7] 8003556: 095b lsrs r3, r3, #5 8003558: 2001 movs r0, #1 800355a: fa00 f202 lsl.w r2, r0, r2 800355e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8003562: bf00 nop 8003564: 370c adds r7, #12 8003566: 46bd mov sp, r7 8003568: bc80 pop {r7} 800356a: 4770 bx lr 800356c: e000e100 .word 0xe000e100 08003570 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8003570: b480 push {r7} 8003572: b083 sub sp, #12 8003574: af00 add r7, sp, #0 8003576: 4603 mov r3, r0 8003578: 6039 str r1, [r7, #0] 800357a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800357c: f997 3007 ldrsb.w r3, [r7, #7] 8003580: 2b00 cmp r3, #0 8003582: db0a blt.n 800359a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003584: 683b ldr r3, [r7, #0] 8003586: b2da uxtb r2, r3 8003588: 490c ldr r1, [pc, #48] @ (80035bc <__NVIC_SetPriority+0x4c>) 800358a: f997 3007 ldrsb.w r3, [r7, #7] 800358e: 0112 lsls r2, r2, #4 8003590: b2d2 uxtb r2, r2 8003592: 440b add r3, r1 8003594: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8003598: e00a b.n 80035b0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800359a: 683b ldr r3, [r7, #0] 800359c: b2da uxtb r2, r3 800359e: 4908 ldr r1, [pc, #32] @ (80035c0 <__NVIC_SetPriority+0x50>) 80035a0: 79fb ldrb r3, [r7, #7] 80035a2: f003 030f and.w r3, r3, #15 80035a6: 3b04 subs r3, #4 80035a8: 0112 lsls r2, r2, #4 80035aa: b2d2 uxtb r2, r2 80035ac: 440b add r3, r1 80035ae: 761a strb r2, [r3, #24] } 80035b0: bf00 nop 80035b2: 370c adds r7, #12 80035b4: 46bd mov sp, r7 80035b6: bc80 pop {r7} 80035b8: 4770 bx lr 80035ba: bf00 nop 80035bc: e000e100 .word 0xe000e100 80035c0: e000ed00 .word 0xe000ed00 080035c4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80035c4: b480 push {r7} 80035c6: b089 sub sp, #36 @ 0x24 80035c8: af00 add r7, sp, #0 80035ca: 60f8 str r0, [r7, #12] 80035cc: 60b9 str r1, [r7, #8] 80035ce: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80035d0: 68fb ldr r3, [r7, #12] 80035d2: f003 0307 and.w r3, r3, #7 80035d6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80035d8: 69fb ldr r3, [r7, #28] 80035da: f1c3 0307 rsb r3, r3, #7 80035de: 2b04 cmp r3, #4 80035e0: bf28 it cs 80035e2: 2304 movcs r3, #4 80035e4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80035e6: 69fb ldr r3, [r7, #28] 80035e8: 3304 adds r3, #4 80035ea: 2b06 cmp r3, #6 80035ec: d902 bls.n 80035f4 80035ee: 69fb ldr r3, [r7, #28] 80035f0: 3b03 subs r3, #3 80035f2: e000 b.n 80035f6 80035f4: 2300 movs r3, #0 80035f6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80035f8: f04f 32ff mov.w r2, #4294967295 80035fc: 69bb ldr r3, [r7, #24] 80035fe: fa02 f303 lsl.w r3, r2, r3 8003602: 43da mvns r2, r3 8003604: 68bb ldr r3, [r7, #8] 8003606: 401a ands r2, r3 8003608: 697b ldr r3, [r7, #20] 800360a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800360c: f04f 31ff mov.w r1, #4294967295 8003610: 697b ldr r3, [r7, #20] 8003612: fa01 f303 lsl.w r3, r1, r3 8003616: 43d9 mvns r1, r3 8003618: 687b ldr r3, [r7, #4] 800361a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800361c: 4313 orrs r3, r2 ); } 800361e: 4618 mov r0, r3 8003620: 3724 adds r7, #36 @ 0x24 8003622: 46bd mov sp, r7 8003624: bc80 pop {r7} 8003626: 4770 bx lr 08003628 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8003628: b580 push {r7, lr} 800362a: b082 sub sp, #8 800362c: af00 add r7, sp, #0 800362e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8003630: 687b ldr r3, [r7, #4] 8003632: 3b01 subs r3, #1 8003634: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8003638: d301 bcc.n 800363e { return (1UL); /* Reload value impossible */ 800363a: 2301 movs r3, #1 800363c: e00f b.n 800365e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800363e: 4a0a ldr r2, [pc, #40] @ (8003668 ) 8003640: 687b ldr r3, [r7, #4] 8003642: 3b01 subs r3, #1 8003644: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8003646: 210f movs r1, #15 8003648: f04f 30ff mov.w r0, #4294967295 800364c: f7ff ff90 bl 8003570 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8003650: 4b05 ldr r3, [pc, #20] @ (8003668 ) 8003652: 2200 movs r2, #0 8003654: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8003656: 4b04 ldr r3, [pc, #16] @ (8003668 ) 8003658: 2207 movs r2, #7 800365a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800365c: 2300 movs r3, #0 } 800365e: 4618 mov r0, r3 8003660: 3708 adds r7, #8 8003662: 46bd mov sp, r7 8003664: bd80 pop {r7, pc} 8003666: bf00 nop 8003668: e000e010 .word 0xe000e010 0800366c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800366c: b580 push {r7, lr} 800366e: b082 sub sp, #8 8003670: af00 add r7, sp, #0 8003672: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8003674: 6878 ldr r0, [r7, #4] 8003676: f7ff ff2d bl 80034d4 <__NVIC_SetPriorityGrouping> } 800367a: bf00 nop 800367c: 3708 adds r7, #8 800367e: 46bd mov sp, r7 8003680: bd80 pop {r7, pc} 08003682 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8003682: b580 push {r7, lr} 8003684: b086 sub sp, #24 8003686: af00 add r7, sp, #0 8003688: 4603 mov r3, r0 800368a: 60b9 str r1, [r7, #8] 800368c: 607a str r2, [r7, #4] 800368e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8003690: 2300 movs r3, #0 8003692: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8003694: f7ff ff42 bl 800351c <__NVIC_GetPriorityGrouping> 8003698: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800369a: 687a ldr r2, [r7, #4] 800369c: 68b9 ldr r1, [r7, #8] 800369e: 6978 ldr r0, [r7, #20] 80036a0: f7ff ff90 bl 80035c4 80036a4: 4602 mov r2, r0 80036a6: f997 300f ldrsb.w r3, [r7, #15] 80036aa: 4611 mov r1, r2 80036ac: 4618 mov r0, r3 80036ae: f7ff ff5f bl 8003570 <__NVIC_SetPriority> } 80036b2: bf00 nop 80036b4: 3718 adds r7, #24 80036b6: 46bd mov sp, r7 80036b8: bd80 pop {r7, pc} 080036ba : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80036ba: b580 push {r7, lr} 80036bc: b082 sub sp, #8 80036be: af00 add r7, sp, #0 80036c0: 4603 mov r3, r0 80036c2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80036c4: f997 3007 ldrsb.w r3, [r7, #7] 80036c8: 4618 mov r0, r3 80036ca: f7ff ff35 bl 8003538 <__NVIC_EnableIRQ> } 80036ce: bf00 nop 80036d0: 3708 adds r7, #8 80036d2: 46bd mov sp, r7 80036d4: bd80 pop {r7, pc} 080036d6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80036d6: b580 push {r7, lr} 80036d8: b082 sub sp, #8 80036da: af00 add r7, sp, #0 80036dc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80036de: 6878 ldr r0, [r7, #4] 80036e0: f7ff ffa2 bl 8003628 80036e4: 4603 mov r3, r0 } 80036e6: 4618 mov r0, r3 80036e8: 3708 adds r7, #8 80036ea: 46bd mov sp, r7 80036ec: bd80 pop {r7, pc} 080036ee : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80036ee: b480 push {r7} 80036f0: b085 sub sp, #20 80036f2: af00 add r7, sp, #0 80036f4: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80036f6: 2300 movs r3, #0 80036f8: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 80036fa: 687b ldr r3, [r7, #4] 80036fc: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8003700: b2db uxtb r3, r3 8003702: 2b02 cmp r3, #2 8003704: d008 beq.n 8003718 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003706: 687b ldr r3, [r7, #4] 8003708: 2204 movs r2, #4 800370a: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800370c: 687b ldr r3, [r7, #4] 800370e: 2200 movs r2, #0 8003710: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8003714: 2301 movs r3, #1 8003716: e020 b.n 800375a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003718: 687b ldr r3, [r7, #4] 800371a: 681b ldr r3, [r3, #0] 800371c: 681a ldr r2, [r3, #0] 800371e: 687b ldr r3, [r7, #4] 8003720: 681b ldr r3, [r3, #0] 8003722: f022 020e bic.w r2, r2, #14 8003726: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8003728: 687b ldr r3, [r7, #4] 800372a: 681b ldr r3, [r3, #0] 800372c: 681a ldr r2, [r3, #0] 800372e: 687b ldr r3, [r7, #4] 8003730: 681b ldr r3, [r3, #0] 8003732: f022 0201 bic.w r2, r2, #1 8003736: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8003738: 687b ldr r3, [r7, #4] 800373a: 6c1a ldr r2, [r3, #64] @ 0x40 800373c: 687b ldr r3, [r7, #4] 800373e: 6bdb ldr r3, [r3, #60] @ 0x3c 8003740: 2101 movs r1, #1 8003742: fa01 f202 lsl.w r2, r1, r2 8003746: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003748: 687b ldr r3, [r7, #4] 800374a: 2201 movs r2, #1 800374c: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003750: 687b ldr r3, [r7, #4] 8003752: 2200 movs r2, #0 8003754: f883 2020 strb.w r2, [r3, #32] return status; 8003758: 7bfb ldrb r3, [r7, #15] } 800375a: 4618 mov r0, r3 800375c: 3714 adds r7, #20 800375e: 46bd mov sp, r7 8003760: bc80 pop {r7} 8003762: 4770 bx lr 08003764 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003764: b580 push {r7, lr} 8003766: b084 sub sp, #16 8003768: af00 add r7, sp, #0 800376a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800376c: 2300 movs r3, #0 800376e: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8003770: 687b ldr r3, [r7, #4] 8003772: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8003776: b2db uxtb r3, r3 8003778: 2b02 cmp r3, #2 800377a: d005 beq.n 8003788 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800377c: 687b ldr r3, [r7, #4] 800377e: 2204 movs r2, #4 8003780: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8003782: 2301 movs r3, #1 8003784: 73fb strb r3, [r7, #15] 8003786: e051 b.n 800382c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003788: 687b ldr r3, [r7, #4] 800378a: 681b ldr r3, [r3, #0] 800378c: 681a ldr r2, [r3, #0] 800378e: 687b ldr r3, [r7, #4] 8003790: 681b ldr r3, [r3, #0] 8003792: f022 020e bic.w r2, r2, #14 8003796: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8003798: 687b ldr r3, [r7, #4] 800379a: 681b ldr r3, [r3, #0] 800379c: 681a ldr r2, [r3, #0] 800379e: 687b ldr r3, [r7, #4] 80037a0: 681b ldr r3, [r3, #0] 80037a2: f022 0201 bic.w r2, r2, #1 80037a6: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80037a8: 687b ldr r3, [r7, #4] 80037aa: 681b ldr r3, [r3, #0] 80037ac: 4a22 ldr r2, [pc, #136] @ (8003838 ) 80037ae: 4293 cmp r3, r2 80037b0: d029 beq.n 8003806 80037b2: 687b ldr r3, [r7, #4] 80037b4: 681b ldr r3, [r3, #0] 80037b6: 4a21 ldr r2, [pc, #132] @ (800383c ) 80037b8: 4293 cmp r3, r2 80037ba: d022 beq.n 8003802 80037bc: 687b ldr r3, [r7, #4] 80037be: 681b ldr r3, [r3, #0] 80037c0: 4a1f ldr r2, [pc, #124] @ (8003840 ) 80037c2: 4293 cmp r3, r2 80037c4: d01a beq.n 80037fc 80037c6: 687b ldr r3, [r7, #4] 80037c8: 681b ldr r3, [r3, #0] 80037ca: 4a1e ldr r2, [pc, #120] @ (8003844 ) 80037cc: 4293 cmp r3, r2 80037ce: d012 beq.n 80037f6 80037d0: 687b ldr r3, [r7, #4] 80037d2: 681b ldr r3, [r3, #0] 80037d4: 4a1c ldr r2, [pc, #112] @ (8003848 ) 80037d6: 4293 cmp r3, r2 80037d8: d00a beq.n 80037f0 80037da: 687b ldr r3, [r7, #4] 80037dc: 681b ldr r3, [r3, #0] 80037de: 4a1b ldr r2, [pc, #108] @ (800384c ) 80037e0: 4293 cmp r3, r2 80037e2: d102 bne.n 80037ea 80037e4: f44f 1380 mov.w r3, #1048576 @ 0x100000 80037e8: e00e b.n 8003808