hardware/fertirrega_v6
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c215488ec22b1964e33f1378bfae4fb8cf778db6
fertirrega_v6/Fertirrega_v6/Debug/Fertirrega_v6.list
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hardware c215488ec2 Fertirrega_v6 AD5934 Bug Fix
2026-07-21 17:57:07 +01:00

15964 lines
598 KiB
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Fertirrega_v6.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000631c 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000074 08006428 08006428 00007428 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800649c 0800649c 00008074 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800649c 0800649c 0000749c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080064a4 080064a4 00008074 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080064a4 080064a4 000074a4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080064a8 080064a8 000074a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000074 20000000 080064ac 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000007d0 20000078 08006520 00008078 2**3
ALLOC
10 ._user_heap_stack 00000600 20000848 08006520 00008848 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00008074 2**0
CONTENTS, READONLY
12 .debug_info 0000fafc 00000000 00000000 0000809d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003352 00000000 00000000 00017b99 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000e10 00000000 00000000 0001aef0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000ad0 00000000 00000000 0001bd00 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00019a5e 00000000 00000000 0001c7d0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000143c6 00000000 00000000 0003622e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008d3f3 00000000 00000000 0004a5f4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000d79e7 2**0
CONTENTS, READONLY
20 .debug_frame 00003a60 00000000 00000000 000d7a2c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000db48c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000078 .word 0x20000078
8000128: 00000000 .word 0x00000000
800012c: 08006410 .word 0x08006410
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 2000007c .word 0x2000007c
8000148: 08006410 .word 0x08006410
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <__aeabi_dmul>:
800015c: b570 push {r4, r5, r6, lr}
800015e: f04f 0cff mov.w ip, #255 @ 0xff
8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20
800016a: bf1d ittte ne
800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000170: ea94 0f0c teqne r4, ip
8000174: ea95 0f0c teqne r5, ip
8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc>
800017c: 442c add r4, r5
800017e: ea81 0603 eor.w r6, r1, r3
8000182: ea21 514c bic.w r1, r1, ip, lsl #21
8000186: ea23 534c bic.w r3, r3, ip, lsl #21
800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12
800018e: bf18 it ne
8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4>
800019e: fba0 ce02 umull ip, lr, r0, r2
80001a2: f04f 0500 mov.w r5, #0
80001a6: fbe1 e502 umlal lr, r5, r1, r2
80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80001ae: fbe0 e503 umlal lr, r5, r0, r3
80001b2: f04f 0600 mov.w r6, #0
80001b6: fbe1 5603 umlal r5, r6, r1, r3
80001ba: f09c 0f00 teq ip, #0
80001be: bf18 it ne
80001c0: f04e 0e01 orrne.w lr, lr, #1
80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff
80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200
80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300
80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80>
80001d2: ea5f 0e4e movs.w lr, lr, lsl #1
80001d6: 416d adcs r5, r5
80001d8: eb46 0606 adc.w r6, r6, r6
80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11
80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21
80001e4: ea4f 20c5 mov.w r0, r5, lsl #11
80001e8: ea40 505e orr.w r0, r0, lr, lsr #21
80001ec: ea4f 2ece mov.w lr, lr, lsl #11
80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80001f4: bf88 it hi
80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde>
80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
8000200: bf08 it eq
8000202: ea5f 0e50 movseq.w lr, r0, lsr #1
8000206: f150 0000 adcs.w r0, r0, #0
800020a: eb41 5104 adc.w r1, r1, r4, lsl #20
800020e: bd70 pop {r4, r5, r6, pc}
8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000214: ea46 0101 orr.w r1, r6, r1
8000218: ea40 0002 orr.w r0, r0, r2
800021c: ea81 0103 eor.w r1, r1, r3
8000220: ebb4 045c subs.w r4, r4, ip, lsr #1
8000224: bfc2 ittt gt
8000226: ebd4 050c rsbsgt r5, r4, ip
800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800022e: bd70 popgt {r4, r5, r6, pc}
8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000234: f04f 0e00 mov.w lr, #0
8000238: 3c01 subs r4, #1
800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238>
800023e: f114 0f36 cmn.w r4, #54 @ 0x36
8000242: bfde ittt le
8000244: 2000 movle r0, #0
8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
800024a: bd70 pople {r4, r5, r6, pc}
800024c: f1c4 0400 rsb r4, r4, #0
8000250: 3c20 subs r4, #32
8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164>
8000254: 340c adds r4, #12
8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134>
8000258: f104 0414 add.w r4, r4, #20
800025c: f1c4 0520 rsb r5, r4, #32
8000260: fa00 f305 lsl.w r3, r0, r5
8000264: fa20 f004 lsr.w r0, r0, r4
8000268: fa01 f205 lsl.w r2, r1, r5
800026c: ea40 0002 orr.w r0, r0, r2
8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31
800027c: fa21 f604 lsr.w r6, r1, r4
8000280: eb42 0106 adc.w r1, r2, r6
8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000288: bf08 it eq
800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800028e: bd70 pop {r4, r5, r6, pc}
8000290: f1c4 040c rsb r4, r4, #12
8000294: f1c4 0520 rsb r5, r4, #32
8000298: fa00 f304 lsl.w r3, r0, r4
800029c: fa20 f005 lsr.w r0, r0, r5
80002a0: fa01 f204 lsl.w r2, r1, r4
80002a4: ea40 0002 orr.w r0, r0, r2
80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002b0: f141 0100 adc.w r1, r1, #0
80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002b8: bf08 it eq
80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002be: bd70 pop {r4, r5, r6, pc}
80002c0: f1c4 0520 rsb r5, r4, #32
80002c4: fa00 f205 lsl.w r2, r0, r5
80002c8: ea4e 0e02 orr.w lr, lr, r2
80002cc: fa20 f304 lsr.w r3, r0, r4
80002d0: fa01 f205 lsl.w r2, r1, r5
80002d4: ea43 0302 orr.w r3, r3, r2
80002d8: fa21 f004 lsr.w r0, r1, r4
80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002e0: fa21 f204 lsr.w r2, r1, r4
80002e4: ea20 0002 bic.w r0, r0, r2
80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31
80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002f0: bf08 it eq
80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002f6: bd70 pop {r4, r5, r6, pc}
80002f8: f094 0f00 teq r4, #0
80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2>
80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
8000302: 0040 lsls r0, r0, #1
8000304: eb41 0101 adc.w r1, r1, r1
8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000
800030c: bf08 it eq
800030e: 3c01 subeq r4, #1
8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6>
8000312: ea41 0106 orr.w r1, r1, r6
8000316: f095 0f00 teq r5, #0
800031a: bf18 it ne
800031c: 4770 bxne lr
800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
8000322: 0052 lsls r2, r2, #1
8000324: eb43 0303 adc.w r3, r3, r3
8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000
800032c: bf08 it eq
800032e: 3d01 subeq r5, #1
8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6>
8000332: ea43 0306 orr.w r3, r3, r6
8000336: 4770 bx lr
8000338: ea94 0f0c teq r4, ip
800033c: ea0c 5513 and.w r5, ip, r3, lsr #20
8000340: bf18 it ne
8000342: ea95 0f0c teqne r5, ip
8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206>
8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1
800034c: bf18 it ne
800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c>
8000354: ea81 0103 eor.w r1, r1, r3
8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800035c: f04f 0000 mov.w r0, #0
8000360: bd70 pop {r4, r5, r6, pc}
8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000366: bf06 itte eq
8000368: 4610 moveq r0, r2
800036a: 4619 moveq r1, r3
800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a>
8000372: ea94 0f0c teq r4, ip
8000376: d102 bne.n 800037e <__aeabi_dmul+0x222>
8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12
800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a>
800037e: ea95 0f0c teq r5, ip
8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234>
8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000388: bf1c itt ne
800038a: 4610 movne r0, r2
800038c: 4619 movne r1, r3
800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a>
8000390: ea81 0103 eor.w r1, r1, r3
8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003a0: f04f 0000 mov.w r0, #0
80003a4: bd70 pop {r4, r5, r6, pc}
80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80003ae: bd70 pop {r4, r5, r6, pc}
080003b0 <__aeabi_drsub>:
80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
80003b4: e002 b.n 80003bc <__adddf3>
80003b6: bf00 nop
080003b8 <__aeabi_dsub>:
80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
080003bc <__adddf3>:
80003bc: b530 push {r4, r5, lr}
80003be: ea4f 0441 mov.w r4, r1, lsl #1
80003c2: ea4f 0543 mov.w r5, r3, lsl #1
80003c6: ea94 0f05 teq r4, r5
80003ca: bf08 it eq
80003cc: ea90 0f02 teqeq r0, r2
80003d0: bf1f itttt ne
80003d2: ea54 0c00 orrsne.w ip, r4, r0
80003d6: ea55 0c02 orrsne.w ip, r5, r2
80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21
80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21
80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee>
80003e6: ea4f 5454 mov.w r4, r4, lsr #21
80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21
80003ee: bfb8 it lt
80003f0: 426d neglt r5, r5
80003f2: dd0c ble.n 800040e <__adddf3+0x52>
80003f4: 442c add r4, r5
80003f6: ea80 0202 eor.w r2, r0, r2
80003fa: ea81 0303 eor.w r3, r1, r3
80003fe: ea82 0000 eor.w r0, r2, r0
8000402: ea83 0101 eor.w r1, r3, r1
8000406: ea80 0202 eor.w r2, r0, r2
800040a: ea81 0303 eor.w r3, r1, r3
800040e: 2d36 cmp r5, #54 @ 0x36
8000410: bf88 it hi
8000412: bd30 pophi {r4, r5, pc}
8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000418: ea4f 3101 mov.w r1, r1, lsl #12
800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000424: d002 beq.n 800042c <__adddf3+0x70>
8000426: 4240 negs r0, r0
8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1
800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000430: ea4f 3303 mov.w r3, r3, lsl #12
8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000438: d002 beq.n 8000440 <__adddf3+0x84>
800043a: 4252 negs r2, r2
800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000440: ea94 0f05 teq r4, r5
8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da>
8000448: f1a4 0401 sub.w r4, r4, #1
800044c: f1d5 0e20 rsbs lr, r5, #32
8000450: db0d blt.n 800046e <__adddf3+0xb2>
8000452: fa02 fc0e lsl.w ip, r2, lr
8000456: fa22 f205 lsr.w r2, r2, r5
800045a: 1880 adds r0, r0, r2
800045c: f141 0100 adc.w r1, r1, #0
8000460: fa03 f20e lsl.w r2, r3, lr
8000464: 1880 adds r0, r0, r2
8000466: fa43 f305 asr.w r3, r3, r5
800046a: 4159 adcs r1, r3
800046c: e00e b.n 800048c <__adddf3+0xd0>
800046e: f1a5 0520 sub.w r5, r5, #32
8000472: f10e 0e20 add.w lr, lr, #32
8000476: 2a01 cmp r2, #1
8000478: fa03 fc0e lsl.w ip, r3, lr
800047c: bf28 it cs
800047e: f04c 0c02 orrcs.w ip, ip, #2
8000482: fa43 f305 asr.w r3, r3, r5
8000486: 18c0 adds r0, r0, r3
8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31
800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000490: d507 bpl.n 80004a2 <__adddf3+0xe6>
8000492: f04f 0e00 mov.w lr, #0
8000496: f1dc 0c00 rsbs ip, ip, #0
800049a: eb7e 0000 sbcs.w r0, lr, r0
800049e: eb6e 0101 sbc.w r1, lr, r1
80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80004a6: d31b bcc.n 80004e0 <__adddf3+0x124>
80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c>
80004ae: 0849 lsrs r1, r1, #1
80004b0: ea5f 0030 movs.w r0, r0, rrx
80004b4: ea4f 0c3c mov.w ip, ip, rrx
80004b8: f104 0401 add.w r4, r4, #1
80004bc: ea4f 5244 mov.w r2, r4, lsl #21
80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240>
80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80004cc: bf08 it eq
80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1
80004d2: f150 0000 adcs.w r0, r0, #0
80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20
80004da: ea41 0105 orr.w r1, r1, r5
80004de: bd30 pop {r4, r5, pc}
80004e0: ea5f 0c4c movs.w ip, ip, lsl #1
80004e4: 4140 adcs r0, r0
80004e6: eb41 0101 adc.w r1, r1, r1
80004ea: 3c01 subs r4, #1
80004ec: bf28 it cs
80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c>
80004f4: f091 0f00 teq r1, #0
80004f8: bf04 itt eq
80004fa: 4601 moveq r1, r0
80004fc: 2000 moveq r0, #0
80004fe: fab1 f381 clz r3, r1
8000502: bf08 it eq
8000504: 3320 addeq r3, #32
8000506: f1a3 030b sub.w r3, r3, #11
800050a: f1b3 0220 subs.w r2, r3, #32
800050e: da0c bge.n 800052a <__adddf3+0x16e>
8000510: 320c adds r2, #12
8000512: dd08 ble.n 8000526 <__adddf3+0x16a>
8000514: f102 0c14 add.w ip, r2, #20
8000518: f1c2 020c rsb r2, r2, #12
800051c: fa01 f00c lsl.w r0, r1, ip
8000520: fa21 f102 lsr.w r1, r1, r2
8000524: e00c b.n 8000540 <__adddf3+0x184>
8000526: f102 0214 add.w r2, r2, #20
800052a: bfd8 it le
800052c: f1c2 0c20 rsble ip, r2, #32
8000530: fa01 f102 lsl.w r1, r1, r2
8000534: fa20 fc0c lsr.w ip, r0, ip
8000538: bfdc itt le
800053a: ea41 010c orrle.w r1, r1, ip
800053e: 4090 lslle r0, r2
8000540: 1ae4 subs r4, r4, r3
8000542: bfa2 ittt ge
8000544: eb01 5104 addge.w r1, r1, r4, lsl #20
8000548: 4329 orrge r1, r5
800054a: bd30 popge {r4, r5, pc}
800054c: ea6f 0404 mvn.w r4, r4
8000550: 3c1f subs r4, #31
8000552: da1c bge.n 800058e <__adddf3+0x1d2>
8000554: 340c adds r4, #12
8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba>
8000558: f104 0414 add.w r4, r4, #20
800055c: f1c4 0220 rsb r2, r4, #32
8000560: fa20 f004 lsr.w r0, r0, r4
8000564: fa01 f302 lsl.w r3, r1, r2
8000568: ea40 0003 orr.w r0, r0, r3
800056c: fa21 f304 lsr.w r3, r1, r4
8000570: ea45 0103 orr.w r1, r5, r3
8000574: bd30 pop {r4, r5, pc}
8000576: f1c4 040c rsb r4, r4, #12
800057a: f1c4 0220 rsb r2, r4, #32
800057e: fa20 f002 lsr.w r0, r0, r2
8000582: fa01 f304 lsl.w r3, r1, r4
8000586: ea40 0003 orr.w r0, r0, r3
800058a: 4629 mov r1, r5
800058c: bd30 pop {r4, r5, pc}
800058e: fa21 f004 lsr.w r0, r1, r4
8000592: 4629 mov r1, r5
8000594: bd30 pop {r4, r5, pc}
8000596: f094 0f00 teq r4, #0
800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800059e: bf06 itte eq
80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
80005a4: 3401 addeq r4, #1
80005a6: 3d01 subne r5, #1
80005a8: e74e b.n 8000448 <__adddf3+0x8c>
80005aa: ea7f 5c64 mvns.w ip, r4, asr #21
80005ae: bf18 it ne
80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21
80005b4: d029 beq.n 800060a <__adddf3+0x24e>
80005b6: ea94 0f05 teq r4, r5
80005ba: bf08 it eq
80005bc: ea90 0f02 teqeq r0, r2
80005c0: d005 beq.n 80005ce <__adddf3+0x212>
80005c2: ea54 0c00 orrs.w ip, r4, r0
80005c6: bf04 itt eq
80005c8: 4619 moveq r1, r3
80005ca: 4610 moveq r0, r2
80005cc: bd30 pop {r4, r5, pc}
80005ce: ea91 0f03 teq r1, r3
80005d2: bf1e ittt ne
80005d4: 2100 movne r1, #0
80005d6: 2000 movne r0, #0
80005d8: bd30 popne {r4, r5, pc}
80005da: ea5f 5c54 movs.w ip, r4, lsr #21
80005de: d105 bne.n 80005ec <__adddf3+0x230>
80005e0: 0040 lsls r0, r0, #1
80005e2: 4149 adcs r1, r1
80005e4: bf28 it cs
80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80005ea: bd30 pop {r4, r5, pc}
80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80005f0: bf3c itt cc
80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80005f6: bd30 popcc {r4, r5, pc}
80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000604: f04f 0000 mov.w r0, #0
8000608: bd30 pop {r4, r5, pc}
800060a: ea7f 5c64 mvns.w ip, r4, asr #21
800060e: bf1a itte ne
8000610: 4619 movne r1, r3
8000612: 4610 movne r0, r2
8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000618: bf1c itt ne
800061a: 460b movne r3, r1
800061c: 4602 movne r2, r0
800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000622: bf06 itte eq
8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12
8000628: ea91 0f03 teqeq r1, r3
800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000630: bd30 pop {r4, r5, pc}
8000632: bf00 nop
08000634 <__aeabi_ui2d>:
8000634: f090 0f00 teq r0, #0
8000638: bf04 itt eq
800063a: 2100 moveq r1, #0
800063c: 4770 bxeq lr
800063e: b530 push {r4, r5, lr}
8000640: f44f 6480 mov.w r4, #1024 @ 0x400
8000644: f104 0432 add.w r4, r4, #50 @ 0x32
8000648: f04f 0500 mov.w r5, #0
800064c: f04f 0100 mov.w r1, #0
8000650: e750 b.n 80004f4 <__adddf3+0x138>
8000652: bf00 nop
08000654 <__aeabi_i2d>:
8000654: f090 0f00 teq r0, #0
8000658: bf04 itt eq
800065a: 2100 moveq r1, #0
800065c: 4770 bxeq lr
800065e: b530 push {r4, r5, lr}
8000660: f44f 6480 mov.w r4, #1024 @ 0x400
8000664: f104 0432 add.w r4, r4, #50 @ 0x32
8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800066c: bf48 it mi
800066e: 4240 negmi r0, r0
8000670: f04f 0100 mov.w r1, #0
8000674: e73e b.n 80004f4 <__adddf3+0x138>
8000676: bf00 nop
08000678 <__aeabi_f2d>:
8000678: 0042 lsls r2, r0, #1
800067a: ea4f 01e2 mov.w r1, r2, asr #3
800067e: ea4f 0131 mov.w r1, r1, rrx
8000682: ea4f 7002 mov.w r0, r2, lsl #28
8000686: bf1f itttt ne
8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000694: 4770 bxne lr
8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800069a: bf08 it eq
800069c: 4770 bxeq lr
800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000
80006a2: bf04 itt eq
80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
80006a8: 4770 bxeq lr
80006aa: b530 push {r4, r5, lr}
80006ac: f44f 7460 mov.w r4, #896 @ 0x380
80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006b8: e71c b.n 80004f4 <__adddf3+0x138>
80006ba: bf00 nop
080006bc <__aeabi_ul2d>:
80006bc: ea50 0201 orrs.w r2, r0, r1
80006c0: bf08 it eq
80006c2: 4770 bxeq lr
80006c4: b530 push {r4, r5, lr}
80006c6: f04f 0500 mov.w r5, #0
80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16>
080006cc <__aeabi_l2d>:
80006cc: ea50 0201 orrs.w r2, r0, r1
80006d0: bf08 it eq
80006d2: 4770 bxeq lr
80006d4: b530 push {r4, r5, lr}
80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16>
80006dc: 4240 negs r0, r0
80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1
80006e2: f44f 6480 mov.w r4, #1024 @ 0x400
80006e6: f104 0432 add.w r4, r4, #50 @ 0x32
80006ea: ea5f 5c91 movs.w ip, r1, lsr #22
80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6>
80006f2: f04f 0203 mov.w r2, #3
80006f6: ea5f 0cdc movs.w ip, ip, lsr #3
80006fa: bf18 it ne
80006fc: 3203 addne r2, #3
80006fe: ea5f 0cdc movs.w ip, ip, lsr #3
8000702: bf18 it ne
8000704: 3203 addne r2, #3
8000706: eb02 02dc add.w r2, r2, ip, lsr #3
800070a: f1c2 0320 rsb r3, r2, #32
800070e: fa00 fc03 lsl.w ip, r0, r3
8000712: fa20 f002 lsr.w r0, r0, r2
8000716: fa01 fe03 lsl.w lr, r1, r3
800071a: ea40 000e orr.w r0, r0, lr
800071e: fa21 f102 lsr.w r1, r1, r2
8000722: 4414 add r4, r2
8000724: e6bd b.n 80004a2 <__adddf3+0xe6>
8000726: bf00 nop
08000728 <__gedf2>:
8000728: f04f 3cff mov.w ip, #4294967295
800072c: e006 b.n 800073c <__cmpdf2+0x4>
800072e: bf00 nop
08000730 <__ledf2>:
8000730: f04f 0c01 mov.w ip, #1
8000734: e002 b.n 800073c <__cmpdf2+0x4>
8000736: bf00 nop
08000738 <__cmpdf2>:
8000738: f04f 0c01 mov.w ip, #1
800073c: f84d cd04 str.w ip, [sp, #-4]!
8000740: ea4f 0c41 mov.w ip, r1, lsl #1
8000744: ea7f 5c6c mvns.w ip, ip, asr #21
8000748: ea4f 0c43 mov.w ip, r3, lsl #1
800074c: bf18 it ne
800074e: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000752: d01b beq.n 800078c <__cmpdf2+0x54>
8000754: b001 add sp, #4
8000756: ea50 0c41 orrs.w ip, r0, r1, lsl #1
800075a: bf0c ite eq
800075c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000760: ea91 0f03 teqne r1, r3
8000764: bf02 ittt eq
8000766: ea90 0f02 teqeq r0, r2
800076a: 2000 moveq r0, #0
800076c: 4770 bxeq lr
800076e: f110 0f00 cmn.w r0, #0
8000772: ea91 0f03 teq r1, r3
8000776: bf58 it pl
8000778: 4299 cmppl r1, r3
800077a: bf08 it eq
800077c: 4290 cmpeq r0, r2
800077e: bf2c ite cs
8000780: 17d8 asrcs r0, r3, #31
8000782: ea6f 70e3 mvncc.w r0, r3, asr #31
8000786: f040 0001 orr.w r0, r0, #1
800078a: 4770 bx lr
800078c: ea4f 0c41 mov.w ip, r1, lsl #1
8000790: ea7f 5c6c mvns.w ip, ip, asr #21
8000794: d102 bne.n 800079c <__cmpdf2+0x64>
8000796: ea50 3c01 orrs.w ip, r0, r1, lsl #12
800079a: d107 bne.n 80007ac <__cmpdf2+0x74>
800079c: ea4f 0c43 mov.w ip, r3, lsl #1
80007a0: ea7f 5c6c mvns.w ip, ip, asr #21
80007a4: d1d6 bne.n 8000754 <__cmpdf2+0x1c>
80007a6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
80007aa: d0d3 beq.n 8000754 <__cmpdf2+0x1c>
80007ac: f85d 0b04 ldr.w r0, [sp], #4
80007b0: 4770 bx lr
80007b2: bf00 nop
080007b4 <__aeabi_cdrcmple>:
80007b4: 4684 mov ip, r0
80007b6: 4610 mov r0, r2
80007b8: 4662 mov r2, ip
80007ba: 468c mov ip, r1
80007bc: 4619 mov r1, r3
80007be: 4663 mov r3, ip
80007c0: e000 b.n 80007c4 <__aeabi_cdcmpeq>
80007c2: bf00 nop
080007c4 <__aeabi_cdcmpeq>:
80007c4: b501 push {r0, lr}
80007c6: f7ff ffb7 bl 8000738 <__cmpdf2>
80007ca: 2800 cmp r0, #0
80007cc: bf48 it mi
80007ce: f110 0f00 cmnmi.w r0, #0
80007d2: bd01 pop {r0, pc}
080007d4 <__aeabi_dcmpeq>:
80007d4: f84d ed08 str.w lr, [sp, #-8]!
80007d8: f7ff fff4 bl 80007c4 <__aeabi_cdcmpeq>
80007dc: bf0c ite eq
80007de: 2001 moveq r0, #1
80007e0: 2000 movne r0, #0
80007e2: f85d fb08 ldr.w pc, [sp], #8
80007e6: bf00 nop
080007e8 <__aeabi_dcmplt>:
80007e8: f84d ed08 str.w lr, [sp, #-8]!
80007ec: f7ff ffea bl 80007c4 <__aeabi_cdcmpeq>
80007f0: bf34 ite cc
80007f2: 2001 movcc r0, #1
80007f4: 2000 movcs r0, #0
80007f6: f85d fb08 ldr.w pc, [sp], #8
80007fa: bf00 nop
080007fc <__aeabi_dcmple>:
80007fc: f84d ed08 str.w lr, [sp, #-8]!
8000800: f7ff ffe0 bl 80007c4 <__aeabi_cdcmpeq>
8000804: bf94 ite ls
8000806: 2001 movls r0, #1
8000808: 2000 movhi r0, #0
800080a: f85d fb08 ldr.w pc, [sp], #8
800080e: bf00 nop
08000810 <__aeabi_dcmpge>:
8000810: f84d ed08 str.w lr, [sp, #-8]!
8000814: f7ff ffce bl 80007b4 <__aeabi_cdrcmple>
8000818: bf94 ite ls
800081a: 2001 movls r0, #1
800081c: 2000 movhi r0, #0
800081e: f85d fb08 ldr.w pc, [sp], #8
8000822: bf00 nop
08000824 <__aeabi_dcmpgt>:
8000824: f84d ed08 str.w lr, [sp, #-8]!
8000828: f7ff ffc4 bl 80007b4 <__aeabi_cdrcmple>
800082c: bf34 ite cc
800082e: 2001 movcc r0, #1
8000830: 2000 movcs r0, #0
8000832: f85d fb08 ldr.w pc, [sp], #8
8000836: bf00 nop
08000838 <__aeabi_d2iz>:
8000838: ea4f 0241 mov.w r2, r1, lsl #1
800083c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000840: d215 bcs.n 800086e <__aeabi_d2iz+0x36>
8000842: d511 bpl.n 8000868 <__aeabi_d2iz+0x30>
8000844: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000848: ebb3 5262 subs.w r2, r3, r2, asr #21
800084c: d912 bls.n 8000874 <__aeabi_d2iz+0x3c>
800084e: ea4f 23c1 mov.w r3, r1, lsl #11
8000852: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000856: ea43 5350 orr.w r3, r3, r0, lsr #21
800085a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
800085e: fa23 f002 lsr.w r0, r3, r2
8000862: bf18 it ne
8000864: 4240 negne r0, r0
8000866: 4770 bx lr
8000868: f04f 0000 mov.w r0, #0
800086c: 4770 bx lr
800086e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000872: d105 bne.n 8000880 <__aeabi_d2iz+0x48>
8000874: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000878: bf08 it eq
800087a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
800087e: 4770 bx lr
8000880: f04f 0000 mov.w r0, #0
8000884: 4770 bx lr
8000886: bf00 nop
08000888 <__aeabi_frsub>:
8000888: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
800088c: e002 b.n 8000894 <__addsf3>
800088e: bf00 nop
08000890 <__aeabi_fsub>:
8000890: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
08000894 <__addsf3>:
8000894: 0042 lsls r2, r0, #1
8000896: bf1f itttt ne
8000898: ea5f 0341 movsne.w r3, r1, lsl #1
800089c: ea92 0f03 teqne r2, r3
80008a0: ea7f 6c22 mvnsne.w ip, r2, asr #24
80008a4: ea7f 6c23 mvnsne.w ip, r3, asr #24
80008a8: d06a beq.n 8000980 <__addsf3+0xec>
80008aa: ea4f 6212 mov.w r2, r2, lsr #24
80008ae: ebd2 6313 rsbs r3, r2, r3, lsr #24
80008b2: bfc1 itttt gt
80008b4: 18d2 addgt r2, r2, r3
80008b6: 4041 eorgt r1, r0
80008b8: 4048 eorgt r0, r1
80008ba: 4041 eorgt r1, r0
80008bc: bfb8 it lt
80008be: 425b neglt r3, r3
80008c0: 2b19 cmp r3, #25
80008c2: bf88 it hi
80008c4: 4770 bxhi lr
80008c6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
80008ca: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80008ce: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
80008d2: bf18 it ne
80008d4: 4240 negne r0, r0
80008d6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80008da: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
80008de: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
80008e2: bf18 it ne
80008e4: 4249 negne r1, r1
80008e6: ea92 0f03 teq r2, r3
80008ea: d03f beq.n 800096c <__addsf3+0xd8>
80008ec: f1a2 0201 sub.w r2, r2, #1
80008f0: fa41 fc03 asr.w ip, r1, r3
80008f4: eb10 000c adds.w r0, r0, ip
80008f8: f1c3 0320 rsb r3, r3, #32
80008fc: fa01 f103 lsl.w r1, r1, r3
8000900: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
8000904: d502 bpl.n 800090c <__addsf3+0x78>
8000906: 4249 negs r1, r1
8000908: eb60 0040 sbc.w r0, r0, r0, lsl #1
800090c: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
8000910: d313 bcc.n 800093a <__addsf3+0xa6>
8000912: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
8000916: d306 bcc.n 8000926 <__addsf3+0x92>
8000918: 0840 lsrs r0, r0, #1
800091a: ea4f 0131 mov.w r1, r1, rrx
800091e: f102 0201 add.w r2, r2, #1
8000922: 2afe cmp r2, #254 @ 0xfe
8000924: d251 bcs.n 80009ca <__addsf3+0x136>
8000926: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
800092a: eb40 50c2 adc.w r0, r0, r2, lsl #23
800092e: bf08 it eq
8000930: f020 0001 biceq.w r0, r0, #1
8000934: ea40 0003 orr.w r0, r0, r3
8000938: 4770 bx lr
800093a: 0049 lsls r1, r1, #1
800093c: eb40 0000 adc.w r0, r0, r0
8000940: 3a01 subs r2, #1
8000942: bf28 it cs
8000944: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
8000948: d2ed bcs.n 8000926 <__addsf3+0x92>
800094a: fab0 fc80 clz ip, r0
800094e: f1ac 0c08 sub.w ip, ip, #8
8000952: ebb2 020c subs.w r2, r2, ip
8000956: fa00 f00c lsl.w r0, r0, ip
800095a: bfaa itet ge
800095c: eb00 50c2 addge.w r0, r0, r2, lsl #23
8000960: 4252 neglt r2, r2
8000962: 4318 orrge r0, r3
8000964: bfbc itt lt
8000966: 40d0 lsrlt r0, r2
8000968: 4318 orrlt r0, r3
800096a: 4770 bx lr
800096c: f092 0f00 teq r2, #0
8000970: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
8000974: bf06 itte eq
8000976: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
800097a: 3201 addeq r2, #1
800097c: 3b01 subne r3, #1
800097e: e7b5 b.n 80008ec <__addsf3+0x58>
8000980: ea4f 0341 mov.w r3, r1, lsl #1
8000984: ea7f 6c22 mvns.w ip, r2, asr #24
8000988: bf18 it ne
800098a: ea7f 6c23 mvnsne.w ip, r3, asr #24
800098e: d021 beq.n 80009d4 <__addsf3+0x140>
8000990: ea92 0f03 teq r2, r3
8000994: d004 beq.n 80009a0 <__addsf3+0x10c>
8000996: f092 0f00 teq r2, #0
800099a: bf08 it eq
800099c: 4608 moveq r0, r1
800099e: 4770 bx lr
80009a0: ea90 0f01 teq r0, r1
80009a4: bf1c itt ne
80009a6: 2000 movne r0, #0
80009a8: 4770 bxne lr
80009aa: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
80009ae: d104 bne.n 80009ba <__addsf3+0x126>
80009b0: 0040 lsls r0, r0, #1
80009b2: bf28 it cs
80009b4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
80009b8: 4770 bx lr
80009ba: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
80009be: bf3c itt cc
80009c0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
80009c4: 4770 bxcc lr
80009c6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
80009ca: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
80009ce: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80009d2: 4770 bx lr
80009d4: ea7f 6222 mvns.w r2, r2, asr #24
80009d8: bf16 itet ne
80009da: 4608 movne r0, r1
80009dc: ea7f 6323 mvnseq.w r3, r3, asr #24
80009e0: 4601 movne r1, r0
80009e2: 0242 lsls r2, r0, #9
80009e4: bf06 itte eq
80009e6: ea5f 2341 movseq.w r3, r1, lsl #9
80009ea: ea90 0f01 teqeq r0, r1
80009ee: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
80009f2: 4770 bx lr
080009f4 <__aeabi_ui2f>:
80009f4: f04f 0300 mov.w r3, #0
80009f8: e004 b.n 8000a04 <__aeabi_i2f+0x8>
80009fa: bf00 nop
080009fc <__aeabi_i2f>:
80009fc: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
8000a00: bf48 it mi
8000a02: 4240 negmi r0, r0
8000a04: ea5f 0c00 movs.w ip, r0
8000a08: bf08 it eq
8000a0a: 4770 bxeq lr
8000a0c: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
8000a10: 4601 mov r1, r0
8000a12: f04f 0000 mov.w r0, #0
8000a16: e01c b.n 8000a52 <__aeabi_l2f+0x2a>
08000a18 <__aeabi_ul2f>:
8000a18: ea50 0201 orrs.w r2, r0, r1
8000a1c: bf08 it eq
8000a1e: 4770 bxeq lr
8000a20: f04f 0300 mov.w r3, #0
8000a24: e00a b.n 8000a3c <__aeabi_l2f+0x14>
8000a26: bf00 nop
08000a28 <__aeabi_l2f>:
8000a28: ea50 0201 orrs.w r2, r0, r1
8000a2c: bf08 it eq
8000a2e: 4770 bxeq lr
8000a30: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
8000a34: d502 bpl.n 8000a3c <__aeabi_l2f+0x14>
8000a36: 4240 negs r0, r0
8000a38: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000a3c: ea5f 0c01 movs.w ip, r1
8000a40: bf02 ittt eq
8000a42: 4684 moveq ip, r0
8000a44: 4601 moveq r1, r0
8000a46: 2000 moveq r0, #0
8000a48: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
8000a4c: bf08 it eq
8000a4e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
8000a52: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
8000a56: fabc f28c clz r2, ip
8000a5a: 3a08 subs r2, #8
8000a5c: eba3 53c2 sub.w r3, r3, r2, lsl #23
8000a60: db10 blt.n 8000a84 <__aeabi_l2f+0x5c>
8000a62: fa01 fc02 lsl.w ip, r1, r2
8000a66: 4463 add r3, ip
8000a68: fa00 fc02 lsl.w ip, r0, r2
8000a6c: f1c2 0220 rsb r2, r2, #32
8000a70: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000a74: fa20 f202 lsr.w r2, r0, r2
8000a78: eb43 0002 adc.w r0, r3, r2
8000a7c: bf08 it eq
8000a7e: f020 0001 biceq.w r0, r0, #1
8000a82: 4770 bx lr
8000a84: f102 0220 add.w r2, r2, #32
8000a88: fa01 fc02 lsl.w ip, r1, r2
8000a8c: f1c2 0220 rsb r2, r2, #32
8000a90: ea50 004c orrs.w r0, r0, ip, lsl #1
8000a94: fa21 f202 lsr.w r2, r1, r2
8000a98: eb43 0002 adc.w r0, r3, r2
8000a9c: bf08 it eq
8000a9e: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000aa2: 4770 bx lr
08000aa4 <__aeabi_fmul>:
8000aa4: f04f 0cff mov.w ip, #255 @ 0xff
8000aa8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000aac: bf1e ittt ne
8000aae: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000ab2: ea92 0f0c teqne r2, ip
8000ab6: ea93 0f0c teqne r3, ip
8000aba: d06f beq.n 8000b9c <__aeabi_fmul+0xf8>
8000abc: 441a add r2, r3
8000abe: ea80 0c01 eor.w ip, r0, r1
8000ac2: 0240 lsls r0, r0, #9
8000ac4: bf18 it ne
8000ac6: ea5f 2141 movsne.w r1, r1, lsl #9
8000aca: d01e beq.n 8000b0a <__aeabi_fmul+0x66>
8000acc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000ad0: ea43 1050 orr.w r0, r3, r0, lsr #5
8000ad4: ea43 1151 orr.w r1, r3, r1, lsr #5
8000ad8: fba0 3101 umull r3, r1, r0, r1
8000adc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000ae0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8000ae4: bf3e ittt cc
8000ae6: 0049 lslcc r1, r1, #1
8000ae8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
8000aec: 005b lslcc r3, r3, #1
8000aee: ea40 0001 orr.w r0, r0, r1
8000af2: f162 027f sbc.w r2, r2, #127 @ 0x7f
8000af6: 2afd cmp r2, #253 @ 0xfd
8000af8: d81d bhi.n 8000b36 <__aeabi_fmul+0x92>
8000afa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8000afe: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000b02: bf08 it eq
8000b04: f020 0001 biceq.w r0, r0, #1
8000b08: 4770 bx lr
8000b0a: f090 0f00 teq r0, #0
8000b0e: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000b12: bf08 it eq
8000b14: 0249 lsleq r1, r1, #9
8000b16: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000b1a: ea40 2051 orr.w r0, r0, r1, lsr #9
8000b1e: 3a7f subs r2, #127 @ 0x7f
8000b20: bfc2 ittt gt
8000b22: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000b26: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000b2a: 4770 bxgt lr
8000b2c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000b30: f04f 0300 mov.w r3, #0
8000b34: 3a01 subs r2, #1
8000b36: dc5d bgt.n 8000bf4 <__aeabi_fmul+0x150>
8000b38: f112 0f19 cmn.w r2, #25
8000b3c: bfdc itt le
8000b3e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
8000b42: 4770 bxle lr
8000b44: f1c2 0200 rsb r2, r2, #0
8000b48: 0041 lsls r1, r0, #1
8000b4a: fa21 f102 lsr.w r1, r1, r2
8000b4e: f1c2 0220 rsb r2, r2, #32
8000b52: fa00 fc02 lsl.w ip, r0, r2
8000b56: ea5f 0031 movs.w r0, r1, rrx
8000b5a: f140 0000 adc.w r0, r0, #0
8000b5e: ea53 034c orrs.w r3, r3, ip, lsl #1
8000b62: bf08 it eq
8000b64: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000b68: 4770 bx lr
8000b6a: f092 0f00 teq r2, #0
8000b6e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000b72: bf02 ittt eq
8000b74: 0040 lsleq r0, r0, #1
8000b76: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000b7a: 3a01 subeq r2, #1
8000b7c: d0f9 beq.n 8000b72 <__aeabi_fmul+0xce>
8000b7e: ea40 000c orr.w r0, r0, ip
8000b82: f093 0f00 teq r3, #0
8000b86: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000b8a: bf02 ittt eq
8000b8c: 0049 lsleq r1, r1, #1
8000b8e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000b92: 3b01 subeq r3, #1
8000b94: d0f9 beq.n 8000b8a <__aeabi_fmul+0xe6>
8000b96: ea41 010c orr.w r1, r1, ip
8000b9a: e78f b.n 8000abc <__aeabi_fmul+0x18>
8000b9c: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000ba0: ea92 0f0c teq r2, ip
8000ba4: bf18 it ne
8000ba6: ea93 0f0c teqne r3, ip
8000baa: d00a beq.n 8000bc2 <__aeabi_fmul+0x11e>
8000bac: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000bb0: bf18 it ne
8000bb2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000bb6: d1d8 bne.n 8000b6a <__aeabi_fmul+0xc6>
8000bb8: ea80 0001 eor.w r0, r0, r1
8000bbc: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bc0: 4770 bx lr
8000bc2: f090 0f00 teq r0, #0
8000bc6: bf17 itett ne
8000bc8: f090 4f00 teqne r0, #2147483648 @ 0x80000000
8000bcc: 4608 moveq r0, r1
8000bce: f091 0f00 teqne r1, #0
8000bd2: f091 4f00 teqne r1, #2147483648 @ 0x80000000
8000bd6: d014 beq.n 8000c02 <__aeabi_fmul+0x15e>
8000bd8: ea92 0f0c teq r2, ip
8000bdc: d101 bne.n 8000be2 <__aeabi_fmul+0x13e>
8000bde: 0242 lsls r2, r0, #9
8000be0: d10f bne.n 8000c02 <__aeabi_fmul+0x15e>
8000be2: ea93 0f0c teq r3, ip
8000be6: d103 bne.n 8000bf0 <__aeabi_fmul+0x14c>
8000be8: 024b lsls r3, r1, #9
8000bea: bf18 it ne
8000bec: 4608 movne r0, r1
8000bee: d108 bne.n 8000c02 <__aeabi_fmul+0x15e>
8000bf0: ea80 0001 eor.w r0, r0, r1
8000bf4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bf8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000bfc: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c00: 4770 bx lr
8000c02: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000c06: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
8000c0a: 4770 bx lr
08000c0c <__aeabi_fdiv>:
8000c0c: f04f 0cff mov.w ip, #255 @ 0xff
8000c10: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000c14: bf1e ittt ne
8000c16: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000c1a: ea92 0f0c teqne r2, ip
8000c1e: ea93 0f0c teqne r3, ip
8000c22: d069 beq.n 8000cf8 <__aeabi_fdiv+0xec>
8000c24: eba2 0203 sub.w r2, r2, r3
8000c28: ea80 0c01 eor.w ip, r0, r1
8000c2c: 0249 lsls r1, r1, #9
8000c2e: ea4f 2040 mov.w r0, r0, lsl #9
8000c32: d037 beq.n 8000ca4 <__aeabi_fdiv+0x98>
8000c34: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8000c38: ea43 1111 orr.w r1, r3, r1, lsr #4
8000c3c: ea43 1310 orr.w r3, r3, r0, lsr #4
8000c40: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000c44: 428b cmp r3, r1
8000c46: bf38 it cc
8000c48: 005b lslcc r3, r3, #1
8000c4a: f142 027d adc.w r2, r2, #125 @ 0x7d
8000c4e: f44f 0c00 mov.w ip, #8388608 @ 0x800000
8000c52: 428b cmp r3, r1
8000c54: bf24 itt cs
8000c56: 1a5b subcs r3, r3, r1
8000c58: ea40 000c orrcs.w r0, r0, ip
8000c5c: ebb3 0f51 cmp.w r3, r1, lsr #1
8000c60: bf24 itt cs
8000c62: eba3 0351 subcs.w r3, r3, r1, lsr #1
8000c66: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000c6a: ebb3 0f91 cmp.w r3, r1, lsr #2
8000c6e: bf24 itt cs
8000c70: eba3 0391 subcs.w r3, r3, r1, lsr #2
8000c74: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000c78: ebb3 0fd1 cmp.w r3, r1, lsr #3
8000c7c: bf24 itt cs
8000c7e: eba3 03d1 subcs.w r3, r3, r1, lsr #3
8000c82: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000c86: 011b lsls r3, r3, #4
8000c88: bf18 it ne
8000c8a: ea5f 1c1c movsne.w ip, ip, lsr #4
8000c8e: d1e0 bne.n 8000c52 <__aeabi_fdiv+0x46>
8000c90: 2afd cmp r2, #253 @ 0xfd
8000c92: f63f af50 bhi.w 8000b36 <__aeabi_fmul+0x92>
8000c96: 428b cmp r3, r1
8000c98: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000c9c: bf08 it eq
8000c9e: f020 0001 biceq.w r0, r0, #1
8000ca2: 4770 bx lr
8000ca4: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000ca8: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000cac: 327f adds r2, #127 @ 0x7f
8000cae: bfc2 ittt gt
8000cb0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000cb4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000cb8: 4770 bxgt lr
8000cba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000cbe: f04f 0300 mov.w r3, #0
8000cc2: 3a01 subs r2, #1
8000cc4: e737 b.n 8000b36 <__aeabi_fmul+0x92>
8000cc6: f092 0f00 teq r2, #0
8000cca: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000cce: bf02 ittt eq
8000cd0: 0040 lsleq r0, r0, #1
8000cd2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000cd6: 3a01 subeq r2, #1
8000cd8: d0f9 beq.n 8000cce <__aeabi_fdiv+0xc2>
8000cda: ea40 000c orr.w r0, r0, ip
8000cde: f093 0f00 teq r3, #0
8000ce2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000ce6: bf02 ittt eq
8000ce8: 0049 lsleq r1, r1, #1
8000cea: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000cee: 3b01 subeq r3, #1
8000cf0: d0f9 beq.n 8000ce6 <__aeabi_fdiv+0xda>
8000cf2: ea41 010c orr.w r1, r1, ip
8000cf6: e795 b.n 8000c24 <__aeabi_fdiv+0x18>
8000cf8: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000cfc: ea92 0f0c teq r2, ip
8000d00: d108 bne.n 8000d14 <__aeabi_fdiv+0x108>
8000d02: 0242 lsls r2, r0, #9
8000d04: f47f af7d bne.w 8000c02 <__aeabi_fmul+0x15e>
8000d08: ea93 0f0c teq r3, ip
8000d0c: f47f af70 bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d10: 4608 mov r0, r1
8000d12: e776 b.n 8000c02 <__aeabi_fmul+0x15e>
8000d14: ea93 0f0c teq r3, ip
8000d18: d104 bne.n 8000d24 <__aeabi_fdiv+0x118>
8000d1a: 024b lsls r3, r1, #9
8000d1c: f43f af4c beq.w 8000bb8 <__aeabi_fmul+0x114>
8000d20: 4608 mov r0, r1
8000d22: e76e b.n 8000c02 <__aeabi_fmul+0x15e>
8000d24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000d28: bf18 it ne
8000d2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000d2e: d1ca bne.n 8000cc6 <__aeabi_fdiv+0xba>
8000d30: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
8000d34: f47f af5c bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d38: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
8000d3c: f47f af3c bne.w 8000bb8 <__aeabi_fmul+0x114>
8000d40: e75f b.n 8000c02 <__aeabi_fmul+0x15e>
8000d42: bf00 nop
08000d44 <__gesf2>:
8000d44: f04f 3cff mov.w ip, #4294967295
8000d48: e006 b.n 8000d58 <__cmpsf2+0x4>
8000d4a: bf00 nop
08000d4c <__lesf2>:
8000d4c: f04f 0c01 mov.w ip, #1
8000d50: e002 b.n 8000d58 <__cmpsf2+0x4>
8000d52: bf00 nop
08000d54 <__cmpsf2>:
8000d54: f04f 0c01 mov.w ip, #1
8000d58: f84d cd04 str.w ip, [sp, #-4]!
8000d5c: ea4f 0240 mov.w r2, r0, lsl #1
8000d60: ea4f 0341 mov.w r3, r1, lsl #1
8000d64: ea7f 6c22 mvns.w ip, r2, asr #24
8000d68: bf18 it ne
8000d6a: ea7f 6c23 mvnsne.w ip, r3, asr #24
8000d6e: d011 beq.n 8000d94 <__cmpsf2+0x40>
8000d70: b001 add sp, #4
8000d72: ea52 0c53 orrs.w ip, r2, r3, lsr #1
8000d76: bf18 it ne
8000d78: ea90 0f01 teqne r0, r1
8000d7c: bf58 it pl
8000d7e: ebb2 0003 subspl.w r0, r2, r3
8000d82: bf88 it hi
8000d84: 17c8 asrhi r0, r1, #31
8000d86: bf38 it cc
8000d88: ea6f 70e1 mvncc.w r0, r1, asr #31
8000d8c: bf18 it ne
8000d8e: f040 0001 orrne.w r0, r0, #1
8000d92: 4770 bx lr
8000d94: ea7f 6c22 mvns.w ip, r2, asr #24
8000d98: d102 bne.n 8000da0 <__cmpsf2+0x4c>
8000d9a: ea5f 2c40 movs.w ip, r0, lsl #9
8000d9e: d105 bne.n 8000dac <__cmpsf2+0x58>
8000da0: ea7f 6c23 mvns.w ip, r3, asr #24
8000da4: d1e4 bne.n 8000d70 <__cmpsf2+0x1c>
8000da6: ea5f 2c41 movs.w ip, r1, lsl #9
8000daa: d0e1 beq.n 8000d70 <__cmpsf2+0x1c>
8000dac: f85d 0b04 ldr.w r0, [sp], #4
8000db0: 4770 bx lr
8000db2: bf00 nop
08000db4 <__aeabi_cfrcmple>:
8000db4: 4684 mov ip, r0
8000db6: 4608 mov r0, r1
8000db8: 4661 mov r1, ip
8000dba: e7ff b.n 8000dbc <__aeabi_cfcmpeq>
08000dbc <__aeabi_cfcmpeq>:
8000dbc: b50f push {r0, r1, r2, r3, lr}
8000dbe: f7ff ffc9 bl 8000d54 <__cmpsf2>
8000dc2: 2800 cmp r0, #0
8000dc4: bf48 it mi
8000dc6: f110 0f00 cmnmi.w r0, #0
8000dca: bd0f pop {r0, r1, r2, r3, pc}
08000dcc <__aeabi_fcmpeq>:
8000dcc: f84d ed08 str.w lr, [sp, #-8]!
8000dd0: f7ff fff4 bl 8000dbc <__aeabi_cfcmpeq>
8000dd4: bf0c ite eq
8000dd6: 2001 moveq r0, #1
8000dd8: 2000 movne r0, #0
8000dda: f85d fb08 ldr.w pc, [sp], #8
8000dde: bf00 nop
08000de0 <__aeabi_fcmplt>:
8000de0: f84d ed08 str.w lr, [sp, #-8]!
8000de4: f7ff ffea bl 8000dbc <__aeabi_cfcmpeq>
8000de8: bf34 ite cc
8000dea: 2001 movcc r0, #1
8000dec: 2000 movcs r0, #0
8000dee: f85d fb08 ldr.w pc, [sp], #8
8000df2: bf00 nop
08000df4 <__aeabi_fcmple>:
8000df4: f84d ed08 str.w lr, [sp, #-8]!
8000df8: f7ff ffe0 bl 8000dbc <__aeabi_cfcmpeq>
8000dfc: bf94 ite ls
8000dfe: 2001 movls r0, #1
8000e00: 2000 movhi r0, #0
8000e02: f85d fb08 ldr.w pc, [sp], #8
8000e06: bf00 nop
08000e08 <__aeabi_fcmpge>:
8000e08: f84d ed08 str.w lr, [sp, #-8]!
8000e0c: f7ff ffd2 bl 8000db4 <__aeabi_cfrcmple>
8000e10: bf94 ite ls
8000e12: 2001 movls r0, #1
8000e14: 2000 movhi r0, #0
8000e16: f85d fb08 ldr.w pc, [sp], #8
8000e1a: bf00 nop
08000e1c <__aeabi_fcmpgt>:
8000e1c: f84d ed08 str.w lr, [sp, #-8]!
8000e20: f7ff ffc8 bl 8000db4 <__aeabi_cfrcmple>
8000e24: bf34 ite cc
8000e26: 2001 movcc r0, #1
8000e28: 2000 movcs r0, #0
8000e2a: f85d fb08 ldr.w pc, [sp], #8
8000e2e: bf00 nop
08000e30 <__aeabi_fcmpun>:
8000e30: ea4f 0240 mov.w r2, r0, lsl #1
8000e34: ea4f 0341 mov.w r3, r1, lsl #1
8000e38: ea7f 6c22 mvns.w ip, r2, asr #24
8000e3c: d102 bne.n 8000e44 <__aeabi_fcmpun+0x14>
8000e3e: ea5f 2c40 movs.w ip, r0, lsl #9
8000e42: d108 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e44: ea7f 6c23 mvns.w ip, r3, asr #24
8000e48: d102 bne.n 8000e50 <__aeabi_fcmpun+0x20>
8000e4a: ea5f 2c41 movs.w ip, r1, lsl #9
8000e4e: d102 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e50: f04f 0000 mov.w r0, #0
8000e54: 4770 bx lr
8000e56: f04f 0001 mov.w r0, #1
8000e5a: 4770 bx lr
08000e5c <__aeabi_f2iz>:
8000e5c: ea4f 0240 mov.w r2, r0, lsl #1
8000e60: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
8000e64: d30f bcc.n 8000e86 <__aeabi_f2iz+0x2a>
8000e66: f04f 039e mov.w r3, #158 @ 0x9e
8000e6a: ebb3 6212 subs.w r2, r3, r2, lsr #24
8000e6e: d90d bls.n 8000e8c <__aeabi_f2iz+0x30>
8000e70: ea4f 2300 mov.w r3, r0, lsl #8
8000e74: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000e78: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
8000e7c: fa23 f002 lsr.w r0, r3, r2
8000e80: bf18 it ne
8000e82: 4240 negne r0, r0
8000e84: 4770 bx lr
8000e86: f04f 0000 mov.w r0, #0
8000e8a: 4770 bx lr
8000e8c: f112 0f61 cmn.w r2, #97 @ 0x61
8000e90: d101 bne.n 8000e96 <__aeabi_f2iz+0x3a>
8000e92: 0242 lsls r2, r0, #9
8000e94: d105 bne.n 8000ea2 <__aeabi_f2iz+0x46>
8000e96: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000
8000e9a: bf08 it eq
8000e9c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000ea0: 4770 bx lr
8000ea2: f04f 0000 mov.w r0, #0
8000ea6: 4770 bx lr
08000ea8 <AD5934_SetRegisterValue>:
* @param numberOfBytes - Number of bytes to be written in the register
*
* @return None.
******************************************************************************/
void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
{
8000ea8: b580 push {r7, lr}
8000eaa: b086 sub sp, #24
8000eac: af02 add r7, sp, #8
8000eae: 4603 mov r3, r0
8000eb0: 6039 str r1, [r7, #0]
8000eb2: 71fb strb r3, [r7, #7]
8000eb4: 4613 mov r3, r2
8000eb6: 71bb strb r3, [r7, #6]
uint8_t writeData[2] = {0, 0};
8000eb8: 2300 movs r3, #0
8000eba: 81bb strh r3, [r7, #12]
HAL_StatusTypeDef status;
union Bytes2Long AD5934_reg;
AD5934_reg.number = registerValue;
8000ebc: 683b ldr r3, [r7, #0]
8000ebe: 60bb str r3, [r7, #8]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ec0: 2300 movs r3, #0
8000ec2: 73fb strb r3, [r7, #15]
8000ec4: e018 b.n 8000ef8 <AD5934_SetRegisterValue+0x50>
{
writeData[0] = registerAddress - i;
8000ec6: 79fa ldrb r2, [r7, #7]
8000ec8: 7bfb ldrb r3, [r7, #15]
8000eca: 1ad3 subs r3, r2, r3
8000ecc: b2db uxtb r3, r3
8000ece: 733b strb r3, [r7, #12]
writeData[1] = AD5934_reg.bytes[i];
8000ed0: 7bfb ldrb r3, [r7, #15]
8000ed2: 3310 adds r3, #16
8000ed4: 443b add r3, r7
8000ed6: f813 3c08 ldrb.w r3, [r3, #-8]
8000eda: 737b strb r3, [r7, #13]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000edc: f107 020c add.w r2, r7, #12
8000ee0: 2305 movs r3, #5
8000ee2: 9300 str r3, [sp, #0]
8000ee4: 2302 movs r3, #2
8000ee6: 211a movs r1, #26
8000ee8: 4807 ldr r0, [pc, #28] @ (8000f08 <AD5934_SetRegisterValue+0x60>)
8000eea: f002 ffcf bl 8003e8c <HAL_I2C_Master_Transmit>
8000eee: 4603 mov r3, r0
8000ef0: 73bb strb r3, [r7, #14]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ef2: 7bfb ldrb r3, [r7, #15]
8000ef4: 3301 adds r3, #1
8000ef6: 73fb strb r3, [r7, #15]
8000ef8: 7bfa ldrb r2, [r7, #15]
8000efa: 79bb ldrb r3, [r7, #6]
8000efc: 429a cmp r2, r3
8000efe: d3e2 bcc.n 8000ec6 <AD5934_SetRegisterValue+0x1e>
}
return;
8000f00: bf00 nop
}
8000f02: 3710 adds r7, #16
8000f04: 46bd mov sp, r7
8000f06: bd80 pop {r7, pc}
8000f08: 20000600 .word 0x20000600
08000f0c <AD5934_GetRegisterValue>:
* @param numberOfBytes - Number of bytes to be read from the register.
*
* @return Register value.
******************************************************************************/
uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
{
8000f0c: b580 push {r7, lr}
8000f0e: b088 sub sp, #32
8000f10: af02 add r7, sp, #8
8000f12: 4603 mov r3, r0
8000f14: 460a mov r2, r1
8000f16: 71fb strb r3, [r7, #7]
8000f18: 4613 mov r3, r2
8000f1a: 71bb strb r3, [r7, #6]
uint8_t readData[1] = {0};
8000f1c: 2300 movs r3, #0
8000f1e: 753b strb r3, [r7, #20]
uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
union Bytes2Long AD5934_reg;
HAL_StatusTypeDef status;
if(numberOfBytes > 4)
8000f20: 79bb ldrb r3, [r7, #6]
8000f22: 2b04 cmp r3, #4
8000f24: d902 bls.n 8000f2c <AD5934_GetRegisterValue+0x20>
return 0xFFFFFFFF; //Overflow
8000f26: f04f 33ff mov.w r3, #4294967295
8000f2a: e031 b.n 8000f90 <AD5934_GetRegisterValue+0x84>
AD5934_reg.number = 0;
8000f2c: 2300 movs r3, #0
8000f2e: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f30: 2300 movs r3, #0
8000f32: 75fb strb r3, [r7, #23]
8000f34: e027 b.n 8000f86 <AD5934_GetRegisterValue+0x7a>
{
writeData[0] = AD5934_ADDR_POINTER;
8000f36: 23b0 movs r3, #176 @ 0xb0
8000f38: 743b strb r3, [r7, #16]
writeData[1] = registerAddress - i;
8000f3a: 79fa ldrb r2, [r7, #7]
8000f3c: 7dfb ldrb r3, [r7, #23]
8000f3e: 1ad3 subs r3, r2, r3
8000f40: b2db uxtb r3, r3
8000f42: 747b strb r3, [r7, #17]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000f44: f107 0210 add.w r2, r7, #16
8000f48: 2305 movs r3, #5
8000f4a: 9300 str r3, [sp, #0]
8000f4c: 2302 movs r3, #2
8000f4e: 211a movs r1, #26
8000f50: 4811 ldr r0, [pc, #68] @ (8000f98 <AD5934_GetRegisterValue+0x8c>)
8000f52: f002 ff9b bl 8003e8c <HAL_I2C_Master_Transmit>
8000f56: 4603 mov r3, r0
8000f58: 75bb strb r3, [r7, #22]
//HAL_Delay(1);
readData[0] = 0;
8000f5a: 2300 movs r3, #0
8000f5c: 753b strb r3, [r7, #20]
status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
8000f5e: f107 0214 add.w r2, r7, #20
8000f62: 2305 movs r3, #5
8000f64: 9300 str r3, [sp, #0]
8000f66: 2301 movs r3, #1
8000f68: 211a movs r1, #26
8000f6a: 480b ldr r0, [pc, #44] @ (8000f98 <AD5934_GetRegisterValue+0x8c>)
8000f6c: f003 f88c bl 8004088 <HAL_I2C_Master_Receive>
8000f70: 4603 mov r3, r0
8000f72: 75bb strb r3, [r7, #22]
AD5934_reg.bytes[i]=readData[0];
8000f74: 7dfb ldrb r3, [r7, #23]
8000f76: 7d3a ldrb r2, [r7, #20]
8000f78: 3318 adds r3, #24
8000f7a: 443b add r3, r7
8000f7c: f803 2c0c strb.w r2, [r3, #-12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f80: 7dfb ldrb r3, [r7, #23]
8000f82: 3301 adds r3, #1
8000f84: 75fb strb r3, [r7, #23]
8000f86: 7dfa ldrb r2, [r7, #23]
8000f88: 79bb ldrb r3, [r7, #6]
8000f8a: 429a cmp r2, r3
8000f8c: d3d3 bcc.n 8000f36 <AD5934_GetRegisterValue+0x2a>
/*
AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048;
AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048;
*/
return AD5934_reg.number;
8000f8e: 68fb ldr r3, [r7, #12]
}
8000f90: 4618 mov r0, r3
8000f92: 3718 adds r7, #24
8000f94: 46bd mov sp, r7
8000f96: bd80 pop {r7, pc}
8000f98: 20000600 .word 0x20000600
08000f9c <AD5934_Init>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_Init(void)
{
8000f9c: b580 push {r7, lr}
8000f9e: af00 add r7, sp, #0
/************ Config Sweep******************/
// Place AD5934 in reset
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
8000fa0: 2201 movs r2, #1
8000fa2: f44f 7180 mov.w r1, #256 @ 0x100
8000fa6: 2081 movs r0, #129 @ 0x81
8000fa8: f7ff ff7e bl 8000ea8 <AD5934_SetRegisterValue>
// Configure starting frequency
AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_1K590HZ, 3);
8000fac: 2203 movs r2, #3
8000fae: 490a ldr r1, [pc, #40] @ (8000fd8 <AD5934_Init+0x3c>)
8000fb0: 2084 movs r0, #132 @ 0x84
8000fb2: f7ff ff79 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure frequency increment step
AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
8000fb6: 2203 movs r2, #3
8000fb8: 2100 movs r1, #0
8000fba: 2087 movs r0, #135 @ 0x87
8000fbc: f7ff ff74 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure number of steps
AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
8000fc0: 2202 movs r2, #2
8000fc2: 2100 movs r1, #0
8000fc4: 2089 movs r0, #137 @ 0x89
8000fc6: f7ff ff6f bl 8000ea8 <AD5934_SetRegisterValue>
// Set 128 Settling Time
AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_0S01, 2);
8000fca: 2202 movs r2, #2
8000fcc: 210c movs r1, #12
8000fce: 208b movs r0, #139 @ 0x8b
8000fd0: f7ff ff6a bl 8000ea8 <AD5934_SetRegisterValue>
}
8000fd4: bf00 nop
8000fd6: bd80 pop {r7, pc}
8000fd8: 003419e3 .word 0x003419e3
08000fdc <AD5934_RestartSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_RestartSweep(void)
{
8000fdc: b580 push {r7, lr}
8000fde: af00 add r7, sp, #0
// Place AD5934 in standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
8000fe0: 2201 movs r2, #1
8000fe2: 21b4 movs r1, #180 @ 0xb4
8000fe4: 2080 movs r0, #128 @ 0x80
8000fe6: f7ff ff5f bl 8000ea8 <AD5934_SetRegisterValue>
// Initialize starting frequency, Start frequency sweep, standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
8000fea: 2201 movs r2, #1
8000fec: 2114 movs r1, #20
8000fee: 2080 movs r0, #128 @ 0x80
8000ff0: f7ff ff5a bl 8000ea8 <AD5934_SetRegisterValue>
// Disable Internal Reset State
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, AD5934_CONTROL_FUNCTION(AD5934_RESERVED), 1);
8000ff4: 2201 movs r2, #1
8000ff6: 2180 movs r1, #128 @ 0x80
8000ff8: 2081 movs r0, #129 @ 0x81
8000ffa: f7ff ff55 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure Range Output, PGA gain andPlace AD5934 in sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
8000ffe: 2201 movs r2, #1
8001000: 2124 movs r1, #36 @ 0x24
8001002: 2080 movs r0, #128 @ 0x80
8001004: f7ff ff50 bl 8000ea8 <AD5934_SetRegisterValue>
// Wait for data to be valid
AD5934_Wait_For_Data_Valid();
8001008: f000 fb1e bl 8001648 <AD5934_Wait_For_Data_Valid>
// Power Down
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
800100c: 2201 movs r2, #1
800100e: 21a4 movs r1, #164 @ 0xa4
8001010: 2080 movs r0, #128 @ 0x80
8001012: f7ff ff49 bl 8000ea8 <AD5934_SetRegisterValue>
}
8001016: bf00 nop
8001018: bd80 pop {r7, pc}
0800101a <AD5934_Sweep>:
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC
*
* @return Real(int16) and Imaginary(int16) numbers into a int32.
******************************************************************************/
uint32_t AD5934_Sweep(void)
{
800101a: b580 push {r7, lr}
800101c: b082 sub sp, #8
800101e: af00 add r7, sp, #0
int16_t real_value, imag_value;
uint32_t value=0;
8001020: 2300 movs r3, #0
8001022: 607b str r3, [r7, #4]
// Restart Sweeping
AD5934_RestartSweep();
8001024: f7ff ffda bl 8000fdc <AD5934_RestartSweep>
real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2)));
8001028: 2102 movs r1, #2
800102a: 2095 movs r0, #149 @ 0x95
800102c: f7ff ff6e bl 8000f0c <AD5934_GetRegisterValue>
8001030: 4603 mov r3, r0
8001032: 807b strh r3, [r7, #2]
imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2)));
8001034: 2102 movs r1, #2
8001036: 2097 movs r0, #151 @ 0x97
8001038: f7ff ff68 bl 8000f0c <AD5934_GetRegisterValue>
800103c: 4603 mov r3, r0
800103e: 803b strh r3, [r7, #0]
// Get Real (16-bit) and Imaginary (16-bit) values into an unsigned 32-bit
value = ((((uint16_t)(imag_value))<<16) | ((uint16_t)(real_value)));
8001040: 883b ldrh r3, [r7, #0]
8001042: 041b lsls r3, r3, #16
8001044: 887a ldrh r2, [r7, #2]
8001046: 4313 orrs r3, r2
8001048: 607b str r3, [r7, #4]
return value;
800104a: 687b ldr r3, [r7, #4]
}
800104c: 4618 mov r0, r3
800104e: 3708 adds r7, #8
8001050: 46bd mov sp, r7
8001052: bd80 pop {r7, pc}
08001054 <AD5934_GetTemperature>:
* @param channel - AD5934_CH_PT100 or AD5934_CH_PT1000.
*
* @return impedance.
******************************************************************************/
float AD5934_GetTemperature(void)
{
8001054: b590 push {r4, r7, lr}
8001056: b093 sub sp, #76 @ 0x4c
8001058: af00 add r7, sp, #0
uint8_t i, ch_dut, ch_ref;
uint32_t sample;
int32_t ref_sum[2], dut_sum[2];
float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum, gain_factor;
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
800105a: 2180 movs r1, #128 @ 0x80
800105c: 48ab ldr r0, [pc, #684] @ (800130c <AD5934_GetTemperature+0x2b8>)
800105e: f002 fd89 bl 8003b74 <HAL_GPIO_ReadPin>
8001062: 4603 mov r3, r0
8001064: 2b01 cmp r3, #1
8001066: d108 bne.n 800107a <AD5934_GetTemperature+0x26>
{
ch_ref = AD5934_CH_REF100R_LOW_GAIN;
8001068: 2309 movs r3, #9
800106a: f887 3045 strb.w r3, [r7, #69] @ 0x45
ch_dut = AD5934_CH_RTD_LOW_GAIN; //PT100
800106e: 2341 movs r3, #65 @ 0x41
8001070: f887 3046 strb.w r3, [r7, #70] @ 0x46
gain_factor = 100.0f;
8001074: 4ba6 ldr r3, [pc, #664] @ (8001310 <AD5934_GetTemperature+0x2bc>)
8001076: 63bb str r3, [r7, #56] @ 0x38
8001078: e007 b.n 800108a <AD5934_GetTemperature+0x36>
}
else
{
ch_ref = AD5934_CH_REF1K_MID_GAIN;
800107a: 2312 movs r3, #18
800107c: f887 3045 strb.w r3, [r7, #69] @ 0x45
ch_dut = AD5934_CH_RTD_MID_GAIN; //PT1000
8001080: 2342 movs r3, #66 @ 0x42
8001082: f887 3046 strb.w r3, [r7, #70] @ 0x46
gain_factor = 1000.0f;
8001086: 4ba3 ldr r3, [pc, #652] @ (8001314 <AD5934_GetTemperature+0x2c0>)
8001088: 63bb str r3, [r7, #56] @ 0x38
}
ADG715_Update(ch_ref); // Set the Reference Resistor on board in the Analog Mux
800108a: f897 3045 ldrb.w r3, [r7, #69] @ 0x45
800108e: 4618 mov r0, r3
8001090: f000 fb7a bl 8001788 <ADG715_Update>
HAL_Delay(2); //Wait a little
8001094: 2002 movs r0, #2
8001096: f001 fdf3 bl 8002c80 <HAL_Delay>
sample = AD5934_Sweep(); // Get Reference Resistor Values from ADC
800109a: f7ff ffbe bl 800101a <AD5934_Sweep>
800109e: 6378 str r0, [r7, #52] @ 0x34
// Move values in the vectors
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80010a0: 2307 movs r3, #7
80010a2: f887 3047 strb.w r3, [r7, #71] @ 0x47
80010a6: e01e b.n 80010e6 <AD5934_GetTemperature+0x92>
{
temperature_ref_samples[i][0] = temperature_ref_samples[i-1][0]; //real
80010a8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80010ac: 1e5a subs r2, r3, #1
80010ae: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80010b2: 4999 ldr r1, [pc, #612] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010b4: f931 1022 ldrsh.w r1, [r1, r2, lsl #2]
80010b8: 4a97 ldr r2, [pc, #604] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010ba: f822 1023 strh.w r1, [r2, r3, lsl #2]
temperature_ref_samples[i][1] = temperature_ref_samples[i-1][1]; //imag
80010be: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80010c2: 3b01 subs r3, #1
80010c4: f897 2047 ldrb.w r2, [r7, #71] @ 0x47
80010c8: 4993 ldr r1, [pc, #588] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010ca: 009b lsls r3, r3, #2
80010cc: 440b add r3, r1
80010ce: f9b3 0002 ldrsh.w r0, [r3, #2]
80010d2: 4991 ldr r1, [pc, #580] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010d4: 0093 lsls r3, r2, #2
80010d6: 440b add r3, r1
80010d8: 4602 mov r2, r0
80010da: 805a strh r2, [r3, #2]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80010dc: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80010e0: 3b01 subs r3, #1
80010e2: f887 3047 strb.w r3, [r7, #71] @ 0x47
80010e6: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80010ea: 2b00 cmp r3, #0
80010ec: d1dc bne.n 80010a8 <AD5934_GetTemperature+0x54>
}
// Read real and imaginary data
temperature_ref_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
80010ee: 6b7b ldr r3, [r7, #52] @ 0x34
80010f0: b21a sxth r2, r3
80010f2: 4b89 ldr r3, [pc, #548] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010f4: 801a strh r2, [r3, #0]
//temperature_ref_samples[0][1] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
temperature_ref_samples[0][1] = (int16_t)((sample & 0xFFFF0000)>>16); //imag
80010f6: 6b7b ldr r3, [r7, #52] @ 0x34
80010f8: 0c1b lsrs r3, r3, #16
80010fa: b21a sxth r2, r3
80010fc: 4b86 ldr r3, [pc, #536] @ (8001318 <AD5934_GetTemperature+0x2c4>)
80010fe: 805a strh r2, [r3, #2]
// Sum values in the vectors
for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001100: 2300 movs r3, #0
8001102: f887 3047 strb.w r3, [r7, #71] @ 0x47
8001106: 2300 movs r3, #0
8001108: 60bb str r3, [r7, #8]
800110a: 2300 movs r3, #0
800110c: 60fb str r3, [r7, #12]
800110e: e016 b.n 800113e <AD5934_GetTemperature+0xea>
{
ref_sum[0] += (int32_t)temperature_ref_samples[i][0]; //real
8001110: 68bb ldr r3, [r7, #8]
8001112: f897 2047 ldrb.w r2, [r7, #71] @ 0x47
8001116: 4980 ldr r1, [pc, #512] @ (8001318 <AD5934_GetTemperature+0x2c4>)
8001118: f931 2022 ldrsh.w r2, [r1, r2, lsl #2]
800111c: 4413 add r3, r2
800111e: 60bb str r3, [r7, #8]
ref_sum[1] += (int32_t)temperature_ref_samples[i][1]; //imag
8001120: 68fa ldr r2, [r7, #12]
8001122: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8001126: 497c ldr r1, [pc, #496] @ (8001318 <AD5934_GetTemperature+0x2c4>)
8001128: 009b lsls r3, r3, #2
800112a: 440b add r3, r1
800112c: f9b3 3002 ldrsh.w r3, [r3, #2]
8001130: 4413 add r3, r2
8001132: 60fb str r3, [r7, #12]
for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001134: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8001138: 3301 adds r3, #1
800113a: f887 3047 strb.w r3, [r7, #71] @ 0x47
800113e: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8001142: 2b07 cmp r3, #7
8001144: d9e4 bls.n 8001110 <AD5934_GetTemperature+0xbc>
}
real_ref = ((float)ref_sum[0])/((float)AD5934_TEMP_AVERAGES);
8001146: 68bb ldr r3, [r7, #8]
8001148: 4618 mov r0, r3
800114a: f7ff fc57 bl 80009fc <__aeabi_i2f>
800114e: 4603 mov r3, r0
8001150: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001154: 4618 mov r0, r3
8001156: f7ff fd59 bl 8000c0c <__aeabi_fdiv>
800115a: 4603 mov r3, r0
800115c: 633b str r3, [r7, #48] @ 0x30
imag_ref = ((float)ref_sum[1])/((float)AD5934_TEMP_AVERAGES);
800115e: 68fb ldr r3, [r7, #12]
8001160: 4618 mov r0, r3
8001162: f7ff fc4b bl 80009fc <__aeabi_i2f>
8001166: 4603 mov r3, r0
8001168: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
800116c: 4618 mov r0, r3
800116e: f7ff fd4d bl 8000c0c <__aeabi_fdiv>
8001172: 4603 mov r3, r0
8001174: 62fb str r3, [r7, #44] @ 0x2c
// Calculate gain factor impedance
mag_ref = sqrtf((real_ref * real_ref) + (imag_ref * imag_ref));
8001176: 6b39 ldr r1, [r7, #48] @ 0x30
8001178: 6b38 ldr r0, [r7, #48] @ 0x30
800117a: f7ff fc93 bl 8000aa4 <__aeabi_fmul>
800117e: 4603 mov r3, r0
8001180: 461c mov r4, r3
8001182: 6af9 ldr r1, [r7, #44] @ 0x2c
8001184: 6af8 ldr r0, [r7, #44] @ 0x2c
8001186: f7ff fc8d bl 8000aa4 <__aeabi_fmul>
800118a: 4603 mov r3, r0
800118c: 4619 mov r1, r3
800118e: 4620 mov r0, r4
8001190: f7ff fb80 bl 8000894 <__addsf3>
8001194: 4603 mov r3, r0
8001196: 4618 mov r0, r3
8001198: f005 f886 bl 80062a8 <sqrtf>
800119c: 62b8 str r0, [r7, #40] @ 0x28
ADG715_Update(ch_dut);
800119e: f897 3046 ldrb.w r3, [r7, #70] @ 0x46
80011a2: 4618 mov r0, r3
80011a4: f000 faf0 bl 8001788 <ADG715_Update>
HAL_Delay(2);
80011a8: 2002 movs r0, #2
80011aa: f001 fd69 bl 8002c80 <HAL_Delay>
sample = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
80011ae: f7ff ff34 bl 800101a <AD5934_Sweep>
80011b2: 6378 str r0, [r7, #52] @ 0x34
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80011b4: 2307 movs r3, #7
80011b6: f887 3047 strb.w r3, [r7, #71] @ 0x47
80011ba: e01e b.n 80011fa <AD5934_GetTemperature+0x1a6>
{
temperature_dut_samples[i][0] = temperature_dut_samples[i-1][0]; //real
80011bc: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80011c0: 1e5a subs r2, r3, #1
80011c2: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80011c6: 4955 ldr r1, [pc, #340] @ (800131c <AD5934_GetTemperature+0x2c8>)
80011c8: f931 1022 ldrsh.w r1, [r1, r2, lsl #2]
80011cc: 4a53 ldr r2, [pc, #332] @ (800131c <AD5934_GetTemperature+0x2c8>)
80011ce: f822 1023 strh.w r1, [r2, r3, lsl #2]
temperature_dut_samples[i][1] = temperature_dut_samples[i-1][1]; //imag
80011d2: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80011d6: 3b01 subs r3, #1
80011d8: f897 2047 ldrb.w r2, [r7, #71] @ 0x47
80011dc: 494f ldr r1, [pc, #316] @ (800131c <AD5934_GetTemperature+0x2c8>)
80011de: 009b lsls r3, r3, #2
80011e0: 440b add r3, r1
80011e2: f9b3 0002 ldrsh.w r0, [r3, #2]
80011e6: 494d ldr r1, [pc, #308] @ (800131c <AD5934_GetTemperature+0x2c8>)
80011e8: 0093 lsls r3, r2, #2
80011ea: 440b add r3, r1
80011ec: 4602 mov r2, r0
80011ee: 805a strh r2, [r3, #2]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80011f0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80011f4: 3b01 subs r3, #1
80011f6: f887 3047 strb.w r3, [r7, #71] @ 0x47
80011fa: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80011fe: 2b00 cmp r3, #0
8001200: d1dc bne.n 80011bc <AD5934_GetTemperature+0x168>
}
// Read real and imaginary data
temperature_dut_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
8001202: 6b7b ldr r3, [r7, #52] @ 0x34
8001204: b21a sxth r2, r3
8001206: 4b45 ldr r3, [pc, #276] @ (800131c <AD5934_GetTemperature+0x2c8>)
8001208: 801a strh r2, [r3, #0]
//temperature_dut_samples[0][1] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
temperature_dut_samples[0][1] = (int16_t)((sample & 0xFFFF0000)>>16); //imag
800120a: 6b7b ldr r3, [r7, #52] @ 0x34
800120c: 0c1b lsrs r3, r3, #16
800120e: b21a sxth r2, r3
8001210: 4b42 ldr r3, [pc, #264] @ (800131c <AD5934_GetTemperature+0x2c8>)
8001212: 805a strh r2, [r3, #2]
for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001214: 2300 movs r3, #0
8001216: f887 3047 strb.w r3, [r7, #71] @ 0x47
800121a: 2300 movs r3, #0
800121c: 603b str r3, [r7, #0]
800121e: 2300 movs r3, #0
8001220: 607b str r3, [r7, #4]
8001222: e016 b.n 8001252 <AD5934_GetTemperature+0x1fe>
{
dut_sum[0] += (int32_t)temperature_dut_samples[i][0]; //real
8001224: 683b ldr r3, [r7, #0]
8001226: f897 2047 ldrb.w r2, [r7, #71] @ 0x47
800122a: 493c ldr r1, [pc, #240] @ (800131c <AD5934_GetTemperature+0x2c8>)
800122c: f931 2022 ldrsh.w r2, [r1, r2, lsl #2]
8001230: 4413 add r3, r2
8001232: 603b str r3, [r7, #0]
dut_sum[1] += (int32_t)temperature_dut_samples[i][1]; //imag
8001234: 687a ldr r2, [r7, #4]
8001236: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
800123a: 4938 ldr r1, [pc, #224] @ (800131c <AD5934_GetTemperature+0x2c8>)
800123c: 009b lsls r3, r3, #2
800123e: 440b add r3, r1
8001240: f9b3 3002 ldrsh.w r3, [r3, #2]
8001244: 4413 add r3, r2
8001246: 607b str r3, [r7, #4]
for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001248: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
800124c: 3301 adds r3, #1
800124e: f887 3047 strb.w r3, [r7, #71] @ 0x47
8001252: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8001256: 2b07 cmp r3, #7
8001258: d9e4 bls.n 8001224 <AD5934_GetTemperature+0x1d0>
}
real_dut = ((float)dut_sum[0])/((float)AD5934_TEMP_AVERAGES);
800125a: 683b ldr r3, [r7, #0]
800125c: 4618 mov r0, r3
800125e: f7ff fbcd bl 80009fc <__aeabi_i2f>
8001262: 4603 mov r3, r0
8001264: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001268: 4618 mov r0, r3
800126a: f7ff fccf bl 8000c0c <__aeabi_fdiv>
800126e: 4603 mov r3, r0
8001270: 627b str r3, [r7, #36] @ 0x24
imag_dut = ((float)dut_sum[1])/((float)AD5934_TEMP_AVERAGES);
8001272: 687b ldr r3, [r7, #4]
8001274: 4618 mov r0, r3
8001276: f7ff fbc1 bl 80009fc <__aeabi_i2f>
800127a: 4603 mov r3, r0
800127c: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001280: 4618 mov r0, r3
8001282: f7ff fcc3 bl 8000c0c <__aeabi_fdiv>
8001286: 4603 mov r3, r0
8001288: 623b str r3, [r7, #32]
// Calculate magnitude
mag_dut = sqrtf((real_dut * real_dut) + (imag_dut * imag_dut));
800128a: 6a79 ldr r1, [r7, #36] @ 0x24
800128c: 6a78 ldr r0, [r7, #36] @ 0x24
800128e: f7ff fc09 bl 8000aa4 <__aeabi_fmul>
8001292: 4603 mov r3, r0
8001294: 461c mov r4, r3
8001296: 6a39 ldr r1, [r7, #32]
8001298: 6a38 ldr r0, [r7, #32]
800129a: f7ff fc03 bl 8000aa4 <__aeabi_fmul>
800129e: 4603 mov r3, r0
80012a0: 4619 mov r1, r3
80012a2: 4620 mov r0, r4
80012a4: f7ff faf6 bl 8000894 <__addsf3>
80012a8: 4603 mov r3, r0
80012aa: 4618 mov r0, r3
80012ac: f004 fffc bl 80062a8 <sqrtf>
80012b0: 61f8 str r0, [r7, #28]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80012b2: 2307 movs r3, #7
80012b4: f887 3047 strb.w r3, [r7, #71] @ 0x47
80012b8: e00f b.n 80012da <AD5934_GetTemperature+0x286>
temperature_display[i] = temperature_display[i-1];
80012ba: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80012be: 1e5a subs r2, r3, #1
80012c0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80012c4: 4916 ldr r1, [pc, #88] @ (8001320 <AD5934_GetTemperature+0x2cc>)
80012c6: f851 2022 ldr.w r2, [r1, r2, lsl #2]
80012ca: 4915 ldr r1, [pc, #84] @ (8001320 <AD5934_GetTemperature+0x2cc>)
80012cc: f841 2023 str.w r2, [r1, r3, lsl #2]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80012d0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80012d4: 3b01 subs r3, #1
80012d6: f887 3047 strb.w r3, [r7, #71] @ 0x47
80012da: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80012de: 2b00 cmp r3, #0
80012e0: d1eb bne.n 80012ba <AD5934_GetTemperature+0x266>
ratio_mag = mag_ref / mag_dut;
80012e2: 69f9 ldr r1, [r7, #28]
80012e4: 6ab8 ldr r0, [r7, #40] @ 0x28
80012e6: f7ff fc91 bl 8000c0c <__aeabi_fdiv>
80012ea: 4603 mov r3, r0
80012ec: 61bb str r3, [r7, #24]
if(ch_ref==AD5934_CH_REF100R_LOW_GAIN) // only for PT100
80012ee: f897 3045 ldrb.w r3, [r7, #69] @ 0x45
80012f2: 2b09 cmp r3, #9
80012f4: d116 bne.n 8001324 <AD5934_GetTemperature+0x2d0>
impedance_dut = AD5934_Linear_Correction(gain_factor * ratio_mag);
80012f6: 69b9 ldr r1, [r7, #24]
80012f8: 6bb8 ldr r0, [r7, #56] @ 0x38
80012fa: f7ff fbd3 bl 8000aa4 <__aeabi_fmul>
80012fe: 4603 mov r3, r0
8001300: 4618 mov r0, r3
8001302: f000 f9f5 bl 80016f0 <AD5934_Linear_Correction>
8001306: 6438 str r0, [r7, #64] @ 0x40
8001308: e012 b.n 8001330 <AD5934_GetTemperature+0x2dc>
800130a: bf00 nop
800130c: 40010800 .word 0x40010800
8001310: 42c80000 .word 0x42c80000
8001314: 447a0000 .word 0x447a0000
8001318: 200000b4 .word 0x200000b4
800131c: 20000094 .word 0x20000094
8001320: 200000d4 .word 0x200000d4
else
impedance_dut = gain_factor * ratio_mag;
8001324: 69b9 ldr r1, [r7, #24]
8001326: 6bb8 ldr r0, [r7, #56] @ 0x38
8001328: f7ff fbbc bl 8000aa4 <__aeabi_fmul>
800132c: 4603 mov r3, r0
800132e: 643b str r3, [r7, #64] @ 0x40
// Calculate impedance ratio with the Reference Resistor
ratio = impedance_dut / gain_factor;
8001330: 6bb9 ldr r1, [r7, #56] @ 0x38
8001332: 6c38 ldr r0, [r7, #64] @ 0x40
8001334: f7ff fc6a bl 8000c0c <__aeabi_fdiv>
8001338: 4603 mov r3, r0
800133a: 617b str r3, [r7, #20]
// Calculate impedance discriminant with the ratio
discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio));
800133c: 6979 ldr r1, [r7, #20]
800133e: f04f 507e mov.w r0, #1065353216 @ 0x3f800000
8001342: f7ff faa5 bl 8000890 <__aeabi_fsub>
8001346: 4603 mov r3, r0
8001348: 493a ldr r1, [pc, #232] @ (8001434 <AD5934_GetTemperature+0x3e0>)
800134a: 4618 mov r0, r3
800134c: f7ff fbaa bl 8000aa4 <__aeabi_fmul>
8001350: 4603 mov r3, r0
8001352: 4939 ldr r1, [pc, #228] @ (8001438 <AD5934_GetTemperature+0x3e4>)
8001354: 4618 mov r0, r3
8001356: f7ff fa9d bl 8000894 <__addsf3>
800135a: 4603 mov r3, r0
800135c: 613b str r3, [r7, #16]
// Calculate new temperature with the discriminant
temperature_display[0] = (-AD5934_RTD_A + sqrtf(discriminant))/(2.0f * AD5934_RTD_B);
800135e: 6938 ldr r0, [r7, #16]
8001360: f004 ffa2 bl 80062a8 <sqrtf>
8001364: 4603 mov r3, r0
8001366: 4935 ldr r1, [pc, #212] @ (800143c <AD5934_GetTemperature+0x3e8>)
8001368: 4618 mov r0, r3
800136a: f7ff fa91 bl 8000890 <__aeabi_fsub>
800136e: 4603 mov r3, r0
8001370: 4933 ldr r1, [pc, #204] @ (8001440 <AD5934_GetTemperature+0x3ec>)
8001372: 4618 mov r0, r3
8001374: f7ff fc4a bl 8000c0c <__aeabi_fdiv>
8001378: 4603 mov r3, r0
800137a: 461a mov r2, r3
800137c: 4b31 ldr r3, [pc, #196] @ (8001444 <AD5934_GetTemperature+0x3f0>)
800137e: 601a str r2, [r3, #0]
// Sum of all temperatures
for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++)
8001380: 2300 movs r3, #0
8001382: f887 3047 strb.w r3, [r7, #71] @ 0x47
8001386: f04f 0300 mov.w r3, #0
800138a: 63fb str r3, [r7, #60] @ 0x3c
800138c: e00f b.n 80013ae <AD5934_GetTemperature+0x35a>
temperature_sum += temperature_display[i];
800138e: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8001392: 4a2c ldr r2, [pc, #176] @ (8001444 <AD5934_GetTemperature+0x3f0>)
8001394: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001398: 4619 mov r1, r3
800139a: 6bf8 ldr r0, [r7, #60] @ 0x3c
800139c: f7ff fa7a bl 8000894 <__addsf3>
80013a0: 4603 mov r3, r0
80013a2: 63fb str r3, [r7, #60] @ 0x3c
for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++)
80013a4: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80013a8: 3301 adds r3, #1
80013aa: f887 3047 strb.w r3, [r7, #71] @ 0x47
80013ae: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
80013b2: 2b07 cmp r3, #7
80013b4: d9eb bls.n 800138e <AD5934_GetTemperature+0x33a>
// Is the temperature stable?
if(temperature_display[0]>0.0f && (abs(temperature_display[0]-temperature_display[AD5934_TEMP_AVERAGES-1])/temperature_display[0])<0.1f)
80013b6: 4b23 ldr r3, [pc, #140] @ (8001444 <AD5934_GetTemperature+0x3f0>)
80013b8: 681b ldr r3, [r3, #0]
80013ba: f04f 0100 mov.w r1, #0
80013be: 4618 mov r0, r3
80013c0: f7ff fd2c bl 8000e1c <__aeabi_fcmpgt>
80013c4: 4603 mov r3, r0
80013c6: 2b00 cmp r3, #0
80013c8: d02d beq.n 8001426 <AD5934_GetTemperature+0x3d2>
80013ca: 4b1e ldr r3, [pc, #120] @ (8001444 <AD5934_GetTemperature+0x3f0>)
80013cc: 681b ldr r3, [r3, #0]
80013ce: 4a1d ldr r2, [pc, #116] @ (8001444 <AD5934_GetTemperature+0x3f0>)
80013d0: 69d2 ldr r2, [r2, #28]
80013d2: 4611 mov r1, r2
80013d4: 4618 mov r0, r3
80013d6: f7ff fa5b bl 8000890 <__aeabi_fsub>
80013da: 4603 mov r3, r0
80013dc: 4618 mov r0, r3
80013de: f7ff fd3d bl 8000e5c <__aeabi_f2iz>
80013e2: 4603 mov r3, r0
80013e4: 2b00 cmp r3, #0
80013e6: bfb8 it lt
80013e8: 425b neglt r3, r3
80013ea: 4618 mov r0, r3
80013ec: f7ff fb06 bl 80009fc <__aeabi_i2f>
80013f0: 4602 mov r2, r0
80013f2: 4b14 ldr r3, [pc, #80] @ (8001444 <AD5934_GetTemperature+0x3f0>)
80013f4: 681b ldr r3, [r3, #0]
80013f6: 4619 mov r1, r3
80013f8: 4610 mov r0, r2
80013fa: f7ff fc07 bl 8000c0c <__aeabi_fdiv>
80013fe: 4603 mov r3, r0
8001400: 4911 ldr r1, [pc, #68] @ (8001448 <AD5934_GetTemperature+0x3f4>)
8001402: 4618 mov r0, r3
8001404: f7ff fcec bl 8000de0 <__aeabi_fcmplt>
8001408: 4603 mov r3, r0
800140a: 2b00 cmp r3, #0
800140c: d00b beq.n 8001426 <AD5934_GetTemperature+0x3d2>
return(AD5934_Round_Float_Precision(temperature_sum/((float)AD5934_TEMP_AVERAGES),1)); // Sum / number of averages
800140e: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001412: 6bf8 ldr r0, [r7, #60] @ 0x3c
8001414: f7ff fbfa bl 8000c0c <__aeabi_fdiv>
8001418: 4603 mov r3, r0
800141a: 2101 movs r1, #1
800141c: 4618 mov r0, r3
800141e: f000 f939 bl 8001694 <AD5934_Round_Float_Precision>
8001422: 4603 mov r3, r0
8001424: e001 b.n 800142a <AD5934_GetTemperature+0x3d6>
else
return 0.0f; //instable values return always 0
8001426: f04f 0300 mov.w r3, #0
}
800142a: 4618 mov r0, r3
800142c: 374c adds r7, #76 @ 0x4c
800142e: 46bd mov sp, r7
8001430: bd90 pop {r4, r7, pc}
8001432: bf00 nop
8001434: 361b057f .word 0x361b057f
8001438: 37802266 .word 0x37802266
800143c: 3b801132 .word 0x3b801132
8001440: b59b057f .word 0xb59b057f
8001444: 200000d4 .word 0x200000d4
8001448: 3dcccccd .word 0x3dcccccd
0800144c <AD5934_GetImpedance>:
*
* @param temperature_dut The current temperature of the DUT (Device Under Test).
* @return float Calculated conductivity in uS/cm.
*/
float AD5934_GetImpedance(float temperature_dut)
{
800144c: b590 push {r4, r7, lr}
800144e: b08b sub sp, #44 @ 0x2c
8001450: af00 add r7, sp, #0
8001452: 6078 str r0, [r7, #4]
uint8_t i, ec_gain;
uint32_t sample_dut;
int32_t dut_sum[2] = {0, 0};
8001454: 2300 movs r3, #0
8001456: 60bb str r3, [r7, #8]
8001458: 2300 movs r3, #0
800145a: 60fb str r3, [r7, #12]
float real_avg, imag_avg, mag_dut, slope, target_cond;
/* 1. Hardware Setup: Gain Selection (PA6) */
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET)
800145c: 2140 movs r1, #64 @ 0x40
800145e: 4874 ldr r0, [pc, #464] @ (8001630 <AD5934_GetImpedance+0x1e4>)
8001460: f002 fb88 bl 8003b74 <HAL_GPIO_ReadPin>
8001464: 4603 mov r3, r0
8001466: 2b01 cmp r3, #1
8001468: d103 bne.n 8001472 <AD5934_GetImpedance+0x26>
ec_gain = AD5934_CH_EC_HIGH_GAIN;
800146a: 2384 movs r3, #132 @ 0x84
800146c: f887 3026 strb.w r3, [r7, #38] @ 0x26
8001470: e002 b.n 8001478 <AD5934_GetImpedance+0x2c>
else
ec_gain = AD5934_CH_EC_MID_GAIN;
8001472: 2382 movs r3, #130 @ 0x82
8001474: f887 3026 strb.w r3, [r7, #38] @ 0x26
if((ec_gain != flash_data.EC10mS_EC5mS_switch) && (main_state != STATE_SETUP_CALIBRATION))
8001478: 4b6e ldr r3, [pc, #440] @ (8001634 <AD5934_GetImpedance+0x1e8>)
800147a: 7e5b ldrb r3, [r3, #25]
800147c: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
8001480: 429a cmp r2, r3
8001482: d005 beq.n 8001490 <AD5934_GetImpedance+0x44>
8001484: 4b6c ldr r3, [pc, #432] @ (8001638 <AD5934_GetImpedance+0x1ec>)
8001486: 781b ldrb r3, [r3, #0]
8001488: 2b01 cmp r3, #1
800148a: d001 beq.n 8001490 <AD5934_GetImpedance+0x44>
return -1.0f; // Fatal error because the gain used in calibration is different
800148c: 4b6b ldr r3, [pc, #428] @ (800163c <AD5934_GetImpedance+0x1f0>)
800148e: e0cb b.n 8001628 <AD5934_GetImpedance+0x1dc>
ADG715_Update(ec_gain);
8001490: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
8001494: 4618 mov r0, r3
8001496: f000 f977 bl 8001788 <ADG715_Update>
HAL_Delay(2);
800149a: 2002 movs r0, #2
800149c: f001 fbf0 bl 8002c80 <HAL_Delay>
/* 2. Data Acquisition */
sample_dut = AD5934_Sweep();
80014a0: f7ff fdbb bl 800101a <AD5934_Sweep>
80014a4: 6238 str r0, [r7, #32]
// Shift buffer for moving average
for (i = (AD5934_EC_AVERAGES - 1); i > 0; i--)
80014a6: 2307 movs r3, #7
80014a8: f887 3027 strb.w r3, [r7, #39] @ 0x27
80014ac: e01e b.n 80014ec <AD5934_GetImpedance+0xa0>
{
ec_dut_samples[i][0] = ec_dut_samples[i-1][0];
80014ae: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80014b2: 1e5a subs r2, r3, #1
80014b4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80014b8: 4961 ldr r1, [pc, #388] @ (8001640 <AD5934_GetImpedance+0x1f4>)
80014ba: f931 1022 ldrsh.w r1, [r1, r2, lsl #2]
80014be: 4a60 ldr r2, [pc, #384] @ (8001640 <AD5934_GetImpedance+0x1f4>)
80014c0: f822 1023 strh.w r1, [r2, r3, lsl #2]
ec_dut_samples[i][1] = ec_dut_samples[i-1][1];
80014c4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80014c8: 3b01 subs r3, #1
80014ca: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
80014ce: 495c ldr r1, [pc, #368] @ (8001640 <AD5934_GetImpedance+0x1f4>)
80014d0: 009b lsls r3, r3, #2
80014d2: 440b add r3, r1
80014d4: f9b3 0002 ldrsh.w r0, [r3, #2]
80014d8: 4959 ldr r1, [pc, #356] @ (8001640 <AD5934_GetImpedance+0x1f4>)
80014da: 0093 lsls r3, r2, #2
80014dc: 440b add r3, r1
80014de: 4602 mov r2, r0
80014e0: 805a strh r2, [r3, #2]
for (i = (AD5934_EC_AVERAGES - 1); i > 0; i--)
80014e2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80014e6: 3b01 subs r3, #1
80014e8: f887 3027 strb.w r3, [r7, #39] @ 0x27
80014ec: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80014f0: 2b00 cmp r3, #0
80014f2: d1dc bne.n 80014ae <AD5934_GetImpedance+0x62>
}
// Deconstruct 32-bit sample into Real and Imaginary components
ec_dut_samples[0][0] = (float)(int16_t)(sample_dut & 0xFFFF);
80014f4: 6a3b ldr r3, [r7, #32]
80014f6: b21b sxth r3, r3
80014f8: 4618 mov r0, r3
80014fa: f7ff fa7f bl 80009fc <__aeabi_i2f>
80014fe: 4603 mov r3, r0
8001500: 4618 mov r0, r3
8001502: f7ff fcab bl 8000e5c <__aeabi_f2iz>
8001506: 4603 mov r3, r0
8001508: b21a sxth r2, r3
800150a: 4b4d ldr r3, [pc, #308] @ (8001640 <AD5934_GetImpedance+0x1f4>)
800150c: 801a strh r2, [r3, #0]
ec_dut_samples[0][1] = (float)(int16_t)((sample_dut >> 16) & 0xFFFF);
800150e: 6a3b ldr r3, [r7, #32]
8001510: 0c1b lsrs r3, r3, #16
8001512: b21b sxth r3, r3
8001514: 4618 mov r0, r3
8001516: f7ff fa71 bl 80009fc <__aeabi_i2f>
800151a: 4603 mov r3, r0
800151c: 4618 mov r0, r3
800151e: f7ff fc9d bl 8000e5c <__aeabi_f2iz>
8001522: 4603 mov r3, r0
8001524: b21a sxth r2, r3
8001526: 4b46 ldr r3, [pc, #280] @ (8001640 <AD5934_GetImpedance+0x1f4>)
8001528: 805a strh r2, [r3, #2]
/* 3. Compute Averages */
for (i = 0; i < AD5934_EC_AVERAGES; i++)
800152a: 2300 movs r3, #0
800152c: f887 3027 strb.w r3, [r7, #39] @ 0x27
8001530: e016 b.n 8001560 <AD5934_GetImpedance+0x114>
{
dut_sum[0] += (int32_t)ec_dut_samples[i][0];
8001532: 68bb ldr r3, [r7, #8]
8001534: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
8001538: 4941 ldr r1, [pc, #260] @ (8001640 <AD5934_GetImpedance+0x1f4>)
800153a: f931 2022 ldrsh.w r2, [r1, r2, lsl #2]
800153e: 4413 add r3, r2
8001540: 60bb str r3, [r7, #8]
dut_sum[1] += (int32_t)ec_dut_samples[i][1];
8001542: 68fa ldr r2, [r7, #12]
8001544: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001548: 493d ldr r1, [pc, #244] @ (8001640 <AD5934_GetImpedance+0x1f4>)
800154a: 009b lsls r3, r3, #2
800154c: 440b add r3, r1
800154e: f9b3 3002 ldrsh.w r3, [r3, #2]
8001552: 4413 add r3, r2
8001554: 60fb str r3, [r7, #12]
for (i = 0; i < AD5934_EC_AVERAGES; i++)
8001556: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
800155a: 3301 adds r3, #1
800155c: f887 3027 strb.w r3, [r7, #39] @ 0x27
8001560: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001564: 2b07 cmp r3, #7
8001566: d9e4 bls.n 8001532 <AD5934_GetImpedance+0xe6>
}
real_avg = (float)dut_sum[0] / (float)AD5934_EC_AVERAGES;
8001568: 68bb ldr r3, [r7, #8]
800156a: 4618 mov r0, r3
800156c: f7ff fa46 bl 80009fc <__aeabi_i2f>
8001570: 4603 mov r3, r0
8001572: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001576: 4618 mov r0, r3
8001578: f7ff fb48 bl 8000c0c <__aeabi_fdiv>
800157c: 4603 mov r3, r0
800157e: 61fb str r3, [r7, #28]
imag_avg = (float)dut_sum[1] / (float)AD5934_EC_AVERAGES;
8001580: 68fb ldr r3, [r7, #12]
8001582: 4618 mov r0, r3
8001584: f7ff fa3a bl 80009fc <__aeabi_i2f>
8001588: 4603 mov r3, r0
800158a: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
800158e: 4618 mov r0, r3
8001590: f7ff fb3c bl 8000c0c <__aeabi_fdiv>
8001594: 4603 mov r3, r0
8001596: 61bb str r3, [r7, #24]
/* 4. Magnitude Calculation */
mag_dut = sqrtf((real_avg * real_avg) + (imag_avg * imag_avg));
8001598: 69f9 ldr r1, [r7, #28]
800159a: 69f8 ldr r0, [r7, #28]
800159c: f7ff fa82 bl 8000aa4 <__aeabi_fmul>
80015a0: 4603 mov r3, r0
80015a2: 461c mov r4, r3
80015a4: 69b9 ldr r1, [r7, #24]
80015a6: 69b8 ldr r0, [r7, #24]
80015a8: f7ff fa7c bl 8000aa4 <__aeabi_fmul>
80015ac: 4603 mov r3, r0
80015ae: 4619 mov r1, r3
80015b0: 4620 mov r0, r4
80015b2: f7ff f96f bl 8000894 <__addsf3>
80015b6: 4603 mov r3, r0
80015b8: 4618 mov r0, r3
80015ba: f004 fe75 bl 80062a8 <sqrtf>
80015be: 6178 str r0, [r7, #20]
/* 5. Calibration Logic Implementation */
// Mode: CALIBRATION SETUP (User is defining the reference magnitude)
if(main_state == STATE_SETUP_CALIBRATION)
80015c0: 4b1d ldr r3, [pc, #116] @ (8001638 <AD5934_GetImpedance+0x1ec>)
80015c2: 781b ldrb r3, [r3, #0]
80015c4: 2b01 cmp r3, #1
80015c6: d101 bne.n 80015cc <AD5934_GetImpedance+0x180>
{
return mag_dut;
80015c8: 697b ldr r3, [r7, #20]
80015ca: e02d b.n 8001628 <AD5934_GetImpedance+0x1dc>
}
// Mode: MEASUREMENT (Applying temperature compensation)
else if(flash_data.ec0_mag != flash_data.ec1413_mag)
80015cc: 4b19 ldr r3, [pc, #100] @ (8001634 <AD5934_GetImpedance+0x1e8>)
80015ce: 691b ldr r3, [r3, #16]
80015d0: 4a18 ldr r2, [pc, #96] @ (8001634 <AD5934_GetImpedance+0x1e8>)
80015d2: 68d2 ldr r2, [r2, #12]
80015d4: 4611 mov r1, r2
80015d6: 4618 mov r0, r3
80015d8: f7ff fbf8 bl 8000dcc <__aeabi_fcmpeq>
80015dc: 4603 mov r3, r0
80015de: 2b00 cmp r3, #0
80015e0: d120 bne.n 8001624 <AD5934_GetImpedance+0x1d8>
{
slope = (AD5934_GAIN_FACTOR_1413US/(flash_data.ec1413_mag-flash_data.ec0_mag));
80015e2: 4b14 ldr r3, [pc, #80] @ (8001634 <AD5934_GetImpedance+0x1e8>)
80015e4: 68db ldr r3, [r3, #12]
80015e6: 4a13 ldr r2, [pc, #76] @ (8001634 <AD5934_GetImpedance+0x1e8>)
80015e8: 6912 ldr r2, [r2, #16]
80015ea: 4611 mov r1, r2
80015ec: 4618 mov r0, r3
80015ee: f7ff f94f bl 8000890 <__aeabi_fsub>
80015f2: 4603 mov r3, r0
80015f4: 4619 mov r1, r3
80015f6: 4813 ldr r0, [pc, #76] @ (8001644 <AD5934_GetImpedance+0x1f8>)
80015f8: f7ff fb08 bl 8000c0c <__aeabi_fdiv>
80015fc: 4603 mov r3, r0
80015fe: 613b str r3, [r7, #16]
return(AD5934_GAIN_FACTOR_1413US + (mag_dut - flash_data.ec1413_mag) * slope);
8001600: 4b0c ldr r3, [pc, #48] @ (8001634 <AD5934_GetImpedance+0x1e8>)
8001602: 68db ldr r3, [r3, #12]
8001604: 4619 mov r1, r3
8001606: 6978 ldr r0, [r7, #20]
8001608: f7ff f942 bl 8000890 <__aeabi_fsub>
800160c: 4603 mov r3, r0
800160e: 6939 ldr r1, [r7, #16]
8001610: 4618 mov r0, r3
8001612: f7ff fa47 bl 8000aa4 <__aeabi_fmul>
8001616: 4603 mov r3, r0
8001618: 490a ldr r1, [pc, #40] @ (8001644 <AD5934_GetImpedance+0x1f8>)
800161a: 4618 mov r0, r3
800161c: f7ff f93a bl 8000894 <__addsf3>
8001620: 4603 mov r3, r0
8001622: e001 b.n 8001628 <AD5934_GetImpedance+0x1dc>
}
else
return 0.0f; // Calibration error fallback
8001624: f04f 0300 mov.w r3, #0
}
8001628: 4618 mov r0, r3
800162a: 372c adds r7, #44 @ 0x2c
800162c: 46bd mov sp, r7
800162e: bd90 pop {r4, r7, pc}
8001630: 40010800 .word 0x40010800
8001634: 200001ac .word 0x200001ac
8001638: 20000654 .word 0x20000654
800163c: bf800000 .word 0xbf800000
8001640: 200000f4 .word 0x200000f4
8001644: 44b0a000 .word 0x44b0a000
08001648 <AD5934_Wait_For_Data_Valid>:
/**
* @brief Monitora o status com TIMEOUT para evitar travamento do sistema.
*/
void AD5934_Wait_For_Data_Valid(void)
{
8001648: b580 push {r7, lr}
800164a: b084 sub sp, #16
800164c: af00 add r7, sp, #0
uint32_t timeout_counter = 0;
800164e: 2300 movs r3, #0
8001650: 60fb str r3, [r7, #12]
const uint32_t MAX_TIMEOUT = 10000; // Limite de tentativas
8001652: f242 7310 movw r3, #10000 @ 0x2710
8001656: 60bb str r3, [r7, #8]
uint8_t status;
while (1)
{
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
8001658: 2101 movs r1, #1
800165a: 208f movs r0, #143 @ 0x8f
800165c: f7ff fc56 bl 8000f0c <AD5934_GetRegisterValue>
8001660: 4603 mov r3, r0
8001662: 71fb strb r3, [r7, #7]
if ((status & AD5934_STATUS_DATA_VALID) != 0)
8001664: 79fb ldrb r3, [r7, #7]
8001666: f003 0302 and.w r3, r3, #2
800166a: 2b00 cmp r3, #0
800166c: d10a bne.n 8001684 <AD5934_Wait_For_Data_Valid+0x3c>
{
break; // Sucesso!
}
timeout_counter++;
800166e: 68fb ldr r3, [r7, #12]
8001670: 3301 adds r3, #1
8001672: 60fb str r3, [r7, #12]
if (timeout_counter >= MAX_TIMEOUT)
8001674: 68fa ldr r2, [r7, #12]
8001676: 68bb ldr r3, [r7, #8]
8001678: 429a cmp r2, r3
800167a: d205 bcs.n 8001688 <AD5934_Wait_For_Data_Valid+0x40>
{
// TRATAMENTO DE ERRO: O sistema não travou, mas o chip falhou.
break;
}
HAL_Delay(1); // Pequeno delay para não sobrecarregar o barramento I2C
800167c: 2001 movs r0, #1
800167e: f001 faff bl 8002c80 <HAL_Delay>
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
8001682: e7e9 b.n 8001658 <AD5934_Wait_For_Data_Valid+0x10>
break; // Sucesso!
8001684: bf00 nop
8001686: e000 b.n 800168a <AD5934_Wait_For_Data_Valid+0x42>
break;
8001688: bf00 nop
}
}
800168a: bf00 nop
800168c: 3710 adds r7, #16
800168e: 46bd mov sp, r7
8001690: bd80 pop {r7, pc}
...
08001694 <AD5934_Round_Float_Precision>:
* @param valor O valor float original.
* @param casas_decimais Quantidade de casas que devem permanecer após a vírgula.
* @return float O valor com as casas decimais excedentes removidas.
*/
float AD5934_Round_Float_Precision(float value, uint8_t number_of_decimals)
{
8001694: b580 push {r7, lr}
8001696: b084 sub sp, #16
8001698: af00 add r7, sp, #0
800169a: 6078 str r0, [r7, #4]
800169c: 460b mov r3, r1
800169e: 70fb strb r3, [r7, #3]
float multiply = 1.0f;
80016a0: f04f 537e mov.w r3, #1065353216 @ 0x3f800000
80016a4: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
80016a6: 2300 movs r3, #0
80016a8: 72fb strb r3, [r7, #11]
80016aa: e008 b.n 80016be <AD5934_Round_Float_Precision+0x2a>
multiply *= 10.0f;
80016ac: 490f ldr r1, [pc, #60] @ (80016ec <AD5934_Round_Float_Precision+0x58>)
80016ae: 68f8 ldr r0, [r7, #12]
80016b0: f7ff f9f8 bl 8000aa4 <__aeabi_fmul>
80016b4: 4603 mov r3, r0
80016b6: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
80016b8: 7afb ldrb r3, [r7, #11]
80016ba: 3301 adds r3, #1
80016bc: 72fb strb r3, [r7, #11]
80016be: 7afa ldrb r2, [r7, #11]
80016c0: 78fb ldrb r3, [r7, #3]
80016c2: 429a cmp r2, r3
80016c4: d3f2 bcc.n 80016ac <AD5934_Round_Float_Precision+0x18>
return roundf(value * multiply) / multiply;
80016c6: 68f9 ldr r1, [r7, #12]
80016c8: 6878 ldr r0, [r7, #4]
80016ca: f7ff f9eb bl 8000aa4 <__aeabi_fmul>
80016ce: 4603 mov r3, r0
80016d0: 4618 mov r0, r3
80016d2: f004 fe79 bl 80063c8 <roundf>
80016d6: 4603 mov r3, r0
80016d8: 68f9 ldr r1, [r7, #12]
80016da: 4618 mov r0, r3
80016dc: f7ff fa96 bl 8000c0c <__aeabi_fdiv>
80016e0: 4603 mov r3, r0
}
80016e2: 4618 mov r0, r3
80016e4: 3710 adds r7, #16
80016e6: 46bd mov sp, r7
80016e8: bd80 pop {r7, pc}
80016ea: bf00 nop
80016ec: 41200000 .word 0x41200000
080016f0 <AD5934_Linear_Correction>:
*
* @param input_val The raw float value from sensor/ADC.
* @return float The transformed value following the requested trend.
*/
float AD5934_Linear_Correction(float raw_value)
{
80016f0: b580 push {r7, lr}
80016f2: b084 sub sp, #16
80016f4: af00 add r7, sp, #0
80016f6: 6078 str r0, [r7, #4]
/* Pre-calculated constants from regression analysis */
const float slope = 1.02281f;
80016f8: 4b08 ldr r3, [pc, #32] @ (800171c <AD5934_Linear_Correction+0x2c>)
80016fa: 60fb str r3, [r7, #12]
const float offset = (-2.1409f);
80016fc: 4b08 ldr r3, [pc, #32] @ (8001720 <AD5934_Linear_Correction+0x30>)
80016fe: 60bb str r3, [r7, #8]
/* Single FPU instruction (if FPU available) or optimized software float mul/add */
return (raw_value * slope) + offset;
8001700: 68f9 ldr r1, [r7, #12]
8001702: 6878 ldr r0, [r7, #4]
8001704: f7ff f9ce bl 8000aa4 <__aeabi_fmul>
8001708: 4603 mov r3, r0
800170a: 68b9 ldr r1, [r7, #8]
800170c: 4618 mov r0, r3
800170e: f7ff f8c1 bl 8000894 <__addsf3>
8001712: 4603 mov r3, r0
}
8001714: 4618 mov r0, r3
8001716: 3710 adds r7, #16
8001718: 46bd mov sp, r7
800171a: bd80 pop {r7, pc}
800171c: 3f82eb70 .word 0x3f82eb70
8001720: c0090481 .word 0xc0090481
08001724 <ADG715_SetRegisterValue>:
*
* @return None.
*******************************************************************************/
void ADG715_SetRegisterValue(char value)
{
8001724: b580 push {r7, lr}
8001726: b086 sub sp, #24
8001728: af02 add r7, sp, #8
800172a: 4603 mov r3, r0
800172c: 71fb strb r3, [r7, #7]
uint8_t writeData[1] = {value};
800172e: 79fb ldrb r3, [r7, #7]
8001730: 733b strb r3, [r7, #12]
HAL_StatusTypeDef status;
status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
8001732: f107 020c add.w r2, r7, #12
8001736: 2301 movs r3, #1
8001738: 9300 str r3, [sp, #0]
800173a: 2301 movs r3, #1
800173c: 2190 movs r1, #144 @ 0x90
800173e: 4804 ldr r0, [pc, #16] @ (8001750 <ADG715_SetRegisterValue+0x2c>)
8001740: f002 fba4 bl 8003e8c <HAL_I2C_Master_Transmit>
8001744: 4603 mov r3, r0
8001746: 73fb strb r3, [r7, #15]
return;
8001748: bf00 nop
}
800174a: 3710 adds r7, #16
800174c: 46bd mov sp, r7
800174e: bd80 pop {r7, pc}
8001750: 20000600 .word 0x20000600
08001754 <ADG715_SetChannels>:
void ADG715_SetChannels(uint8_t ch1, uint8_t ch2)
{
8001754: b580 push {r7, lr}
8001756: b082 sub sp, #8
8001758: af00 add r7, sp, #0
800175a: 4603 mov r3, r0
800175c: 460a mov r2, r1
800175e: 71fb strb r3, [r7, #7]
8001760: 4613 mov r3, r2
8001762: 71bb strb r3, [r7, #6]
ADG715_SetRegisterValue(ch1+ch2);
8001764: 79fa ldrb r2, [r7, #7]
8001766: 79bb ldrb r3, [r7, #6]
8001768: 4413 add r3, r2
800176a: b2db uxtb r3, r3
800176c: 4618 mov r0, r3
800176e: f7ff ffd9 bl 8001724 <ADG715_SetRegisterValue>
}
8001772: bf00 nop
8001774: 3708 adds r7, #8
8001776: 46bd mov sp, r7
8001778: bd80 pop {r7, pc}
0800177a <ADG715_ResetChannels>:
void ADG715_ResetChannels(void)
{
800177a: b580 push {r7, lr}
800177c: af00 add r7, sp, #0
ADG715_SetRegisterValue(0);
800177e: 2000 movs r0, #0
8001780: f7ff ffd0 bl 8001724 <ADG715_SetRegisterValue>
}
8001784: bf00 nop
8001786: bd80 pop {r7, pc}
08001788 <ADG715_Update>:
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC
*
* @return none.
******************************************************************************/
void ADG715_Update(uint8_t channel)
{
8001788: b580 push {r7, lr}
800178a: b082 sub sp, #8
800178c: af00 add r7, sp, #0
800178e: 4603 mov r3, r0
8001790: 71fb strb r3, [r7, #7]
HAL_StatusTypeDef status;
// Disconnect all Analog Switches
ADG715_ResetChannels();
8001792: f7ff fff2 bl 800177a <ADG715_ResetChannels>
// Set the pair of connections
if(channel == AD5934_CH_REF100R_LOW_GAIN)
8001796: 79fb ldrb r3, [r7, #7]
8001798: 2b09 cmp r3, #9
800179a: d104 bne.n 80017a6 <ADG715_Update+0x1e>
{
ADG715_SetChannels(ADG715_SW1, ADG715_SW4); // Rf = 150R, Ch = Ref_100R
800179c: 2108 movs r1, #8
800179e: 2001 movs r0, #1
80017a0: f7ff ffd8 bl 8001754 <ADG715_SetChannels>
else if(channel == AD5934_CH_EC_HIGH_GAIN)
{
ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC
}
}
80017a4: e06e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF100R_MID_GAIN)
80017a6: 79fb ldrb r3, [r7, #7]
80017a8: 2b0a cmp r3, #10
80017aa: d104 bne.n 80017b6 <ADG715_Update+0x2e>
ADG715_SetChannels(ADG715_SW2, ADG715_SW4); // Rf = 1k5, Ch = Ref_100R
80017ac: 2108 movs r1, #8
80017ae: 2002 movs r0, #2
80017b0: f7ff ffd0 bl 8001754 <ADG715_SetChannels>
}
80017b4: e066 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF100R_HIGH_GAIN)
80017b6: 79fb ldrb r3, [r7, #7]
80017b8: 2b0c cmp r3, #12
80017ba: d104 bne.n 80017c6 <ADG715_Update+0x3e>
ADG715_SetChannels(ADG715_SW3, ADG715_SW4); // Rf = 6k2, Ch = Ref_100R
80017bc: 2108 movs r1, #8
80017be: 2004 movs r0, #4
80017c0: f7ff ffc8 bl 8001754 <ADG715_SetChannels>
}
80017c4: e05e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF1K_LOW_GAIN)
80017c6: 79fb ldrb r3, [r7, #7]
80017c8: 2b11 cmp r3, #17
80017ca: d104 bne.n 80017d6 <ADG715_Update+0x4e>
ADG715_SetChannels(ADG715_SW1, ADG715_SW5); // Rf = 150R, Ch = Ref_1k
80017cc: 2110 movs r1, #16
80017ce: 2001 movs r0, #1
80017d0: f7ff ffc0 bl 8001754 <ADG715_SetChannels>
}
80017d4: e056 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF1K_MID_GAIN)
80017d6: 79fb ldrb r3, [r7, #7]
80017d8: 2b12 cmp r3, #18
80017da: d104 bne.n 80017e6 <ADG715_Update+0x5e>
ADG715_SetChannels(ADG715_SW2, ADG715_SW5); // Rf = 1k5, Ch = Ref_1k
80017dc: 2110 movs r1, #16
80017de: 2002 movs r0, #2
80017e0: f7ff ffb8 bl 8001754 <ADG715_SetChannels>
}
80017e4: e04e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF1K_HIGH_GAIN)
80017e6: 79fb ldrb r3, [r7, #7]
80017e8: 2b14 cmp r3, #20
80017ea: d104 bne.n 80017f6 <ADG715_Update+0x6e>
ADG715_SetChannels(ADG715_SW3, ADG715_SW5); // Rf = 6k2, Ch = Ref_1k
80017ec: 2110 movs r1, #16
80017ee: 2004 movs r0, #4
80017f0: f7ff ffb0 bl 8001754 <ADG715_SetChannels>
}
80017f4: e046 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF10K_LOW_GAIN)
80017f6: 79fb ldrb r3, [r7, #7]
80017f8: 2b21 cmp r3, #33 @ 0x21
80017fa: d104 bne.n 8001806 <ADG715_Update+0x7e>
ADG715_SetChannels(ADG715_SW1, ADG715_SW6); // Rf = 150R, Ch = Ref_10k
80017fc: 2120 movs r1, #32
80017fe: 2001 movs r0, #1
8001800: f7ff ffa8 bl 8001754 <ADG715_SetChannels>
}
8001804: e03e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF10K_MID_GAIN)
8001806: 79fb ldrb r3, [r7, #7]
8001808: 2b22 cmp r3, #34 @ 0x22
800180a: d104 bne.n 8001816 <ADG715_Update+0x8e>
ADG715_SetChannels(ADG715_SW2, ADG715_SW6); // Rf = 1k5, Ch = Ref_10k
800180c: 2120 movs r1, #32
800180e: 2002 movs r0, #2
8001810: f7ff ffa0 bl 8001754 <ADG715_SetChannels>
}
8001814: e036 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_REF10K_HIGH_GAIN)
8001816: 79fb ldrb r3, [r7, #7]
8001818: 2b24 cmp r3, #36 @ 0x24
800181a: d104 bne.n 8001826 <ADG715_Update+0x9e>
ADG715_SetChannels(ADG715_SW3, ADG715_SW6); // Rf = 6k2, Ch = Ref_10k
800181c: 2120 movs r1, #32
800181e: 2004 movs r0, #4
8001820: f7ff ff98 bl 8001754 <ADG715_SetChannels>
}
8001824: e02e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_RTD_LOW_GAIN)
8001826: 79fb ldrb r3, [r7, #7]
8001828: 2b41 cmp r3, #65 @ 0x41
800182a: d104 bne.n 8001836 <ADG715_Update+0xae>
ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = RTD
800182c: 2140 movs r1, #64 @ 0x40
800182e: 2001 movs r0, #1
8001830: f7ff ff90 bl 8001754 <ADG715_SetChannels>
}
8001834: e026 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_RTD_MID_GAIN)
8001836: 79fb ldrb r3, [r7, #7]
8001838: 2b42 cmp r3, #66 @ 0x42
800183a: d104 bne.n 8001846 <ADG715_Update+0xbe>
ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = RTD
800183c: 2140 movs r1, #64 @ 0x40
800183e: 2002 movs r0, #2
8001840: f7ff ff88 bl 8001754 <ADG715_SetChannels>
}
8001844: e01e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_RTD_HIGH_GAIN)
8001846: 79fb ldrb r3, [r7, #7]
8001848: 2b44 cmp r3, #68 @ 0x44
800184a: d104 bne.n 8001856 <ADG715_Update+0xce>
ADG715_SetChannels(ADG715_SW3, ADG715_SW7); // Rf = 6k2, Ch = RTD
800184c: 2140 movs r1, #64 @ 0x40
800184e: 2004 movs r0, #4
8001850: f7ff ff80 bl 8001754 <ADG715_SetChannels>
}
8001854: e016 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_EC_LOW_GAIN)
8001856: 79fb ldrb r3, [r7, #7]
8001858: 2b81 cmp r3, #129 @ 0x81
800185a: d104 bne.n 8001866 <ADG715_Update+0xde>
ADG715_SetChannels(ADG715_SW1, ADG715_SW8); // Rf = 150R, Ch = EC
800185c: 2180 movs r1, #128 @ 0x80
800185e: 2001 movs r0, #1
8001860: f7ff ff78 bl 8001754 <ADG715_SetChannels>
}
8001864: e00e b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_EC_MID_GAIN)
8001866: 79fb ldrb r3, [r7, #7]
8001868: 2b82 cmp r3, #130 @ 0x82
800186a: d104 bne.n 8001876 <ADG715_Update+0xee>
ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC
800186c: 2180 movs r1, #128 @ 0x80
800186e: 2002 movs r0, #2
8001870: f7ff ff70 bl 8001754 <ADG715_SetChannels>
}
8001874: e006 b.n 8001884 <ADG715_Update+0xfc>
else if(channel == AD5934_CH_EC_HIGH_GAIN)
8001876: 79fb ldrb r3, [r7, #7]
8001878: 2b84 cmp r3, #132 @ 0x84
800187a: d103 bne.n 8001884 <ADG715_Update+0xfc>
ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC
800187c: 2180 movs r1, #128 @ 0x80
800187e: 2004 movs r0, #4
8001880: f7ff ff68 bl 8001754 <ADG715_SetChannels>
}
8001884: bf00 nop
8001886: 3708 adds r7, #8
8001888: 46bd mov sp, r7
800188a: bd80 pop {r7, pc}
0800188c <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
800188c: b580 push {r7, lr}
800188e: b084 sub sp, #16
8001890: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8001892: 1d3b adds r3, r7, #4
8001894: 2200 movs r2, #0
8001896: 601a str r2, [r3, #0]
8001898: 605a str r2, [r3, #4]
800189a: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
800189c: 4b18 ldr r3, [pc, #96] @ (8001900 <MX_ADC1_Init+0x74>)
800189e: 4a19 ldr r2, [pc, #100] @ (8001904 <MX_ADC1_Init+0x78>)
80018a0: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
80018a2: 4b17 ldr r3, [pc, #92] @ (8001900 <MX_ADC1_Init+0x74>)
80018a4: 2200 movs r2, #0
80018a6: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
80018a8: 4b15 ldr r3, [pc, #84] @ (8001900 <MX_ADC1_Init+0x74>)
80018aa: 2201 movs r2, #1
80018ac: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
80018ae: 4b14 ldr r3, [pc, #80] @ (8001900 <MX_ADC1_Init+0x74>)
80018b0: 2200 movs r2, #0
80018b2: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80018b4: 4b12 ldr r3, [pc, #72] @ (8001900 <MX_ADC1_Init+0x74>)
80018b6: f44f 2260 mov.w r2, #917504 @ 0xe0000
80018ba: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80018bc: 4b10 ldr r3, [pc, #64] @ (8001900 <MX_ADC1_Init+0x74>)
80018be: 2200 movs r2, #0
80018c0: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 1;
80018c2: 4b0f ldr r3, [pc, #60] @ (8001900 <MX_ADC1_Init+0x74>)
80018c4: 2201 movs r2, #1
80018c6: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80018c8: 480d ldr r0, [pc, #52] @ (8001900 <MX_ADC1_Init+0x74>)
80018ca: f001 f9fd bl 8002cc8 <HAL_ADC_Init>
80018ce: 4603 mov r3, r0
80018d0: 2b00 cmp r3, #0
80018d2: d001 beq.n 80018d8 <MX_ADC1_Init+0x4c>
{
Error_Handler();
80018d4: f000 ff66 bl 80027a4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_0;
80018d8: 2300 movs r3, #0
80018da: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80018dc: 2301 movs r3, #1
80018de: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80018e0: 2300 movs r3, #0
80018e2: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80018e4: 1d3b adds r3, r7, #4
80018e6: 4619 mov r1, r3
80018e8: 4805 ldr r0, [pc, #20] @ (8001900 <MX_ADC1_Init+0x74>)
80018ea: f001 fac5 bl 8002e78 <HAL_ADC_ConfigChannel>
80018ee: 4603 mov r3, r0
80018f0: 2b00 cmp r3, #0
80018f2: d001 beq.n 80018f8 <MX_ADC1_Init+0x6c>
{
Error_Handler();
80018f4: f000 ff56 bl 80027a4 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80018f8: bf00 nop
80018fa: 3710 adds r7, #16
80018fc: 46bd mov sp, r7
80018fe: bd80 pop {r7, pc}
8001900: 20000114 .word 0x20000114
8001904: 40012400 .word 0x40012400
08001908 <MX_ADC2_Init>:
/* ADC2 init function */
void MX_ADC2_Init(void)
{
8001908: b580 push {r7, lr}
800190a: b084 sub sp, #16
800190c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800190e: 1d3b adds r3, r7, #4
8001910: 2200 movs r2, #0
8001912: 601a str r2, [r3, #0]
8001914: 605a str r2, [r3, #4]
8001916: 609a str r2, [r3, #8]
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
8001918: 4b18 ldr r3, [pc, #96] @ (800197c <MX_ADC2_Init+0x74>)
800191a: 4a19 ldr r2, [pc, #100] @ (8001980 <MX_ADC2_Init+0x78>)
800191c: 601a str r2, [r3, #0]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
800191e: 4b17 ldr r3, [pc, #92] @ (800197c <MX_ADC2_Init+0x74>)
8001920: 2200 movs r2, #0
8001922: 609a str r2, [r3, #8]
hadc2.Init.ContinuousConvMode = ENABLE;
8001924: 4b15 ldr r3, [pc, #84] @ (800197c <MX_ADC2_Init+0x74>)
8001926: 2201 movs r2, #1
8001928: 731a strb r2, [r3, #12]
hadc2.Init.DiscontinuousConvMode = DISABLE;
800192a: 4b14 ldr r3, [pc, #80] @ (800197c <MX_ADC2_Init+0x74>)
800192c: 2200 movs r2, #0
800192e: 751a strb r2, [r3, #20]
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001930: 4b12 ldr r3, [pc, #72] @ (800197c <MX_ADC2_Init+0x74>)
8001932: f44f 2260 mov.w r2, #917504 @ 0xe0000
8001936: 61da str r2, [r3, #28]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001938: 4b10 ldr r3, [pc, #64] @ (800197c <MX_ADC2_Init+0x74>)
800193a: 2200 movs r2, #0
800193c: 605a str r2, [r3, #4]
hadc2.Init.NbrOfConversion = 1;
800193e: 4b0f ldr r3, [pc, #60] @ (800197c <MX_ADC2_Init+0x74>)
8001940: 2201 movs r2, #1
8001942: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8001944: 480d ldr r0, [pc, #52] @ (800197c <MX_ADC2_Init+0x74>)
8001946: f001 f9bf bl 8002cc8 <HAL_ADC_Init>
800194a: 4603 mov r3, r0
800194c: 2b00 cmp r3, #0
800194e: d001 beq.n 8001954 <MX_ADC2_Init+0x4c>
{
Error_Handler();
8001950: f000 ff28 bl 80027a4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
8001954: 2301 movs r3, #1
8001956: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001958: 2301 movs r3, #1
800195a: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800195c: 2300 movs r3, #0
800195e: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8001960: 1d3b adds r3, r7, #4
8001962: 4619 mov r1, r3
8001964: 4805 ldr r0, [pc, #20] @ (800197c <MX_ADC2_Init+0x74>)
8001966: f001 fa87 bl 8002e78 <HAL_ADC_ConfigChannel>
800196a: 4603 mov r3, r0
800196c: 2b00 cmp r3, #0
800196e: d001 beq.n 8001974 <MX_ADC2_Init+0x6c>
{
Error_Handler();
8001970: f000 ff18 bl 80027a4 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8001974: bf00 nop
8001976: 3710 adds r7, #16
8001978: 46bd mov sp, r7
800197a: bd80 pop {r7, pc}
800197c: 20000144 .word 0x20000144
8001980: 40012800 .word 0x40012800
08001984 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
8001984: b580 push {r7, lr}
8001986: b08a sub sp, #40 @ 0x28
8001988: af00 add r7, sp, #0
800198a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800198c: f107 0318 add.w r3, r7, #24
8001990: 2200 movs r2, #0
8001992: 601a str r2, [r3, #0]
8001994: 605a str r2, [r3, #4]
8001996: 609a str r2, [r3, #8]
8001998: 60da str r2, [r3, #12]
if(adcHandle->Instance==ADC1)
800199a: 687b ldr r3, [r7, #4]
800199c: 681b ldr r3, [r3, #0]
800199e: 4a28 ldr r2, [pc, #160] @ (8001a40 <HAL_ADC_MspInit+0xbc>)
80019a0: 4293 cmp r3, r2
80019a2: d122 bne.n 80019ea <HAL_ADC_MspInit+0x66>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
80019a4: 4b27 ldr r3, [pc, #156] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019a6: 699b ldr r3, [r3, #24]
80019a8: 4a26 ldr r2, [pc, #152] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019aa: f443 7300 orr.w r3, r3, #512 @ 0x200
80019ae: 6193 str r3, [r2, #24]
80019b0: 4b24 ldr r3, [pc, #144] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019b2: 699b ldr r3, [r3, #24]
80019b4: f403 7300 and.w r3, r3, #512 @ 0x200
80019b8: 617b str r3, [r7, #20]
80019ba: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
80019bc: 4b21 ldr r3, [pc, #132] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019be: 699b ldr r3, [r3, #24]
80019c0: 4a20 ldr r2, [pc, #128] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019c2: f043 0304 orr.w r3, r3, #4
80019c6: 6193 str r3, [r2, #24]
80019c8: 4b1e ldr r3, [pc, #120] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019ca: 699b ldr r3, [r3, #24]
80019cc: f003 0304 and.w r3, r3, #4
80019d0: 613b str r3, [r7, #16]
80019d2: 693b ldr r3, [r7, #16]
/**ADC1 GPIO Configuration
PA0-WKUP ------> ADC1_IN0
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
80019d4: 2303 movs r3, #3
80019d6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80019d8: 2303 movs r3, #3
80019da: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80019dc: f107 0318 add.w r3, r7, #24
80019e0: 4619 mov r1, r3
80019e2: 4819 ldr r0, [pc, #100] @ (8001a48 <HAL_ADC_MspInit+0xc4>)
80019e4: f001 ff42 bl 800386c <HAL_GPIO_Init>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80019e8: e026 b.n 8001a38 <HAL_ADC_MspInit+0xb4>
else if(adcHandle->Instance==ADC2)
80019ea: 687b ldr r3, [r7, #4]
80019ec: 681b ldr r3, [r3, #0]
80019ee: 4a17 ldr r2, [pc, #92] @ (8001a4c <HAL_ADC_MspInit+0xc8>)
80019f0: 4293 cmp r3, r2
80019f2: d121 bne.n 8001a38 <HAL_ADC_MspInit+0xb4>
__HAL_RCC_ADC2_CLK_ENABLE();
80019f4: 4b13 ldr r3, [pc, #76] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019f6: 699b ldr r3, [r3, #24]
80019f8: 4a12 ldr r2, [pc, #72] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
80019fa: f443 6380 orr.w r3, r3, #1024 @ 0x400
80019fe: 6193 str r3, [r2, #24]
8001a00: 4b10 ldr r3, [pc, #64] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
8001a02: 699b ldr r3, [r3, #24]
8001a04: f403 6380 and.w r3, r3, #1024 @ 0x400
8001a08: 60fb str r3, [r7, #12]
8001a0a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001a0c: 4b0d ldr r3, [pc, #52] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
8001a0e: 699b ldr r3, [r3, #24]
8001a10: 4a0c ldr r2, [pc, #48] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
8001a12: f043 0304 orr.w r3, r3, #4
8001a16: 6193 str r3, [r2, #24]
8001a18: 4b0a ldr r3, [pc, #40] @ (8001a44 <HAL_ADC_MspInit+0xc0>)
8001a1a: 699b ldr r3, [r3, #24]
8001a1c: f003 0304 and.w r3, r3, #4
8001a20: 60bb str r3, [r7, #8]
8001a22: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
8001a24: 2303 movs r3, #3
8001a26: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001a28: 2303 movs r3, #3
8001a2a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a2c: f107 0318 add.w r3, r7, #24
8001a30: 4619 mov r1, r3
8001a32: 4805 ldr r0, [pc, #20] @ (8001a48 <HAL_ADC_MspInit+0xc4>)
8001a34: f001 ff1a bl 800386c <HAL_GPIO_Init>
}
8001a38: bf00 nop
8001a3a: 3728 adds r7, #40 @ 0x28
8001a3c: 46bd mov sp, r7
8001a3e: bd80 pop {r7, pc}
8001a40: 40012400 .word 0x40012400
8001a44: 40021000 .word 0x40021000
8001a48: 40010800 .word 0x40010800
8001a4c: 40012800 .word 0x40012800
08001a50 <writeRegister>:
ADS1015_I2C i2c;
float ph_dut_samples[ADS1015_PH_AVERAGES]={0};
// Write the register
static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
8001a50: b580 push {r7, lr}
8001a52: b086 sub sp, #24
8001a54: af02 add r7, sp, #8
8001a56: 6078 str r0, [r7, #4]
8001a58: 460b mov r3, r1
8001a5a: 70fb strb r3, [r7, #3]
8001a5c: 4613 mov r3, r2
8001a5e: 803b strh r3, [r7, #0]
uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
8001a60: 78fb ldrb r3, [r7, #3]
8001a62: 733b strb r3, [r7, #12]
8001a64: 883b ldrh r3, [r7, #0]
8001a66: 0a1b lsrs r3, r3, #8
8001a68: b29b uxth r3, r3
8001a6a: b2db uxtb r3, r3
8001a6c: 737b strb r3, [r7, #13]
8001a6e: 883b ldrh r3, [r7, #0]
8001a70: b2db uxtb r3, r3
8001a72: 73bb strb r3, [r7, #14]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
8001a74: 687b ldr r3, [r7, #4]
8001a76: 68d8 ldr r0, [r3, #12]
8001a78: 687b ldr r3, [r7, #4]
8001a7a: 8819 ldrh r1, [r3, #0]
8001a7c: f107 020c add.w r2, r7, #12
8001a80: 230a movs r3, #10
8001a82: 9300 str r3, [sp, #0]
8001a84: 2303 movs r3, #3
8001a86: f002 fa01 bl 8003e8c <HAL_I2C_Master_Transmit>
}
8001a8a: bf00 nop
8001a8c: 3710 adds r7, #16
8001a8e: 46bd mov sp, r7
8001a90: bd80 pop {r7, pc}
08001a92 <readRegister>:
// Read the register
static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
8001a92: b580 push {r7, lr}
8001a94: b086 sub sp, #24
8001a96: af02 add r7, sp, #8
8001a98: 6078 str r0, [r7, #4]
8001a9a: 460b mov r3, r1
8001a9c: 70fb strb r3, [r7, #3]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, &reg, 1, 10);
8001a9e: 687b ldr r3, [r7, #4]
8001aa0: 68d8 ldr r0, [r3, #12]
8001aa2: 687b ldr r3, [r7, #4]
8001aa4: 8819 ldrh r1, [r3, #0]
8001aa6: 1cfa adds r2, r7, #3
8001aa8: 230a movs r3, #10
8001aaa: 9300 str r3, [sp, #0]
8001aac: 2301 movs r3, #1
8001aae: f002 f9ed bl 8003e8c <HAL_I2C_Master_Transmit>
uint8_t pData[2] = { 0, 0 };
8001ab2: 2300 movs r3, #0
8001ab4: 81bb strh r3, [r7, #12]
HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
8001ab6: 687b ldr r3, [r7, #4]
8001ab8: 68d8 ldr r0, [r3, #12]
8001aba: 687b ldr r3, [r7, #4]
8001abc: 8819 ldrh r1, [r3, #0]
8001abe: f107 020c add.w r2, r7, #12
8001ac2: 230a movs r3, #10
8001ac4: 9300 str r3, [sp, #0]
8001ac6: 2302 movs r3, #2
8001ac8: f002 fade bl 8004088 <HAL_I2C_Master_Receive>
return ((pData[0] << 8) | pData[1]);
8001acc: 7b3b ldrb r3, [r7, #12]
8001ace: b21b sxth r3, r3
8001ad0: 021b lsls r3, r3, #8
8001ad2: b21a sxth r2, r3
8001ad4: 7b7b ldrb r3, [r7, #13]
8001ad6: b21b sxth r3, r3
8001ad8: 4313 orrs r3, r2
8001ada: b21b sxth r3, r3
8001adc: b29b uxth r3, r3
}
8001ade: 4618 mov r0, r3
8001ae0: 3710 adds r7, #16
8001ae2: 46bd mov sp, r7
8001ae4: bd80 pop {r7, pc}
08001ae6 <ADS1015>:
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // This MUST have GPIO PA5 ready to use - ERROR I2C - Wrong address
}
// Declare an ADS1015 structure
void ADS1015(ADS1015_I2C *i2c, I2C_HandleTypeDef *hi2c, uint8_t i2cAddress) {
8001ae6: b480 push {r7}
8001ae8: b085 sub sp, #20
8001aea: af00 add r7, sp, #0
8001aec: 60f8 str r0, [r7, #12]
8001aee: 60b9 str r1, [r7, #8]
8001af0: 4613 mov r3, r2
8001af2: 71fb strb r3, [r7, #7]
i2c->hi2c = hi2c;
8001af4: 68fb ldr r3, [r7, #12]
8001af6: 68ba ldr r2, [r7, #8]
8001af8: 60da str r2, [r3, #12]
i2c->m_i2cAddress = i2cAddress << 1; // It's Important to shift the address << 1
8001afa: 79fb ldrb r3, [r7, #7]
8001afc: b29b uxth r3, r3
8001afe: 005b lsls r3, r3, #1
8001b00: b29a uxth r2, r3
8001b02: 68fb ldr r3, [r7, #12]
8001b04: 801a strh r2, [r3, #0]
i2c->m_conversionDelay = ADS1015_CONVERSIONDELAY;
8001b06: 68fb ldr r3, [r7, #12]
8001b08: 2204 movs r2, #4
8001b0a: 605a str r2, [r3, #4]
i2c->m_bitShift = 4;
8001b0c: 68fb ldr r3, [r7, #12]
8001b0e: 2204 movs r2, #4
8001b10: 721a strb r2, [r3, #8]
i2c->m_gain = GAIN_TWOTHIRDS; /* +/- 6.144V range (limited to VDD +0.3V max!) */
8001b12: 68fb ldr r3, [r7, #12]
8001b14: 2200 movs r2, #0
8001b16: 815a strh r2, [r3, #10]
//ADSbegin(i2c); //Ready is not used
}
8001b18: bf00 nop
8001b1a: 3714 adds r7, #20
8001b1c: 46bd mov sp, r7
8001b1e: bc80 pop {r7}
8001b20: 4770 bx lr
08001b22 <ADSsetGain>:
// ADSsetGain(GAIN_TWO); // 2x gain +/- 2.048V 1 bit = 1mV 0.0625mV
// ADSsetGain(GAIN_FOUR); // 4x gain +/- 1.024V 1 bit = 0.5mV 0.03125mV
// ADSsetGain(GAIN_EIGHT); // 8x gain +/- 0.512V 1 bit = 0.25mV 0.015625mV
// ADSsetGain(GAIN_SIXTEEN); // 16x gain +/- 0.256V 1 bit = 0.125mV 0.0078125mV
*/
void ADSsetGain(ADS1015_I2C *i2c, adsGain_t gain) {
8001b22: b480 push {r7}
8001b24: b083 sub sp, #12
8001b26: af00 add r7, sp, #0
8001b28: 6078 str r0, [r7, #4]
8001b2a: 460b mov r3, r1
8001b2c: 807b strh r3, [r7, #2]
i2c->m_gain = gain;
8001b2e: 687b ldr r3, [r7, #4]
8001b30: 887a ldrh r2, [r7, #2]
8001b32: 815a strh r2, [r3, #10]
}
8001b34: bf00 nop
8001b36: 370c adds r7, #12
8001b38: 46bd mov sp, r7
8001b3a: bc80 pop {r7}
8001b3c: 4770 bx lr
08001b3e <ADSreadADC_Differential_0_1>:
/*
* Reads the conversion results, measuring the voltage
* difference between the P (AIN0) and N (AIN1) input. Generates
* a signed value since the difference can be either positive or negative.
*/
int16_t ADSreadADC_Differential_0_1(ADS1015_I2C *i2c) {
8001b3e: b580 push {r7, lr}
8001b40: b084 sub sp, #16
8001b42: af00 add r7, sp, #0
8001b44: 6078 str r0, [r7, #4]
// Start with default values
uint16_t config =
8001b46: f240 1303 movw r3, #259 @ 0x103
8001b4a: 81bb strh r3, [r7, #12]
ADS1015_REG_CONFIG_CMODE_TRAD | // Traditional comparator (default val)
ADS1015_REG_CONFIG_DR_128SPS | // 128 samples per second (default)
ADS1015_REG_CONFIG_MODE_SINGLE; // Single-shot mode (default)
// Set PGA/voltage range
config |= i2c->m_gain;
8001b4c: 687b ldr r3, [r7, #4]
8001b4e: 895a ldrh r2, [r3, #10]
8001b50: 89bb ldrh r3, [r7, #12]
8001b52: 4313 orrs r3, r2
8001b54: 81bb strh r3, [r7, #12]
// Set channels
config |= ADS1015_REG_CONFIG_MUX_DIFF_0_1; // AIN0 = P, AIN1 = N
// Set 'start single-conversion' bit
config |= ADS1015_REG_CONFIG_OS_SINGLE;
8001b56: 89bb ldrh r3, [r7, #12]
8001b58: ea6f 4343 mvn.w r3, r3, lsl #17
8001b5c: ea6f 4353 mvn.w r3, r3, lsr #17
8001b60: 81bb strh r3, [r7, #12]
// Write config register to the ADC
writeRegister(i2c, ADS1015_REG_POINTER_CONFIG, config);
8001b62: 89bb ldrh r3, [r7, #12]
8001b64: 461a mov r2, r3
8001b66: 2101 movs r1, #1
8001b68: 6878 ldr r0, [r7, #4]
8001b6a: f7ff ff71 bl 8001a50 <writeRegister>
// Wait for the conversion to complete
HAL_Delay(i2c->m_conversionDelay);
8001b6e: 687b ldr r3, [r7, #4]
8001b70: 685b ldr r3, [r3, #4]
8001b72: 4618 mov r0, r3
8001b74: f001 f884 bl 8002c80 <HAL_Delay>
// Read the conversion results
uint16_t res = readRegister(i2c, ADS1015_REG_POINTER_CONVERT) >> i2c->m_bitShift;
8001b78: 2100 movs r1, #0
8001b7a: 6878 ldr r0, [r7, #4]
8001b7c: f7ff ff89 bl 8001a92 <readRegister>
8001b80: 4603 mov r3, r0
8001b82: 461a mov r2, r3
8001b84: 687b ldr r3, [r7, #4]
8001b86: 7a1b ldrb r3, [r3, #8]
8001b88: fa42 f303 asr.w r3, r2, r3
8001b8c: 81fb strh r3, [r7, #14]
if (i2c->m_bitShift == 0) {
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 7a1b ldrb r3, [r3, #8]
8001b92: 2b00 cmp r3, #0
8001b94: d102 bne.n 8001b9c <ADSreadADC_Differential_0_1+0x5e>
return (int16_t) res;
8001b96: f9b7 300e ldrsh.w r3, [r7, #14]
8001b9a: e00b b.n 8001bb4 <ADSreadADC_Differential_0_1+0x76>
} else {
// Shift 12-bit results right 4 bits for the ADS1015,
// making sure we keep the sign bit intact
if (res > 0x07FF) {
8001b9c: 89fb ldrh r3, [r7, #14]
8001b9e: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8001ba2: d305 bcc.n 8001bb0 <ADSreadADC_Differential_0_1+0x72>
// negative number - extend the sign to 16th bit
res |= 0xF000;
8001ba4: 89fb ldrh r3, [r7, #14]
8001ba6: ea6f 5303 mvn.w r3, r3, lsl #20
8001baa: ea6f 5313 mvn.w r3, r3, lsr #20
8001bae: 81fb strh r3, [r7, #14]
}
return (int16_t) res;
8001bb0: f9b7 300e ldrsh.w r3, [r7, #14]
}
}
8001bb4: 4618 mov r0, r3
8001bb6: 3710 adds r7, #16
8001bb8: 46bd mov sp, r7
8001bba: bd80 pop {r7, pc}
08001bbc <ADSCalculate_ph_Volts>:
return (int16_t) res;
}
}
float ADSCalculate_ph_Volts(void)
{
8001bbc: b580 push {r7, lr}
8001bbe: b082 sub sp, #8
8001bc0: af00 add r7, sp, #0
float ph_dut_sum;
uint8_t i;
for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
8001bc2: 2307 movs r3, #7
8001bc4: 70fb strb r3, [r7, #3]
8001bc6: e00b b.n 8001be0 <ADSCalculate_ph_Volts+0x24>
ph_dut_samples[i] = ph_dut_samples[i-1];
8001bc8: 78fb ldrb r3, [r7, #3]
8001bca: 1e5a subs r2, r3, #1
8001bcc: 78fb ldrb r3, [r7, #3]
8001bce: 4922 ldr r1, [pc, #136] @ (8001c58 <ADSCalculate_ph_Volts+0x9c>)
8001bd0: f851 2022 ldr.w r2, [r1, r2, lsl #2]
8001bd4: 4920 ldr r1, [pc, #128] @ (8001c58 <ADSCalculate_ph_Volts+0x9c>)
8001bd6: f841 2023 str.w r2, [r1, r3, lsl #2]
for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
8001bda: 78fb ldrb r3, [r7, #3]
8001bdc: 3b01 subs r3, #1
8001bde: 70fb strb r3, [r7, #3]
8001be0: 78fb ldrb r3, [r7, #3]
8001be2: 2b00 cmp r3, #0
8001be4: d1f0 bne.n 8001bc8 <ADSCalculate_ph_Volts+0xc>
ph_dut_samples[0] = (((float)(2048 - ADSreadADC_Differential_0_1(&i2c)) * ADS1015_ADC_VREF) / ADS1015_ADC_MAX); // 1. Converter leitura bruta do ADC para tensão real (Volts)
8001be6: 481d ldr r0, [pc, #116] @ (8001c5c <ADSCalculate_ph_Volts+0xa0>)
8001be8: f7ff ffa9 bl 8001b3e <ADSreadADC_Differential_0_1>
8001bec: 4603 mov r3, r0
8001bee: f5c3 6300 rsb r3, r3, #2048 @ 0x800
8001bf2: 4618 mov r0, r3
8001bf4: f7fe ff02 bl 80009fc <__aeabi_i2f>
8001bf8: 4603 mov r3, r0
8001bfa: 4919 ldr r1, [pc, #100] @ (8001c60 <ADSCalculate_ph_Volts+0xa4>)
8001bfc: 4618 mov r0, r3
8001bfe: f7fe ff51 bl 8000aa4 <__aeabi_fmul>
8001c02: 4603 mov r3, r0
8001c04: 4917 ldr r1, [pc, #92] @ (8001c64 <ADSCalculate_ph_Volts+0xa8>)
8001c06: 4618 mov r0, r3
8001c08: f7ff f800 bl 8000c0c <__aeabi_fdiv>
8001c0c: 4603 mov r3, r0
8001c0e: 461a mov r2, r3
8001c10: 4b11 ldr r3, [pc, #68] @ (8001c58 <ADSCalculate_ph_Volts+0x9c>)
8001c12: 601a str r2, [r3, #0]
for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
8001c14: 2300 movs r3, #0
8001c16: 70fb strb r3, [r7, #3]
8001c18: f04f 0300 mov.w r3, #0
8001c1c: 607b str r3, [r7, #4]
8001c1e: e00c b.n 8001c3a <ADSCalculate_ph_Volts+0x7e>
ph_dut_sum += ph_dut_samples[i];
8001c20: 78fb ldrb r3, [r7, #3]
8001c22: 4a0d ldr r2, [pc, #52] @ (8001c58 <ADSCalculate_ph_Volts+0x9c>)
8001c24: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001c28: 4619 mov r1, r3
8001c2a: 6878 ldr r0, [r7, #4]
8001c2c: f7fe fe32 bl 8000894 <__addsf3>
8001c30: 4603 mov r3, r0
8001c32: 607b str r3, [r7, #4]
for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
8001c34: 78fb ldrb r3, [r7, #3]
8001c36: 3301 adds r3, #1
8001c38: 70fb strb r3, [r7, #3]
8001c3a: 78fb ldrb r3, [r7, #3]
8001c3c: 2b07 cmp r3, #7
8001c3e: d9ef bls.n 8001c20 <ADSCalculate_ph_Volts+0x64>
ph_dut_sum /= ADS1015_PH_AVERAGES;
8001c40: f04f 4182 mov.w r1, #1090519040 @ 0x41000000
8001c44: 6878 ldr r0, [r7, #4]
8001c46: f7fe ffe1 bl 8000c0c <__aeabi_fdiv>
8001c4a: 4603 mov r3, r0
8001c4c: 607b str r3, [r7, #4]
return (ph_dut_sum);
8001c4e: 687b ldr r3, [r7, #4]
}
8001c50: 4618 mov r0, r3
8001c52: 3708 adds r7, #8
8001c54: 46bd mov sp, r7
8001c56: bd80 pop {r7, pc}
8001c58: 20000184 .word 0x20000184
8001c5c: 20000174 .word 0x20000174
8001c60: 40533333 .word 0x40533333
8001c64: 457ff000 .word 0x457ff000
08001c68 <ADSCalculate_ph_Uncompensated>:
*
* @param temp_dut Unused in this non-compensated version.
* @return float Calculated pH value [0.0, 14.0]. Returns 0.0 if calibration error detected.
*/
float ADSCalculate_ph_Uncompensated(void)
{
8001c68: b580 push {r7, lr}
8001c6a: b084 sub sp, #16
8001c6c: af00 add r7, sp, #0
/*
* 1. Convert raw ADC reading to actual voltage (Volts).
* Note: The subtraction of 2048 assumes a differential configuration
* where the midpoint is at the mid-scale of the ADS1015.
*/
float v_measured = ((float)(2048 - ADSreadADC_Differential_0_1(&i2c)) * ADS1015_ADC_VREF) / ADS1015_ADC_MAX;
8001c6e: 482e ldr r0, [pc, #184] @ (8001d28 <ADSCalculate_ph_Uncompensated+0xc0>)
8001c70: f7ff ff65 bl 8001b3e <ADSreadADC_Differential_0_1>
8001c74: 4603 mov r3, r0
8001c76: f5c3 6300 rsb r3, r3, #2048 @ 0x800
8001c7a: 4618 mov r0, r3
8001c7c: f7fe febe bl 80009fc <__aeabi_i2f>
8001c80: 4603 mov r3, r0
8001c82: 492a ldr r1, [pc, #168] @ (8001d2c <ADSCalculate_ph_Uncompensated+0xc4>)
8001c84: 4618 mov r0, r3
8001c86: f7fe ff0d bl 8000aa4 <__aeabi_fmul>
8001c8a: 4603 mov r3, r0
8001c8c: 4928 ldr r1, [pc, #160] @ (8001d30 <ADSCalculate_ph_Uncompensated+0xc8>)
8001c8e: 4618 mov r0, r3
8001c90: f7fe ffbc bl 8000c0c <__aeabi_fdiv>
8001c94: 4603 mov r3, r0
8001c96: 60bb str r3, [r7, #8]
/*
* 2. Calculate the original Slope (measured during calibration).
* PH_DELTA_CALIB is a constant representing the pH difference between
* calibration points (e.g., |7.0 - 4.0| = 3.0).
*/
float delta_v_calib = flash_data.ph7_volts - flash_data.ph4_volts;
8001c98: 4b26 ldr r3, [pc, #152] @ (8001d34 <ADSCalculate_ph_Uncompensated+0xcc>)
8001c9a: 689b ldr r3, [r3, #8]
8001c9c: 4a25 ldr r2, [pc, #148] @ (8001d34 <ADSCalculate_ph_Uncompensated+0xcc>)
8001c9e: 6852 ldr r2, [r2, #4]
8001ca0: 4611 mov r1, r2
8001ca2: 4618 mov r0, r3
8001ca4: f7fe fdf4 bl 8000890 <__aeabi_fsub>
8001ca8: 4603 mov r3, r0
8001caa: 607b str r3, [r7, #4]
/* Safety check: Prevent division by zero if calibration data is invalid */
if (delta_v_calib == 0.0f)
8001cac: f04f 0100 mov.w r1, #0
8001cb0: 6878 ldr r0, [r7, #4]
8001cb2: f7ff f88b bl 8000dcc <__aeabi_fcmpeq>
8001cb6: 4603 mov r3, r0
8001cb8: 2b00 cmp r3, #0
8001cba: d002 beq.n 8001cc2 <ADSCalculate_ph_Uncompensated+0x5a>
{
return 0.0f;
8001cbc: f04f 0300 mov.w r3, #0
8001cc0: e02d b.n 8001d1e <ADSCalculate_ph_Uncompensated+0xb6>
}
/* Slope = Delta pH / Delta Voltage */
float slope_at_calib = PH_DELTA_CALIB / delta_v_calib;
8001cc2: 6879 ldr r1, [r7, #4]
8001cc4: 481c ldr r0, [pc, #112] @ (8001d38 <ADSCalculate_ph_Uncompensated+0xd0>)
8001cc6: f7fe ffa1 bl 8000c0c <__aeabi_fdiv>
8001cca: 4603 mov r3, r0
8001ccc: 603b str r3, [r7, #0]
/*
* 3. Final pH Calculation (Non-compensated)
* Formula: pH = pH_ref + (V_measured - V_ref_7) * Slope
* Where pH_ref is 7.0.
*/
float ph_result = 7.0f + ((v_measured - flash_data.ph7_volts) * slope_at_calib);
8001cce: 4b19 ldr r3, [pc, #100] @ (8001d34 <ADSCalculate_ph_Uncompensated+0xcc>)
8001cd0: 689b ldr r3, [r3, #8]
8001cd2: 4619 mov r1, r3
8001cd4: 68b8 ldr r0, [r7, #8]
8001cd6: f7fe fddb bl 8000890 <__aeabi_fsub>
8001cda: 4603 mov r3, r0
8001cdc: 6839 ldr r1, [r7, #0]
8001cde: 4618 mov r0, r3
8001ce0: f7fe fee0 bl 8000aa4 <__aeabi_fmul>
8001ce4: 4603 mov r3, r0
8001ce6: 4915 ldr r1, [pc, #84] @ (8001d3c <ADSCalculate_ph_Uncompensated+0xd4>)
8001ce8: 4618 mov r0, r3
8001cea: f7fe fdd3 bl 8000894 <__addsf3>
8001cee: 4603 mov r3, r0
8001cf0: 60fb str r3, [r7, #12]
/* 4. Clamping (Ensure physical limits of the pH scale) */
if (ph_result < 0.0f)
8001cf2: f04f 0100 mov.w r1, #0
8001cf6: 68f8 ldr r0, [r7, #12]
8001cf8: f7ff f872 bl 8000de0 <__aeabi_fcmplt>
8001cfc: 4603 mov r3, r0
8001cfe: 2b00 cmp r3, #0
8001d00: d003 beq.n 8001d0a <ADSCalculate_ph_Uncompensated+0xa2>
{
ph_result = 0.0f;
8001d02: f04f 0300 mov.w r3, #0
8001d06: 60fb str r3, [r7, #12]
8001d08: e008 b.n 8001d1c <ADSCalculate_ph_Uncompensated+0xb4>
}
else if (ph_result > 14.0f)
8001d0a: 490d ldr r1, [pc, #52] @ (8001d40 <ADSCalculate_ph_Uncompensated+0xd8>)
8001d0c: 68f8 ldr r0, [r7, #12]
8001d0e: f7ff f885 bl 8000e1c <__aeabi_fcmpgt>
8001d12: 4603 mov r3, r0
8001d14: 2b00 cmp r3, #0
8001d16: d001 beq.n 8001d1c <ADSCalculate_ph_Uncompensated+0xb4>
{
ph_result = 14.0f;
8001d18: 4b09 ldr r3, [pc, #36] @ (8001d40 <ADSCalculate_ph_Uncompensated+0xd8>)
8001d1a: 60fb str r3, [r7, #12]
}
return ph_result;
8001d1c: 68fb ldr r3, [r7, #12]
}
8001d1e: 4618 mov r0, r3
8001d20: 3710 adds r7, #16
8001d22: 46bd mov sp, r7
8001d24: bd80 pop {r7, pc}
8001d26: bf00 nop
8001d28: 20000174 .word 0x20000174
8001d2c: 40533333 .word 0x40533333
8001d30: 457ff000 .word 0x457ff000
8001d34: 200001ac .word 0x200001ac
8001d38: 40400000 .word 0x40400000
8001d3c: 40e00000 .word 0x40e00000
8001d40: 41600000 .word 0x41600000
08001d44 <digital_outputs_init>:
* @brief Initializes the GPIO hardware and sets initial states.
* @note This function replaces the handle-based init.
* @retval None
*/
void digital_outputs_init(void)
{
8001d44: b580 push {r7, lr}
8001d46: b086 sub sp, #24
8001d48: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001d4a: 1d3b adds r3, r7, #4
8001d4c: 2200 movs r2, #0
8001d4e: 601a str r2, [r3, #0]
8001d50: 605a str r2, [r3, #4]
8001d52: 609a str r2, [r3, #8]
8001d54: 60da str r2, [r3, #12]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001d56: 2300 movs r3, #0
8001d58: 617b str r3, [r7, #20]
8001d5a: e029 b.n 8001db0 <digital_outputs_init+0x6c>
GPIO_InitStruct.Pin = output_pins[i].pin;
8001d5c: 4a18 ldr r2, [pc, #96] @ (8001dc0 <digital_outputs_init+0x7c>)
8001d5e: 697b ldr r3, [r7, #20]
8001d60: 00db lsls r3, r3, #3
8001d62: 4413 add r3, r2
8001d64: 889b ldrh r3, [r3, #4]
8001d66: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain
8001d68: 2311 movs r3, #17
8001d6a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d6c: 2300 movs r3, #0
8001d6e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001d70: 2302 movs r3, #2
8001d72: 613b str r3, [r7, #16]
HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
8001d74: 4a12 ldr r2, [pc, #72] @ (8001dc0 <digital_outputs_init+0x7c>)
8001d76: 697b ldr r3, [r7, #20]
8001d78: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8001d7c: 1d3a adds r2, r7, #4
8001d7e: 4611 mov r1, r2
8001d80: 4618 mov r0, r3
8001d82: f001 fd73 bl 800386c <HAL_GPIO_Init>
// Force initial state to LOW (Reset)
HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET);
8001d86: 4a0e ldr r2, [pc, #56] @ (8001dc0 <digital_outputs_init+0x7c>)
8001d88: 697b ldr r3, [r7, #20]
8001d8a: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8001d8e: 4a0c ldr r2, [pc, #48] @ (8001dc0 <digital_outputs_init+0x7c>)
8001d90: 697b ldr r3, [r7, #20]
8001d92: 00db lsls r3, r3, #3
8001d94: 4413 add r3, r2
8001d96: 889b ldrh r3, [r3, #4]
8001d98: 2200 movs r2, #0
8001d9a: 4619 mov r1, r3
8001d9c: f001 ff01 bl 8003ba2 <HAL_GPIO_WritePin>
pin_states[i] = 0;
8001da0: 4a08 ldr r2, [pc, #32] @ (8001dc4 <digital_outputs_init+0x80>)
8001da2: 697b ldr r3, [r7, #20]
8001da4: 4413 add r3, r2
8001da6: 2200 movs r2, #0
8001da8: 701a strb r2, [r3, #0]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001daa: 697b ldr r3, [r7, #20]
8001dac: 3301 adds r3, #1
8001dae: 617b str r3, [r7, #20]
8001db0: 697b ldr r3, [r7, #20]
8001db2: 2b07 cmp r3, #7
8001db4: ddd2 ble.n 8001d5c <digital_outputs_init+0x18>
}
}
8001db6: bf00 nop
8001db8: bf00 nop
8001dba: 3718 adds r7, #24
8001dbc: 46bd mov sp, r7
8001dbe: bd80 pop {r7, pc}
8001dc0: 08006428 .word 0x08006428
8001dc4: 200001a4 .word 0x200001a4
08001dc8 <Flash_Save_Page>:
* @return HAL_OK em caso de sucesso.
*/
FlashPage_t flash_data;
HAL_StatusTypeDef Flash_Save_Page(FlashPage_t *pPage) {
8001dc8: b5b0 push {r4, r5, r7, lr}
8001dca: b08c sub sp, #48 @ 0x30
8001dcc: af00 add r7, sp, #0
8001dce: 6078 str r0, [r7, #4]
if (pPage == NULL) return HAL_ERROR;
8001dd0: 687b ldr r3, [r7, #4]
8001dd2: 2b00 cmp r3, #0
8001dd4: d101 bne.n 8001dda <Flash_Save_Page+0x12>
8001dd6: 2301 movs r3, #1
8001dd8: e04a b.n 8001e70 <Flash_Save_Page+0xa8>
HAL_StatusTypeDef status = HAL_OK;
8001dda: 2300 movs r3, #0
8001ddc: f887 302f strb.w r3, [r7, #47] @ 0x2f
HAL_FLASH_Unlock();
8001de0: f001 fbb4 bl 800354c <HAL_FLASH_Unlock>
// 1. Apagar a página inteira (limpa os 1024 bytes)
FLASH_EraseInitTypeDef EraseInitStruct;
uint32_t PageError = 0;
8001de4: 2300 movs r3, #0
8001de6: 60bb str r3, [r7, #8]
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
8001de8: 2300 movs r3, #0
8001dea: 60fb str r3, [r7, #12]
EraseInitStruct.PageAddress = FLASH_PAGE_ADDR;
8001dec: 4b22 ldr r3, [pc, #136] @ (8001e78 <Flash_Save_Page+0xb0>)
8001dee: 617b str r3, [r7, #20]
EraseInitStruct.NbPages = 1;
8001df0: 2301 movs r3, #1
8001df2: 61bb str r3, [r7, #24]
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) {
8001df4: f107 0208 add.w r2, r7, #8
8001df8: f107 030c add.w r3, r7, #12
8001dfc: 4611 mov r1, r2
8001dfe: 4618 mov r0, r3
8001e00: f001 fc8c bl 800371c <HAL_FLASHEx_Erase>
8001e04: 4603 mov r3, r0
8001e06: 2b00 cmp r3, #0
8001e08: d003 beq.n 8001e12 <Flash_Save_Page+0x4a>
status = HAL_ERROR;
8001e0a: 2301 movs r3, #1
8001e0c: f887 302f strb.w r3, [r7, #47] @ 0x2f
goto Exit;
8001e10: e02a b.n 8001e68 <Flash_Save_Page+0xa0>
// 2. Gravar o bloco de 1KB
// Como a estrutura é exatamente 1KB e alinhada, podemos tratar como um array de uint32_t.
// O STM32F1 grava preferencialmente em DoubleWord (64-bit), mas HalfWord (16-bit)
// funciona de forma segura para qualquer tamanho múltiplo de 2.
uint32_t *pSrc = (uint32_t *)pPage;
8001e12: 687b ldr r3, [r7, #4]
8001e14: 627b str r3, [r7, #36] @ 0x24
uint32_t *pDest = (uint32_t *)FLASH_PAGE_ADDR;
8001e16: 4b18 ldr r3, [pc, #96] @ (8001e78 <Flash_Save_Page+0xb0>)
8001e18: 623b str r3, [r7, #32]
uint32_t iterations = FLASH_PAGE_SIZE / sizeof(uint32_t); // 1024 / 4 = 256 iterações
8001e1a: f44f 7380 mov.w r3, #256 @ 0x100
8001e1e: 61fb str r3, [r7, #28]
for (uint32_t i = 0; i < iterations; i++) {
8001e20: 2300 movs r3, #0
8001e22: 62bb str r3, [r7, #40] @ 0x28
8001e24: e01b b.n 8001e5e <Flash_Save_Page+0x96>
// Usamos o modo de gravação de 32-bit (Word) se disponível,
// ou simulamos com duas gravações de 16-bit para máxima compatuidade no F1.
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, (uint32_t)&pDest[i], pSrc[i]) != HAL_OK) {
8001e26: 6abb ldr r3, [r7, #40] @ 0x28
8001e28: 009b lsls r3, r3, #2
8001e2a: 6a3a ldr r2, [r7, #32]
8001e2c: 4413 add r3, r2
8001e2e: 4619 mov r1, r3
8001e30: 6abb ldr r3, [r7, #40] @ 0x28
8001e32: 009b lsls r3, r3, #2
8001e34: 6a7a ldr r2, [r7, #36] @ 0x24
8001e36: 4413 add r3, r2
8001e38: 681b ldr r3, [r3, #0]
8001e3a: 2200 movs r2, #0
8001e3c: 461c mov r4, r3
8001e3e: 4615 mov r5, r2
8001e40: 4622 mov r2, r4
8001e42: 462b mov r3, r5
8001e44: 2002 movs r0, #2
8001e46: f001 fb11 bl 800346c <HAL_FLASH_Program>
8001e4a: 4603 mov r3, r0
8001e4c: 2b00 cmp r3, #0
8001e4e: d003 beq.n 8001e58 <Flash_Save_Page+0x90>
status = HAL_ERROR;
8001e50: 2301 movs r3, #1
8001e52: f887 302f strb.w r3, [r7, #47] @ 0x2f
break;
8001e56: e007 b.n 8001e68 <Flash_Save_Page+0xa0>
for (uint32_t i = 0; i < iterations; i++) {
8001e58: 6abb ldr r3, [r7, #40] @ 0x28
8001e5a: 3301 adds r3, #1
8001e5c: 62bb str r3, [r7, #40] @ 0x28
8001e5e: 6aba ldr r2, [r7, #40] @ 0x28
8001e60: 69fb ldr r3, [r7, #28]
8001e62: 429a cmp r2, r3
8001e64: d3df bcc.n 8001e26 <Flash_Save_Page+0x5e>
}
}
Exit:
8001e66: bf00 nop
HAL_FLASH_Lock();
8001e68: f001 fb96 bl 8003598 <HAL_FLASH_Lock>
return status;
8001e6c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
}
8001e70: 4618 mov r0, r3
8001e72: 3730 adds r7, #48 @ 0x30
8001e74: 46bd mov sp, r7
8001e76: bdb0 pop {r4, r5, r7, pc}
8001e78: 0800fc00 .word 0x0800fc00
08001e7c <Flash_Load_Page>:
/**
* @brief Lê a página da Flash para a RAM.
*/
HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest) {
8001e7c: b580 push {r7, lr}
8001e7e: b082 sub sp, #8
8001e80: af00 add r7, sp, #0
8001e82: 6078 str r0, [r7, #4]
if (pDest == NULL) return HAL_ERROR;
8001e84: 687b ldr r3, [r7, #4]
8001e86: 2b00 cmp r3, #0
8001e88: d101 bne.n 8001e8e <Flash_Load_Page+0x12>
8001e8a: 2301 movs r3, #1
8001e8c: e00d b.n 8001eaa <Flash_Load_Page+0x2e>
// Leitura direta por memcpy (A Flash é mapeada no espaço de endereçamento comum)
memcpy(pDest, (void *)FLASH_PAGE_ADDR, FLASH_PAGE_SIZE);
8001e8e: f44f 6280 mov.w r2, #1024 @ 0x400
8001e92: 4908 ldr r1, [pc, #32] @ (8001eb4 <Flash_Load_Page+0x38>)
8001e94: 6878 ldr r0, [r7, #4]
8001e96: f004 f9f9 bl 800628c <memcpy>
// Validação da integridade através do Magic Number
if (pDest->magic_number != 0xDEADBEEF) {
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 681b ldr r3, [r3, #0]
8001e9e: 4a06 ldr r2, [pc, #24] @ (8001eb8 <Flash_Load_Page+0x3c>)
8001ea0: 4293 cmp r3, r2
8001ea2: d001 beq.n 8001ea8 <Flash_Load_Page+0x2c>
return HAL_ERROR;
8001ea4: 2301 movs r3, #1
8001ea6: e000 b.n 8001eaa <Flash_Load_Page+0x2e>
}
return HAL_OK;
8001ea8: 2300 movs r3, #0
}
8001eaa: 4618 mov r0, r3
8001eac: 3708 adds r7, #8
8001eae: 46bd mov sp, r7
8001eb0: bd80 pop {r7, pc}
8001eb2: bf00 nop
8001eb4: 0800fc00 .word 0x0800fc00
8001eb8: deadbeef .word 0xdeadbeef
08001ebc <MX_GPIO_Init>:
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
8001ebc: b580 push {r7, lr}
8001ebe: b088 sub sp, #32
8001ec0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001ec2: f107 0310 add.w r3, r7, #16
8001ec6: 2200 movs r2, #0
8001ec8: 601a str r2, [r3, #0]
8001eca: 605a str r2, [r3, #4]
8001ecc: 609a str r2, [r3, #8]
8001ece: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ed0: 4b46 ldr r3, [pc, #280] @ (8001fec <MX_GPIO_Init+0x130>)
8001ed2: 699b ldr r3, [r3, #24]
8001ed4: 4a45 ldr r2, [pc, #276] @ (8001fec <MX_GPIO_Init+0x130>)
8001ed6: f043 0310 orr.w r3, r3, #16
8001eda: 6193 str r3, [r2, #24]
8001edc: 4b43 ldr r3, [pc, #268] @ (8001fec <MX_GPIO_Init+0x130>)
8001ede: 699b ldr r3, [r3, #24]
8001ee0: f003 0310 and.w r3, r3, #16
8001ee4: 60fb str r3, [r7, #12]
8001ee6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001ee8: 4b40 ldr r3, [pc, #256] @ (8001fec <MX_GPIO_Init+0x130>)
8001eea: 699b ldr r3, [r3, #24]
8001eec: 4a3f ldr r2, [pc, #252] @ (8001fec <MX_GPIO_Init+0x130>)
8001eee: f043 0320 orr.w r3, r3, #32
8001ef2: 6193 str r3, [r2, #24]
8001ef4: 4b3d ldr r3, [pc, #244] @ (8001fec <MX_GPIO_Init+0x130>)
8001ef6: 699b ldr r3, [r3, #24]
8001ef8: f003 0320 and.w r3, r3, #32
8001efc: 60bb str r3, [r7, #8]
8001efe: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001f00: 4b3a ldr r3, [pc, #232] @ (8001fec <MX_GPIO_Init+0x130>)
8001f02: 699b ldr r3, [r3, #24]
8001f04: 4a39 ldr r2, [pc, #228] @ (8001fec <MX_GPIO_Init+0x130>)
8001f06: f043 0304 orr.w r3, r3, #4
8001f0a: 6193 str r3, [r2, #24]
8001f0c: 4b37 ldr r3, [pc, #220] @ (8001fec <MX_GPIO_Init+0x130>)
8001f0e: 699b ldr r3, [r3, #24]
8001f10: f003 0304 and.w r3, r3, #4
8001f14: 607b str r3, [r7, #4]
8001f16: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001f18: 4b34 ldr r3, [pc, #208] @ (8001fec <MX_GPIO_Init+0x130>)
8001f1a: 699b ldr r3, [r3, #24]
8001f1c: 4a33 ldr r2, [pc, #204] @ (8001fec <MX_GPIO_Init+0x130>)
8001f1e: f043 0308 orr.w r3, r3, #8
8001f22: 6193 str r3, [r2, #24]
8001f24: 4b31 ldr r3, [pc, #196] @ (8001fec <MX_GPIO_Init+0x130>)
8001f26: 699b ldr r3, [r3, #24]
8001f28: f003 0308 and.w r3, r3, #8
8001f2c: 603b str r3, [r7, #0]
8001f2e: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
8001f30: 2200 movs r2, #0
8001f32: f44f 4160 mov.w r1, #57344 @ 0xe000
8001f36: 482e ldr r0, [pc, #184] @ (8001ff0 <MX_GPIO_Init+0x134>)
8001f38: f001 fe33 bl 8003ba2 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
8001f3c: 2200 movs r2, #0
8001f3e: f240 3137 movw r1, #823 @ 0x337
8001f42: 482c ldr r0, [pc, #176] @ (8001ff4 <MX_GPIO_Init+0x138>)
8001f44: f001 fe2d bl 8003ba2 <HAL_GPIO_WritePin>
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
8001f48: 2200 movs r2, #0
8001f4a: f44f 5180 mov.w r1, #4096 @ 0x1000
8001f4e: 482a ldr r0, [pc, #168] @ (8001ff8 <MX_GPIO_Init+0x13c>)
8001f50: f001 fe27 bl 8003ba2 <HAL_GPIO_WritePin>
/*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
8001f54: f44f 4360 mov.w r3, #57344 @ 0xe000
8001f58: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001f5a: 2311 movs r3, #17
8001f5c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f5e: 2300 movs r3, #0
8001f60: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f62: 2302 movs r3, #2
8001f64: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001f66: f107 0310 add.w r3, r7, #16
8001f6a: 4619 mov r1, r3
8001f6c: 4820 ldr r0, [pc, #128] @ (8001ff0 <MX_GPIO_Init+0x134>)
8001f6e: f001 fc7d bl 800386c <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
PG_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
8001f72: f648 13fc movw r3, #35324 @ 0x89fc
8001f76: 613b str r3, [r7, #16]
|SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
|PG_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001f78: 2300 movs r3, #0
8001f7a: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001f7c: 2301 movs r3, #1
8001f7e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001f80: f107 0310 add.w r3, r7, #16
8001f84: 4619 mov r1, r3
8001f86: 481c ldr r0, [pc, #112] @ (8001ff8 <MX_GPIO_Init+0x13c>)
8001f88: f001 fc70 bl 800386c <HAL_GPIO_Init>
/*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
8001f8c: f240 3337 movw r3, #823 @ 0x337
8001f90: 613b str r3, [r7, #16]
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001f92: 2311 movs r3, #17
8001f94: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f96: 2300 movs r3, #0
8001f98: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f9a: 2302 movs r3, #2
8001f9c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001f9e: f107 0310 add.w r3, r7, #16
8001fa2: 4619 mov r1, r3
8001fa4: 4813 ldr r0, [pc, #76] @ (8001ff4 <MX_GPIO_Init+0x138>)
8001fa6: f001 fc61 bl 800386c <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin
Calib_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin
8001faa: f24f 0308 movw r3, #61448 @ 0xf008
8001fae: 613b str r3, [r7, #16]
|Calib_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001fb0: 2300 movs r3, #0
8001fb2: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001fb4: 2301 movs r3, #1
8001fb6: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001fb8: f107 0310 add.w r3, r7, #16
8001fbc: 4619 mov r1, r3
8001fbe: 480d ldr r0, [pc, #52] @ (8001ff4 <MX_GPIO_Init+0x138>)
8001fc0: f001 fc54 bl 800386c <HAL_GPIO_Init>
/*Configure GPIO pin : TX_EN_RS485_Pin */
GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
8001fc4: f44f 5380 mov.w r3, #4096 @ 0x1000
8001fc8: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001fca: 2301 movs r3, #1
8001fcc: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001fce: 2300 movs r3, #0
8001fd0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001fd2: 2302 movs r3, #2
8001fd4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
8001fd6: f107 0310 add.w r3, r7, #16
8001fda: 4619 mov r1, r3
8001fdc: 4806 ldr r0, [pc, #24] @ (8001ff8 <MX_GPIO_Init+0x13c>)
8001fde: f001 fc45 bl 800386c <HAL_GPIO_Init>
}
8001fe2: bf00 nop
8001fe4: 3720 adds r7, #32
8001fe6: 46bd mov sp, r7
8001fe8: bd80 pop {r7, pc}
8001fea: bf00 nop
8001fec: 40021000 .word 0x40021000
8001ff0: 40011000 .word 0x40011000
8001ff4: 40010c00 .word 0x40010c00
8001ff8: 40010800 .word 0x40010800
08001ffc <MX_I2C1_Init>:
I2C_HandleTypeDef hi2c1;
I2C_HandleTypeDef hi2c2;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
8001ffc: b580 push {r7, lr}
8001ffe: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8002000: 4b12 ldr r3, [pc, #72] @ (800204c <MX_I2C1_Init+0x50>)
8002002: 4a13 ldr r2, [pc, #76] @ (8002050 <MX_I2C1_Init+0x54>)
8002004: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
8002006: 4b11 ldr r3, [pc, #68] @ (800204c <MX_I2C1_Init+0x50>)
8002008: 4a12 ldr r2, [pc, #72] @ (8002054 <MX_I2C1_Init+0x58>)
800200a: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
800200c: 4b0f ldr r3, [pc, #60] @ (800204c <MX_I2C1_Init+0x50>)
800200e: 2200 movs r2, #0
8002010: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
8002012: 4b0e ldr r3, [pc, #56] @ (800204c <MX_I2C1_Init+0x50>)
8002014: 2200 movs r2, #0
8002016: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8002018: 4b0c ldr r3, [pc, #48] @ (800204c <MX_I2C1_Init+0x50>)
800201a: f44f 4280 mov.w r2, #16384 @ 0x4000
800201e: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8002020: 4b0a ldr r3, [pc, #40] @ (800204c <MX_I2C1_Init+0x50>)
8002022: 2200 movs r2, #0
8002024: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
8002026: 4b09 ldr r3, [pc, #36] @ (800204c <MX_I2C1_Init+0x50>)
8002028: 2200 movs r2, #0
800202a: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
800202c: 4b07 ldr r3, [pc, #28] @ (800204c <MX_I2C1_Init+0x50>)
800202e: 2200 movs r2, #0
8002030: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8002032: 4b06 ldr r3, [pc, #24] @ (800204c <MX_I2C1_Init+0x50>)
8002034: 2200 movs r2, #0
8002036: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8002038: 4804 ldr r0, [pc, #16] @ (800204c <MX_I2C1_Init+0x50>)
800203a: f001 fde3 bl 8003c04 <HAL_I2C_Init>
800203e: 4603 mov r3, r0
8002040: 2b00 cmp r3, #0
8002042: d001 beq.n 8002048 <MX_I2C1_Init+0x4c>
{
Error_Handler();
8002044: f000 fbae bl 80027a4 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8002048: bf00 nop
800204a: bd80 pop {r7, pc}
800204c: 200005ac .word 0x200005ac
8002050: 40005400 .word 0x40005400
8002054: 000186a0 .word 0x000186a0
08002058 <MX_I2C2_Init>:
/* I2C2 init function */
void MX_I2C2_Init(void)
{
8002058: b580 push {r7, lr}
800205a: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
800205c: 4b12 ldr r3, [pc, #72] @ (80020a8 <MX_I2C2_Init+0x50>)
800205e: 4a13 ldr r2, [pc, #76] @ (80020ac <MX_I2C2_Init+0x54>)
8002060: 601a str r2, [r3, #0]
hi2c2.Init.ClockSpeed = 100000;
8002062: 4b11 ldr r3, [pc, #68] @ (80020a8 <MX_I2C2_Init+0x50>)
8002064: 4a12 ldr r2, [pc, #72] @ (80020b0 <MX_I2C2_Init+0x58>)
8002066: 605a str r2, [r3, #4]
hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
8002068: 4b0f ldr r3, [pc, #60] @ (80020a8 <MX_I2C2_Init+0x50>)
800206a: 2200 movs r2, #0
800206c: 609a str r2, [r3, #8]
hi2c2.Init.OwnAddress1 = 0;
800206e: 4b0e ldr r3, [pc, #56] @ (80020a8 <MX_I2C2_Init+0x50>)
8002070: 2200 movs r2, #0
8002072: 60da str r2, [r3, #12]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8002074: 4b0c ldr r3, [pc, #48] @ (80020a8 <MX_I2C2_Init+0x50>)
8002076: f44f 4280 mov.w r2, #16384 @ 0x4000
800207a: 611a str r2, [r3, #16]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800207c: 4b0a ldr r3, [pc, #40] @ (80020a8 <MX_I2C2_Init+0x50>)
800207e: 2200 movs r2, #0
8002080: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2 = 0;
8002082: 4b09 ldr r3, [pc, #36] @ (80020a8 <MX_I2C2_Init+0x50>)
8002084: 2200 movs r2, #0
8002086: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8002088: 4b07 ldr r3, [pc, #28] @ (80020a8 <MX_I2C2_Init+0x50>)
800208a: 2200 movs r2, #0
800208c: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800208e: 4b06 ldr r3, [pc, #24] @ (80020a8 <MX_I2C2_Init+0x50>)
8002090: 2200 movs r2, #0
8002092: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
8002094: 4804 ldr r0, [pc, #16] @ (80020a8 <MX_I2C2_Init+0x50>)
8002096: f001 fdb5 bl 8003c04 <HAL_I2C_Init>
800209a: 4603 mov r3, r0
800209c: 2b00 cmp r3, #0
800209e: d001 beq.n 80020a4 <MX_I2C2_Init+0x4c>
{
Error_Handler();
80020a0: f000 fb80 bl 80027a4 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
80020a4: bf00 nop
80020a6: bd80 pop {r7, pc}
80020a8: 20000600 .word 0x20000600
80020ac: 40005800 .word 0x40005800
80020b0: 000186a0 .word 0x000186a0
080020b4 <HAL_I2C_MspInit>:
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
80020b4: b580 push {r7, lr}
80020b6: b08a sub sp, #40 @ 0x28
80020b8: af00 add r7, sp, #0
80020ba: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80020bc: f107 0318 add.w r3, r7, #24
80020c0: 2200 movs r2, #0
80020c2: 601a str r2, [r3, #0]
80020c4: 605a str r2, [r3, #4]
80020c6: 609a str r2, [r3, #8]
80020c8: 60da str r2, [r3, #12]
if(i2cHandle->Instance==I2C1)
80020ca: 687b ldr r3, [r7, #4]
80020cc: 681b ldr r3, [r3, #0]
80020ce: 4a2b ldr r2, [pc, #172] @ (800217c <HAL_I2C_MspInit+0xc8>)
80020d0: 4293 cmp r3, r2
80020d2: d124 bne.n 800211e <HAL_I2C_MspInit+0x6a>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
80020d4: 4b2a ldr r3, [pc, #168] @ (8002180 <HAL_I2C_MspInit+0xcc>)
80020d6: 699b ldr r3, [r3, #24]
80020d8: 4a29 ldr r2, [pc, #164] @ (8002180 <HAL_I2C_MspInit+0xcc>)
80020da: f043 0308 orr.w r3, r3, #8
80020de: 6193 str r3, [r2, #24]
80020e0: 4b27 ldr r3, [pc, #156] @ (8002180 <HAL_I2C_MspInit+0xcc>)
80020e2: 699b ldr r3, [r3, #24]
80020e4: f003 0308 and.w r3, r3, #8
80020e8: 617b str r3, [r7, #20]
80020ea: 697b ldr r3, [r7, #20]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
80020ec: 23c0 movs r3, #192 @ 0xc0
80020ee: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80020f0: 2312 movs r3, #18
80020f2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80020f4: 2302 movs r3, #2
80020f6: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80020f8: f107 0318 add.w r3, r7, #24
80020fc: 4619 mov r1, r3
80020fe: 4821 ldr r0, [pc, #132] @ (8002184 <HAL_I2C_MspInit+0xd0>)
8002100: f001 fbb4 bl 800386c <HAL_GPIO_Init>
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8002104: 4b1e ldr r3, [pc, #120] @ (8002180 <HAL_I2C_MspInit+0xcc>)
8002106: 69db ldr r3, [r3, #28]
8002108: 4a1d ldr r2, [pc, #116] @ (8002180 <HAL_I2C_MspInit+0xcc>)
800210a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
800210e: 61d3 str r3, [r2, #28]
8002110: 4b1b ldr r3, [pc, #108] @ (8002180 <HAL_I2C_MspInit+0xcc>)
8002112: 69db ldr r3, [r3, #28]
8002114: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002118: 613b str r3, [r7, #16]
800211a: 693b ldr r3, [r7, #16]
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
}
800211c: e029 b.n 8002172 <HAL_I2C_MspInit+0xbe>
else if(i2cHandle->Instance==I2C2)
800211e: 687b ldr r3, [r7, #4]
8002120: 681b ldr r3, [r3, #0]
8002122: 4a19 ldr r2, [pc, #100] @ (8002188 <HAL_I2C_MspInit+0xd4>)
8002124: 4293 cmp r3, r2
8002126: d124 bne.n 8002172 <HAL_I2C_MspInit+0xbe>
__HAL_RCC_GPIOB_CLK_ENABLE();
8002128: 4b15 ldr r3, [pc, #84] @ (8002180 <HAL_I2C_MspInit+0xcc>)
800212a: 699b ldr r3, [r3, #24]
800212c: 4a14 ldr r2, [pc, #80] @ (8002180 <HAL_I2C_MspInit+0xcc>)
800212e: f043 0308 orr.w r3, r3, #8
8002132: 6193 str r3, [r2, #24]
8002134: 4b12 ldr r3, [pc, #72] @ (8002180 <HAL_I2C_MspInit+0xcc>)
8002136: 699b ldr r3, [r3, #24]
8002138: f003 0308 and.w r3, r3, #8
800213c: 60fb str r3, [r7, #12]
800213e: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
8002140: f44f 6340 mov.w r3, #3072 @ 0xc00
8002144: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8002146: 2312 movs r3, #18
8002148: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800214a: 2302 movs r3, #2
800214c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800214e: f107 0318 add.w r3, r7, #24
8002152: 4619 mov r1, r3
8002154: 480b ldr r0, [pc, #44] @ (8002184 <HAL_I2C_MspInit+0xd0>)
8002156: f001 fb89 bl 800386c <HAL_GPIO_Init>
__HAL_RCC_I2C2_CLK_ENABLE();
800215a: 4b09 ldr r3, [pc, #36] @ (8002180 <HAL_I2C_MspInit+0xcc>)
800215c: 69db ldr r3, [r3, #28]
800215e: 4a08 ldr r2, [pc, #32] @ (8002180 <HAL_I2C_MspInit+0xcc>)
8002160: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002164: 61d3 str r3, [r2, #28]
8002166: 4b06 ldr r3, [pc, #24] @ (8002180 <HAL_I2C_MspInit+0xcc>)
8002168: 69db ldr r3, [r3, #28]
800216a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800216e: 60bb str r3, [r7, #8]
8002170: 68bb ldr r3, [r7, #8]
}
8002172: bf00 nop
8002174: 3728 adds r7, #40 @ 0x28
8002176: 46bd mov sp, r7
8002178: bd80 pop {r7, pc}
800217a: bf00 nop
800217c: 40005400 .word 0x40005400
8002180: 40021000 .word 0x40021000
8002184: 40010c00 .word 0x40010c00
8002188: 40005800 .word 0x40005800
0800218c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800218c: b580 push {r7, lr}
800218e: b090 sub sp, #64 @ 0x40
8002190: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
HAL_StatusTypeDef status0,status1;
// Variables to store previous LED states
uint8_t previous_green_state = 0;
8002192: 2300 movs r3, #0
8002194: f887 303f strb.w r3, [r7, #63] @ 0x3f
uint8_t previous_red_state = 0;
8002198: 2300 movs r3, #0
800219a: f887 303e strb.w r3, [r7, #62] @ 0x3e
// Variables for timing
uint32_t previous_millis_green = 0;
800219e: 2300 movs r3, #0
80021a0: 63bb str r3, [r7, #56] @ 0x38
uint32_t previous_millis_red = 0;
80021a2: 2300 movs r3, #0
80021a4: 637b str r3, [r7, #52] @ 0x34
/*! Temporary variables */
uint8_t tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
80021a6: f107 0308 add.w r3, r7, #8
80021aa: 2200 movs r2, #0
80021ac: 601a str r2, [r3, #0]
80021ae: 605a str r2, [r3, #4]
80021b0: 811a strh r2, [r3, #8]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80021b2: f000 fd03 bl 8002bbc <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80021b6: f000 f991 bl 80024dc <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80021ba: f7ff fe7f bl 8001ebc <MX_GPIO_Init>
MX_ADC1_Init();
80021be: f7ff fb65 bl 800188c <MX_ADC1_Init>
MX_ADC2_Init();
80021c2: f7ff fba1 bl 8001908 <MX_ADC2_Init>
MX_I2C1_Init();
80021c6: f7ff ff19 bl 8001ffc <MX_I2C1_Init>
MX_I2C2_Init();
80021ca: f7ff ff45 bl 8002058 <MX_I2C2_Init>
MX_USART1_UART_Init();
80021ce: f000 fc51 bl 8002a74 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
Flash_Load_Page(&flash_data);
80021d2: 48b9 ldr r0, [pc, #740] @ (80024b8 <main+0x32c>)
80021d4: f7ff fe52 bl 8001e7c <Flash_Load_Page>
HAL_TIM_Base_Start(&htim3);
HAL_ADCEx_Calibration_Start(&hadc1);
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2); // Internal Temperature conversion
*/
digital_outputs_init();
80021d8: f7ff fdb4 bl 8001d44 <digital_outputs_init>
// Initialize RS-485 driver
rs485_init();
80021dc: f000 faf4 bl 80027c8 <rs485_init>
ADS1015(&i2c, &hi2c1, ADS_ADDR_GND);
80021e0: 2248 movs r2, #72 @ 0x48
80021e2: 49b6 ldr r1, [pc, #728] @ (80024bc <main+0x330>)
80021e4: 48b6 ldr r0, [pc, #728] @ (80024c0 <main+0x334>)
80021e6: f7ff fc7e bl 8001ae6 <ADS1015>
ADSsetGain(&i2c, GAIN_SIXTEEN);
80021ea: f44f 6120 mov.w r1, #2560 @ 0xa00
80021ee: 48b4 ldr r0, [pc, #720] @ (80024c0 <main+0x334>)
80021f0: f7ff fc97 bl 8001b22 <ADSsetGain>
// Start CE and RTD Measurement
AD5934_Init();
80021f4: f7fe fed2 bl 8000f9c <AD5934_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
if(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET) // When PB3 (with internal pull up) in the Prog Header is set to GND
80021f8: 2108 movs r1, #8
80021fa: 48b2 ldr r0, [pc, #712] @ (80024c4 <main+0x338>)
80021fc: f001 fcba bl 8003b74 <HAL_GPIO_ReadPin>
8002200: 4603 mov r3, r0
8002202: 2b00 cmp r3, #0
8002204: f040 8091 bne.w 800232a <main+0x19e>
{
main_state = STATE_SETUP_CALIBRATION;
8002208: 4baf ldr r3, [pc, #700] @ (80024c8 <main+0x33c>)
800220a: 2201 movs r2, #1
800220c: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
800220e: 2201 movs r2, #1
8002210: 2110 movs r1, #16
8002212: 48ac ldr r0, [pc, #688] @ (80024c4 <main+0x338>)
8002214: f001 fcc5 bl 8003ba2 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
8002218: 2200 movs r2, #0
800221a: 2120 movs r1, #32
800221c: 48a9 ldr r0, [pc, #676] @ (80024c4 <main+0x338>)
800221e: f001 fcc0 bl 8003ba2 <HAL_GPIO_WritePin>
for(i=0;i<32;i++) // Loop to get stability and get averages
8002222: 2300 movs r3, #0
8002224: f887 3033 strb.w r3, [r7, #51] @ 0x33
8002228: e032 b.n 8002290 <main+0x104>
{
flash_data.ph4_volts = ADSCalculate_ph_Volts();
800222a: f7ff fcc7 bl 8001bbc <ADSCalculate_ph_Volts>
800222e: 4603 mov r3, r0
8002230: 4aa1 ldr r2, [pc, #644] @ (80024b8 <main+0x32c>)
8002232: 6053 str r3, [r2, #4]
flash_data.temperature_value = AD5934_GetTemperature(); // Air Temperature is not stored, just used to calculate impedance
8002234: f7fe ff0e bl 8001054 <AD5934_GetTemperature>
8002238: 4603 mov r3, r0
800223a: 4a9f ldr r2, [pc, #636] @ (80024b8 <main+0x32c>)
800223c: 6153 str r3, [r2, #20]
flash_data.ec0_mag = AD5934_GetImpedance(flash_data.temperature_value); // Dry Probe
800223e: 4b9e ldr r3, [pc, #632] @ (80024b8 <main+0x32c>)
8002240: 695b ldr r3, [r3, #20]
8002242: 4618 mov r0, r3
8002244: f7ff f902 bl 800144c <AD5934_GetImpedance>
8002248: 4603 mov r3, r0
800224a: 4a9b ldr r2, [pc, #620] @ (80024b8 <main+0x32c>)
800224c: 6113 str r3, [r2, #16]
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET)
800224e: 2140 movs r1, #64 @ 0x40
8002250: 489e ldr r0, [pc, #632] @ (80024cc <main+0x340>)
8002252: f001 fc8f bl 8003b74 <HAL_GPIO_ReadPin>
8002256: 4603 mov r3, r0
8002258: 2b01 cmp r3, #1
800225a: d103 bne.n 8002264 <main+0xd8>
flash_data.EC10mS_EC5mS_switch = AD5934_CH_EC_HIGH_GAIN; // 5mS/cm option
800225c: 4b96 ldr r3, [pc, #600] @ (80024b8 <main+0x32c>)
800225e: 2284 movs r2, #132 @ 0x84
8002260: 765a strb r2, [r3, #25]
8002262: e002 b.n 800226a <main+0xde>
else
flash_data.EC10mS_EC5mS_switch = AD5934_CH_EC_MID_GAIN; //10ms/cm option
8002264: 4b94 ldr r3, [pc, #592] @ (80024b8 <main+0x32c>)
8002266: 2282 movs r2, #130 @ 0x82
8002268: 765a strb r2, [r3, #25]
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET)
800226a: 2180 movs r1, #128 @ 0x80
800226c: 4897 ldr r0, [pc, #604] @ (80024cc <main+0x340>)
800226e: f001 fc81 bl 8003b74 <HAL_GPIO_ReadPin>
8002272: 4603 mov r3, r0
8002274: 2b01 cmp r3, #1
8002276: d103 bne.n 8002280 <main+0xf4>
flash_data.PT100_PT1000_switch = AD5934_CH_RTD_LOW_GAIN; //PT100 option
8002278: 4b8f ldr r3, [pc, #572] @ (80024b8 <main+0x32c>)
800227a: 2241 movs r2, #65 @ 0x41
800227c: 761a strb r2, [r3, #24]
800227e: e002 b.n 8002286 <main+0xfa>
else
flash_data.PT100_PT1000_switch = AD5934_CH_RTD_MID_GAIN; //PT1000 option
8002280: 4b8d ldr r3, [pc, #564] @ (80024b8 <main+0x32c>)
8002282: 2242 movs r2, #66 @ 0x42
8002284: 761a strb r2, [r3, #24]
for(i=0;i<32;i++) // Loop to get stability and get averages
8002286: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
800228a: 3301 adds r3, #1
800228c: f887 3033 strb.w r3, [r7, #51] @ 0x33
8002290: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8002294: 2b1f cmp r3, #31
8002296: d9c8 bls.n 800222a <main+0x9e>
}
while(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET);
8002298: bf00 nop
800229a: 2108 movs r1, #8
800229c: 4889 ldr r0, [pc, #548] @ (80024c4 <main+0x338>)
800229e: f001 fc69 bl 8003b74 <HAL_GPIO_ReadPin>
80022a2: 4603 mov r3, r0
80022a4: 2b00 cmp r3, #0
80022a6: d0f8 beq.n 800229a <main+0x10e>
HAL_Delay(500);
80022a8: f44f 70fa mov.w r0, #500 @ 0x1f4
80022ac: f000 fce8 bl 8002c80 <HAL_Delay>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
80022b0: 2200 movs r2, #0
80022b2: 2110 movs r1, #16
80022b4: 4883 ldr r0, [pc, #524] @ (80024c4 <main+0x338>)
80022b6: f001 fc74 bl 8003ba2 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
80022ba: 2201 movs r2, #1
80022bc: 2120 movs r1, #32
80022be: 4881 ldr r0, [pc, #516] @ (80024c4 <main+0x338>)
80022c0: f001 fc6f bl 8003ba2 <HAL_GPIO_WritePin>
for(i=0;i<32;i++) // Loop to get stability and get averages
80022c4: 2300 movs r3, #0
80022c6: f887 3033 strb.w r3, [r7, #51] @ 0x33
80022ca: e019 b.n 8002300 <main+0x174>
{
flash_data.temperature_value = AD5934_GetTemperature(); // Liquid Temperature is stored
80022cc: f7fe fec2 bl 8001054 <AD5934_GetTemperature>
80022d0: 4603 mov r3, r0
80022d2: 4a79 ldr r2, [pc, #484] @ (80024b8 <main+0x32c>)
80022d4: 6153 str r3, [r2, #20]
flash_data.ph7_volts = ADSCalculate_ph_Volts();
80022d6: f7ff fc71 bl 8001bbc <ADSCalculate_ph_Volts>
80022da: 4603 mov r3, r0
80022dc: 4a76 ldr r2, [pc, #472] @ (80024b8 <main+0x32c>)
80022de: 6093 str r3, [r2, #8]
flash_data.ec1413_mag = AD5934_GetImpedance(flash_data.temperature_value); // Get the impedance of the reference liquid
80022e0: 4b75 ldr r3, [pc, #468] @ (80024b8 <main+0x32c>)
80022e2: 695b ldr r3, [r3, #20]
80022e4: 4618 mov r0, r3
80022e6: f7ff f8b1 bl 800144c <AD5934_GetImpedance>
80022ea: 4603 mov r3, r0
80022ec: 4a72 ldr r2, [pc, #456] @ (80024b8 <main+0x32c>)
80022ee: 60d3 str r3, [r2, #12]
Flash_Save_Page(&flash_data); // Store Calibration parameters in Flash
80022f0: 4871 ldr r0, [pc, #452] @ (80024b8 <main+0x32c>)
80022f2: f7ff fd69 bl 8001dc8 <Flash_Save_Page>
for(i=0;i<32;i++) // Loop to get stability and get averages
80022f6: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80022fa: 3301 adds r3, #1
80022fc: f887 3033 strb.w r3, [r7, #51] @ 0x33
8002300: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8002304: 2b1f cmp r3, #31
8002306: d9e1 bls.n 80022cc <main+0x140>
}
HAL_Delay(500);
8002308: f44f 70fa mov.w r0, #500 @ 0x1f4
800230c: f000 fcb8 bl 8002c80 <HAL_Delay>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
8002310: 2200 movs r2, #0
8002312: 2110 movs r1, #16
8002314: 486b ldr r0, [pc, #428] @ (80024c4 <main+0x338>)
8002316: f001 fc44 bl 8003ba2 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
800231a: 2200 movs r2, #0
800231c: 2120 movs r1, #32
800231e: 4869 ldr r0, [pc, #420] @ (80024c4 <main+0x338>)
8002320: f001 fc3f bl 8003ba2 <HAL_GPIO_WritePin>
main_state = STATE_RUNNING_OK;
8002324: 4b68 ldr r3, [pc, #416] @ (80024c8 <main+0x33c>)
8002326: 2200 movs r2, #0
8002328: 701a strb r2, [r3, #0]
{
current_millis = HAL_GetTick();
800232a: f000 fc9f bl 8002c6c <HAL_GetTick>
800232e: 62f8 str r0, [r7, #44] @ 0x2c
// Piscar LED verde em PB5 a cada 0,5 segundos
if ((current_millis - previous_millis_green) >= 500)
8002330: 6afa ldr r2, [r7, #44] @ 0x2c
8002332: 6bbb ldr r3, [r7, #56] @ 0x38
8002334: 1ad3 subs r3, r2, r3
8002336: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
800233a: d372 bcc.n 8002422 <main+0x296>
{
previous_millis_green = current_millis;
800233c: 6afb ldr r3, [r7, #44] @ 0x2c
800233e: 63bb str r3, [r7, #56] @ 0x38
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_5);
8002340: 2120 movs r1, #32
8002342: 4860 ldr r0, [pc, #384] @ (80024c4 <main+0x338>)
8002344: f001 fc45 bl 8003bd2 <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_green_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_5);
8002348: 2120 movs r1, #32
800234a: 485e ldr r0, [pc, #376] @ (80024c4 <main+0x338>)
800234c: f001 fc12 bl 8003b74 <HAL_GPIO_ReadPin>
8002350: 4603 mov r3, r0
8002352: f887 302b strb.w r3, [r7, #43] @ 0x2b
if (current_green_state != previous_green_state)
8002356: f897 202b ldrb.w r2, [r7, #43] @ 0x2b
800235a: f897 303f ldrb.w r3, [r7, #63] @ 0x3f
800235e: 429a cmp r2, r3
8002360: d008 beq.n 8002374 <main+0x1e8>
{
previous_green_state = current_green_state;
8002362: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8002366: f887 303f strb.w r3, [r7, #63] @ 0x3f
uint8_t led_data[2] = {0x01, current_green_state}; // Command 0x01 for green LED
800236a: 2301 movs r3, #1
800236c: 713b strb r3, [r7, #4]
800236e: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8002372: 717b strb r3, [r7, #5]
}
temperature_RTD = AD5934_GetTemperature();
8002374: f7fe fe6e bl 8001054 <AD5934_GetTemperature>
8002378: 6278 str r0, [r7, #36] @ 0x24
FloatToString(tempString, temperature_RTD);
800237a: 6a78 ldr r0, [r7, #36] @ 0x24
800237c: f7fe f97c bl 8000678 <__aeabi_f2d>
8002380: 4602 mov r2, r0
8002382: 460b mov r3, r1
8002384: f107 0108 add.w r1, r7, #8
8002388: 4608 mov r0, r1
800238a: f000 f8f7 bl 800257c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
800238e: f107 0308 add.w r3, r7, #8
8002392: 4618 mov r0, r3
8002394: f7fd feda bl 800014c <strlen>
8002398: 4603 mov r3, r0
800239a: b29b uxth r3, r3
800239c: 3b01 subs r3, #1
800239e: b29a uxth r2, r3
80023a0: f107 0308 add.w r3, r7, #8
80023a4: 4611 mov r1, r2
80023a6: 4618 mov r0, r3
80023a8: f000 fa3a bl 8002820 <rs485_send_broadcast>
80023ac: 4603 mov r3, r0
80023ae: f887 3023 strb.w r3, [r7, #35] @ 0x23
status1 = rs485_send_broadcast(newline_temp, strlen((char*)newline_temp));
80023b2: 4847 ldr r0, [pc, #284] @ (80024d0 <main+0x344>)
80023b4: f7fd feca bl 800014c <strlen>
80023b8: 4603 mov r3, r0
80023ba: b29b uxth r3, r3
80023bc: 4619 mov r1, r3
80023be: 4844 ldr r0, [pc, #272] @ (80024d0 <main+0x344>)
80023c0: f000 fa2e bl 8002820 <rs485_send_broadcast>
80023c4: 4603 mov r3, r0
80023c6: f887 3022 strb.w r3, [r7, #34] @ 0x22
admittance_EC = AD5934_GetImpedance(temperature_RTD);
80023ca: 6a78 ldr r0, [r7, #36] @ 0x24
80023cc: f7ff f83e bl 800144c <AD5934_GetImpedance>
80023d0: 61f8 str r0, [r7, #28]
FloatToString(tempString, admittance_EC);
80023d2: 69f8 ldr r0, [r7, #28]
80023d4: f7fe f950 bl 8000678 <__aeabi_f2d>
80023d8: 4602 mov r2, r0
80023da: 460b mov r3, r1
80023dc: f107 0108 add.w r1, r7, #8
80023e0: 4608 mov r0, r1
80023e2: f000 f8cb bl 800257c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
80023e6: f107 0308 add.w r3, r7, #8
80023ea: 4618 mov r0, r3
80023ec: f7fd feae bl 800014c <strlen>
80023f0: 4603 mov r3, r0
80023f2: b29b uxth r3, r3
80023f4: 3b01 subs r3, #1
80023f6: b29a uxth r2, r3
80023f8: f107 0308 add.w r3, r7, #8
80023fc: 4611 mov r1, r2
80023fe: 4618 mov r0, r3
8002400: f000 fa0e bl 8002820 <rs485_send_broadcast>
8002404: 4603 mov r3, r0
8002406: f887 3023 strb.w r3, [r7, #35] @ 0x23
status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi));
800240a: 4832 ldr r0, [pc, #200] @ (80024d4 <main+0x348>)
800240c: f7fd fe9e bl 800014c <strlen>
8002410: 4603 mov r3, r0
8002412: b29b uxth r3, r3
8002414: 4619 mov r1, r3
8002416: 482f ldr r0, [pc, #188] @ (80024d4 <main+0x348>)
8002418: f000 fa02 bl 8002820 <rs485_send_broadcast>
800241c: 4603 mov r3, r0
800241e: f887 3022 strb.w r3, [r7, #34] @ 0x22
}
// Piscar LED vermelho em PB4 a cada 1 segundo
if ((current_millis - previous_millis_red) >= 1000)
8002422: 6afa ldr r2, [r7, #44] @ 0x2c
8002424: 6b7b ldr r3, [r7, #52] @ 0x34
8002426: 1ad3 subs r3, r2, r3
8002428: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800242c: f4ff af7d bcc.w 800232a <main+0x19e>
{
previous_millis_red = current_millis;
8002430: 6afb ldr r3, [r7, #44] @ 0x2c
8002432: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4);
8002434: 2110 movs r1, #16
8002436: 4823 ldr r0, [pc, #140] @ (80024c4 <main+0x338>)
8002438: f001 fbcb bl 8003bd2 <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_red_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_4);
800243c: 2110 movs r1, #16
800243e: 4821 ldr r0, [pc, #132] @ (80024c4 <main+0x338>)
8002440: f001 fb98 bl 8003b74 <HAL_GPIO_ReadPin>
8002444: 4603 mov r3, r0
8002446: 76fb strb r3, [r7, #27]
if (current_red_state != previous_red_state)
8002448: 7efa ldrb r2, [r7, #27]
800244a: f897 303e ldrb.w r3, [r7, #62] @ 0x3e
800244e: 429a cmp r2, r3
8002450: d006 beq.n 8002460 <main+0x2d4>
{
previous_red_state = current_red_state;
8002452: 7efb ldrb r3, [r7, #27]
8002454: f887 303e strb.w r3, [r7, #62] @ 0x3e
uint8_t led_data[2] = {0x02, current_red_state}; // Command 0x02 for red LED
8002458: 2302 movs r3, #2
800245a: 703b strb r3, [r7, #0]
800245c: 7efb ldrb r3, [r7, #27]
800245e: 707b strb r3, [r7, #1]
}
ph_compensated = ADSCalculate_ph_Uncompensated();
8002460: f7ff fc02 bl 8001c68 <ADSCalculate_ph_Uncompensated>
8002464: 6178 str r0, [r7, #20]
FloatToString(tempString, ph_compensated);
8002466: 6978 ldr r0, [r7, #20]
8002468: f7fe f906 bl 8000678 <__aeabi_f2d>
800246c: 4602 mov r2, r0
800246e: 460b mov r3, r1
8002470: f107 0108 add.w r1, r7, #8
8002474: 4608 mov r0, r1
8002476: f000 f881 bl 800257c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
800247a: f107 0308 add.w r3, r7, #8
800247e: 4618 mov r0, r3
8002480: f7fd fe64 bl 800014c <strlen>
8002484: 4603 mov r3, r0
8002486: b29b uxth r3, r3
8002488: 3b01 subs r3, #1
800248a: b29a uxth r2, r3
800248c: f107 0308 add.w r3, r7, #8
8002490: 4611 mov r1, r2
8002492: 4618 mov r0, r3
8002494: f000 f9c4 bl 8002820 <rs485_send_broadcast>
8002498: 4603 mov r3, r0
800249a: f887 3023 strb.w r3, [r7, #35] @ 0x23
status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph));
800249e: 480e ldr r0, [pc, #56] @ (80024d8 <main+0x34c>)
80024a0: f7fd fe54 bl 800014c <strlen>
80024a4: 4603 mov r3, r0
80024a6: b29b uxth r3, r3
80024a8: 4619 mov r1, r3
80024aa: 480b ldr r0, [pc, #44] @ (80024d8 <main+0x34c>)
80024ac: f000 f9b8 bl 8002820 <rs485_send_broadcast>
80024b0: 4603 mov r3, r0
80024b2: f887 3022 strb.w r3, [r7, #34] @ 0x22
current_millis = HAL_GetTick();
80024b6: e738 b.n 800232a <main+0x19e>
80024b8: 200001ac .word 0x200001ac
80024bc: 200005ac .word 0x200005ac
80024c0: 20000174 .word 0x20000174
80024c4: 40010c00 .word 0x40010c00
80024c8: 20000654 .word 0x20000654
80024cc: 40010800 .word 0x40010800
80024d0: 20000010 .word 0x20000010
80024d4: 20000008 .word 0x20000008
80024d8: 20000000 .word 0x20000000
080024dc <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80024dc: b580 push {r7, lr}
80024de: b094 sub sp, #80 @ 0x50
80024e0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80024e2: f107 0328 add.w r3, r7, #40 @ 0x28
80024e6: 2228 movs r2, #40 @ 0x28
80024e8: 2100 movs r1, #0
80024ea: 4618 mov r0, r3
80024ec: f003 fe9c bl 8006228 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80024f0: f107 0314 add.w r3, r7, #20
80024f4: 2200 movs r2, #0
80024f6: 601a str r2, [r3, #0]
80024f8: 605a str r2, [r3, #4]
80024fa: 609a str r2, [r3, #8]
80024fc: 60da str r2, [r3, #12]
80024fe: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8002500: 1d3b adds r3, r7, #4
8002502: 2200 movs r2, #0
8002504: 601a str r2, [r3, #0]
8002506: 605a str r2, [r3, #4]
8002508: 609a str r2, [r3, #8]
800250a: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
800250c: 2301 movs r3, #1
800250e: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8002510: f44f 3380 mov.w r3, #65536 @ 0x10000
8002514: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8002516: 2300 movs r3, #0
8002518: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800251a: f107 0328 add.w r3, r7, #40 @ 0x28
800251e: 4618 mov r0, r3
8002520: f002 fba4 bl 8004c6c <HAL_RCC_OscConfig>
8002524: 4603 mov r3, r0
8002526: 2b00 cmp r3, #0
8002528: d001 beq.n 800252e <SystemClock_Config+0x52>
{
Error_Handler();
800252a: f000 f93b bl 80027a4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800252e: 230f movs r3, #15
8002530: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
8002532: 2301 movs r3, #1
8002534: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8002536: 2300 movs r3, #0
8002538: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800253a: 2300 movs r3, #0
800253c: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800253e: 2300 movs r3, #0
8002540: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8002542: f107 0314 add.w r3, r7, #20
8002546: 2100 movs r1, #0
8002548: 4618 mov r0, r3
800254a: f002 fe11 bl 8005170 <HAL_RCC_ClockConfig>
800254e: 4603 mov r3, r0
8002550: 2b00 cmp r3, #0
8002552: d001 beq.n 8002558 <SystemClock_Config+0x7c>
{
Error_Handler();
8002554: f000 f926 bl 80027a4 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
8002558: 2302 movs r3, #2
800255a: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
800255c: f44f 4340 mov.w r3, #49152 @ 0xc000
8002560: 60fb str r3, [r7, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002562: 1d3b adds r3, r7, #4
8002564: 4618 mov r0, r3
8002566: f002 ff93 bl 8005490 <HAL_RCCEx_PeriphCLKConfig>
800256a: 4603 mov r3, r0
800256c: 2b00 cmp r3, #0
800256e: d001 beq.n 8002574 <SystemClock_Config+0x98>
{
Error_Handler();
8002570: f000 f918 bl 80027a4 <Error_Handler>
}
}
8002574: bf00 nop
8002576: 3750 adds r7, #80 @ 0x50
8002578: 46bd mov sp, r7
800257a: bd80 pop {r7, pc}
0800257c <FloatToString>:
* @param val - value to be converted
*
* @return None.
*******************************************************************************/
void FloatToString(char *buf, double val)
{
800257c: b5b0 push {r4, r5, r7, lr}
800257e: b096 sub sp, #88 @ 0x58
8002580: af00 add r7, sp, #0
8002582: 60f8 str r0, [r7, #12]
8002584: e9c7 2300 strd r2, r3, [r7]
char temp[20]; // Buffer auxiliar para construção segura
int i = 0;
8002588: 2300 movs r3, #0
800258a: 657b str r3, [r7, #84] @ 0x54
// 1. Tratar sinal negativo
if (val < 0) {
800258c: f04f 0200 mov.w r2, #0
8002590: f04f 0300 mov.w r3, #0
8002594: e9d7 0100 ldrd r0, r1, [r7]
8002598: f7fe f926 bl 80007e8 <__aeabi_dcmplt>
800259c: 4603 mov r3, r0
800259e: 2b00 cmp r3, #0
80025a0: d00d beq.n 80025be <FloatToString+0x42>
temp[i++] = '-';
80025a2: 6d7b ldr r3, [r7, #84] @ 0x54
80025a4: 1c5a adds r2, r3, #1
80025a6: 657a str r2, [r7, #84] @ 0x54
80025a8: 3358 adds r3, #88 @ 0x58
80025aa: 443b add r3, r7
80025ac: 222d movs r2, #45 @ 0x2d
80025ae: f803 2c30 strb.w r2, [r3, #-48]
val = -val;
80025b2: 683c ldr r4, [r7, #0]
80025b4: 687b ldr r3, [r7, #4]
80025b6: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000
80025ba: e9c7 4500 strd r4, r5, [r7]
}
// 2. Separar parte inteira e fracionária
long intPart = (long)val;
80025be: e9d7 0100 ldrd r0, r1, [r7]
80025c2: f7fe f939 bl 8000838 <__aeabi_d2iz>
80025c6: 4603 mov r3, r0
80025c8: 653b str r3, [r7, #80] @ 0x50
// Multiplicamos por 1000 para obter 3 casas decimais fixas
int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
80025ca: 6d38 ldr r0, [r7, #80] @ 0x50
80025cc: f7fe f842 bl 8000654 <__aeabi_i2d>
80025d0: 4602 mov r2, r0
80025d2: 460b mov r3, r1
80025d4: e9d7 0100 ldrd r0, r1, [r7]
80025d8: f7fd feee bl 80003b8 <__aeabi_dsub>
80025dc: 4602 mov r2, r0
80025de: 460b mov r3, r1
80025e0: 4610 mov r0, r2
80025e2: 4619 mov r1, r3
80025e4: f04f 0200 mov.w r2, #0
80025e8: 4b6a ldr r3, [pc, #424] @ (8002794 <FloatToString+0x218>)
80025ea: f7fd fdb7 bl 800015c <__aeabi_dmul>
80025ee: 4602 mov r2, r0
80025f0: 460b mov r3, r1
80025f2: 4610 mov r0, r2
80025f4: 4619 mov r1, r3
80025f6: f04f 0200 mov.w r2, #0
80025fa: 4b67 ldr r3, [pc, #412] @ (8002798 <FloatToString+0x21c>)
80025fc: f7fd fede bl 80003bc <__adddf3>
8002600: 4602 mov r2, r0
8002602: 460b mov r3, r1
8002604: 4610 mov r0, r2
8002606: 4619 mov r1, r3
8002608: f7fe f916 bl 8000838 <__aeabi_d2iz>
800260c: 4603 mov r3, r0
800260e: 63fb str r3, [r7, #60] @ 0x3c
// 3. Converter a parte inteira para o buffer temp
// Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
char intRev[12];
int j = 0;
8002610: 2300 movs r3, #0
8002612: 64fb str r3, [r7, #76] @ 0x4c
if (intPart == 0) {
8002614: 6d3b ldr r3, [r7, #80] @ 0x50
8002616: 2b00 cmp r3, #0
8002618: d126 bne.n 8002668 <FloatToString+0xec>
intRev[j++] = '0';
800261a: 6cfb ldr r3, [r7, #76] @ 0x4c
800261c: 1c5a adds r2, r3, #1
800261e: 64fa str r2, [r7, #76] @ 0x4c
8002620: 3358 adds r3, #88 @ 0x58
8002622: 443b add r3, r7
8002624: 2230 movs r2, #48 @ 0x30
8002626: f803 2c3c strb.w r2, [r3, #-60]
800262a: e020 b.n 800266e <FloatToString+0xf2>
} else {
while (intPart > 0) {
intRev[j++] = (intPart % 10) + '0';
800262c: 6d3a ldr r2, [r7, #80] @ 0x50
800262e: 4b5b ldr r3, [pc, #364] @ (800279c <FloatToString+0x220>)
8002630: fb83 1302 smull r1, r3, r3, r2
8002634: 1099 asrs r1, r3, #2
8002636: 17d3 asrs r3, r2, #31
8002638: 1ac9 subs r1, r1, r3
800263a: 460b mov r3, r1
800263c: 009b lsls r3, r3, #2
800263e: 440b add r3, r1
8002640: 005b lsls r3, r3, #1
8002642: 1ad1 subs r1, r2, r3
8002644: b2ca uxtb r2, r1
8002646: 6cfb ldr r3, [r7, #76] @ 0x4c
8002648: 1c59 adds r1, r3, #1
800264a: 64f9 str r1, [r7, #76] @ 0x4c
800264c: 3230 adds r2, #48 @ 0x30
800264e: b2d2 uxtb r2, r2
8002650: 3358 adds r3, #88 @ 0x58
8002652: 443b add r3, r7
8002654: f803 2c3c strb.w r2, [r3, #-60]
intPart /= 10;
8002658: 6d3b ldr r3, [r7, #80] @ 0x50
800265a: 4a50 ldr r2, [pc, #320] @ (800279c <FloatToString+0x220>)
800265c: fb82 1203 smull r1, r2, r2, r3
8002660: 1092 asrs r2, r2, #2
8002662: 17db asrs r3, r3, #31
8002664: 1ad3 subs r3, r2, r3
8002666: 653b str r3, [r7, #80] @ 0x50
while (intPart > 0) {
8002668: 6d3b ldr r3, [r7, #80] @ 0x50
800266a: 2b00 cmp r3, #0
800266c: dcde bgt.n 800262c <FloatToString+0xb0>
}
}
// Inverter a parte inteira de volta para o buffer principal
for (int k = j - 1; k >= 0; k--) {
800266e: 6cfb ldr r3, [r7, #76] @ 0x4c
8002670: 3b01 subs r3, #1
8002672: 64bb str r3, [r7, #72] @ 0x48
8002674: e00e b.n 8002694 <FloatToString+0x118>
temp[i++] = intRev[k];
8002676: 6d7b ldr r3, [r7, #84] @ 0x54
8002678: 1c5a adds r2, r3, #1
800267a: 657a str r2, [r7, #84] @ 0x54
800267c: f107 011c add.w r1, r7, #28
8002680: 6cba ldr r2, [r7, #72] @ 0x48
8002682: 440a add r2, r1
8002684: 7812 ldrb r2, [r2, #0]
8002686: 3358 adds r3, #88 @ 0x58
8002688: 443b add r3, r7
800268a: f803 2c30 strb.w r2, [r3, #-48]
for (int k = j - 1; k >= 0; k--) {
800268e: 6cbb ldr r3, [r7, #72] @ 0x48
8002690: 3b01 subs r3, #1
8002692: 64bb str r3, [r7, #72] @ 0x48
8002694: 6cbb ldr r3, [r7, #72] @ 0x48
8002696: 2b00 cmp r3, #0
8002698: daed bge.n 8002676 <FloatToString+0xfa>
}
// 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
temp[i++] = '.';
800269a: 6d7b ldr r3, [r7, #84] @ 0x54
800269c: 1c5a adds r2, r3, #1
800269e: 657a str r2, [r7, #84] @ 0x54
80026a0: 3358 adds r3, #88 @ 0x58
80026a2: 443b add r3, r7
80026a4: 222e movs r2, #46 @ 0x2e
80026a6: f803 2c30 strb.w r2, [r3, #-48]
// Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
int fracBuffer[3];
fracBuffer[2] = fracPart % 10; // Unidade
80026aa: 6bf9 ldr r1, [r7, #60] @ 0x3c
80026ac: 4b3b ldr r3, [pc, #236] @ (800279c <FloatToString+0x220>)
80026ae: fb83 2301 smull r2, r3, r3, r1
80026b2: 109a asrs r2, r3, #2
80026b4: 17cb asrs r3, r1, #31
80026b6: 1ad2 subs r2, r2, r3
80026b8: 4613 mov r3, r2
80026ba: 009b lsls r3, r3, #2
80026bc: 4413 add r3, r2
80026be: 005b lsls r3, r3, #1
80026c0: 1aca subs r2, r1, r3
80026c2: 61ba str r2, [r7, #24]
fracBuffer[1] = (fracPart / 10) % 10; // Dezena
80026c4: 6bfb ldr r3, [r7, #60] @ 0x3c
80026c6: 4a35 ldr r2, [pc, #212] @ (800279c <FloatToString+0x220>)
80026c8: fb82 1203 smull r1, r2, r2, r3
80026cc: 1092 asrs r2, r2, #2
80026ce: 17db asrs r3, r3, #31
80026d0: 1ad1 subs r1, r2, r3
80026d2: 4b32 ldr r3, [pc, #200] @ (800279c <FloatToString+0x220>)
80026d4: fb83 2301 smull r2, r3, r3, r1
80026d8: 109a asrs r2, r3, #2
80026da: 17cb asrs r3, r1, #31
80026dc: 1ad2 subs r2, r2, r3
80026de: 4613 mov r3, r2
80026e0: 009b lsls r3, r3, #2
80026e2: 4413 add r3, r2
80026e4: 005b lsls r3, r3, #1
80026e6: 1aca subs r2, r1, r3
80026e8: 617a str r2, [r7, #20]
fracBuffer[0] = (fracPart / 100) % 10; // Centena
80026ea: 6bfb ldr r3, [r7, #60] @ 0x3c
80026ec: 4a2c ldr r2, [pc, #176] @ (80027a0 <FloatToString+0x224>)
80026ee: fb82 1203 smull r1, r2, r2, r3
80026f2: 1152 asrs r2, r2, #5
80026f4: 17db asrs r3, r3, #31
80026f6: 1ad1 subs r1, r2, r3
80026f8: 4b28 ldr r3, [pc, #160] @ (800279c <FloatToString+0x220>)
80026fa: fb83 2301 smull r2, r3, r3, r1
80026fe: 109a asrs r2, r3, #2
8002700: 17cb asrs r3, r1, #31
8002702: 1ad2 subs r2, r2, r3
8002704: 4613 mov r3, r2
8002706: 009b lsls r3, r3, #2
8002708: 4413 add r3, r2
800270a: 005b lsls r3, r3, #1
800270c: 1aca subs r2, r1, r3
800270e: 613a str r2, [r7, #16]
for (int k = 2; k >= 0; k--) {
8002710: 2302 movs r3, #2
8002712: 647b str r3, [r7, #68] @ 0x44
8002714: e012 b.n 800273c <FloatToString+0x1c0>
temp[i++] = fracBuffer[k] + '0';
8002716: 6c7b ldr r3, [r7, #68] @ 0x44
8002718: 009b lsls r3, r3, #2
800271a: 3358 adds r3, #88 @ 0x58
800271c: 443b add r3, r7
800271e: f853 3c48 ldr.w r3, [r3, #-72]
8002722: b2da uxtb r2, r3
8002724: 6d7b ldr r3, [r7, #84] @ 0x54
8002726: 1c59 adds r1, r3, #1
8002728: 6579 str r1, [r7, #84] @ 0x54
800272a: 3230 adds r2, #48 @ 0x30
800272c: b2d2 uxtb r2, r2
800272e: 3358 adds r3, #88 @ 0x58
8002730: 443b add r3, r7
8002732: f803 2c30 strb.w r2, [r3, #-48]
for (int k = 2; k >= 0; k--) {
8002736: 6c7b ldr r3, [r7, #68] @ 0x44
8002738: 3b01 subs r3, #1
800273a: 647b str r3, [r7, #68] @ 0x44
800273c: 6c7b ldr r3, [r7, #68] @ 0x44
800273e: 2b00 cmp r3, #0
8002740: dae9 bge.n 8002716 <FloatToString+0x19a>
}
// 5. Finalizar a string com o caractere nulo
temp[i] = '\0';
8002742: f107 0228 add.w r2, r7, #40 @ 0x28
8002746: 6d7b ldr r3, [r7, #84] @ 0x54
8002748: 4413 add r3, r2
800274a: 2200 movs r2, #0
800274c: 701a strb r2, [r3, #0]
// 6. Copiar para o buffer de destino final (sem risco de lixo)
int destIdx = 0;
800274e: 2300 movs r3, #0
8002750: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
8002752: e00b b.n 800276c <FloatToString+0x1f0>
buf[destIdx] = temp[destIdx];
8002754: 6c3b ldr r3, [r7, #64] @ 0x40
8002756: 68fa ldr r2, [r7, #12]
8002758: 4413 add r3, r2
800275a: f107 0128 add.w r1, r7, #40 @ 0x28
800275e: 6c3a ldr r2, [r7, #64] @ 0x40
8002760: 440a add r2, r1
8002762: 7812 ldrb r2, [r2, #0]
8002764: 701a strb r2, [r3, #0]
destIdx++;
8002766: 6c3b ldr r3, [r7, #64] @ 0x40
8002768: 3301 adds r3, #1
800276a: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
800276c: f107 0228 add.w r2, r7, #40 @ 0x28
8002770: 6c3b ldr r3, [r7, #64] @ 0x40
8002772: 4413 add r3, r2
8002774: 781b ldrb r3, [r3, #0]
8002776: 2b00 cmp r3, #0
8002778: d002 beq.n 8002780 <FloatToString+0x204>
800277a: 6c3b ldr r3, [r7, #64] @ 0x40
800277c: 2b0e cmp r3, #14
800277e: dde9 ble.n 8002754 <FloatToString+0x1d8>
}
buf[destIdx] = '\0';
8002780: 6c3b ldr r3, [r7, #64] @ 0x40
8002782: 68fa ldr r2, [r7, #12]
8002784: 4413 add r3, r2
8002786: 2200 movs r2, #0
8002788: 701a strb r2, [r3, #0]
}
800278a: bf00 nop
800278c: 3758 adds r7, #88 @ 0x58
800278e: 46bd mov sp, r7
8002790: bdb0 pop {r4, r5, r7, pc}
8002792: bf00 nop
8002794: 408f4000 .word 0x408f4000
8002798: 3fe00000 .word 0x3fe00000
800279c: 66666667 .word 0x66666667
80027a0: 51eb851f .word 0x51eb851f
080027a4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80027a4: b480 push {r7}
80027a6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80027a8: b672 cpsid i
}
80027aa: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80027ac: bf00 nop
80027ae: e7fd b.n 80027ac <Error_Handler+0x8>
080027b0 <LL_GPIO_ReadInputPort>:
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
80027b0: b480 push {r7}
80027b2: b083 sub sp, #12
80027b4: af00 add r7, sp, #0
80027b6: 6078 str r0, [r7, #4]
return (READ_REG(GPIOx->IDR));
80027b8: 687b ldr r3, [r7, #4]
80027ba: 689b ldr r3, [r3, #8]
}
80027bc: 4618 mov r0, r3
80027be: 370c adds r7, #12
80027c0: 46bd mov sp, r7
80027c2: bc80 pop {r7}
80027c4: 4770 bx lr
...
080027c8 <rs485_init>:
/**
* @brief Initializes the RS-485 driver.
* @note This function configures GPIOs for address detection and USART1 for communication.
*/
void rs485_init(void)
{
80027c8: b580 push {r7, lr}
80027ca: af00 add r7, sp, #0
/* Configure GPIOs for address detection */
rs485_configure_gpio_address();
80027cc: f000 f864 bl 8002898 <rs485_configure_gpio_address>
/* Configure USART1 for RS-485 communication */
rs485_configure_usart1();
80027d0: f000 f8a8 bl 8002924 <rs485_configure_usart1>
/* Get the current device address from GPIOs */
device_address.full_address = rs485_get_address();
80027d4: f000 f808 bl 80027e8 <rs485_get_address>
80027d8: 4603 mov r3, r0
80027da: 461a mov r2, r3
80027dc: 4b01 ldr r3, [pc, #4] @ (80027e4 <rs485_init+0x1c>)
80027de: 709a strb r2, [r3, #2]
}
80027e0: bf00 nop
80027e2: bd80 pop {r7, pc}
80027e4: 20000658 .word 0x20000658
080027e8 <rs485_get_address>:
/**
* @brief Gets the current device address from GPIOs.
* @return The 8-bit device address.
*/
uint8_t rs485_get_address(void)
{
80027e8: b598 push {r3, r4, r7, lr}
80027ea: af00 add r7, sp, #0
return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
80027ec: 480a ldr r0, [pc, #40] @ (8002818 <rs485_get_address+0x30>)
80027ee: f7ff ffdf bl 80027b0 <LL_GPIO_ReadInputPort>
80027f2: 4603 mov r3, r0
80027f4: 0a1b lsrs r3, r3, #8
80027f6: b2db uxtb r3, r3
80027f8: f023 030f bic.w r3, r3, #15
80027fc: b2dc uxtb r4, r3
80027fe: 4807 ldr r0, [pc, #28] @ (800281c <rs485_get_address+0x34>)
8002800: f7ff ffd6 bl 80027b0 <LL_GPIO_ReadInputPort>
8002804: 4603 mov r3, r0
8002806: 089b lsrs r3, r3, #2
8002808: b2db uxtb r3, r3
800280a: f003 030f and.w r3, r3, #15
800280e: b2db uxtb r3, r3
8002810: 4323 orrs r3, r4
8002812: b2db uxtb r3, r3
}
8002814: 4618 mov r0, r3
8002816: bd98 pop {r3, r4, r7, pc}
8002818: 40010c00 .word 0x40010c00
800281c: 40010800 .word 0x40010800
08002820 <rs485_send_broadcast>:
* @param data Pointer to the data buffer.
* @param length Number of bytes to send.
* @retval HAL_OK on success, otherwise error code.
*/
HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
{
8002820: b580 push {r7, lr}
8002822: b084 sub sp, #16
8002824: af00 add r7, sp, #0
8002826: 6078 str r0, [r7, #4]
8002828: 460b mov r3, r1
800282a: 807b strh r3, [r7, #2]
/* Enable transmission mode */
rs485_enable_tx();
800282c: f000 f81c bl 8002868 <rs485_enable_tx>
/* Send the broadcast address (0x00) first */
uint8_t broadcast_address = 0x00;
8002830: 2300 movs r3, #0
8002832: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
8002834: f107 010e add.w r1, r7, #14
8002838: f04f 33ff mov.w r3, #4294967295
800283c: 2201 movs r2, #1
800283e: 4809 ldr r0, [pc, #36] @ (8002864 <rs485_send_broadcast+0x44>)
8002840: f002 ff2c bl 800569c <HAL_UART_Transmit>
/* Send the data */
HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
8002844: 887a ldrh r2, [r7, #2]
8002846: f04f 33ff mov.w r3, #4294967295
800284a: 6879 ldr r1, [r7, #4]
800284c: 4805 ldr r0, [pc, #20] @ (8002864 <rs485_send_broadcast+0x44>)
800284e: f002 ff25 bl 800569c <HAL_UART_Transmit>
8002852: 4603 mov r3, r0
8002854: 73fb strb r3, [r7, #15]
/* Disable transmission mode after sending */
rs485_disable_tx();
8002856: f000 f813 bl 8002880 <rs485_disable_tx>
return status;
800285a: 7bfb ldrb r3, [r7, #15]
}
800285c: 4618 mov r0, r3
800285e: 3710 adds r7, #16
8002860: 46bd mov sp, r7
8002862: bd80 pop {r7, pc}
8002864: 2000065c .word 0x2000065c
08002868 <rs485_enable_tx>:
/**
* @brief Enables transmission mode on RS-485 transceiver.
*/
void rs485_enable_tx(void)
{
8002868: b580 push {r7, lr}
800286a: af00 add r7, sp, #0
/* Set TX EN pin high to enable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
800286c: 2201 movs r2, #1
800286e: f44f 5180 mov.w r1, #4096 @ 0x1000
8002872: 4802 ldr r0, [pc, #8] @ (800287c <rs485_enable_tx+0x14>)
8002874: f001 f995 bl 8003ba2 <HAL_GPIO_WritePin>
}
8002878: bf00 nop
800287a: bd80 pop {r7, pc}
800287c: 40010800 .word 0x40010800
08002880 <rs485_disable_tx>:
/**
* @brief Disables transmission mode on RS-485 transceiver.
*/
void rs485_disable_tx(void)
{
8002880: b580 push {r7, lr}
8002882: af00 add r7, sp, #0
/* Set TX EN pin low to disable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
8002884: 2200 movs r2, #0
8002886: f44f 5180 mov.w r1, #4096 @ 0x1000
800288a: 4802 ldr r0, [pc, #8] @ (8002894 <rs485_disable_tx+0x14>)
800288c: f001 f989 bl 8003ba2 <HAL_GPIO_WritePin>
}
8002890: bf00 nop
8002892: bd80 pop {r7, pc}
8002894: 40010800 .word 0x40010800
08002898 <rs485_configure_gpio_address>:
/**
* @brief Configures GPIOs for address detection.
*/
static void rs485_configure_gpio_address(void)
{
8002898: b580 push {r7, lr}
800289a: b086 sub sp, #24
800289c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800289e: f107 0308 add.w r3, r7, #8
80028a2: 2200 movs r2, #0
80028a4: 601a str r2, [r3, #0]
80028a6: 605a str r2, [r3, #4]
80028a8: 609a str r2, [r3, #8]
80028aa: 60da str r2, [r3, #12]
/* Enable clock for GPIOA and GPIOB */
__HAL_RCC_GPIOA_CLK_ENABLE();
80028ac: 4b1a ldr r3, [pc, #104] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028ae: 699b ldr r3, [r3, #24]
80028b0: 4a19 ldr r2, [pc, #100] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028b2: f043 0304 orr.w r3, r3, #4
80028b6: 6193 str r3, [r2, #24]
80028b8: 4b17 ldr r3, [pc, #92] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028ba: 699b ldr r3, [r3, #24]
80028bc: f003 0304 and.w r3, r3, #4
80028c0: 607b str r3, [r7, #4]
80028c2: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80028c4: 4b14 ldr r3, [pc, #80] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028c6: 699b ldr r3, [r3, #24]
80028c8: 4a13 ldr r2, [pc, #76] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028ca: f043 0308 orr.w r3, r3, #8
80028ce: 6193 str r3, [r2, #24]
80028d0: 4b11 ldr r3, [pc, #68] @ (8002918 <rs485_configure_gpio_address+0x80>)
80028d2: 699b ldr r3, [r3, #24]
80028d4: f003 0308 and.w r3, r3, #8
80028d8: 603b str r3, [r7, #0]
80028da: 683b ldr r3, [r7, #0]
/* Configure PA2-PA5 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
80028dc: 233c movs r3, #60 @ 0x3c
80028de: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80028e0: 2300 movs r3, #0
80028e2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80028e4: 2301 movs r3, #1
80028e6: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80028e8: f107 0308 add.w r3, r7, #8
80028ec: 4619 mov r1, r3
80028ee: 480b ldr r0, [pc, #44] @ (800291c <rs485_configure_gpio_address+0x84>)
80028f0: f000 ffbc bl 800386c <HAL_GPIO_Init>
/* Configure PB12-PB15 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
80028f4: f44f 4370 mov.w r3, #61440 @ 0xf000
80028f8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80028fa: 2300 movs r3, #0
80028fc: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80028fe: 2301 movs r3, #1
8002900: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002902: f107 0308 add.w r3, r7, #8
8002906: 4619 mov r1, r3
8002908: 4805 ldr r0, [pc, #20] @ (8002920 <rs485_configure_gpio_address+0x88>)
800290a: f000 ffaf bl 800386c <HAL_GPIO_Init>
}
800290e: bf00 nop
8002910: 3718 adds r7, #24
8002912: 46bd mov sp, r7
8002914: bd80 pop {r7, pc}
8002916: bf00 nop
8002918: 40021000 .word 0x40021000
800291c: 40010800 .word 0x40010800
8002920: 40010c00 .word 0x40010c00
08002924 <rs485_configure_usart1>:
/**
* @brief Configures USART1 for RS-485 communication.
*/
static void rs485_configure_usart1(void)
{
8002924: b580 push {r7, lr}
8002926: b082 sub sp, #8
8002928: af00 add r7, sp, #0
/* Enable clock for USART1 */
__HAL_RCC_USART1_CLK_ENABLE();
800292a: 4b18 ldr r3, [pc, #96] @ (800298c <rs485_configure_usart1+0x68>)
800292c: 699b ldr r3, [r3, #24]
800292e: 4a17 ldr r2, [pc, #92] @ (800298c <rs485_configure_usart1+0x68>)
8002930: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002934: 6193 str r3, [r2, #24]
8002936: 4b15 ldr r3, [pc, #84] @ (800298c <rs485_configure_usart1+0x68>)
8002938: 699b ldr r3, [r3, #24]
800293a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800293e: 607b str r3, [r7, #4]
8002940: 687b ldr r3, [r7, #4]
huart1.Instance = USART1;
8002942: 4b13 ldr r3, [pc, #76] @ (8002990 <rs485_configure_usart1+0x6c>)
8002944: 4a13 ldr r2, [pc, #76] @ (8002994 <rs485_configure_usart1+0x70>)
8002946: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */
8002948: 4b11 ldr r3, [pc, #68] @ (8002990 <rs485_configure_usart1+0x6c>)
800294a: f44f 5216 mov.w r2, #9600 @ 0x2580
800294e: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002950: 4b0f ldr r3, [pc, #60] @ (8002990 <rs485_configure_usart1+0x6c>)
8002952: 2200 movs r2, #0
8002954: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002956: 4b0e ldr r3, [pc, #56] @ (8002990 <rs485_configure_usart1+0x6c>)
8002958: 2200 movs r2, #0
800295a: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800295c: 4b0c ldr r3, [pc, #48] @ (8002990 <rs485_configure_usart1+0x6c>)
800295e: 2200 movs r2, #0
8002960: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002962: 4b0b ldr r3, [pc, #44] @ (8002990 <rs485_configure_usart1+0x6c>)
8002964: 220c movs r2, #12
8002966: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
8002968: 4b09 ldr r3, [pc, #36] @ (8002990 <rs485_configure_usart1+0x6c>)
800296a: 2200 movs r2, #0
800296c: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
800296e: 4b08 ldr r3, [pc, #32] @ (8002990 <rs485_configure_usart1+0x6c>)
8002970: 2200 movs r2, #0
8002972: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002974: 4806 ldr r0, [pc, #24] @ (8002990 <rs485_configure_usart1+0x6c>)
8002976: f002 fe41 bl 80055fc <HAL_UART_Init>
800297a: 4603 mov r3, r0
800297c: 2b00 cmp r3, #0
800297e: d001 beq.n 8002984 <rs485_configure_usart1+0x60>
{
/* Initialization Error */
while(1);
8002980: bf00 nop
8002982: e7fd b.n 8002980 <rs485_configure_usart1+0x5c>
}
}
8002984: bf00 nop
8002986: 3708 adds r7, #8
8002988: 46bd mov sp, r7
800298a: bd80 pop {r7, pc}
800298c: 40021000 .word 0x40021000
8002990: 2000065c .word 0x2000065c
8002994: 40013800 .word 0x40013800
08002998 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8002998: b480 push {r7}
800299a: b085 sub sp, #20
800299c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
800299e: 4b15 ldr r3, [pc, #84] @ (80029f4 <HAL_MspInit+0x5c>)
80029a0: 699b ldr r3, [r3, #24]
80029a2: 4a14 ldr r2, [pc, #80] @ (80029f4 <HAL_MspInit+0x5c>)
80029a4: f043 0301 orr.w r3, r3, #1
80029a8: 6193 str r3, [r2, #24]
80029aa: 4b12 ldr r3, [pc, #72] @ (80029f4 <HAL_MspInit+0x5c>)
80029ac: 699b ldr r3, [r3, #24]
80029ae: f003 0301 and.w r3, r3, #1
80029b2: 60bb str r3, [r7, #8]
80029b4: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
80029b6: 4b0f ldr r3, [pc, #60] @ (80029f4 <HAL_MspInit+0x5c>)
80029b8: 69db ldr r3, [r3, #28]
80029ba: 4a0e ldr r2, [pc, #56] @ (80029f4 <HAL_MspInit+0x5c>)
80029bc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80029c0: 61d3 str r3, [r2, #28]
80029c2: 4b0c ldr r3, [pc, #48] @ (80029f4 <HAL_MspInit+0x5c>)
80029c4: 69db ldr r3, [r3, #28]
80029c6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80029ca: 607b str r3, [r7, #4]
80029cc: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
80029ce: 4b0a ldr r3, [pc, #40] @ (80029f8 <HAL_MspInit+0x60>)
80029d0: 685b ldr r3, [r3, #4]
80029d2: 60fb str r3, [r7, #12]
80029d4: 68fb ldr r3, [r7, #12]
80029d6: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
80029da: 60fb str r3, [r7, #12]
80029dc: 68fb ldr r3, [r7, #12]
80029de: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80029e2: 60fb str r3, [r7, #12]
80029e4: 4a04 ldr r2, [pc, #16] @ (80029f8 <HAL_MspInit+0x60>)
80029e6: 68fb ldr r3, [r7, #12]
80029e8: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80029ea: bf00 nop
80029ec: 3714 adds r7, #20
80029ee: 46bd mov sp, r7
80029f0: bc80 pop {r7}
80029f2: 4770 bx lr
80029f4: 40021000 .word 0x40021000
80029f8: 40010000 .word 0x40010000
080029fc <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80029fc: b480 push {r7}
80029fe: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8002a00: bf00 nop
8002a02: e7fd b.n 8002a00 <NMI_Handler+0x4>
08002a04 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8002a04: b480 push {r7}
8002a06: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8002a08: bf00 nop
8002a0a: e7fd b.n 8002a08 <HardFault_Handler+0x4>
08002a0c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8002a0c: b480 push {r7}
8002a0e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8002a10: bf00 nop
8002a12: e7fd b.n 8002a10 <MemManage_Handler+0x4>
08002a14 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8002a14: b480 push {r7}
8002a16: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8002a18: bf00 nop
8002a1a: e7fd b.n 8002a18 <BusFault_Handler+0x4>
08002a1c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8002a1c: b480 push {r7}
8002a1e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8002a20: bf00 nop
8002a22: e7fd b.n 8002a20 <UsageFault_Handler+0x4>
08002a24 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8002a24: b480 push {r7}
8002a26: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8002a28: bf00 nop
8002a2a: 46bd mov sp, r7
8002a2c: bc80 pop {r7}
8002a2e: 4770 bx lr
08002a30 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8002a30: b480 push {r7}
8002a32: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8002a34: bf00 nop
8002a36: 46bd mov sp, r7
8002a38: bc80 pop {r7}
8002a3a: 4770 bx lr
08002a3c <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8002a3c: b480 push {r7}
8002a3e: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8002a40: bf00 nop
8002a42: 46bd mov sp, r7
8002a44: bc80 pop {r7}
8002a46: 4770 bx lr
08002a48 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002a48: b580 push {r7, lr}
8002a4a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002a4c: f000 f8fc bl 8002c48 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8002a50: bf00 nop
8002a52: bd80 pop {r7, pc}
08002a54 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8002a54: b580 push {r7, lr}
8002a56: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8002a58: 4802 ldr r0, [pc, #8] @ (8002a64 <USART1_IRQHandler+0x10>)
8002a5a: f002 feab bl 80057b4 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8002a5e: bf00 nop
8002a60: bd80 pop {r7, pc}
8002a62: bf00 nop
8002a64: 200006a4 .word 0x200006a4
08002a68 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8002a68: b480 push {r7}
8002a6a: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8002a6c: bf00 nop
8002a6e: 46bd mov sp, r7
8002a70: bc80 pop {r7}
8002a72: 4770 bx lr
08002a74 <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8002a74: b580 push {r7, lr}
8002a76: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8002a78: 4b11 ldr r3, [pc, #68] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a7a: 4a12 ldr r2, [pc, #72] @ (8002ac4 <MX_USART1_UART_Init+0x50>)
8002a7c: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8002a7e: 4b10 ldr r3, [pc, #64] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a80: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8002a84: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002a86: 4b0e ldr r3, [pc, #56] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a88: 2200 movs r2, #0
8002a8a: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002a8c: 4b0c ldr r3, [pc, #48] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a8e: 2200 movs r2, #0
8002a90: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8002a92: 4b0b ldr r3, [pc, #44] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a94: 2200 movs r2, #0
8002a96: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002a98: 4b09 ldr r3, [pc, #36] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002a9a: 220c movs r2, #12
8002a9c: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8002a9e: 4b08 ldr r3, [pc, #32] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002aa0: 2200 movs r2, #0
8002aa2: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8002aa4: 4b06 ldr r3, [pc, #24] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002aa6: 2200 movs r2, #0
8002aa8: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002aaa: 4805 ldr r0, [pc, #20] @ (8002ac0 <MX_USART1_UART_Init+0x4c>)
8002aac: f002 fda6 bl 80055fc <HAL_UART_Init>
8002ab0: 4603 mov r3, r0
8002ab2: 2b00 cmp r3, #0
8002ab4: d001 beq.n 8002aba <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8002ab6: f7ff fe75 bl 80027a4 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8002aba: bf00 nop
8002abc: bd80 pop {r7, pc}
8002abe: bf00 nop
8002ac0: 200006a4 .word 0x200006a4
8002ac4: 40013800 .word 0x40013800
08002ac8 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8002ac8: b580 push {r7, lr}
8002aca: b088 sub sp, #32
8002acc: af00 add r7, sp, #0
8002ace: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002ad0: f107 0310 add.w r3, r7, #16
8002ad4: 2200 movs r2, #0
8002ad6: 601a str r2, [r3, #0]
8002ad8: 605a str r2, [r3, #4]
8002ada: 609a str r2, [r3, #8]
8002adc: 60da str r2, [r3, #12]
if(uartHandle->Instance==USART1)
8002ade: 687b ldr r3, [r7, #4]
8002ae0: 681b ldr r3, [r3, #0]
8002ae2: 4a20 ldr r2, [pc, #128] @ (8002b64 <HAL_UART_MspInit+0x9c>)
8002ae4: 4293 cmp r3, r2
8002ae6: d139 bne.n 8002b5c <HAL_UART_MspInit+0x94>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8002ae8: 4b1f ldr r3, [pc, #124] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002aea: 699b ldr r3, [r3, #24]
8002aec: 4a1e ldr r2, [pc, #120] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002aee: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002af2: 6193 str r3, [r2, #24]
8002af4: 4b1c ldr r3, [pc, #112] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002af6: 699b ldr r3, [r3, #24]
8002af8: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002afc: 60fb str r3, [r7, #12]
8002afe: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8002b00: 4b19 ldr r3, [pc, #100] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002b02: 699b ldr r3, [r3, #24]
8002b04: 4a18 ldr r2, [pc, #96] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002b06: f043 0304 orr.w r3, r3, #4
8002b0a: 6193 str r3, [r2, #24]
8002b0c: 4b16 ldr r3, [pc, #88] @ (8002b68 <HAL_UART_MspInit+0xa0>)
8002b0e: 699b ldr r3, [r3, #24]
8002b10: f003 0304 and.w r3, r3, #4
8002b14: 60bb str r3, [r7, #8]
8002b16: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = TX_RS485_Pin;
8002b18: f44f 7300 mov.w r3, #512 @ 0x200
8002b1c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8002b1e: 2302 movs r3, #2
8002b20: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
8002b22: 2301 movs r3, #1
8002b24: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
8002b26: f107 0310 add.w r3, r7, #16
8002b2a: 4619 mov r1, r3
8002b2c: 480f ldr r0, [pc, #60] @ (8002b6c <HAL_UART_MspInit+0xa4>)
8002b2e: f000 fe9d bl 800386c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RX_RS485_Pin;
8002b32: f44f 6380 mov.w r3, #1024 @ 0x400
8002b36: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002b38: 2300 movs r3, #0
8002b3a: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002b3c: 2300 movs r3, #0
8002b3e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
8002b40: f107 0310 add.w r3, r7, #16
8002b44: 4619 mov r1, r3
8002b46: 4809 ldr r0, [pc, #36] @ (8002b6c <HAL_UART_MspInit+0xa4>)
8002b48: f000 fe90 bl 800386c <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8002b4c: 2200 movs r2, #0
8002b4e: 2100 movs r1, #0
8002b50: 2025 movs r0, #37 @ 0x25
8002b52: f000 fba2 bl 800329a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8002b56: 2025 movs r0, #37 @ 0x25
8002b58: f000 fbbb bl 80032d2 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8002b5c: bf00 nop
8002b5e: 3720 adds r7, #32
8002b60: 46bd mov sp, r7
8002b62: bd80 pop {r7, pc}
8002b64: 40013800 .word 0x40013800
8002b68: 40021000 .word 0x40021000
8002b6c: 40010800 .word 0x40010800
08002b70 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8002b70: f7ff ff7a bl 8002a68 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8002b74: 480b ldr r0, [pc, #44] @ (8002ba4 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8002b76: 490c ldr r1, [pc, #48] @ (8002ba8 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8002b78: 4a0c ldr r2, [pc, #48] @ (8002bac <LoopFillZerobss+0x16>)
movs r3, #0
8002b7a: 2300 movs r3, #0
b LoopCopyDataInit
8002b7c: e002 b.n 8002b84 <LoopCopyDataInit>
08002b7e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8002b7e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8002b80: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8002b82: 3304 adds r3, #4
08002b84 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002b84: 18c4 adds r4, r0, r3
cmp r4, r1
8002b86: 428c cmp r4, r1
bcc CopyDataInit
8002b88: d3f9 bcc.n 8002b7e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8002b8a: 4a09 ldr r2, [pc, #36] @ (8002bb0 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8002b8c: 4c09 ldr r4, [pc, #36] @ (8002bb4 <LoopFillZerobss+0x1e>)
movs r3, #0
8002b8e: 2300 movs r3, #0
b LoopFillZerobss
8002b90: e001 b.n 8002b96 <LoopFillZerobss>
08002b92 <FillZerobss>:
FillZerobss:
str r3, [r2]
8002b92: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002b94: 3204 adds r2, #4
08002b96 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002b96: 42a2 cmp r2, r4
bcc FillZerobss
8002b98: d3fb bcc.n 8002b92 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8002b9a: f003 fb53 bl 8006244 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8002b9e: f7ff faf5 bl 800218c <main>
bx lr
8002ba2: 4770 bx lr
ldr r0, =_sdata
8002ba4: 20000000 .word 0x20000000
ldr r1, =_edata
8002ba8: 20000074 .word 0x20000074
ldr r2, =_sidata
8002bac: 080064ac .word 0x080064ac
ldr r2, =_sbss
8002bb0: 20000078 .word 0x20000078
ldr r4, =_ebss
8002bb4: 20000848 .word 0x20000848
08002bb8 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002bb8: e7fe b.n 8002bb8 <ADC1_2_IRQHandler>
...
08002bbc <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8002bbc: b580 push {r7, lr}
8002bbe: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002bc0: 4b08 ldr r3, [pc, #32] @ (8002be4 <HAL_Init+0x28>)
8002bc2: 681b ldr r3, [r3, #0]
8002bc4: 4a07 ldr r2, [pc, #28] @ (8002be4 <HAL_Init+0x28>)
8002bc6: f043 0310 orr.w r3, r3, #16
8002bca: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8002bcc: 2003 movs r0, #3
8002bce: f000 fb59 bl 8003284 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002bd2: 200f movs r0, #15
8002bd4: f000 f808 bl 8002be8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002bd8: f7ff fede bl 8002998 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8002bdc: 2300 movs r3, #0
}
8002bde: 4618 mov r0, r3
8002be0: bd80 pop {r7, pc}
8002be2: bf00 nop
8002be4: 40022000 .word 0x40022000
08002be8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002be8: b580 push {r7, lr}
8002bea: b082 sub sp, #8
8002bec: af00 add r7, sp, #0
8002bee: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002bf0: 4b12 ldr r3, [pc, #72] @ (8002c3c <HAL_InitTick+0x54>)
8002bf2: 681a ldr r2, [r3, #0]
8002bf4: 4b12 ldr r3, [pc, #72] @ (8002c40 <HAL_InitTick+0x58>)
8002bf6: 781b ldrb r3, [r3, #0]
8002bf8: 4619 mov r1, r3
8002bfa: f44f 737a mov.w r3, #1000 @ 0x3e8
8002bfe: fbb3 f3f1 udiv r3, r3, r1
8002c02: fbb2 f3f3 udiv r3, r2, r3
8002c06: 4618 mov r0, r3
8002c08: f000 fb71 bl 80032ee <HAL_SYSTICK_Config>
8002c0c: 4603 mov r3, r0
8002c0e: 2b00 cmp r3, #0
8002c10: d001 beq.n 8002c16 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002c12: 2301 movs r3, #1
8002c14: e00e b.n 8002c34 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002c16: 687b ldr r3, [r7, #4]
8002c18: 2b0f cmp r3, #15
8002c1a: d80a bhi.n 8002c32 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8002c1c: 2200 movs r2, #0
8002c1e: 6879 ldr r1, [r7, #4]
8002c20: f04f 30ff mov.w r0, #4294967295
8002c24: f000 fb39 bl 800329a <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8002c28: 4a06 ldr r2, [pc, #24] @ (8002c44 <HAL_InitTick+0x5c>)
8002c2a: 687b ldr r3, [r7, #4]
8002c2c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8002c2e: 2300 movs r3, #0
8002c30: e000 b.n 8002c34 <HAL_InitTick+0x4c>
return HAL_ERROR;
8002c32: 2301 movs r3, #1
}
8002c34: 4618 mov r0, r3
8002c36: 3708 adds r7, #8
8002c38: 46bd mov sp, r7
8002c3a: bd80 pop {r7, pc}
8002c3c: 20000018 .word 0x20000018
8002c40: 20000020 .word 0x20000020
8002c44: 2000001c .word 0x2000001c
08002c48 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8002c48: b480 push {r7}
8002c4a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8002c4c: 4b05 ldr r3, [pc, #20] @ (8002c64 <HAL_IncTick+0x1c>)
8002c4e: 781b ldrb r3, [r3, #0]
8002c50: 461a mov r2, r3
8002c52: 4b05 ldr r3, [pc, #20] @ (8002c68 <HAL_IncTick+0x20>)
8002c54: 681b ldr r3, [r3, #0]
8002c56: 4413 add r3, r2
8002c58: 4a03 ldr r2, [pc, #12] @ (8002c68 <HAL_IncTick+0x20>)
8002c5a: 6013 str r3, [r2, #0]
}
8002c5c: bf00 nop
8002c5e: 46bd mov sp, r7
8002c60: bc80 pop {r7}
8002c62: 4770 bx lr
8002c64: 20000020 .word 0x20000020
8002c68: 200006ec .word 0x200006ec
08002c6c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8002c6c: b480 push {r7}
8002c6e: af00 add r7, sp, #0
return uwTick;
8002c70: 4b02 ldr r3, [pc, #8] @ (8002c7c <HAL_GetTick+0x10>)
8002c72: 681b ldr r3, [r3, #0]
}
8002c74: 4618 mov r0, r3
8002c76: 46bd mov sp, r7
8002c78: bc80 pop {r7}
8002c7a: 4770 bx lr
8002c7c: 200006ec .word 0x200006ec
08002c80 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8002c80: b580 push {r7, lr}
8002c82: b084 sub sp, #16
8002c84: af00 add r7, sp, #0
8002c86: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8002c88: f7ff fff0 bl 8002c6c <HAL_GetTick>
8002c8c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8002c8e: 687b ldr r3, [r7, #4]
8002c90: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8002c92: 68fb ldr r3, [r7, #12]
8002c94: f1b3 3fff cmp.w r3, #4294967295
8002c98: d005 beq.n 8002ca6 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8002c9a: 4b0a ldr r3, [pc, #40] @ (8002cc4 <HAL_Delay+0x44>)
8002c9c: 781b ldrb r3, [r3, #0]
8002c9e: 461a mov r2, r3
8002ca0: 68fb ldr r3, [r7, #12]
8002ca2: 4413 add r3, r2
8002ca4: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8002ca6: bf00 nop
8002ca8: f7ff ffe0 bl 8002c6c <HAL_GetTick>
8002cac: 4602 mov r2, r0
8002cae: 68bb ldr r3, [r7, #8]
8002cb0: 1ad3 subs r3, r2, r3
8002cb2: 68fa ldr r2, [r7, #12]
8002cb4: 429a cmp r2, r3
8002cb6: d8f7 bhi.n 8002ca8 <HAL_Delay+0x28>
{
}
}
8002cb8: bf00 nop
8002cba: bf00 nop
8002cbc: 3710 adds r7, #16
8002cbe: 46bd mov sp, r7
8002cc0: bd80 pop {r7, pc}
8002cc2: bf00 nop
8002cc4: 20000020 .word 0x20000020
08002cc8 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8002cc8: b580 push {r7, lr}
8002cca: b086 sub sp, #24
8002ccc: af00 add r7, sp, #0
8002cce: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002cd0: 2300 movs r3, #0
8002cd2: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
8002cd4: 2300 movs r3, #0
8002cd6: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8002cd8: 2300 movs r3, #0
8002cda: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
8002cdc: 2300 movs r3, #0
8002cde: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8002ce0: 687b ldr r3, [r7, #4]
8002ce2: 2b00 cmp r3, #0
8002ce4: d101 bne.n 8002cea <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
8002ce6: 2301 movs r3, #1
8002ce8: e0be b.n 8002e68 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8002cea: 687b ldr r3, [r7, #4]
8002cec: 689b ldr r3, [r3, #8]
8002cee: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002cf0: 687b ldr r3, [r7, #4]
8002cf2: 6a9b ldr r3, [r3, #40] @ 0x28
8002cf4: 2b00 cmp r3, #0
8002cf6: d109 bne.n 8002d0c <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8002cf8: 687b ldr r3, [r7, #4]
8002cfa: 2200 movs r2, #0
8002cfc: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8002cfe: 687b ldr r3, [r7, #4]
8002d00: 2200 movs r2, #0
8002d02: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8002d06: 6878 ldr r0, [r7, #4]
8002d08: f7fe fe3c bl 8001984 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8002d0c: 6878 ldr r0, [r7, #4]
8002d0e: f000 f9ab bl 8003068 <ADC_ConversionStop_Disable>
8002d12: 4603 mov r3, r0
8002d14: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8002d16: 687b ldr r3, [r7, #4]
8002d18: 6a9b ldr r3, [r3, #40] @ 0x28
8002d1a: f003 0310 and.w r3, r3, #16
8002d1e: 2b00 cmp r3, #0
8002d20: f040 8099 bne.w 8002e56 <HAL_ADC_Init+0x18e>
8002d24: 7dfb ldrb r3, [r7, #23]
8002d26: 2b00 cmp r3, #0
8002d28: f040 8095 bne.w 8002e56 <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002d2c: 687b ldr r3, [r7, #4]
8002d2e: 6a9b ldr r3, [r3, #40] @ 0x28
8002d30: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002d34: f023 0302 bic.w r3, r3, #2
8002d38: f043 0202 orr.w r2, r3, #2
8002d3c: 687b ldr r3, [r7, #4]
8002d3e: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8002d40: 687b ldr r3, [r7, #4]
8002d42: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002d44: 687b ldr r3, [r7, #4]
8002d46: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8002d48: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8002d4a: 687b ldr r3, [r7, #4]
8002d4c: 7b1b ldrb r3, [r3, #12]
8002d4e: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002d50: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8002d52: 68ba ldr r2, [r7, #8]
8002d54: 4313 orrs r3, r2
8002d56: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8002d58: 687b ldr r3, [r7, #4]
8002d5a: 689b ldr r3, [r3, #8]
8002d5c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002d60: d003 beq.n 8002d6a <HAL_ADC_Init+0xa2>
8002d62: 687b ldr r3, [r7, #4]
8002d64: 689b ldr r3, [r3, #8]
8002d66: 2b01 cmp r3, #1
8002d68: d102 bne.n 8002d70 <HAL_ADC_Init+0xa8>
8002d6a: f44f 7380 mov.w r3, #256 @ 0x100
8002d6e: e000 b.n 8002d72 <HAL_ADC_Init+0xaa>
8002d70: 2300 movs r3, #0
8002d72: 693a ldr r2, [r7, #16]
8002d74: 4313 orrs r3, r2
8002d76: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002d78: 687b ldr r3, [r7, #4]
8002d7a: 7d1b ldrb r3, [r3, #20]
8002d7c: 2b01 cmp r3, #1
8002d7e: d119 bne.n 8002db4 <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8002d80: 687b ldr r3, [r7, #4]
8002d82: 7b1b ldrb r3, [r3, #12]
8002d84: 2b00 cmp r3, #0
8002d86: d109 bne.n 8002d9c <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8002d88: 687b ldr r3, [r7, #4]
8002d8a: 699b ldr r3, [r3, #24]
8002d8c: 3b01 subs r3, #1
8002d8e: 035a lsls r2, r3, #13
8002d90: 693b ldr r3, [r7, #16]
8002d92: 4313 orrs r3, r2
8002d94: f443 6300 orr.w r3, r3, #2048 @ 0x800
8002d98: 613b str r3, [r7, #16]
8002d9a: e00b b.n 8002db4 <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002d9c: 687b ldr r3, [r7, #4]
8002d9e: 6a9b ldr r3, [r3, #40] @ 0x28
8002da0: f043 0220 orr.w r2, r3, #32
8002da4: 687b ldr r3, [r7, #4]
8002da6: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002da8: 687b ldr r3, [r7, #4]
8002daa: 6adb ldr r3, [r3, #44] @ 0x2c
8002dac: f043 0201 orr.w r2, r3, #1
8002db0: 687b ldr r3, [r7, #4]
8002db2: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
8002db4: 687b ldr r3, [r7, #4]
8002db6: 681b ldr r3, [r3, #0]
8002db8: 685b ldr r3, [r3, #4]
8002dba: f423 4169 bic.w r1, r3, #59648 @ 0xe900
8002dbe: 687b ldr r3, [r7, #4]
8002dc0: 681b ldr r3, [r3, #0]
8002dc2: 693a ldr r2, [r7, #16]
8002dc4: 430a orrs r2, r1
8002dc6: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
8002dc8: 687b ldr r3, [r7, #4]
8002dca: 681b ldr r3, [r3, #0]
8002dcc: 689a ldr r2, [r3, #8]
8002dce: 4b28 ldr r3, [pc, #160] @ (8002e70 <HAL_ADC_Init+0x1a8>)
8002dd0: 4013 ands r3, r2
8002dd2: 687a ldr r2, [r7, #4]
8002dd4: 6812 ldr r2, [r2, #0]
8002dd6: 68b9 ldr r1, [r7, #8]
8002dd8: 430b orrs r3, r1
8002dda: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8002ddc: 687b ldr r3, [r7, #4]
8002dde: 689b ldr r3, [r3, #8]
8002de0: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002de4: d003 beq.n 8002dee <HAL_ADC_Init+0x126>
8002de6: 687b ldr r3, [r7, #4]
8002de8: 689b ldr r3, [r3, #8]
8002dea: 2b01 cmp r3, #1
8002dec: d104 bne.n 8002df8 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
8002dee: 687b ldr r3, [r7, #4]
8002df0: 691b ldr r3, [r3, #16]
8002df2: 3b01 subs r3, #1
8002df4: 051b lsls r3, r3, #20
8002df6: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8002df8: 687b ldr r3, [r7, #4]
8002dfa: 681b ldr r3, [r3, #0]
8002dfc: 6adb ldr r3, [r3, #44] @ 0x2c
8002dfe: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
8002e02: 687b ldr r3, [r7, #4]
8002e04: 681b ldr r3, [r3, #0]
8002e06: 68fa ldr r2, [r7, #12]
8002e08: 430a orrs r2, r1
8002e0a: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002e0c: 687b ldr r3, [r7, #4]
8002e0e: 681b ldr r3, [r3, #0]
8002e10: 689a ldr r2, [r3, #8]
8002e12: 4b18 ldr r3, [pc, #96] @ (8002e74 <HAL_ADC_Init+0x1ac>)
8002e14: 4013 ands r3, r2
8002e16: 68ba ldr r2, [r7, #8]
8002e18: 429a cmp r2, r3
8002e1a: d10b bne.n 8002e34 <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002e1c: 687b ldr r3, [r7, #4]
8002e1e: 2200 movs r2, #0
8002e20: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002e22: 687b ldr r3, [r7, #4]
8002e24: 6a9b ldr r3, [r3, #40] @ 0x28
8002e26: f023 0303 bic.w r3, r3, #3
8002e2a: f043 0201 orr.w r2, r3, #1
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002e32: e018 b.n 8002e66 <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002e34: 687b ldr r3, [r7, #4]
8002e36: 6a9b ldr r3, [r3, #40] @ 0x28
8002e38: f023 0312 bic.w r3, r3, #18
8002e3c: f043 0210 orr.w r2, r3, #16
8002e40: 687b ldr r3, [r7, #4]
8002e42: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002e44: 687b ldr r3, [r7, #4]
8002e46: 6adb ldr r3, [r3, #44] @ 0x2c
8002e48: f043 0201 orr.w r2, r3, #1
8002e4c: 687b ldr r3, [r7, #4]
8002e4e: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8002e50: 2301 movs r3, #1
8002e52: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002e54: e007 b.n 8002e66 <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002e56: 687b ldr r3, [r7, #4]
8002e58: 6a9b ldr r3, [r3, #40] @ 0x28
8002e5a: f043 0210 orr.w r2, r3, #16
8002e5e: 687b ldr r3, [r7, #4]
8002e60: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8002e62: 2301 movs r3, #1
8002e64: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8002e66: 7dfb ldrb r3, [r7, #23]
}
8002e68: 4618 mov r0, r3
8002e6a: 3718 adds r7, #24
8002e6c: 46bd mov sp, r7
8002e6e: bd80 pop {r7, pc}
8002e70: ffe1f7fd .word 0xffe1f7fd
8002e74: ff1f0efe .word 0xff1f0efe
08002e78 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002e78: b480 push {r7}
8002e7a: b085 sub sp, #20
8002e7c: af00 add r7, sp, #0
8002e7e: 6078 str r0, [r7, #4]
8002e80: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002e82: 2300 movs r3, #0
8002e84: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
8002e86: 2300 movs r3, #0
8002e88: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8002e8a: 687b ldr r3, [r7, #4]
8002e8c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8002e90: 2b01 cmp r3, #1
8002e92: d101 bne.n 8002e98 <HAL_ADC_ConfigChannel+0x20>
8002e94: 2302 movs r3, #2
8002e96: e0dc b.n 8003052 <HAL_ADC_ConfigChannel+0x1da>
8002e98: 687b ldr r3, [r7, #4]
8002e9a: 2201 movs r2, #1
8002e9c: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
8002ea0: 683b ldr r3, [r7, #0]
8002ea2: 685b ldr r3, [r3, #4]
8002ea4: 2b06 cmp r3, #6
8002ea6: d81c bhi.n 8002ee2 <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8002ea8: 687b ldr r3, [r7, #4]
8002eaa: 681b ldr r3, [r3, #0]
8002eac: 6b59 ldr r1, [r3, #52] @ 0x34
8002eae: 683b ldr r3, [r7, #0]
8002eb0: 685a ldr r2, [r3, #4]
8002eb2: 4613 mov r3, r2
8002eb4: 009b lsls r3, r3, #2
8002eb6: 4413 add r3, r2
8002eb8: 3b05 subs r3, #5
8002eba: 221f movs r2, #31
8002ebc: fa02 f303 lsl.w r3, r2, r3
8002ec0: 43db mvns r3, r3
8002ec2: 4019 ands r1, r3
8002ec4: 683b ldr r3, [r7, #0]
8002ec6: 6818 ldr r0, [r3, #0]
8002ec8: 683b ldr r3, [r7, #0]
8002eca: 685a ldr r2, [r3, #4]
8002ecc: 4613 mov r3, r2
8002ece: 009b lsls r3, r3, #2
8002ed0: 4413 add r3, r2
8002ed2: 3b05 subs r3, #5
8002ed4: fa00 f203 lsl.w r2, r0, r3
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 681b ldr r3, [r3, #0]
8002edc: 430a orrs r2, r1
8002ede: 635a str r2, [r3, #52] @ 0x34
8002ee0: e03c b.n 8002f5c <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
8002ee2: 683b ldr r3, [r7, #0]
8002ee4: 685b ldr r3, [r3, #4]
8002ee6: 2b0c cmp r3, #12
8002ee8: d81c bhi.n 8002f24 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
8002eea: 687b ldr r3, [r7, #4]
8002eec: 681b ldr r3, [r3, #0]
8002eee: 6b19 ldr r1, [r3, #48] @ 0x30
8002ef0: 683b ldr r3, [r7, #0]
8002ef2: 685a ldr r2, [r3, #4]
8002ef4: 4613 mov r3, r2
8002ef6: 009b lsls r3, r3, #2
8002ef8: 4413 add r3, r2
8002efa: 3b23 subs r3, #35 @ 0x23
8002efc: 221f movs r2, #31
8002efe: fa02 f303 lsl.w r3, r2, r3
8002f02: 43db mvns r3, r3
8002f04: 4019 ands r1, r3
8002f06: 683b ldr r3, [r7, #0]
8002f08: 6818 ldr r0, [r3, #0]
8002f0a: 683b ldr r3, [r7, #0]
8002f0c: 685a ldr r2, [r3, #4]
8002f0e: 4613 mov r3, r2
8002f10: 009b lsls r3, r3, #2
8002f12: 4413 add r3, r2
8002f14: 3b23 subs r3, #35 @ 0x23
8002f16: fa00 f203 lsl.w r2, r0, r3
8002f1a: 687b ldr r3, [r7, #4]
8002f1c: 681b ldr r3, [r3, #0]
8002f1e: 430a orrs r2, r1
8002f20: 631a str r2, [r3, #48] @ 0x30
8002f22: e01b b.n 8002f5c <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
8002f24: 687b ldr r3, [r7, #4]
8002f26: 681b ldr r3, [r3, #0]
8002f28: 6ad9 ldr r1, [r3, #44] @ 0x2c
8002f2a: 683b ldr r3, [r7, #0]
8002f2c: 685a ldr r2, [r3, #4]
8002f2e: 4613 mov r3, r2
8002f30: 009b lsls r3, r3, #2
8002f32: 4413 add r3, r2
8002f34: 3b41 subs r3, #65 @ 0x41
8002f36: 221f movs r2, #31
8002f38: fa02 f303 lsl.w r3, r2, r3
8002f3c: 43db mvns r3, r3
8002f3e: 4019 ands r1, r3
8002f40: 683b ldr r3, [r7, #0]
8002f42: 6818 ldr r0, [r3, #0]
8002f44: 683b ldr r3, [r7, #0]
8002f46: 685a ldr r2, [r3, #4]
8002f48: 4613 mov r3, r2
8002f4a: 009b lsls r3, r3, #2
8002f4c: 4413 add r3, r2
8002f4e: 3b41 subs r3, #65 @ 0x41
8002f50: fa00 f203 lsl.w r2, r0, r3
8002f54: 687b ldr r3, [r7, #4]
8002f56: 681b ldr r3, [r3, #0]
8002f58: 430a orrs r2, r1
8002f5a: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8002f5c: 683b ldr r3, [r7, #0]
8002f5e: 681b ldr r3, [r3, #0]
8002f60: 2b09 cmp r3, #9
8002f62: d91c bls.n 8002f9e <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8002f64: 687b ldr r3, [r7, #4]
8002f66: 681b ldr r3, [r3, #0]
8002f68: 68d9 ldr r1, [r3, #12]
8002f6a: 683b ldr r3, [r7, #0]
8002f6c: 681a ldr r2, [r3, #0]
8002f6e: 4613 mov r3, r2
8002f70: 005b lsls r3, r3, #1
8002f72: 4413 add r3, r2
8002f74: 3b1e subs r3, #30
8002f76: 2207 movs r2, #7
8002f78: fa02 f303 lsl.w r3, r2, r3
8002f7c: 43db mvns r3, r3
8002f7e: 4019 ands r1, r3
8002f80: 683b ldr r3, [r7, #0]
8002f82: 6898 ldr r0, [r3, #8]
8002f84: 683b ldr r3, [r7, #0]
8002f86: 681a ldr r2, [r3, #0]
8002f88: 4613 mov r3, r2
8002f8a: 005b lsls r3, r3, #1
8002f8c: 4413 add r3, r2
8002f8e: 3b1e subs r3, #30
8002f90: fa00 f203 lsl.w r2, r0, r3
8002f94: 687b ldr r3, [r7, #4]
8002f96: 681b ldr r3, [r3, #0]
8002f98: 430a orrs r2, r1
8002f9a: 60da str r2, [r3, #12]
8002f9c: e019 b.n 8002fd2 <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
8002f9e: 687b ldr r3, [r7, #4]
8002fa0: 681b ldr r3, [r3, #0]
8002fa2: 6919 ldr r1, [r3, #16]
8002fa4: 683b ldr r3, [r7, #0]
8002fa6: 681a ldr r2, [r3, #0]
8002fa8: 4613 mov r3, r2
8002faa: 005b lsls r3, r3, #1
8002fac: 4413 add r3, r2
8002fae: 2207 movs r2, #7
8002fb0: fa02 f303 lsl.w r3, r2, r3
8002fb4: 43db mvns r3, r3
8002fb6: 4019 ands r1, r3
8002fb8: 683b ldr r3, [r7, #0]
8002fba: 6898 ldr r0, [r3, #8]
8002fbc: 683b ldr r3, [r7, #0]
8002fbe: 681a ldr r2, [r3, #0]
8002fc0: 4613 mov r3, r2
8002fc2: 005b lsls r3, r3, #1
8002fc4: 4413 add r3, r2
8002fc6: fa00 f203 lsl.w r2, r0, r3
8002fca: 687b ldr r3, [r7, #4]
8002fcc: 681b ldr r3, [r3, #0]
8002fce: 430a orrs r2, r1
8002fd0: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8002fd2: 683b ldr r3, [r7, #0]
8002fd4: 681b ldr r3, [r3, #0]
8002fd6: 2b10 cmp r3, #16
8002fd8: d003 beq.n 8002fe2 <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
8002fda: 683b ldr r3, [r7, #0]
8002fdc: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8002fde: 2b11 cmp r3, #17
8002fe0: d132 bne.n 8003048 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
8002fe2: 687b ldr r3, [r7, #4]
8002fe4: 681b ldr r3, [r3, #0]
8002fe6: 4a1d ldr r2, [pc, #116] @ (800305c <HAL_ADC_ConfigChannel+0x1e4>)
8002fe8: 4293 cmp r3, r2
8002fea: d125 bne.n 8003038 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
8002fec: 687b ldr r3, [r7, #4]
8002fee: 681b ldr r3, [r3, #0]
8002ff0: 689b ldr r3, [r3, #8]
8002ff2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002ff6: 2b00 cmp r3, #0
8002ff8: d126 bne.n 8003048 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8002ffa: 687b ldr r3, [r7, #4]
8002ffc: 681b ldr r3, [r3, #0]
8002ffe: 689a ldr r2, [r3, #8]
8003000: 687b ldr r3, [r7, #4]
8003002: 681b ldr r3, [r3, #0]
8003004: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8003008: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
800300a: 683b ldr r3, [r7, #0]
800300c: 681b ldr r3, [r3, #0]
800300e: 2b10 cmp r3, #16
8003010: d11a bne.n 8003048 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8003012: 4b13 ldr r3, [pc, #76] @ (8003060 <HAL_ADC_ConfigChannel+0x1e8>)
8003014: 681b ldr r3, [r3, #0]
8003016: 4a13 ldr r2, [pc, #76] @ (8003064 <HAL_ADC_ConfigChannel+0x1ec>)
8003018: fba2 2303 umull r2, r3, r2, r3
800301c: 0c9a lsrs r2, r3, #18
800301e: 4613 mov r3, r2
8003020: 009b lsls r3, r3, #2
8003022: 4413 add r3, r2
8003024: 005b lsls r3, r3, #1
8003026: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003028: e002 b.n 8003030 <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
800302a: 68bb ldr r3, [r7, #8]
800302c: 3b01 subs r3, #1
800302e: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003030: 68bb ldr r3, [r7, #8]
8003032: 2b00 cmp r3, #0
8003034: d1f9 bne.n 800302a <HAL_ADC_ConfigChannel+0x1b2>
8003036: e007 b.n 8003048 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003038: 687b ldr r3, [r7, #4]
800303a: 6a9b ldr r3, [r3, #40] @ 0x28
800303c: f043 0220 orr.w r2, r3, #32
8003040: 687b ldr r3, [r7, #4]
8003042: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8003044: 2301 movs r3, #1
8003046: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003048: 687b ldr r3, [r7, #4]
800304a: 2200 movs r2, #0
800304c: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
8003050: 7bfb ldrb r3, [r7, #15]
}
8003052: 4618 mov r0, r3
8003054: 3714 adds r7, #20
8003056: 46bd mov sp, r7
8003058: bc80 pop {r7}
800305a: 4770 bx lr
800305c: 40012400 .word 0x40012400
8003060: 20000018 .word 0x20000018
8003064: 431bde83 .word 0x431bde83
08003068 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8003068: b580 push {r7, lr}
800306a: b084 sub sp, #16
800306c: af00 add r7, sp, #0
800306e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8003070: 2300 movs r3, #0
8003072: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
8003074: 687b ldr r3, [r7, #4]
8003076: 681b ldr r3, [r3, #0]
8003078: 689b ldr r3, [r3, #8]
800307a: f003 0301 and.w r3, r3, #1
800307e: 2b01 cmp r3, #1
8003080: d12e bne.n 80030e0 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8003082: 687b ldr r3, [r7, #4]
8003084: 681b ldr r3, [r3, #0]
8003086: 689a ldr r2, [r3, #8]
8003088: 687b ldr r3, [r7, #4]
800308a: 681b ldr r3, [r3, #0]
800308c: f022 0201 bic.w r2, r2, #1
8003090: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
8003092: f7ff fdeb bl 8002c6c <HAL_GetTick>
8003096: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8003098: e01b b.n 80030d2 <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
800309a: f7ff fde7 bl 8002c6c <HAL_GetTick>
800309e: 4602 mov r2, r0
80030a0: 68fb ldr r3, [r7, #12]
80030a2: 1ad3 subs r3, r2, r3
80030a4: 2b02 cmp r3, #2
80030a6: d914 bls.n 80030d2 <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
80030a8: 687b ldr r3, [r7, #4]
80030aa: 681b ldr r3, [r3, #0]
80030ac: 689b ldr r3, [r3, #8]
80030ae: f003 0301 and.w r3, r3, #1
80030b2: 2b01 cmp r3, #1
80030b4: d10d bne.n 80030d2 <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80030b6: 687b ldr r3, [r7, #4]
80030b8: 6a9b ldr r3, [r3, #40] @ 0x28
80030ba: f043 0210 orr.w r2, r3, #16
80030be: 687b ldr r3, [r7, #4]
80030c0: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80030c2: 687b ldr r3, [r7, #4]
80030c4: 6adb ldr r3, [r3, #44] @ 0x2c
80030c6: f043 0201 orr.w r2, r3, #1
80030ca: 687b ldr r3, [r7, #4]
80030cc: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
80030ce: 2301 movs r3, #1
80030d0: e007 b.n 80030e2 <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
80030d2: 687b ldr r3, [r7, #4]
80030d4: 681b ldr r3, [r3, #0]
80030d6: 689b ldr r3, [r3, #8]
80030d8: f003 0301 and.w r3, r3, #1
80030dc: 2b01 cmp r3, #1
80030de: d0dc beq.n 800309a <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
80030e0: 2300 movs r3, #0
}
80030e2: 4618 mov r0, r3
80030e4: 3710 adds r7, #16
80030e6: 46bd mov sp, r7
80030e8: bd80 pop {r7, pc}
...
080030ec <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80030ec: b480 push {r7}
80030ee: b085 sub sp, #20
80030f0: af00 add r7, sp, #0
80030f2: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80030f4: 687b ldr r3, [r7, #4]
80030f6: f003 0307 and.w r3, r3, #7
80030fa: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80030fc: 4b0c ldr r3, [pc, #48] @ (8003130 <__NVIC_SetPriorityGrouping+0x44>)
80030fe: 68db ldr r3, [r3, #12]
8003100: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8003102: 68ba ldr r2, [r7, #8]
8003104: f64f 03ff movw r3, #63743 @ 0xf8ff
8003108: 4013 ands r3, r2
800310a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800310c: 68fb ldr r3, [r7, #12]
800310e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8003110: 68bb ldr r3, [r7, #8]
8003112: 4313 orrs r3, r2
reg_value = (reg_value |
8003114: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003118: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800311c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800311e: 4a04 ldr r2, [pc, #16] @ (8003130 <__NVIC_SetPriorityGrouping+0x44>)
8003120: 68bb ldr r3, [r7, #8]
8003122: 60d3 str r3, [r2, #12]
}
8003124: bf00 nop
8003126: 3714 adds r7, #20
8003128: 46bd mov sp, r7
800312a: bc80 pop {r7}
800312c: 4770 bx lr
800312e: bf00 nop
8003130: e000ed00 .word 0xe000ed00
08003134 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8003134: b480 push {r7}
8003136: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003138: 4b04 ldr r3, [pc, #16] @ (800314c <__NVIC_GetPriorityGrouping+0x18>)
800313a: 68db ldr r3, [r3, #12]
800313c: 0a1b lsrs r3, r3, #8
800313e: f003 0307 and.w r3, r3, #7
}
8003142: 4618 mov r0, r3
8003144: 46bd mov sp, r7
8003146: bc80 pop {r7}
8003148: 4770 bx lr
800314a: bf00 nop
800314c: e000ed00 .word 0xe000ed00
08003150 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003150: b480 push {r7}
8003152: b083 sub sp, #12
8003154: af00 add r7, sp, #0
8003156: 4603 mov r3, r0
8003158: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800315a: f997 3007 ldrsb.w r3, [r7, #7]
800315e: 2b00 cmp r3, #0
8003160: db0b blt.n 800317a <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8003162: 79fb ldrb r3, [r7, #7]
8003164: f003 021f and.w r2, r3, #31
8003168: 4906 ldr r1, [pc, #24] @ (8003184 <__NVIC_EnableIRQ+0x34>)
800316a: f997 3007 ldrsb.w r3, [r7, #7]
800316e: 095b lsrs r3, r3, #5
8003170: 2001 movs r0, #1
8003172: fa00 f202 lsl.w r2, r0, r2
8003176: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
800317a: bf00 nop
800317c: 370c adds r7, #12
800317e: 46bd mov sp, r7
8003180: bc80 pop {r7}
8003182: 4770 bx lr
8003184: e000e100 .word 0xe000e100
08003188 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003188: b480 push {r7}
800318a: b083 sub sp, #12
800318c: af00 add r7, sp, #0
800318e: 4603 mov r3, r0
8003190: 6039 str r1, [r7, #0]
8003192: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003194: f997 3007 ldrsb.w r3, [r7, #7]
8003198: 2b00 cmp r3, #0
800319a: db0a blt.n 80031b2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800319c: 683b ldr r3, [r7, #0]
800319e: b2da uxtb r2, r3
80031a0: 490c ldr r1, [pc, #48] @ (80031d4 <__NVIC_SetPriority+0x4c>)
80031a2: f997 3007 ldrsb.w r3, [r7, #7]
80031a6: 0112 lsls r2, r2, #4
80031a8: b2d2 uxtb r2, r2
80031aa: 440b add r3, r1
80031ac: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80031b0: e00a b.n 80031c8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80031b2: 683b ldr r3, [r7, #0]
80031b4: b2da uxtb r2, r3
80031b6: 4908 ldr r1, [pc, #32] @ (80031d8 <__NVIC_SetPriority+0x50>)
80031b8: 79fb ldrb r3, [r7, #7]
80031ba: f003 030f and.w r3, r3, #15
80031be: 3b04 subs r3, #4
80031c0: 0112 lsls r2, r2, #4
80031c2: b2d2 uxtb r2, r2
80031c4: 440b add r3, r1
80031c6: 761a strb r2, [r3, #24]
}
80031c8: bf00 nop
80031ca: 370c adds r7, #12
80031cc: 46bd mov sp, r7
80031ce: bc80 pop {r7}
80031d0: 4770 bx lr
80031d2: bf00 nop
80031d4: e000e100 .word 0xe000e100
80031d8: e000ed00 .word 0xe000ed00
080031dc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80031dc: b480 push {r7}
80031de: b089 sub sp, #36 @ 0x24
80031e0: af00 add r7, sp, #0
80031e2: 60f8 str r0, [r7, #12]
80031e4: 60b9 str r1, [r7, #8]
80031e6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80031e8: 68fb ldr r3, [r7, #12]
80031ea: f003 0307 and.w r3, r3, #7
80031ee: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80031f0: 69fb ldr r3, [r7, #28]
80031f2: f1c3 0307 rsb r3, r3, #7
80031f6: 2b04 cmp r3, #4
80031f8: bf28 it cs
80031fa: 2304 movcs r3, #4
80031fc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80031fe: 69fb ldr r3, [r7, #28]
8003200: 3304 adds r3, #4
8003202: 2b06 cmp r3, #6
8003204: d902 bls.n 800320c <NVIC_EncodePriority+0x30>
8003206: 69fb ldr r3, [r7, #28]
8003208: 3b03 subs r3, #3
800320a: e000 b.n 800320e <NVIC_EncodePriority+0x32>
800320c: 2300 movs r3, #0
800320e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003210: f04f 32ff mov.w r2, #4294967295
8003214: 69bb ldr r3, [r7, #24]
8003216: fa02 f303 lsl.w r3, r2, r3
800321a: 43da mvns r2, r3
800321c: 68bb ldr r3, [r7, #8]
800321e: 401a ands r2, r3
8003220: 697b ldr r3, [r7, #20]
8003222: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003224: f04f 31ff mov.w r1, #4294967295
8003228: 697b ldr r3, [r7, #20]
800322a: fa01 f303 lsl.w r3, r1, r3
800322e: 43d9 mvns r1, r3
8003230: 687b ldr r3, [r7, #4]
8003232: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003234: 4313 orrs r3, r2
);
}
8003236: 4618 mov r0, r3
8003238: 3724 adds r7, #36 @ 0x24
800323a: 46bd mov sp, r7
800323c: bc80 pop {r7}
800323e: 4770 bx lr
08003240 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003240: b580 push {r7, lr}
8003242: b082 sub sp, #8
8003244: af00 add r7, sp, #0
8003246: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003248: 687b ldr r3, [r7, #4]
800324a: 3b01 subs r3, #1
800324c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003250: d301 bcc.n 8003256 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8003252: 2301 movs r3, #1
8003254: e00f b.n 8003276 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003256: 4a0a ldr r2, [pc, #40] @ (8003280 <SysTick_Config+0x40>)
8003258: 687b ldr r3, [r7, #4]
800325a: 3b01 subs r3, #1
800325c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800325e: 210f movs r1, #15
8003260: f04f 30ff mov.w r0, #4294967295
8003264: f7ff ff90 bl 8003188 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003268: 4b05 ldr r3, [pc, #20] @ (8003280 <SysTick_Config+0x40>)
800326a: 2200 movs r2, #0
800326c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800326e: 4b04 ldr r3, [pc, #16] @ (8003280 <SysTick_Config+0x40>)
8003270: 2207 movs r2, #7
8003272: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003274: 2300 movs r3, #0
}
8003276: 4618 mov r0, r3
8003278: 3708 adds r7, #8
800327a: 46bd mov sp, r7
800327c: bd80 pop {r7, pc}
800327e: bf00 nop
8003280: e000e010 .word 0xe000e010
08003284 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003284: b580 push {r7, lr}
8003286: b082 sub sp, #8
8003288: af00 add r7, sp, #0
800328a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800328c: 6878 ldr r0, [r7, #4]
800328e: f7ff ff2d bl 80030ec <__NVIC_SetPriorityGrouping>
}
8003292: bf00 nop
8003294: 3708 adds r7, #8
8003296: 46bd mov sp, r7
8003298: bd80 pop {r7, pc}
0800329a <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800329a: b580 push {r7, lr}
800329c: b086 sub sp, #24
800329e: af00 add r7, sp, #0
80032a0: 4603 mov r3, r0
80032a2: 60b9 str r1, [r7, #8]
80032a4: 607a str r2, [r7, #4]
80032a6: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80032a8: 2300 movs r3, #0
80032aa: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80032ac: f7ff ff42 bl 8003134 <__NVIC_GetPriorityGrouping>
80032b0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80032b2: 687a ldr r2, [r7, #4]
80032b4: 68b9 ldr r1, [r7, #8]
80032b6: 6978 ldr r0, [r7, #20]
80032b8: f7ff ff90 bl 80031dc <NVIC_EncodePriority>
80032bc: 4602 mov r2, r0
80032be: f997 300f ldrsb.w r3, [r7, #15]
80032c2: 4611 mov r1, r2
80032c4: 4618 mov r0, r3
80032c6: f7ff ff5f bl 8003188 <__NVIC_SetPriority>
}
80032ca: bf00 nop
80032cc: 3718 adds r7, #24
80032ce: 46bd mov sp, r7
80032d0: bd80 pop {r7, pc}
080032d2 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80032d2: b580 push {r7, lr}
80032d4: b082 sub sp, #8
80032d6: af00 add r7, sp, #0
80032d8: 4603 mov r3, r0
80032da: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80032dc: f997 3007 ldrsb.w r3, [r7, #7]
80032e0: 4618 mov r0, r3
80032e2: f7ff ff35 bl 8003150 <__NVIC_EnableIRQ>
}
80032e6: bf00 nop
80032e8: 3708 adds r7, #8
80032ea: 46bd mov sp, r7
80032ec: bd80 pop {r7, pc}
080032ee <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80032ee: b580 push {r7, lr}
80032f0: b082 sub sp, #8
80032f2: af00 add r7, sp, #0
80032f4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80032f6: 6878 ldr r0, [r7, #4]
80032f8: f7ff ffa2 bl 8003240 <SysTick_Config>
80032fc: 4603 mov r3, r0
}
80032fe: 4618 mov r0, r3
8003300: 3708 adds r7, #8
8003302: 46bd mov sp, r7
8003304: bd80 pop {r7, pc}
08003306 <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003306: b480 push {r7}
8003308: b085 sub sp, #20
800330a: af00 add r7, sp, #0
800330c: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800330e: 2300 movs r3, #0
8003310: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
8003312: 687b ldr r3, [r7, #4]
8003314: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003318: b2db uxtb r3, r3
800331a: 2b02 cmp r3, #2
800331c: d008 beq.n 8003330 <HAL_DMA_Abort+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800331e: 687b ldr r3, [r7, #4]
8003320: 2204 movs r2, #4
8003322: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003324: 687b ldr r3, [r7, #4]
8003326: 2200 movs r2, #0
8003328: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800332c: 2301 movs r3, #1
800332e: e020 b.n 8003372 <HAL_DMA_Abort+0x6c>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003330: 687b ldr r3, [r7, #4]
8003332: 681b ldr r3, [r3, #0]
8003334: 681a ldr r2, [r3, #0]
8003336: 687b ldr r3, [r7, #4]
8003338: 681b ldr r3, [r3, #0]
800333a: f022 020e bic.w r2, r2, #14
800333e: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003340: 687b ldr r3, [r7, #4]
8003342: 681b ldr r3, [r3, #0]
8003344: 681a ldr r2, [r3, #0]
8003346: 687b ldr r3, [r7, #4]
8003348: 681b ldr r3, [r3, #0]
800334a: f022 0201 bic.w r2, r2, #1
800334e: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8003350: 687b ldr r3, [r7, #4]
8003352: 6c1a ldr r2, [r3, #64] @ 0x40
8003354: 687b ldr r3, [r7, #4]
8003356: 6bdb ldr r3, [r3, #60] @ 0x3c
8003358: 2101 movs r1, #1
800335a: fa01 f202 lsl.w r2, r1, r2
800335e: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003360: 687b ldr r3, [r7, #4]
8003362: 2201 movs r2, #1
8003364: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003368: 687b ldr r3, [r7, #4]
800336a: 2200 movs r2, #0
800336c: f883 2020 strb.w r2, [r3, #32]
return status;
8003370: 7bfb ldrb r3, [r7, #15]
}
8003372: 4618 mov r0, r3
8003374: 3714 adds r7, #20
8003376: 46bd mov sp, r7
8003378: bc80 pop {r7}
800337a: 4770 bx lr
0800337c <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
800337c: b580 push {r7, lr}
800337e: b084 sub sp, #16
8003380: af00 add r7, sp, #0
8003382: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003384: 2300 movs r3, #0
8003386: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8003388: 687b ldr r3, [r7, #4]
800338a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
800338e: b2db uxtb r3, r3
8003390: 2b02 cmp r3, #2
8003392: d005 beq.n 80033a0 <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003394: 687b ldr r3, [r7, #4]
8003396: 2204 movs r2, #4
8003398: 639a str r2, [r3, #56] @ 0x38
status = HAL_ERROR;
800339a: 2301 movs r3, #1
800339c: 73fb strb r3, [r7, #15]
800339e: e051 b.n 8003444 <HAL_DMA_Abort_IT+0xc8>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80033a0: 687b ldr r3, [r7, #4]
80033a2: 681b ldr r3, [r3, #0]
80033a4: 681a ldr r2, [r3, #0]
80033a6: 687b ldr r3, [r7, #4]
80033a8: 681b ldr r3, [r3, #0]
80033aa: f022 020e bic.w r2, r2, #14
80033ae: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80033b0: 687b ldr r3, [r7, #4]
80033b2: 681b ldr r3, [r3, #0]
80033b4: 681a ldr r2, [r3, #0]
80033b6: 687b ldr r3, [r7, #4]
80033b8: 681b ldr r3, [r3, #0]
80033ba: f022 0201 bic.w r2, r2, #1
80033be: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
80033c0: 687b ldr r3, [r7, #4]
80033c2: 681b ldr r3, [r3, #0]
80033c4: 4a22 ldr r2, [pc, #136] @ (8003450 <HAL_DMA_Abort_IT+0xd4>)
80033c6: 4293 cmp r3, r2
80033c8: d029 beq.n 800341e <HAL_DMA_Abort_IT+0xa2>
80033ca: 687b ldr r3, [r7, #4]
80033cc: 681b ldr r3, [r3, #0]
80033ce: 4a21 ldr r2, [pc, #132] @ (8003454 <HAL_DMA_Abort_IT+0xd8>)
80033d0: 4293 cmp r3, r2
80033d2: d022 beq.n 800341a <HAL_DMA_Abort_IT+0x9e>
80033d4: 687b ldr r3, [r7, #4]
80033d6: 681b ldr r3, [r3, #0]
80033d8: 4a1f ldr r2, [pc, #124] @ (8003458 <HAL_DMA_Abort_IT+0xdc>)
80033da: 4293 cmp r3, r2
80033dc: d01a beq.n 8003414 <HAL_DMA_Abort_IT+0x98>
80033de: 687b ldr r3, [r7, #4]
80033e0: 681b ldr r3, [r3, #0]
80033e2: 4a1e ldr r2, [pc, #120] @ (800345c <HAL_DMA_Abort_IT+0xe0>)
80033e4: 4293 cmp r3, r2
80033e6: d012 beq.n 800340e <HAL_DMA_Abort_IT+0x92>
80033e8: 687b ldr r3, [r7, #4]
80033ea: 681b ldr r3, [r3, #0]
80033ec: 4a1c ldr r2, [pc, #112] @ (8003460 <HAL_DMA_Abort_IT+0xe4>)
80033ee: 4293 cmp r3, r2
80033f0: d00a beq.n 8003408 <HAL_DMA_Abort_IT+0x8c>
80033f2: 687b ldr r3, [r7, #4]
80033f4: 681b ldr r3, [r3, #0]
80033f6: 4a1b ldr r2, [pc, #108] @ (8003464 <HAL_DMA_Abort_IT+0xe8>)
80033f8: 4293 cmp r3, r2
80033fa: d102 bne.n 8003402 <HAL_DMA_Abort_IT+0x86>
80033fc: f44f 1380 mov.w r3, #1048576 @ 0x100000
8003400: e00e b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
8003402: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8003406: e00b b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
8003408: f44f 3380 mov.w r3, #65536 @ 0x10000
800340c: e008 b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
800340e: f44f 5380 mov.w r3, #4096 @ 0x1000
8003412: e005 b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
8003414: f44f 7380 mov.w r3, #256 @ 0x100
8003418: e002 b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
800341a: 2310 movs r3, #16
800341c: e000 b.n 8003420 <HAL_DMA_Abort_IT+0xa4>
800341e: 2301 movs r3, #1
8003420: 4a11 ldr r2, [pc, #68] @ (8003468 <HAL_DMA_Abort_IT+0xec>)
8003422: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003424: 687b ldr r3, [r7, #4]
8003426: 2201 movs r2, #1
8003428: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800342c: 687b ldr r3, [r7, #4]
800342e: 2200 movs r2, #0
8003430: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
8003434: 687b ldr r3, [r7, #4]
8003436: 6b5b ldr r3, [r3, #52] @ 0x34
8003438: 2b00 cmp r3, #0
800343a: d003 beq.n 8003444 <HAL_DMA_Abort_IT+0xc8>
{
hdma->XferAbortCallback(hdma);
800343c: 687b ldr r3, [r7, #4]
800343e: 6b5b ldr r3, [r3, #52] @ 0x34
8003440: 6878 ldr r0, [r7, #4]
8003442: 4798 blx r3
}
}
return status;
8003444: 7bfb ldrb r3, [r7, #15]
}
8003446: 4618 mov r0, r3
8003448: 3710 adds r7, #16
800344a: 46bd mov sp, r7
800344c: bd80 pop {r7, pc}
800344e: bf00 nop
8003450: 40020008 .word 0x40020008
8003454: 4002001c .word 0x4002001c
8003458: 40020030 .word 0x40020030
800345c: 40020044 .word 0x40020044
8003460: 40020058 .word 0x40020058
8003464: 4002006c .word 0x4002006c
8003468: 40020000 .word 0x40020000
0800346c <HAL_FLASH_Program>:
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
800346c: b5f0 push {r4, r5, r6, r7, lr}
800346e: b087 sub sp, #28
8003470: af00 add r7, sp, #0
8003472: 60f8 str r0, [r7, #12]
8003474: 60b9 str r1, [r7, #8]
8003476: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
800347a: 2301 movs r3, #1
800347c: 75fb strb r3, [r7, #23]
uint8_t index = 0;
800347e: 2300 movs r3, #0
8003480: 75bb strb r3, [r7, #22]
uint8_t nbiterations = 0;
8003482: 2300 movs r3, #0
8003484: 757b strb r3, [r7, #21]
/* Process Locked */
__HAL_LOCK(&pFlash);
8003486: 4b2f ldr r3, [pc, #188] @ (8003544 <HAL_FLASH_Program+0xd8>)
8003488: 7e1b ldrb r3, [r3, #24]
800348a: 2b01 cmp r3, #1
800348c: d101 bne.n 8003492 <HAL_FLASH_Program+0x26>
800348e: 2302 movs r3, #2
8003490: e054 b.n 800353c <HAL_FLASH_Program+0xd0>
8003492: 4b2c ldr r3, [pc, #176] @ (8003544 <HAL_FLASH_Program+0xd8>)
8003494: 2201 movs r2, #1
8003496: 761a strb r2, [r3, #24]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8003498: f24c 3050 movw r0, #50000 @ 0xc350
800349c: f000 f8a8 bl 80035f0 <FLASH_WaitForLastOperation>
80034a0: 4603 mov r3, r0
80034a2: 75fb strb r3, [r7, #23]
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
80034a4: 7dfb ldrb r3, [r7, #23]
80034a6: 2b00 cmp r3, #0
80034a8: d144 bne.n 8003534 <HAL_FLASH_Program+0xc8>
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
80034aa: 68fb ldr r3, [r7, #12]
80034ac: 2b01 cmp r3, #1
80034ae: d102 bne.n 80034b6 <HAL_FLASH_Program+0x4a>
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
80034b0: 2301 movs r3, #1
80034b2: 757b strb r3, [r7, #21]
80034b4: e007 b.n 80034c6 <HAL_FLASH_Program+0x5a>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
80034b6: 68fb ldr r3, [r7, #12]
80034b8: 2b02 cmp r3, #2
80034ba: d102 bne.n 80034c2 <HAL_FLASH_Program+0x56>
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
80034bc: 2302 movs r3, #2
80034be: 757b strb r3, [r7, #21]
80034c0: e001 b.n 80034c6 <HAL_FLASH_Program+0x5a>
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
80034c2: 2304 movs r3, #4
80034c4: 757b strb r3, [r7, #21]
}
for (index = 0U; index < nbiterations; index++)
80034c6: 2300 movs r3, #0
80034c8: 75bb strb r3, [r7, #22]
80034ca: e02d b.n 8003528 <HAL_FLASH_Program+0xbc>
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
80034cc: 7dbb ldrb r3, [r7, #22]
80034ce: 005a lsls r2, r3, #1
80034d0: 68bb ldr r3, [r7, #8]
80034d2: eb02 0c03 add.w ip, r2, r3
80034d6: 7dbb ldrb r3, [r7, #22]
80034d8: 0119 lsls r1, r3, #4
80034da: e9d7 2300 ldrd r2, r3, [r7]
80034de: f1c1 0620 rsb r6, r1, #32
80034e2: f1a1 0020 sub.w r0, r1, #32
80034e6: fa22 f401 lsr.w r4, r2, r1
80034ea: fa03 f606 lsl.w r6, r3, r6
80034ee: 4334 orrs r4, r6
80034f0: fa23 f000 lsr.w r0, r3, r0
80034f4: 4304 orrs r4, r0
80034f6: fa23 f501 lsr.w r5, r3, r1
80034fa: b2a3 uxth r3, r4
80034fc: 4619 mov r1, r3
80034fe: 4660 mov r0, ip
8003500: f000 f85a bl 80035b8 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8003504: f24c 3050 movw r0, #50000 @ 0xc350
8003508: f000 f872 bl 80035f0 <FLASH_WaitForLastOperation>
800350c: 4603 mov r3, r0
800350e: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
8003510: 4b0d ldr r3, [pc, #52] @ (8003548 <HAL_FLASH_Program+0xdc>)
8003512: 691b ldr r3, [r3, #16]
8003514: 4a0c ldr r2, [pc, #48] @ (8003548 <HAL_FLASH_Program+0xdc>)
8003516: f023 0301 bic.w r3, r3, #1
800351a: 6113 str r3, [r2, #16]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
800351c: 7dfb ldrb r3, [r7, #23]
800351e: 2b00 cmp r3, #0
8003520: d107 bne.n 8003532 <HAL_FLASH_Program+0xc6>
for (index = 0U; index < nbiterations; index++)
8003522: 7dbb ldrb r3, [r7, #22]
8003524: 3301 adds r3, #1
8003526: 75bb strb r3, [r7, #22]
8003528: 7dba ldrb r2, [r7, #22]
800352a: 7d7b ldrb r3, [r7, #21]
800352c: 429a cmp r2, r3
800352e: d3cd bcc.n 80034cc <HAL_FLASH_Program+0x60>
8003530: e000 b.n 8003534 <HAL_FLASH_Program+0xc8>
{
break;
8003532: bf00 nop
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8003534: 4b03 ldr r3, [pc, #12] @ (8003544 <HAL_FLASH_Program+0xd8>)
8003536: 2200 movs r2, #0
8003538: 761a strb r2, [r3, #24]
return status;
800353a: 7dfb ldrb r3, [r7, #23]
}
800353c: 4618 mov r0, r3
800353e: 371c adds r7, #28
8003540: 46bd mov sp, r7
8003542: bdf0 pop {r4, r5, r6, r7, pc}
8003544: 200006f0 .word 0x200006f0
8003548: 40022000 .word 0x40022000
0800354c <HAL_FLASH_Unlock>:
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
800354c: b480 push {r7}
800354e: b083 sub sp, #12
8003550: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8003552: 2300 movs r3, #0
8003554: 71fb strb r3, [r7, #7]
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
8003556: 4b0d ldr r3, [pc, #52] @ (800358c <HAL_FLASH_Unlock+0x40>)
8003558: 691b ldr r3, [r3, #16]
800355a: f003 0380 and.w r3, r3, #128 @ 0x80
800355e: 2b00 cmp r3, #0
8003560: d00d beq.n 800357e <HAL_FLASH_Unlock+0x32>
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
8003562: 4b0a ldr r3, [pc, #40] @ (800358c <HAL_FLASH_Unlock+0x40>)
8003564: 4a0a ldr r2, [pc, #40] @ (8003590 <HAL_FLASH_Unlock+0x44>)
8003566: 605a str r2, [r3, #4]
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
8003568: 4b08 ldr r3, [pc, #32] @ (800358c <HAL_FLASH_Unlock+0x40>)
800356a: 4a0a ldr r2, [pc, #40] @ (8003594 <HAL_FLASH_Unlock+0x48>)
800356c: 605a str r2, [r3, #4]
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
800356e: 4b07 ldr r3, [pc, #28] @ (800358c <HAL_FLASH_Unlock+0x40>)
8003570: 691b ldr r3, [r3, #16]
8003572: f003 0380 and.w r3, r3, #128 @ 0x80
8003576: 2b00 cmp r3, #0
8003578: d001 beq.n 800357e <HAL_FLASH_Unlock+0x32>
{
status = HAL_ERROR;
800357a: 2301 movs r3, #1
800357c: 71fb strb r3, [r7, #7]
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
800357e: 79fb ldrb r3, [r7, #7]
}
8003580: 4618 mov r0, r3
8003582: 370c adds r7, #12
8003584: 46bd mov sp, r7
8003586: bc80 pop {r7}
8003588: 4770 bx lr
800358a: bf00 nop
800358c: 40022000 .word 0x40022000
8003590: 45670123 .word 0x45670123
8003594: cdef89ab .word 0xcdef89ab
08003598 <HAL_FLASH_Lock>:
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
8003598: b480 push {r7}
800359a: af00 add r7, sp, #0
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
800359c: 4b05 ldr r3, [pc, #20] @ (80035b4 <HAL_FLASH_Lock+0x1c>)
800359e: 691b ldr r3, [r3, #16]
80035a0: 4a04 ldr r2, [pc, #16] @ (80035b4 <HAL_FLASH_Lock+0x1c>)
80035a2: f043 0380 orr.w r3, r3, #128 @ 0x80
80035a6: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
80035a8: 2300 movs r3, #0
}
80035aa: 4618 mov r0, r3
80035ac: 46bd mov sp, r7
80035ae: bc80 pop {r7}
80035b0: 4770 bx lr
80035b2: bf00 nop
80035b4: 40022000 .word 0x40022000
080035b8 <FLASH_Program_HalfWord>:
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
80035b8: b480 push {r7}
80035ba: b083 sub sp, #12
80035bc: af00 add r7, sp, #0
80035be: 6078 str r0, [r7, #4]
80035c0: 460b mov r3, r1
80035c2: 807b strh r3, [r7, #2]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80035c4: 4b08 ldr r3, [pc, #32] @ (80035e8 <FLASH_Program_HalfWord+0x30>)
80035c6: 2200 movs r2, #0
80035c8: 61da str r2, [r3, #28]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
80035ca: 4b08 ldr r3, [pc, #32] @ (80035ec <FLASH_Program_HalfWord+0x34>)
80035cc: 691b ldr r3, [r3, #16]
80035ce: 4a07 ldr r2, [pc, #28] @ (80035ec <FLASH_Program_HalfWord+0x34>)
80035d0: f043 0301 orr.w r3, r3, #1
80035d4: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
80035d6: 687b ldr r3, [r7, #4]
80035d8: 887a ldrh r2, [r7, #2]
80035da: 801a strh r2, [r3, #0]
}
80035dc: bf00 nop
80035de: 370c adds r7, #12
80035e0: 46bd mov sp, r7
80035e2: bc80 pop {r7}
80035e4: 4770 bx lr
80035e6: bf00 nop
80035e8: 200006f0 .word 0x200006f0
80035ec: 40022000 .word 0x40022000
080035f0 <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
80035f0: b580 push {r7, lr}
80035f2: b084 sub sp, #16
80035f4: af00 add r7, sp, #0
80035f6: 6078 str r0, [r7, #4]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
80035f8: f7ff fb38 bl 8002c6c <HAL_GetTick>
80035fc: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
80035fe: e010 b.n 8003622 <FLASH_WaitForLastOperation+0x32>
{
if (Timeout != HAL_MAX_DELAY)
8003600: 687b ldr r3, [r7, #4]
8003602: f1b3 3fff cmp.w r3, #4294967295
8003606: d00c beq.n 8003622 <FLASH_WaitForLastOperation+0x32>
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
8003608: 687b ldr r3, [r7, #4]
800360a: 2b00 cmp r3, #0
800360c: d007 beq.n 800361e <FLASH_WaitForLastOperation+0x2e>
800360e: f7ff fb2d bl 8002c6c <HAL_GetTick>
8003612: 4602 mov r2, r0
8003614: 68fb ldr r3, [r7, #12]
8003616: 1ad3 subs r3, r2, r3
8003618: 687a ldr r2, [r7, #4]
800361a: 429a cmp r2, r3
800361c: d201 bcs.n 8003622 <FLASH_WaitForLastOperation+0x32>
{
return HAL_TIMEOUT;
800361e: 2303 movs r3, #3
8003620: e025 b.n 800366e <FLASH_WaitForLastOperation+0x7e>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
8003622: 4b15 ldr r3, [pc, #84] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
8003624: 68db ldr r3, [r3, #12]
8003626: f003 0301 and.w r3, r3, #1
800362a: 2b00 cmp r3, #0
800362c: d1e8 bne.n 8003600 <FLASH_WaitForLastOperation+0x10>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
800362e: 4b12 ldr r3, [pc, #72] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
8003630: 68db ldr r3, [r3, #12]
8003632: f003 0320 and.w r3, r3, #32
8003636: 2b00 cmp r3, #0
8003638: d002 beq.n 8003640 <FLASH_WaitForLastOperation+0x50>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
800363a: 4b0f ldr r3, [pc, #60] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
800363c: 2220 movs r2, #32
800363e: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003640: 4b0d ldr r3, [pc, #52] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
8003642: 68db ldr r3, [r3, #12]
8003644: f003 0310 and.w r3, r3, #16
8003648: 2b00 cmp r3, #0
800364a: d10b bne.n 8003664 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
800364c: 4b0a ldr r3, [pc, #40] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
800364e: 69db ldr r3, [r3, #28]
8003650: f003 0301 and.w r3, r3, #1
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003654: 2b00 cmp r3, #0
8003656: d105 bne.n 8003664 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8003658: 4b07 ldr r3, [pc, #28] @ (8003678 <FLASH_WaitForLastOperation+0x88>)
800365a: 68db ldr r3, [r3, #12]
800365c: f003 0304 and.w r3, r3, #4
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
8003660: 2b00 cmp r3, #0
8003662: d003 beq.n 800366c <FLASH_WaitForLastOperation+0x7c>
{
/*Save the error code*/
FLASH_SetErrorCode();
8003664: f000 f80a bl 800367c <FLASH_SetErrorCode>
return HAL_ERROR;
8003668: 2301 movs r3, #1
800366a: e000 b.n 800366e <FLASH_WaitForLastOperation+0x7e>
}
/* There is no error flag set */
return HAL_OK;
800366c: 2300 movs r3, #0
}
800366e: 4618 mov r0, r3
8003670: 3710 adds r7, #16
8003672: 46bd mov sp, r7
8003674: bd80 pop {r7, pc}
8003676: bf00 nop
8003678: 40022000 .word 0x40022000
0800367c <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
800367c: b480 push {r7}
800367e: b083 sub sp, #12
8003680: af00 add r7, sp, #0
uint32_t flags = 0U;
8003682: 2300 movs r3, #0
8003684: 607b str r3, [r7, #4]
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
8003686: 4b23 ldr r3, [pc, #140] @ (8003714 <FLASH_SetErrorCode+0x98>)
8003688: 68db ldr r3, [r3, #12]
800368a: f003 0310 and.w r3, r3, #16
800368e: 2b00 cmp r3, #0
8003690: d009 beq.n 80036a6 <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
8003692: 4b21 ldr r3, [pc, #132] @ (8003718 <FLASH_SetErrorCode+0x9c>)
8003694: 69db ldr r3, [r3, #28]
8003696: f043 0302 orr.w r3, r3, #2
800369a: 4a1f ldr r2, [pc, #124] @ (8003718 <FLASH_SetErrorCode+0x9c>)
800369c: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
800369e: 687b ldr r3, [r7, #4]
80036a0: f043 0310 orr.w r3, r3, #16
80036a4: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
80036a6: 4b1b ldr r3, [pc, #108] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036a8: 68db ldr r3, [r3, #12]
80036aa: f003 0304 and.w r3, r3, #4
80036ae: 2b00 cmp r3, #0
80036b0: d009 beq.n 80036c6 <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
80036b2: 4b19 ldr r3, [pc, #100] @ (8003718 <FLASH_SetErrorCode+0x9c>)
80036b4: 69db ldr r3, [r3, #28]
80036b6: f043 0301 orr.w r3, r3, #1
80036ba: 4a17 ldr r2, [pc, #92] @ (8003718 <FLASH_SetErrorCode+0x9c>)
80036bc: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
80036be: 687b ldr r3, [r7, #4]
80036c0: f043 0304 orr.w r3, r3, #4
80036c4: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
80036c6: 4b13 ldr r3, [pc, #76] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036c8: 69db ldr r3, [r3, #28]
80036ca: f003 0301 and.w r3, r3, #1
80036ce: 2b00 cmp r3, #0
80036d0: d00b beq.n 80036ea <FLASH_SetErrorCode+0x6e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
80036d2: 4b11 ldr r3, [pc, #68] @ (8003718 <FLASH_SetErrorCode+0x9c>)
80036d4: 69db ldr r3, [r3, #28]
80036d6: f043 0304 orr.w r3, r3, #4
80036da: 4a0f ldr r2, [pc, #60] @ (8003718 <FLASH_SetErrorCode+0x9c>)
80036dc: 61d3 str r3, [r2, #28]
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
80036de: 4b0d ldr r3, [pc, #52] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036e0: 69db ldr r3, [r3, #28]
80036e2: 4a0c ldr r2, [pc, #48] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036e4: f023 0301 bic.w r3, r3, #1
80036e8: 61d3 str r3, [r2, #28]
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
80036ea: 687b ldr r3, [r7, #4]
80036ec: f240 1201 movw r2, #257 @ 0x101
80036f0: 4293 cmp r3, r2
80036f2: d106 bne.n 8003702 <FLASH_SetErrorCode+0x86>
80036f4: 4b07 ldr r3, [pc, #28] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036f6: 69db ldr r3, [r3, #28]
80036f8: 4a06 ldr r2, [pc, #24] @ (8003714 <FLASH_SetErrorCode+0x98>)
80036fa: f023 0301 bic.w r3, r3, #1
80036fe: 61d3 str r3, [r2, #28]
}
8003700: e002 b.n 8003708 <FLASH_SetErrorCode+0x8c>
__HAL_FLASH_CLEAR_FLAG(flags);
8003702: 4a04 ldr r2, [pc, #16] @ (8003714 <FLASH_SetErrorCode+0x98>)
8003704: 687b ldr r3, [r7, #4]
8003706: 60d3 str r3, [r2, #12]
}
8003708: bf00 nop
800370a: 370c adds r7, #12
800370c: 46bd mov sp, r7
800370e: bc80 pop {r7}
8003710: 4770 bx lr
8003712: bf00 nop
8003714: 40022000 .word 0x40022000
8003718: 200006f0 .word 0x200006f0
0800371c <HAL_FLASHEx_Erase>:
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
800371c: b580 push {r7, lr}
800371e: b084 sub sp, #16
8003720: af00 add r7, sp, #0
8003722: 6078 str r0, [r7, #4]
8003724: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
8003726: 2301 movs r3, #1
8003728: 73fb strb r3, [r7, #15]
uint32_t address = 0U;
800372a: 2300 movs r3, #0
800372c: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
800372e: 4b2f ldr r3, [pc, #188] @ (80037ec <HAL_FLASHEx_Erase+0xd0>)
8003730: 7e1b ldrb r3, [r3, #24]
8003732: 2b01 cmp r3, #1
8003734: d101 bne.n 800373a <HAL_FLASHEx_Erase+0x1e>
8003736: 2302 movs r3, #2
8003738: e053 b.n 80037e2 <HAL_FLASHEx_Erase+0xc6>
800373a: 4b2c ldr r3, [pc, #176] @ (80037ec <HAL_FLASHEx_Erase+0xd0>)
800373c: 2201 movs r2, #1
800373e: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
8003740: 687b ldr r3, [r7, #4]
8003742: 681b ldr r3, [r3, #0]
8003744: 2b02 cmp r3, #2
8003746: d116 bne.n 8003776 <HAL_FLASHEx_Erase+0x5a>
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003748: f24c 3050 movw r0, #50000 @ 0xc350
800374c: f7ff ff50 bl 80035f0 <FLASH_WaitForLastOperation>
8003750: 4603 mov r3, r0
8003752: 2b00 cmp r3, #0
8003754: d141 bne.n 80037da <HAL_FLASHEx_Erase+0xbe>
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
8003756: 2001 movs r0, #1
8003758: f000 f84c bl 80037f4 <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
800375c: f24c 3050 movw r0, #50000 @ 0xc350
8003760: f7ff ff46 bl 80035f0 <FLASH_WaitForLastOperation>
8003764: 4603 mov r3, r0
8003766: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
8003768: 4b21 ldr r3, [pc, #132] @ (80037f0 <HAL_FLASHEx_Erase+0xd4>)
800376a: 691b ldr r3, [r3, #16]
800376c: 4a20 ldr r2, [pc, #128] @ (80037f0 <HAL_FLASHEx_Erase+0xd4>)
800376e: f023 0304 bic.w r3, r3, #4
8003772: 6113 str r3, [r2, #16]
8003774: e031 b.n 80037da <HAL_FLASHEx_Erase+0xbe>
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003776: f24c 3050 movw r0, #50000 @ 0xc350
800377a: f7ff ff39 bl 80035f0 <FLASH_WaitForLastOperation>
800377e: 4603 mov r3, r0
8003780: 2b00 cmp r3, #0
8003782: d12a bne.n 80037da <HAL_FLASHEx_Erase+0xbe>
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
8003784: 683b ldr r3, [r7, #0]
8003786: f04f 32ff mov.w r2, #4294967295
800378a: 601a str r2, [r3, #0]
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
800378c: 687b ldr r3, [r7, #4]
800378e: 689b ldr r3, [r3, #8]
8003790: 60bb str r3, [r7, #8]
8003792: e019 b.n 80037c8 <HAL_FLASHEx_Erase+0xac>
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
8003794: 68b8 ldr r0, [r7, #8]
8003796: f000 f849 bl 800382c <FLASH_PageErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
800379a: f24c 3050 movw r0, #50000 @ 0xc350
800379e: f7ff ff27 bl 80035f0 <FLASH_WaitForLastOperation>
80037a2: 4603 mov r3, r0
80037a4: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
80037a6: 4b12 ldr r3, [pc, #72] @ (80037f0 <HAL_FLASHEx_Erase+0xd4>)
80037a8: 691b ldr r3, [r3, #16]
80037aa: 4a11 ldr r2, [pc, #68] @ (80037f0 <HAL_FLASHEx_Erase+0xd4>)
80037ac: f023 0302 bic.w r3, r3, #2
80037b0: 6113 str r3, [r2, #16]
if (status != HAL_OK)
80037b2: 7bfb ldrb r3, [r7, #15]
80037b4: 2b00 cmp r3, #0
80037b6: d003 beq.n 80037c0 <HAL_FLASHEx_Erase+0xa4>
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
80037b8: 683b ldr r3, [r7, #0]
80037ba: 68ba ldr r2, [r7, #8]
80037bc: 601a str r2, [r3, #0]
break;
80037be: e00c b.n 80037da <HAL_FLASHEx_Erase+0xbe>
address += FLASH_PAGE_SIZE)
80037c0: 68bb ldr r3, [r7, #8]
80037c2: f503 6380 add.w r3, r3, #1024 @ 0x400
80037c6: 60bb str r3, [r7, #8]
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
80037c8: 687b ldr r3, [r7, #4]
80037ca: 68db ldr r3, [r3, #12]
80037cc: 029a lsls r2, r3, #10
80037ce: 687b ldr r3, [r7, #4]
80037d0: 689b ldr r3, [r3, #8]
80037d2: 4413 add r3, r2
80037d4: 68ba ldr r2, [r7, #8]
80037d6: 429a cmp r2, r3
80037d8: d3dc bcc.n 8003794 <HAL_FLASHEx_Erase+0x78>
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
80037da: 4b04 ldr r3, [pc, #16] @ (80037ec <HAL_FLASHEx_Erase+0xd0>)
80037dc: 2200 movs r2, #0
80037de: 761a strb r2, [r3, #24]
return status;
80037e0: 7bfb ldrb r3, [r7, #15]
}
80037e2: 4618 mov r0, r3
80037e4: 3710 adds r7, #16
80037e6: 46bd mov sp, r7
80037e8: bd80 pop {r7, pc}
80037ea: bf00 nop
80037ec: 200006f0 .word 0x200006f0
80037f0: 40022000 .word 0x40022000
080037f4 <FLASH_MassErase>:
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
80037f4: b480 push {r7}
80037f6: b083 sub sp, #12
80037f8: af00 add r7, sp, #0
80037fa: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80037fc: 4b09 ldr r3, [pc, #36] @ (8003824 <FLASH_MassErase+0x30>)
80037fe: 2200 movs r2, #0
8003800: 61da str r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
8003802: 4b09 ldr r3, [pc, #36] @ (8003828 <FLASH_MassErase+0x34>)
8003804: 691b ldr r3, [r3, #16]
8003806: 4a08 ldr r2, [pc, #32] @ (8003828 <FLASH_MassErase+0x34>)
8003808: f043 0304 orr.w r3, r3, #4
800380c: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
800380e: 4b06 ldr r3, [pc, #24] @ (8003828 <FLASH_MassErase+0x34>)
8003810: 691b ldr r3, [r3, #16]
8003812: 4a05 ldr r2, [pc, #20] @ (8003828 <FLASH_MassErase+0x34>)
8003814: f043 0340 orr.w r3, r3, #64 @ 0x40
8003818: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
800381a: bf00 nop
800381c: 370c adds r7, #12
800381e: 46bd mov sp, r7
8003820: bc80 pop {r7}
8003822: 4770 bx lr
8003824: 200006f0 .word 0x200006f0
8003828: 40022000 .word 0x40022000
0800382c <FLASH_PageErase>:
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
800382c: b480 push {r7}
800382e: b083 sub sp, #12
8003830: af00 add r7, sp, #0
8003832: 6078 str r0, [r7, #4]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003834: 4b0b ldr r3, [pc, #44] @ (8003864 <FLASH_PageErase+0x38>)
8003836: 2200 movs r2, #0
8003838: 61da str r2, [r3, #28]
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
800383a: 4b0b ldr r3, [pc, #44] @ (8003868 <FLASH_PageErase+0x3c>)
800383c: 691b ldr r3, [r3, #16]
800383e: 4a0a ldr r2, [pc, #40] @ (8003868 <FLASH_PageErase+0x3c>)
8003840: f043 0302 orr.w r3, r3, #2
8003844: 6113 str r3, [r2, #16]
WRITE_REG(FLASH->AR, PageAddress);
8003846: 4a08 ldr r2, [pc, #32] @ (8003868 <FLASH_PageErase+0x3c>)
8003848: 687b ldr r3, [r7, #4]
800384a: 6153 str r3, [r2, #20]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
800384c: 4b06 ldr r3, [pc, #24] @ (8003868 <FLASH_PageErase+0x3c>)
800384e: 691b ldr r3, [r3, #16]
8003850: 4a05 ldr r2, [pc, #20] @ (8003868 <FLASH_PageErase+0x3c>)
8003852: f043 0340 orr.w r3, r3, #64 @ 0x40
8003856: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8003858: bf00 nop
800385a: 370c adds r7, #12
800385c: 46bd mov sp, r7
800385e: bc80 pop {r7}
8003860: 4770 bx lr
8003862: bf00 nop
8003864: 200006f0 .word 0x200006f0
8003868: 40022000 .word 0x40022000
0800386c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800386c: b480 push {r7}
800386e: b08b sub sp, #44 @ 0x2c
8003870: af00 add r7, sp, #0
8003872: 6078 str r0, [r7, #4]
8003874: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003876: 2300 movs r3, #0
8003878: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800387a: 2300 movs r3, #0
800387c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800387e: e169 b.n 8003b54 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8003880: 2201 movs r2, #1
8003882: 6a7b ldr r3, [r7, #36] @ 0x24
8003884: fa02 f303 lsl.w r3, r2, r3
8003888: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800388a: 683b ldr r3, [r7, #0]
800388c: 681b ldr r3, [r3, #0]
800388e: 69fa ldr r2, [r7, #28]
8003890: 4013 ands r3, r2
8003892: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8003894: 69ba ldr r2, [r7, #24]
8003896: 69fb ldr r3, [r7, #28]
8003898: 429a cmp r2, r3
800389a: f040 8158 bne.w 8003b4e <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800389e: 683b ldr r3, [r7, #0]
80038a0: 685b ldr r3, [r3, #4]
80038a2: 4a9a ldr r2, [pc, #616] @ (8003b0c <HAL_GPIO_Init+0x2a0>)
80038a4: 4293 cmp r3, r2
80038a6: d05e beq.n 8003966 <HAL_GPIO_Init+0xfa>
80038a8: 4a98 ldr r2, [pc, #608] @ (8003b0c <HAL_GPIO_Init+0x2a0>)
80038aa: 4293 cmp r3, r2
80038ac: d875 bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038ae: 4a98 ldr r2, [pc, #608] @ (8003b10 <HAL_GPIO_Init+0x2a4>)
80038b0: 4293 cmp r3, r2
80038b2: d058 beq.n 8003966 <HAL_GPIO_Init+0xfa>
80038b4: 4a96 ldr r2, [pc, #600] @ (8003b10 <HAL_GPIO_Init+0x2a4>)
80038b6: 4293 cmp r3, r2
80038b8: d86f bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038ba: 4a96 ldr r2, [pc, #600] @ (8003b14 <HAL_GPIO_Init+0x2a8>)
80038bc: 4293 cmp r3, r2
80038be: d052 beq.n 8003966 <HAL_GPIO_Init+0xfa>
80038c0: 4a94 ldr r2, [pc, #592] @ (8003b14 <HAL_GPIO_Init+0x2a8>)
80038c2: 4293 cmp r3, r2
80038c4: d869 bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038c6: 4a94 ldr r2, [pc, #592] @ (8003b18 <HAL_GPIO_Init+0x2ac>)
80038c8: 4293 cmp r3, r2
80038ca: d04c beq.n 8003966 <HAL_GPIO_Init+0xfa>
80038cc: 4a92 ldr r2, [pc, #584] @ (8003b18 <HAL_GPIO_Init+0x2ac>)
80038ce: 4293 cmp r3, r2
80038d0: d863 bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038d2: 4a92 ldr r2, [pc, #584] @ (8003b1c <HAL_GPIO_Init+0x2b0>)
80038d4: 4293 cmp r3, r2
80038d6: d046 beq.n 8003966 <HAL_GPIO_Init+0xfa>
80038d8: 4a90 ldr r2, [pc, #576] @ (8003b1c <HAL_GPIO_Init+0x2b0>)
80038da: 4293 cmp r3, r2
80038dc: d85d bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038de: 2b12 cmp r3, #18
80038e0: d82a bhi.n 8003938 <HAL_GPIO_Init+0xcc>
80038e2: 2b12 cmp r3, #18
80038e4: d859 bhi.n 800399a <HAL_GPIO_Init+0x12e>
80038e6: a201 add r2, pc, #4 @ (adr r2, 80038ec <HAL_GPIO_Init+0x80>)
80038e8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80038ec: 08003967 .word 0x08003967
80038f0: 08003941 .word 0x08003941
80038f4: 08003953 .word 0x08003953
80038f8: 08003995 .word 0x08003995
80038fc: 0800399b .word 0x0800399b
8003900: 0800399b .word 0x0800399b
8003904: 0800399b .word 0x0800399b
8003908: 0800399b .word 0x0800399b
800390c: 0800399b .word 0x0800399b
8003910: 0800399b .word 0x0800399b
8003914: 0800399b .word 0x0800399b
8003918: 0800399b .word 0x0800399b
800391c: 0800399b .word 0x0800399b
8003920: 0800399b .word 0x0800399b
8003924: 0800399b .word 0x0800399b
8003928: 0800399b .word 0x0800399b
800392c: 0800399b .word 0x0800399b
8003930: 08003949 .word 0x08003949
8003934: 0800395d .word 0x0800395d
8003938: 4a79 ldr r2, [pc, #484] @ (8003b20 <HAL_GPIO_Init+0x2b4>)
800393a: 4293 cmp r3, r2
800393c: d013 beq.n 8003966 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800393e: e02c b.n 800399a <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8003940: 683b ldr r3, [r7, #0]
8003942: 68db ldr r3, [r3, #12]
8003944: 623b str r3, [r7, #32]
break;
8003946: e029 b.n 800399c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003948: 683b ldr r3, [r7, #0]
800394a: 68db ldr r3, [r3, #12]
800394c: 3304 adds r3, #4
800394e: 623b str r3, [r7, #32]
break;
8003950: e024 b.n 800399c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8003952: 683b ldr r3, [r7, #0]
8003954: 68db ldr r3, [r3, #12]
8003956: 3308 adds r3, #8
8003958: 623b str r3, [r7, #32]
break;
800395a: e01f b.n 800399c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
800395c: 683b ldr r3, [r7, #0]
800395e: 68db ldr r3, [r3, #12]
8003960: 330c adds r3, #12
8003962: 623b str r3, [r7, #32]
break;
8003964: e01a b.n 800399c <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8003966: 683b ldr r3, [r7, #0]
8003968: 689b ldr r3, [r3, #8]
800396a: 2b00 cmp r3, #0
800396c: d102 bne.n 8003974 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800396e: 2304 movs r3, #4
8003970: 623b str r3, [r7, #32]
break;
8003972: e013 b.n 800399c <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8003974: 683b ldr r3, [r7, #0]
8003976: 689b ldr r3, [r3, #8]
8003978: 2b01 cmp r3, #1
800397a: d105 bne.n 8003988 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
800397c: 2308 movs r3, #8
800397e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8003980: 687b ldr r3, [r7, #4]
8003982: 69fa ldr r2, [r7, #28]
8003984: 611a str r2, [r3, #16]
break;
8003986: e009 b.n 800399c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003988: 2308 movs r3, #8
800398a: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
800398c: 687b ldr r3, [r7, #4]
800398e: 69fa ldr r2, [r7, #28]
8003990: 615a str r2, [r3, #20]
break;
8003992: e003 b.n 800399c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8003994: 2300 movs r3, #0
8003996: 623b str r3, [r7, #32]
break;
8003998: e000 b.n 800399c <HAL_GPIO_Init+0x130>
break;
800399a: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
800399c: 69bb ldr r3, [r7, #24]
800399e: 2bff cmp r3, #255 @ 0xff
80039a0: d801 bhi.n 80039a6 <HAL_GPIO_Init+0x13a>
80039a2: 687b ldr r3, [r7, #4]
80039a4: e001 b.n 80039aa <HAL_GPIO_Init+0x13e>
80039a6: 687b ldr r3, [r7, #4]
80039a8: 3304 adds r3, #4
80039aa: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80039ac: 69bb ldr r3, [r7, #24]
80039ae: 2bff cmp r3, #255 @ 0xff
80039b0: d802 bhi.n 80039b8 <HAL_GPIO_Init+0x14c>
80039b2: 6a7b ldr r3, [r7, #36] @ 0x24
80039b4: 009b lsls r3, r3, #2
80039b6: e002 b.n 80039be <HAL_GPIO_Init+0x152>
80039b8: 6a7b ldr r3, [r7, #36] @ 0x24
80039ba: 3b08 subs r3, #8
80039bc: 009b lsls r3, r3, #2
80039be: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80039c0: 697b ldr r3, [r7, #20]
80039c2: 681a ldr r2, [r3, #0]
80039c4: 210f movs r1, #15
80039c6: 693b ldr r3, [r7, #16]
80039c8: fa01 f303 lsl.w r3, r1, r3
80039cc: 43db mvns r3, r3
80039ce: 401a ands r2, r3
80039d0: 6a39 ldr r1, [r7, #32]
80039d2: 693b ldr r3, [r7, #16]
80039d4: fa01 f303 lsl.w r3, r1, r3
80039d8: 431a orrs r2, r3
80039da: 697b ldr r3, [r7, #20]
80039dc: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80039de: 683b ldr r3, [r7, #0]
80039e0: 685b ldr r3, [r3, #4]
80039e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80039e6: 2b00 cmp r3, #0
80039e8: f000 80b1 beq.w 8003b4e <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80039ec: 4b4d ldr r3, [pc, #308] @ (8003b24 <HAL_GPIO_Init+0x2b8>)
80039ee: 699b ldr r3, [r3, #24]
80039f0: 4a4c ldr r2, [pc, #304] @ (8003b24 <HAL_GPIO_Init+0x2b8>)
80039f2: f043 0301 orr.w r3, r3, #1
80039f6: 6193 str r3, [r2, #24]
80039f8: 4b4a ldr r3, [pc, #296] @ (8003b24 <HAL_GPIO_Init+0x2b8>)
80039fa: 699b ldr r3, [r3, #24]
80039fc: f003 0301 and.w r3, r3, #1
8003a00: 60bb str r3, [r7, #8]
8003a02: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8003a04: 4a48 ldr r2, [pc, #288] @ (8003b28 <HAL_GPIO_Init+0x2bc>)
8003a06: 6a7b ldr r3, [r7, #36] @ 0x24
8003a08: 089b lsrs r3, r3, #2
8003a0a: 3302 adds r3, #2
8003a0c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003a10: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8003a12: 6a7b ldr r3, [r7, #36] @ 0x24
8003a14: f003 0303 and.w r3, r3, #3
8003a18: 009b lsls r3, r3, #2
8003a1a: 220f movs r2, #15
8003a1c: fa02 f303 lsl.w r3, r2, r3
8003a20: 43db mvns r3, r3
8003a22: 68fa ldr r2, [r7, #12]
8003a24: 4013 ands r3, r2
8003a26: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 4a40 ldr r2, [pc, #256] @ (8003b2c <HAL_GPIO_Init+0x2c0>)
8003a2c: 4293 cmp r3, r2
8003a2e: d013 beq.n 8003a58 <HAL_GPIO_Init+0x1ec>
8003a30: 687b ldr r3, [r7, #4]
8003a32: 4a3f ldr r2, [pc, #252] @ (8003b30 <HAL_GPIO_Init+0x2c4>)
8003a34: 4293 cmp r3, r2
8003a36: d00d beq.n 8003a54 <HAL_GPIO_Init+0x1e8>
8003a38: 687b ldr r3, [r7, #4]
8003a3a: 4a3e ldr r2, [pc, #248] @ (8003b34 <HAL_GPIO_Init+0x2c8>)
8003a3c: 4293 cmp r3, r2
8003a3e: d007 beq.n 8003a50 <HAL_GPIO_Init+0x1e4>
8003a40: 687b ldr r3, [r7, #4]
8003a42: 4a3d ldr r2, [pc, #244] @ (8003b38 <HAL_GPIO_Init+0x2cc>)
8003a44: 4293 cmp r3, r2
8003a46: d101 bne.n 8003a4c <HAL_GPIO_Init+0x1e0>
8003a48: 2303 movs r3, #3
8003a4a: e006 b.n 8003a5a <HAL_GPIO_Init+0x1ee>
8003a4c: 2304 movs r3, #4
8003a4e: e004 b.n 8003a5a <HAL_GPIO_Init+0x1ee>
8003a50: 2302 movs r3, #2
8003a52: e002 b.n 8003a5a <HAL_GPIO_Init+0x1ee>
8003a54: 2301 movs r3, #1
8003a56: e000 b.n 8003a5a <HAL_GPIO_Init+0x1ee>
8003a58: 2300 movs r3, #0
8003a5a: 6a7a ldr r2, [r7, #36] @ 0x24
8003a5c: f002 0203 and.w r2, r2, #3
8003a60: 0092 lsls r2, r2, #2
8003a62: 4093 lsls r3, r2
8003a64: 68fa ldr r2, [r7, #12]
8003a66: 4313 orrs r3, r2
8003a68: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8003a6a: 492f ldr r1, [pc, #188] @ (8003b28 <HAL_GPIO_Init+0x2bc>)
8003a6c: 6a7b ldr r3, [r7, #36] @ 0x24
8003a6e: 089b lsrs r3, r3, #2
8003a70: 3302 adds r3, #2
8003a72: 68fa ldr r2, [r7, #12]
8003a74: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003a78: 683b ldr r3, [r7, #0]
8003a7a: 685b ldr r3, [r3, #4]
8003a7c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003a80: 2b00 cmp r3, #0
8003a82: d006 beq.n 8003a92 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8003a84: 4b2d ldr r3, [pc, #180] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003a86: 689a ldr r2, [r3, #8]
8003a88: 492c ldr r1, [pc, #176] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003a8a: 69bb ldr r3, [r7, #24]
8003a8c: 4313 orrs r3, r2
8003a8e: 608b str r3, [r1, #8]
8003a90: e006 b.n 8003aa0 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8003a92: 4b2a ldr r3, [pc, #168] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003a94: 689a ldr r2, [r3, #8]
8003a96: 69bb ldr r3, [r7, #24]
8003a98: 43db mvns r3, r3
8003a9a: 4928 ldr r1, [pc, #160] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003a9c: 4013 ands r3, r2
8003a9e: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8003aa0: 683b ldr r3, [r7, #0]
8003aa2: 685b ldr r3, [r3, #4]
8003aa4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003aa8: 2b00 cmp r3, #0
8003aaa: d006 beq.n 8003aba <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
8003aac: 4b23 ldr r3, [pc, #140] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003aae: 68da ldr r2, [r3, #12]
8003ab0: 4922 ldr r1, [pc, #136] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003ab2: 69bb ldr r3, [r7, #24]
8003ab4: 4313 orrs r3, r2
8003ab6: 60cb str r3, [r1, #12]
8003ab8: e006 b.n 8003ac8 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8003aba: 4b20 ldr r3, [pc, #128] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003abc: 68da ldr r2, [r3, #12]
8003abe: 69bb ldr r3, [r7, #24]
8003ac0: 43db mvns r3, r3
8003ac2: 491e ldr r1, [pc, #120] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003ac4: 4013 ands r3, r2
8003ac6: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8003ac8: 683b ldr r3, [r7, #0]
8003aca: 685b ldr r3, [r3, #4]
8003acc: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003ad0: 2b00 cmp r3, #0
8003ad2: d006 beq.n 8003ae2 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8003ad4: 4b19 ldr r3, [pc, #100] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003ad6: 685a ldr r2, [r3, #4]
8003ad8: 4918 ldr r1, [pc, #96] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003ada: 69bb ldr r3, [r7, #24]
8003adc: 4313 orrs r3, r2
8003ade: 604b str r3, [r1, #4]
8003ae0: e006 b.n 8003af0 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8003ae2: 4b16 ldr r3, [pc, #88] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003ae4: 685a ldr r2, [r3, #4]
8003ae6: 69bb ldr r3, [r7, #24]
8003ae8: 43db mvns r3, r3
8003aea: 4914 ldr r1, [pc, #80] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003aec: 4013 ands r3, r2
8003aee: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8003af0: 683b ldr r3, [r7, #0]
8003af2: 685b ldr r3, [r3, #4]
8003af4: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003af8: 2b00 cmp r3, #0
8003afa: d021 beq.n 8003b40 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8003afc: 4b0f ldr r3, [pc, #60] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003afe: 681a ldr r2, [r3, #0]
8003b00: 490e ldr r1, [pc, #56] @ (8003b3c <HAL_GPIO_Init+0x2d0>)
8003b02: 69bb ldr r3, [r7, #24]
8003b04: 4313 orrs r3, r2
8003b06: 600b str r3, [r1, #0]
8003b08: e021 b.n 8003b4e <HAL_GPIO_Init+0x2e2>
8003b0a: bf00 nop
8003b0c: 10320000 .word 0x10320000
8003b10: 10310000 .word 0x10310000
8003b14: 10220000 .word 0x10220000
8003b18: 10210000 .word 0x10210000
8003b1c: 10120000 .word 0x10120000
8003b20: 10110000 .word 0x10110000
8003b24: 40021000 .word 0x40021000
8003b28: 40010000 .word 0x40010000
8003b2c: 40010800 .word 0x40010800
8003b30: 40010c00 .word 0x40010c00
8003b34: 40011000 .word 0x40011000
8003b38: 40011400 .word 0x40011400
8003b3c: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8003b40: 4b0b ldr r3, [pc, #44] @ (8003b70 <HAL_GPIO_Init+0x304>)
8003b42: 681a ldr r2, [r3, #0]
8003b44: 69bb ldr r3, [r7, #24]
8003b46: 43db mvns r3, r3
8003b48: 4909 ldr r1, [pc, #36] @ (8003b70 <HAL_GPIO_Init+0x304>)
8003b4a: 4013 ands r3, r2
8003b4c: 600b str r3, [r1, #0]
}
}
}
position++;
8003b4e: 6a7b ldr r3, [r7, #36] @ 0x24
8003b50: 3301 adds r3, #1
8003b52: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003b54: 683b ldr r3, [r7, #0]
8003b56: 681a ldr r2, [r3, #0]
8003b58: 6a7b ldr r3, [r7, #36] @ 0x24
8003b5a: fa22 f303 lsr.w r3, r2, r3
8003b5e: 2b00 cmp r3, #0
8003b60: f47f ae8e bne.w 8003880 <HAL_GPIO_Init+0x14>
}
}
8003b64: bf00 nop
8003b66: bf00 nop
8003b68: 372c adds r7, #44 @ 0x2c
8003b6a: 46bd mov sp, r7
8003b6c: bc80 pop {r7}
8003b6e: 4770 bx lr
8003b70: 40010400 .word 0x40010400
08003b74 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003b74: b480 push {r7}
8003b76: b085 sub sp, #20
8003b78: af00 add r7, sp, #0
8003b7a: 6078 str r0, [r7, #4]
8003b7c: 460b mov r3, r1
8003b7e: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8003b80: 687b ldr r3, [r7, #4]
8003b82: 689a ldr r2, [r3, #8]
8003b84: 887b ldrh r3, [r7, #2]
8003b86: 4013 ands r3, r2
8003b88: 2b00 cmp r3, #0
8003b8a: d002 beq.n 8003b92 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8003b8c: 2301 movs r3, #1
8003b8e: 73fb strb r3, [r7, #15]
8003b90: e001 b.n 8003b96 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8003b92: 2300 movs r3, #0
8003b94: 73fb strb r3, [r7, #15]
}
return bitstatus;
8003b96: 7bfb ldrb r3, [r7, #15]
}
8003b98: 4618 mov r0, r3
8003b9a: 3714 adds r7, #20
8003b9c: 46bd mov sp, r7
8003b9e: bc80 pop {r7}
8003ba0: 4770 bx lr
08003ba2 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003ba2: b480 push {r7}
8003ba4: b083 sub sp, #12
8003ba6: af00 add r7, sp, #0
8003ba8: 6078 str r0, [r7, #4]
8003baa: 460b mov r3, r1
8003bac: 807b strh r3, [r7, #2]
8003bae: 4613 mov r3, r2
8003bb0: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003bb2: 787b ldrb r3, [r7, #1]
8003bb4: 2b00 cmp r3, #0
8003bb6: d003 beq.n 8003bc0 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8003bb8: 887a ldrh r2, [r7, #2]
8003bba: 687b ldr r3, [r7, #4]
8003bbc: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8003bbe: e003 b.n 8003bc8 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8003bc0: 887b ldrh r3, [r7, #2]
8003bc2: 041a lsls r2, r3, #16
8003bc4: 687b ldr r3, [r7, #4]
8003bc6: 611a str r2, [r3, #16]
}
8003bc8: bf00 nop
8003bca: 370c adds r7, #12
8003bcc: 46bd mov sp, r7
8003bce: bc80 pop {r7}
8003bd0: 4770 bx lr
08003bd2 <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003bd2: b480 push {r7}
8003bd4: b085 sub sp, #20
8003bd6: af00 add r7, sp, #0
8003bd8: 6078 str r0, [r7, #4]
8003bda: 460b mov r3, r1
8003bdc: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8003bde: 687b ldr r3, [r7, #4]
8003be0: 68db ldr r3, [r3, #12]
8003be2: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8003be4: 887a ldrh r2, [r7, #2]
8003be6: 68fb ldr r3, [r7, #12]
8003be8: 4013 ands r3, r2
8003bea: 041a lsls r2, r3, #16
8003bec: 68fb ldr r3, [r7, #12]
8003bee: 43d9 mvns r1, r3
8003bf0: 887b ldrh r3, [r7, #2]
8003bf2: 400b ands r3, r1
8003bf4: 431a orrs r2, r3
8003bf6: 687b ldr r3, [r7, #4]
8003bf8: 611a str r2, [r3, #16]
}
8003bfa: bf00 nop
8003bfc: 3714 adds r7, #20
8003bfe: 46bd mov sp, r7
8003c00: bc80 pop {r7}
8003c02: 4770 bx lr
08003c04 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003c04: b580 push {r7, lr}
8003c06: b084 sub sp, #16
8003c08: af00 add r7, sp, #0
8003c0a: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003c0c: 687b ldr r3, [r7, #4]
8003c0e: 2b00 cmp r3, #0
8003c10: d101 bne.n 8003c16 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8003c12: 2301 movs r3, #1
8003c14: e12b b.n 8003e6e <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003c16: 687b ldr r3, [r7, #4]
8003c18: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003c1c: b2db uxtb r3, r3
8003c1e: 2b00 cmp r3, #0
8003c20: d106 bne.n 8003c30 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8003c22: 687b ldr r3, [r7, #4]
8003c24: 2200 movs r2, #0
8003c26: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003c2a: 6878 ldr r0, [r7, #4]
8003c2c: f7fe fa42 bl 80020b4 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8003c30: 687b ldr r3, [r7, #4]
8003c32: 2224 movs r2, #36 @ 0x24
8003c34: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003c38: 687b ldr r3, [r7, #4]
8003c3a: 681b ldr r3, [r3, #0]
8003c3c: 681a ldr r2, [r3, #0]
8003c3e: 687b ldr r3, [r7, #4]
8003c40: 681b ldr r3, [r3, #0]
8003c42: f022 0201 bic.w r2, r2, #1
8003c46: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003c48: 687b ldr r3, [r7, #4]
8003c4a: 681b ldr r3, [r3, #0]
8003c4c: 681a ldr r2, [r3, #0]
8003c4e: 687b ldr r3, [r7, #4]
8003c50: 681b ldr r3, [r3, #0]
8003c52: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003c56: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003c58: 687b ldr r3, [r7, #4]
8003c5a: 681b ldr r3, [r3, #0]
8003c5c: 681a ldr r2, [r3, #0]
8003c5e: 687b ldr r3, [r7, #4]
8003c60: 681b ldr r3, [r3, #0]
8003c62: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003c66: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003c68: f001 fbcc bl 8005404 <HAL_RCC_GetPCLK1Freq>
8003c6c: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
8003c6e: 687b ldr r3, [r7, #4]
8003c70: 685b ldr r3, [r3, #4]
8003c72: 4a81 ldr r2, [pc, #516] @ (8003e78 <HAL_I2C_Init+0x274>)
8003c74: 4293 cmp r3, r2
8003c76: d807 bhi.n 8003c88 <HAL_I2C_Init+0x84>
8003c78: 68fb ldr r3, [r7, #12]
8003c7a: 4a80 ldr r2, [pc, #512] @ (8003e7c <HAL_I2C_Init+0x278>)
8003c7c: 4293 cmp r3, r2
8003c7e: bf94 ite ls
8003c80: 2301 movls r3, #1
8003c82: 2300 movhi r3, #0
8003c84: b2db uxtb r3, r3
8003c86: e006 b.n 8003c96 <HAL_I2C_Init+0x92>
8003c88: 68fb ldr r3, [r7, #12]
8003c8a: 4a7d ldr r2, [pc, #500] @ (8003e80 <HAL_I2C_Init+0x27c>)
8003c8c: 4293 cmp r3, r2
8003c8e: bf94 ite ls
8003c90: 2301 movls r3, #1
8003c92: 2300 movhi r3, #0
8003c94: b2db uxtb r3, r3
8003c96: 2b00 cmp r3, #0
8003c98: d001 beq.n 8003c9e <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003c9a: 2301 movs r3, #1
8003c9c: e0e7 b.n 8003e6e <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
8003c9e: 68fb ldr r3, [r7, #12]
8003ca0: 4a78 ldr r2, [pc, #480] @ (8003e84 <HAL_I2C_Init+0x280>)
8003ca2: fba2 2303 umull r2, r3, r2, r3
8003ca6: 0c9b lsrs r3, r3, #18
8003ca8: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
8003caa: 687b ldr r3, [r7, #4]
8003cac: 681b ldr r3, [r3, #0]
8003cae: 685b ldr r3, [r3, #4]
8003cb0: f023 013f bic.w r1, r3, #63 @ 0x3f
8003cb4: 687b ldr r3, [r7, #4]
8003cb6: 681b ldr r3, [r3, #0]
8003cb8: 68ba ldr r2, [r7, #8]
8003cba: 430a orrs r2, r1
8003cbc: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
8003cbe: 687b ldr r3, [r7, #4]
8003cc0: 681b ldr r3, [r3, #0]
8003cc2: 6a1b ldr r3, [r3, #32]
8003cc4: f023 013f bic.w r1, r3, #63 @ 0x3f
8003cc8: 687b ldr r3, [r7, #4]
8003cca: 685b ldr r3, [r3, #4]
8003ccc: 4a6a ldr r2, [pc, #424] @ (8003e78 <HAL_I2C_Init+0x274>)
8003cce: 4293 cmp r3, r2
8003cd0: d802 bhi.n 8003cd8 <HAL_I2C_Init+0xd4>
8003cd2: 68bb ldr r3, [r7, #8]
8003cd4: 3301 adds r3, #1
8003cd6: e009 b.n 8003cec <HAL_I2C_Init+0xe8>
8003cd8: 68bb ldr r3, [r7, #8]
8003cda: f44f 7296 mov.w r2, #300 @ 0x12c
8003cde: fb02 f303 mul.w r3, r2, r3
8003ce2: 4a69 ldr r2, [pc, #420] @ (8003e88 <HAL_I2C_Init+0x284>)
8003ce4: fba2 2303 umull r2, r3, r2, r3
8003ce8: 099b lsrs r3, r3, #6
8003cea: 3301 adds r3, #1
8003cec: 687a ldr r2, [r7, #4]
8003cee: 6812 ldr r2, [r2, #0]
8003cf0: 430b orrs r3, r1
8003cf2: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8003cf4: 687b ldr r3, [r7, #4]
8003cf6: 681b ldr r3, [r3, #0]
8003cf8: 69db ldr r3, [r3, #28]
8003cfa: f423 424f bic.w r2, r3, #52992 @ 0xcf00
8003cfe: f022 02ff bic.w r2, r2, #255 @ 0xff
8003d02: 687b ldr r3, [r7, #4]
8003d04: 685b ldr r3, [r3, #4]
8003d06: 495c ldr r1, [pc, #368] @ (8003e78 <HAL_I2C_Init+0x274>)
8003d08: 428b cmp r3, r1
8003d0a: d819 bhi.n 8003d40 <HAL_I2C_Init+0x13c>
8003d0c: 68fb ldr r3, [r7, #12]
8003d0e: 1e59 subs r1, r3, #1
8003d10: 687b ldr r3, [r7, #4]
8003d12: 685b ldr r3, [r3, #4]
8003d14: 005b lsls r3, r3, #1
8003d16: fbb1 f3f3 udiv r3, r1, r3
8003d1a: 1c59 adds r1, r3, #1
8003d1c: f640 73fc movw r3, #4092 @ 0xffc
8003d20: 400b ands r3, r1
8003d22: 2b00 cmp r3, #0
8003d24: d00a beq.n 8003d3c <HAL_I2C_Init+0x138>
8003d26: 68fb ldr r3, [r7, #12]
8003d28: 1e59 subs r1, r3, #1
8003d2a: 687b ldr r3, [r7, #4]
8003d2c: 685b ldr r3, [r3, #4]
8003d2e: 005b lsls r3, r3, #1
8003d30: fbb1 f3f3 udiv r3, r1, r3
8003d34: 3301 adds r3, #1
8003d36: f3c3 030b ubfx r3, r3, #0, #12
8003d3a: e051 b.n 8003de0 <HAL_I2C_Init+0x1dc>
8003d3c: 2304 movs r3, #4
8003d3e: e04f b.n 8003de0 <HAL_I2C_Init+0x1dc>
8003d40: 687b ldr r3, [r7, #4]
8003d42: 689b ldr r3, [r3, #8]
8003d44: 2b00 cmp r3, #0
8003d46: d111 bne.n 8003d6c <HAL_I2C_Init+0x168>
8003d48: 68fb ldr r3, [r7, #12]
8003d4a: 1e58 subs r0, r3, #1
8003d4c: 687b ldr r3, [r7, #4]
8003d4e: 6859 ldr r1, [r3, #4]
8003d50: 460b mov r3, r1
8003d52: 005b lsls r3, r3, #1
8003d54: 440b add r3, r1
8003d56: fbb0 f3f3 udiv r3, r0, r3
8003d5a: 3301 adds r3, #1
8003d5c: f3c3 030b ubfx r3, r3, #0, #12
8003d60: 2b00 cmp r3, #0
8003d62: bf0c ite eq
8003d64: 2301 moveq r3, #1
8003d66: 2300 movne r3, #0
8003d68: b2db uxtb r3, r3
8003d6a: e012 b.n 8003d92 <HAL_I2C_Init+0x18e>
8003d6c: 68fb ldr r3, [r7, #12]
8003d6e: 1e58 subs r0, r3, #1
8003d70: 687b ldr r3, [r7, #4]
8003d72: 6859 ldr r1, [r3, #4]
8003d74: 460b mov r3, r1
8003d76: 009b lsls r3, r3, #2
8003d78: 440b add r3, r1
8003d7a: 0099 lsls r1, r3, #2
8003d7c: 440b add r3, r1
8003d7e: fbb0 f3f3 udiv r3, r0, r3
8003d82: 3301 adds r3, #1
8003d84: f3c3 030b ubfx r3, r3, #0, #12
8003d88: 2b00 cmp r3, #0
8003d8a: bf0c ite eq
8003d8c: 2301 moveq r3, #1
8003d8e: 2300 movne r3, #0
8003d90: b2db uxtb r3, r3
8003d92: 2b00 cmp r3, #0
8003d94: d001 beq.n 8003d9a <HAL_I2C_Init+0x196>
8003d96: 2301 movs r3, #1
8003d98: e022 b.n 8003de0 <HAL_I2C_Init+0x1dc>
8003d9a: 687b ldr r3, [r7, #4]
8003d9c: 689b ldr r3, [r3, #8]
8003d9e: 2b00 cmp r3, #0
8003da0: d10e bne.n 8003dc0 <HAL_I2C_Init+0x1bc>
8003da2: 68fb ldr r3, [r7, #12]
8003da4: 1e58 subs r0, r3, #1
8003da6: 687b ldr r3, [r7, #4]
8003da8: 6859 ldr r1, [r3, #4]
8003daa: 460b mov r3, r1
8003dac: 005b lsls r3, r3, #1
8003dae: 440b add r3, r1
8003db0: fbb0 f3f3 udiv r3, r0, r3
8003db4: 3301 adds r3, #1
8003db6: f3c3 030b ubfx r3, r3, #0, #12
8003dba: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8003dbe: e00f b.n 8003de0 <HAL_I2C_Init+0x1dc>
8003dc0: 68fb ldr r3, [r7, #12]
8003dc2: 1e58 subs r0, r3, #1
8003dc4: 687b ldr r3, [r7, #4]
8003dc6: 6859 ldr r1, [r3, #4]
8003dc8: 460b mov r3, r1
8003dca: 009b lsls r3, r3, #2
8003dcc: 440b add r3, r1
8003dce: 0099 lsls r1, r3, #2
8003dd0: 440b add r3, r1
8003dd2: fbb0 f3f3 udiv r3, r0, r3
8003dd6: 3301 adds r3, #1
8003dd8: f3c3 030b ubfx r3, r3, #0, #12
8003ddc: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8003de0: 6879 ldr r1, [r7, #4]
8003de2: 6809 ldr r1, [r1, #0]
8003de4: 4313 orrs r3, r2
8003de6: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8003de8: 687b ldr r3, [r7, #4]
8003dea: 681b ldr r3, [r3, #0]
8003dec: 681b ldr r3, [r3, #0]
8003dee: f023 01c0 bic.w r1, r3, #192 @ 0xc0
8003df2: 687b ldr r3, [r7, #4]
8003df4: 69da ldr r2, [r3, #28]
8003df6: 687b ldr r3, [r7, #4]
8003df8: 6a1b ldr r3, [r3, #32]
8003dfa: 431a orrs r2, r3
8003dfc: 687b ldr r3, [r7, #4]
8003dfe: 681b ldr r3, [r3, #0]
8003e00: 430a orrs r2, r1
8003e02: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8003e04: 687b ldr r3, [r7, #4]
8003e06: 681b ldr r3, [r3, #0]
8003e08: 689b ldr r3, [r3, #8]
8003e0a: f423 4303 bic.w r3, r3, #33536 @ 0x8300
8003e0e: f023 03ff bic.w r3, r3, #255 @ 0xff
8003e12: 687a ldr r2, [r7, #4]
8003e14: 6911 ldr r1, [r2, #16]
8003e16: 687a ldr r2, [r7, #4]
8003e18: 68d2 ldr r2, [r2, #12]
8003e1a: 4311 orrs r1, r2
8003e1c: 687a ldr r2, [r7, #4]
8003e1e: 6812 ldr r2, [r2, #0]
8003e20: 430b orrs r3, r1
8003e22: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
8003e24: 687b ldr r3, [r7, #4]
8003e26: 681b ldr r3, [r3, #0]
8003e28: 68db ldr r3, [r3, #12]
8003e2a: f023 01ff bic.w r1, r3, #255 @ 0xff
8003e2e: 687b ldr r3, [r7, #4]
8003e30: 695a ldr r2, [r3, #20]
8003e32: 687b ldr r3, [r7, #4]
8003e34: 699b ldr r3, [r3, #24]
8003e36: 431a orrs r2, r3
8003e38: 687b ldr r3, [r7, #4]
8003e3a: 681b ldr r3, [r3, #0]
8003e3c: 430a orrs r2, r1
8003e3e: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003e40: 687b ldr r3, [r7, #4]
8003e42: 681b ldr r3, [r3, #0]
8003e44: 681a ldr r2, [r3, #0]
8003e46: 687b ldr r3, [r7, #4]
8003e48: 681b ldr r3, [r3, #0]
8003e4a: f042 0201 orr.w r2, r2, #1
8003e4e: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003e50: 687b ldr r3, [r7, #4]
8003e52: 2200 movs r2, #0
8003e54: 641a str r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_READY;
8003e56: 687b ldr r3, [r7, #4]
8003e58: 2220 movs r2, #32
8003e5a: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
8003e5e: 687b ldr r3, [r7, #4]
8003e60: 2200 movs r2, #0
8003e62: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8003e64: 687b ldr r3, [r7, #4]
8003e66: 2200 movs r2, #0
8003e68: f883 203e strb.w r2, [r3, #62] @ 0x3e
return HAL_OK;
8003e6c: 2300 movs r3, #0
}
8003e6e: 4618 mov r0, r3
8003e70: 3710 adds r7, #16
8003e72: 46bd mov sp, r7
8003e74: bd80 pop {r7, pc}
8003e76: bf00 nop
8003e78: 000186a0 .word 0x000186a0
8003e7c: 001e847f .word 0x001e847f
8003e80: 003d08ff .word 0x003d08ff
8003e84: 431bde83 .word 0x431bde83
8003e88: 10624dd3 .word 0x10624dd3
08003e8c <HAL_I2C_Master_Transmit>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003e8c: b580 push {r7, lr}
8003e8e: b088 sub sp, #32
8003e90: af02 add r7, sp, #8
8003e92: 60f8 str r0, [r7, #12]
8003e94: 607a str r2, [r7, #4]
8003e96: 461a mov r2, r3
8003e98: 460b mov r3, r1
8003e9a: 817b strh r3, [r7, #10]
8003e9c: 4613 mov r3, r2
8003e9e: 813b strh r3, [r7, #8]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
8003ea0: f7fe fee4 bl 8002c6c <HAL_GetTick>
8003ea4: 6178 str r0, [r7, #20]
if (hi2c->State == HAL_I2C_STATE_READY)
8003ea6: 68fb ldr r3, [r7, #12]
8003ea8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003eac: b2db uxtb r3, r3
8003eae: 2b20 cmp r3, #32
8003eb0: f040 80e0 bne.w 8004074 <HAL_I2C_Master_Transmit+0x1e8>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
8003eb4: 697b ldr r3, [r7, #20]
8003eb6: 9300 str r3, [sp, #0]
8003eb8: 2319 movs r3, #25
8003eba: 2201 movs r2, #1
8003ebc: 4970 ldr r1, [pc, #448] @ (8004080 <HAL_I2C_Master_Transmit+0x1f4>)
8003ebe: 68f8 ldr r0, [r7, #12]
8003ec0: f000 fc9e bl 8004800 <I2C_WaitOnFlagUntilTimeout>
8003ec4: 4603 mov r3, r0
8003ec6: 2b00 cmp r3, #0
8003ec8: d001 beq.n 8003ece <HAL_I2C_Master_Transmit+0x42>
{
return HAL_BUSY;
8003eca: 2302 movs r3, #2
8003ecc: e0d3 b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8003ece: 68fb ldr r3, [r7, #12]
8003ed0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8003ed4: 2b01 cmp r3, #1
8003ed6: d101 bne.n 8003edc <HAL_I2C_Master_Transmit+0x50>
8003ed8: 2302 movs r3, #2
8003eda: e0cc b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
8003edc: 68fb ldr r3, [r7, #12]
8003ede: 2201 movs r2, #1
8003ee0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
8003ee4: 68fb ldr r3, [r7, #12]
8003ee6: 681b ldr r3, [r3, #0]
8003ee8: 681b ldr r3, [r3, #0]
8003eea: f003 0301 and.w r3, r3, #1
8003eee: 2b01 cmp r3, #1
8003ef0: d007 beq.n 8003f02 <HAL_I2C_Master_Transmit+0x76>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003ef2: 68fb ldr r3, [r7, #12]
8003ef4: 681b ldr r3, [r3, #0]
8003ef6: 681a ldr r2, [r3, #0]
8003ef8: 68fb ldr r3, [r7, #12]
8003efa: 681b ldr r3, [r3, #0]
8003efc: f042 0201 orr.w r2, r2, #1
8003f00: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8003f02: 68fb ldr r3, [r7, #12]
8003f04: 681b ldr r3, [r3, #0]
8003f06: 681a ldr r2, [r3, #0]
8003f08: 68fb ldr r3, [r7, #12]
8003f0a: 681b ldr r3, [r3, #0]
8003f0c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003f10: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8003f12: 68fb ldr r3, [r7, #12]
8003f14: 2221 movs r2, #33 @ 0x21
8003f16: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8003f1a: 68fb ldr r3, [r7, #12]
8003f1c: 2210 movs r2, #16
8003f1e: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003f22: 68fb ldr r3, [r7, #12]
8003f24: 2200 movs r2, #0
8003f26: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8003f28: 68fb ldr r3, [r7, #12]
8003f2a: 687a ldr r2, [r7, #4]
8003f2c: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8003f2e: 68fb ldr r3, [r7, #12]
8003f30: 893a ldrh r2, [r7, #8]
8003f32: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8003f34: 68fb ldr r3, [r7, #12]
8003f36: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003f38: b29a uxth r2, r3
8003f3a: 68fb ldr r3, [r7, #12]
8003f3c: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8003f3e: 68fb ldr r3, [r7, #12]
8003f40: 4a50 ldr r2, [pc, #320] @ (8004084 <HAL_I2C_Master_Transmit+0x1f8>)
8003f42: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
8003f44: 8979 ldrh r1, [r7, #10]
8003f46: 697b ldr r3, [r7, #20]
8003f48: 6a3a ldr r2, [r7, #32]
8003f4a: 68f8 ldr r0, [r7, #12]
8003f4c: f000 fb08 bl 8004560 <I2C_MasterRequestWrite>
8003f50: 4603 mov r3, r0
8003f52: 2b00 cmp r3, #0
8003f54: d001 beq.n 8003f5a <HAL_I2C_Master_Transmit+0xce>
{
return HAL_ERROR;
8003f56: 2301 movs r3, #1
8003f58: e08d b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003f5a: 2300 movs r3, #0
8003f5c: 613b str r3, [r7, #16]
8003f5e: 68fb ldr r3, [r7, #12]
8003f60: 681b ldr r3, [r3, #0]
8003f62: 695b ldr r3, [r3, #20]
8003f64: 613b str r3, [r7, #16]
8003f66: 68fb ldr r3, [r7, #12]
8003f68: 681b ldr r3, [r3, #0]
8003f6a: 699b ldr r3, [r3, #24]
8003f6c: 613b str r3, [r7, #16]
8003f6e: 693b ldr r3, [r7, #16]
while (hi2c->XferSize > 0U)
8003f70: e066 b.n 8004040 <HAL_I2C_Master_Transmit+0x1b4>
{
/* Wait until TXE flag is set */
if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003f72: 697a ldr r2, [r7, #20]
8003f74: 6a39 ldr r1, [r7, #32]
8003f76: 68f8 ldr r0, [r7, #12]
8003f78: f000 fd5c bl 8004a34 <I2C_WaitOnTXEFlagUntilTimeout>
8003f7c: 4603 mov r3, r0
8003f7e: 2b00 cmp r3, #0
8003f80: d00d beq.n 8003f9e <HAL_I2C_Master_Transmit+0x112>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
8003f82: 68fb ldr r3, [r7, #12]
8003f84: 6c1b ldr r3, [r3, #64] @ 0x40
8003f86: 2b04 cmp r3, #4
8003f88: d107 bne.n 8003f9a <HAL_I2C_Master_Transmit+0x10e>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003f8a: 68fb ldr r3, [r7, #12]
8003f8c: 681b ldr r3, [r3, #0]
8003f8e: 681a ldr r2, [r3, #0]
8003f90: 68fb ldr r3, [r7, #12]
8003f92: 681b ldr r3, [r3, #0]
8003f94: f442 7200 orr.w r2, r2, #512 @ 0x200
8003f98: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8003f9a: 2301 movs r3, #1
8003f9c: e06b b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003f9e: 68fb ldr r3, [r7, #12]
8003fa0: 6a5b ldr r3, [r3, #36] @ 0x24
8003fa2: 781a ldrb r2, [r3, #0]
8003fa4: 68fb ldr r3, [r7, #12]
8003fa6: 681b ldr r3, [r3, #0]
8003fa8: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003faa: 68fb ldr r3, [r7, #12]
8003fac: 6a5b ldr r3, [r3, #36] @ 0x24
8003fae: 1c5a adds r2, r3, #1
8003fb0: 68fb ldr r3, [r7, #12]
8003fb2: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003fb4: 68fb ldr r3, [r7, #12]
8003fb6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003fb8: b29b uxth r3, r3
8003fba: 3b01 subs r3, #1
8003fbc: b29a uxth r2, r3
8003fbe: 68fb ldr r3, [r7, #12]
8003fc0: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8003fc2: 68fb ldr r3, [r7, #12]
8003fc4: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fc6: 3b01 subs r3, #1
8003fc8: b29a uxth r2, r3
8003fca: 68fb ldr r3, [r7, #12]
8003fcc: 851a strh r2, [r3, #40] @ 0x28
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
8003fce: 68fb ldr r3, [r7, #12]
8003fd0: 681b ldr r3, [r3, #0]
8003fd2: 695b ldr r3, [r3, #20]
8003fd4: f003 0304 and.w r3, r3, #4
8003fd8: 2b04 cmp r3, #4
8003fda: d11b bne.n 8004014 <HAL_I2C_Master_Transmit+0x188>
8003fdc: 68fb ldr r3, [r7, #12]
8003fde: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fe0: 2b00 cmp r3, #0
8003fe2: d017 beq.n 8004014 <HAL_I2C_Master_Transmit+0x188>
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003fe4: 68fb ldr r3, [r7, #12]
8003fe6: 6a5b ldr r3, [r3, #36] @ 0x24
8003fe8: 781a ldrb r2, [r3, #0]
8003fea: 68fb ldr r3, [r7, #12]
8003fec: 681b ldr r3, [r3, #0]
8003fee: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003ff0: 68fb ldr r3, [r7, #12]
8003ff2: 6a5b ldr r3, [r3, #36] @ 0x24
8003ff4: 1c5a adds r2, r3, #1
8003ff6: 68fb ldr r3, [r7, #12]
8003ff8: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003ffa: 68fb ldr r3, [r7, #12]
8003ffc: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003ffe: b29b uxth r3, r3
8004000: 3b01 subs r3, #1
8004002: b29a uxth r2, r3
8004004: 68fb ldr r3, [r7, #12]
8004006: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8004008: 68fb ldr r3, [r7, #12]
800400a: 8d1b ldrh r3, [r3, #40] @ 0x28
800400c: 3b01 subs r3, #1
800400e: b29a uxth r2, r3
8004010: 68fb ldr r3, [r7, #12]
8004012: 851a strh r2, [r3, #40] @ 0x28
}
/* Wait until BTF flag is set */
if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004014: 697a ldr r2, [r7, #20]
8004016: 6a39 ldr r1, [r7, #32]
8004018: 68f8 ldr r0, [r7, #12]
800401a: f000 fd53 bl 8004ac4 <I2C_WaitOnBTFFlagUntilTimeout>
800401e: 4603 mov r3, r0
8004020: 2b00 cmp r3, #0
8004022: d00d beq.n 8004040 <HAL_I2C_Master_Transmit+0x1b4>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
8004024: 68fb ldr r3, [r7, #12]
8004026: 6c1b ldr r3, [r3, #64] @ 0x40
8004028: 2b04 cmp r3, #4
800402a: d107 bne.n 800403c <HAL_I2C_Master_Transmit+0x1b0>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
800402c: 68fb ldr r3, [r7, #12]
800402e: 681b ldr r3, [r3, #0]
8004030: 681a ldr r2, [r3, #0]
8004032: 68fb ldr r3, [r7, #12]
8004034: 681b ldr r3, [r3, #0]
8004036: f442 7200 orr.w r2, r2, #512 @ 0x200
800403a: 601a str r2, [r3, #0]
}
return HAL_ERROR;
800403c: 2301 movs r3, #1
800403e: e01a b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
while (hi2c->XferSize > 0U)
8004040: 68fb ldr r3, [r7, #12]
8004042: 8d1b ldrh r3, [r3, #40] @ 0x28
8004044: 2b00 cmp r3, #0
8004046: d194 bne.n 8003f72 <HAL_I2C_Master_Transmit+0xe6>
}
}
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004048: 68fb ldr r3, [r7, #12]
800404a: 681b ldr r3, [r3, #0]
800404c: 681a ldr r2, [r3, #0]
800404e: 68fb ldr r3, [r7, #12]
8004050: 681b ldr r3, [r3, #0]
8004052: f442 7200 orr.w r2, r2, #512 @ 0x200
8004056: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8004058: 68fb ldr r3, [r7, #12]
800405a: 2220 movs r2, #32
800405c: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004060: 68fb ldr r3, [r7, #12]
8004062: 2200 movs r2, #0
8004064: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004068: 68fb ldr r3, [r7, #12]
800406a: 2200 movs r2, #0
800406c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8004070: 2300 movs r3, #0
8004072: e000 b.n 8004076 <HAL_I2C_Master_Transmit+0x1ea>
}
else
{
return HAL_BUSY;
8004074: 2302 movs r3, #2
}
}
8004076: 4618 mov r0, r3
8004078: 3718 adds r7, #24
800407a: 46bd mov sp, r7
800407c: bd80 pop {r7, pc}
800407e: bf00 nop
8004080: 00100002 .word 0x00100002
8004084: ffff0000 .word 0xffff0000
08004088 <HAL_I2C_Master_Receive>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8004088: b580 push {r7, lr}
800408a: b08c sub sp, #48 @ 0x30
800408c: af02 add r7, sp, #8
800408e: 60f8 str r0, [r7, #12]
8004090: 607a str r2, [r7, #4]
8004092: 461a mov r2, r3
8004094: 460b mov r3, r1
8004096: 817b strh r3, [r7, #10]
8004098: 4613 mov r3, r2
800409a: 813b strh r3, [r7, #8]
__IO uint32_t count = 0U;
800409c: 2300 movs r3, #0
800409e: 623b str r3, [r7, #32]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
80040a0: f7fe fde4 bl 8002c6c <HAL_GetTick>
80040a4: 6278 str r0, [r7, #36] @ 0x24
if (hi2c->State == HAL_I2C_STATE_READY)
80040a6: 68fb ldr r3, [r7, #12]
80040a8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80040ac: b2db uxtb r3, r3
80040ae: 2b20 cmp r3, #32
80040b0: f040 824b bne.w 800454a <HAL_I2C_Master_Receive+0x4c2>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
80040b4: 6a7b ldr r3, [r7, #36] @ 0x24
80040b6: 9300 str r3, [sp, #0]
80040b8: 2319 movs r3, #25
80040ba: 2201 movs r2, #1
80040bc: 497f ldr r1, [pc, #508] @ (80042bc <HAL_I2C_Master_Receive+0x234>)
80040be: 68f8 ldr r0, [r7, #12]
80040c0: f000 fb9e bl 8004800 <I2C_WaitOnFlagUntilTimeout>
80040c4: 4603 mov r3, r0
80040c6: 2b00 cmp r3, #0
80040c8: d001 beq.n 80040ce <HAL_I2C_Master_Receive+0x46>
{
return HAL_BUSY;
80040ca: 2302 movs r3, #2
80040cc: e23e b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80040ce: 68fb ldr r3, [r7, #12]
80040d0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80040d4: 2b01 cmp r3, #1
80040d6: d101 bne.n 80040dc <HAL_I2C_Master_Receive+0x54>
80040d8: 2302 movs r3, #2
80040da: e237 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
80040dc: 68fb ldr r3, [r7, #12]
80040de: 2201 movs r2, #1
80040e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
80040e4: 68fb ldr r3, [r7, #12]
80040e6: 681b ldr r3, [r3, #0]
80040e8: 681b ldr r3, [r3, #0]
80040ea: f003 0301 and.w r3, r3, #1
80040ee: 2b01 cmp r3, #1
80040f0: d007 beq.n 8004102 <HAL_I2C_Master_Receive+0x7a>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80040f2: 68fb ldr r3, [r7, #12]
80040f4: 681b ldr r3, [r3, #0]
80040f6: 681a ldr r2, [r3, #0]
80040f8: 68fb ldr r3, [r7, #12]
80040fa: 681b ldr r3, [r3, #0]
80040fc: f042 0201 orr.w r2, r2, #1
8004100: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8004102: 68fb ldr r3, [r7, #12]
8004104: 681b ldr r3, [r3, #0]
8004106: 681a ldr r2, [r3, #0]
8004108: 68fb ldr r3, [r7, #12]
800410a: 681b ldr r3, [r3, #0]
800410c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8004110: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_RX;
8004112: 68fb ldr r3, [r7, #12]
8004114: 2222 movs r2, #34 @ 0x22
8004116: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
800411a: 68fb ldr r3, [r7, #12]
800411c: 2210 movs r2, #16
800411e: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8004122: 68fb ldr r3, [r7, #12]
8004124: 2200 movs r2, #0
8004126: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8004128: 68fb ldr r3, [r7, #12]
800412a: 687a ldr r2, [r7, #4]
800412c: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
800412e: 68fb ldr r3, [r7, #12]
8004130: 893a ldrh r2, [r7, #8]
8004132: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8004134: 68fb ldr r3, [r7, #12]
8004136: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004138: b29a uxth r2, r3
800413a: 68fb ldr r3, [r7, #12]
800413c: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
800413e: 68fb ldr r3, [r7, #12]
8004140: 4a5f ldr r2, [pc, #380] @ (80042c0 <HAL_I2C_Master_Receive+0x238>)
8004142: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
8004144: 8979 ldrh r1, [r7, #10]
8004146: 6a7b ldr r3, [r7, #36] @ 0x24
8004148: 6b3a ldr r2, [r7, #48] @ 0x30
800414a: 68f8 ldr r0, [r7, #12]
800414c: f000 fa8a bl 8004664 <I2C_MasterRequestRead>
8004150: 4603 mov r3, r0
8004152: 2b00 cmp r3, #0
8004154: d001 beq.n 800415a <HAL_I2C_Master_Receive+0xd2>
{
return HAL_ERROR;
8004156: 2301 movs r3, #1
8004158: e1f8 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
if (hi2c->XferSize == 0U)
800415a: 68fb ldr r3, [r7, #12]
800415c: 8d1b ldrh r3, [r3, #40] @ 0x28
800415e: 2b00 cmp r3, #0
8004160: d113 bne.n 800418a <HAL_I2C_Master_Receive+0x102>
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004162: 2300 movs r3, #0
8004164: 61fb str r3, [r7, #28]
8004166: 68fb ldr r3, [r7, #12]
8004168: 681b ldr r3, [r3, #0]
800416a: 695b ldr r3, [r3, #20]
800416c: 61fb str r3, [r7, #28]
800416e: 68fb ldr r3, [r7, #12]
8004170: 681b ldr r3, [r3, #0]
8004172: 699b ldr r3, [r3, #24]
8004174: 61fb str r3, [r7, #28]
8004176: 69fb ldr r3, [r7, #28]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004178: 68fb ldr r3, [r7, #12]
800417a: 681b ldr r3, [r3, #0]
800417c: 681a ldr r2, [r3, #0]
800417e: 68fb ldr r3, [r7, #12]
8004180: 681b ldr r3, [r3, #0]
8004182: f442 7200 orr.w r2, r2, #512 @ 0x200
8004186: 601a str r2, [r3, #0]
8004188: e1cc b.n 8004524 <HAL_I2C_Master_Receive+0x49c>
}
else if (hi2c->XferSize == 1U)
800418a: 68fb ldr r3, [r7, #12]
800418c: 8d1b ldrh r3, [r3, #40] @ 0x28
800418e: 2b01 cmp r3, #1
8004190: d11e bne.n 80041d0 <HAL_I2C_Master_Receive+0x148>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004192: 68fb ldr r3, [r7, #12]
8004194: 681b ldr r3, [r3, #0]
8004196: 681a ldr r2, [r3, #0]
8004198: 68fb ldr r3, [r7, #12]
800419a: 681b ldr r3, [r3, #0]
800419c: f422 6280 bic.w r2, r2, #1024 @ 0x400
80041a0: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
80041a2: b672 cpsid i
}
80041a4: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80041a6: 2300 movs r3, #0
80041a8: 61bb str r3, [r7, #24]
80041aa: 68fb ldr r3, [r7, #12]
80041ac: 681b ldr r3, [r3, #0]
80041ae: 695b ldr r3, [r3, #20]
80041b0: 61bb str r3, [r7, #24]
80041b2: 68fb ldr r3, [r7, #12]
80041b4: 681b ldr r3, [r3, #0]
80041b6: 699b ldr r3, [r3, #24]
80041b8: 61bb str r3, [r7, #24]
80041ba: 69bb ldr r3, [r7, #24]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80041bc: 68fb ldr r3, [r7, #12]
80041be: 681b ldr r3, [r3, #0]
80041c0: 681a ldr r2, [r3, #0]
80041c2: 68fb ldr r3, [r7, #12]
80041c4: 681b ldr r3, [r3, #0]
80041c6: f442 7200 orr.w r2, r2, #512 @ 0x200
80041ca: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
80041cc: b662 cpsie i
}
80041ce: e035 b.n 800423c <HAL_I2C_Master_Receive+0x1b4>
/* Re-enable IRQs */
__enable_irq();
}
else if (hi2c->XferSize == 2U)
80041d0: 68fb ldr r3, [r7, #12]
80041d2: 8d1b ldrh r3, [r3, #40] @ 0x28
80041d4: 2b02 cmp r3, #2
80041d6: d11e bne.n 8004216 <HAL_I2C_Master_Receive+0x18e>
{
/* Enable Pos */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
80041d8: 68fb ldr r3, [r7, #12]
80041da: 681b ldr r3, [r3, #0]
80041dc: 681a ldr r2, [r3, #0]
80041de: 68fb ldr r3, [r7, #12]
80041e0: 681b ldr r3, [r3, #0]
80041e2: f442 6200 orr.w r2, r2, #2048 @ 0x800
80041e6: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
80041e8: b672 cpsid i
}
80041ea: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80041ec: 2300 movs r3, #0
80041ee: 617b str r3, [r7, #20]
80041f0: 68fb ldr r3, [r7, #12]
80041f2: 681b ldr r3, [r3, #0]
80041f4: 695b ldr r3, [r3, #20]
80041f6: 617b str r3, [r7, #20]
80041f8: 68fb ldr r3, [r7, #12]
80041fa: 681b ldr r3, [r3, #0]
80041fc: 699b ldr r3, [r3, #24]
80041fe: 617b str r3, [r7, #20]
8004200: 697b ldr r3, [r7, #20]
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004202: 68fb ldr r3, [r7, #12]
8004204: 681b ldr r3, [r3, #0]
8004206: 681a ldr r2, [r3, #0]
8004208: 68fb ldr r3, [r7, #12]
800420a: 681b ldr r3, [r3, #0]
800420c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004210: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
8004212: b662 cpsie i
}
8004214: e012 b.n 800423c <HAL_I2C_Master_Receive+0x1b4>
__enable_irq();
}
else
{
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004216: 68fb ldr r3, [r7, #12]
8004218: 681b ldr r3, [r3, #0]
800421a: 681a ldr r2, [r3, #0]
800421c: 68fb ldr r3, [r7, #12]
800421e: 681b ldr r3, [r3, #0]
8004220: f442 6280 orr.w r2, r2, #1024 @ 0x400
8004224: 601a str r2, [r3, #0]
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004226: 2300 movs r3, #0
8004228: 613b str r3, [r7, #16]
800422a: 68fb ldr r3, [r7, #12]
800422c: 681b ldr r3, [r3, #0]
800422e: 695b ldr r3, [r3, #20]
8004230: 613b str r3, [r7, #16]
8004232: 68fb ldr r3, [r7, #12]
8004234: 681b ldr r3, [r3, #0]
8004236: 699b ldr r3, [r3, #24]
8004238: 613b str r3, [r7, #16]
800423a: 693b ldr r3, [r7, #16]
}
while (hi2c->XferSize > 0U)
800423c: e172 b.n 8004524 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize <= 3U)
800423e: 68fb ldr r3, [r7, #12]
8004240: 8d1b ldrh r3, [r3, #40] @ 0x28
8004242: 2b03 cmp r3, #3
8004244: f200 811f bhi.w 8004486 <HAL_I2C_Master_Receive+0x3fe>
{
/* One byte */
if (hi2c->XferSize == 1U)
8004248: 68fb ldr r3, [r7, #12]
800424a: 8d1b ldrh r3, [r3, #40] @ 0x28
800424c: 2b01 cmp r3, #1
800424e: d123 bne.n 8004298 <HAL_I2C_Master_Receive+0x210>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004250: 6a7a ldr r2, [r7, #36] @ 0x24
8004252: 6b39 ldr r1, [r7, #48] @ 0x30
8004254: 68f8 ldr r0, [r7, #12]
8004256: f000 fc7d bl 8004b54 <I2C_WaitOnRXNEFlagUntilTimeout>
800425a: 4603 mov r3, r0
800425c: 2b00 cmp r3, #0
800425e: d001 beq.n 8004264 <HAL_I2C_Master_Receive+0x1dc>
{
return HAL_ERROR;
8004260: 2301 movs r3, #1
8004262: e173 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004264: 68fb ldr r3, [r7, #12]
8004266: 681b ldr r3, [r3, #0]
8004268: 691a ldr r2, [r3, #16]
800426a: 68fb ldr r3, [r7, #12]
800426c: 6a5b ldr r3, [r3, #36] @ 0x24
800426e: b2d2 uxtb r2, r2
8004270: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004272: 68fb ldr r3, [r7, #12]
8004274: 6a5b ldr r3, [r3, #36] @ 0x24
8004276: 1c5a adds r2, r3, #1
8004278: 68fb ldr r3, [r7, #12]
800427a: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800427c: 68fb ldr r3, [r7, #12]
800427e: 8d1b ldrh r3, [r3, #40] @ 0x28
8004280: 3b01 subs r3, #1
8004282: b29a uxth r2, r3
8004284: 68fb ldr r3, [r7, #12]
8004286: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004288: 68fb ldr r3, [r7, #12]
800428a: 8d5b ldrh r3, [r3, #42] @ 0x2a
800428c: b29b uxth r3, r3
800428e: 3b01 subs r3, #1
8004290: b29a uxth r2, r3
8004292: 68fb ldr r3, [r7, #12]
8004294: 855a strh r2, [r3, #42] @ 0x2a
8004296: e145 b.n 8004524 <HAL_I2C_Master_Receive+0x49c>
}
/* Two bytes */
else if (hi2c->XferSize == 2U)
8004298: 68fb ldr r3, [r7, #12]
800429a: 8d1b ldrh r3, [r3, #40] @ 0x28
800429c: 2b02 cmp r3, #2
800429e: d152 bne.n 8004346 <HAL_I2C_Master_Receive+0x2be>
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
80042a0: 6a7b ldr r3, [r7, #36] @ 0x24
80042a2: 9300 str r3, [sp, #0]
80042a4: 6b3b ldr r3, [r7, #48] @ 0x30
80042a6: 2200 movs r2, #0
80042a8: 4906 ldr r1, [pc, #24] @ (80042c4 <HAL_I2C_Master_Receive+0x23c>)
80042aa: 68f8 ldr r0, [r7, #12]
80042ac: f000 faa8 bl 8004800 <I2C_WaitOnFlagUntilTimeout>
80042b0: 4603 mov r3, r0
80042b2: 2b00 cmp r3, #0
80042b4: d008 beq.n 80042c8 <HAL_I2C_Master_Receive+0x240>
{
return HAL_ERROR;
80042b6: 2301 movs r3, #1
80042b8: e148 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
80042ba: bf00 nop
80042bc: 00100002 .word 0x00100002
80042c0: ffff0000 .word 0xffff0000
80042c4: 00010004 .word 0x00010004
__ASM volatile ("cpsid i" : : : "memory");
80042c8: b672 cpsid i
}
80042ca: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80042cc: 68fb ldr r3, [r7, #12]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 681a ldr r2, [r3, #0]
80042d2: 68fb ldr r3, [r7, #12]
80042d4: 681b ldr r3, [r3, #0]
80042d6: f442 7200 orr.w r2, r2, #512 @ 0x200
80042da: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80042dc: 68fb ldr r3, [r7, #12]
80042de: 681b ldr r3, [r3, #0]
80042e0: 691a ldr r2, [r3, #16]
80042e2: 68fb ldr r3, [r7, #12]
80042e4: 6a5b ldr r3, [r3, #36] @ 0x24
80042e6: b2d2 uxtb r2, r2
80042e8: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80042ea: 68fb ldr r3, [r7, #12]
80042ec: 6a5b ldr r3, [r3, #36] @ 0x24
80042ee: 1c5a adds r2, r3, #1
80042f0: 68fb ldr r3, [r7, #12]
80042f2: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80042f4: 68fb ldr r3, [r7, #12]
80042f6: 8d1b ldrh r3, [r3, #40] @ 0x28
80042f8: 3b01 subs r3, #1
80042fa: b29a uxth r2, r3
80042fc: 68fb ldr r3, [r7, #12]
80042fe: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004300: 68fb ldr r3, [r7, #12]
8004302: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004304: b29b uxth r3, r3
8004306: 3b01 subs r3, #1
8004308: b29a uxth r2, r3
800430a: 68fb ldr r3, [r7, #12]
800430c: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
800430e: b662 cpsie i
}
8004310: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004312: 68fb ldr r3, [r7, #12]
8004314: 681b ldr r3, [r3, #0]
8004316: 691a ldr r2, [r3, #16]
8004318: 68fb ldr r3, [r7, #12]
800431a: 6a5b ldr r3, [r3, #36] @ 0x24
800431c: b2d2 uxtb r2, r2
800431e: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004320: 68fb ldr r3, [r7, #12]
8004322: 6a5b ldr r3, [r3, #36] @ 0x24
8004324: 1c5a adds r2, r3, #1
8004326: 68fb ldr r3, [r7, #12]
8004328: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800432a: 68fb ldr r3, [r7, #12]
800432c: 8d1b ldrh r3, [r3, #40] @ 0x28
800432e: 3b01 subs r3, #1
8004330: b29a uxth r2, r3
8004332: 68fb ldr r3, [r7, #12]
8004334: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004336: 68fb ldr r3, [r7, #12]
8004338: 8d5b ldrh r3, [r3, #42] @ 0x2a
800433a: b29b uxth r3, r3
800433c: 3b01 subs r3, #1
800433e: b29a uxth r2, r3
8004340: 68fb ldr r3, [r7, #12]
8004342: 855a strh r2, [r3, #42] @ 0x2a
8004344: e0ee b.n 8004524 <HAL_I2C_Master_Receive+0x49c>
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
8004346: 6a7b ldr r3, [r7, #36] @ 0x24
8004348: 9300 str r3, [sp, #0]
800434a: 6b3b ldr r3, [r7, #48] @ 0x30
800434c: 2200 movs r2, #0
800434e: 4981 ldr r1, [pc, #516] @ (8004554 <HAL_I2C_Master_Receive+0x4cc>)
8004350: 68f8 ldr r0, [r7, #12]
8004352: f000 fa55 bl 8004800 <I2C_WaitOnFlagUntilTimeout>
8004356: 4603 mov r3, r0
8004358: 2b00 cmp r3, #0
800435a: d001 beq.n 8004360 <HAL_I2C_Master_Receive+0x2d8>
{
return HAL_ERROR;
800435c: 2301 movs r3, #1
800435e: e0f5 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004360: 68fb ldr r3, [r7, #12]
8004362: 681b ldr r3, [r3, #0]
8004364: 681a ldr r2, [r3, #0]
8004366: 68fb ldr r3, [r7, #12]
8004368: 681b ldr r3, [r3, #0]
800436a: f422 6280 bic.w r2, r2, #1024 @ 0x400
800436e: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8004370: b672 cpsid i
}
8004372: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004374: 68fb ldr r3, [r7, #12]
8004376: 681b ldr r3, [r3, #0]
8004378: 691a ldr r2, [r3, #16]
800437a: 68fb ldr r3, [r7, #12]
800437c: 6a5b ldr r3, [r3, #36] @ 0x24
800437e: b2d2 uxtb r2, r2
8004380: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004382: 68fb ldr r3, [r7, #12]
8004384: 6a5b ldr r3, [r3, #36] @ 0x24
8004386: 1c5a adds r2, r3, #1
8004388: 68fb ldr r3, [r7, #12]
800438a: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800438c: 68fb ldr r3, [r7, #12]
800438e: 8d1b ldrh r3, [r3, #40] @ 0x28
8004390: 3b01 subs r3, #1
8004392: b29a uxth r2, r3
8004394: 68fb ldr r3, [r7, #12]
8004396: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004398: 68fb ldr r3, [r7, #12]
800439a: 8d5b ldrh r3, [r3, #42] @ 0x2a
800439c: b29b uxth r3, r3
800439e: 3b01 subs r3, #1
80043a0: b29a uxth r2, r3
80043a2: 68fb ldr r3, [r7, #12]
80043a4: 855a strh r2, [r3, #42] @ 0x2a
/* Wait until BTF flag is set */
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
80043a6: 4b6c ldr r3, [pc, #432] @ (8004558 <HAL_I2C_Master_Receive+0x4d0>)
80043a8: 681b ldr r3, [r3, #0]
80043aa: 08db lsrs r3, r3, #3
80043ac: 4a6b ldr r2, [pc, #428] @ (800455c <HAL_I2C_Master_Receive+0x4d4>)
80043ae: fba2 2303 umull r2, r3, r2, r3
80043b2: 0a1a lsrs r2, r3, #8
80043b4: 4613 mov r3, r2
80043b6: 009b lsls r3, r3, #2
80043b8: 4413 add r3, r2
80043ba: 00da lsls r2, r3, #3
80043bc: 1ad3 subs r3, r2, r3
80043be: 623b str r3, [r7, #32]
do
{
count--;
80043c0: 6a3b ldr r3, [r7, #32]
80043c2: 3b01 subs r3, #1
80043c4: 623b str r3, [r7, #32]
if (count == 0U)
80043c6: 6a3b ldr r3, [r7, #32]
80043c8: 2b00 cmp r3, #0
80043ca: d118 bne.n 80043fe <HAL_I2C_Master_Receive+0x376>
{
hi2c->PreviousState = I2C_STATE_NONE;
80043cc: 68fb ldr r3, [r7, #12]
80043ce: 2200 movs r2, #0
80043d0: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80043d2: 68fb ldr r3, [r7, #12]
80043d4: 2220 movs r2, #32
80043d6: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80043da: 68fb ldr r3, [r7, #12]
80043dc: 2200 movs r2, #0
80043de: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80043e2: 68fb ldr r3, [r7, #12]
80043e4: 6c1b ldr r3, [r3, #64] @ 0x40
80043e6: f043 0220 orr.w r2, r3, #32
80043ea: 68fb ldr r3, [r7, #12]
80043ec: 641a str r2, [r3, #64] @ 0x40
__ASM volatile ("cpsie i" : : : "memory");
80043ee: b662 cpsie i
}
80043f0: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80043f2: 68fb ldr r3, [r7, #12]
80043f4: 2200 movs r2, #0
80043f6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80043fa: 2301 movs r3, #1
80043fc: e0a6 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
80043fe: 68fb ldr r3, [r7, #12]
8004400: 681b ldr r3, [r3, #0]
8004402: 695b ldr r3, [r3, #20]
8004404: f003 0304 and.w r3, r3, #4
8004408: 2b04 cmp r3, #4
800440a: d1d9 bne.n 80043c0 <HAL_I2C_Master_Receive+0x338>
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
800440c: 68fb ldr r3, [r7, #12]
800440e: 681b ldr r3, [r3, #0]
8004410: 681a ldr r2, [r3, #0]
8004412: 68fb ldr r3, [r7, #12]
8004414: 681b ldr r3, [r3, #0]
8004416: f442 7200 orr.w r2, r2, #512 @ 0x200
800441a: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800441c: 68fb ldr r3, [r7, #12]
800441e: 681b ldr r3, [r3, #0]
8004420: 691a ldr r2, [r3, #16]
8004422: 68fb ldr r3, [r7, #12]
8004424: 6a5b ldr r3, [r3, #36] @ 0x24
8004426: b2d2 uxtb r2, r2
8004428: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800442a: 68fb ldr r3, [r7, #12]
800442c: 6a5b ldr r3, [r3, #36] @ 0x24
800442e: 1c5a adds r2, r3, #1
8004430: 68fb ldr r3, [r7, #12]
8004432: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004434: 68fb ldr r3, [r7, #12]
8004436: 8d1b ldrh r3, [r3, #40] @ 0x28
8004438: 3b01 subs r3, #1
800443a: b29a uxth r2, r3
800443c: 68fb ldr r3, [r7, #12]
800443e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004440: 68fb ldr r3, [r7, #12]
8004442: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004444: b29b uxth r3, r3
8004446: 3b01 subs r3, #1
8004448: b29a uxth r2, r3
800444a: 68fb ldr r3, [r7, #12]
800444c: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
800444e: b662 cpsie i
}
8004450: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004452: 68fb ldr r3, [r7, #12]
8004454: 681b ldr r3, [r3, #0]
8004456: 691a ldr r2, [r3, #16]
8004458: 68fb ldr r3, [r7, #12]
800445a: 6a5b ldr r3, [r3, #36] @ 0x24
800445c: b2d2 uxtb r2, r2
800445e: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004460: 68fb ldr r3, [r7, #12]
8004462: 6a5b ldr r3, [r3, #36] @ 0x24
8004464: 1c5a adds r2, r3, #1
8004466: 68fb ldr r3, [r7, #12]
8004468: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800446a: 68fb ldr r3, [r7, #12]
800446c: 8d1b ldrh r3, [r3, #40] @ 0x28
800446e: 3b01 subs r3, #1
8004470: b29a uxth r2, r3
8004472: 68fb ldr r3, [r7, #12]
8004474: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004476: 68fb ldr r3, [r7, #12]
8004478: 8d5b ldrh r3, [r3, #42] @ 0x2a
800447a: b29b uxth r3, r3
800447c: 3b01 subs r3, #1
800447e: b29a uxth r2, r3
8004480: 68fb ldr r3, [r7, #12]
8004482: 855a strh r2, [r3, #42] @ 0x2a
8004484: e04e b.n 8004524 <HAL_I2C_Master_Receive+0x49c>
}
}
else
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004486: 6a7a ldr r2, [r7, #36] @ 0x24
8004488: 6b39 ldr r1, [r7, #48] @ 0x30
800448a: 68f8 ldr r0, [r7, #12]
800448c: f000 fb62 bl 8004b54 <I2C_WaitOnRXNEFlagUntilTimeout>
8004490: 4603 mov r3, r0
8004492: 2b00 cmp r3, #0
8004494: d001 beq.n 800449a <HAL_I2C_Master_Receive+0x412>
{
return HAL_ERROR;
8004496: 2301 movs r3, #1
8004498: e058 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800449a: 68fb ldr r3, [r7, #12]
800449c: 681b ldr r3, [r3, #0]
800449e: 691a ldr r2, [r3, #16]
80044a0: 68fb ldr r3, [r7, #12]
80044a2: 6a5b ldr r3, [r3, #36] @ 0x24
80044a4: b2d2 uxtb r2, r2
80044a6: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80044a8: 68fb ldr r3, [r7, #12]
80044aa: 6a5b ldr r3, [r3, #36] @ 0x24
80044ac: 1c5a adds r2, r3, #1
80044ae: 68fb ldr r3, [r7, #12]
80044b0: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80044b2: 68fb ldr r3, [r7, #12]
80044b4: 8d1b ldrh r3, [r3, #40] @ 0x28
80044b6: 3b01 subs r3, #1
80044b8: b29a uxth r2, r3
80044ba: 68fb ldr r3, [r7, #12]
80044bc: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80044be: 68fb ldr r3, [r7, #12]
80044c0: 8d5b ldrh r3, [r3, #42] @ 0x2a
80044c2: b29b uxth r3, r3
80044c4: 3b01 subs r3, #1
80044c6: b29a uxth r2, r3
80044c8: 68fb ldr r3, [r7, #12]
80044ca: 855a strh r2, [r3, #42] @ 0x2a
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
80044cc: 68fb ldr r3, [r7, #12]
80044ce: 681b ldr r3, [r3, #0]
80044d0: 695b ldr r3, [r3, #20]
80044d2: f003 0304 and.w r3, r3, #4
80044d6: 2b04 cmp r3, #4
80044d8: d124 bne.n 8004524 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize == 3U)
80044da: 68fb ldr r3, [r7, #12]
80044dc: 8d1b ldrh r3, [r3, #40] @ 0x28
80044de: 2b03 cmp r3, #3
80044e0: d107 bne.n 80044f2 <HAL_I2C_Master_Receive+0x46a>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80044e2: 68fb ldr r3, [r7, #12]
80044e4: 681b ldr r3, [r3, #0]
80044e6: 681a ldr r2, [r3, #0]
80044e8: 68fb ldr r3, [r7, #12]
80044ea: 681b ldr r3, [r3, #0]
80044ec: f422 6280 bic.w r2, r2, #1024 @ 0x400
80044f0: 601a str r2, [r3, #0]
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80044f2: 68fb ldr r3, [r7, #12]
80044f4: 681b ldr r3, [r3, #0]
80044f6: 691a ldr r2, [r3, #16]
80044f8: 68fb ldr r3, [r7, #12]
80044fa: 6a5b ldr r3, [r3, #36] @ 0x24
80044fc: b2d2 uxtb r2, r2
80044fe: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004500: 68fb ldr r3, [r7, #12]
8004502: 6a5b ldr r3, [r3, #36] @ 0x24
8004504: 1c5a adds r2, r3, #1
8004506: 68fb ldr r3, [r7, #12]
8004508: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800450a: 68fb ldr r3, [r7, #12]
800450c: 8d1b ldrh r3, [r3, #40] @ 0x28
800450e: 3b01 subs r3, #1
8004510: b29a uxth r2, r3
8004512: 68fb ldr r3, [r7, #12]
8004514: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004516: 68fb ldr r3, [r7, #12]
8004518: 8d5b ldrh r3, [r3, #42] @ 0x2a
800451a: b29b uxth r3, r3
800451c: 3b01 subs r3, #1
800451e: b29a uxth r2, r3
8004520: 68fb ldr r3, [r7, #12]
8004522: 855a strh r2, [r3, #42] @ 0x2a
while (hi2c->XferSize > 0U)
8004524: 68fb ldr r3, [r7, #12]
8004526: 8d1b ldrh r3, [r3, #40] @ 0x28
8004528: 2b00 cmp r3, #0
800452a: f47f ae88 bne.w 800423e <HAL_I2C_Master_Receive+0x1b6>
}
}
}
hi2c->State = HAL_I2C_STATE_READY;
800452e: 68fb ldr r3, [r7, #12]
8004530: 2220 movs r2, #32
8004532: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004536: 68fb ldr r3, [r7, #12]
8004538: 2200 movs r2, #0
800453a: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800453e: 68fb ldr r3, [r7, #12]
8004540: 2200 movs r2, #0
8004542: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8004546: 2300 movs r3, #0
8004548: e000 b.n 800454c <HAL_I2C_Master_Receive+0x4c4>
}
else
{
return HAL_BUSY;
800454a: 2302 movs r3, #2
}
}
800454c: 4618 mov r0, r3
800454e: 3728 adds r7, #40 @ 0x28
8004550: 46bd mov sp, r7
8004552: bd80 pop {r7, pc}
8004554: 00010004 .word 0x00010004
8004558: 20000018 .word 0x20000018
800455c: 14f8b589 .word 0x14f8b589
08004560 <I2C_MasterRequestWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
8004560: b580 push {r7, lr}
8004562: b088 sub sp, #32
8004564: af02 add r7, sp, #8
8004566: 60f8 str r0, [r7, #12]
8004568: 607a str r2, [r7, #4]
800456a: 603b str r3, [r7, #0]
800456c: 460b mov r3, r1
800456e: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
8004570: 68fb ldr r3, [r7, #12]
8004572: 6adb ldr r3, [r3, #44] @ 0x2c
8004574: 617b str r3, [r7, #20]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
8004576: 697b ldr r3, [r7, #20]
8004578: 2b08 cmp r3, #8
800457a: d006 beq.n 800458a <I2C_MasterRequestWrite+0x2a>
800457c: 697b ldr r3, [r7, #20]
800457e: 2b01 cmp r3, #1
8004580: d003 beq.n 800458a <I2C_MasterRequestWrite+0x2a>
8004582: 697b ldr r3, [r7, #20]
8004584: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004588: d108 bne.n 800459c <I2C_MasterRequestWrite+0x3c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800458a: 68fb ldr r3, [r7, #12]
800458c: 681b ldr r3, [r3, #0]
800458e: 681a ldr r2, [r3, #0]
8004590: 68fb ldr r3, [r7, #12]
8004592: 681b ldr r3, [r3, #0]
8004594: f442 7280 orr.w r2, r2, #256 @ 0x100
8004598: 601a str r2, [r3, #0]
800459a: e00b b.n 80045b4 <I2C_MasterRequestWrite+0x54>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
800459c: 68fb ldr r3, [r7, #12]
800459e: 6b1b ldr r3, [r3, #48] @ 0x30
80045a0: 2b12 cmp r3, #18
80045a2: d107 bne.n 80045b4 <I2C_MasterRequestWrite+0x54>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80045a4: 68fb ldr r3, [r7, #12]
80045a6: 681b ldr r3, [r3, #0]
80045a8: 681a ldr r2, [r3, #0]
80045aa: 68fb ldr r3, [r7, #12]
80045ac: 681b ldr r3, [r3, #0]
80045ae: f442 7280 orr.w r2, r2, #256 @ 0x100
80045b2: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
80045b4: 683b ldr r3, [r7, #0]
80045b6: 9300 str r3, [sp, #0]
80045b8: 687b ldr r3, [r7, #4]
80045ba: 2200 movs r2, #0
80045bc: f04f 1101 mov.w r1, #65537 @ 0x10001
80045c0: 68f8 ldr r0, [r7, #12]
80045c2: f000 f91d bl 8004800 <I2C_WaitOnFlagUntilTimeout>
80045c6: 4603 mov r3, r0
80045c8: 2b00 cmp r3, #0
80045ca: d00d beq.n 80045e8 <I2C_MasterRequestWrite+0x88>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80045cc: 68fb ldr r3, [r7, #12]
80045ce: 681b ldr r3, [r3, #0]
80045d0: 681b ldr r3, [r3, #0]
80045d2: f403 7380 and.w r3, r3, #256 @ 0x100
80045d6: f5b3 7f80 cmp.w r3, #256 @ 0x100
80045da: d103 bne.n 80045e4 <I2C_MasterRequestWrite+0x84>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80045dc: 68fb ldr r3, [r7, #12]
80045de: f44f 7200 mov.w r2, #512 @ 0x200
80045e2: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80045e4: 2303 movs r3, #3
80045e6: e035 b.n 8004654 <I2C_MasterRequestWrite+0xf4>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80045e8: 68fb ldr r3, [r7, #12]
80045ea: 691b ldr r3, [r3, #16]
80045ec: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80045f0: d108 bne.n 8004604 <I2C_MasterRequestWrite+0xa4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
80045f2: 897b ldrh r3, [r7, #10]
80045f4: b2db uxtb r3, r3
80045f6: 461a mov r2, r3
80045f8: 68fb ldr r3, [r7, #12]
80045fa: 681b ldr r3, [r3, #0]
80045fc: f002 02fe and.w r2, r2, #254 @ 0xfe
8004600: 611a str r2, [r3, #16]
8004602: e01b b.n 800463c <I2C_MasterRequestWrite+0xdc>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004604: 897b ldrh r3, [r7, #10]
8004606: 11db asrs r3, r3, #7
8004608: b2db uxtb r3, r3
800460a: f003 0306 and.w r3, r3, #6
800460e: b2db uxtb r3, r3
8004610: f063 030f orn r3, r3, #15
8004614: b2da uxtb r2, r3
8004616: 68fb ldr r3, [r7, #12]
8004618: 681b ldr r3, [r3, #0]
800461a: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
800461c: 683b ldr r3, [r7, #0]
800461e: 687a ldr r2, [r7, #4]
8004620: 490e ldr r1, [pc, #56] @ (800465c <I2C_MasterRequestWrite+0xfc>)
8004622: 68f8 ldr r0, [r7, #12]
8004624: f000 f966 bl 80048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004628: 4603 mov r3, r0
800462a: 2b00 cmp r3, #0
800462c: d001 beq.n 8004632 <I2C_MasterRequestWrite+0xd2>
{
return HAL_ERROR;
800462e: 2301 movs r3, #1
8004630: e010 b.n 8004654 <I2C_MasterRequestWrite+0xf4>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
8004632: 897b ldrh r3, [r7, #10]
8004634: b2da uxtb r2, r3
8004636: 68fb ldr r3, [r7, #12]
8004638: 681b ldr r3, [r3, #0]
800463a: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
800463c: 683b ldr r3, [r7, #0]
800463e: 687a ldr r2, [r7, #4]
8004640: 4907 ldr r1, [pc, #28] @ (8004660 <I2C_MasterRequestWrite+0x100>)
8004642: 68f8 ldr r0, [r7, #12]
8004644: f000 f956 bl 80048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004648: 4603 mov r3, r0
800464a: 2b00 cmp r3, #0
800464c: d001 beq.n 8004652 <I2C_MasterRequestWrite+0xf2>
{
return HAL_ERROR;
800464e: 2301 movs r3, #1
8004650: e000 b.n 8004654 <I2C_MasterRequestWrite+0xf4>
}
return HAL_OK;
8004652: 2300 movs r3, #0
}
8004654: 4618 mov r0, r3
8004656: 3718 adds r7, #24
8004658: 46bd mov sp, r7
800465a: bd80 pop {r7, pc}
800465c: 00010008 .word 0x00010008
8004660: 00010002 .word 0x00010002
08004664 <I2C_MasterRequestRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
8004664: b580 push {r7, lr}
8004666: b088 sub sp, #32
8004668: af02 add r7, sp, #8
800466a: 60f8 str r0, [r7, #12]
800466c: 607a str r2, [r7, #4]
800466e: 603b str r3, [r7, #0]
8004670: 460b mov r3, r1
8004672: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
8004674: 68fb ldr r3, [r7, #12]
8004676: 6adb ldr r3, [r3, #44] @ 0x2c
8004678: 617b str r3, [r7, #20]
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
800467a: 68fb ldr r3, [r7, #12]
800467c: 681b ldr r3, [r3, #0]
800467e: 681a ldr r2, [r3, #0]
8004680: 68fb ldr r3, [r7, #12]
8004682: 681b ldr r3, [r3, #0]
8004684: f442 6280 orr.w r2, r2, #1024 @ 0x400
8004688: 601a str r2, [r3, #0]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
800468a: 697b ldr r3, [r7, #20]
800468c: 2b08 cmp r3, #8
800468e: d006 beq.n 800469e <I2C_MasterRequestRead+0x3a>
8004690: 697b ldr r3, [r7, #20]
8004692: 2b01 cmp r3, #1
8004694: d003 beq.n 800469e <I2C_MasterRequestRead+0x3a>
8004696: 697b ldr r3, [r7, #20]
8004698: f513 3f80 cmn.w r3, #65536 @ 0x10000
800469c: d108 bne.n 80046b0 <I2C_MasterRequestRead+0x4c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800469e: 68fb ldr r3, [r7, #12]
80046a0: 681b ldr r3, [r3, #0]
80046a2: 681a ldr r2, [r3, #0]
80046a4: 68fb ldr r3, [r7, #12]
80046a6: 681b ldr r3, [r3, #0]
80046a8: f442 7280 orr.w r2, r2, #256 @ 0x100
80046ac: 601a str r2, [r3, #0]
80046ae: e00b b.n 80046c8 <I2C_MasterRequestRead+0x64>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
80046b0: 68fb ldr r3, [r7, #12]
80046b2: 6b1b ldr r3, [r3, #48] @ 0x30
80046b4: 2b11 cmp r3, #17
80046b6: d107 bne.n 80046c8 <I2C_MasterRequestRead+0x64>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80046b8: 68fb ldr r3, [r7, #12]
80046ba: 681b ldr r3, [r3, #0]
80046bc: 681a ldr r2, [r3, #0]
80046be: 68fb ldr r3, [r7, #12]
80046c0: 681b ldr r3, [r3, #0]
80046c2: f442 7280 orr.w r2, r2, #256 @ 0x100
80046c6: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
80046c8: 683b ldr r3, [r7, #0]
80046ca: 9300 str r3, [sp, #0]
80046cc: 687b ldr r3, [r7, #4]
80046ce: 2200 movs r2, #0
80046d0: f04f 1101 mov.w r1, #65537 @ 0x10001
80046d4: 68f8 ldr r0, [r7, #12]
80046d6: f000 f893 bl 8004800 <I2C_WaitOnFlagUntilTimeout>
80046da: 4603 mov r3, r0
80046dc: 2b00 cmp r3, #0
80046de: d00d beq.n 80046fc <I2C_MasterRequestRead+0x98>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80046e0: 68fb ldr r3, [r7, #12]
80046e2: 681b ldr r3, [r3, #0]
80046e4: 681b ldr r3, [r3, #0]
80046e6: f403 7380 and.w r3, r3, #256 @ 0x100
80046ea: f5b3 7f80 cmp.w r3, #256 @ 0x100
80046ee: d103 bne.n 80046f8 <I2C_MasterRequestRead+0x94>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80046f0: 68fb ldr r3, [r7, #12]
80046f2: f44f 7200 mov.w r2, #512 @ 0x200
80046f6: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80046f8: 2303 movs r3, #3
80046fa: e079 b.n 80047f0 <I2C_MasterRequestRead+0x18c>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80046fc: 68fb ldr r3, [r7, #12]
80046fe: 691b ldr r3, [r3, #16]
8004700: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8004704: d108 bne.n 8004718 <I2C_MasterRequestRead+0xb4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
8004706: 897b ldrh r3, [r7, #10]
8004708: b2db uxtb r3, r3
800470a: f043 0301 orr.w r3, r3, #1
800470e: b2da uxtb r2, r3
8004710: 68fb ldr r3, [r7, #12]
8004712: 681b ldr r3, [r3, #0]
8004714: 611a str r2, [r3, #16]
8004716: e05f b.n 80047d8 <I2C_MasterRequestRead+0x174>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004718: 897b ldrh r3, [r7, #10]
800471a: 11db asrs r3, r3, #7
800471c: b2db uxtb r3, r3
800471e: f003 0306 and.w r3, r3, #6
8004722: b2db uxtb r3, r3
8004724: f063 030f orn r3, r3, #15
8004728: b2da uxtb r2, r3
800472a: 68fb ldr r3, [r7, #12]
800472c: 681b ldr r3, [r3, #0]
800472e: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
8004730: 683b ldr r3, [r7, #0]
8004732: 687a ldr r2, [r7, #4]
8004734: 4930 ldr r1, [pc, #192] @ (80047f8 <I2C_MasterRequestRead+0x194>)
8004736: 68f8 ldr r0, [r7, #12]
8004738: f000 f8dc bl 80048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>
800473c: 4603 mov r3, r0
800473e: 2b00 cmp r3, #0
8004740: d001 beq.n 8004746 <I2C_MasterRequestRead+0xe2>
{
return HAL_ERROR;
8004742: 2301 movs r3, #1
8004744: e054 b.n 80047f0 <I2C_MasterRequestRead+0x18c>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
8004746: 897b ldrh r3, [r7, #10]
8004748: b2da uxtb r2, r3
800474a: 68fb ldr r3, [r7, #12]
800474c: 681b ldr r3, [r3, #0]
800474e: 611a str r2, [r3, #16]
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
8004750: 683b ldr r3, [r7, #0]
8004752: 687a ldr r2, [r7, #4]
8004754: 4929 ldr r1, [pc, #164] @ (80047fc <I2C_MasterRequestRead+0x198>)
8004756: 68f8 ldr r0, [r7, #12]
8004758: f000 f8cc bl 80048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>
800475c: 4603 mov r3, r0
800475e: 2b00 cmp r3, #0
8004760: d001 beq.n 8004766 <I2C_MasterRequestRead+0x102>
{
return HAL_ERROR;
8004762: 2301 movs r3, #1
8004764: e044 b.n 80047f0 <I2C_MasterRequestRead+0x18c>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004766: 2300 movs r3, #0
8004768: 613b str r3, [r7, #16]
800476a: 68fb ldr r3, [r7, #12]
800476c: 681b ldr r3, [r3, #0]
800476e: 695b ldr r3, [r3, #20]
8004770: 613b str r3, [r7, #16]
8004772: 68fb ldr r3, [r7, #12]
8004774: 681b ldr r3, [r3, #0]
8004776: 699b ldr r3, [r3, #24]
8004778: 613b str r3, [r7, #16]
800477a: 693b ldr r3, [r7, #16]
/* Generate Restart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800477c: 68fb ldr r3, [r7, #12]
800477e: 681b ldr r3, [r3, #0]
8004780: 681a ldr r2, [r3, #0]
8004782: 68fb ldr r3, [r7, #12]
8004784: 681b ldr r3, [r3, #0]
8004786: f442 7280 orr.w r2, r2, #256 @ 0x100
800478a: 601a str r2, [r3, #0]
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
800478c: 683b ldr r3, [r7, #0]
800478e: 9300 str r3, [sp, #0]
8004790: 687b ldr r3, [r7, #4]
8004792: 2200 movs r2, #0
8004794: f04f 1101 mov.w r1, #65537 @ 0x10001
8004798: 68f8 ldr r0, [r7, #12]
800479a: f000 f831 bl 8004800 <I2C_WaitOnFlagUntilTimeout>
800479e: 4603 mov r3, r0
80047a0: 2b00 cmp r3, #0
80047a2: d00d beq.n 80047c0 <I2C_MasterRequestRead+0x15c>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80047a4: 68fb ldr r3, [r7, #12]
80047a6: 681b ldr r3, [r3, #0]
80047a8: 681b ldr r3, [r3, #0]
80047aa: f403 7380 and.w r3, r3, #256 @ 0x100
80047ae: f5b3 7f80 cmp.w r3, #256 @ 0x100
80047b2: d103 bne.n 80047bc <I2C_MasterRequestRead+0x158>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80047b4: 68fb ldr r3, [r7, #12]
80047b6: f44f 7200 mov.w r2, #512 @ 0x200
80047ba: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80047bc: 2303 movs r3, #3
80047be: e017 b.n 80047f0 <I2C_MasterRequestRead+0x18c>
}
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
80047c0: 897b ldrh r3, [r7, #10]
80047c2: 11db asrs r3, r3, #7
80047c4: b2db uxtb r3, r3
80047c6: f003 0306 and.w r3, r3, #6
80047ca: b2db uxtb r3, r3
80047cc: f063 030e orn r3, r3, #14
80047d0: b2da uxtb r2, r3
80047d2: 68fb ldr r3, [r7, #12]
80047d4: 681b ldr r3, [r3, #0]
80047d6: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
80047d8: 683b ldr r3, [r7, #0]
80047da: 687a ldr r2, [r7, #4]
80047dc: 4907 ldr r1, [pc, #28] @ (80047fc <I2C_MasterRequestRead+0x198>)
80047de: 68f8 ldr r0, [r7, #12]
80047e0: f000 f888 bl 80048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80047e4: 4603 mov r3, r0
80047e6: 2b00 cmp r3, #0
80047e8: d001 beq.n 80047ee <I2C_MasterRequestRead+0x18a>
{
return HAL_ERROR;
80047ea: 2301 movs r3, #1
80047ec: e000 b.n 80047f0 <I2C_MasterRequestRead+0x18c>
}
return HAL_OK;
80047ee: 2300 movs r3, #0
}
80047f0: 4618 mov r0, r3
80047f2: 3718 adds r7, #24
80047f4: 46bd mov sp, r7
80047f6: bd80 pop {r7, pc}
80047f8: 00010008 .word 0x00010008
80047fc: 00010002 .word 0x00010002
08004800 <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
8004800: b580 push {r7, lr}
8004802: b084 sub sp, #16
8004804: af00 add r7, sp, #0
8004806: 60f8 str r0, [r7, #12]
8004808: 60b9 str r1, [r7, #8]
800480a: 603b str r3, [r7, #0]
800480c: 4613 mov r3, r2
800480e: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8004810: e048 b.n 80048a4 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004812: 683b ldr r3, [r7, #0]
8004814: f1b3 3fff cmp.w r3, #4294967295
8004818: d044 beq.n 80048a4 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800481a: f7fe fa27 bl 8002c6c <HAL_GetTick>
800481e: 4602 mov r2, r0
8004820: 69bb ldr r3, [r7, #24]
8004822: 1ad3 subs r3, r2, r3
8004824: 683a ldr r2, [r7, #0]
8004826: 429a cmp r2, r3
8004828: d302 bcc.n 8004830 <I2C_WaitOnFlagUntilTimeout+0x30>
800482a: 683b ldr r3, [r7, #0]
800482c: 2b00 cmp r3, #0
800482e: d139 bne.n 80048a4 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
8004830: 68bb ldr r3, [r7, #8]
8004832: 0c1b lsrs r3, r3, #16
8004834: b2db uxtb r3, r3
8004836: 2b01 cmp r3, #1
8004838: d10d bne.n 8004856 <I2C_WaitOnFlagUntilTimeout+0x56>
800483a: 68fb ldr r3, [r7, #12]
800483c: 681b ldr r3, [r3, #0]
800483e: 695b ldr r3, [r3, #20]
8004840: 43da mvns r2, r3
8004842: 68bb ldr r3, [r7, #8]
8004844: 4013 ands r3, r2
8004846: b29b uxth r3, r3
8004848: 2b00 cmp r3, #0
800484a: bf0c ite eq
800484c: 2301 moveq r3, #1
800484e: 2300 movne r3, #0
8004850: b2db uxtb r3, r3
8004852: 461a mov r2, r3
8004854: e00c b.n 8004870 <I2C_WaitOnFlagUntilTimeout+0x70>
8004856: 68fb ldr r3, [r7, #12]
8004858: 681b ldr r3, [r3, #0]
800485a: 699b ldr r3, [r3, #24]
800485c: 43da mvns r2, r3
800485e: 68bb ldr r3, [r7, #8]
8004860: 4013 ands r3, r2
8004862: b29b uxth r3, r3
8004864: 2b00 cmp r3, #0
8004866: bf0c ite eq
8004868: 2301 moveq r3, #1
800486a: 2300 movne r3, #0
800486c: b2db uxtb r3, r3
800486e: 461a mov r2, r3
8004870: 79fb ldrb r3, [r7, #7]
8004872: 429a cmp r2, r3
8004874: d116 bne.n 80048a4 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004876: 68fb ldr r3, [r7, #12]
8004878: 2200 movs r2, #0
800487a: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
800487c: 68fb ldr r3, [r7, #12]
800487e: 2220 movs r2, #32
8004880: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004884: 68fb ldr r3, [r7, #12]
8004886: 2200 movs r2, #0
8004888: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
800488c: 68fb ldr r3, [r7, #12]
800488e: 6c1b ldr r3, [r3, #64] @ 0x40
8004890: f043 0220 orr.w r2, r3, #32
8004894: 68fb ldr r3, [r7, #12]
8004896: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004898: 68fb ldr r3, [r7, #12]
800489a: 2200 movs r2, #0
800489c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80048a0: 2301 movs r3, #1
80048a2: e023 b.n 80048ec <I2C_WaitOnFlagUntilTimeout+0xec>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80048a4: 68bb ldr r3, [r7, #8]
80048a6: 0c1b lsrs r3, r3, #16
80048a8: b2db uxtb r3, r3
80048aa: 2b01 cmp r3, #1
80048ac: d10d bne.n 80048ca <I2C_WaitOnFlagUntilTimeout+0xca>
80048ae: 68fb ldr r3, [r7, #12]
80048b0: 681b ldr r3, [r3, #0]
80048b2: 695b ldr r3, [r3, #20]
80048b4: 43da mvns r2, r3
80048b6: 68bb ldr r3, [r7, #8]
80048b8: 4013 ands r3, r2
80048ba: b29b uxth r3, r3
80048bc: 2b00 cmp r3, #0
80048be: bf0c ite eq
80048c0: 2301 moveq r3, #1
80048c2: 2300 movne r3, #0
80048c4: b2db uxtb r3, r3
80048c6: 461a mov r2, r3
80048c8: e00c b.n 80048e4 <I2C_WaitOnFlagUntilTimeout+0xe4>
80048ca: 68fb ldr r3, [r7, #12]
80048cc: 681b ldr r3, [r3, #0]
80048ce: 699b ldr r3, [r3, #24]
80048d0: 43da mvns r2, r3
80048d2: 68bb ldr r3, [r7, #8]
80048d4: 4013 ands r3, r2
80048d6: b29b uxth r3, r3
80048d8: 2b00 cmp r3, #0
80048da: bf0c ite eq
80048dc: 2301 moveq r3, #1
80048de: 2300 movne r3, #0
80048e0: b2db uxtb r3, r3
80048e2: 461a mov r2, r3
80048e4: 79fb ldrb r3, [r7, #7]
80048e6: 429a cmp r2, r3
80048e8: d093 beq.n 8004812 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80048ea: 2300 movs r3, #0
}
80048ec: 4618 mov r0, r3
80048ee: 3710 adds r7, #16
80048f0: 46bd mov sp, r7
80048f2: bd80 pop {r7, pc}
080048f4 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
80048f4: b580 push {r7, lr}
80048f6: b084 sub sp, #16
80048f8: af00 add r7, sp, #0
80048fa: 60f8 str r0, [r7, #12]
80048fc: 60b9 str r1, [r7, #8]
80048fe: 607a str r2, [r7, #4]
8004900: 603b str r3, [r7, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
8004902: e071 b.n 80049e8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004904: 68fb ldr r3, [r7, #12]
8004906: 681b ldr r3, [r3, #0]
8004908: 695b ldr r3, [r3, #20]
800490a: f403 6380 and.w r3, r3, #1024 @ 0x400
800490e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004912: d123 bne.n 800495c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004914: 68fb ldr r3, [r7, #12]
8004916: 681b ldr r3, [r3, #0]
8004918: 681a ldr r2, [r3, #0]
800491a: 68fb ldr r3, [r7, #12]
800491c: 681b ldr r3, [r3, #0]
800491e: f442 7200 orr.w r2, r2, #512 @ 0x200
8004922: 601a str r2, [r3, #0]
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004924: 68fb ldr r3, [r7, #12]
8004926: 681b ldr r3, [r3, #0]
8004928: f46f 6280 mvn.w r2, #1024 @ 0x400
800492c: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
800492e: 68fb ldr r3, [r7, #12]
8004930: 2200 movs r2, #0
8004932: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004934: 68fb ldr r3, [r7, #12]
8004936: 2220 movs r2, #32
8004938: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
800493c: 68fb ldr r3, [r7, #12]
800493e: 2200 movs r2, #0
8004940: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004944: 68fb ldr r3, [r7, #12]
8004946: 6c1b ldr r3, [r3, #64] @ 0x40
8004948: f043 0204 orr.w r2, r3, #4
800494c: 68fb ldr r3, [r7, #12]
800494e: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004950: 68fb ldr r3, [r7, #12]
8004952: 2200 movs r2, #0
8004954: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004958: 2301 movs r3, #1
800495a: e067 b.n 8004a2c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800495c: 687b ldr r3, [r7, #4]
800495e: f1b3 3fff cmp.w r3, #4294967295
8004962: d041 beq.n 80049e8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004964: f7fe f982 bl 8002c6c <HAL_GetTick>
8004968: 4602 mov r2, r0
800496a: 683b ldr r3, [r7, #0]
800496c: 1ad3 subs r3, r2, r3
800496e: 687a ldr r2, [r7, #4]
8004970: 429a cmp r2, r3
8004972: d302 bcc.n 800497a <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
8004974: 687b ldr r3, [r7, #4]
8004976: 2b00 cmp r3, #0
8004978: d136 bne.n 80049e8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
800497a: 68bb ldr r3, [r7, #8]
800497c: 0c1b lsrs r3, r3, #16
800497e: b2db uxtb r3, r3
8004980: 2b01 cmp r3, #1
8004982: d10c bne.n 800499e <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
8004984: 68fb ldr r3, [r7, #12]
8004986: 681b ldr r3, [r3, #0]
8004988: 695b ldr r3, [r3, #20]
800498a: 43da mvns r2, r3
800498c: 68bb ldr r3, [r7, #8]
800498e: 4013 ands r3, r2
8004990: b29b uxth r3, r3
8004992: 2b00 cmp r3, #0
8004994: bf14 ite ne
8004996: 2301 movne r3, #1
8004998: 2300 moveq r3, #0
800499a: b2db uxtb r3, r3
800499c: e00b b.n 80049b6 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
800499e: 68fb ldr r3, [r7, #12]
80049a0: 681b ldr r3, [r3, #0]
80049a2: 699b ldr r3, [r3, #24]
80049a4: 43da mvns r2, r3
80049a6: 68bb ldr r3, [r7, #8]
80049a8: 4013 ands r3, r2
80049aa: b29b uxth r3, r3
80049ac: 2b00 cmp r3, #0
80049ae: bf14 ite ne
80049b0: 2301 movne r3, #1
80049b2: 2300 moveq r3, #0
80049b4: b2db uxtb r3, r3
80049b6: 2b00 cmp r3, #0
80049b8: d016 beq.n 80049e8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
hi2c->PreviousState = I2C_STATE_NONE;
80049ba: 68fb ldr r3, [r7, #12]
80049bc: 2200 movs r2, #0
80049be: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80049c0: 68fb ldr r3, [r7, #12]
80049c2: 2220 movs r2, #32
80049c4: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80049c8: 68fb ldr r3, [r7, #12]
80049ca: 2200 movs r2, #0
80049cc: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80049d0: 68fb ldr r3, [r7, #12]
80049d2: 6c1b ldr r3, [r3, #64] @ 0x40
80049d4: f043 0220 orr.w r2, r3, #32
80049d8: 68fb ldr r3, [r7, #12]
80049da: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80049dc: 68fb ldr r3, [r7, #12]
80049de: 2200 movs r2, #0
80049e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80049e4: 2301 movs r3, #1
80049e6: e021 b.n 8004a2c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
80049e8: 68bb ldr r3, [r7, #8]
80049ea: 0c1b lsrs r3, r3, #16
80049ec: b2db uxtb r3, r3
80049ee: 2b01 cmp r3, #1
80049f0: d10c bne.n 8004a0c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
80049f2: 68fb ldr r3, [r7, #12]
80049f4: 681b ldr r3, [r3, #0]
80049f6: 695b ldr r3, [r3, #20]
80049f8: 43da mvns r2, r3
80049fa: 68bb ldr r3, [r7, #8]
80049fc: 4013 ands r3, r2
80049fe: b29b uxth r3, r3
8004a00: 2b00 cmp r3, #0
8004a02: bf14 ite ne
8004a04: 2301 movne r3, #1
8004a06: 2300 moveq r3, #0
8004a08: b2db uxtb r3, r3
8004a0a: e00b b.n 8004a24 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
8004a0c: 68fb ldr r3, [r7, #12]
8004a0e: 681b ldr r3, [r3, #0]
8004a10: 699b ldr r3, [r3, #24]
8004a12: 43da mvns r2, r3
8004a14: 68bb ldr r3, [r7, #8]
8004a16: 4013 ands r3, r2
8004a18: b29b uxth r3, r3
8004a1a: 2b00 cmp r3, #0
8004a1c: bf14 ite ne
8004a1e: 2301 movne r3, #1
8004a20: 2300 moveq r3, #0
8004a22: b2db uxtb r3, r3
8004a24: 2b00 cmp r3, #0
8004a26: f47f af6d bne.w 8004904 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
}
}
}
}
return HAL_OK;
8004a2a: 2300 movs r3, #0
}
8004a2c: 4618 mov r0, r3
8004a2e: 3710 adds r7, #16
8004a30: 46bd mov sp, r7
8004a32: bd80 pop {r7, pc}
08004a34 <I2C_WaitOnTXEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004a34: b580 push {r7, lr}
8004a36: b084 sub sp, #16
8004a38: af00 add r7, sp, #0
8004a3a: 60f8 str r0, [r7, #12]
8004a3c: 60b9 str r1, [r7, #8]
8004a3e: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004a40: e034 b.n 8004aac <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004a42: 68f8 ldr r0, [r7, #12]
8004a44: f000 f8e3 bl 8004c0e <I2C_IsAcknowledgeFailed>
8004a48: 4603 mov r3, r0
8004a4a: 2b00 cmp r3, #0
8004a4c: d001 beq.n 8004a52 <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004a4e: 2301 movs r3, #1
8004a50: e034 b.n 8004abc <I2C_WaitOnTXEFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004a52: 68bb ldr r3, [r7, #8]
8004a54: f1b3 3fff cmp.w r3, #4294967295
8004a58: d028 beq.n 8004aac <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004a5a: f7fe f907 bl 8002c6c <HAL_GetTick>
8004a5e: 4602 mov r2, r0
8004a60: 687b ldr r3, [r7, #4]
8004a62: 1ad3 subs r3, r2, r3
8004a64: 68ba ldr r2, [r7, #8]
8004a66: 429a cmp r2, r3
8004a68: d302 bcc.n 8004a70 <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
8004a6a: 68bb ldr r3, [r7, #8]
8004a6c: 2b00 cmp r3, #0
8004a6e: d11d bne.n 8004aac <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
8004a70: 68fb ldr r3, [r7, #12]
8004a72: 681b ldr r3, [r3, #0]
8004a74: 695b ldr r3, [r3, #20]
8004a76: f003 0380 and.w r3, r3, #128 @ 0x80
8004a7a: 2b80 cmp r3, #128 @ 0x80
8004a7c: d016 beq.n 8004aac <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004a7e: 68fb ldr r3, [r7, #12]
8004a80: 2200 movs r2, #0
8004a82: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004a84: 68fb ldr r3, [r7, #12]
8004a86: 2220 movs r2, #32
8004a88: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004a8c: 68fb ldr r3, [r7, #12]
8004a8e: 2200 movs r2, #0
8004a90: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004a94: 68fb ldr r3, [r7, #12]
8004a96: 6c1b ldr r3, [r3, #64] @ 0x40
8004a98: f043 0220 orr.w r2, r3, #32
8004a9c: 68fb ldr r3, [r7, #12]
8004a9e: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004aa0: 68fb ldr r3, [r7, #12]
8004aa2: 2200 movs r2, #0
8004aa4: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004aa8: 2301 movs r3, #1
8004aaa: e007 b.n 8004abc <I2C_WaitOnTXEFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004aac: 68fb ldr r3, [r7, #12]
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 695b ldr r3, [r3, #20]
8004ab2: f003 0380 and.w r3, r3, #128 @ 0x80
8004ab6: 2b80 cmp r3, #128 @ 0x80
8004ab8: d1c3 bne.n 8004a42 <I2C_WaitOnTXEFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004aba: 2300 movs r3, #0
}
8004abc: 4618 mov r0, r3
8004abe: 3710 adds r7, #16
8004ac0: 46bd mov sp, r7
8004ac2: bd80 pop {r7, pc}
08004ac4 <I2C_WaitOnBTFFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004ac4: b580 push {r7, lr}
8004ac6: b084 sub sp, #16
8004ac8: af00 add r7, sp, #0
8004aca: 60f8 str r0, [r7, #12]
8004acc: 60b9 str r1, [r7, #8]
8004ace: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004ad0: e034 b.n 8004b3c <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004ad2: 68f8 ldr r0, [r7, #12]
8004ad4: f000 f89b bl 8004c0e <I2C_IsAcknowledgeFailed>
8004ad8: 4603 mov r3, r0
8004ada: 2b00 cmp r3, #0
8004adc: d001 beq.n 8004ae2 <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004ade: 2301 movs r3, #1
8004ae0: e034 b.n 8004b4c <I2C_WaitOnBTFFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004ae2: 68bb ldr r3, [r7, #8]
8004ae4: f1b3 3fff cmp.w r3, #4294967295
8004ae8: d028 beq.n 8004b3c <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004aea: f7fe f8bf bl 8002c6c <HAL_GetTick>
8004aee: 4602 mov r2, r0
8004af0: 687b ldr r3, [r7, #4]
8004af2: 1ad3 subs r3, r2, r3
8004af4: 68ba ldr r2, [r7, #8]
8004af6: 429a cmp r2, r3
8004af8: d302 bcc.n 8004b00 <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
8004afa: 68bb ldr r3, [r7, #8]
8004afc: 2b00 cmp r3, #0
8004afe: d11d bne.n 8004b3c <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
8004b00: 68fb ldr r3, [r7, #12]
8004b02: 681b ldr r3, [r3, #0]
8004b04: 695b ldr r3, [r3, #20]
8004b06: f003 0304 and.w r3, r3, #4
8004b0a: 2b04 cmp r3, #4
8004b0c: d016 beq.n 8004b3c <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004b0e: 68fb ldr r3, [r7, #12]
8004b10: 2200 movs r2, #0
8004b12: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004b14: 68fb ldr r3, [r7, #12]
8004b16: 2220 movs r2, #32
8004b18: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004b1c: 68fb ldr r3, [r7, #12]
8004b1e: 2200 movs r2, #0
8004b20: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004b24: 68fb ldr r3, [r7, #12]
8004b26: 6c1b ldr r3, [r3, #64] @ 0x40
8004b28: f043 0220 orr.w r2, r3, #32
8004b2c: 68fb ldr r3, [r7, #12]
8004b2e: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004b30: 68fb ldr r3, [r7, #12]
8004b32: 2200 movs r2, #0
8004b34: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004b38: 2301 movs r3, #1
8004b3a: e007 b.n 8004b4c <I2C_WaitOnBTFFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004b3c: 68fb ldr r3, [r7, #12]
8004b3e: 681b ldr r3, [r3, #0]
8004b40: 695b ldr r3, [r3, #20]
8004b42: f003 0304 and.w r3, r3, #4
8004b46: 2b04 cmp r3, #4
8004b48: d1c3 bne.n 8004ad2 <I2C_WaitOnBTFFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004b4a: 2300 movs r3, #0
}
8004b4c: 4618 mov r0, r3
8004b4e: 3710 adds r7, #16
8004b50: 46bd mov sp, r7
8004b52: bd80 pop {r7, pc}
08004b54 <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004b54: b580 push {r7, lr}
8004b56: b084 sub sp, #16
8004b58: af00 add r7, sp, #0
8004b5a: 60f8 str r0, [r7, #12]
8004b5c: 60b9 str r1, [r7, #8]
8004b5e: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004b60: e049 b.n 8004bf6 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
8004b62: 68fb ldr r3, [r7, #12]
8004b64: 681b ldr r3, [r3, #0]
8004b66: 695b ldr r3, [r3, #20]
8004b68: f003 0310 and.w r3, r3, #16
8004b6c: 2b10 cmp r3, #16
8004b6e: d119 bne.n 8004ba4 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8004b70: 68fb ldr r3, [r7, #12]
8004b72: 681b ldr r3, [r3, #0]
8004b74: f06f 0210 mvn.w r2, #16
8004b78: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004b7a: 68fb ldr r3, [r7, #12]
8004b7c: 2200 movs r2, #0
8004b7e: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 2220 movs r2, #32
8004b84: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004b88: 68fb ldr r3, [r7, #12]
8004b8a: 2200 movs r2, #0
8004b8c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
8004b90: 68fb ldr r3, [r7, #12]
8004b92: 6c1a ldr r2, [r3, #64] @ 0x40
8004b94: 68fb ldr r3, [r7, #12]
8004b96: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004b98: 68fb ldr r3, [r7, #12]
8004b9a: 2200 movs r2, #0
8004b9c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004ba0: 2301 movs r3, #1
8004ba2: e030 b.n 8004c06 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004ba4: f7fe f862 bl 8002c6c <HAL_GetTick>
8004ba8: 4602 mov r2, r0
8004baa: 687b ldr r3, [r7, #4]
8004bac: 1ad3 subs r3, r2, r3
8004bae: 68ba ldr r2, [r7, #8]
8004bb0: 429a cmp r2, r3
8004bb2: d302 bcc.n 8004bba <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
8004bb4: 68bb ldr r3, [r7, #8]
8004bb6: 2b00 cmp r3, #0
8004bb8: d11d bne.n 8004bf6 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
8004bba: 68fb ldr r3, [r7, #12]
8004bbc: 681b ldr r3, [r3, #0]
8004bbe: 695b ldr r3, [r3, #20]
8004bc0: f003 0340 and.w r3, r3, #64 @ 0x40
8004bc4: 2b40 cmp r3, #64 @ 0x40
8004bc6: d016 beq.n 8004bf6 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004bc8: 68fb ldr r3, [r7, #12]
8004bca: 2200 movs r2, #0
8004bcc: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004bce: 68fb ldr r3, [r7, #12]
8004bd0: 2220 movs r2, #32
8004bd2: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004bd6: 68fb ldr r3, [r7, #12]
8004bd8: 2200 movs r2, #0
8004bda: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004bde: 68fb ldr r3, [r7, #12]
8004be0: 6c1b ldr r3, [r3, #64] @ 0x40
8004be2: f043 0220 orr.w r2, r3, #32
8004be6: 68fb ldr r3, [r7, #12]
8004be8: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004bea: 68fb ldr r3, [r7, #12]
8004bec: 2200 movs r2, #0
8004bee: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004bf2: 2301 movs r3, #1
8004bf4: e007 b.n 8004c06 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004bf6: 68fb ldr r3, [r7, #12]
8004bf8: 681b ldr r3, [r3, #0]
8004bfa: 695b ldr r3, [r3, #20]
8004bfc: f003 0340 and.w r3, r3, #64 @ 0x40
8004c00: 2b40 cmp r3, #64 @ 0x40
8004c02: d1ae bne.n 8004b62 <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8004c04: 2300 movs r3, #0
}
8004c06: 4618 mov r0, r3
8004c08: 3710 adds r7, #16
8004c0a: 46bd mov sp, r7
8004c0c: bd80 pop {r7, pc}
08004c0e <I2C_IsAcknowledgeFailed>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
8004c0e: b480 push {r7}
8004c10: b083 sub sp, #12
8004c12: af00 add r7, sp, #0
8004c14: 6078 str r0, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004c16: 687b ldr r3, [r7, #4]
8004c18: 681b ldr r3, [r3, #0]
8004c1a: 695b ldr r3, [r3, #20]
8004c1c: f403 6380 and.w r3, r3, #1024 @ 0x400
8004c20: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004c24: d11b bne.n 8004c5e <I2C_IsAcknowledgeFailed+0x50>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004c26: 687b ldr r3, [r7, #4]
8004c28: 681b ldr r3, [r3, #0]
8004c2a: f46f 6280 mvn.w r2, #1024 @ 0x400
8004c2e: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004c30: 687b ldr r3, [r7, #4]
8004c32: 2200 movs r2, #0
8004c34: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004c36: 687b ldr r3, [r7, #4]
8004c38: 2220 movs r2, #32
8004c3a: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004c3e: 687b ldr r3, [r7, #4]
8004c40: 2200 movs r2, #0
8004c42: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004c46: 687b ldr r3, [r7, #4]
8004c48: 6c1b ldr r3, [r3, #64] @ 0x40
8004c4a: f043 0204 orr.w r2, r3, #4
8004c4e: 687b ldr r3, [r7, #4]
8004c50: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004c52: 687b ldr r3, [r7, #4]
8004c54: 2200 movs r2, #0
8004c56: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004c5a: 2301 movs r3, #1
8004c5c: e000 b.n 8004c60 <I2C_IsAcknowledgeFailed+0x52>
}
return HAL_OK;
8004c5e: 2300 movs r3, #0
}
8004c60: 4618 mov r0, r3
8004c62: 370c adds r7, #12
8004c64: 46bd mov sp, r7
8004c66: bc80 pop {r7}
8004c68: 4770 bx lr
...
08004c6c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004c6c: b580 push {r7, lr}
8004c6e: b086 sub sp, #24
8004c70: af00 add r7, sp, #0
8004c72: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004c74: 687b ldr r3, [r7, #4]
8004c76: 2b00 cmp r3, #0
8004c78: d101 bne.n 8004c7e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8004c7a: 2301 movs r3, #1
8004c7c: e272 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8004c7e: 687b ldr r3, [r7, #4]
8004c80: 681b ldr r3, [r3, #0]
8004c82: f003 0301 and.w r3, r3, #1
8004c86: 2b00 cmp r3, #0
8004c88: f000 8087 beq.w 8004d9a <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8004c8c: 4b92 ldr r3, [pc, #584] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004c8e: 685b ldr r3, [r3, #4]
8004c90: f003 030c and.w r3, r3, #12
8004c94: 2b04 cmp r3, #4
8004c96: d00c beq.n 8004cb2 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8004c98: 4b8f ldr r3, [pc, #572] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004c9a: 685b ldr r3, [r3, #4]
8004c9c: f003 030c and.w r3, r3, #12
8004ca0: 2b08 cmp r3, #8
8004ca2: d112 bne.n 8004cca <HAL_RCC_OscConfig+0x5e>
8004ca4: 4b8c ldr r3, [pc, #560] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004ca6: 685b ldr r3, [r3, #4]
8004ca8: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004cac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004cb0: d10b bne.n 8004cca <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004cb2: 4b89 ldr r3, [pc, #548] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cb4: 681b ldr r3, [r3, #0]
8004cb6: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004cba: 2b00 cmp r3, #0
8004cbc: d06c beq.n 8004d98 <HAL_RCC_OscConfig+0x12c>
8004cbe: 687b ldr r3, [r7, #4]
8004cc0: 685b ldr r3, [r3, #4]
8004cc2: 2b00 cmp r3, #0
8004cc4: d168 bne.n 8004d98 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8004cc6: 2301 movs r3, #1
8004cc8: e24c b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8004cca: 687b ldr r3, [r7, #4]
8004ccc: 685b ldr r3, [r3, #4]
8004cce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004cd2: d106 bne.n 8004ce2 <HAL_RCC_OscConfig+0x76>
8004cd4: 4b80 ldr r3, [pc, #512] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cd6: 681b ldr r3, [r3, #0]
8004cd8: 4a7f ldr r2, [pc, #508] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cda: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004cde: 6013 str r3, [r2, #0]
8004ce0: e02e b.n 8004d40 <HAL_RCC_OscConfig+0xd4>
8004ce2: 687b ldr r3, [r7, #4]
8004ce4: 685b ldr r3, [r3, #4]
8004ce6: 2b00 cmp r3, #0
8004ce8: d10c bne.n 8004d04 <HAL_RCC_OscConfig+0x98>
8004cea: 4b7b ldr r3, [pc, #492] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cec: 681b ldr r3, [r3, #0]
8004cee: 4a7a ldr r2, [pc, #488] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cf0: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004cf4: 6013 str r3, [r2, #0]
8004cf6: 4b78 ldr r3, [pc, #480] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cf8: 681b ldr r3, [r3, #0]
8004cfa: 4a77 ldr r2, [pc, #476] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004cfc: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004d00: 6013 str r3, [r2, #0]
8004d02: e01d b.n 8004d40 <HAL_RCC_OscConfig+0xd4>
8004d04: 687b ldr r3, [r7, #4]
8004d06: 685b ldr r3, [r3, #4]
8004d08: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004d0c: d10c bne.n 8004d28 <HAL_RCC_OscConfig+0xbc>
8004d0e: 4b72 ldr r3, [pc, #456] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d10: 681b ldr r3, [r3, #0]
8004d12: 4a71 ldr r2, [pc, #452] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d14: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8004d18: 6013 str r3, [r2, #0]
8004d1a: 4b6f ldr r3, [pc, #444] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d1c: 681b ldr r3, [r3, #0]
8004d1e: 4a6e ldr r2, [pc, #440] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d20: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004d24: 6013 str r3, [r2, #0]
8004d26: e00b b.n 8004d40 <HAL_RCC_OscConfig+0xd4>
8004d28: 4b6b ldr r3, [pc, #428] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d2a: 681b ldr r3, [r3, #0]
8004d2c: 4a6a ldr r2, [pc, #424] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d2e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004d32: 6013 str r3, [r2, #0]
8004d34: 4b68 ldr r3, [pc, #416] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d36: 681b ldr r3, [r3, #0]
8004d38: 4a67 ldr r2, [pc, #412] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d3a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004d3e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8004d40: 687b ldr r3, [r7, #4]
8004d42: 685b ldr r3, [r3, #4]
8004d44: 2b00 cmp r3, #0
8004d46: d013 beq.n 8004d70 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004d48: f7fd ff90 bl 8002c6c <HAL_GetTick>
8004d4c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004d4e: e008 b.n 8004d62 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004d50: f7fd ff8c bl 8002c6c <HAL_GetTick>
8004d54: 4602 mov r2, r0
8004d56: 693b ldr r3, [r7, #16]
8004d58: 1ad3 subs r3, r2, r3
8004d5a: 2b64 cmp r3, #100 @ 0x64
8004d5c: d901 bls.n 8004d62 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8004d5e: 2303 movs r3, #3
8004d60: e200 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004d62: 4b5d ldr r3, [pc, #372] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d64: 681b ldr r3, [r3, #0]
8004d66: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004d6a: 2b00 cmp r3, #0
8004d6c: d0f0 beq.n 8004d50 <HAL_RCC_OscConfig+0xe4>
8004d6e: e014 b.n 8004d9a <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004d70: f7fd ff7c bl 8002c6c <HAL_GetTick>
8004d74: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004d76: e008 b.n 8004d8a <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004d78: f7fd ff78 bl 8002c6c <HAL_GetTick>
8004d7c: 4602 mov r2, r0
8004d7e: 693b ldr r3, [r7, #16]
8004d80: 1ad3 subs r3, r2, r3
8004d82: 2b64 cmp r3, #100 @ 0x64
8004d84: d901 bls.n 8004d8a <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8004d86: 2303 movs r3, #3
8004d88: e1ec b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004d8a: 4b53 ldr r3, [pc, #332] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004d8c: 681b ldr r3, [r3, #0]
8004d8e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004d92: 2b00 cmp r3, #0
8004d94: d1f0 bne.n 8004d78 <HAL_RCC_OscConfig+0x10c>
8004d96: e000 b.n 8004d9a <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004d98: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8004d9a: 687b ldr r3, [r7, #4]
8004d9c: 681b ldr r3, [r3, #0]
8004d9e: f003 0302 and.w r3, r3, #2
8004da2: 2b00 cmp r3, #0
8004da4: d063 beq.n 8004e6e <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8004da6: 4b4c ldr r3, [pc, #304] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004da8: 685b ldr r3, [r3, #4]
8004daa: f003 030c and.w r3, r3, #12
8004dae: 2b00 cmp r3, #0
8004db0: d00b beq.n 8004dca <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8004db2: 4b49 ldr r3, [pc, #292] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004db4: 685b ldr r3, [r3, #4]
8004db6: f003 030c and.w r3, r3, #12
8004dba: 2b08 cmp r3, #8
8004dbc: d11c bne.n 8004df8 <HAL_RCC_OscConfig+0x18c>
8004dbe: 4b46 ldr r3, [pc, #280] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004dc0: 685b ldr r3, [r3, #4]
8004dc2: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004dc6: 2b00 cmp r3, #0
8004dc8: d116 bne.n 8004df8 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8004dca: 4b43 ldr r3, [pc, #268] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004dcc: 681b ldr r3, [r3, #0]
8004dce: f003 0302 and.w r3, r3, #2
8004dd2: 2b00 cmp r3, #0
8004dd4: d005 beq.n 8004de2 <HAL_RCC_OscConfig+0x176>
8004dd6: 687b ldr r3, [r7, #4]
8004dd8: 691b ldr r3, [r3, #16]
8004dda: 2b01 cmp r3, #1
8004ddc: d001 beq.n 8004de2 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8004dde: 2301 movs r3, #1
8004de0: e1c0 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004de2: 4b3d ldr r3, [pc, #244] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004de4: 681b ldr r3, [r3, #0]
8004de6: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8004dea: 687b ldr r3, [r7, #4]
8004dec: 695b ldr r3, [r3, #20]
8004dee: 00db lsls r3, r3, #3
8004df0: 4939 ldr r1, [pc, #228] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004df2: 4313 orrs r3, r2
8004df4: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8004df6: e03a b.n 8004e6e <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8004df8: 687b ldr r3, [r7, #4]
8004dfa: 691b ldr r3, [r3, #16]
8004dfc: 2b00 cmp r3, #0
8004dfe: d020 beq.n 8004e42 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8004e00: 4b36 ldr r3, [pc, #216] @ (8004edc <HAL_RCC_OscConfig+0x270>)
8004e02: 2201 movs r2, #1
8004e04: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004e06: f7fd ff31 bl 8002c6c <HAL_GetTick>
8004e0a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004e0c: e008 b.n 8004e20 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004e0e: f7fd ff2d bl 8002c6c <HAL_GetTick>
8004e12: 4602 mov r2, r0
8004e14: 693b ldr r3, [r7, #16]
8004e16: 1ad3 subs r3, r2, r3
8004e18: 2b02 cmp r3, #2
8004e1a: d901 bls.n 8004e20 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8004e1c: 2303 movs r3, #3
8004e1e: e1a1 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004e20: 4b2d ldr r3, [pc, #180] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004e22: 681b ldr r3, [r3, #0]
8004e24: f003 0302 and.w r3, r3, #2
8004e28: 2b00 cmp r3, #0
8004e2a: d0f0 beq.n 8004e0e <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004e2c: 4b2a ldr r3, [pc, #168] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004e2e: 681b ldr r3, [r3, #0]
8004e30: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8004e34: 687b ldr r3, [r7, #4]
8004e36: 695b ldr r3, [r3, #20]
8004e38: 00db lsls r3, r3, #3
8004e3a: 4927 ldr r1, [pc, #156] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004e3c: 4313 orrs r3, r2
8004e3e: 600b str r3, [r1, #0]
8004e40: e015 b.n 8004e6e <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8004e42: 4b26 ldr r3, [pc, #152] @ (8004edc <HAL_RCC_OscConfig+0x270>)
8004e44: 2200 movs r2, #0
8004e46: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004e48: f7fd ff10 bl 8002c6c <HAL_GetTick>
8004e4c: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8004e4e: e008 b.n 8004e62 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004e50: f7fd ff0c bl 8002c6c <HAL_GetTick>
8004e54: 4602 mov r2, r0
8004e56: 693b ldr r3, [r7, #16]
8004e58: 1ad3 subs r3, r2, r3
8004e5a: 2b02 cmp r3, #2
8004e5c: d901 bls.n 8004e62 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8004e5e: 2303 movs r3, #3
8004e60: e180 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8004e62: 4b1d ldr r3, [pc, #116] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004e64: 681b ldr r3, [r3, #0]
8004e66: f003 0302 and.w r3, r3, #2
8004e6a: 2b00 cmp r3, #0
8004e6c: d1f0 bne.n 8004e50 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8004e6e: 687b ldr r3, [r7, #4]
8004e70: 681b ldr r3, [r3, #0]
8004e72: f003 0308 and.w r3, r3, #8
8004e76: 2b00 cmp r3, #0
8004e78: d03a beq.n 8004ef0 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8004e7a: 687b ldr r3, [r7, #4]
8004e7c: 699b ldr r3, [r3, #24]
8004e7e: 2b00 cmp r3, #0
8004e80: d019 beq.n 8004eb6 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8004e82: 4b17 ldr r3, [pc, #92] @ (8004ee0 <HAL_RCC_OscConfig+0x274>)
8004e84: 2201 movs r2, #1
8004e86: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004e88: f7fd fef0 bl 8002c6c <HAL_GetTick>
8004e8c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8004e8e: e008 b.n 8004ea2 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8004e90: f7fd feec bl 8002c6c <HAL_GetTick>
8004e94: 4602 mov r2, r0
8004e96: 693b ldr r3, [r7, #16]
8004e98: 1ad3 subs r3, r2, r3
8004e9a: 2b02 cmp r3, #2
8004e9c: d901 bls.n 8004ea2 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8004e9e: 2303 movs r3, #3
8004ea0: e160 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8004ea2: 4b0d ldr r3, [pc, #52] @ (8004ed8 <HAL_RCC_OscConfig+0x26c>)
8004ea4: 6a5b ldr r3, [r3, #36] @ 0x24
8004ea6: f003 0302 and.w r3, r3, #2
8004eaa: 2b00 cmp r3, #0
8004eac: d0f0 beq.n 8004e90 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8004eae: 2001 movs r0, #1
8004eb0: f000 fad0 bl 8005454 <RCC_Delay>
8004eb4: e01c b.n 8004ef0 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8004eb6: 4b0a ldr r3, [pc, #40] @ (8004ee0 <HAL_RCC_OscConfig+0x274>)
8004eb8: 2200 movs r2, #0
8004eba: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004ebc: f7fd fed6 bl 8002c6c <HAL_GetTick>
8004ec0: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8004ec2: e00f b.n 8004ee4 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8004ec4: f7fd fed2 bl 8002c6c <HAL_GetTick>
8004ec8: 4602 mov r2, r0
8004eca: 693b ldr r3, [r7, #16]
8004ecc: 1ad3 subs r3, r2, r3
8004ece: 2b02 cmp r3, #2
8004ed0: d908 bls.n 8004ee4 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8004ed2: 2303 movs r3, #3
8004ed4: e146 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
8004ed6: bf00 nop
8004ed8: 40021000 .word 0x40021000
8004edc: 42420000 .word 0x42420000
8004ee0: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8004ee4: 4b92 ldr r3, [pc, #584] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004ee6: 6a5b ldr r3, [r3, #36] @ 0x24
8004ee8: f003 0302 and.w r3, r3, #2
8004eec: 2b00 cmp r3, #0
8004eee: d1e9 bne.n 8004ec4 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8004ef0: 687b ldr r3, [r7, #4]
8004ef2: 681b ldr r3, [r3, #0]
8004ef4: f003 0304 and.w r3, r3, #4
8004ef8: 2b00 cmp r3, #0
8004efa: f000 80a6 beq.w 800504a <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8004efe: 2300 movs r3, #0
8004f00: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8004f02: 4b8b ldr r3, [pc, #556] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f04: 69db ldr r3, [r3, #28]
8004f06: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004f0a: 2b00 cmp r3, #0
8004f0c: d10d bne.n 8004f2a <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004f0e: 4b88 ldr r3, [pc, #544] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f10: 69db ldr r3, [r3, #28]
8004f12: 4a87 ldr r2, [pc, #540] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f14: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004f18: 61d3 str r3, [r2, #28]
8004f1a: 4b85 ldr r3, [pc, #532] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f1c: 69db ldr r3, [r3, #28]
8004f1e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004f22: 60bb str r3, [r7, #8]
8004f24: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004f26: 2301 movs r3, #1
8004f28: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f2a: 4b82 ldr r3, [pc, #520] @ (8005134 <HAL_RCC_OscConfig+0x4c8>)
8004f2c: 681b ldr r3, [r3, #0]
8004f2e: f403 7380 and.w r3, r3, #256 @ 0x100
8004f32: 2b00 cmp r3, #0
8004f34: d118 bne.n 8004f68 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8004f36: 4b7f ldr r3, [pc, #508] @ (8005134 <HAL_RCC_OscConfig+0x4c8>)
8004f38: 681b ldr r3, [r3, #0]
8004f3a: 4a7e ldr r2, [pc, #504] @ (8005134 <HAL_RCC_OscConfig+0x4c8>)
8004f3c: f443 7380 orr.w r3, r3, #256 @ 0x100
8004f40: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004f42: f7fd fe93 bl 8002c6c <HAL_GetTick>
8004f46: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f48: e008 b.n 8004f5c <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004f4a: f7fd fe8f bl 8002c6c <HAL_GetTick>
8004f4e: 4602 mov r2, r0
8004f50: 693b ldr r3, [r7, #16]
8004f52: 1ad3 subs r3, r2, r3
8004f54: 2b64 cmp r3, #100 @ 0x64
8004f56: d901 bls.n 8004f5c <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8004f58: 2303 movs r3, #3
8004f5a: e103 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004f5c: 4b75 ldr r3, [pc, #468] @ (8005134 <HAL_RCC_OscConfig+0x4c8>)
8004f5e: 681b ldr r3, [r3, #0]
8004f60: f403 7380 and.w r3, r3, #256 @ 0x100
8004f64: 2b00 cmp r3, #0
8004f66: d0f0 beq.n 8004f4a <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8004f68: 687b ldr r3, [r7, #4]
8004f6a: 68db ldr r3, [r3, #12]
8004f6c: 2b01 cmp r3, #1
8004f6e: d106 bne.n 8004f7e <HAL_RCC_OscConfig+0x312>
8004f70: 4b6f ldr r3, [pc, #444] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f72: 6a1b ldr r3, [r3, #32]
8004f74: 4a6e ldr r2, [pc, #440] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f76: f043 0301 orr.w r3, r3, #1
8004f7a: 6213 str r3, [r2, #32]
8004f7c: e02d b.n 8004fda <HAL_RCC_OscConfig+0x36e>
8004f7e: 687b ldr r3, [r7, #4]
8004f80: 68db ldr r3, [r3, #12]
8004f82: 2b00 cmp r3, #0
8004f84: d10c bne.n 8004fa0 <HAL_RCC_OscConfig+0x334>
8004f86: 4b6a ldr r3, [pc, #424] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f88: 6a1b ldr r3, [r3, #32]
8004f8a: 4a69 ldr r2, [pc, #420] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f8c: f023 0301 bic.w r3, r3, #1
8004f90: 6213 str r3, [r2, #32]
8004f92: 4b67 ldr r3, [pc, #412] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f94: 6a1b ldr r3, [r3, #32]
8004f96: 4a66 ldr r2, [pc, #408] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004f98: f023 0304 bic.w r3, r3, #4
8004f9c: 6213 str r3, [r2, #32]
8004f9e: e01c b.n 8004fda <HAL_RCC_OscConfig+0x36e>
8004fa0: 687b ldr r3, [r7, #4]
8004fa2: 68db ldr r3, [r3, #12]
8004fa4: 2b05 cmp r3, #5
8004fa6: d10c bne.n 8004fc2 <HAL_RCC_OscConfig+0x356>
8004fa8: 4b61 ldr r3, [pc, #388] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004faa: 6a1b ldr r3, [r3, #32]
8004fac: 4a60 ldr r2, [pc, #384] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fae: f043 0304 orr.w r3, r3, #4
8004fb2: 6213 str r3, [r2, #32]
8004fb4: 4b5e ldr r3, [pc, #376] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fb6: 6a1b ldr r3, [r3, #32]
8004fb8: 4a5d ldr r2, [pc, #372] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fba: f043 0301 orr.w r3, r3, #1
8004fbe: 6213 str r3, [r2, #32]
8004fc0: e00b b.n 8004fda <HAL_RCC_OscConfig+0x36e>
8004fc2: 4b5b ldr r3, [pc, #364] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fc4: 6a1b ldr r3, [r3, #32]
8004fc6: 4a5a ldr r2, [pc, #360] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fc8: f023 0301 bic.w r3, r3, #1
8004fcc: 6213 str r3, [r2, #32]
8004fce: 4b58 ldr r3, [pc, #352] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fd0: 6a1b ldr r3, [r3, #32]
8004fd2: 4a57 ldr r2, [pc, #348] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8004fd4: f023 0304 bic.w r3, r3, #4
8004fd8: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8004fda: 687b ldr r3, [r7, #4]
8004fdc: 68db ldr r3, [r3, #12]
8004fde: 2b00 cmp r3, #0
8004fe0: d015 beq.n 800500e <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004fe2: f7fd fe43 bl 8002c6c <HAL_GetTick>
8004fe6: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004fe8: e00a b.n 8005000 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004fea: f7fd fe3f bl 8002c6c <HAL_GetTick>
8004fee: 4602 mov r2, r0
8004ff0: 693b ldr r3, [r7, #16]
8004ff2: 1ad3 subs r3, r2, r3
8004ff4: f241 3288 movw r2, #5000 @ 0x1388
8004ff8: 4293 cmp r3, r2
8004ffa: d901 bls.n 8005000 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8004ffc: 2303 movs r3, #3
8004ffe: e0b1 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005000: 4b4b ldr r3, [pc, #300] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8005002: 6a1b ldr r3, [r3, #32]
8005004: f003 0302 and.w r3, r3, #2
8005008: 2b00 cmp r3, #0
800500a: d0ee beq.n 8004fea <HAL_RCC_OscConfig+0x37e>
800500c: e014 b.n 8005038 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800500e: f7fd fe2d bl 8002c6c <HAL_GetTick>
8005012: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8005014: e00a b.n 800502c <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005016: f7fd fe29 bl 8002c6c <HAL_GetTick>
800501a: 4602 mov r2, r0
800501c: 693b ldr r3, [r7, #16]
800501e: 1ad3 subs r3, r2, r3
8005020: f241 3288 movw r2, #5000 @ 0x1388
8005024: 4293 cmp r3, r2
8005026: d901 bls.n 800502c <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8005028: 2303 movs r3, #3
800502a: e09b b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800502c: 4b40 ldr r3, [pc, #256] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
800502e: 6a1b ldr r3, [r3, #32]
8005030: f003 0302 and.w r3, r3, #2
8005034: 2b00 cmp r3, #0
8005036: d1ee bne.n 8005016 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005038: 7dfb ldrb r3, [r7, #23]
800503a: 2b01 cmp r3, #1
800503c: d105 bne.n 800504a <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
800503e: 4b3c ldr r3, [pc, #240] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8005040: 69db ldr r3, [r3, #28]
8005042: 4a3b ldr r2, [pc, #236] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8005044: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005048: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800504a: 687b ldr r3, [r7, #4]
800504c: 69db ldr r3, [r3, #28]
800504e: 2b00 cmp r3, #0
8005050: f000 8087 beq.w 8005162 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8005054: 4b36 ldr r3, [pc, #216] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8005056: 685b ldr r3, [r3, #4]
8005058: f003 030c and.w r3, r3, #12
800505c: 2b08 cmp r3, #8
800505e: d061 beq.n 8005124 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8005060: 687b ldr r3, [r7, #4]
8005062: 69db ldr r3, [r3, #28]
8005064: 2b02 cmp r3, #2
8005066: d146 bne.n 80050f6 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8005068: 4b33 ldr r3, [pc, #204] @ (8005138 <HAL_RCC_OscConfig+0x4cc>)
800506a: 2200 movs r2, #0
800506c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800506e: f7fd fdfd bl 8002c6c <HAL_GetTick>
8005072: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005074: e008 b.n 8005088 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005076: f7fd fdf9 bl 8002c6c <HAL_GetTick>
800507a: 4602 mov r2, r0
800507c: 693b ldr r3, [r7, #16]
800507e: 1ad3 subs r3, r2, r3
8005080: 2b02 cmp r3, #2
8005082: d901 bls.n 8005088 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8005084: 2303 movs r3, #3
8005086: e06d b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005088: 4b29 ldr r3, [pc, #164] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
800508a: 681b ldr r3, [r3, #0]
800508c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005090: 2b00 cmp r3, #0
8005092: d1f0 bne.n 8005076 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8005094: 687b ldr r3, [r7, #4]
8005096: 6a1b ldr r3, [r3, #32]
8005098: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800509c: d108 bne.n 80050b0 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
800509e: 4b24 ldr r3, [pc, #144] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
80050a0: 685b ldr r3, [r3, #4]
80050a2: f423 3200 bic.w r2, r3, #131072 @ 0x20000
80050a6: 687b ldr r3, [r7, #4]
80050a8: 689b ldr r3, [r3, #8]
80050aa: 4921 ldr r1, [pc, #132] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
80050ac: 4313 orrs r3, r2
80050ae: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80050b0: 4b1f ldr r3, [pc, #124] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
80050b2: 685b ldr r3, [r3, #4]
80050b4: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
80050b8: 687b ldr r3, [r7, #4]
80050ba: 6a19 ldr r1, [r3, #32]
80050bc: 687b ldr r3, [r7, #4]
80050be: 6a5b ldr r3, [r3, #36] @ 0x24
80050c0: 430b orrs r3, r1
80050c2: 491b ldr r1, [pc, #108] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
80050c4: 4313 orrs r3, r2
80050c6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80050c8: 4b1b ldr r3, [pc, #108] @ (8005138 <HAL_RCC_OscConfig+0x4cc>)
80050ca: 2201 movs r2, #1
80050cc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80050ce: f7fd fdcd bl 8002c6c <HAL_GetTick>
80050d2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80050d4: e008 b.n 80050e8 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80050d6: f7fd fdc9 bl 8002c6c <HAL_GetTick>
80050da: 4602 mov r2, r0
80050dc: 693b ldr r3, [r7, #16]
80050de: 1ad3 subs r3, r2, r3
80050e0: 2b02 cmp r3, #2
80050e2: d901 bls.n 80050e8 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
80050e4: 2303 movs r3, #3
80050e6: e03d b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80050e8: 4b11 ldr r3, [pc, #68] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
80050ea: 681b ldr r3, [r3, #0]
80050ec: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80050f0: 2b00 cmp r3, #0
80050f2: d0f0 beq.n 80050d6 <HAL_RCC_OscConfig+0x46a>
80050f4: e035 b.n 8005162 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80050f6: 4b10 ldr r3, [pc, #64] @ (8005138 <HAL_RCC_OscConfig+0x4cc>)
80050f8: 2200 movs r2, #0
80050fa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80050fc: f7fd fdb6 bl 8002c6c <HAL_GetTick>
8005100: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005102: e008 b.n 8005116 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005104: f7fd fdb2 bl 8002c6c <HAL_GetTick>
8005108: 4602 mov r2, r0
800510a: 693b ldr r3, [r7, #16]
800510c: 1ad3 subs r3, r2, r3
800510e: 2b02 cmp r3, #2
8005110: d901 bls.n 8005116 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8005112: 2303 movs r3, #3
8005114: e026 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005116: 4b06 ldr r3, [pc, #24] @ (8005130 <HAL_RCC_OscConfig+0x4c4>)
8005118: 681b ldr r3, [r3, #0]
800511a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800511e: 2b00 cmp r3, #0
8005120: d1f0 bne.n 8005104 <HAL_RCC_OscConfig+0x498>
8005122: e01e b.n 8005162 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8005124: 687b ldr r3, [r7, #4]
8005126: 69db ldr r3, [r3, #28]
8005128: 2b01 cmp r3, #1
800512a: d107 bne.n 800513c <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
800512c: 2301 movs r3, #1
800512e: e019 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
8005130: 40021000 .word 0x40021000
8005134: 40007000 .word 0x40007000
8005138: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800513c: 4b0b ldr r3, [pc, #44] @ (800516c <HAL_RCC_OscConfig+0x500>)
800513e: 685b ldr r3, [r3, #4]
8005140: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8005142: 68fb ldr r3, [r7, #12]
8005144: f403 3280 and.w r2, r3, #65536 @ 0x10000
8005148: 687b ldr r3, [r7, #4]
800514a: 6a1b ldr r3, [r3, #32]
800514c: 429a cmp r2, r3
800514e: d106 bne.n 800515e <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8005150: 68fb ldr r3, [r7, #12]
8005152: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8005156: 687b ldr r3, [r7, #4]
8005158: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800515a: 429a cmp r2, r3
800515c: d001 beq.n 8005162 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
800515e: 2301 movs r3, #1
8005160: e000 b.n 8005164 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
8005162: 2300 movs r3, #0
}
8005164: 4618 mov r0, r3
8005166: 3718 adds r7, #24
8005168: 46bd mov sp, r7
800516a: bd80 pop {r7, pc}
800516c: 40021000 .word 0x40021000
08005170 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8005170: b580 push {r7, lr}
8005172: b084 sub sp, #16
8005174: af00 add r7, sp, #0
8005176: 6078 str r0, [r7, #4]
8005178: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
800517a: 687b ldr r3, [r7, #4]
800517c: 2b00 cmp r3, #0
800517e: d101 bne.n 8005184 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8005180: 2301 movs r3, #1
8005182: e0d0 b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8005184: 4b6a ldr r3, [pc, #424] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
8005186: 681b ldr r3, [r3, #0]
8005188: f003 0307 and.w r3, r3, #7
800518c: 683a ldr r2, [r7, #0]
800518e: 429a cmp r2, r3
8005190: d910 bls.n 80051b4 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8005192: 4b67 ldr r3, [pc, #412] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
8005194: 681b ldr r3, [r3, #0]
8005196: f023 0207 bic.w r2, r3, #7
800519a: 4965 ldr r1, [pc, #404] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
800519c: 683b ldr r3, [r7, #0]
800519e: 4313 orrs r3, r2
80051a0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80051a2: 4b63 ldr r3, [pc, #396] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
80051a4: 681b ldr r3, [r3, #0]
80051a6: f003 0307 and.w r3, r3, #7
80051aa: 683a ldr r2, [r7, #0]
80051ac: 429a cmp r2, r3
80051ae: d001 beq.n 80051b4 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
80051b0: 2301 movs r3, #1
80051b2: e0b8 b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80051b4: 687b ldr r3, [r7, #4]
80051b6: 681b ldr r3, [r3, #0]
80051b8: f003 0302 and.w r3, r3, #2
80051bc: 2b00 cmp r3, #0
80051be: d020 beq.n 8005202 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80051c0: 687b ldr r3, [r7, #4]
80051c2: 681b ldr r3, [r3, #0]
80051c4: f003 0304 and.w r3, r3, #4
80051c8: 2b00 cmp r3, #0
80051ca: d005 beq.n 80051d8 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80051cc: 4b59 ldr r3, [pc, #356] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051ce: 685b ldr r3, [r3, #4]
80051d0: 4a58 ldr r2, [pc, #352] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051d2: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80051d6: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80051d8: 687b ldr r3, [r7, #4]
80051da: 681b ldr r3, [r3, #0]
80051dc: f003 0308 and.w r3, r3, #8
80051e0: 2b00 cmp r3, #0
80051e2: d005 beq.n 80051f0 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80051e4: 4b53 ldr r3, [pc, #332] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051e6: 685b ldr r3, [r3, #4]
80051e8: 4a52 ldr r2, [pc, #328] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051ea: f443 5360 orr.w r3, r3, #14336 @ 0x3800
80051ee: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80051f0: 4b50 ldr r3, [pc, #320] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051f2: 685b ldr r3, [r3, #4]
80051f4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80051f8: 687b ldr r3, [r7, #4]
80051fa: 689b ldr r3, [r3, #8]
80051fc: 494d ldr r1, [pc, #308] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80051fe: 4313 orrs r3, r2
8005200: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8005202: 687b ldr r3, [r7, #4]
8005204: 681b ldr r3, [r3, #0]
8005206: f003 0301 and.w r3, r3, #1
800520a: 2b00 cmp r3, #0
800520c: d040 beq.n 8005290 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800520e: 687b ldr r3, [r7, #4]
8005210: 685b ldr r3, [r3, #4]
8005212: 2b01 cmp r3, #1
8005214: d107 bne.n 8005226 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8005216: 4b47 ldr r3, [pc, #284] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005218: 681b ldr r3, [r3, #0]
800521a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800521e: 2b00 cmp r3, #0
8005220: d115 bne.n 800524e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8005222: 2301 movs r3, #1
8005224: e07f b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8005226: 687b ldr r3, [r7, #4]
8005228: 685b ldr r3, [r3, #4]
800522a: 2b02 cmp r3, #2
800522c: d107 bne.n 800523e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800522e: 4b41 ldr r3, [pc, #260] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005230: 681b ldr r3, [r3, #0]
8005232: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005236: 2b00 cmp r3, #0
8005238: d109 bne.n 800524e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800523a: 2301 movs r3, #1
800523c: e073 b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800523e: 4b3d ldr r3, [pc, #244] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005240: 681b ldr r3, [r3, #0]
8005242: f003 0302 and.w r3, r3, #2
8005246: 2b00 cmp r3, #0
8005248: d101 bne.n 800524e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800524a: 2301 movs r3, #1
800524c: e06b b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800524e: 4b39 ldr r3, [pc, #228] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005250: 685b ldr r3, [r3, #4]
8005252: f023 0203 bic.w r2, r3, #3
8005256: 687b ldr r3, [r7, #4]
8005258: 685b ldr r3, [r3, #4]
800525a: 4936 ldr r1, [pc, #216] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
800525c: 4313 orrs r3, r2
800525e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005260: f7fd fd04 bl 8002c6c <HAL_GetTick>
8005264: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8005266: e00a b.n 800527e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8005268: f7fd fd00 bl 8002c6c <HAL_GetTick>
800526c: 4602 mov r2, r0
800526e: 68fb ldr r3, [r7, #12]
8005270: 1ad3 subs r3, r2, r3
8005272: f241 3288 movw r2, #5000 @ 0x1388
8005276: 4293 cmp r3, r2
8005278: d901 bls.n 800527e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800527a: 2303 movs r3, #3
800527c: e053 b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800527e: 4b2d ldr r3, [pc, #180] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005280: 685b ldr r3, [r3, #4]
8005282: f003 020c and.w r2, r3, #12
8005286: 687b ldr r3, [r7, #4]
8005288: 685b ldr r3, [r3, #4]
800528a: 009b lsls r3, r3, #2
800528c: 429a cmp r2, r3
800528e: d1eb bne.n 8005268 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8005290: 4b27 ldr r3, [pc, #156] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
8005292: 681b ldr r3, [r3, #0]
8005294: f003 0307 and.w r3, r3, #7
8005298: 683a ldr r2, [r7, #0]
800529a: 429a cmp r2, r3
800529c: d210 bcs.n 80052c0 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800529e: 4b24 ldr r3, [pc, #144] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
80052a0: 681b ldr r3, [r3, #0]
80052a2: f023 0207 bic.w r2, r3, #7
80052a6: 4922 ldr r1, [pc, #136] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
80052a8: 683b ldr r3, [r7, #0]
80052aa: 4313 orrs r3, r2
80052ac: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80052ae: 4b20 ldr r3, [pc, #128] @ (8005330 <HAL_RCC_ClockConfig+0x1c0>)
80052b0: 681b ldr r3, [r3, #0]
80052b2: f003 0307 and.w r3, r3, #7
80052b6: 683a ldr r2, [r7, #0]
80052b8: 429a cmp r2, r3
80052ba: d001 beq.n 80052c0 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80052bc: 2301 movs r3, #1
80052be: e032 b.n 8005326 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80052c0: 687b ldr r3, [r7, #4]
80052c2: 681b ldr r3, [r3, #0]
80052c4: f003 0304 and.w r3, r3, #4
80052c8: 2b00 cmp r3, #0
80052ca: d008 beq.n 80052de <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80052cc: 4b19 ldr r3, [pc, #100] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80052ce: 685b ldr r3, [r3, #4]
80052d0: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80052d4: 687b ldr r3, [r7, #4]
80052d6: 68db ldr r3, [r3, #12]
80052d8: 4916 ldr r1, [pc, #88] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80052da: 4313 orrs r3, r2
80052dc: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80052de: 687b ldr r3, [r7, #4]
80052e0: 681b ldr r3, [r3, #0]
80052e2: f003 0308 and.w r3, r3, #8
80052e6: 2b00 cmp r3, #0
80052e8: d009 beq.n 80052fe <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
80052ea: 4b12 ldr r3, [pc, #72] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80052ec: 685b ldr r3, [r3, #4]
80052ee: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80052f2: 687b ldr r3, [r7, #4]
80052f4: 691b ldr r3, [r3, #16]
80052f6: 00db lsls r3, r3, #3
80052f8: 490e ldr r1, [pc, #56] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
80052fa: 4313 orrs r3, r2
80052fc: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80052fe: f000 f821 bl 8005344 <HAL_RCC_GetSysClockFreq>
8005302: 4602 mov r2, r0
8005304: 4b0b ldr r3, [pc, #44] @ (8005334 <HAL_RCC_ClockConfig+0x1c4>)
8005306: 685b ldr r3, [r3, #4]
8005308: 091b lsrs r3, r3, #4
800530a: f003 030f and.w r3, r3, #15
800530e: 490a ldr r1, [pc, #40] @ (8005338 <HAL_RCC_ClockConfig+0x1c8>)
8005310: 5ccb ldrb r3, [r1, r3]
8005312: fa22 f303 lsr.w r3, r2, r3
8005316: 4a09 ldr r2, [pc, #36] @ (800533c <HAL_RCC_ClockConfig+0x1cc>)
8005318: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800531a: 4b09 ldr r3, [pc, #36] @ (8005340 <HAL_RCC_ClockConfig+0x1d0>)
800531c: 681b ldr r3, [r3, #0]
800531e: 4618 mov r0, r3
8005320: f7fd fc62 bl 8002be8 <HAL_InitTick>
return HAL_OK;
8005324: 2300 movs r3, #0
}
8005326: 4618 mov r0, r3
8005328: 3710 adds r7, #16
800532a: 46bd mov sp, r7
800532c: bd80 pop {r7, pc}
800532e: bf00 nop
8005330: 40022000 .word 0x40022000
8005334: 40021000 .word 0x40021000
8005338: 08006468 .word 0x08006468
800533c: 20000018 .word 0x20000018
8005340: 2000001c .word 0x2000001c
08005344 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8005344: b480 push {r7}
8005346: b087 sub sp, #28
8005348: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800534a: 2300 movs r3, #0
800534c: 60fb str r3, [r7, #12]
800534e: 2300 movs r3, #0
8005350: 60bb str r3, [r7, #8]
8005352: 2300 movs r3, #0
8005354: 617b str r3, [r7, #20]
8005356: 2300 movs r3, #0
8005358: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
800535a: 2300 movs r3, #0
800535c: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
800535e: 4b1e ldr r3, [pc, #120] @ (80053d8 <HAL_RCC_GetSysClockFreq+0x94>)
8005360: 685b ldr r3, [r3, #4]
8005362: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8005364: 68fb ldr r3, [r7, #12]
8005366: f003 030c and.w r3, r3, #12
800536a: 2b04 cmp r3, #4
800536c: d002 beq.n 8005374 <HAL_RCC_GetSysClockFreq+0x30>
800536e: 2b08 cmp r3, #8
8005370: d003 beq.n 800537a <HAL_RCC_GetSysClockFreq+0x36>
8005372: e027 b.n 80053c4 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8005374: 4b19 ldr r3, [pc, #100] @ (80053dc <HAL_RCC_GetSysClockFreq+0x98>)
8005376: 613b str r3, [r7, #16]
break;
8005378: e027 b.n 80053ca <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
800537a: 68fb ldr r3, [r7, #12]
800537c: 0c9b lsrs r3, r3, #18
800537e: f003 030f and.w r3, r3, #15
8005382: 4a17 ldr r2, [pc, #92] @ (80053e0 <HAL_RCC_GetSysClockFreq+0x9c>)
8005384: 5cd3 ldrb r3, [r2, r3]
8005386: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8005388: 68fb ldr r3, [r7, #12]
800538a: f403 3380 and.w r3, r3, #65536 @ 0x10000
800538e: 2b00 cmp r3, #0
8005390: d010 beq.n 80053b4 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8005392: 4b11 ldr r3, [pc, #68] @ (80053d8 <HAL_RCC_GetSysClockFreq+0x94>)
8005394: 685b ldr r3, [r3, #4]
8005396: 0c5b lsrs r3, r3, #17
8005398: f003 0301 and.w r3, r3, #1
800539c: 4a11 ldr r2, [pc, #68] @ (80053e4 <HAL_RCC_GetSysClockFreq+0xa0>)
800539e: 5cd3 ldrb r3, [r2, r3]
80053a0: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80053a2: 687b ldr r3, [r7, #4]
80053a4: 4a0d ldr r2, [pc, #52] @ (80053dc <HAL_RCC_GetSysClockFreq+0x98>)
80053a6: fb03 f202 mul.w r2, r3, r2
80053aa: 68bb ldr r3, [r7, #8]
80053ac: fbb2 f3f3 udiv r3, r2, r3
80053b0: 617b str r3, [r7, #20]
80053b2: e004 b.n 80053be <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
80053b4: 687b ldr r3, [r7, #4]
80053b6: 4a0c ldr r2, [pc, #48] @ (80053e8 <HAL_RCC_GetSysClockFreq+0xa4>)
80053b8: fb02 f303 mul.w r3, r2, r3
80053bc: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
80053be: 697b ldr r3, [r7, #20]
80053c0: 613b str r3, [r7, #16]
break;
80053c2: e002 b.n 80053ca <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80053c4: 4b09 ldr r3, [pc, #36] @ (80053ec <HAL_RCC_GetSysClockFreq+0xa8>)
80053c6: 613b str r3, [r7, #16]
break;
80053c8: bf00 nop
}
}
return sysclockfreq;
80053ca: 693b ldr r3, [r7, #16]
}
80053cc: 4618 mov r0, r3
80053ce: 371c adds r7, #28
80053d0: 46bd mov sp, r7
80053d2: bc80 pop {r7}
80053d4: 4770 bx lr
80053d6: bf00 nop
80053d8: 40021000 .word 0x40021000
80053dc: 00b71b00 .word 0x00b71b00
80053e0: 08006480 .word 0x08006480
80053e4: 08006490 .word 0x08006490
80053e8: 003d0900 .word 0x003d0900
80053ec: 007a1200 .word 0x007a1200
080053f0 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80053f0: b480 push {r7}
80053f2: af00 add r7, sp, #0
return SystemCoreClock;
80053f4: 4b02 ldr r3, [pc, #8] @ (8005400 <HAL_RCC_GetHCLKFreq+0x10>)
80053f6: 681b ldr r3, [r3, #0]
}
80053f8: 4618 mov r0, r3
80053fa: 46bd mov sp, r7
80053fc: bc80 pop {r7}
80053fe: 4770 bx lr
8005400: 20000018 .word 0x20000018
08005404 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8005404: b580 push {r7, lr}
8005406: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8005408: f7ff fff2 bl 80053f0 <HAL_RCC_GetHCLKFreq>
800540c: 4602 mov r2, r0
800540e: 4b05 ldr r3, [pc, #20] @ (8005424 <HAL_RCC_GetPCLK1Freq+0x20>)
8005410: 685b ldr r3, [r3, #4]
8005412: 0a1b lsrs r3, r3, #8
8005414: f003 0307 and.w r3, r3, #7
8005418: 4903 ldr r1, [pc, #12] @ (8005428 <HAL_RCC_GetPCLK1Freq+0x24>)
800541a: 5ccb ldrb r3, [r1, r3]
800541c: fa22 f303 lsr.w r3, r2, r3
}
8005420: 4618 mov r0, r3
8005422: bd80 pop {r7, pc}
8005424: 40021000 .word 0x40021000
8005428: 08006478 .word 0x08006478
0800542c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
800542c: b580 push {r7, lr}
800542e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8005430: f7ff ffde bl 80053f0 <HAL_RCC_GetHCLKFreq>
8005434: 4602 mov r2, r0
8005436: 4b05 ldr r3, [pc, #20] @ (800544c <HAL_RCC_GetPCLK2Freq+0x20>)
8005438: 685b ldr r3, [r3, #4]
800543a: 0adb lsrs r3, r3, #11
800543c: f003 0307 and.w r3, r3, #7
8005440: 4903 ldr r1, [pc, #12] @ (8005450 <HAL_RCC_GetPCLK2Freq+0x24>)
8005442: 5ccb ldrb r3, [r1, r3]
8005444: fa22 f303 lsr.w r3, r2, r3
}
8005448: 4618 mov r0, r3
800544a: bd80 pop {r7, pc}
800544c: 40021000 .word 0x40021000
8005450: 08006478 .word 0x08006478
08005454 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8005454: b480 push {r7}
8005456: b085 sub sp, #20
8005458: af00 add r7, sp, #0
800545a: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
800545c: 4b0a ldr r3, [pc, #40] @ (8005488 <RCC_Delay+0x34>)
800545e: 681b ldr r3, [r3, #0]
8005460: 4a0a ldr r2, [pc, #40] @ (800548c <RCC_Delay+0x38>)
8005462: fba2 2303 umull r2, r3, r2, r3
8005466: 0a5b lsrs r3, r3, #9
8005468: 687a ldr r2, [r7, #4]
800546a: fb02 f303 mul.w r3, r2, r3
800546e: 60fb str r3, [r7, #12]
do
{
__NOP();
8005470: bf00 nop
}
while (Delay --);
8005472: 68fb ldr r3, [r7, #12]
8005474: 1e5a subs r2, r3, #1
8005476: 60fa str r2, [r7, #12]
8005478: 2b00 cmp r3, #0
800547a: d1f9 bne.n 8005470 <RCC_Delay+0x1c>
}
800547c: bf00 nop
800547e: bf00 nop
8005480: 3714 adds r7, #20
8005482: 46bd mov sp, r7
8005484: bc80 pop {r7}
8005486: 4770 bx lr
8005488: 20000018 .word 0x20000018
800548c: 10624dd3 .word 0x10624dd3
08005490 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8005490: b580 push {r7, lr}
8005492: b086 sub sp, #24
8005494: af00 add r7, sp, #0
8005496: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8005498: 2300 movs r3, #0
800549a: 613b str r3, [r7, #16]
800549c: 2300 movs r3, #0
800549e: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
80054a0: 687b ldr r3, [r7, #4]
80054a2: 681b ldr r3, [r3, #0]
80054a4: f003 0301 and.w r3, r3, #1
80054a8: 2b00 cmp r3, #0
80054aa: d07d beq.n 80055a8 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
80054ac: 2300 movs r3, #0
80054ae: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80054b0: 4b4f ldr r3, [pc, #316] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054b2: 69db ldr r3, [r3, #28]
80054b4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80054b8: 2b00 cmp r3, #0
80054ba: d10d bne.n 80054d8 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
80054bc: 4b4c ldr r3, [pc, #304] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054be: 69db ldr r3, [r3, #28]
80054c0: 4a4b ldr r2, [pc, #300] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054c2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80054c6: 61d3 str r3, [r2, #28]
80054c8: 4b49 ldr r3, [pc, #292] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80054ca: 69db ldr r3, [r3, #28]
80054cc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80054d0: 60bb str r3, [r7, #8]
80054d2: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80054d4: 2301 movs r3, #1
80054d6: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054d8: 4b46 ldr r3, [pc, #280] @ (80055f4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054da: 681b ldr r3, [r3, #0]
80054dc: f403 7380 and.w r3, r3, #256 @ 0x100
80054e0: 2b00 cmp r3, #0
80054e2: d118 bne.n 8005516 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80054e4: 4b43 ldr r3, [pc, #268] @ (80055f4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054e6: 681b ldr r3, [r3, #0]
80054e8: 4a42 ldr r2, [pc, #264] @ (80055f4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80054ea: f443 7380 orr.w r3, r3, #256 @ 0x100
80054ee: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80054f0: f7fd fbbc bl 8002c6c <HAL_GetTick>
80054f4: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054f6: e008 b.n 800550a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80054f8: f7fd fbb8 bl 8002c6c <HAL_GetTick>
80054fc: 4602 mov r2, r0
80054fe: 693b ldr r3, [r7, #16]
8005500: 1ad3 subs r3, r2, r3
8005502: 2b64 cmp r3, #100 @ 0x64
8005504: d901 bls.n 800550a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8005506: 2303 movs r3, #3
8005508: e06d b.n 80055e6 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800550a: 4b3a ldr r3, [pc, #232] @ (80055f4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
800550c: 681b ldr r3, [r3, #0]
800550e: f403 7380 and.w r3, r3, #256 @ 0x100
8005512: 2b00 cmp r3, #0
8005514: d0f0 beq.n 80054f8 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8005516: 4b36 ldr r3, [pc, #216] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005518: 6a1b ldr r3, [r3, #32]
800551a: f403 7340 and.w r3, r3, #768 @ 0x300
800551e: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8005520: 68fb ldr r3, [r7, #12]
8005522: 2b00 cmp r3, #0
8005524: d02e beq.n 8005584 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8005526: 687b ldr r3, [r7, #4]
8005528: 685b ldr r3, [r3, #4]
800552a: f403 7340 and.w r3, r3, #768 @ 0x300
800552e: 68fa ldr r2, [r7, #12]
8005530: 429a cmp r2, r3
8005532: d027 beq.n 8005584 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8005534: 4b2e ldr r3, [pc, #184] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005536: 6a1b ldr r3, [r3, #32]
8005538: f423 7340 bic.w r3, r3, #768 @ 0x300
800553c: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800553e: 4b2e ldr r3, [pc, #184] @ (80055f8 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005540: 2201 movs r2, #1
8005542: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8005544: 4b2c ldr r3, [pc, #176] @ (80055f8 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005546: 2200 movs r2, #0
8005548: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
800554a: 4a29 ldr r2, [pc, #164] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800554c: 68fb ldr r3, [r7, #12]
800554e: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8005550: 68fb ldr r3, [r7, #12]
8005552: f003 0301 and.w r3, r3, #1
8005556: 2b00 cmp r3, #0
8005558: d014 beq.n 8005584 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800555a: f7fd fb87 bl 8002c6c <HAL_GetTick>
800555e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005560: e00a b.n 8005578 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005562: f7fd fb83 bl 8002c6c <HAL_GetTick>
8005566: 4602 mov r2, r0
8005568: 693b ldr r3, [r7, #16]
800556a: 1ad3 subs r3, r2, r3
800556c: f241 3288 movw r2, #5000 @ 0x1388
8005570: 4293 cmp r3, r2
8005572: d901 bls.n 8005578 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8005574: 2303 movs r3, #3
8005576: e036 b.n 80055e6 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005578: 4b1d ldr r3, [pc, #116] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800557a: 6a1b ldr r3, [r3, #32]
800557c: f003 0302 and.w r3, r3, #2
8005580: 2b00 cmp r3, #0
8005582: d0ee beq.n 8005562 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005584: 4b1a ldr r3, [pc, #104] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005586: 6a1b ldr r3, [r3, #32]
8005588: f423 7240 bic.w r2, r3, #768 @ 0x300
800558c: 687b ldr r3, [r7, #4]
800558e: 685b ldr r3, [r3, #4]
8005590: 4917 ldr r1, [pc, #92] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005592: 4313 orrs r3, r2
8005594: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005596: 7dfb ldrb r3, [r7, #23]
8005598: 2b01 cmp r3, #1
800559a: d105 bne.n 80055a8 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
800559c: 4b14 ldr r3, [pc, #80] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800559e: 69db ldr r3, [r3, #28]
80055a0: 4a13 ldr r2, [pc, #76] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055a2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80055a6: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80055a8: 687b ldr r3, [r7, #4]
80055aa: 681b ldr r3, [r3, #0]
80055ac: f003 0302 and.w r3, r3, #2
80055b0: 2b00 cmp r3, #0
80055b2: d008 beq.n 80055c6 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80055b4: 4b0e ldr r3, [pc, #56] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055b6: 685b ldr r3, [r3, #4]
80055b8: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80055bc: 687b ldr r3, [r7, #4]
80055be: 689b ldr r3, [r3, #8]
80055c0: 490b ldr r1, [pc, #44] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055c2: 4313 orrs r3, r2
80055c4: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80055c6: 687b ldr r3, [r7, #4]
80055c8: 681b ldr r3, [r3, #0]
80055ca: f003 0310 and.w r3, r3, #16
80055ce: 2b00 cmp r3, #0
80055d0: d008 beq.n 80055e4 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80055d2: 4b07 ldr r3, [pc, #28] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055d4: 685b ldr r3, [r3, #4]
80055d6: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
80055da: 687b ldr r3, [r7, #4]
80055dc: 68db ldr r3, [r3, #12]
80055de: 4904 ldr r1, [pc, #16] @ (80055f0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80055e0: 4313 orrs r3, r2
80055e2: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
80055e4: 2300 movs r3, #0
}
80055e6: 4618 mov r0, r3
80055e8: 3718 adds r7, #24
80055ea: 46bd mov sp, r7
80055ec: bd80 pop {r7, pc}
80055ee: bf00 nop
80055f0: 40021000 .word 0x40021000
80055f4: 40007000 .word 0x40007000
80055f8: 42420440 .word 0x42420440
080055fc <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80055fc: b580 push {r7, lr}
80055fe: b082 sub sp, #8
8005600: af00 add r7, sp, #0
8005602: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005604: 687b ldr r3, [r7, #4]
8005606: 2b00 cmp r3, #0
8005608: d101 bne.n 800560e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800560a: 2301 movs r3, #1
800560c: e042 b.n 8005694 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
800560e: 687b ldr r3, [r7, #4]
8005610: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005614: b2db uxtb r3, r3
8005616: 2b00 cmp r3, #0
8005618: d106 bne.n 8005628 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800561a: 687b ldr r3, [r7, #4]
800561c: 2200 movs r2, #0
800561e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005622: 6878 ldr r0, [r7, #4]
8005624: f7fd fa50 bl 8002ac8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8005628: 687b ldr r3, [r7, #4]
800562a: 2224 movs r2, #36 @ 0x24
800562c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8005630: 687b ldr r3, [r7, #4]
8005632: 681b ldr r3, [r3, #0]
8005634: 68da ldr r2, [r3, #12]
8005636: 687b ldr r3, [r7, #4]
8005638: 681b ldr r3, [r3, #0]
800563a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800563e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8005640: 6878 ldr r0, [r7, #4]
8005642: f000 fd63 bl 800610c <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005646: 687b ldr r3, [r7, #4]
8005648: 681b ldr r3, [r3, #0]
800564a: 691a ldr r2, [r3, #16]
800564c: 687b ldr r3, [r7, #4]
800564e: 681b ldr r3, [r3, #0]
8005650: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005654: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005656: 687b ldr r3, [r7, #4]
8005658: 681b ldr r3, [r3, #0]
800565a: 695a ldr r2, [r3, #20]
800565c: 687b ldr r3, [r7, #4]
800565e: 681b ldr r3, [r3, #0]
8005660: f022 022a bic.w r2, r2, #42 @ 0x2a
8005664: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8005666: 687b ldr r3, [r7, #4]
8005668: 681b ldr r3, [r3, #0]
800566a: 68da ldr r2, [r3, #12]
800566c: 687b ldr r3, [r7, #4]
800566e: 681b ldr r3, [r3, #0]
8005670: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8005674: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005676: 687b ldr r3, [r7, #4]
8005678: 2200 movs r2, #0
800567a: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
800567c: 687b ldr r3, [r7, #4]
800567e: 2220 movs r2, #32
8005680: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8005684: 687b ldr r3, [r7, #4]
8005686: 2220 movs r2, #32
8005688: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
800568c: 687b ldr r3, [r7, #4]
800568e: 2200 movs r2, #0
8005690: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8005692: 2300 movs r3, #0
}
8005694: 4618 mov r0, r3
8005696: 3708 adds r7, #8
8005698: 46bd mov sp, r7
800569a: bd80 pop {r7, pc}
0800569c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800569c: b580 push {r7, lr}
800569e: b08a sub sp, #40 @ 0x28
80056a0: af02 add r7, sp, #8
80056a2: 60f8 str r0, [r7, #12]
80056a4: 60b9 str r1, [r7, #8]
80056a6: 603b str r3, [r7, #0]
80056a8: 4613 mov r3, r2
80056aa: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
80056ac: 2300 movs r3, #0
80056ae: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
80056b0: 68fb ldr r3, [r7, #12]
80056b2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80056b6: b2db uxtb r3, r3
80056b8: 2b20 cmp r3, #32
80056ba: d175 bne.n 80057a8 <HAL_UART_Transmit+0x10c>
{
if ((pData == NULL) || (Size == 0U))
80056bc: 68bb ldr r3, [r7, #8]
80056be: 2b00 cmp r3, #0
80056c0: d002 beq.n 80056c8 <HAL_UART_Transmit+0x2c>
80056c2: 88fb ldrh r3, [r7, #6]
80056c4: 2b00 cmp r3, #0
80056c6: d101 bne.n 80056cc <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
80056c8: 2301 movs r3, #1
80056ca: e06e b.n 80057aa <HAL_UART_Transmit+0x10e>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
80056cc: 68fb ldr r3, [r7, #12]
80056ce: 2200 movs r2, #0
80056d0: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_BUSY_TX;
80056d2: 68fb ldr r3, [r7, #12]
80056d4: 2221 movs r2, #33 @ 0x21
80056d6: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80056da: f7fd fac7 bl 8002c6c <HAL_GetTick>
80056de: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80056e0: 68fb ldr r3, [r7, #12]
80056e2: 88fa ldrh r2, [r7, #6]
80056e4: 849a strh r2, [r3, #36] @ 0x24
huart->TxXferCount = Size;
80056e6: 68fb ldr r3, [r7, #12]
80056e8: 88fa ldrh r2, [r7, #6]
80056ea: 84da strh r2, [r3, #38] @ 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80056ec: 68fb ldr r3, [r7, #12]
80056ee: 689b ldr r3, [r3, #8]
80056f0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80056f4: d108 bne.n 8005708 <HAL_UART_Transmit+0x6c>
80056f6: 68fb ldr r3, [r7, #12]
80056f8: 691b ldr r3, [r3, #16]
80056fa: 2b00 cmp r3, #0
80056fc: d104 bne.n 8005708 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
80056fe: 2300 movs r3, #0
8005700: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8005702: 68bb ldr r3, [r7, #8]
8005704: 61bb str r3, [r7, #24]
8005706: e003 b.n 8005710 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8005708: 68bb ldr r3, [r7, #8]
800570a: 61fb str r3, [r7, #28]
pdata16bits = NULL;
800570c: 2300 movs r3, #0
800570e: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8005710: e02e b.n 8005770 <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8005712: 683b ldr r3, [r7, #0]
8005714: 9300 str r3, [sp, #0]
8005716: 697b ldr r3, [r7, #20]
8005718: 2200 movs r2, #0
800571a: 2180 movs r1, #128 @ 0x80
800571c: 68f8 ldr r0, [r7, #12]
800571e: f000 fb01 bl 8005d24 <UART_WaitOnFlagUntilTimeout>
8005722: 4603 mov r3, r0
8005724: 2b00 cmp r3, #0
8005726: d005 beq.n 8005734 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8005728: 68fb ldr r3, [r7, #12]
800572a: 2220 movs r2, #32
800572c: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005730: 2303 movs r3, #3
8005732: e03a b.n 80057aa <HAL_UART_Transmit+0x10e>
}
if (pdata8bits == NULL)
8005734: 69fb ldr r3, [r7, #28]
8005736: 2b00 cmp r3, #0
8005738: d10b bne.n 8005752 <HAL_UART_Transmit+0xb6>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
800573a: 69bb ldr r3, [r7, #24]
800573c: 881b ldrh r3, [r3, #0]
800573e: 461a mov r2, r3
8005740: 68fb ldr r3, [r7, #12]
8005742: 681b ldr r3, [r3, #0]
8005744: f3c2 0208 ubfx r2, r2, #0, #9
8005748: 605a str r2, [r3, #4]
pdata16bits++;
800574a: 69bb ldr r3, [r7, #24]
800574c: 3302 adds r3, #2
800574e: 61bb str r3, [r7, #24]
8005750: e007 b.n 8005762 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8005752: 69fb ldr r3, [r7, #28]
8005754: 781a ldrb r2, [r3, #0]
8005756: 68fb ldr r3, [r7, #12]
8005758: 681b ldr r3, [r3, #0]
800575a: 605a str r2, [r3, #4]
pdata8bits++;
800575c: 69fb ldr r3, [r7, #28]
800575e: 3301 adds r3, #1
8005760: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8005762: 68fb ldr r3, [r7, #12]
8005764: 8cdb ldrh r3, [r3, #38] @ 0x26
8005766: b29b uxth r3, r3
8005768: 3b01 subs r3, #1
800576a: b29a uxth r2, r3
800576c: 68fb ldr r3, [r7, #12]
800576e: 84da strh r2, [r3, #38] @ 0x26
while (huart->TxXferCount > 0U)
8005770: 68fb ldr r3, [r7, #12]
8005772: 8cdb ldrh r3, [r3, #38] @ 0x26
8005774: b29b uxth r3, r3
8005776: 2b00 cmp r3, #0
8005778: d1cb bne.n 8005712 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
800577a: 683b ldr r3, [r7, #0]
800577c: 9300 str r3, [sp, #0]
800577e: 697b ldr r3, [r7, #20]
8005780: 2200 movs r2, #0
8005782: 2140 movs r1, #64 @ 0x40
8005784: 68f8 ldr r0, [r7, #12]
8005786: f000 facd bl 8005d24 <UART_WaitOnFlagUntilTimeout>
800578a: 4603 mov r3, r0
800578c: 2b00 cmp r3, #0
800578e: d005 beq.n 800579c <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8005790: 68fb ldr r3, [r7, #12]
8005792: 2220 movs r2, #32
8005794: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005798: 2303 movs r3, #3
800579a: e006 b.n 80057aa <HAL_UART_Transmit+0x10e>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800579c: 68fb ldr r3, [r7, #12]
800579e: 2220 movs r2, #32
80057a0: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_OK;
80057a4: 2300 movs r3, #0
80057a6: e000 b.n 80057aa <HAL_UART_Transmit+0x10e>
}
else
{
return HAL_BUSY;
80057a8: 2302 movs r3, #2
}
}
80057aa: 4618 mov r0, r3
80057ac: 3720 adds r7, #32
80057ae: 46bd mov sp, r7
80057b0: bd80 pop {r7, pc}
...
080057b4 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
80057b4: b580 push {r7, lr}
80057b6: b0ba sub sp, #232 @ 0xe8
80057b8: af00 add r7, sp, #0
80057ba: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
80057bc: 687b ldr r3, [r7, #4]
80057be: 681b ldr r3, [r3, #0]
80057c0: 681b ldr r3, [r3, #0]
80057c2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80057c6: 687b ldr r3, [r7, #4]
80057c8: 681b ldr r3, [r3, #0]
80057ca: 68db ldr r3, [r3, #12]
80057cc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80057d0: 687b ldr r3, [r7, #4]
80057d2: 681b ldr r3, [r3, #0]
80057d4: 695b ldr r3, [r3, #20]
80057d6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags = 0x00U;
80057da: 2300 movs r3, #0
80057dc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
uint32_t dmarequest = 0x00U;
80057e0: 2300 movs r3, #0
80057e2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
80057e6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80057ea: f003 030f and.w r3, r3, #15
80057ee: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == RESET)
80057f2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
80057f6: 2b00 cmp r3, #0
80057f8: d10f bne.n 800581a <HAL_UART_IRQHandler+0x66>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
80057fa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80057fe: f003 0320 and.w r3, r3, #32
8005802: 2b00 cmp r3, #0
8005804: d009 beq.n 800581a <HAL_UART_IRQHandler+0x66>
8005806: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800580a: f003 0320 and.w r3, r3, #32
800580e: 2b00 cmp r3, #0
8005810: d003 beq.n 800581a <HAL_UART_IRQHandler+0x66>
{
UART_Receive_IT(huart);
8005812: 6878 ldr r0, [r7, #4]
8005814: f000 fbbc bl 8005f90 <UART_Receive_IT>
return;
8005818: e25b b.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
800581a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
800581e: 2b00 cmp r3, #0
8005820: f000 80de beq.w 80059e0 <HAL_UART_IRQHandler+0x22c>
8005824: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005828: f003 0301 and.w r3, r3, #1
800582c: 2b00 cmp r3, #0
800582e: d106 bne.n 800583e <HAL_UART_IRQHandler+0x8a>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8005830: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005834: f403 7390 and.w r3, r3, #288 @ 0x120
8005838: 2b00 cmp r3, #0
800583a: f000 80d1 beq.w 80059e0 <HAL_UART_IRQHandler+0x22c>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
800583e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005842: f003 0301 and.w r3, r3, #1
8005846: 2b00 cmp r3, #0
8005848: d00b beq.n 8005862 <HAL_UART_IRQHandler+0xae>
800584a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800584e: f403 7380 and.w r3, r3, #256 @ 0x100
8005852: 2b00 cmp r3, #0
8005854: d005 beq.n 8005862 <HAL_UART_IRQHandler+0xae>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
8005856: 687b ldr r3, [r7, #4]
8005858: 6c5b ldr r3, [r3, #68] @ 0x44
800585a: f043 0201 orr.w r2, r3, #1
800585e: 687b ldr r3, [r7, #4]
8005860: 645a str r2, [r3, #68] @ 0x44
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005862: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005866: f003 0304 and.w r3, r3, #4
800586a: 2b00 cmp r3, #0
800586c: d00b beq.n 8005886 <HAL_UART_IRQHandler+0xd2>
800586e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005872: f003 0301 and.w r3, r3, #1
8005876: 2b00 cmp r3, #0
8005878: d005 beq.n 8005886 <HAL_UART_IRQHandler+0xd2>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
800587a: 687b ldr r3, [r7, #4]
800587c: 6c5b ldr r3, [r3, #68] @ 0x44
800587e: f043 0202 orr.w r2, r3, #2
8005882: 687b ldr r3, [r7, #4]
8005884: 645a str r2, [r3, #68] @ 0x44
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005886: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800588a: f003 0302 and.w r3, r3, #2
800588e: 2b00 cmp r3, #0
8005890: d00b beq.n 80058aa <HAL_UART_IRQHandler+0xf6>
8005892: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005896: f003 0301 and.w r3, r3, #1
800589a: 2b00 cmp r3, #0
800589c: d005 beq.n 80058aa <HAL_UART_IRQHandler+0xf6>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
800589e: 687b ldr r3, [r7, #4]
80058a0: 6c5b ldr r3, [r3, #68] @ 0x44
80058a2: f043 0204 orr.w r2, r3, #4
80058a6: 687b ldr r3, [r7, #4]
80058a8: 645a str r2, [r3, #68] @ 0x44
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
80058aa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80058ae: f003 0308 and.w r3, r3, #8
80058b2: 2b00 cmp r3, #0
80058b4: d011 beq.n 80058da <HAL_UART_IRQHandler+0x126>
80058b6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80058ba: f003 0320 and.w r3, r3, #32
80058be: 2b00 cmp r3, #0
80058c0: d105 bne.n 80058ce <HAL_UART_IRQHandler+0x11a>
|| ((cr3its & USART_CR3_EIE) != RESET)))
80058c2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80058c6: f003 0301 and.w r3, r3, #1
80058ca: 2b00 cmp r3, #0
80058cc: d005 beq.n 80058da <HAL_UART_IRQHandler+0x126>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
80058ce: 687b ldr r3, [r7, #4]
80058d0: 6c5b ldr r3, [r3, #68] @ 0x44
80058d2: f043 0208 orr.w r2, r3, #8
80058d6: 687b ldr r3, [r7, #4]
80058d8: 645a str r2, [r3, #68] @ 0x44
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
80058da: 687b ldr r3, [r7, #4]
80058dc: 6c5b ldr r3, [r3, #68] @ 0x44
80058de: 2b00 cmp r3, #0
80058e0: f000 81f2 beq.w 8005cc8 <HAL_UART_IRQHandler+0x514>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
80058e4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80058e8: f003 0320 and.w r3, r3, #32
80058ec: 2b00 cmp r3, #0
80058ee: d008 beq.n 8005902 <HAL_UART_IRQHandler+0x14e>
80058f0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80058f4: f003 0320 and.w r3, r3, #32
80058f8: 2b00 cmp r3, #0
80058fa: d002 beq.n 8005902 <HAL_UART_IRQHandler+0x14e>
{
UART_Receive_IT(huart);
80058fc: 6878 ldr r0, [r7, #4]
80058fe: f000 fb47 bl 8005f90 <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
8005902: 687b ldr r3, [r7, #4]
8005904: 681b ldr r3, [r3, #0]
8005906: 695b ldr r3, [r3, #20]
8005908: f003 0340 and.w r3, r3, #64 @ 0x40
800590c: 2b00 cmp r3, #0
800590e: bf14 ite ne
8005910: 2301 movne r3, #1
8005912: 2300 moveq r3, #0
8005914: b2db uxtb r3, r3
8005916: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
800591a: 687b ldr r3, [r7, #4]
800591c: 6c5b ldr r3, [r3, #68] @ 0x44
800591e: f003 0308 and.w r3, r3, #8
8005922: 2b00 cmp r3, #0
8005924: d103 bne.n 800592e <HAL_UART_IRQHandler+0x17a>
8005926: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
800592a: 2b00 cmp r3, #0
800592c: d04f beq.n 80059ce <HAL_UART_IRQHandler+0x21a>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
800592e: 6878 ldr r0, [r7, #4]
8005930: f000 fa51 bl 8005dd6 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005934: 687b ldr r3, [r7, #4]
8005936: 681b ldr r3, [r3, #0]
8005938: 695b ldr r3, [r3, #20]
800593a: f003 0340 and.w r3, r3, #64 @ 0x40
800593e: 2b00 cmp r3, #0
8005940: d041 beq.n 80059c6 <HAL_UART_IRQHandler+0x212>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005942: 687b ldr r3, [r7, #4]
8005944: 681b ldr r3, [r3, #0]
8005946: 3314 adds r3, #20
8005948: f8c7 309c str.w r3, [r7, #156] @ 0x9c
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800594c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8005950: e853 3f00 ldrex r3, [r3]
8005954: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8005958: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800595c: f023 0340 bic.w r3, r3, #64 @ 0x40
8005960: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8005964: 687b ldr r3, [r7, #4]
8005966: 681b ldr r3, [r3, #0]
8005968: 3314 adds r3, #20
800596a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
800596e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
8005972: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005976: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
800597a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
800597e: e841 2300 strex r3, r2, [r1]
8005982: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8005986: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800598a: 2b00 cmp r3, #0
800598c: d1d9 bne.n 8005942 <HAL_UART_IRQHandler+0x18e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
800598e: 687b ldr r3, [r7, #4]
8005990: 6bdb ldr r3, [r3, #60] @ 0x3c
8005992: 2b00 cmp r3, #0
8005994: d013 beq.n 80059be <HAL_UART_IRQHandler+0x20a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8005996: 687b ldr r3, [r7, #4]
8005998: 6bdb ldr r3, [r3, #60] @ 0x3c
800599a: 4a7e ldr r2, [pc, #504] @ (8005b94 <HAL_UART_IRQHandler+0x3e0>)
800599c: 635a str r2, [r3, #52] @ 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
800599e: 687b ldr r3, [r7, #4]
80059a0: 6bdb ldr r3, [r3, #60] @ 0x3c
80059a2: 4618 mov r0, r3
80059a4: f7fd fcea bl 800337c <HAL_DMA_Abort_IT>
80059a8: 4603 mov r3, r0
80059aa: 2b00 cmp r3, #0
80059ac: d016 beq.n 80059dc <HAL_UART_IRQHandler+0x228>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80059ae: 687b ldr r3, [r7, #4]
80059b0: 6bdb ldr r3, [r3, #60] @ 0x3c
80059b2: 6b5b ldr r3, [r3, #52] @ 0x34
80059b4: 687a ldr r2, [r7, #4]
80059b6: 6bd2 ldr r2, [r2, #60] @ 0x3c
80059b8: 4610 mov r0, r2
80059ba: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80059bc: e00e b.n 80059dc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80059be: 6878 ldr r0, [r7, #4]
80059c0: f000 f99c bl 8005cfc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80059c4: e00a b.n 80059dc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80059c6: 6878 ldr r0, [r7, #4]
80059c8: f000 f998 bl 8005cfc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80059cc: e006 b.n 80059dc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80059ce: 6878 ldr r0, [r7, #4]
80059d0: f000 f994 bl 8005cfc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80059d4: 687b ldr r3, [r7, #4]
80059d6: 2200 movs r2, #0
80059d8: 645a str r2, [r3, #68] @ 0x44
}
}
return;
80059da: e175 b.n 8005cc8 <HAL_UART_IRQHandler+0x514>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80059dc: bf00 nop
return;
80059de: e173 b.n 8005cc8 <HAL_UART_IRQHandler+0x514>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80059e0: 687b ldr r3, [r7, #4]
80059e2: 6b1b ldr r3, [r3, #48] @ 0x30
80059e4: 2b01 cmp r3, #1
80059e6: f040 814f bne.w 8005c88 <HAL_UART_IRQHandler+0x4d4>
&& ((isrflags & USART_SR_IDLE) != 0U)
80059ea: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80059ee: f003 0310 and.w r3, r3, #16
80059f2: 2b00 cmp r3, #0
80059f4: f000 8148 beq.w 8005c88 <HAL_UART_IRQHandler+0x4d4>
&& ((cr1its & USART_SR_IDLE) != 0U))
80059f8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80059fc: f003 0310 and.w r3, r3, #16
8005a00: 2b00 cmp r3, #0
8005a02: f000 8141 beq.w 8005c88 <HAL_UART_IRQHandler+0x4d4>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
8005a06: 2300 movs r3, #0
8005a08: 60bb str r3, [r7, #8]
8005a0a: 687b ldr r3, [r7, #4]
8005a0c: 681b ldr r3, [r3, #0]
8005a0e: 681b ldr r3, [r3, #0]
8005a10: 60bb str r3, [r7, #8]
8005a12: 687b ldr r3, [r7, #4]
8005a14: 681b ldr r3, [r3, #0]
8005a16: 685b ldr r3, [r3, #4]
8005a18: 60bb str r3, [r7, #8]
8005a1a: 68bb ldr r3, [r7, #8]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005a1c: 687b ldr r3, [r7, #4]
8005a1e: 681b ldr r3, [r3, #0]
8005a20: 695b ldr r3, [r3, #20]
8005a22: f003 0340 and.w r3, r3, #64 @ 0x40
8005a26: 2b00 cmp r3, #0
8005a28: f000 80b6 beq.w 8005b98 <HAL_UART_IRQHandler+0x3e4>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8005a2c: 687b ldr r3, [r7, #4]
8005a2e: 6bdb ldr r3, [r3, #60] @ 0x3c
8005a30: 681b ldr r3, [r3, #0]
8005a32: 685b ldr r3, [r3, #4]
8005a34: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
8005a38: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8005a3c: 2b00 cmp r3, #0
8005a3e: f000 8145 beq.w 8005ccc <HAL_UART_IRQHandler+0x518>
&& (nb_remaining_rx_data < huart->RxXferSize))
8005a42: 687b ldr r3, [r7, #4]
8005a44: 8d9b ldrh r3, [r3, #44] @ 0x2c
8005a46: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005a4a: 429a cmp r2, r3
8005a4c: f080 813e bcs.w 8005ccc <HAL_UART_IRQHandler+0x518>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8005a50: 687b ldr r3, [r7, #4]
8005a52: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005a56: 85da strh r2, [r3, #46] @ 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8005a58: 687b ldr r3, [r7, #4]
8005a5a: 6bdb ldr r3, [r3, #60] @ 0x3c
8005a5c: 699b ldr r3, [r3, #24]
8005a5e: 2b20 cmp r3, #32
8005a60: f000 8088 beq.w 8005b74 <HAL_UART_IRQHandler+0x3c0>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8005a64: 687b ldr r3, [r7, #4]
8005a66: 681b ldr r3, [r3, #0]
8005a68: 330c adds r3, #12
8005a6a: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005a6e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8005a72: e853 3f00 ldrex r3, [r3]
8005a76: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8005a7a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8005a7e: f423 7380 bic.w r3, r3, #256 @ 0x100
8005a82: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8005a86: 687b ldr r3, [r7, #4]
8005a88: 681b ldr r3, [r3, #0]
8005a8a: 330c adds r3, #12
8005a8c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
8005a90: f8c7 2094 str.w r2, [r7, #148] @ 0x94
8005a94: f8c7 3090 str.w r3, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005a98: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8005a9c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8005aa0: e841 2300 strex r3, r2, [r1]
8005aa4: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
8005aa8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005aac: 2b00 cmp r3, #0
8005aae: d1d9 bne.n 8005a64 <HAL_UART_IRQHandler+0x2b0>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005ab0: 687b ldr r3, [r7, #4]
8005ab2: 681b ldr r3, [r3, #0]
8005ab4: 3314 adds r3, #20
8005ab6: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005ab8: 6f7b ldr r3, [r7, #116] @ 0x74
8005aba: e853 3f00 ldrex r3, [r3]
8005abe: 673b str r3, [r7, #112] @ 0x70
return(result);
8005ac0: 6f3b ldr r3, [r7, #112] @ 0x70
8005ac2: f023 0301 bic.w r3, r3, #1
8005ac6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8005aca: 687b ldr r3, [r7, #4]
8005acc: 681b ldr r3, [r3, #0]
8005ace: 3314 adds r3, #20
8005ad0: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8005ad4: f8c7 2080 str.w r2, [r7, #128] @ 0x80
8005ad8: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005ada: 6ff9 ldr r1, [r7, #124] @ 0x7c
8005adc: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
8005ae0: e841 2300 strex r3, r2, [r1]
8005ae4: 67bb str r3, [r7, #120] @ 0x78
return(result);
8005ae6: 6fbb ldr r3, [r7, #120] @ 0x78
8005ae8: 2b00 cmp r3, #0
8005aea: d1e1 bne.n 8005ab0 <HAL_UART_IRQHandler+0x2fc>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005aec: 687b ldr r3, [r7, #4]
8005aee: 681b ldr r3, [r3, #0]
8005af0: 3314 adds r3, #20
8005af2: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005af4: 6e3b ldr r3, [r7, #96] @ 0x60
8005af6: e853 3f00 ldrex r3, [r3]
8005afa: 65fb str r3, [r7, #92] @ 0x5c
return(result);
8005afc: 6dfb ldr r3, [r7, #92] @ 0x5c
8005afe: f023 0340 bic.w r3, r3, #64 @ 0x40
8005b02: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8005b06: 687b ldr r3, [r7, #4]
8005b08: 681b ldr r3, [r3, #0]
8005b0a: 3314 adds r3, #20
8005b0c: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
8005b10: 66fa str r2, [r7, #108] @ 0x6c
8005b12: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005b14: 6eb9 ldr r1, [r7, #104] @ 0x68
8005b16: 6efa ldr r2, [r7, #108] @ 0x6c
8005b18: e841 2300 strex r3, r2, [r1]
8005b1c: 667b str r3, [r7, #100] @ 0x64
return(result);
8005b1e: 6e7b ldr r3, [r7, #100] @ 0x64
8005b20: 2b00 cmp r3, #0
8005b22: d1e3 bne.n 8005aec <HAL_UART_IRQHandler+0x338>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005b24: 687b ldr r3, [r7, #4]
8005b26: 2220 movs r2, #32
8005b28: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005b2c: 687b ldr r3, [r7, #4]
8005b2e: 2200 movs r2, #0
8005b30: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005b32: 687b ldr r3, [r7, #4]
8005b34: 681b ldr r3, [r3, #0]
8005b36: 330c adds r3, #12
8005b38: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005b3a: 6cfb ldr r3, [r7, #76] @ 0x4c
8005b3c: e853 3f00 ldrex r3, [r3]
8005b40: 64bb str r3, [r7, #72] @ 0x48
return(result);
8005b42: 6cbb ldr r3, [r7, #72] @ 0x48
8005b44: f023 0310 bic.w r3, r3, #16
8005b48: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8005b4c: 687b ldr r3, [r7, #4]
8005b4e: 681b ldr r3, [r3, #0]
8005b50: 330c adds r3, #12
8005b52: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
8005b56: 65ba str r2, [r7, #88] @ 0x58
8005b58: 657b str r3, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005b5a: 6d79 ldr r1, [r7, #84] @ 0x54
8005b5c: 6dba ldr r2, [r7, #88] @ 0x58
8005b5e: e841 2300 strex r3, r2, [r1]
8005b62: 653b str r3, [r7, #80] @ 0x50
return(result);
8005b64: 6d3b ldr r3, [r7, #80] @ 0x50
8005b66: 2b00 cmp r3, #0
8005b68: d1e3 bne.n 8005b32 <HAL_UART_IRQHandler+0x37e>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8005b6a: 687b ldr r3, [r7, #4]
8005b6c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005b6e: 4618 mov r0, r3
8005b70: f7fd fbc9 bl 8003306 <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005b74: 687b ldr r3, [r7, #4]
8005b76: 2202 movs r2, #2
8005b78: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8005b7a: 687b ldr r3, [r7, #4]
8005b7c: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005b82: b29b uxth r3, r3
8005b84: 1ad3 subs r3, r2, r3
8005b86: b29b uxth r3, r3
8005b88: 4619 mov r1, r3
8005b8a: 6878 ldr r0, [r7, #4]
8005b8c: f000 f8bf bl 8005d0e <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005b90: e09c b.n 8005ccc <HAL_UART_IRQHandler+0x518>
8005b92: bf00 nop
8005b94: 08005e9b .word 0x08005e9b
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8005b98: 687b ldr r3, [r7, #4]
8005b9a: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005ba0: b29b uxth r3, r3
8005ba2: 1ad3 subs r3, r2, r3
8005ba4: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8005ba8: 687b ldr r3, [r7, #4]
8005baa: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005bac: b29b uxth r3, r3
8005bae: 2b00 cmp r3, #0
8005bb0: f000 808e beq.w 8005cd0 <HAL_UART_IRQHandler+0x51c>
&& (nb_rx_data > 0U))
8005bb4: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005bb8: 2b00 cmp r3, #0
8005bba: f000 8089 beq.w 8005cd0 <HAL_UART_IRQHandler+0x51c>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 681b ldr r3, [r3, #0]
8005bc2: 330c adds r3, #12
8005bc4: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005bc6: 6bbb ldr r3, [r7, #56] @ 0x38
8005bc8: e853 3f00 ldrex r3, [r3]
8005bcc: 637b str r3, [r7, #52] @ 0x34
return(result);
8005bce: 6b7b ldr r3, [r7, #52] @ 0x34
8005bd0: f423 7390 bic.w r3, r3, #288 @ 0x120
8005bd4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8005bd8: 687b ldr r3, [r7, #4]
8005bda: 681b ldr r3, [r3, #0]
8005bdc: 330c adds r3, #12
8005bde: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
8005be2: 647a str r2, [r7, #68] @ 0x44
8005be4: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005be6: 6c39 ldr r1, [r7, #64] @ 0x40
8005be8: 6c7a ldr r2, [r7, #68] @ 0x44
8005bea: e841 2300 strex r3, r2, [r1]
8005bee: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8005bf0: 6bfb ldr r3, [r7, #60] @ 0x3c
8005bf2: 2b00 cmp r3, #0
8005bf4: d1e3 bne.n 8005bbe <HAL_UART_IRQHandler+0x40a>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005bf6: 687b ldr r3, [r7, #4]
8005bf8: 681b ldr r3, [r3, #0]
8005bfa: 3314 adds r3, #20
8005bfc: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005bfe: 6a7b ldr r3, [r7, #36] @ 0x24
8005c00: e853 3f00 ldrex r3, [r3]
8005c04: 623b str r3, [r7, #32]
return(result);
8005c06: 6a3b ldr r3, [r7, #32]
8005c08: f023 0301 bic.w r3, r3, #1
8005c0c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8005c10: 687b ldr r3, [r7, #4]
8005c12: 681b ldr r3, [r3, #0]
8005c14: 3314 adds r3, #20
8005c16: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8005c1a: 633a str r2, [r7, #48] @ 0x30
8005c1c: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005c1e: 6af9 ldr r1, [r7, #44] @ 0x2c
8005c20: 6b3a ldr r2, [r7, #48] @ 0x30
8005c22: e841 2300 strex r3, r2, [r1]
8005c26: 62bb str r3, [r7, #40] @ 0x28
return(result);
8005c28: 6abb ldr r3, [r7, #40] @ 0x28
8005c2a: 2b00 cmp r3, #0
8005c2c: d1e3 bne.n 8005bf6 <HAL_UART_IRQHandler+0x442>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005c2e: 687b ldr r3, [r7, #4]
8005c30: 2220 movs r2, #32
8005c32: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005c36: 687b ldr r3, [r7, #4]
8005c38: 2200 movs r2, #0
8005c3a: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005c3c: 687b ldr r3, [r7, #4]
8005c3e: 681b ldr r3, [r3, #0]
8005c40: 330c adds r3, #12
8005c42: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005c44: 693b ldr r3, [r7, #16]
8005c46: e853 3f00 ldrex r3, [r3]
8005c4a: 60fb str r3, [r7, #12]
return(result);
8005c4c: 68fb ldr r3, [r7, #12]
8005c4e: f023 0310 bic.w r3, r3, #16
8005c52: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8005c56: 687b ldr r3, [r7, #4]
8005c58: 681b ldr r3, [r3, #0]
8005c5a: 330c adds r3, #12
8005c5c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
8005c60: 61fa str r2, [r7, #28]
8005c62: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005c64: 69b9 ldr r1, [r7, #24]
8005c66: 69fa ldr r2, [r7, #28]
8005c68: e841 2300 strex r3, r2, [r1]
8005c6c: 617b str r3, [r7, #20]
return(result);
8005c6e: 697b ldr r3, [r7, #20]
8005c70: 2b00 cmp r3, #0
8005c72: d1e3 bne.n 8005c3c <HAL_UART_IRQHandler+0x488>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005c74: 687b ldr r3, [r7, #4]
8005c76: 2202 movs r2, #2
8005c78: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8005c7a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005c7e: 4619 mov r1, r3
8005c80: 6878 ldr r0, [r7, #4]
8005c82: f000 f844 bl 8005d0e <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005c86: e023 b.n 8005cd0 <HAL_UART_IRQHandler+0x51c>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
8005c88: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005c8c: f003 0380 and.w r3, r3, #128 @ 0x80
8005c90: 2b00 cmp r3, #0
8005c92: d009 beq.n 8005ca8 <HAL_UART_IRQHandler+0x4f4>
8005c94: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005c98: f003 0380 and.w r3, r3, #128 @ 0x80
8005c9c: 2b00 cmp r3, #0
8005c9e: d003 beq.n 8005ca8 <HAL_UART_IRQHandler+0x4f4>
{
UART_Transmit_IT(huart);
8005ca0: 6878 ldr r0, [r7, #4]
8005ca2: f000 f90e bl 8005ec2 <UART_Transmit_IT>
return;
8005ca6: e014 b.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
8005ca8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005cac: f003 0340 and.w r3, r3, #64 @ 0x40
8005cb0: 2b00 cmp r3, #0
8005cb2: d00e beq.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
8005cb4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005cb8: f003 0340 and.w r3, r3, #64 @ 0x40
8005cbc: 2b00 cmp r3, #0
8005cbe: d008 beq.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
{
UART_EndTransmit_IT(huart);
8005cc0: 6878 ldr r0, [r7, #4]
8005cc2: f000 f94d bl 8005f60 <UART_EndTransmit_IT>
return;
8005cc6: e004 b.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
return;
8005cc8: bf00 nop
8005cca: e002 b.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
return;
8005ccc: bf00 nop
8005cce: e000 b.n 8005cd2 <HAL_UART_IRQHandler+0x51e>
return;
8005cd0: bf00 nop
}
}
8005cd2: 37e8 adds r7, #232 @ 0xe8
8005cd4: 46bd mov sp, r7
8005cd6: bd80 pop {r7, pc}
08005cd8 <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8005cd8: b480 push {r7}
8005cda: b083 sub sp, #12
8005cdc: af00 add r7, sp, #0
8005cde: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
8005ce0: bf00 nop
8005ce2: 370c adds r7, #12
8005ce4: 46bd mov sp, r7
8005ce6: bc80 pop {r7}
8005ce8: 4770 bx lr
08005cea <HAL_UART_RxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8005cea: b480 push {r7}
8005cec: b083 sub sp, #12
8005cee: af00 add r7, sp, #0
8005cf0: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
8005cf2: bf00 nop
8005cf4: 370c adds r7, #12
8005cf6: 46bd mov sp, r7
8005cf8: bc80 pop {r7}
8005cfa: 4770 bx lr
08005cfc <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8005cfc: b480 push {r7}
8005cfe: b083 sub sp, #12
8005d00: af00 add r7, sp, #0
8005d02: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8005d04: bf00 nop
8005d06: 370c adds r7, #12
8005d08: 46bd mov sp, r7
8005d0a: bc80 pop {r7}
8005d0c: 4770 bx lr
08005d0e <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8005d0e: b480 push {r7}
8005d10: b083 sub sp, #12
8005d12: af00 add r7, sp, #0
8005d14: 6078 str r0, [r7, #4]
8005d16: 460b mov r3, r1
8005d18: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8005d1a: bf00 nop
8005d1c: 370c adds r7, #12
8005d1e: 46bd mov sp, r7
8005d20: bc80 pop {r7}
8005d22: 4770 bx lr
08005d24 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8005d24: b580 push {r7, lr}
8005d26: b086 sub sp, #24
8005d28: af00 add r7, sp, #0
8005d2a: 60f8 str r0, [r7, #12]
8005d2c: 60b9 str r1, [r7, #8]
8005d2e: 603b str r3, [r7, #0]
8005d30: 4613 mov r3, r2
8005d32: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005d34: e03b b.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005d36: 6a3b ldr r3, [r7, #32]
8005d38: f1b3 3fff cmp.w r3, #4294967295
8005d3c: d037 beq.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8005d3e: f7fc ff95 bl 8002c6c <HAL_GetTick>
8005d42: 4602 mov r2, r0
8005d44: 683b ldr r3, [r7, #0]
8005d46: 1ad3 subs r3, r2, r3
8005d48: 6a3a ldr r2, [r7, #32]
8005d4a: 429a cmp r2, r3
8005d4c: d302 bcc.n 8005d54 <UART_WaitOnFlagUntilTimeout+0x30>
8005d4e: 6a3b ldr r3, [r7, #32]
8005d50: 2b00 cmp r3, #0
8005d52: d101 bne.n 8005d58 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8005d54: 2303 movs r3, #3
8005d56: e03a b.n 8005dce <UART_WaitOnFlagUntilTimeout+0xaa>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8005d58: 68fb ldr r3, [r7, #12]
8005d5a: 681b ldr r3, [r3, #0]
8005d5c: 68db ldr r3, [r3, #12]
8005d5e: f003 0304 and.w r3, r3, #4
8005d62: 2b00 cmp r3, #0
8005d64: d023 beq.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
8005d66: 68bb ldr r3, [r7, #8]
8005d68: 2b80 cmp r3, #128 @ 0x80
8005d6a: d020 beq.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
8005d6c: 68bb ldr r3, [r7, #8]
8005d6e: 2b40 cmp r3, #64 @ 0x40
8005d70: d01d beq.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8005d72: 68fb ldr r3, [r7, #12]
8005d74: 681b ldr r3, [r3, #0]
8005d76: 681b ldr r3, [r3, #0]
8005d78: f003 0308 and.w r3, r3, #8
8005d7c: 2b08 cmp r3, #8
8005d7e: d116 bne.n 8005dae <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_OREFLAG(huart);
8005d80: 2300 movs r3, #0
8005d82: 617b str r3, [r7, #20]
8005d84: 68fb ldr r3, [r7, #12]
8005d86: 681b ldr r3, [r3, #0]
8005d88: 681b ldr r3, [r3, #0]
8005d8a: 617b str r3, [r7, #20]
8005d8c: 68fb ldr r3, [r7, #12]
8005d8e: 681b ldr r3, [r3, #0]
8005d90: 685b ldr r3, [r3, #4]
8005d92: 617b str r3, [r7, #20]
8005d94: 697b ldr r3, [r7, #20]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8005d96: 68f8 ldr r0, [r7, #12]
8005d98: f000 f81d bl 8005dd6 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8005d9c: 68fb ldr r3, [r7, #12]
8005d9e: 2208 movs r2, #8
8005da0: 645a str r2, [r3, #68] @ 0x44
/* Process Unlocked */
__HAL_UNLOCK(huart);
8005da2: 68fb ldr r3, [r7, #12]
8005da4: 2200 movs r2, #0
8005da6: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8005daa: 2301 movs r3, #1
8005dac: e00f b.n 8005dce <UART_WaitOnFlagUntilTimeout+0xaa>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005dae: 68fb ldr r3, [r7, #12]
8005db0: 681b ldr r3, [r3, #0]
8005db2: 681a ldr r2, [r3, #0]
8005db4: 68bb ldr r3, [r7, #8]
8005db6: 4013 ands r3, r2
8005db8: 68ba ldr r2, [r7, #8]
8005dba: 429a cmp r2, r3
8005dbc: bf0c ite eq
8005dbe: 2301 moveq r3, #1
8005dc0: 2300 movne r3, #0
8005dc2: b2db uxtb r3, r3
8005dc4: 461a mov r2, r3
8005dc6: 79fb ldrb r3, [r7, #7]
8005dc8: 429a cmp r2, r3
8005dca: d0b4 beq.n 8005d36 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8005dcc: 2300 movs r3, #0
}
8005dce: 4618 mov r0, r3
8005dd0: 3718 adds r7, #24
8005dd2: 46bd mov sp, r7
8005dd4: bd80 pop {r7, pc}
08005dd6 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8005dd6: b480 push {r7}
8005dd8: b095 sub sp, #84 @ 0x54
8005dda: af00 add r7, sp, #0
8005ddc: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005dde: 687b ldr r3, [r7, #4]
8005de0: 681b ldr r3, [r3, #0]
8005de2: 330c adds r3, #12
8005de4: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005de6: 6b7b ldr r3, [r7, #52] @ 0x34
8005de8: e853 3f00 ldrex r3, [r3]
8005dec: 633b str r3, [r7, #48] @ 0x30
return(result);
8005dee: 6b3b ldr r3, [r7, #48] @ 0x30
8005df0: f423 7390 bic.w r3, r3, #288 @ 0x120
8005df4: 64fb str r3, [r7, #76] @ 0x4c
8005df6: 687b ldr r3, [r7, #4]
8005df8: 681b ldr r3, [r3, #0]
8005dfa: 330c adds r3, #12
8005dfc: 6cfa ldr r2, [r7, #76] @ 0x4c
8005dfe: 643a str r2, [r7, #64] @ 0x40
8005e00: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e02: 6bf9 ldr r1, [r7, #60] @ 0x3c
8005e04: 6c3a ldr r2, [r7, #64] @ 0x40
8005e06: e841 2300 strex r3, r2, [r1]
8005e0a: 63bb str r3, [r7, #56] @ 0x38
return(result);
8005e0c: 6bbb ldr r3, [r7, #56] @ 0x38
8005e0e: 2b00 cmp r3, #0
8005e10: d1e5 bne.n 8005dde <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005e12: 687b ldr r3, [r7, #4]
8005e14: 681b ldr r3, [r3, #0]
8005e16: 3314 adds r3, #20
8005e18: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005e1a: 6a3b ldr r3, [r7, #32]
8005e1c: e853 3f00 ldrex r3, [r3]
8005e20: 61fb str r3, [r7, #28]
return(result);
8005e22: 69fb ldr r3, [r7, #28]
8005e24: f023 0301 bic.w r3, r3, #1
8005e28: 64bb str r3, [r7, #72] @ 0x48
8005e2a: 687b ldr r3, [r7, #4]
8005e2c: 681b ldr r3, [r3, #0]
8005e2e: 3314 adds r3, #20
8005e30: 6cba ldr r2, [r7, #72] @ 0x48
8005e32: 62fa str r2, [r7, #44] @ 0x2c
8005e34: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e36: 6ab9 ldr r1, [r7, #40] @ 0x28
8005e38: 6afa ldr r2, [r7, #44] @ 0x2c
8005e3a: e841 2300 strex r3, r2, [r1]
8005e3e: 627b str r3, [r7, #36] @ 0x24
return(result);
8005e40: 6a7b ldr r3, [r7, #36] @ 0x24
8005e42: 2b00 cmp r3, #0
8005e44: d1e5 bne.n 8005e12 <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005e46: 687b ldr r3, [r7, #4]
8005e48: 6b1b ldr r3, [r3, #48] @ 0x30
8005e4a: 2b01 cmp r3, #1
8005e4c: d119 bne.n 8005e82 <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005e4e: 687b ldr r3, [r7, #4]
8005e50: 681b ldr r3, [r3, #0]
8005e52: 330c adds r3, #12
8005e54: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005e56: 68fb ldr r3, [r7, #12]
8005e58: e853 3f00 ldrex r3, [r3]
8005e5c: 60bb str r3, [r7, #8]
return(result);
8005e5e: 68bb ldr r3, [r7, #8]
8005e60: f023 0310 bic.w r3, r3, #16
8005e64: 647b str r3, [r7, #68] @ 0x44
8005e66: 687b ldr r3, [r7, #4]
8005e68: 681b ldr r3, [r3, #0]
8005e6a: 330c adds r3, #12
8005e6c: 6c7a ldr r2, [r7, #68] @ 0x44
8005e6e: 61ba str r2, [r7, #24]
8005e70: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e72: 6979 ldr r1, [r7, #20]
8005e74: 69ba ldr r2, [r7, #24]
8005e76: e841 2300 strex r3, r2, [r1]
8005e7a: 613b str r3, [r7, #16]
return(result);
8005e7c: 693b ldr r3, [r7, #16]
8005e7e: 2b00 cmp r3, #0
8005e80: d1e5 bne.n 8005e4e <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005e82: 687b ldr r3, [r7, #4]
8005e84: 2220 movs r2, #32
8005e86: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005e8a: 687b ldr r3, [r7, #4]
8005e8c: 2200 movs r2, #0
8005e8e: 631a str r2, [r3, #48] @ 0x30
}
8005e90: bf00 nop
8005e92: 3754 adds r7, #84 @ 0x54
8005e94: 46bd mov sp, r7
8005e96: bc80 pop {r7}
8005e98: 4770 bx lr
08005e9a <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8005e9a: b580 push {r7, lr}
8005e9c: b084 sub sp, #16
8005e9e: af00 add r7, sp, #0
8005ea0: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8005ea2: 687b ldr r3, [r7, #4]
8005ea4: 6a5b ldr r3, [r3, #36] @ 0x24
8005ea6: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8005ea8: 68fb ldr r3, [r7, #12]
8005eaa: 2200 movs r2, #0
8005eac: 85da strh r2, [r3, #46] @ 0x2e
huart->TxXferCount = 0x00U;
8005eae: 68fb ldr r3, [r7, #12]
8005eb0: 2200 movs r2, #0
8005eb2: 84da strh r2, [r3, #38] @ 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005eb4: 68f8 ldr r0, [r7, #12]
8005eb6: f7ff ff21 bl 8005cfc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8005eba: bf00 nop
8005ebc: 3710 adds r7, #16
8005ebe: 46bd mov sp, r7
8005ec0: bd80 pop {r7, pc}
08005ec2 <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
8005ec2: b480 push {r7}
8005ec4: b085 sub sp, #20
8005ec6: af00 add r7, sp, #0
8005ec8: 6078 str r0, [r7, #4]
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8005eca: 687b ldr r3, [r7, #4]
8005ecc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005ed0: b2db uxtb r3, r3
8005ed2: 2b21 cmp r3, #33 @ 0x21
8005ed4: d13e bne.n 8005f54 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005ed6: 687b ldr r3, [r7, #4]
8005ed8: 689b ldr r3, [r3, #8]
8005eda: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005ede: d114 bne.n 8005f0a <UART_Transmit_IT+0x48>
8005ee0: 687b ldr r3, [r7, #4]
8005ee2: 691b ldr r3, [r3, #16]
8005ee4: 2b00 cmp r3, #0
8005ee6: d110 bne.n 8005f0a <UART_Transmit_IT+0x48>
{
tmp = (const uint16_t *) huart->pTxBuffPtr;
8005ee8: 687b ldr r3, [r7, #4]
8005eea: 6a1b ldr r3, [r3, #32]
8005eec: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
8005eee: 68fb ldr r3, [r7, #12]
8005ef0: 881b ldrh r3, [r3, #0]
8005ef2: 461a mov r2, r3
8005ef4: 687b ldr r3, [r7, #4]
8005ef6: 681b ldr r3, [r3, #0]
8005ef8: f3c2 0208 ubfx r2, r2, #0, #9
8005efc: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
8005efe: 687b ldr r3, [r7, #4]
8005f00: 6a1b ldr r3, [r3, #32]
8005f02: 1c9a adds r2, r3, #2
8005f04: 687b ldr r3, [r7, #4]
8005f06: 621a str r2, [r3, #32]
8005f08: e008 b.n 8005f1c <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
8005f0a: 687b ldr r3, [r7, #4]
8005f0c: 6a1b ldr r3, [r3, #32]
8005f0e: 1c59 adds r1, r3, #1
8005f10: 687a ldr r2, [r7, #4]
8005f12: 6211 str r1, [r2, #32]
8005f14: 781a ldrb r2, [r3, #0]
8005f16: 687b ldr r3, [r7, #4]
8005f18: 681b ldr r3, [r3, #0]
8005f1a: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
8005f1c: 687b ldr r3, [r7, #4]
8005f1e: 8cdb ldrh r3, [r3, #38] @ 0x26
8005f20: b29b uxth r3, r3
8005f22: 3b01 subs r3, #1
8005f24: b29b uxth r3, r3
8005f26: 687a ldr r2, [r7, #4]
8005f28: 4619 mov r1, r3
8005f2a: 84d1 strh r1, [r2, #38] @ 0x26
8005f2c: 2b00 cmp r3, #0
8005f2e: d10f bne.n 8005f50 <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
8005f30: 687b ldr r3, [r7, #4]
8005f32: 681b ldr r3, [r3, #0]
8005f34: 68da ldr r2, [r3, #12]
8005f36: 687b ldr r3, [r7, #4]
8005f38: 681b ldr r3, [r3, #0]
8005f3a: f022 0280 bic.w r2, r2, #128 @ 0x80
8005f3e: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
8005f40: 687b ldr r3, [r7, #4]
8005f42: 681b ldr r3, [r3, #0]
8005f44: 68da ldr r2, [r3, #12]
8005f46: 687b ldr r3, [r7, #4]
8005f48: 681b ldr r3, [r3, #0]
8005f4a: f042 0240 orr.w r2, r2, #64 @ 0x40
8005f4e: 60da str r2, [r3, #12]
}
return HAL_OK;
8005f50: 2300 movs r3, #0
8005f52: e000 b.n 8005f56 <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
8005f54: 2302 movs r3, #2
}
}
8005f56: 4618 mov r0, r3
8005f58: 3714 adds r7, #20
8005f5a: 46bd mov sp, r7
8005f5c: bc80 pop {r7}
8005f5e: 4770 bx lr
08005f60 <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8005f60: b580 push {r7, lr}
8005f62: b082 sub sp, #8
8005f64: af00 add r7, sp, #0
8005f66: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
8005f68: 687b ldr r3, [r7, #4]
8005f6a: 681b ldr r3, [r3, #0]
8005f6c: 68da ldr r2, [r3, #12]
8005f6e: 687b ldr r3, [r7, #4]
8005f70: 681b ldr r3, [r3, #0]
8005f72: f022 0240 bic.w r2, r2, #64 @ 0x40
8005f76: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8005f78: 687b ldr r3, [r7, #4]
8005f7a: 2220 movs r2, #32
8005f7c: f883 2041 strb.w r2, [r3, #65] @ 0x41
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8005f80: 6878 ldr r0, [r7, #4]
8005f82: f7ff fea9 bl 8005cd8 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8005f86: 2300 movs r3, #0
}
8005f88: 4618 mov r0, r3
8005f8a: 3708 adds r7, #8
8005f8c: 46bd mov sp, r7
8005f8e: bd80 pop {r7, pc}
08005f90 <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
8005f90: b580 push {r7, lr}
8005f92: b08c sub sp, #48 @ 0x30
8005f94: af00 add r7, sp, #0
8005f96: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8005f98: 687b ldr r3, [r7, #4]
8005f9a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
8005f9e: b2db uxtb r3, r3
8005fa0: 2b22 cmp r3, #34 @ 0x22
8005fa2: f040 80ae bne.w 8006102 <UART_Receive_IT+0x172>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005fa6: 687b ldr r3, [r7, #4]
8005fa8: 689b ldr r3, [r3, #8]
8005faa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005fae: d117 bne.n 8005fe0 <UART_Receive_IT+0x50>
8005fb0: 687b ldr r3, [r7, #4]
8005fb2: 691b ldr r3, [r3, #16]
8005fb4: 2b00 cmp r3, #0
8005fb6: d113 bne.n 8005fe0 <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
8005fb8: 2300 movs r3, #0
8005fba: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
8005fbc: 687b ldr r3, [r7, #4]
8005fbe: 6a9b ldr r3, [r3, #40] @ 0x28
8005fc0: 62bb str r3, [r7, #40] @ 0x28
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
8005fc2: 687b ldr r3, [r7, #4]
8005fc4: 681b ldr r3, [r3, #0]
8005fc6: 685b ldr r3, [r3, #4]
8005fc8: b29b uxth r3, r3
8005fca: f3c3 0308 ubfx r3, r3, #0, #9
8005fce: b29a uxth r2, r3
8005fd0: 6abb ldr r3, [r7, #40] @ 0x28
8005fd2: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8005fd4: 687b ldr r3, [r7, #4]
8005fd6: 6a9b ldr r3, [r3, #40] @ 0x28
8005fd8: 1c9a adds r2, r3, #2
8005fda: 687b ldr r3, [r7, #4]
8005fdc: 629a str r2, [r3, #40] @ 0x28
8005fde: e026 b.n 800602e <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
8005fe0: 687b ldr r3, [r7, #4]
8005fe2: 6a9b ldr r3, [r3, #40] @ 0x28
8005fe4: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = NULL;
8005fe6: 2300 movs r3, #0
8005fe8: 62bb str r3, [r7, #40] @ 0x28
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8005fea: 687b ldr r3, [r7, #4]
8005fec: 689b ldr r3, [r3, #8]
8005fee: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005ff2: d007 beq.n 8006004 <UART_Receive_IT+0x74>
8005ff4: 687b ldr r3, [r7, #4]
8005ff6: 689b ldr r3, [r3, #8]
8005ff8: 2b00 cmp r3, #0
8005ffa: d10a bne.n 8006012 <UART_Receive_IT+0x82>
8005ffc: 687b ldr r3, [r7, #4]
8005ffe: 691b ldr r3, [r3, #16]
8006000: 2b00 cmp r3, #0
8006002: d106 bne.n 8006012 <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8006004: 687b ldr r3, [r7, #4]
8006006: 681b ldr r3, [r3, #0]
8006008: 685b ldr r3, [r3, #4]
800600a: b2da uxtb r2, r3
800600c: 6afb ldr r3, [r7, #44] @ 0x2c
800600e: 701a strb r2, [r3, #0]
8006010: e008 b.n 8006024 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8006012: 687b ldr r3, [r7, #4]
8006014: 681b ldr r3, [r3, #0]
8006016: 685b ldr r3, [r3, #4]
8006018: b2db uxtb r3, r3
800601a: f003 037f and.w r3, r3, #127 @ 0x7f
800601e: b2da uxtb r2, r3
8006020: 6afb ldr r3, [r7, #44] @ 0x2c
8006022: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
8006024: 687b ldr r3, [r7, #4]
8006026: 6a9b ldr r3, [r3, #40] @ 0x28
8006028: 1c5a adds r2, r3, #1
800602a: 687b ldr r3, [r7, #4]
800602c: 629a str r2, [r3, #40] @ 0x28
}
if (--huart->RxXferCount == 0U)
800602e: 687b ldr r3, [r7, #4]
8006030: 8ddb ldrh r3, [r3, #46] @ 0x2e
8006032: b29b uxth r3, r3
8006034: 3b01 subs r3, #1
8006036: b29b uxth r3, r3
8006038: 687a ldr r2, [r7, #4]
800603a: 4619 mov r1, r3
800603c: 85d1 strh r1, [r2, #46] @ 0x2e
800603e: 2b00 cmp r3, #0
8006040: d15d bne.n 80060fe <UART_Receive_IT+0x16e>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
8006042: 687b ldr r3, [r7, #4]
8006044: 681b ldr r3, [r3, #0]
8006046: 68da ldr r2, [r3, #12]
8006048: 687b ldr r3, [r7, #4]
800604a: 681b ldr r3, [r3, #0]
800604c: f022 0220 bic.w r2, r2, #32
8006050: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
8006052: 687b ldr r3, [r7, #4]
8006054: 681b ldr r3, [r3, #0]
8006056: 68da ldr r2, [r3, #12]
8006058: 687b ldr r3, [r7, #4]
800605a: 681b ldr r3, [r3, #0]
800605c: f422 7280 bic.w r2, r2, #256 @ 0x100
8006060: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
8006062: 687b ldr r3, [r7, #4]
8006064: 681b ldr r3, [r3, #0]
8006066: 695a ldr r2, [r3, #20]
8006068: 687b ldr r3, [r7, #4]
800606a: 681b ldr r3, [r3, #0]
800606c: f022 0201 bic.w r2, r2, #1
8006070: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006072: 687b ldr r3, [r7, #4]
8006074: 2220 movs r2, #32
8006076: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
800607a: 687b ldr r3, [r7, #4]
800607c: 2200 movs r2, #0
800607e: 635a str r2, [r3, #52] @ 0x34
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006080: 687b ldr r3, [r7, #4]
8006082: 6b1b ldr r3, [r3, #48] @ 0x30
8006084: 2b01 cmp r3, #1
8006086: d135 bne.n 80060f4 <UART_Receive_IT+0x164>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006088: 687b ldr r3, [r7, #4]
800608a: 2200 movs r2, #0
800608c: 631a str r2, [r3, #48] @ 0x30
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800608e: 687b ldr r3, [r7, #4]
8006090: 681b ldr r3, [r3, #0]
8006092: 330c adds r3, #12
8006094: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006096: 697b ldr r3, [r7, #20]
8006098: e853 3f00 ldrex r3, [r3]
800609c: 613b str r3, [r7, #16]
return(result);
800609e: 693b ldr r3, [r7, #16]
80060a0: f023 0310 bic.w r3, r3, #16
80060a4: 627b str r3, [r7, #36] @ 0x24
80060a6: 687b ldr r3, [r7, #4]
80060a8: 681b ldr r3, [r3, #0]
80060aa: 330c adds r3, #12
80060ac: 6a7a ldr r2, [r7, #36] @ 0x24
80060ae: 623a str r2, [r7, #32]
80060b0: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80060b2: 69f9 ldr r1, [r7, #28]
80060b4: 6a3a ldr r2, [r7, #32]
80060b6: e841 2300 strex r3, r2, [r1]
80060ba: 61bb str r3, [r7, #24]
return(result);
80060bc: 69bb ldr r3, [r7, #24]
80060be: 2b00 cmp r3, #0
80060c0: d1e5 bne.n 800608e <UART_Receive_IT+0xfe>
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
80060c2: 687b ldr r3, [r7, #4]
80060c4: 681b ldr r3, [r3, #0]
80060c6: 681b ldr r3, [r3, #0]
80060c8: f003 0310 and.w r3, r3, #16
80060cc: 2b10 cmp r3, #16
80060ce: d10a bne.n 80060e6 <UART_Receive_IT+0x156>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
80060d0: 2300 movs r3, #0
80060d2: 60fb str r3, [r7, #12]
80060d4: 687b ldr r3, [r7, #4]
80060d6: 681b ldr r3, [r3, #0]
80060d8: 681b ldr r3, [r3, #0]
80060da: 60fb str r3, [r7, #12]
80060dc: 687b ldr r3, [r7, #4]
80060de: 681b ldr r3, [r3, #0]
80060e0: 685b ldr r3, [r3, #4]
80060e2: 60fb str r3, [r7, #12]
80060e4: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80060e6: 687b ldr r3, [r7, #4]
80060e8: 8d9b ldrh r3, [r3, #44] @ 0x2c
80060ea: 4619 mov r1, r3
80060ec: 6878 ldr r0, [r7, #4]
80060ee: f7ff fe0e bl 8005d0e <HAL_UARTEx_RxEventCallback>
80060f2: e002 b.n 80060fa <UART_Receive_IT+0x16a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
80060f4: 6878 ldr r0, [r7, #4]
80060f6: f7ff fdf8 bl 8005cea <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
80060fa: 2300 movs r3, #0
80060fc: e002 b.n 8006104 <UART_Receive_IT+0x174>
}
return HAL_OK;
80060fe: 2300 movs r3, #0
8006100: e000 b.n 8006104 <UART_Receive_IT+0x174>
}
else
{
return HAL_BUSY;
8006102: 2302 movs r3, #2
}
}
8006104: 4618 mov r0, r3
8006106: 3730 adds r7, #48 @ 0x30
8006108: 46bd mov sp, r7
800610a: bd80 pop {r7, pc}
0800610c <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
800610c: b580 push {r7, lr}
800610e: b084 sub sp, #16
8006110: af00 add r7, sp, #0
8006112: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8006114: 687b ldr r3, [r7, #4]
8006116: 681b ldr r3, [r3, #0]
8006118: 691b ldr r3, [r3, #16]
800611a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
800611e: 687b ldr r3, [r7, #4]
8006120: 68da ldr r2, [r3, #12]
8006122: 687b ldr r3, [r7, #4]
8006124: 681b ldr r3, [r3, #0]
8006126: 430a orrs r2, r1
8006128: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
800612a: 687b ldr r3, [r7, #4]
800612c: 689a ldr r2, [r3, #8]
800612e: 687b ldr r3, [r7, #4]
8006130: 691b ldr r3, [r3, #16]
8006132: 431a orrs r2, r3
8006134: 687b ldr r3, [r7, #4]
8006136: 695b ldr r3, [r3, #20]
8006138: 4313 orrs r3, r2
800613a: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
800613c: 687b ldr r3, [r7, #4]
800613e: 681b ldr r3, [r3, #0]
8006140: 68db ldr r3, [r3, #12]
8006142: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8006146: f023 030c bic.w r3, r3, #12
800614a: 687a ldr r2, [r7, #4]
800614c: 6812 ldr r2, [r2, #0]
800614e: 68b9 ldr r1, [r7, #8]
8006150: 430b orrs r3, r1
8006152: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8006154: 687b ldr r3, [r7, #4]
8006156: 681b ldr r3, [r3, #0]
8006158: 695b ldr r3, [r3, #20]
800615a: f423 7140 bic.w r1, r3, #768 @ 0x300
800615e: 687b ldr r3, [r7, #4]
8006160: 699a ldr r2, [r3, #24]
8006162: 687b ldr r3, [r7, #4]
8006164: 681b ldr r3, [r3, #0]
8006166: 430a orrs r2, r1
8006168: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
800616a: 687b ldr r3, [r7, #4]
800616c: 681b ldr r3, [r3, #0]
800616e: 4a2c ldr r2, [pc, #176] @ (8006220 <UART_SetConfig+0x114>)
8006170: 4293 cmp r3, r2
8006172: d103 bne.n 800617c <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8006174: f7ff f95a bl 800542c <HAL_RCC_GetPCLK2Freq>
8006178: 60f8 str r0, [r7, #12]
800617a: e002 b.n 8006182 <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800617c: f7ff f942 bl 8005404 <HAL_RCC_GetPCLK1Freq>
8006180: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8006182: 68fa ldr r2, [r7, #12]
8006184: 4613 mov r3, r2
8006186: 009b lsls r3, r3, #2
8006188: 4413 add r3, r2
800618a: 009a lsls r2, r3, #2
800618c: 441a add r2, r3
800618e: 687b ldr r3, [r7, #4]
8006190: 685b ldr r3, [r3, #4]
8006192: 009b lsls r3, r3, #2
8006194: fbb2 f3f3 udiv r3, r2, r3
8006198: 4a22 ldr r2, [pc, #136] @ (8006224 <UART_SetConfig+0x118>)
800619a: fba2 2303 umull r2, r3, r2, r3
800619e: 095b lsrs r3, r3, #5
80061a0: 0119 lsls r1, r3, #4
80061a2: 68fa ldr r2, [r7, #12]
80061a4: 4613 mov r3, r2
80061a6: 009b lsls r3, r3, #2
80061a8: 4413 add r3, r2
80061aa: 009a lsls r2, r3, #2
80061ac: 441a add r2, r3
80061ae: 687b ldr r3, [r7, #4]
80061b0: 685b ldr r3, [r3, #4]
80061b2: 009b lsls r3, r3, #2
80061b4: fbb2 f2f3 udiv r2, r2, r3
80061b8: 4b1a ldr r3, [pc, #104] @ (8006224 <UART_SetConfig+0x118>)
80061ba: fba3 0302 umull r0, r3, r3, r2
80061be: 095b lsrs r3, r3, #5
80061c0: 2064 movs r0, #100 @ 0x64
80061c2: fb00 f303 mul.w r3, r0, r3
80061c6: 1ad3 subs r3, r2, r3
80061c8: 011b lsls r3, r3, #4
80061ca: 3332 adds r3, #50 @ 0x32
80061cc: 4a15 ldr r2, [pc, #84] @ (8006224 <UART_SetConfig+0x118>)
80061ce: fba2 2303 umull r2, r3, r2, r3
80061d2: 095b lsrs r3, r3, #5
80061d4: f003 03f0 and.w r3, r3, #240 @ 0xf0
80061d8: 4419 add r1, r3
80061da: 68fa ldr r2, [r7, #12]
80061dc: 4613 mov r3, r2
80061de: 009b lsls r3, r3, #2
80061e0: 4413 add r3, r2
80061e2: 009a lsls r2, r3, #2
80061e4: 441a add r2, r3
80061e6: 687b ldr r3, [r7, #4]
80061e8: 685b ldr r3, [r3, #4]
80061ea: 009b lsls r3, r3, #2
80061ec: fbb2 f2f3 udiv r2, r2, r3
80061f0: 4b0c ldr r3, [pc, #48] @ (8006224 <UART_SetConfig+0x118>)
80061f2: fba3 0302 umull r0, r3, r3, r2
80061f6: 095b lsrs r3, r3, #5
80061f8: 2064 movs r0, #100 @ 0x64
80061fa: fb00 f303 mul.w r3, r0, r3
80061fe: 1ad3 subs r3, r2, r3
8006200: 011b lsls r3, r3, #4
8006202: 3332 adds r3, #50 @ 0x32
8006204: 4a07 ldr r2, [pc, #28] @ (8006224 <UART_SetConfig+0x118>)
8006206: fba2 2303 umull r2, r3, r2, r3
800620a: 095b lsrs r3, r3, #5
800620c: f003 020f and.w r2, r3, #15
8006210: 687b ldr r3, [r7, #4]
8006212: 681b ldr r3, [r3, #0]
8006214: 440a add r2, r1
8006216: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8006218: bf00 nop
800621a: 3710 adds r7, #16
800621c: 46bd mov sp, r7
800621e: bd80 pop {r7, pc}
8006220: 40013800 .word 0x40013800
8006224: 51eb851f .word 0x51eb851f
08006228 <memset>:
8006228: 4603 mov r3, r0
800622a: 4402 add r2, r0
800622c: 4293 cmp r3, r2
800622e: d100 bne.n 8006232 <memset+0xa>
8006230: 4770 bx lr
8006232: f803 1b01 strb.w r1, [r3], #1
8006236: e7f9 b.n 800622c <memset+0x4>
08006238 <__errno>:
8006238: 4b01 ldr r3, [pc, #4] @ (8006240 <__errno+0x8>)
800623a: 6818 ldr r0, [r3, #0]
800623c: 4770 bx lr
800623e: bf00 nop
8006240: 20000024 .word 0x20000024
08006244 <__libc_init_array>:
8006244: b570 push {r4, r5, r6, lr}
8006246: 2600 movs r6, #0
8006248: 4d0c ldr r5, [pc, #48] @ (800627c <__libc_init_array+0x38>)
800624a: 4b0d ldr r3, [pc, #52] @ (8006280 <__libc_init_array+0x3c>)
800624c: 1b5b subs r3, r3, r5
800624e: 109c asrs r4, r3, #2
8006250: 42a6 cmp r6, r4
8006252: d109 bne.n 8006268 <__libc_init_array+0x24>
8006254: 2600 movs r6, #0
8006256: f000 f8db bl 8006410 <_init>
800625a: 4d0a ldr r5, [pc, #40] @ (8006284 <__libc_init_array+0x40>)
800625c: 4b0a ldr r3, [pc, #40] @ (8006288 <__libc_init_array+0x44>)
800625e: 1b5b subs r3, r3, r5
8006260: 109c asrs r4, r3, #2
8006262: 42a6 cmp r6, r4
8006264: d105 bne.n 8006272 <__libc_init_array+0x2e>
8006266: bd70 pop {r4, r5, r6, pc}
8006268: f855 3b04 ldr.w r3, [r5], #4
800626c: 4798 blx r3
800626e: 3601 adds r6, #1
8006270: e7ee b.n 8006250 <__libc_init_array+0xc>
8006272: f855 3b04 ldr.w r3, [r5], #4
8006276: 4798 blx r3
8006278: 3601 adds r6, #1
800627a: e7f2 b.n 8006262 <__libc_init_array+0x1e>
800627c: 080064a4 .word 0x080064a4
8006280: 080064a4 .word 0x080064a4
8006284: 080064a4 .word 0x080064a4
8006288: 080064a8 .word 0x080064a8
0800628c <memcpy>:
800628c: 440a add r2, r1
800628e: 4291 cmp r1, r2
8006290: f100 33ff add.w r3, r0, #4294967295
8006294: d100 bne.n 8006298 <memcpy+0xc>
8006296: 4770 bx lr
8006298: b510 push {r4, lr}
800629a: f811 4b01 ldrb.w r4, [r1], #1
800629e: 4291 cmp r1, r2
80062a0: f803 4f01 strb.w r4, [r3, #1]!
80062a4: d1f9 bne.n 800629a <memcpy+0xe>
80062a6: bd10 pop {r4, pc}
080062a8 <sqrtf>:
80062a8: b538 push {r3, r4, r5, lr}
80062aa: 4604 mov r4, r0
80062ac: f000 f81a bl 80062e4 <__ieee754_sqrtf>
80062b0: 4621 mov r1, r4
80062b2: 4605 mov r5, r0
80062b4: 4620 mov r0, r4
80062b6: f7fa fdbb bl 8000e30 <__aeabi_fcmpun>
80062ba: b920 cbnz r0, 80062c6 <sqrtf+0x1e>
80062bc: 4620 mov r0, r4
80062be: 2100 movs r1, #0
80062c0: f7fa fd8e bl 8000de0 <__aeabi_fcmplt>
80062c4: b908 cbnz r0, 80062ca <sqrtf+0x22>
80062c6: 4628 mov r0, r5
80062c8: bd38 pop {r3, r4, r5, pc}
80062ca: f7ff ffb5 bl 8006238 <__errno>
80062ce: 2221 movs r2, #33 @ 0x21
80062d0: 4603 mov r3, r0
80062d2: 2100 movs r1, #0
80062d4: 601a str r2, [r3, #0]
80062d6: 4608 mov r0, r1
80062d8: f7fa fc98 bl 8000c0c <__aeabi_fdiv>
80062dc: 4605 mov r5, r0
80062de: 4628 mov r0, r5
80062e0: bd38 pop {r3, r4, r5, pc}
80062e2: bf00 nop
080062e4 <__ieee754_sqrtf>:
80062e4: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000
80062e8: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000
80062ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80062f0: 4604 mov r4, r0
80062f2: d24f bcs.n 8006394 <__ieee754_sqrtf+0xb0>
80062f4: 2a00 cmp r2, #0
80062f6: d04b beq.n 8006390 <__ieee754_sqrtf+0xac>
80062f8: 2800 cmp r0, #0
80062fa: 4603 mov r3, r0
80062fc: db54 blt.n 80063a8 <__ieee754_sqrtf+0xc4>
80062fe: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000
8006302: d14f bne.n 80063a4 <__ieee754_sqrtf+0xc0>
8006304: 005b lsls r3, r3, #1
8006306: 0218 lsls r0, r3, #8
8006308: 4611 mov r1, r2
800630a: f102 0201 add.w r2, r2, #1
800630e: d5f9 bpl.n 8006304 <__ieee754_sqrtf+0x20>
8006310: 4249 negs r1, r1
8006312: 2400 movs r4, #0
8006314: f3c3 0216 ubfx r2, r3, #0, #23
8006318: f1a1 057f sub.w r5, r1, #127 @ 0x7f
800631c: 07cb lsls r3, r1, #31
800631e: f04f 0e19 mov.w lr, #25
8006322: f04f 7c80 mov.w ip, #16777216 @ 0x1000000
8006326: 4621 mov r1, r4
8006328: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
800632c: bf58 it pl
800632e: 0052 lslpl r2, r2, #1
8006330: 106d asrs r5, r5, #1
8006332: 0052 lsls r2, r2, #1
8006334: eb01 030c add.w r3, r1, ip
8006338: 4293 cmp r3, r2
800633a: bfcf iteee gt
800633c: 4613 movgt r3, r2
800633e: eb03 010c addle.w r1, r3, ip
8006342: 4464 addle r4, ip
8006344: 1ad3 suble r3, r2, r3
8006346: f1be 0e01 subs.w lr, lr, #1
800634a: ea4f 0243 mov.w r2, r3, lsl #1
800634e: ea4f 0c5c mov.w ip, ip, lsr #1
8006352: d1ef bne.n 8006334 <__ieee754_sqrtf+0x50>
8006354: b1bb cbz r3, 8006386 <__ieee754_sqrtf+0xa2>
8006356: 4e1a ldr r6, [pc, #104] @ (80063c0 <__ieee754_sqrtf+0xdc>)
8006358: 4f1a ldr r7, [pc, #104] @ (80063c4 <__ieee754_sqrtf+0xe0>)
800635a: 6830 ldr r0, [r6, #0]
800635c: 6839 ldr r1, [r7, #0]
800635e: f7fa fa97 bl 8000890 <__aeabi_fsub>
8006362: f8d6 8000 ldr.w r8, [r6]
8006366: 4601 mov r1, r0
8006368: 4640 mov r0, r8
800636a: f7fa fd43 bl 8000df4 <__aeabi_fcmple>
800636e: b150 cbz r0, 8006386 <__ieee754_sqrtf+0xa2>
8006370: 6830 ldr r0, [r6, #0]
8006372: 6839 ldr r1, [r7, #0]
8006374: f7fa fa8e bl 8000894 <__addsf3>
8006378: 6836 ldr r6, [r6, #0]
800637a: 4601 mov r1, r0
800637c: 4630 mov r0, r6
800637e: f7fa fd2f bl 8000de0 <__aeabi_fcmplt>
8006382: b1c8 cbz r0, 80063b8 <__ieee754_sqrtf+0xd4>
8006384: 3402 adds r4, #2
8006386: 1060 asrs r0, r4, #1
8006388: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000
800638c: eb00 50c5 add.w r0, r0, r5, lsl #23
8006390: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006394: 4601 mov r1, r0
8006396: f7fa fb85 bl 8000aa4 <__aeabi_fmul>
800639a: 4621 mov r1, r4
800639c: f7fa fa7a bl 8000894 <__addsf3>
80063a0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80063a4: 15c1 asrs r1, r0, #23
80063a6: e7b4 b.n 8006312 <__ieee754_sqrtf+0x2e>
80063a8: 4601 mov r1, r0
80063aa: f7fa fa71 bl 8000890 <__aeabi_fsub>
80063ae: 4601 mov r1, r0
80063b0: f7fa fc2c bl 8000c0c <__aeabi_fdiv>
80063b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80063b8: 3401 adds r4, #1
80063ba: f024 0401 bic.w r4, r4, #1
80063be: e7e2 b.n 8006386 <__ieee754_sqrtf+0xa2>
80063c0: 08006498 .word 0x08006498
80063c4: 08006494 .word 0x08006494
080063c8 <roundf>:
80063c8: b508 push {r3, lr}
80063ca: f3c0 53c7 ubfx r3, r0, #23, #8
80063ce: 3b7f subs r3, #127 @ 0x7f
80063d0: 2b16 cmp r3, #22
80063d2: 4601 mov r1, r0
80063d4: dc0e bgt.n 80063f4 <roundf+0x2c>
80063d6: 2b00 cmp r3, #0
80063d8: 4602 mov r2, r0
80063da: db10 blt.n 80063fe <roundf+0x36>
80063dc: 480b ldr r0, [pc, #44] @ (800640c <roundf+0x44>)
80063de: 4118 asrs r0, r3
80063e0: 4201 tst r1, r0
80063e2: d005 beq.n 80063f0 <roundf+0x28>
80063e4: f44f 0180 mov.w r1, #4194304 @ 0x400000
80063e8: 4119 asrs r1, r3
80063ea: 4411 add r1, r2
80063ec: ea21 0100 bic.w r1, r1, r0
80063f0: 4608 mov r0, r1
80063f2: bd08 pop {r3, pc}
80063f4: 2b80 cmp r3, #128 @ 0x80
80063f6: d1fb bne.n 80063f0 <roundf+0x28>
80063f8: f7fa fa4c bl 8000894 <__addsf3>
80063fc: bd08 pop {r3, pc}
80063fe: 3301 adds r3, #1
8006400: f000 4100 and.w r1, r0, #2147483648 @ 0x80000000
8006404: d1f4 bne.n 80063f0 <roundf+0x28>
8006406: f041 517e orr.w r1, r1, #1065353216 @ 0x3f800000
800640a: e7f1 b.n 80063f0 <roundf+0x28>
800640c: 007fffff .word 0x007fffff
08006410 <_init>:
8006410: b5f8 push {r3, r4, r5, r6, r7, lr}
8006412: bf00 nop
8006414: bcf8 pop {r3, r4, r5, r6, r7}
8006416: bc08 pop {r3}
8006418: 469e mov lr, r3
800641a: 4770 bx lr
0800641c <_fini>:
800641c: b5f8 push {r3, r4, r5, r6, r7, lr}
800641e: bf00 nop
8006420: bcf8 pop {r3, r4, r5, r6, r7}
8006422: bc08 pop {r3}
8006424: 469e mov lr, r3
8006426: 4770 bx lr
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