hardware/fertirrega_v6
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f1cf74ceafe04096669fced5e2353a1ee972536e
fertirrega_v6/Fertirrega_v6/Debug/Fertirrega_v6.list
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Fertirrega_v6.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000065b4 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000084 080066c0 080066c0 000076c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08006744 08006744 00008094 2**0
CONTENTS, READONLY
4 .ARM 00000008 08006744 08006744 00007744 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800674c 0800674c 00008094 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800674c 0800674c 0000774c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08006750 08006750 00007750 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000094 20000000 08006754 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000008b8 20000094 080067e8 00008094 2**2
ALLOC
10 ._user_heap_stack 00000604 2000094c 080067e8 0000894c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00008094 2**0
CONTENTS, READONLY
12 .debug_info 00014af9 00000000 00000000 000080bd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003648 00000000 00000000 0001cbb6 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001310 00000000 00000000 00020200 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000f01 00000000 00000000 00021510 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001a7c4 00000000 00000000 00022411 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00018bbb 00000000 00000000 0003cbd5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00095b1b 00000000 00000000 00055790 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000eb2ab 2**0
CONTENTS, READONLY
20 .debug_frame 00005088 00000000 00000000 000eb2f0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000f0378 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000094 .word 0x20000094
8000128: 00000000 .word 0x00000000
800012c: 080066a8 .word 0x080066a8
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000098 .word 0x20000098
8000148: 080066a8 .word 0x080066a8
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <__aeabi_dmul>:
800015c: b570 push {r4, r5, r6, lr}
800015e: f04f 0cff mov.w ip, #255 @ 0xff
8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20
800016a: bf1d ittte ne
800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000170: ea94 0f0c teqne r4, ip
8000174: ea95 0f0c teqne r5, ip
8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc>
800017c: 442c add r4, r5
800017e: ea81 0603 eor.w r6, r1, r3
8000182: ea21 514c bic.w r1, r1, ip, lsl #21
8000186: ea23 534c bic.w r3, r3, ip, lsl #21
800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12
800018e: bf18 it ne
8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4>
800019e: fba0 ce02 umull ip, lr, r0, r2
80001a2: f04f 0500 mov.w r5, #0
80001a6: fbe1 e502 umlal lr, r5, r1, r2
80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80001ae: fbe0 e503 umlal lr, r5, r0, r3
80001b2: f04f 0600 mov.w r6, #0
80001b6: fbe1 5603 umlal r5, r6, r1, r3
80001ba: f09c 0f00 teq ip, #0
80001be: bf18 it ne
80001c0: f04e 0e01 orrne.w lr, lr, #1
80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff
80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200
80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300
80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80>
80001d2: ea5f 0e4e movs.w lr, lr, lsl #1
80001d6: 416d adcs r5, r5
80001d8: eb46 0606 adc.w r6, r6, r6
80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11
80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21
80001e4: ea4f 20c5 mov.w r0, r5, lsl #11
80001e8: ea40 505e orr.w r0, r0, lr, lsr #21
80001ec: ea4f 2ece mov.w lr, lr, lsl #11
80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80001f4: bf88 it hi
80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde>
80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
8000200: bf08 it eq
8000202: ea5f 0e50 movseq.w lr, r0, lsr #1
8000206: f150 0000 adcs.w r0, r0, #0
800020a: eb41 5104 adc.w r1, r1, r4, lsl #20
800020e: bd70 pop {r4, r5, r6, pc}
8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000214: ea46 0101 orr.w r1, r6, r1
8000218: ea40 0002 orr.w r0, r0, r2
800021c: ea81 0103 eor.w r1, r1, r3
8000220: ebb4 045c subs.w r4, r4, ip, lsr #1
8000224: bfc2 ittt gt
8000226: ebd4 050c rsbsgt r5, r4, ip
800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800022e: bd70 popgt {r4, r5, r6, pc}
8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000234: f04f 0e00 mov.w lr, #0
8000238: 3c01 subs r4, #1
800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238>
800023e: f114 0f36 cmn.w r4, #54 @ 0x36
8000242: bfde ittt le
8000244: 2000 movle r0, #0
8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
800024a: bd70 pople {r4, r5, r6, pc}
800024c: f1c4 0400 rsb r4, r4, #0
8000250: 3c20 subs r4, #32
8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164>
8000254: 340c adds r4, #12
8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134>
8000258: f104 0414 add.w r4, r4, #20
800025c: f1c4 0520 rsb r5, r4, #32
8000260: fa00 f305 lsl.w r3, r0, r5
8000264: fa20 f004 lsr.w r0, r0, r4
8000268: fa01 f205 lsl.w r2, r1, r5
800026c: ea40 0002 orr.w r0, r0, r2
8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31
800027c: fa21 f604 lsr.w r6, r1, r4
8000280: eb42 0106 adc.w r1, r2, r6
8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000288: bf08 it eq
800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800028e: bd70 pop {r4, r5, r6, pc}
8000290: f1c4 040c rsb r4, r4, #12
8000294: f1c4 0520 rsb r5, r4, #32
8000298: fa00 f304 lsl.w r3, r0, r4
800029c: fa20 f005 lsr.w r0, r0, r5
80002a0: fa01 f204 lsl.w r2, r1, r4
80002a4: ea40 0002 orr.w r0, r0, r2
80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002b0: f141 0100 adc.w r1, r1, #0
80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002b8: bf08 it eq
80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002be: bd70 pop {r4, r5, r6, pc}
80002c0: f1c4 0520 rsb r5, r4, #32
80002c4: fa00 f205 lsl.w r2, r0, r5
80002c8: ea4e 0e02 orr.w lr, lr, r2
80002cc: fa20 f304 lsr.w r3, r0, r4
80002d0: fa01 f205 lsl.w r2, r1, r5
80002d4: ea43 0302 orr.w r3, r3, r2
80002d8: fa21 f004 lsr.w r0, r1, r4
80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002e0: fa21 f204 lsr.w r2, r1, r4
80002e4: ea20 0002 bic.w r0, r0, r2
80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31
80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002f0: bf08 it eq
80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002f6: bd70 pop {r4, r5, r6, pc}
80002f8: f094 0f00 teq r4, #0
80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2>
80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
8000302: 0040 lsls r0, r0, #1
8000304: eb41 0101 adc.w r1, r1, r1
8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000
800030c: bf08 it eq
800030e: 3c01 subeq r4, #1
8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6>
8000312: ea41 0106 orr.w r1, r1, r6
8000316: f095 0f00 teq r5, #0
800031a: bf18 it ne
800031c: 4770 bxne lr
800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
8000322: 0052 lsls r2, r2, #1
8000324: eb43 0303 adc.w r3, r3, r3
8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000
800032c: bf08 it eq
800032e: 3d01 subeq r5, #1
8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6>
8000332: ea43 0306 orr.w r3, r3, r6
8000336: 4770 bx lr
8000338: ea94 0f0c teq r4, ip
800033c: ea0c 5513 and.w r5, ip, r3, lsr #20
8000340: bf18 it ne
8000342: ea95 0f0c teqne r5, ip
8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206>
8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1
800034c: bf18 it ne
800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c>
8000354: ea81 0103 eor.w r1, r1, r3
8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800035c: f04f 0000 mov.w r0, #0
8000360: bd70 pop {r4, r5, r6, pc}
8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000366: bf06 itte eq
8000368: 4610 moveq r0, r2
800036a: 4619 moveq r1, r3
800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a>
8000372: ea94 0f0c teq r4, ip
8000376: d102 bne.n 800037e <__aeabi_dmul+0x222>
8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12
800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a>
800037e: ea95 0f0c teq r5, ip
8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234>
8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000388: bf1c itt ne
800038a: 4610 movne r0, r2
800038c: 4619 movne r1, r3
800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a>
8000390: ea81 0103 eor.w r1, r1, r3
8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003a0: f04f 0000 mov.w r0, #0
80003a4: bd70 pop {r4, r5, r6, pc}
80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80003ae: bd70 pop {r4, r5, r6, pc}
080003b0 <__aeabi_drsub>:
80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
80003b4: e002 b.n 80003bc <__adddf3>
80003b6: bf00 nop
080003b8 <__aeabi_dsub>:
80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
080003bc <__adddf3>:
80003bc: b530 push {r4, r5, lr}
80003be: ea4f 0441 mov.w r4, r1, lsl #1
80003c2: ea4f 0543 mov.w r5, r3, lsl #1
80003c6: ea94 0f05 teq r4, r5
80003ca: bf08 it eq
80003cc: ea90 0f02 teqeq r0, r2
80003d0: bf1f itttt ne
80003d2: ea54 0c00 orrsne.w ip, r4, r0
80003d6: ea55 0c02 orrsne.w ip, r5, r2
80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21
80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21
80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee>
80003e6: ea4f 5454 mov.w r4, r4, lsr #21
80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21
80003ee: bfb8 it lt
80003f0: 426d neglt r5, r5
80003f2: dd0c ble.n 800040e <__adddf3+0x52>
80003f4: 442c add r4, r5
80003f6: ea80 0202 eor.w r2, r0, r2
80003fa: ea81 0303 eor.w r3, r1, r3
80003fe: ea82 0000 eor.w r0, r2, r0
8000402: ea83 0101 eor.w r1, r3, r1
8000406: ea80 0202 eor.w r2, r0, r2
800040a: ea81 0303 eor.w r3, r1, r3
800040e: 2d36 cmp r5, #54 @ 0x36
8000410: bf88 it hi
8000412: bd30 pophi {r4, r5, pc}
8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000418: ea4f 3101 mov.w r1, r1, lsl #12
800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000424: d002 beq.n 800042c <__adddf3+0x70>
8000426: 4240 negs r0, r0
8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1
800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000430: ea4f 3303 mov.w r3, r3, lsl #12
8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000438: d002 beq.n 8000440 <__adddf3+0x84>
800043a: 4252 negs r2, r2
800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000440: ea94 0f05 teq r4, r5
8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da>
8000448: f1a4 0401 sub.w r4, r4, #1
800044c: f1d5 0e20 rsbs lr, r5, #32
8000450: db0d blt.n 800046e <__adddf3+0xb2>
8000452: fa02 fc0e lsl.w ip, r2, lr
8000456: fa22 f205 lsr.w r2, r2, r5
800045a: 1880 adds r0, r0, r2
800045c: f141 0100 adc.w r1, r1, #0
8000460: fa03 f20e lsl.w r2, r3, lr
8000464: 1880 adds r0, r0, r2
8000466: fa43 f305 asr.w r3, r3, r5
800046a: 4159 adcs r1, r3
800046c: e00e b.n 800048c <__adddf3+0xd0>
800046e: f1a5 0520 sub.w r5, r5, #32
8000472: f10e 0e20 add.w lr, lr, #32
8000476: 2a01 cmp r2, #1
8000478: fa03 fc0e lsl.w ip, r3, lr
800047c: bf28 it cs
800047e: f04c 0c02 orrcs.w ip, ip, #2
8000482: fa43 f305 asr.w r3, r3, r5
8000486: 18c0 adds r0, r0, r3
8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31
800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000490: d507 bpl.n 80004a2 <__adddf3+0xe6>
8000492: f04f 0e00 mov.w lr, #0
8000496: f1dc 0c00 rsbs ip, ip, #0
800049a: eb7e 0000 sbcs.w r0, lr, r0
800049e: eb6e 0101 sbc.w r1, lr, r1
80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80004a6: d31b bcc.n 80004e0 <__adddf3+0x124>
80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c>
80004ae: 0849 lsrs r1, r1, #1
80004b0: ea5f 0030 movs.w r0, r0, rrx
80004b4: ea4f 0c3c mov.w ip, ip, rrx
80004b8: f104 0401 add.w r4, r4, #1
80004bc: ea4f 5244 mov.w r2, r4, lsl #21
80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240>
80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80004cc: bf08 it eq
80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1
80004d2: f150 0000 adcs.w r0, r0, #0
80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20
80004da: ea41 0105 orr.w r1, r1, r5
80004de: bd30 pop {r4, r5, pc}
80004e0: ea5f 0c4c movs.w ip, ip, lsl #1
80004e4: 4140 adcs r0, r0
80004e6: eb41 0101 adc.w r1, r1, r1
80004ea: 3c01 subs r4, #1
80004ec: bf28 it cs
80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c>
80004f4: f091 0f00 teq r1, #0
80004f8: bf04 itt eq
80004fa: 4601 moveq r1, r0
80004fc: 2000 moveq r0, #0
80004fe: fab1 f381 clz r3, r1
8000502: bf08 it eq
8000504: 3320 addeq r3, #32
8000506: f1a3 030b sub.w r3, r3, #11
800050a: f1b3 0220 subs.w r2, r3, #32
800050e: da0c bge.n 800052a <__adddf3+0x16e>
8000510: 320c adds r2, #12
8000512: dd08 ble.n 8000526 <__adddf3+0x16a>
8000514: f102 0c14 add.w ip, r2, #20
8000518: f1c2 020c rsb r2, r2, #12
800051c: fa01 f00c lsl.w r0, r1, ip
8000520: fa21 f102 lsr.w r1, r1, r2
8000524: e00c b.n 8000540 <__adddf3+0x184>
8000526: f102 0214 add.w r2, r2, #20
800052a: bfd8 it le
800052c: f1c2 0c20 rsble ip, r2, #32
8000530: fa01 f102 lsl.w r1, r1, r2
8000534: fa20 fc0c lsr.w ip, r0, ip
8000538: bfdc itt le
800053a: ea41 010c orrle.w r1, r1, ip
800053e: 4090 lslle r0, r2
8000540: 1ae4 subs r4, r4, r3
8000542: bfa2 ittt ge
8000544: eb01 5104 addge.w r1, r1, r4, lsl #20
8000548: 4329 orrge r1, r5
800054a: bd30 popge {r4, r5, pc}
800054c: ea6f 0404 mvn.w r4, r4
8000550: 3c1f subs r4, #31
8000552: da1c bge.n 800058e <__adddf3+0x1d2>
8000554: 340c adds r4, #12
8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba>
8000558: f104 0414 add.w r4, r4, #20
800055c: f1c4 0220 rsb r2, r4, #32
8000560: fa20 f004 lsr.w r0, r0, r4
8000564: fa01 f302 lsl.w r3, r1, r2
8000568: ea40 0003 orr.w r0, r0, r3
800056c: fa21 f304 lsr.w r3, r1, r4
8000570: ea45 0103 orr.w r1, r5, r3
8000574: bd30 pop {r4, r5, pc}
8000576: f1c4 040c rsb r4, r4, #12
800057a: f1c4 0220 rsb r2, r4, #32
800057e: fa20 f002 lsr.w r0, r0, r2
8000582: fa01 f304 lsl.w r3, r1, r4
8000586: ea40 0003 orr.w r0, r0, r3
800058a: 4629 mov r1, r5
800058c: bd30 pop {r4, r5, pc}
800058e: fa21 f004 lsr.w r0, r1, r4
8000592: 4629 mov r1, r5
8000594: bd30 pop {r4, r5, pc}
8000596: f094 0f00 teq r4, #0
800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800059e: bf06 itte eq
80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
80005a4: 3401 addeq r4, #1
80005a6: 3d01 subne r5, #1
80005a8: e74e b.n 8000448 <__adddf3+0x8c>
80005aa: ea7f 5c64 mvns.w ip, r4, asr #21
80005ae: bf18 it ne
80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21
80005b4: d029 beq.n 800060a <__adddf3+0x24e>
80005b6: ea94 0f05 teq r4, r5
80005ba: bf08 it eq
80005bc: ea90 0f02 teqeq r0, r2
80005c0: d005 beq.n 80005ce <__adddf3+0x212>
80005c2: ea54 0c00 orrs.w ip, r4, r0
80005c6: bf04 itt eq
80005c8: 4619 moveq r1, r3
80005ca: 4610 moveq r0, r2
80005cc: bd30 pop {r4, r5, pc}
80005ce: ea91 0f03 teq r1, r3
80005d2: bf1e ittt ne
80005d4: 2100 movne r1, #0
80005d6: 2000 movne r0, #0
80005d8: bd30 popne {r4, r5, pc}
80005da: ea5f 5c54 movs.w ip, r4, lsr #21
80005de: d105 bne.n 80005ec <__adddf3+0x230>
80005e0: 0040 lsls r0, r0, #1
80005e2: 4149 adcs r1, r1
80005e4: bf28 it cs
80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80005ea: bd30 pop {r4, r5, pc}
80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80005f0: bf3c itt cc
80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80005f6: bd30 popcc {r4, r5, pc}
80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000604: f04f 0000 mov.w r0, #0
8000608: bd30 pop {r4, r5, pc}
800060a: ea7f 5c64 mvns.w ip, r4, asr #21
800060e: bf1a itte ne
8000610: 4619 movne r1, r3
8000612: 4610 movne r0, r2
8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000618: bf1c itt ne
800061a: 460b movne r3, r1
800061c: 4602 movne r2, r0
800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000622: bf06 itte eq
8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12
8000628: ea91 0f03 teqeq r1, r3
800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000630: bd30 pop {r4, r5, pc}
8000632: bf00 nop
08000634 <__aeabi_ui2d>:
8000634: f090 0f00 teq r0, #0
8000638: bf04 itt eq
800063a: 2100 moveq r1, #0
800063c: 4770 bxeq lr
800063e: b530 push {r4, r5, lr}
8000640: f44f 6480 mov.w r4, #1024 @ 0x400
8000644: f104 0432 add.w r4, r4, #50 @ 0x32
8000648: f04f 0500 mov.w r5, #0
800064c: f04f 0100 mov.w r1, #0
8000650: e750 b.n 80004f4 <__adddf3+0x138>
8000652: bf00 nop
08000654 <__aeabi_i2d>:
8000654: f090 0f00 teq r0, #0
8000658: bf04 itt eq
800065a: 2100 moveq r1, #0
800065c: 4770 bxeq lr
800065e: b530 push {r4, r5, lr}
8000660: f44f 6480 mov.w r4, #1024 @ 0x400
8000664: f104 0432 add.w r4, r4, #50 @ 0x32
8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800066c: bf48 it mi
800066e: 4240 negmi r0, r0
8000670: f04f 0100 mov.w r1, #0
8000674: e73e b.n 80004f4 <__adddf3+0x138>
8000676: bf00 nop
08000678 <__aeabi_f2d>:
8000678: 0042 lsls r2, r0, #1
800067a: ea4f 01e2 mov.w r1, r2, asr #3
800067e: ea4f 0131 mov.w r1, r1, rrx
8000682: ea4f 7002 mov.w r0, r2, lsl #28
8000686: bf1f itttt ne
8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000694: 4770 bxne lr
8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800069a: bf08 it eq
800069c: 4770 bxeq lr
800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000
80006a2: bf04 itt eq
80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
80006a8: 4770 bxeq lr
80006aa: b530 push {r4, r5, lr}
80006ac: f44f 7460 mov.w r4, #896 @ 0x380
80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006b8: e71c b.n 80004f4 <__adddf3+0x138>
80006ba: bf00 nop
080006bc <__aeabi_ul2d>:
80006bc: ea50 0201 orrs.w r2, r0, r1
80006c0: bf08 it eq
80006c2: 4770 bxeq lr
80006c4: b530 push {r4, r5, lr}
80006c6: f04f 0500 mov.w r5, #0
80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16>
080006cc <__aeabi_l2d>:
80006cc: ea50 0201 orrs.w r2, r0, r1
80006d0: bf08 it eq
80006d2: 4770 bxeq lr
80006d4: b530 push {r4, r5, lr}
80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16>
80006dc: 4240 negs r0, r0
80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1
80006e2: f44f 6480 mov.w r4, #1024 @ 0x400
80006e6: f104 0432 add.w r4, r4, #50 @ 0x32
80006ea: ea5f 5c91 movs.w ip, r1, lsr #22
80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6>
80006f2: f04f 0203 mov.w r2, #3
80006f6: ea5f 0cdc movs.w ip, ip, lsr #3
80006fa: bf18 it ne
80006fc: 3203 addne r2, #3
80006fe: ea5f 0cdc movs.w ip, ip, lsr #3
8000702: bf18 it ne
8000704: 3203 addne r2, #3
8000706: eb02 02dc add.w r2, r2, ip, lsr #3
800070a: f1c2 0320 rsb r3, r2, #32
800070e: fa00 fc03 lsl.w ip, r0, r3
8000712: fa20 f002 lsr.w r0, r0, r2
8000716: fa01 fe03 lsl.w lr, r1, r3
800071a: ea40 000e orr.w r0, r0, lr
800071e: fa21 f102 lsr.w r1, r1, r2
8000722: 4414 add r4, r2
8000724: e6bd b.n 80004a2 <__adddf3+0xe6>
8000726: bf00 nop
08000728 <__gedf2>:
8000728: f04f 3cff mov.w ip, #4294967295
800072c: e006 b.n 800073c <__cmpdf2+0x4>
800072e: bf00 nop
08000730 <__ledf2>:
8000730: f04f 0c01 mov.w ip, #1
8000734: e002 b.n 800073c <__cmpdf2+0x4>
8000736: bf00 nop
08000738 <__cmpdf2>:
8000738: f04f 0c01 mov.w ip, #1
800073c: f84d cd04 str.w ip, [sp, #-4]!
8000740: ea4f 0c41 mov.w ip, r1, lsl #1
8000744: ea7f 5c6c mvns.w ip, ip, asr #21
8000748: ea4f 0c43 mov.w ip, r3, lsl #1
800074c: bf18 it ne
800074e: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000752: d01b beq.n 800078c <__cmpdf2+0x54>
8000754: b001 add sp, #4
8000756: ea50 0c41 orrs.w ip, r0, r1, lsl #1
800075a: bf0c ite eq
800075c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000760: ea91 0f03 teqne r1, r3
8000764: bf02 ittt eq
8000766: ea90 0f02 teqeq r0, r2
800076a: 2000 moveq r0, #0
800076c: 4770 bxeq lr
800076e: f110 0f00 cmn.w r0, #0
8000772: ea91 0f03 teq r1, r3
8000776: bf58 it pl
8000778: 4299 cmppl r1, r3
800077a: bf08 it eq
800077c: 4290 cmpeq r0, r2
800077e: bf2c ite cs
8000780: 17d8 asrcs r0, r3, #31
8000782: ea6f 70e3 mvncc.w r0, r3, asr #31
8000786: f040 0001 orr.w r0, r0, #1
800078a: 4770 bx lr
800078c: ea4f 0c41 mov.w ip, r1, lsl #1
8000790: ea7f 5c6c mvns.w ip, ip, asr #21
8000794: d102 bne.n 800079c <__cmpdf2+0x64>
8000796: ea50 3c01 orrs.w ip, r0, r1, lsl #12
800079a: d107 bne.n 80007ac <__cmpdf2+0x74>
800079c: ea4f 0c43 mov.w ip, r3, lsl #1
80007a0: ea7f 5c6c mvns.w ip, ip, asr #21
80007a4: d1d6 bne.n 8000754 <__cmpdf2+0x1c>
80007a6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
80007aa: d0d3 beq.n 8000754 <__cmpdf2+0x1c>
80007ac: f85d 0b04 ldr.w r0, [sp], #4
80007b0: 4770 bx lr
80007b2: bf00 nop
080007b4 <__aeabi_cdrcmple>:
80007b4: 4684 mov ip, r0
80007b6: 4610 mov r0, r2
80007b8: 4662 mov r2, ip
80007ba: 468c mov ip, r1
80007bc: 4619 mov r1, r3
80007be: 4663 mov r3, ip
80007c0: e000 b.n 80007c4 <__aeabi_cdcmpeq>
80007c2: bf00 nop
080007c4 <__aeabi_cdcmpeq>:
80007c4: b501 push {r0, lr}
80007c6: f7ff ffb7 bl 8000738 <__cmpdf2>
80007ca: 2800 cmp r0, #0
80007cc: bf48 it mi
80007ce: f110 0f00 cmnmi.w r0, #0
80007d2: bd01 pop {r0, pc}
080007d4 <__aeabi_dcmpeq>:
80007d4: f84d ed08 str.w lr, [sp, #-8]!
80007d8: f7ff fff4 bl 80007c4 <__aeabi_cdcmpeq>
80007dc: bf0c ite eq
80007de: 2001 moveq r0, #1
80007e0: 2000 movne r0, #0
80007e2: f85d fb08 ldr.w pc, [sp], #8
80007e6: bf00 nop
080007e8 <__aeabi_dcmplt>:
80007e8: f84d ed08 str.w lr, [sp, #-8]!
80007ec: f7ff ffea bl 80007c4 <__aeabi_cdcmpeq>
80007f0: bf34 ite cc
80007f2: 2001 movcc r0, #1
80007f4: 2000 movcs r0, #0
80007f6: f85d fb08 ldr.w pc, [sp], #8
80007fa: bf00 nop
080007fc <__aeabi_dcmple>:
80007fc: f84d ed08 str.w lr, [sp, #-8]!
8000800: f7ff ffe0 bl 80007c4 <__aeabi_cdcmpeq>
8000804: bf94 ite ls
8000806: 2001 movls r0, #1
8000808: 2000 movhi r0, #0
800080a: f85d fb08 ldr.w pc, [sp], #8
800080e: bf00 nop
08000810 <__aeabi_dcmpge>:
8000810: f84d ed08 str.w lr, [sp, #-8]!
8000814: f7ff ffce bl 80007b4 <__aeabi_cdrcmple>
8000818: bf94 ite ls
800081a: 2001 movls r0, #1
800081c: 2000 movhi r0, #0
800081e: f85d fb08 ldr.w pc, [sp], #8
8000822: bf00 nop
08000824 <__aeabi_dcmpgt>:
8000824: f84d ed08 str.w lr, [sp, #-8]!
8000828: f7ff ffc4 bl 80007b4 <__aeabi_cdrcmple>
800082c: bf34 ite cc
800082e: 2001 movcc r0, #1
8000830: 2000 movcs r0, #0
8000832: f85d fb08 ldr.w pc, [sp], #8
8000836: bf00 nop
08000838 <__aeabi_d2iz>:
8000838: ea4f 0241 mov.w r2, r1, lsl #1
800083c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000840: d215 bcs.n 800086e <__aeabi_d2iz+0x36>
8000842: d511 bpl.n 8000868 <__aeabi_d2iz+0x30>
8000844: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000848: ebb3 5262 subs.w r2, r3, r2, asr #21
800084c: d912 bls.n 8000874 <__aeabi_d2iz+0x3c>
800084e: ea4f 23c1 mov.w r3, r1, lsl #11
8000852: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000856: ea43 5350 orr.w r3, r3, r0, lsr #21
800085a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
800085e: fa23 f002 lsr.w r0, r3, r2
8000862: bf18 it ne
8000864: 4240 negne r0, r0
8000866: 4770 bx lr
8000868: f04f 0000 mov.w r0, #0
800086c: 4770 bx lr
800086e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000872: d105 bne.n 8000880 <__aeabi_d2iz+0x48>
8000874: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000878: bf08 it eq
800087a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
800087e: 4770 bx lr
8000880: f04f 0000 mov.w r0, #0
8000884: 4770 bx lr
8000886: bf00 nop
08000888 <__aeabi_frsub>:
8000888: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
800088c: e002 b.n 8000894 <__addsf3>
800088e: bf00 nop
08000890 <__aeabi_fsub>:
8000890: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
08000894 <__addsf3>:
8000894: 0042 lsls r2, r0, #1
8000896: bf1f itttt ne
8000898: ea5f 0341 movsne.w r3, r1, lsl #1
800089c: ea92 0f03 teqne r2, r3
80008a0: ea7f 6c22 mvnsne.w ip, r2, asr #24
80008a4: ea7f 6c23 mvnsne.w ip, r3, asr #24
80008a8: d06a beq.n 8000980 <__addsf3+0xec>
80008aa: ea4f 6212 mov.w r2, r2, lsr #24
80008ae: ebd2 6313 rsbs r3, r2, r3, lsr #24
80008b2: bfc1 itttt gt
80008b4: 18d2 addgt r2, r2, r3
80008b6: 4041 eorgt r1, r0
80008b8: 4048 eorgt r0, r1
80008ba: 4041 eorgt r1, r0
80008bc: bfb8 it lt
80008be: 425b neglt r3, r3
80008c0: 2b19 cmp r3, #25
80008c2: bf88 it hi
80008c4: 4770 bxhi lr
80008c6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
80008ca: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80008ce: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
80008d2: bf18 it ne
80008d4: 4240 negne r0, r0
80008d6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80008da: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
80008de: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
80008e2: bf18 it ne
80008e4: 4249 negne r1, r1
80008e6: ea92 0f03 teq r2, r3
80008ea: d03f beq.n 800096c <__addsf3+0xd8>
80008ec: f1a2 0201 sub.w r2, r2, #1
80008f0: fa41 fc03 asr.w ip, r1, r3
80008f4: eb10 000c adds.w r0, r0, ip
80008f8: f1c3 0320 rsb r3, r3, #32
80008fc: fa01 f103 lsl.w r1, r1, r3
8000900: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
8000904: d502 bpl.n 800090c <__addsf3+0x78>
8000906: 4249 negs r1, r1
8000908: eb60 0040 sbc.w r0, r0, r0, lsl #1
800090c: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
8000910: d313 bcc.n 800093a <__addsf3+0xa6>
8000912: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
8000916: d306 bcc.n 8000926 <__addsf3+0x92>
8000918: 0840 lsrs r0, r0, #1
800091a: ea4f 0131 mov.w r1, r1, rrx
800091e: f102 0201 add.w r2, r2, #1
8000922: 2afe cmp r2, #254 @ 0xfe
8000924: d251 bcs.n 80009ca <__addsf3+0x136>
8000926: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
800092a: eb40 50c2 adc.w r0, r0, r2, lsl #23
800092e: bf08 it eq
8000930: f020 0001 biceq.w r0, r0, #1
8000934: ea40 0003 orr.w r0, r0, r3
8000938: 4770 bx lr
800093a: 0049 lsls r1, r1, #1
800093c: eb40 0000 adc.w r0, r0, r0
8000940: 3a01 subs r2, #1
8000942: bf28 it cs
8000944: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
8000948: d2ed bcs.n 8000926 <__addsf3+0x92>
800094a: fab0 fc80 clz ip, r0
800094e: f1ac 0c08 sub.w ip, ip, #8
8000952: ebb2 020c subs.w r2, r2, ip
8000956: fa00 f00c lsl.w r0, r0, ip
800095a: bfaa itet ge
800095c: eb00 50c2 addge.w r0, r0, r2, lsl #23
8000960: 4252 neglt r2, r2
8000962: 4318 orrge r0, r3
8000964: bfbc itt lt
8000966: 40d0 lsrlt r0, r2
8000968: 4318 orrlt r0, r3
800096a: 4770 bx lr
800096c: f092 0f00 teq r2, #0
8000970: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
8000974: bf06 itte eq
8000976: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
800097a: 3201 addeq r2, #1
800097c: 3b01 subne r3, #1
800097e: e7b5 b.n 80008ec <__addsf3+0x58>
8000980: ea4f 0341 mov.w r3, r1, lsl #1
8000984: ea7f 6c22 mvns.w ip, r2, asr #24
8000988: bf18 it ne
800098a: ea7f 6c23 mvnsne.w ip, r3, asr #24
800098e: d021 beq.n 80009d4 <__addsf3+0x140>
8000990: ea92 0f03 teq r2, r3
8000994: d004 beq.n 80009a0 <__addsf3+0x10c>
8000996: f092 0f00 teq r2, #0
800099a: bf08 it eq
800099c: 4608 moveq r0, r1
800099e: 4770 bx lr
80009a0: ea90 0f01 teq r0, r1
80009a4: bf1c itt ne
80009a6: 2000 movne r0, #0
80009a8: 4770 bxne lr
80009aa: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
80009ae: d104 bne.n 80009ba <__addsf3+0x126>
80009b0: 0040 lsls r0, r0, #1
80009b2: bf28 it cs
80009b4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
80009b8: 4770 bx lr
80009ba: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
80009be: bf3c itt cc
80009c0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
80009c4: 4770 bxcc lr
80009c6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
80009ca: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
80009ce: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80009d2: 4770 bx lr
80009d4: ea7f 6222 mvns.w r2, r2, asr #24
80009d8: bf16 itet ne
80009da: 4608 movne r0, r1
80009dc: ea7f 6323 mvnseq.w r3, r3, asr #24
80009e0: 4601 movne r1, r0
80009e2: 0242 lsls r2, r0, #9
80009e4: bf06 itte eq
80009e6: ea5f 2341 movseq.w r3, r1, lsl #9
80009ea: ea90 0f01 teqeq r0, r1
80009ee: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
80009f2: 4770 bx lr
080009f4 <__aeabi_ui2f>:
80009f4: f04f 0300 mov.w r3, #0
80009f8: e004 b.n 8000a04 <__aeabi_i2f+0x8>
80009fa: bf00 nop
080009fc <__aeabi_i2f>:
80009fc: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
8000a00: bf48 it mi
8000a02: 4240 negmi r0, r0
8000a04: ea5f 0c00 movs.w ip, r0
8000a08: bf08 it eq
8000a0a: 4770 bxeq lr
8000a0c: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
8000a10: 4601 mov r1, r0
8000a12: f04f 0000 mov.w r0, #0
8000a16: e01c b.n 8000a52 <__aeabi_l2f+0x2a>
08000a18 <__aeabi_ul2f>:
8000a18: ea50 0201 orrs.w r2, r0, r1
8000a1c: bf08 it eq
8000a1e: 4770 bxeq lr
8000a20: f04f 0300 mov.w r3, #0
8000a24: e00a b.n 8000a3c <__aeabi_l2f+0x14>
8000a26: bf00 nop
08000a28 <__aeabi_l2f>:
8000a28: ea50 0201 orrs.w r2, r0, r1
8000a2c: bf08 it eq
8000a2e: 4770 bxeq lr
8000a30: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
8000a34: d502 bpl.n 8000a3c <__aeabi_l2f+0x14>
8000a36: 4240 negs r0, r0
8000a38: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000a3c: ea5f 0c01 movs.w ip, r1
8000a40: bf02 ittt eq
8000a42: 4684 moveq ip, r0
8000a44: 4601 moveq r1, r0
8000a46: 2000 moveq r0, #0
8000a48: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
8000a4c: bf08 it eq
8000a4e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
8000a52: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
8000a56: fabc f28c clz r2, ip
8000a5a: 3a08 subs r2, #8
8000a5c: eba3 53c2 sub.w r3, r3, r2, lsl #23
8000a60: db10 blt.n 8000a84 <__aeabi_l2f+0x5c>
8000a62: fa01 fc02 lsl.w ip, r1, r2
8000a66: 4463 add r3, ip
8000a68: fa00 fc02 lsl.w ip, r0, r2
8000a6c: f1c2 0220 rsb r2, r2, #32
8000a70: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000a74: fa20 f202 lsr.w r2, r0, r2
8000a78: eb43 0002 adc.w r0, r3, r2
8000a7c: bf08 it eq
8000a7e: f020 0001 biceq.w r0, r0, #1
8000a82: 4770 bx lr
8000a84: f102 0220 add.w r2, r2, #32
8000a88: fa01 fc02 lsl.w ip, r1, r2
8000a8c: f1c2 0220 rsb r2, r2, #32
8000a90: ea50 004c orrs.w r0, r0, ip, lsl #1
8000a94: fa21 f202 lsr.w r2, r1, r2
8000a98: eb43 0002 adc.w r0, r3, r2
8000a9c: bf08 it eq
8000a9e: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000aa2: 4770 bx lr
08000aa4 <__aeabi_fmul>:
8000aa4: f04f 0cff mov.w ip, #255 @ 0xff
8000aa8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000aac: bf1e ittt ne
8000aae: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000ab2: ea92 0f0c teqne r2, ip
8000ab6: ea93 0f0c teqne r3, ip
8000aba: d06f beq.n 8000b9c <__aeabi_fmul+0xf8>
8000abc: 441a add r2, r3
8000abe: ea80 0c01 eor.w ip, r0, r1
8000ac2: 0240 lsls r0, r0, #9
8000ac4: bf18 it ne
8000ac6: ea5f 2141 movsne.w r1, r1, lsl #9
8000aca: d01e beq.n 8000b0a <__aeabi_fmul+0x66>
8000acc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000ad0: ea43 1050 orr.w r0, r3, r0, lsr #5
8000ad4: ea43 1151 orr.w r1, r3, r1, lsr #5
8000ad8: fba0 3101 umull r3, r1, r0, r1
8000adc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000ae0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8000ae4: bf3e ittt cc
8000ae6: 0049 lslcc r1, r1, #1
8000ae8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
8000aec: 005b lslcc r3, r3, #1
8000aee: ea40 0001 orr.w r0, r0, r1
8000af2: f162 027f sbc.w r2, r2, #127 @ 0x7f
8000af6: 2afd cmp r2, #253 @ 0xfd
8000af8: d81d bhi.n 8000b36 <__aeabi_fmul+0x92>
8000afa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8000afe: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000b02: bf08 it eq
8000b04: f020 0001 biceq.w r0, r0, #1
8000b08: 4770 bx lr
8000b0a: f090 0f00 teq r0, #0
8000b0e: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000b12: bf08 it eq
8000b14: 0249 lsleq r1, r1, #9
8000b16: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000b1a: ea40 2051 orr.w r0, r0, r1, lsr #9
8000b1e: 3a7f subs r2, #127 @ 0x7f
8000b20: bfc2 ittt gt
8000b22: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000b26: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000b2a: 4770 bxgt lr
8000b2c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000b30: f04f 0300 mov.w r3, #0
8000b34: 3a01 subs r2, #1
8000b36: dc5d bgt.n 8000bf4 <__aeabi_fmul+0x150>
8000b38: f112 0f19 cmn.w r2, #25
8000b3c: bfdc itt le
8000b3e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
8000b42: 4770 bxle lr
8000b44: f1c2 0200 rsb r2, r2, #0
8000b48: 0041 lsls r1, r0, #1
8000b4a: fa21 f102 lsr.w r1, r1, r2
8000b4e: f1c2 0220 rsb r2, r2, #32
8000b52: fa00 fc02 lsl.w ip, r0, r2
8000b56: ea5f 0031 movs.w r0, r1, rrx
8000b5a: f140 0000 adc.w r0, r0, #0
8000b5e: ea53 034c orrs.w r3, r3, ip, lsl #1
8000b62: bf08 it eq
8000b64: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000b68: 4770 bx lr
8000b6a: f092 0f00 teq r2, #0
8000b6e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000b72: bf02 ittt eq
8000b74: 0040 lsleq r0, r0, #1
8000b76: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000b7a: 3a01 subeq r2, #1
8000b7c: d0f9 beq.n 8000b72 <__aeabi_fmul+0xce>
8000b7e: ea40 000c orr.w r0, r0, ip
8000b82: f093 0f00 teq r3, #0
8000b86: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000b8a: bf02 ittt eq
8000b8c: 0049 lsleq r1, r1, #1
8000b8e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000b92: 3b01 subeq r3, #1
8000b94: d0f9 beq.n 8000b8a <__aeabi_fmul+0xe6>
8000b96: ea41 010c orr.w r1, r1, ip
8000b9a: e78f b.n 8000abc <__aeabi_fmul+0x18>
8000b9c: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000ba0: ea92 0f0c teq r2, ip
8000ba4: bf18 it ne
8000ba6: ea93 0f0c teqne r3, ip
8000baa: d00a beq.n 8000bc2 <__aeabi_fmul+0x11e>
8000bac: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000bb0: bf18 it ne
8000bb2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000bb6: d1d8 bne.n 8000b6a <__aeabi_fmul+0xc6>
8000bb8: ea80 0001 eor.w r0, r0, r1
8000bbc: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bc0: 4770 bx lr
8000bc2: f090 0f00 teq r0, #0
8000bc6: bf17 itett ne
8000bc8: f090 4f00 teqne r0, #2147483648 @ 0x80000000
8000bcc: 4608 moveq r0, r1
8000bce: f091 0f00 teqne r1, #0
8000bd2: f091 4f00 teqne r1, #2147483648 @ 0x80000000
8000bd6: d014 beq.n 8000c02 <__aeabi_fmul+0x15e>
8000bd8: ea92 0f0c teq r2, ip
8000bdc: d101 bne.n 8000be2 <__aeabi_fmul+0x13e>
8000bde: 0242 lsls r2, r0, #9
8000be0: d10f bne.n 8000c02 <__aeabi_fmul+0x15e>
8000be2: ea93 0f0c teq r3, ip
8000be6: d103 bne.n 8000bf0 <__aeabi_fmul+0x14c>
8000be8: 024b lsls r3, r1, #9
8000bea: bf18 it ne
8000bec: 4608 movne r0, r1
8000bee: d108 bne.n 8000c02 <__aeabi_fmul+0x15e>
8000bf0: ea80 0001 eor.w r0, r0, r1
8000bf4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bf8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000bfc: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c00: 4770 bx lr
8000c02: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000c06: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
8000c0a: 4770 bx lr
08000c0c <__aeabi_fdiv>:
8000c0c: f04f 0cff mov.w ip, #255 @ 0xff
8000c10: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000c14: bf1e ittt ne
8000c16: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000c1a: ea92 0f0c teqne r2, ip
8000c1e: ea93 0f0c teqne r3, ip
8000c22: d069 beq.n 8000cf8 <__aeabi_fdiv+0xec>
8000c24: eba2 0203 sub.w r2, r2, r3
8000c28: ea80 0c01 eor.w ip, r0, r1
8000c2c: 0249 lsls r1, r1, #9
8000c2e: ea4f 2040 mov.w r0, r0, lsl #9
8000c32: d037 beq.n 8000ca4 <__aeabi_fdiv+0x98>
8000c34: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8000c38: ea43 1111 orr.w r1, r3, r1, lsr #4
8000c3c: ea43 1310 orr.w r3, r3, r0, lsr #4
8000c40: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000c44: 428b cmp r3, r1
8000c46: bf38 it cc
8000c48: 005b lslcc r3, r3, #1
8000c4a: f142 027d adc.w r2, r2, #125 @ 0x7d
8000c4e: f44f 0c00 mov.w ip, #8388608 @ 0x800000
8000c52: 428b cmp r3, r1
8000c54: bf24 itt cs
8000c56: 1a5b subcs r3, r3, r1
8000c58: ea40 000c orrcs.w r0, r0, ip
8000c5c: ebb3 0f51 cmp.w r3, r1, lsr #1
8000c60: bf24 itt cs
8000c62: eba3 0351 subcs.w r3, r3, r1, lsr #1
8000c66: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000c6a: ebb3 0f91 cmp.w r3, r1, lsr #2
8000c6e: bf24 itt cs
8000c70: eba3 0391 subcs.w r3, r3, r1, lsr #2
8000c74: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000c78: ebb3 0fd1 cmp.w r3, r1, lsr #3
8000c7c: bf24 itt cs
8000c7e: eba3 03d1 subcs.w r3, r3, r1, lsr #3
8000c82: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000c86: 011b lsls r3, r3, #4
8000c88: bf18 it ne
8000c8a: ea5f 1c1c movsne.w ip, ip, lsr #4
8000c8e: d1e0 bne.n 8000c52 <__aeabi_fdiv+0x46>
8000c90: 2afd cmp r2, #253 @ 0xfd
8000c92: f63f af50 bhi.w 8000b36 <__aeabi_fmul+0x92>
8000c96: 428b cmp r3, r1
8000c98: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000c9c: bf08 it eq
8000c9e: f020 0001 biceq.w r0, r0, #1
8000ca2: 4770 bx lr
8000ca4: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000ca8: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000cac: 327f adds r2, #127 @ 0x7f
8000cae: bfc2 ittt gt
8000cb0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000cb4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000cb8: 4770 bxgt lr
8000cba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000cbe: f04f 0300 mov.w r3, #0
8000cc2: 3a01 subs r2, #1
8000cc4: e737 b.n 8000b36 <__aeabi_fmul+0x92>
8000cc6: f092 0f00 teq r2, #0
8000cca: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000cce: bf02 ittt eq
8000cd0: 0040 lsleq r0, r0, #1
8000cd2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000cd6: 3a01 subeq r2, #1
8000cd8: d0f9 beq.n 8000cce <__aeabi_fdiv+0xc2>
8000cda: ea40 000c orr.w r0, r0, ip
8000cde: f093 0f00 teq r3, #0
8000ce2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000ce6: bf02 ittt eq
8000ce8: 0049 lsleq r1, r1, #1
8000cea: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000cee: 3b01 subeq r3, #1
8000cf0: d0f9 beq.n 8000ce6 <__aeabi_fdiv+0xda>
8000cf2: ea41 010c orr.w r1, r1, ip
8000cf6: e795 b.n 8000c24 <__aeabi_fdiv+0x18>
8000cf8: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000cfc: ea92 0f0c teq r2, ip
8000d00: d108 bne.n 8000d14 <__aeabi_fdiv+0x108>
8000d02: 0242 lsls r2, r0, #9
8000d04: f47f af7d bne.w 8000c02 <__aeabi_fmul+0x15e>
8000d08: ea93 0f0c teq r3, ip
8000d0c: f47f af70 bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d10: 4608 mov r0, r1
8000d12: e776 b.n 8000c02 <__aeabi_fmul+0x15e>
8000d14: ea93 0f0c teq r3, ip
8000d18: d104 bne.n 8000d24 <__aeabi_fdiv+0x118>
8000d1a: 024b lsls r3, r1, #9
8000d1c: f43f af4c beq.w 8000bb8 <__aeabi_fmul+0x114>
8000d20: 4608 mov r0, r1
8000d22: e76e b.n 8000c02 <__aeabi_fmul+0x15e>
8000d24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000d28: bf18 it ne
8000d2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000d2e: d1ca bne.n 8000cc6 <__aeabi_fdiv+0xba>
8000d30: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
8000d34: f47f af5c bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d38: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
8000d3c: f47f af3c bne.w 8000bb8 <__aeabi_fmul+0x114>
8000d40: e75f b.n 8000c02 <__aeabi_fmul+0x15e>
8000d42: bf00 nop
08000d44 <__gesf2>:
8000d44: f04f 3cff mov.w ip, #4294967295
8000d48: e006 b.n 8000d58 <__cmpsf2+0x4>
8000d4a: bf00 nop
08000d4c <__lesf2>:
8000d4c: f04f 0c01 mov.w ip, #1
8000d50: e002 b.n 8000d58 <__cmpsf2+0x4>
8000d52: bf00 nop
08000d54 <__cmpsf2>:
8000d54: f04f 0c01 mov.w ip, #1
8000d58: f84d cd04 str.w ip, [sp, #-4]!
8000d5c: ea4f 0240 mov.w r2, r0, lsl #1
8000d60: ea4f 0341 mov.w r3, r1, lsl #1
8000d64: ea7f 6c22 mvns.w ip, r2, asr #24
8000d68: bf18 it ne
8000d6a: ea7f 6c23 mvnsne.w ip, r3, asr #24
8000d6e: d011 beq.n 8000d94 <__cmpsf2+0x40>
8000d70: b001 add sp, #4
8000d72: ea52 0c53 orrs.w ip, r2, r3, lsr #1
8000d76: bf18 it ne
8000d78: ea90 0f01 teqne r0, r1
8000d7c: bf58 it pl
8000d7e: ebb2 0003 subspl.w r0, r2, r3
8000d82: bf88 it hi
8000d84: 17c8 asrhi r0, r1, #31
8000d86: bf38 it cc
8000d88: ea6f 70e1 mvncc.w r0, r1, asr #31
8000d8c: bf18 it ne
8000d8e: f040 0001 orrne.w r0, r0, #1
8000d92: 4770 bx lr
8000d94: ea7f 6c22 mvns.w ip, r2, asr #24
8000d98: d102 bne.n 8000da0 <__cmpsf2+0x4c>
8000d9a: ea5f 2c40 movs.w ip, r0, lsl #9
8000d9e: d105 bne.n 8000dac <__cmpsf2+0x58>
8000da0: ea7f 6c23 mvns.w ip, r3, asr #24
8000da4: d1e4 bne.n 8000d70 <__cmpsf2+0x1c>
8000da6: ea5f 2c41 movs.w ip, r1, lsl #9
8000daa: d0e1 beq.n 8000d70 <__cmpsf2+0x1c>
8000dac: f85d 0b04 ldr.w r0, [sp], #4
8000db0: 4770 bx lr
8000db2: bf00 nop
08000db4 <__aeabi_cfrcmple>:
8000db4: 4684 mov ip, r0
8000db6: 4608 mov r0, r1
8000db8: 4661 mov r1, ip
8000dba: e7ff b.n 8000dbc <__aeabi_cfcmpeq>
08000dbc <__aeabi_cfcmpeq>:
8000dbc: b50f push {r0, r1, r2, r3, lr}
8000dbe: f7ff ffc9 bl 8000d54 <__cmpsf2>
8000dc2: 2800 cmp r0, #0
8000dc4: bf48 it mi
8000dc6: f110 0f00 cmnmi.w r0, #0
8000dca: bd0f pop {r0, r1, r2, r3, pc}
08000dcc <__aeabi_fcmpeq>:
8000dcc: f84d ed08 str.w lr, [sp, #-8]!
8000dd0: f7ff fff4 bl 8000dbc <__aeabi_cfcmpeq>
8000dd4: bf0c ite eq
8000dd6: 2001 moveq r0, #1
8000dd8: 2000 movne r0, #0
8000dda: f85d fb08 ldr.w pc, [sp], #8
8000dde: bf00 nop
08000de0 <__aeabi_fcmplt>:
8000de0: f84d ed08 str.w lr, [sp, #-8]!
8000de4: f7ff ffea bl 8000dbc <__aeabi_cfcmpeq>
8000de8: bf34 ite cc
8000dea: 2001 movcc r0, #1
8000dec: 2000 movcs r0, #0
8000dee: f85d fb08 ldr.w pc, [sp], #8
8000df2: bf00 nop
08000df4 <__aeabi_fcmple>:
8000df4: f84d ed08 str.w lr, [sp, #-8]!
8000df8: f7ff ffe0 bl 8000dbc <__aeabi_cfcmpeq>
8000dfc: bf94 ite ls
8000dfe: 2001 movls r0, #1
8000e00: 2000 movhi r0, #0
8000e02: f85d fb08 ldr.w pc, [sp], #8
8000e06: bf00 nop
08000e08 <__aeabi_fcmpge>:
8000e08: f84d ed08 str.w lr, [sp, #-8]!
8000e0c: f7ff ffd2 bl 8000db4 <__aeabi_cfrcmple>
8000e10: bf94 ite ls
8000e12: 2001 movls r0, #1
8000e14: 2000 movhi r0, #0
8000e16: f85d fb08 ldr.w pc, [sp], #8
8000e1a: bf00 nop
08000e1c <__aeabi_fcmpgt>:
8000e1c: f84d ed08 str.w lr, [sp, #-8]!
8000e20: f7ff ffc8 bl 8000db4 <__aeabi_cfrcmple>
8000e24: bf34 ite cc
8000e26: 2001 movcc r0, #1
8000e28: 2000 movcs r0, #0
8000e2a: f85d fb08 ldr.w pc, [sp], #8
8000e2e: bf00 nop
08000e30 <__aeabi_fcmpun>:
8000e30: ea4f 0240 mov.w r2, r0, lsl #1
8000e34: ea4f 0341 mov.w r3, r1, lsl #1
8000e38: ea7f 6c22 mvns.w ip, r2, asr #24
8000e3c: d102 bne.n 8000e44 <__aeabi_fcmpun+0x14>
8000e3e: ea5f 2c40 movs.w ip, r0, lsl #9
8000e42: d108 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e44: ea7f 6c23 mvns.w ip, r3, asr #24
8000e48: d102 bne.n 8000e50 <__aeabi_fcmpun+0x20>
8000e4a: ea5f 2c41 movs.w ip, r1, lsl #9
8000e4e: d102 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e50: f04f 0000 mov.w r0, #0
8000e54: 4770 bx lr
8000e56: f04f 0001 mov.w r0, #1
8000e5a: 4770 bx lr
08000e5c <AD5934_SetRegisterValue>:
* @param numberOfBytes - Number of bytes to be written in the register
*
* @return None.
******************************************************************************/
void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
{
8000e5c: b580 push {r7, lr}
8000e5e: b086 sub sp, #24
8000e60: af02 add r7, sp, #8
8000e62: 4603 mov r3, r0
8000e64: 6039 str r1, [r7, #0]
8000e66: 71fb strb r3, [r7, #7]
8000e68: 4613 mov r3, r2
8000e6a: 71bb strb r3, [r7, #6]
uint8_t writeData[2] = {0, 0};
8000e6c: 2300 movs r3, #0
8000e6e: 81bb strh r3, [r7, #12]
HAL_StatusTypeDef status;
union Bytes2Long AD5934_reg;
AD5934_reg.number = registerValue;
8000e70: 683b ldr r3, [r7, #0]
8000e72: 60bb str r3, [r7, #8]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000e74: 2300 movs r3, #0
8000e76: 73fb strb r3, [r7, #15]
8000e78: e018 b.n 8000eac <AD5934_SetRegisterValue+0x50>
{
writeData[0] = registerAddress - i;
8000e7a: 79fa ldrb r2, [r7, #7]
8000e7c: 7bfb ldrb r3, [r7, #15]
8000e7e: 1ad3 subs r3, r2, r3
8000e80: b2db uxtb r3, r3
8000e82: 733b strb r3, [r7, #12]
writeData[1] = AD5934_reg.bytes[i];
8000e84: 7bfb ldrb r3, [r7, #15]
8000e86: 3310 adds r3, #16
8000e88: 443b add r3, r7
8000e8a: f813 3c08 ldrb.w r3, [r3, #-8]
8000e8e: 737b strb r3, [r7, #13]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000e90: f107 020c add.w r2, r7, #12
8000e94: 2305 movs r3, #5
8000e96: 9300 str r3, [sp, #0]
8000e98: 2302 movs r3, #2
8000e9a: 211a movs r1, #26
8000e9c: 4807 ldr r0, [pc, #28] @ (8000ebc <AD5934_SetRegisterValue+0x60>)
8000e9e: f002 fd73 bl 8003988 <HAL_I2C_Master_Transmit>
8000ea2: 4603 mov r3, r0
8000ea4: 73bb strb r3, [r7, #14]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ea6: 7bfb ldrb r3, [r7, #15]
8000ea8: 3301 adds r3, #1
8000eaa: 73fb strb r3, [r7, #15]
8000eac: 7bfa ldrb r2, [r7, #15]
8000eae: 79bb ldrb r3, [r7, #6]
8000eb0: 429a cmp r2, r3
8000eb2: d3e2 bcc.n 8000e7a <AD5934_SetRegisterValue+0x1e>
}
return;
8000eb4: bf00 nop
}
8000eb6: 3710 adds r7, #16
8000eb8: 46bd mov sp, r7
8000eba: bd80 pop {r7, pc}
8000ebc: 200006e0 .word 0x200006e0
08000ec0 <AD5934_GetRegisterValue>:
* @param numberOfBytes - Number of bytes to be read from the register.
*
* @return Register value.
******************************************************************************/
uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
{
8000ec0: b580 push {r7, lr}
8000ec2: b088 sub sp, #32
8000ec4: af02 add r7, sp, #8
8000ec6: 4603 mov r3, r0
8000ec8: 460a mov r2, r1
8000eca: 71fb strb r3, [r7, #7]
8000ecc: 4613 mov r3, r2
8000ece: 71bb strb r3, [r7, #6]
uint8_t readData[1] = {0};
8000ed0: 2300 movs r3, #0
8000ed2: 753b strb r3, [r7, #20]
uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
union Bytes2Long AD5934_reg;
HAL_StatusTypeDef status;
if(numberOfBytes > 4)
8000ed4: 79bb ldrb r3, [r7, #6]
8000ed6: 2b04 cmp r3, #4
8000ed8: d902 bls.n 8000ee0 <AD5934_GetRegisterValue+0x20>
return 0xFFFFFFFF; //Overflow
8000eda: f04f 33ff mov.w r3, #4294967295
8000ede: e031 b.n 8000f44 <AD5934_GetRegisterValue+0x84>
AD5934_reg.number = 0;
8000ee0: 2300 movs r3, #0
8000ee2: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ee4: 2300 movs r3, #0
8000ee6: 75fb strb r3, [r7, #23]
8000ee8: e027 b.n 8000f3a <AD5934_GetRegisterValue+0x7a>
{
writeData[0] = AD5934_ADDR_POINTER;
8000eea: 23b0 movs r3, #176 @ 0xb0
8000eec: 743b strb r3, [r7, #16]
writeData[1] = registerAddress - i;
8000eee: 79fa ldrb r2, [r7, #7]
8000ef0: 7dfb ldrb r3, [r7, #23]
8000ef2: 1ad3 subs r3, r2, r3
8000ef4: b2db uxtb r3, r3
8000ef6: 747b strb r3, [r7, #17]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000ef8: f107 0210 add.w r2, r7, #16
8000efc: 2305 movs r3, #5
8000efe: 9300 str r3, [sp, #0]
8000f00: 2302 movs r3, #2
8000f02: 211a movs r1, #26
8000f04: 4811 ldr r0, [pc, #68] @ (8000f4c <AD5934_GetRegisterValue+0x8c>)
8000f06: f002 fd3f bl 8003988 <HAL_I2C_Master_Transmit>
8000f0a: 4603 mov r3, r0
8000f0c: 75bb strb r3, [r7, #22]
//HAL_Delay(1);
readData[0] = 0;
8000f0e: 2300 movs r3, #0
8000f10: 753b strb r3, [r7, #20]
status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
8000f12: f107 0214 add.w r2, r7, #20
8000f16: 2305 movs r3, #5
8000f18: 9300 str r3, [sp, #0]
8000f1a: 2301 movs r3, #1
8000f1c: 211a movs r1, #26
8000f1e: 480b ldr r0, [pc, #44] @ (8000f4c <AD5934_GetRegisterValue+0x8c>)
8000f20: f002 fe30 bl 8003b84 <HAL_I2C_Master_Receive>
8000f24: 4603 mov r3, r0
8000f26: 75bb strb r3, [r7, #22]
AD5934_reg.bytes[i]=readData[0];
8000f28: 7dfb ldrb r3, [r7, #23]
8000f2a: 7d3a ldrb r2, [r7, #20]
8000f2c: 3318 adds r3, #24
8000f2e: 443b add r3, r7
8000f30: f803 2c0c strb.w r2, [r3, #-12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f34: 7dfb ldrb r3, [r7, #23]
8000f36: 3301 adds r3, #1
8000f38: 75fb strb r3, [r7, #23]
8000f3a: 7dfa ldrb r2, [r7, #23]
8000f3c: 79bb ldrb r3, [r7, #6]
8000f3e: 429a cmp r2, r3
8000f40: d3d3 bcc.n 8000eea <AD5934_GetRegisterValue+0x2a>
/*
AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048;
AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048;
*/
return AD5934_reg.number;
8000f42: 68fb ldr r3, [r7, #12]
}
8000f44: 4618 mov r0, r3
8000f46: 3718 adds r7, #24
8000f48: 46bd mov sp, r7
8000f4a: bd80 pop {r7, pc}
8000f4c: 200006e0 .word 0x200006e0
08000f50 <AD5934_Init>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_Init(void)
{
8000f50: b580 push {r7, lr}
8000f52: af00 add r7, sp, #0
/************ Config Sweep******************/
// Place AD5934 in reset
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
8000f54: 2201 movs r2, #1
8000f56: f44f 7180 mov.w r1, #256 @ 0x100
8000f5a: 2081 movs r0, #129 @ 0x81
8000f5c: f7ff ff7e bl 8000e5c <AD5934_SetRegisterValue>
// Configure starting frequency
AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_2K5HZ, 3);
8000f60: 2203 movs r2, #3
8000f62: 490a ldr r1, [pc, #40] @ (8000f8c <AD5934_Init+0x3c>)
8000f64: 2084 movs r0, #132 @ 0x84
8000f66: f7ff ff79 bl 8000e5c <AD5934_SetRegisterValue>
// Configure frequency increment step
AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
8000f6a: 2203 movs r2, #3
8000f6c: 2100 movs r1, #0
8000f6e: 2087 movs r0, #135 @ 0x87
8000f70: f7ff ff74 bl 8000e5c <AD5934_SetRegisterValue>
// Configure number of steps
AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
8000f74: 2202 movs r2, #2
8000f76: 2100 movs r1, #0
8000f78: 2089 movs r0, #137 @ 0x89
8000f7a: f7ff ff6f bl 8000e5c <AD5934_SetRegisterValue>
// Set 128 Settling Time
AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_64, 2);
8000f7e: 2202 movs r2, #2
8000f80: 2140 movs r1, #64 @ 0x40
8000f82: 208b movs r0, #139 @ 0x8b
8000f84: f7ff ff6a bl 8000e5c <AD5934_SetRegisterValue>
}
8000f88: bf00 nop
8000f8a: bd80 pop {r7, pc}
8000f8c: 0051eb86 .word 0x0051eb86
08000f90 <AD5934_RestartSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_RestartSweep(void)
{
8000f90: b580 push {r7, lr}
8000f92: af00 add r7, sp, #0
// Place AD5934 in standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000f94: 2201 movs r2, #1
8000f96: 21b5 movs r1, #181 @ 0xb5
8000f98: 2080 movs r0, #128 @ 0x80
8000f9a: f7ff ff5f bl 8000e5c <AD5934_SetRegisterValue>
// Initialize starting frequency, Start frequency sweep, standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000f9e: 2201 movs r2, #1
8000fa0: 2115 movs r1, #21
8000fa2: 2080 movs r0, #128 @ 0x80
8000fa4: f7ff ff5a bl 8000e5c <AD5934_SetRegisterValue>
// Disable Internal Reset State
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, AD5934_CONTROL_FUNCTION(AD5934_RESERVED), 1);
8000fa8: 2201 movs r2, #1
8000faa: 2180 movs r1, #128 @ 0x80
8000fac: 2081 movs r0, #129 @ 0x81
8000fae: f7ff ff55 bl 8000e5c <AD5934_SetRegisterValue>
// Configure Range Output, PGA gain andPlace AD5934 in sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000fb2: 2201 movs r2, #1
8000fb4: 2125 movs r1, #37 @ 0x25
8000fb6: 2080 movs r0, #128 @ 0x80
8000fb8: f7ff ff50 bl 8000e5c <AD5934_SetRegisterValue>
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
// Place AD5934 in standby (instead of power down)
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
}
8000fbc: bf00 nop
8000fbe: bd80 pop {r7, pc}
08000fc0 <AD5934_Repeat_Sweep>:
* @param None.
*
* @return none.
******************************************************************************/
void AD5934_Repeat_Sweep(void)
{
8000fc0: b580 push {r7, lr}
8000fc2: af00 add r7, sp, #0
// Repeat AD5934 Sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_REPEAT_FREQ) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000fc4: 2201 movs r2, #1
8000fc6: 2145 movs r1, #69 @ 0x45
8000fc8: 2080 movs r0, #128 @ 0x80
8000fca: f7ff ff47 bl 8000e5c <AD5934_SetRegisterValue>
}
8000fce: bf00 nop
8000fd0: bd80 pop {r7, pc}
08000fd2 <AD5934_StopSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_StopSweep(void)
{
8000fd2: b580 push {r7, lr}
8000fd4: af00 add r7, sp, #0
// Power Down
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
// Place AD5934 in standby (instead of power down to save startup time)
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000fd6: 2201 movs r2, #1
8000fd8: 21b5 movs r1, #181 @ 0xb5
8000fda: 2080 movs r0, #128 @ 0x80
8000fdc: f7ff ff3e bl 8000e5c <AD5934_SetRegisterValue>
}
8000fe0: bf00 nop
8000fe2: bd80 pop {r7, pc}
08000fe4 <AD5934_GetMagnitude>:
* @param: none
*
* @return Magnitude (float).
******************************************************************************/
float AD5934_GetMagnitude(void)
{
8000fe4: b5b0 push {r4, r5, r7, lr}
8000fe6: b082 sub sp, #8
8000fe8: af00 add r7, sp, #0
// Get Real Data register
int16_t real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2)));
8000fea: 2102 movs r1, #2
8000fec: 2095 movs r0, #149 @ 0x95
8000fee: f7ff ff67 bl 8000ec0 <AD5934_GetRegisterValue>
8000ff2: 4603 mov r3, r0
8000ff4: 80fb strh r3, [r7, #6]
// Get Imaginary Data register
int16_t imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2)));
8000ff6: 2102 movs r1, #2
8000ff8: 2097 movs r0, #151 @ 0x97
8000ffa: f7ff ff61 bl 8000ec0 <AD5934_GetRegisterValue>
8000ffe: 4603 mov r3, r0
8001000: 80bb strh r3, [r7, #4]
// Calculate Magnitude using float function sqrtf
float magnitude = sqrtf(((float)real_value * (float)real_value) + ((float)imag_value * (float)imag_value));
8001002: f9b7 3006 ldrsh.w r3, [r7, #6]
8001006: 4618 mov r0, r3
8001008: f7ff fcf8 bl 80009fc <__aeabi_i2f>
800100c: 4604 mov r4, r0
800100e: f9b7 3006 ldrsh.w r3, [r7, #6]
8001012: 4618 mov r0, r3
8001014: f7ff fcf2 bl 80009fc <__aeabi_i2f>
8001018: 4603 mov r3, r0
800101a: 4619 mov r1, r3
800101c: 4620 mov r0, r4
800101e: f7ff fd41 bl 8000aa4 <__aeabi_fmul>
8001022: 4603 mov r3, r0
8001024: 461d mov r5, r3
8001026: f9b7 3004 ldrsh.w r3, [r7, #4]
800102a: 4618 mov r0, r3
800102c: f7ff fce6 bl 80009fc <__aeabi_i2f>
8001030: 4604 mov r4, r0
8001032: f9b7 3004 ldrsh.w r3, [r7, #4]
8001036: 4618 mov r0, r3
8001038: f7ff fce0 bl 80009fc <__aeabi_i2f>
800103c: 4603 mov r3, r0
800103e: 4619 mov r1, r3
8001040: 4620 mov r0, r4
8001042: f7ff fd2f bl 8000aa4 <__aeabi_fmul>
8001046: 4603 mov r3, r0
8001048: 4619 mov r1, r3
800104a: 4628 mov r0, r5
800104c: f7ff fc22 bl 8000894 <__addsf3>
8001050: 4603 mov r3, r0
8001052: 4618 mov r0, r3
8001054: f005 fa98 bl 8006588 <sqrtf>
8001058: 6038 str r0, [r7, #0]
// Return magnitude value
return (magnitude);
800105a: 683b ldr r3, [r7, #0]
}
800105c: 4618 mov r0, r3
800105e: 3708 adds r7, #8
8001060: 46bd mov sp, r7
8001062: bdb0 pop {r4, r5, r7, pc}
08001064 <AD5934_Process_System>:
return calibration_factor;
}
void AD5934_Process_System(void)
{
8001064: b580 push {r7, lr}
8001066: b082 sub sp, #8
8001068: af00 add r7, sp, #0
static uint32_t state_timer = 0;
uint8_t status = 0;
800106a: 2300 movs r3, #0
800106c: 71fb strb r3, [r7, #7]
switch (ad5934_state)
800106e: 4b79 ldr r3, [pc, #484] @ (8001254 <AD5934_Process_System+0x1f0>)
8001070: 781b ldrb r3, [r3, #0]
8001072: b2db uxtb r3, r3
8001074: 2b06 cmp r3, #6
8001076: f200 80e9 bhi.w 800124c <AD5934_Process_System+0x1e8>
800107a: a201 add r2, pc, #4 @ (adr r2, 8001080 <AD5934_Process_System+0x1c>)
800107c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001080: 0800109d .word 0x0800109d
8001084: 080010db .word 0x080010db
8001088: 08001103 .word 0x08001103
800108c: 08001123 .word 0x08001123
8001090: 0800117b .word 0x0800117b
8001094: 08001191 .word 0x08001191
8001098: 080010bd .word 0x080010bd
{
case AD5934_IDLE:
ADG715_Update(current_mux_channel); // Starts changing the mux channel
800109c: 4b6e ldr r3, [pc, #440] @ (8001258 <AD5934_Process_System+0x1f4>)
800109e: 781b ldrb r3, [r3, #0]
80010a0: 4618 mov r0, r3
80010a2: f000 fa85 bl 80015b0 <ADG715_Update>
is_new_channel = 1; // Forces first channel
80010a6: 4b6d ldr r3, [pc, #436] @ (800125c <AD5934_Process_System+0x1f8>)
80010a8: 2201 movs r2, #1
80010aa: 701a strb r2, [r3, #0]
state_timer = g_ms_counter;
80010ac: 4b6c ldr r3, [pc, #432] @ (8001260 <AD5934_Process_System+0x1fc>)
80010ae: 681b ldr r3, [r3, #0]
80010b0: 4a6c ldr r2, [pc, #432] @ (8001264 <AD5934_Process_System+0x200>)
80010b2: 6013 str r3, [r2, #0]
ad5934_state = AD5934_WAIT_MUX;
80010b4: 4b67 ldr r3, [pc, #412] @ (8001254 <AD5934_Process_System+0x1f0>)
80010b6: 2206 movs r2, #6
80010b8: 701a strb r2, [r3, #0]
break;
80010ba: e0c7 b.n 800124c <AD5934_Process_System+0x1e8>
case AD5934_WAIT_MUX:
if ((g_ms_counter - state_timer) >= AD5934_SYNC_MUX_SETTLING) // Wait until AD715 Mux switch stability
80010bc: 4b68 ldr r3, [pc, #416] @ (8001260 <AD5934_Process_System+0x1fc>)
80010be: 681a ldr r2, [r3, #0]
80010c0: 4b68 ldr r3, [pc, #416] @ (8001264 <AD5934_Process_System+0x200>)
80010c2: 681b ldr r3, [r3, #0]
80010c4: 1ad3 subs r3, r2, r3
80010c6: 2b04 cmp r3, #4
80010c8: f240 80bb bls.w 8001242 <AD5934_Process_System+0x1de>
{
sweep_count = 0;
80010cc: 4b66 ldr r3, [pc, #408] @ (8001268 <AD5934_Process_System+0x204>)
80010ce: 2200 movs r2, #0
80010d0: 701a strb r2, [r3, #0]
ad5934_state = AD5934_START_CONVERSION;
80010d2: 4b60 ldr r3, [pc, #384] @ (8001254 <AD5934_Process_System+0x1f0>)
80010d4: 2201 movs r2, #1
80010d6: 701a strb r2, [r3, #0]
}
break;
80010d8: e0b3 b.n 8001242 <AD5934_Process_System+0x1de>
case AD5934_START_CONVERSION:
state_timer = g_ms_counter; // Starts to count the Burst period for the sweeps
80010da: 4b61 ldr r3, [pc, #388] @ (8001260 <AD5934_Process_System+0x1fc>)
80010dc: 681b ldr r3, [r3, #0]
80010de: 4a61 ldr r2, [pc, #388] @ (8001264 <AD5934_Process_System+0x200>)
80010e0: 6013 str r3, [r2, #0]
/* DECISÃO DE COMANDO: Novo canal vs Leituras sucessivas */
if (is_new_channel) // Decision: Channel Switched or Next Sample in the Burst ?
80010e2: 4b5e ldr r3, [pc, #376] @ (800125c <AD5934_Process_System+0x1f8>)
80010e4: 781b ldrb r3, [r3, #0]
80010e6: 2b00 cmp r3, #0
80010e8: d005 beq.n 80010f6 <AD5934_Process_System+0x92>
{
AD5934_RestartSweep(); // Clean some AD5934 internal registers to Re-Start Sweep
80010ea: f7ff ff51 bl 8000f90 <AD5934_RestartSweep>
is_new_channel = 0; // Resets the flag to read the next Sample Burst
80010ee: 4b5b ldr r3, [pc, #364] @ (800125c <AD5934_Process_System+0x1f8>)
80010f0: 2200 movs r2, #0
80010f2: 701a strb r2, [r3, #0]
80010f4: e001 b.n 80010fa <AD5934_Process_System+0x96>
}
else
{
AD5934_Repeat_Sweep(); // Get Sample and just repeat reading
80010f6: f7ff ff63 bl 8000fc0 <AD5934_Repeat_Sweep>
}
ad5934_state = AD5934_WAIT_CONVERSION; // Next State
80010fa: 4b56 ldr r3, [pc, #344] @ (8001254 <AD5934_Process_System+0x1f0>)
80010fc: 2202 movs r2, #2
80010fe: 701a strb r2, [r3, #0]
break;
8001100: e0a4 b.n 800124c <AD5934_Process_System+0x1e8>
case AD5934_WAIT_CONVERSION:
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1); // Check if the current converion is ready in the AD5934
8001102: 2101 movs r1, #1
8001104: 208f movs r0, #143 @ 0x8f
8001106: f7ff fedb bl 8000ec0 <AD5934_GetRegisterValue>
800110a: 4603 mov r3, r0
800110c: 71fb strb r3, [r7, #7]
if ((status & AD5934_STATUS_DATA_VALID) != 0)
800110e: 79fb ldrb r3, [r7, #7]
8001110: f003 0302 and.w r3, r3, #2
8001114: 2b00 cmp r3, #0
8001116: f000 8096 beq.w 8001246 <AD5934_Process_System+0x1e2>
{
ad5934_state = AD5934_READ_DATA;
800111a: 4b4e ldr r3, [pc, #312] @ (8001254 <AD5934_Process_System+0x1f0>)
800111c: 2203 movs r2, #3
800111e: 701a strb r2, [r3, #0]
}
break;
8001120: e091 b.n 8001246 <AD5934_Process_System+0x1e2>
case AD5934_READ_DATA:
{
float magnitude = AD5934_GetMagnitude();
8001122: f7ff ff5f bl 8000fe4 <AD5934_GetMagnitude>
8001126: 6038 str r0, [r7, #0]
switch (current_mux_channel)
8001128: 4b4b ldr r3, [pc, #300] @ (8001258 <AD5934_Process_System+0x1f4>)
800112a: 781b ldrb r3, [r3, #0]
800112c: 2b02 cmp r3, #2
800112e: d00e beq.n 800114e <AD5934_Process_System+0xea>
8001130: 2b02 cmp r3, #2
8001132: dc10 bgt.n 8001156 <AD5934_Process_System+0xf2>
8001134: 2b00 cmp r3, #0
8001136: d002 beq.n 800113e <AD5934_Process_System+0xda>
8001138: 2b01 cmp r3, #1
800113a: d004 beq.n 8001146 <AD5934_Process_System+0xe2>
800113c: e00b b.n 8001156 <AD5934_Process_System+0xf2>
{
case AD5934_ID_RTD:
AD5934_RTD_NewSample(magnitude);
800113e: 6838 ldr r0, [r7, #0]
8001140: f000 f9ec bl 800151c <AD5934_RTD_NewSample>
break;
8001144: e007 b.n 8001156 <AD5934_Process_System+0xf2>
case AD5934_ID_EC:
AD5934_EC_NewSample(magnitude);
8001146: 6838 ldr r0, [r7, #0]
8001148: f000 f9f6 bl 8001538 <AD5934_EC_NewSample>
break;
800114c: e003 b.n 8001156 <AD5934_Process_System+0xf2>
case AD5934_ID_REF:
AD5934_Reference_NewSample(magnitude);
800114e: 6838 ldr r0, [r7, #0]
8001150: f000 fa00 bl 8001554 <AD5934_Reference_NewSample>
break;
8001154: bf00 nop
}
sweep_count++;
8001156: 4b44 ldr r3, [pc, #272] @ (8001268 <AD5934_Process_System+0x204>)
8001158: 781b ldrb r3, [r3, #0]
800115a: 3301 adds r3, #1
800115c: b2da uxtb r2, r3
800115e: 4b42 ldr r3, [pc, #264] @ (8001268 <AD5934_Process_System+0x204>)
8001160: 701a strb r2, [r3, #0]
if (sweep_count >= AD5934_BURST_SIZE) // Check if number of samples for the burst is complete
8001162: 4b41 ldr r3, [pc, #260] @ (8001268 <AD5934_Process_System+0x204>)
8001164: 781b ldrb r3, [r3, #0]
8001166: 2b06 cmp r3, #6
8001168: d903 bls.n 8001172 <AD5934_Process_System+0x10e>
{
ad5934_state = AD5934_SWITCH_MUX; // Next Re-Start Sweep
800116a: 4b3a ldr r3, [pc, #232] @ (8001254 <AD5934_Process_System+0x1f0>)
800116c: 2205 movs r2, #5
800116e: 701a strb r2, [r3, #0]
else
{
ad5934_state = AD5934_WAIT_NEXT_SWEEP; // Next Repeat Sweep
}
}
break;
8001170: e06c b.n 800124c <AD5934_Process_System+0x1e8>
ad5934_state = AD5934_WAIT_NEXT_SWEEP; // Next Repeat Sweep
8001172: 4b38 ldr r3, [pc, #224] @ (8001254 <AD5934_Process_System+0x1f0>)
8001174: 2204 movs r2, #4
8001176: 701a strb r2, [r3, #0]
break;
8001178: e068 b.n 800124c <AD5934_Process_System+0x1e8>
case AD5934_WAIT_NEXT_SWEEP:
if ((g_ms_counter - state_timer) >= AD5934_TIME_PER_SWEEP)
800117a: 4b39 ldr r3, [pc, #228] @ (8001260 <AD5934_Process_System+0x1fc>)
800117c: 681a ldr r2, [r3, #0]
800117e: 4b39 ldr r3, [pc, #228] @ (8001264 <AD5934_Process_System+0x200>)
8001180: 681b ldr r3, [r3, #0]
8001182: 1ad3 subs r3, r2, r3
8001184: 2b3b cmp r3, #59 @ 0x3b
8001186: d960 bls.n 800124a <AD5934_Process_System+0x1e6>
{
ad5934_state = AD5934_START_CONVERSION;
8001188: 4b32 ldr r3, [pc, #200] @ (8001254 <AD5934_Process_System+0x1f0>)
800118a: 2201 movs r2, #1
800118c: 701a strb r2, [r3, #0]
}
break;
800118e: e05c b.n 800124a <AD5934_Process_System+0x1e6>
case AD5934_SWITCH_MUX:
AD5934_StopSweep(); // Put AD5934 in Standby
8001190: f7ff ff1f bl 8000fd2 <AD5934_StopSweep>
current_mux_channel = (uint8_t)((current_mux_channel + 1) % 3); // Pointer to the next channel (Circular Buffer 0 to 2)
8001194: 4b30 ldr r3, [pc, #192] @ (8001258 <AD5934_Process_System+0x1f4>)
8001196: 781b ldrb r3, [r3, #0]
8001198: 1c5a adds r2, r3, #1
800119a: 4b34 ldr r3, [pc, #208] @ (800126c <AD5934_Process_System+0x208>)
800119c: fb83 3102 smull r3, r1, r3, r2
80011a0: 17d3 asrs r3, r2, #31
80011a2: 1ac9 subs r1, r1, r3
80011a4: 460b mov r3, r1
80011a6: 005b lsls r3, r3, #1
80011a8: 440b add r3, r1
80011aa: 1ad1 subs r1, r2, r3
80011ac: b2ca uxtb r2, r1
80011ae: 4b2a ldr r3, [pc, #168] @ (8001258 <AD5934_Process_System+0x1f4>)
80011b0: 701a strb r2, [r3, #0]
switch (current_mux_channel)
80011b2: 4b29 ldr r3, [pc, #164] @ (8001258 <AD5934_Process_System+0x1f4>)
80011b4: 781b ldrb r3, [r3, #0]
80011b6: 2b02 cmp r3, #2
80011b8: d024 beq.n 8001204 <AD5934_Process_System+0x1a0>
80011ba: 2b02 cmp r3, #2
80011bc: dc31 bgt.n 8001222 <AD5934_Process_System+0x1be>
80011be: 2b00 cmp r3, #0
80011c0: d002 beq.n 80011c8 <AD5934_Process_System+0x164>
80011c2: 2b01 cmp r3, #1
80011c4: d00f beq.n 80011e6 <AD5934_Process_System+0x182>
80011c6: e02c b.n 8001222 <AD5934_Process_System+0x1be>
{
case AD5934_ID_RTD:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
80011c8: 2180 movs r1, #128 @ 0x80
80011ca: 4829 ldr r0, [pc, #164] @ (8001270 <AD5934_Process_System+0x20c>)
80011cc: f002 fa50 bl 8003670 <HAL_GPIO_ReadPin>
80011d0: 4603 mov r3, r0
80011d2: 2b01 cmp r3, #1
80011d4: d103 bne.n 80011de <AD5934_Process_System+0x17a>
current_hw_mux_connection = AD5934_CH_RTD_LOW_GAIN; //PT100
80011d6: 4b27 ldr r3, [pc, #156] @ (8001274 <AD5934_Process_System+0x210>)
80011d8: 2209 movs r2, #9
80011da: 701a strb r2, [r3, #0]
else
current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
break;
80011dc: e021 b.n 8001222 <AD5934_Process_System+0x1be>
current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
80011de: 4b25 ldr r3, [pc, #148] @ (8001274 <AD5934_Process_System+0x210>)
80011e0: 220a movs r2, #10
80011e2: 701a strb r2, [r3, #0]
break;
80011e4: e01d b.n 8001222 <AD5934_Process_System+0x1be>
case AD5934_ID_EC:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // Hardware Setup: Gain Selection (PA6)
80011e6: 2140 movs r1, #64 @ 0x40
80011e8: 4821 ldr r0, [pc, #132] @ (8001270 <AD5934_Process_System+0x20c>)
80011ea: f002 fa41 bl 8003670 <HAL_GPIO_ReadPin>
80011ee: 4603 mov r3, r0
80011f0: 2b01 cmp r3, #1
80011f2: d103 bne.n 80011fc <AD5934_Process_System+0x198>
current_hw_mux_connection = AD5934_CH_EC_HIGH_GAIN;
80011f4: 4b1f ldr r3, [pc, #124] @ (8001274 <AD5934_Process_System+0x210>)
80011f6: 220e movs r2, #14
80011f8: 701a strb r2, [r3, #0]
else
current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
break;
80011fa: e012 b.n 8001222 <AD5934_Process_System+0x1be>
current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
80011fc: 4b1d ldr r3, [pc, #116] @ (8001274 <AD5934_Process_System+0x210>)
80011fe: 220d movs r2, #13
8001200: 701a strb r2, [r3, #0]
break;
8001202: e00e b.n 8001222 <AD5934_Process_System+0x1be>
case AD5934_ID_REF:
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
8001204: 2180 movs r1, #128 @ 0x80
8001206: 481a ldr r0, [pc, #104] @ (8001270 <AD5934_Process_System+0x20c>)
8001208: f002 fa32 bl 8003670 <HAL_GPIO_ReadPin>
800120c: 4603 mov r3, r0
800120e: 2b01 cmp r3, #1
8001210: d103 bne.n 800121a <AD5934_Process_System+0x1b6>
current_hw_mux_connection = AD5934_CH_REF100R_LOW_GAIN; // 100 Ohms Reference Resistor
8001212: 4b18 ldr r3, [pc, #96] @ (8001274 <AD5934_Process_System+0x210>)
8001214: 2200 movs r2, #0
8001216: 701a strb r2, [r3, #0]
else
current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
break;
8001218: e002 b.n 8001220 <AD5934_Process_System+0x1bc>
current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
800121a: 4b16 ldr r3, [pc, #88] @ (8001274 <AD5934_Process_System+0x210>)
800121c: 2204 movs r2, #4
800121e: 701a strb r2, [r3, #0]
break;
8001220: bf00 nop
}
ADG715_Update(current_hw_mux_connection); // Change the analog mux
8001222: 4b14 ldr r3, [pc, #80] @ (8001274 <AD5934_Process_System+0x210>)
8001224: 781b ldrb r3, [r3, #0]
8001226: 4618 mov r0, r3
8001228: f000 f9c2 bl 80015b0 <ADG715_Update>
is_new_channel = 1; // Channel Switched
800122c: 4b0b ldr r3, [pc, #44] @ (800125c <AD5934_Process_System+0x1f8>)
800122e: 2201 movs r2, #1
8001230: 701a strb r2, [r3, #0]
state_timer = g_ms_counter; // Reload timer to wait for stability
8001232: 4b0b ldr r3, [pc, #44] @ (8001260 <AD5934_Process_System+0x1fc>)
8001234: 681b ldr r3, [r3, #0]
8001236: 4a0b ldr r2, [pc, #44] @ (8001264 <AD5934_Process_System+0x200>)
8001238: 6013 str r3, [r2, #0]
ad5934_state = AD5934_WAIT_MUX; // Next State
800123a: 4b06 ldr r3, [pc, #24] @ (8001254 <AD5934_Process_System+0x1f0>)
800123c: 2206 movs r2, #6
800123e: 701a strb r2, [r3, #0]
break;
8001240: e004 b.n 800124c <AD5934_Process_System+0x1e8>
break;
8001242: bf00 nop
8001244: e002 b.n 800124c <AD5934_Process_System+0x1e8>
break;
8001246: bf00 nop
8001248: e000 b.n 800124c <AD5934_Process_System+0x1e8>
break;
800124a: bf00 nop
}
}
800124c: bf00 nop
800124e: 3708 adds r7, #8
8001250: 46bd mov sp, r7
8001252: bd80 pop {r7, pc}
8001254: 200000b0 .word 0x200000b0
8001258: 200000b8 .word 0x200000b8
800125c: 20000001 .word 0x20000001
8001260: 200000b4 .word 0x200000b4
8001264: 200001b8 .word 0x200001b8
8001268: 200000b9 .word 0x200000b9
800126c: 55555556 .word 0x55555556
8001270: 40010800 .word 0x40010800
8001274: 20000000 .word 0x20000000
08001278 <AD5934_Sort_Array>:
/**
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
* and it avoids depending on qsort/heap allocation.
**/
void AD5934_Sort_Array(float *v, uint8_t n)
{
8001278: b580 push {r7, lr}
800127a: b084 sub sp, #16
800127c: af00 add r7, sp, #0
800127e: 6078 str r0, [r7, #4]
8001280: 460b mov r3, r1
8001282: 70fb strb r3, [r7, #3]
for (uint8_t i = 1; i < n; i++)
8001284: 2301 movs r3, #1
8001286: 73fb strb r3, [r7, #15]
8001288: e039 b.n 80012fe <AD5934_Sort_Array+0x86>
{
float key = v[i];
800128a: 7bfb ldrb r3, [r7, #15]
800128c: 009b lsls r3, r3, #2
800128e: 687a ldr r2, [r7, #4]
8001290: 4413 add r3, r2
8001292: 681b ldr r3, [r3, #0]
8001294: 60bb str r3, [r7, #8]
int8_t j = (int8_t)i - 1;
8001296: 7bfb ldrb r3, [r7, #15]
8001298: 3b01 subs r3, #1
800129a: b2db uxtb r3, r3
800129c: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
800129e: e012 b.n 80012c6 <AD5934_Sort_Array+0x4e>
{
v[j + 1] = v[j];
80012a0: f997 300e ldrsb.w r3, [r7, #14]
80012a4: 009b lsls r3, r3, #2
80012a6: 687a ldr r2, [r7, #4]
80012a8: 441a add r2, r3
80012aa: f997 300e ldrsb.w r3, [r7, #14]
80012ae: 3301 adds r3, #1
80012b0: 009b lsls r3, r3, #2
80012b2: 6879 ldr r1, [r7, #4]
80012b4: 440b add r3, r1
80012b6: 6812 ldr r2, [r2, #0]
80012b8: 601a str r2, [r3, #0]
j--;
80012ba: f997 300e ldrsb.w r3, [r7, #14]
80012be: b2db uxtb r3, r3
80012c0: 3b01 subs r3, #1
80012c2: b2db uxtb r3, r3
80012c4: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
80012c6: f997 300e ldrsb.w r3, [r7, #14]
80012ca: 2b00 cmp r3, #0
80012cc: db0c blt.n 80012e8 <AD5934_Sort_Array+0x70>
80012ce: f997 300e ldrsb.w r3, [r7, #14]
80012d2: 009b lsls r3, r3, #2
80012d4: 687a ldr r2, [r7, #4]
80012d6: 4413 add r3, r2
80012d8: 681b ldr r3, [r3, #0]
80012da: 4619 mov r1, r3
80012dc: 68b8 ldr r0, [r7, #8]
80012de: f7ff fd7f bl 8000de0 <__aeabi_fcmplt>
80012e2: 4603 mov r3, r0
80012e4: 2b00 cmp r3, #0
80012e6: d1db bne.n 80012a0 <AD5934_Sort_Array+0x28>
}
v[j + 1] = key;
80012e8: f997 300e ldrsb.w r3, [r7, #14]
80012ec: 3301 adds r3, #1
80012ee: 009b lsls r3, r3, #2
80012f0: 687a ldr r2, [r7, #4]
80012f2: 4413 add r3, r2
80012f4: 68ba ldr r2, [r7, #8]
80012f6: 601a str r2, [r3, #0]
for (uint8_t i = 1; i < n; i++)
80012f8: 7bfb ldrb r3, [r7, #15]
80012fa: 3301 adds r3, #1
80012fc: 73fb strb r3, [r7, #15]
80012fe: 7bfa ldrb r2, [r7, #15]
8001300: 78fb ldrb r3, [r7, #3]
8001302: 429a cmp r2, r3
8001304: d3c1 bcc.n 800128a <AD5934_Sort_Array+0x12>
}
}
8001306: bf00 nop
8001308: bf00 nop
800130a: 3710 adds r7, #16
800130c: 46bd mov sp, r7
800130e: bd80 pop {r7, pc}
08001310 <AD5934_Trimmed_Mean>:
* original order is not needed), discards TRIM_COUNT values from each
* end, and averages the remainder. Sorting in place avoids a temporary
* array and removes the need for memcpy()/string.h entirely.
**/
float AD5934_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
{
8001310: b580 push {r7, lr}
8001312: b086 sub sp, #24
8001314: af00 add r7, sp, #0
8001316: 6078 str r0, [r7, #4]
8001318: 460b mov r3, r1
800131a: 70fb strb r3, [r7, #3]
800131c: 4613 mov r3, r2
800131e: 70bb strb r3, [r7, #2]
AD5934_Sort_Array(buffer, n);
8001320: 78fb ldrb r3, [r7, #3]
8001322: 4619 mov r1, r3
8001324: 6878 ldr r0, [r7, #4]
8001326: f7ff ffa7 bl 8001278 <AD5934_Sort_Array>
uint8_t start = trim;
800132a: 78bb ldrb r3, [r7, #2]
800132c: 75fb strb r3, [r7, #23]
uint8_t end = n - trim; /* exclusive */
800132e: 78fa ldrb r2, [r7, #3]
8001330: 78bb ldrb r3, [r7, #2]
8001332: 1ad3 subs r3, r2, r3
8001334: 75bb strb r3, [r7, #22]
if (end <= start) /* guard against a misconfigured trim value */
8001336: 7dba ldrb r2, [r7, #22]
8001338: 7dfb ldrb r3, [r7, #23]
800133a: 429a cmp r2, r3
800133c: d803 bhi.n 8001346 <AD5934_Trimmed_Mean+0x36>
{
start = 0;
800133e: 2300 movs r3, #0
8001340: 75fb strb r3, [r7, #23]
end = n;
8001342: 78fb ldrb r3, [r7, #3]
8001344: 75bb strb r3, [r7, #22]
}
float sum = 0.0f;
8001346: f04f 0300 mov.w r3, #0
800134a: 613b str r3, [r7, #16]
uint8_t count = 0;
800134c: 2300 movs r3, #0
800134e: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001350: 7dfb ldrb r3, [r7, #23]
8001352: 73bb strb r3, [r7, #14]
8001354: e010 b.n 8001378 <AD5934_Trimmed_Mean+0x68>
{
sum += buffer[i];
8001356: 7bbb ldrb r3, [r7, #14]
8001358: 009b lsls r3, r3, #2
800135a: 687a ldr r2, [r7, #4]
800135c: 4413 add r3, r2
800135e: 681b ldr r3, [r3, #0]
8001360: 4619 mov r1, r3
8001362: 6938 ldr r0, [r7, #16]
8001364: f7ff fa96 bl 8000894 <__addsf3>
8001368: 4603 mov r3, r0
800136a: 613b str r3, [r7, #16]
count++;
800136c: 7bfb ldrb r3, [r7, #15]
800136e: 3301 adds r3, #1
8001370: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001372: 7bbb ldrb r3, [r7, #14]
8001374: 3301 adds r3, #1
8001376: 73bb strb r3, [r7, #14]
8001378: 7bba ldrb r2, [r7, #14]
800137a: 7dbb ldrb r3, [r7, #22]
800137c: 429a cmp r2, r3
800137e: d3ea bcc.n 8001356 <AD5934_Trimmed_Mean+0x46>
}
return sum / (float)count;
8001380: 7bfb ldrb r3, [r7, #15]
8001382: 4618 mov r0, r3
8001384: f7ff fb36 bl 80009f4 <__aeabi_ui2f>
8001388: 4603 mov r3, r0
800138a: 4619 mov r1, r3
800138c: 6938 ldr r0, [r7, #16]
800138e: f7ff fc3d bl 8000c0c <__aeabi_fdiv>
8001392: 4603 mov r3, r0
}
8001394: 4618 mov r0, r3
8001396: 3718 adds r7, #24
8001398: 46bd mov sp, r7
800139a: bd80 pop {r7, pc}
0800139c <AD5934_History_Average>:
/*
* Simple average of the history buffer (stage-2 sliding window)
*/
float AD5934_History_Average(const float *hist, uint8_t n)
{
800139c: b580 push {r7, lr}
800139e: b084 sub sp, #16
80013a0: af00 add r7, sp, #0
80013a2: 6078 str r0, [r7, #4]
80013a4: 460b mov r3, r1
80013a6: 70fb strb r3, [r7, #3]
float sum = 0.0f;
80013a8: f04f 0300 mov.w r3, #0
80013ac: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
80013ae: 2300 movs r3, #0
80013b0: 72fb strb r3, [r7, #11]
80013b2: e00d b.n 80013d0 <AD5934_History_Average+0x34>
sum += hist[i];
80013b4: 7afb ldrb r3, [r7, #11]
80013b6: 009b lsls r3, r3, #2
80013b8: 687a ldr r2, [r7, #4]
80013ba: 4413 add r3, r2
80013bc: 681b ldr r3, [r3, #0]
80013be: 4619 mov r1, r3
80013c0: 68f8 ldr r0, [r7, #12]
80013c2: f7ff fa67 bl 8000894 <__addsf3>
80013c6: 4603 mov r3, r0
80013c8: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
80013ca: 7afb ldrb r3, [r7, #11]
80013cc: 3301 adds r3, #1
80013ce: 72fb strb r3, [r7, #11]
80013d0: 7afa ldrb r2, [r7, #11]
80013d2: 78fb ldrb r3, [r7, #3]
80013d4: 429a cmp r2, r3
80013d6: d3ed bcc.n 80013b4 <AD5934_History_Average+0x18>
return sum / (float)n;
80013d8: 78fb ldrb r3, [r7, #3]
80013da: 4618 mov r0, r3
80013dc: f7ff fb0a bl 80009f4 <__aeabi_ui2f>
80013e0: 4603 mov r3, r0
80013e2: 4619 mov r1, r3
80013e4: 68f8 ldr r0, [r7, #12]
80013e6: f7ff fc11 bl 8000c0c <__aeabi_fdiv>
80013ea: 4603 mov r3, r0
}
80013ec: 4618 mov r0, r3
80013ee: 3710 adds r7, #16
80013f0: 46bd mov sp, r7
80013f2: bd80 pop {r7, pc}
080013f4 <AD5934_Process_Sample>:
* Common processing core: applied identically to all 3 channels.
* Receives the current raw reading and the channel's state (global
* arrays/struct).
**/
void AD5934_Process_Sample(AD5934_filter_t *ch, float raw)
{
80013f4: b590 push {r4, r7, lr}
80013f6: b085 sub sp, #20
80013f8: af00 add r7, sp, #0
80013fa: 6078 str r0, [r7, #4]
80013fc: 6039 str r1, [r7, #0]
/* --- Stage 1: accumulate into the current burst --- */
ch->burst[ch->burst_index] = raw;
80013fe: 687b ldr r3, [r7, #4]
8001400: 7f1b ldrb r3, [r3, #28]
8001402: 4619 mov r1, r3
8001404: 687b ldr r3, [r7, #4]
8001406: 683a ldr r2, [r7, #0]
8001408: f843 2021 str.w r2, [r3, r1, lsl #2]
ch->burst_index++;
800140c: 687b ldr r3, [r7, #4]
800140e: 7f1b ldrb r3, [r3, #28]
8001410: 3301 adds r3, #1
8001412: b2da uxtb r2, r3
8001414: 687b ldr r3, [r7, #4]
8001416: 771a strb r2, [r3, #28]
if (ch->burst_index < AD5934_BURST_SIZE)
8001418: 687b ldr r3, [r7, #4]
800141a: 7f1b ldrb r3, [r3, #28]
800141c: 2b06 cmp r3, #6
800141e: d979 bls.n 8001514 <AD5934_Process_Sample+0x120>
return; /* still collecting the burst, nothing else to do */
/* Burst complete: compute the trimmed mean */
float burst_result = AD5934_Trimmed_Mean(ch->burst, AD5934_BURST_SIZE, AD5934_TRIM_COUNT);
8001420: 687b ldr r3, [r7, #4]
8001422: 2201 movs r2, #1
8001424: 2107 movs r1, #7
8001426: 4618 mov r0, r3
8001428: f7ff ff72 bl 8001310 <AD5934_Trimmed_Mean>
800142c: 60f8 str r0, [r7, #12]
ch->burst_index = 0; /* reset for the next burst */
800142e: 687b ldr r3, [r7, #4]
8001430: 2200 movs r2, #0
8001432: 771a strb r2, [r3, #28]
/* --- Stage 2a: rolling history / sliding window --- */
ch->history[ch->history_index] = burst_result;
8001434: 687b ldr r3, [r7, #4]
8001436: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800143a: 461a mov r2, r3
800143c: 687b ldr r3, [r7, #4]
800143e: 3208 adds r2, #8
8001440: 68f9 ldr r1, [r7, #12]
8001442: f843 1022 str.w r1, [r3, r2, lsl #2]
ch->history_index = (uint8_t)((ch->history_index + 1) % AD5934_HISTORY_SIZE);
8001446: 687b ldr r3, [r7, #4]
8001448: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800144c: 3301 adds r3, #1
800144e: 425a negs r2, r3
8001450: f003 0307 and.w r3, r3, #7
8001454: f002 0207 and.w r2, r2, #7
8001458: bf58 it pl
800145a: 4253 negpl r3, r2
800145c: b2da uxtb r2, r3
800145e: 687b ldr r3, [r7, #4]
8001460: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (ch->history_count < AD5934_HISTORY_SIZE)
8001464: 687b ldr r3, [r7, #4]
8001466: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800146a: 2b07 cmp r3, #7
800146c: d807 bhi.n 800147e <AD5934_Process_Sample+0x8a>
ch->history_count++;
800146e: 687b ldr r3, [r7, #4]
8001470: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001474: 3301 adds r3, #1
8001476: b2da uxtb r2, r3
8001478: 687b ldr r3, [r7, #4]
800147a: f883 2041 strb.w r2, [r3, #65] @ 0x41
float window_average = AD5934_History_Average(ch->history, ch->history_count);
800147e: 687b ldr r3, [r7, #4]
8001480: f103 0220 add.w r2, r3, #32
8001484: 687b ldr r3, [r7, #4]
8001486: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800148a: 4619 mov r1, r3
800148c: 4610 mov r0, r2
800148e: f7ff ff85 bl 800139c <AD5934_History_Average>
8001492: 60b8 str r0, [r7, #8]
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
if (!ch->iir_initialized)
8001494: 687b ldr r3, [r7, #4]
8001496: f893 3048 ldrb.w r3, [r3, #72] @ 0x48
800149a: 2b00 cmp r3, #0
800149c: d107 bne.n 80014ae <AD5934_Process_Sample+0xba>
{
ch->iir_state = burst_result;
800149e: 687b ldr r3, [r7, #4]
80014a0: 68fa ldr r2, [r7, #12]
80014a2: 645a str r2, [r3, #68] @ 0x44
ch->iir_initialized = 1;
80014a4: 687b ldr r3, [r7, #4]
80014a6: 2201 movs r2, #1
80014a8: f883 2048 strb.w r2, [r3, #72] @ 0x48
80014ac: e016 b.n 80014dc <AD5934_Process_Sample+0xe8>
}
else
{
ch->iir_state = AD5934_IIR_ALPHA * burst_result + (1.0f - AD5934_IIR_ALPHA) * ch->iir_state;
80014ae: f04f 517a mov.w r1, #1048576000 @ 0x3e800000
80014b2: 68f8 ldr r0, [r7, #12]
80014b4: f7ff faf6 bl 8000aa4 <__aeabi_fmul>
80014b8: 4603 mov r3, r0
80014ba: 461c mov r4, r3
80014bc: 687b ldr r3, [r7, #4]
80014be: 6c5b ldr r3, [r3, #68] @ 0x44
80014c0: f04f 517d mov.w r1, #1061158912 @ 0x3f400000
80014c4: 4618 mov r0, r3
80014c6: f7ff faed bl 8000aa4 <__aeabi_fmul>
80014ca: 4603 mov r3, r0
80014cc: 4619 mov r1, r3
80014ce: 4620 mov r0, r4
80014d0: f7ff f9e0 bl 8000894 <__addsf3>
80014d4: 4603 mov r3, r0
80014d6: 461a mov r2, r3
80014d8: 687b ldr r3, [r7, #4]
80014da: 645a str r2, [r3, #68] @ 0x44
}
/* Final output: combines the IIR state (fast response to real drift)
* with the window average (more stable, slower response). Adjust
* the weighting per channel if needed. */
ch->filtered_value = 0.5f * ch->iir_state + 0.5f * window_average;
80014dc: 687b ldr r3, [r7, #4]
80014de: 6c5b ldr r3, [r3, #68] @ 0x44
80014e0: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
80014e4: 4618 mov r0, r3
80014e6: f7ff fadd bl 8000aa4 <__aeabi_fmul>
80014ea: 4603 mov r3, r0
80014ec: 461c mov r4, r3
80014ee: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
80014f2: 68b8 ldr r0, [r7, #8]
80014f4: f7ff fad6 bl 8000aa4 <__aeabi_fmul>
80014f8: 4603 mov r3, r0
80014fa: 4619 mov r1, r3
80014fc: 4620 mov r0, r4
80014fe: f7ff f9c9 bl 8000894 <__addsf3>
8001502: 4603 mov r3, r0
8001504: 461a mov r2, r3
8001506: 687b ldr r3, [r7, #4]
8001508: 64da str r2, [r3, #76] @ 0x4c
ch->value_valid = 1;
800150a: 687b ldr r3, [r7, #4]
800150c: 2201 movs r2, #1
800150e: f883 2050 strb.w r2, [r3, #80] @ 0x50
8001512: e000 b.n 8001516 <AD5934_Process_Sample+0x122>
return; /* still collecting the burst, nothing else to do */
8001514: bf00 nop
}
8001516: 3714 adds r7, #20
8001518: 46bd mov sp, r7
800151a: bd90 pop {r4, r7, pc}
0800151c <AD5934_RTD_NewSample>:
/* ---------------------------------------------------------------------- */
/* Call this every time a sweep completes with the mux on the RTD
* (PT100/PT1000) channel */
void AD5934_RTD_NewSample(float raw)
{
800151c: b580 push {r7, lr}
800151e: b082 sub sp, #8
8001520: af00 add r7, sp, #0
8001522: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_rtd_filter, raw);
8001524: 6879 ldr r1, [r7, #4]
8001526: 4803 ldr r0, [pc, #12] @ (8001534 <AD5934_RTD_NewSample+0x18>)
8001528: f7ff ff64 bl 80013f4 <AD5934_Process_Sample>
}
800152c: bf00 nop
800152e: 3708 adds r7, #8
8001530: 46bd mov sp, r7
8001532: bd80 pop {r7, pc}
8001534: 200000bc .word 0x200000bc
08001538 <AD5934_EC_NewSample>:
/* Call this every time a sweep completes with the mux on the EC
* (conductivity probe) channel */
void AD5934_EC_NewSample(float raw)
{
8001538: b580 push {r7, lr}
800153a: b082 sub sp, #8
800153c: af00 add r7, sp, #0
800153e: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_ec_filter, raw);
8001540: 6879 ldr r1, [r7, #4]
8001542: 4803 ldr r0, [pc, #12] @ (8001550 <AD5934_EC_NewSample+0x18>)
8001544: f7ff ff56 bl 80013f4 <AD5934_Process_Sample>
}
8001548: bf00 nop
800154a: 3708 adds r7, #8
800154c: 46bd mov sp, r7
800154e: bd80 pop {r7, pc}
8001550: 20000110 .word 0x20000110
08001554 <AD5934_Reference_NewSample>:
/* Call this every time a sweep completes with the mux on the on-board
* precision reference resistor channel */
void AD5934_Reference_NewSample(float raw)
{
8001554: b580 push {r7, lr}
8001556: b082 sub sp, #8
8001558: af00 add r7, sp, #0
800155a: 6078 str r0, [r7, #4]
AD5934_Process_Sample(&g_ref_filter, raw);
800155c: 6879 ldr r1, [r7, #4]
800155e: 4803 ldr r0, [pc, #12] @ (800156c <AD5934_Reference_NewSample+0x18>)
8001560: f7ff ff48 bl 80013f4 <AD5934_Process_Sample>
}
8001564: bf00 nop
8001566: 3708 adds r7, #8
8001568: 46bd mov sp, r7
800156a: bd80 pop {r7, pc}
800156c: 20000164 .word 0x20000164
08001570 <ADG715_SetRegisterValue>:
*
* @return None.
*******************************************************************************/
void ADG715_SetRegisterValue(char value)
{
8001570: b580 push {r7, lr}
8001572: b086 sub sp, #24
8001574: af02 add r7, sp, #8
8001576: 4603 mov r3, r0
8001578: 71fb strb r3, [r7, #7]
uint8_t writeData[1] = {value};
800157a: 79fb ldrb r3, [r7, #7]
800157c: 733b strb r3, [r7, #12]
HAL_StatusTypeDef status;
status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
800157e: f107 020c add.w r2, r7, #12
8001582: 2301 movs r3, #1
8001584: 9300 str r3, [sp, #0]
8001586: 2301 movs r3, #1
8001588: 2190 movs r1, #144 @ 0x90
800158a: 4804 ldr r0, [pc, #16] @ (800159c <ADG715_SetRegisterValue+0x2c>)
800158c: f002 f9fc bl 8003988 <HAL_I2C_Master_Transmit>
8001590: 4603 mov r3, r0
8001592: 73fb strb r3, [r7, #15]
return;
8001594: bf00 nop
}
8001596: 3710 adds r7, #16
8001598: 46bd mov sp, r7
800159a: bd80 pop {r7, pc}
800159c: 200006e0 .word 0x200006e0
080015a0 <ADG715_ResetChannels>:
{
ADG715_SetRegisterValue(ch1+ch2);
}
void ADG715_ResetChannels(void)
{
80015a0: b580 push {r7, lr}
80015a2: af00 add r7, sp, #0
ADG715_SetRegisterValue(0);
80015a4: 2000 movs r0, #0
80015a6: f7ff ffe3 bl 8001570 <ADG715_SetRegisterValue>
}
80015aa: bf00 nop
80015ac: bd80 pop {r7, pc}
...
080015b0 <ADG715_Update>:
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000, AD5934_CH_EC, ...
*
* @return none.
******************************************************************************/
void ADG715_Update(AD5934_Channel_t channel)
{
80015b0: b580 push {r7, lr}
80015b2: b082 sub sp, #8
80015b4: af00 add r7, sp, #0
80015b6: 4603 mov r3, r0
80015b8: 71fb strb r3, [r7, #7]
// Garante que o índice recebido não ultrapassa os limites do vetor
if (channel >= AD5934_CH_MAX)
80015ba: 79fb ldrb r3, [r7, #7]
80015bc: 2b0e cmp r3, #14
80015be: d810 bhi.n 80015e2 <ADG715_Update+0x32>
return;
// Envia o byte combinado via I2C (Make-before-break nativo por barramento)
ADG715_SetRegisterValue(ADG715_Channel_Map[channel]);
80015c0: 79fb ldrb r3, [r7, #7]
80015c2: 4a0a ldr r2, [pc, #40] @ (80015ec <ADG715_Update+0x3c>)
80015c4: 5cd3 ldrb r3, [r2, r3]
80015c6: 4618 mov r0, r3
80015c8: f7ff ffd2 bl 8001570 <ADG715_SetRegisterValue>
// Gestão inteligente do delay de acomodação
if (channel >= AD5934_CH_EC_LOW_GAIN)
80015cc: 79fb ldrb r3, [r7, #7]
80015ce: 2b0b cmp r3, #11
80015d0: d903 bls.n 80015da <ADG715_Update+0x2a>
HAL_Delay(20); // Canais de Condutividade Elétrica (CE) necessitam de maior estabilização química
80015d2: 2014 movs r0, #20
80015d4: f001 fad2 bl 8002b7c <HAL_Delay>
80015d8: e004 b.n 80015e4 <ADG715_Update+0x34>
else
HAL_Delay(10); // Resistores puros e RTD estabilizam mais rapidamente
80015da: 200a movs r0, #10
80015dc: f001 face bl 8002b7c <HAL_Delay>
80015e0: e000 b.n 80015e4 <ADG715_Update+0x34>
return;
80015e2: bf00 nop
}
80015e4: 3708 adds r7, #8
80015e6: 46bd mov sp, r7
80015e8: bd80 pop {r7, pc}
80015ea: bf00 nop
80015ec: 080066c0 .word 0x080066c0
080015f0 <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
80015f0: b580 push {r7, lr}
80015f2: b084 sub sp, #16
80015f4: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80015f6: 1d3b adds r3, r7, #4
80015f8: 2200 movs r2, #0
80015fa: 601a str r2, [r3, #0]
80015fc: 605a str r2, [r3, #4]
80015fe: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8001600: 4b18 ldr r3, [pc, #96] @ (8001664 <MX_ADC1_Init+0x74>)
8001602: 4a19 ldr r2, [pc, #100] @ (8001668 <MX_ADC1_Init+0x78>)
8001604: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001606: 4b17 ldr r3, [pc, #92] @ (8001664 <MX_ADC1_Init+0x74>)
8001608: 2200 movs r2, #0
800160a: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
800160c: 4b15 ldr r3, [pc, #84] @ (8001664 <MX_ADC1_Init+0x74>)
800160e: 2201 movs r2, #1
8001610: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8001612: 4b14 ldr r3, [pc, #80] @ (8001664 <MX_ADC1_Init+0x74>)
8001614: 2200 movs r2, #0
8001616: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001618: 4b12 ldr r3, [pc, #72] @ (8001664 <MX_ADC1_Init+0x74>)
800161a: f44f 2260 mov.w r2, #917504 @ 0xe0000
800161e: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001620: 4b10 ldr r3, [pc, #64] @ (8001664 <MX_ADC1_Init+0x74>)
8001622: 2200 movs r2, #0
8001624: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 1;
8001626: 4b0f ldr r3, [pc, #60] @ (8001664 <MX_ADC1_Init+0x74>)
8001628: 2201 movs r2, #1
800162a: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
800162c: 480d ldr r0, [pc, #52] @ (8001664 <MX_ADC1_Init+0x74>)
800162e: f001 fac9 bl 8002bc4 <HAL_ADC_Init>
8001632: 4603 mov r3, r0
8001634: 2b00 cmp r3, #0
8001636: d001 beq.n 800163c <MX_ADC1_Init+0x4c>
{
Error_Handler();
8001638: f000 ffb4 bl 80025a4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_0;
800163c: 2300 movs r3, #0
800163e: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001640: 2301 movs r3, #1
8001642: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
8001644: 2300 movs r3, #0
8001646: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001648: 1d3b adds r3, r7, #4
800164a: 4619 mov r1, r3
800164c: 4805 ldr r0, [pc, #20] @ (8001664 <MX_ADC1_Init+0x74>)
800164e: f001 fb91 bl 8002d74 <HAL_ADC_ConfigChannel>
8001652: 4603 mov r3, r0
8001654: 2b00 cmp r3, #0
8001656: d001 beq.n 800165c <MX_ADC1_Init+0x6c>
{
Error_Handler();
8001658: f000 ffa4 bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
800165c: bf00 nop
800165e: 3710 adds r7, #16
8001660: 46bd mov sp, r7
8001662: bd80 pop {r7, pc}
8001664: 200001bc .word 0x200001bc
8001668: 40012400 .word 0x40012400
0800166c <MX_ADC2_Init>:
/* ADC2 init function */
void MX_ADC2_Init(void)
{
800166c: b580 push {r7, lr}
800166e: b084 sub sp, #16
8001670: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8001672: 1d3b adds r3, r7, #4
8001674: 2200 movs r2, #0
8001676: 601a str r2, [r3, #0]
8001678: 605a str r2, [r3, #4]
800167a: 609a str r2, [r3, #8]
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
800167c: 4b18 ldr r3, [pc, #96] @ (80016e0 <MX_ADC2_Init+0x74>)
800167e: 4a19 ldr r2, [pc, #100] @ (80016e4 <MX_ADC2_Init+0x78>)
8001680: 601a str r2, [r3, #0]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001682: 4b17 ldr r3, [pc, #92] @ (80016e0 <MX_ADC2_Init+0x74>)
8001684: 2200 movs r2, #0
8001686: 609a str r2, [r3, #8]
hadc2.Init.ContinuousConvMode = ENABLE;
8001688: 4b15 ldr r3, [pc, #84] @ (80016e0 <MX_ADC2_Init+0x74>)
800168a: 2201 movs r2, #1
800168c: 731a strb r2, [r3, #12]
hadc2.Init.DiscontinuousConvMode = DISABLE;
800168e: 4b14 ldr r3, [pc, #80] @ (80016e0 <MX_ADC2_Init+0x74>)
8001690: 2200 movs r2, #0
8001692: 751a strb r2, [r3, #20]
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001694: 4b12 ldr r3, [pc, #72] @ (80016e0 <MX_ADC2_Init+0x74>)
8001696: f44f 2260 mov.w r2, #917504 @ 0xe0000
800169a: 61da str r2, [r3, #28]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800169c: 4b10 ldr r3, [pc, #64] @ (80016e0 <MX_ADC2_Init+0x74>)
800169e: 2200 movs r2, #0
80016a0: 605a str r2, [r3, #4]
hadc2.Init.NbrOfConversion = 1;
80016a2: 4b0f ldr r3, [pc, #60] @ (80016e0 <MX_ADC2_Init+0x74>)
80016a4: 2201 movs r2, #1
80016a6: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc2) != HAL_OK)
80016a8: 480d ldr r0, [pc, #52] @ (80016e0 <MX_ADC2_Init+0x74>)
80016aa: f001 fa8b bl 8002bc4 <HAL_ADC_Init>
80016ae: 4603 mov r3, r0
80016b0: 2b00 cmp r3, #0
80016b2: d001 beq.n 80016b8 <MX_ADC2_Init+0x4c>
{
Error_Handler();
80016b4: f000 ff76 bl 80025a4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
80016b8: 2301 movs r3, #1
80016ba: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80016bc: 2301 movs r3, #1
80016be: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80016c0: 2300 movs r3, #0
80016c2: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
80016c4: 1d3b adds r3, r7, #4
80016c6: 4619 mov r1, r3
80016c8: 4805 ldr r0, [pc, #20] @ (80016e0 <MX_ADC2_Init+0x74>)
80016ca: f001 fb53 bl 8002d74 <HAL_ADC_ConfigChannel>
80016ce: 4603 mov r3, r0
80016d0: 2b00 cmp r3, #0
80016d2: d001 beq.n 80016d8 <MX_ADC2_Init+0x6c>
{
Error_Handler();
80016d4: f000 ff66 bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
80016d8: bf00 nop
80016da: 3710 adds r7, #16
80016dc: 46bd mov sp, r7
80016de: bd80 pop {r7, pc}
80016e0: 200001ec .word 0x200001ec
80016e4: 40012800 .word 0x40012800
080016e8 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
80016e8: b580 push {r7, lr}
80016ea: b08a sub sp, #40 @ 0x28
80016ec: af00 add r7, sp, #0
80016ee: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80016f0: f107 0318 add.w r3, r7, #24
80016f4: 2200 movs r2, #0
80016f6: 601a str r2, [r3, #0]
80016f8: 605a str r2, [r3, #4]
80016fa: 609a str r2, [r3, #8]
80016fc: 60da str r2, [r3, #12]
if(adcHandle->Instance==ADC1)
80016fe: 687b ldr r3, [r7, #4]
8001700: 681b ldr r3, [r3, #0]
8001702: 4a28 ldr r2, [pc, #160] @ (80017a4 <HAL_ADC_MspInit+0xbc>)
8001704: 4293 cmp r3, r2
8001706: d122 bne.n 800174e <HAL_ADC_MspInit+0x66>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001708: 4b27 ldr r3, [pc, #156] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800170a: 699b ldr r3, [r3, #24]
800170c: 4a26 ldr r2, [pc, #152] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800170e: f443 7300 orr.w r3, r3, #512 @ 0x200
8001712: 6193 str r3, [r2, #24]
8001714: 4b24 ldr r3, [pc, #144] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001716: 699b ldr r3, [r3, #24]
8001718: f403 7300 and.w r3, r3, #512 @ 0x200
800171c: 617b str r3, [r7, #20]
800171e: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001720: 4b21 ldr r3, [pc, #132] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001722: 699b ldr r3, [r3, #24]
8001724: 4a20 ldr r2, [pc, #128] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001726: f043 0304 orr.w r3, r3, #4
800172a: 6193 str r3, [r2, #24]
800172c: 4b1e ldr r3, [pc, #120] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800172e: 699b ldr r3, [r3, #24]
8001730: f003 0304 and.w r3, r3, #4
8001734: 613b str r3, [r7, #16]
8001736: 693b ldr r3, [r7, #16]
/**ADC1 GPIO Configuration
PA0-WKUP ------> ADC1_IN0
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
8001738: 2303 movs r3, #3
800173a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800173c: 2303 movs r3, #3
800173e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001740: f107 0318 add.w r3, r7, #24
8001744: 4619 mov r1, r3
8001746: 4819 ldr r0, [pc, #100] @ (80017ac <HAL_ADC_MspInit+0xc4>)
8001748: f001 fe0e bl 8003368 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
800174c: e026 b.n 800179c <HAL_ADC_MspInit+0xb4>
else if(adcHandle->Instance==ADC2)
800174e: 687b ldr r3, [r7, #4]
8001750: 681b ldr r3, [r3, #0]
8001752: 4a17 ldr r2, [pc, #92] @ (80017b0 <HAL_ADC_MspInit+0xc8>)
8001754: 4293 cmp r3, r2
8001756: d121 bne.n 800179c <HAL_ADC_MspInit+0xb4>
__HAL_RCC_ADC2_CLK_ENABLE();
8001758: 4b13 ldr r3, [pc, #76] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800175a: 699b ldr r3, [r3, #24]
800175c: 4a12 ldr r2, [pc, #72] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800175e: f443 6380 orr.w r3, r3, #1024 @ 0x400
8001762: 6193 str r3, [r2, #24]
8001764: 4b10 ldr r3, [pc, #64] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001766: 699b ldr r3, [r3, #24]
8001768: f403 6380 and.w r3, r3, #1024 @ 0x400
800176c: 60fb str r3, [r7, #12]
800176e: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001770: 4b0d ldr r3, [pc, #52] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001772: 699b ldr r3, [r3, #24]
8001774: 4a0c ldr r2, [pc, #48] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
8001776: f043 0304 orr.w r3, r3, #4
800177a: 6193 str r3, [r2, #24]
800177c: 4b0a ldr r3, [pc, #40] @ (80017a8 <HAL_ADC_MspInit+0xc0>)
800177e: 699b ldr r3, [r3, #24]
8001780: f003 0304 and.w r3, r3, #4
8001784: 60bb str r3, [r7, #8]
8001786: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
8001788: 2303 movs r3, #3
800178a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800178c: 2303 movs r3, #3
800178e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001790: f107 0318 add.w r3, r7, #24
8001794: 4619 mov r1, r3
8001796: 4805 ldr r0, [pc, #20] @ (80017ac <HAL_ADC_MspInit+0xc4>)
8001798: f001 fde6 bl 8003368 <HAL_GPIO_Init>
}
800179c: bf00 nop
800179e: 3728 adds r7, #40 @ 0x28
80017a0: 46bd mov sp, r7
80017a2: bd80 pop {r7, pc}
80017a4: 40012400 .word 0x40012400
80017a8: 40021000 .word 0x40021000
80017ac: 40010800 .word 0x40010800
80017b0: 40012800 .word 0x40012800
080017b4 <writeRegister>:
ADS1015_filter_t g_ph_filter = {0};
volatile ADS1015_State_t ads1015_state = ADS1015_IDLE;
// Write the register
static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
80017b4: b580 push {r7, lr}
80017b6: b086 sub sp, #24
80017b8: af02 add r7, sp, #8
80017ba: 6078 str r0, [r7, #4]
80017bc: 460b mov r3, r1
80017be: 70fb strb r3, [r7, #3]
80017c0: 4613 mov r3, r2
80017c2: 803b strh r3, [r7, #0]
uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
80017c4: 78fb ldrb r3, [r7, #3]
80017c6: 733b strb r3, [r7, #12]
80017c8: 883b ldrh r3, [r7, #0]
80017ca: 0a1b lsrs r3, r3, #8
80017cc: b29b uxth r3, r3
80017ce: b2db uxtb r3, r3
80017d0: 737b strb r3, [r7, #13]
80017d2: 883b ldrh r3, [r7, #0]
80017d4: b2db uxtb r3, r3
80017d6: 73bb strb r3, [r7, #14]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
80017d8: 687b ldr r3, [r7, #4]
80017da: 68d8 ldr r0, [r3, #12]
80017dc: 687b ldr r3, [r7, #4]
80017de: 8819 ldrh r1, [r3, #0]
80017e0: f107 020c add.w r2, r7, #12
80017e4: 230a movs r3, #10
80017e6: 9300 str r3, [sp, #0]
80017e8: 2303 movs r3, #3
80017ea: f002 f8cd bl 8003988 <HAL_I2C_Master_Transmit>
}
80017ee: bf00 nop
80017f0: 3710 adds r7, #16
80017f2: 46bd mov sp, r7
80017f4: bd80 pop {r7, pc}
080017f6 <readRegister>:
// Read the register
static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
80017f6: b580 push {r7, lr}
80017f8: b086 sub sp, #24
80017fa: af02 add r7, sp, #8
80017fc: 6078 str r0, [r7, #4]
80017fe: 460b mov r3, r1
8001800: 70fb strb r3, [r7, #3]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, &reg, 1, 10);
8001802: 687b ldr r3, [r7, #4]
8001804: 68d8 ldr r0, [r3, #12]
8001806: 687b ldr r3, [r7, #4]
8001808: 8819 ldrh r1, [r3, #0]
800180a: 1cfa adds r2, r7, #3
800180c: 230a movs r3, #10
800180e: 9300 str r3, [sp, #0]
8001810: 2301 movs r3, #1
8001812: f002 f8b9 bl 8003988 <HAL_I2C_Master_Transmit>
uint8_t pData[2] = { 0, 0 };
8001816: 2300 movs r3, #0
8001818: 81bb strh r3, [r7, #12]
HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
800181a: 687b ldr r3, [r7, #4]
800181c: 68d8 ldr r0, [r3, #12]
800181e: 687b ldr r3, [r7, #4]
8001820: 8819 ldrh r1, [r3, #0]
8001822: f107 020c add.w r2, r7, #12
8001826: 230a movs r3, #10
8001828: 9300 str r3, [sp, #0]
800182a: 2302 movs r3, #2
800182c: f002 f9aa bl 8003b84 <HAL_I2C_Master_Receive>
return ((pData[0] << 8) | pData[1]);
8001830: 7b3b ldrb r3, [r7, #12]
8001832: b21b sxth r3, r3
8001834: 021b lsls r3, r3, #8
8001836: b21a sxth r2, r3
8001838: 7b7b ldrb r3, [r7, #13]
800183a: b21b sxth r3, r3
800183c: 4313 orrs r3, r2
800183e: b21b sxth r3, r3
8001840: b29b uxth r3, r3
}
8001842: 4618 mov r0, r3
8001844: 3710 adds r7, #16
8001846: 46bd mov sp, r7
8001848: bd80 pop {r7, pc}
0800184a <ADS1015>:
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // This MUST have GPIO PA5 ready to use - ERROR I2C - Wrong address
}
// Declare an ADS1015 structure
void ADS1015(ADS1015_I2C *i2c, I2C_HandleTypeDef *hi2c, uint8_t i2cAddress) {
800184a: b480 push {r7}
800184c: b085 sub sp, #20
800184e: af00 add r7, sp, #0
8001850: 60f8 str r0, [r7, #12]
8001852: 60b9 str r1, [r7, #8]
8001854: 4613 mov r3, r2
8001856: 71fb strb r3, [r7, #7]
i2c->hi2c = hi2c;
8001858: 68fb ldr r3, [r7, #12]
800185a: 68ba ldr r2, [r7, #8]
800185c: 60da str r2, [r3, #12]
i2c->m_i2cAddress = i2cAddress; // << 1; // It's Important to shift the address << 1
800185e: 79fb ldrb r3, [r7, #7]
8001860: b29a uxth r2, r3
8001862: 68fb ldr r3, [r7, #12]
8001864: 801a strh r2, [r3, #0]
i2c->m_conversionDelay = ADS1015_CONVERSIONDELAY;
8001866: 68fb ldr r3, [r7, #12]
8001868: 2204 movs r2, #4
800186a: 605a str r2, [r3, #4]
i2c->m_bitShift = 4;
800186c: 68fb ldr r3, [r7, #12]
800186e: 2204 movs r2, #4
8001870: 721a strb r2, [r3, #8]
i2c->m_gain = GAIN_SIXTEEN; /* +/- 6.144V range (limited to VDD +0.3V max!) */
8001872: 68fb ldr r3, [r7, #12]
8001874: f44f 6220 mov.w r2, #2560 @ 0xa00
8001878: 815a strh r2, [r3, #10]
//ADSbegin(i2c); //Ready is not used
}
800187a: bf00 nop
800187c: 3714 adds r7, #20
800187e: 46bd mov sp, r7
8001880: bc80 pop {r7}
8001882: 4770 bx lr
08001884 <ADS1015_Process_System>:
void ADS1015_Process_System(void)
{
8001884: b580 push {r7, lr}
8001886: b082 sub sp, #8
8001888: af00 add r7, sp, #0
static uint32_t state_timer = 0;
static uint32_t sample_count = 0;
uint16_t config_reg = 0;
800188a: 2300 movs r3, #0
800188c: 80fb strh r3, [r7, #6]
switch (ads1015_state)
800188e: 4b3d ldr r3, [pc, #244] @ (8001984 <ADS1015_Process_System+0x100>)
8001890: 781b ldrb r3, [r3, #0]
8001892: b2db uxtb r3, r3
8001894: 2b04 cmp r3, #4
8001896: d870 bhi.n 800197a <ADS1015_Process_System+0xf6>
8001898: a201 add r2, pc, #4 @ (adr r2, 80018a0 <ADS1015_Process_System+0x1c>)
800189a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800189e: bf00 nop
80018a0: 080018b5 .word 0x080018b5
80018a4: 080018c3 .word 0x080018c3
80018a8: 080018df .word 0x080018df
80018ac: 08001909 .word 0x08001909
80018b0: 0800195f .word 0x0800195f
{
case ADS1015_IDLE:
sample_count = 0;
80018b4: 4b34 ldr r3, [pc, #208] @ (8001988 <ADS1015_Process_System+0x104>)
80018b6: 2200 movs r2, #0
80018b8: 601a str r2, [r3, #0]
ads1015_state = ADS1015_START_CONVERSION;
80018ba: 4b32 ldr r3, [pc, #200] @ (8001984 <ADS1015_Process_System+0x100>)
80018bc: 2201 movs r2, #1
80018be: 701a strb r2, [r3, #0]
break;
80018c0: e05b b.n 800197a <ADS1015_Process_System+0xf6>
case ADS1015_START_CONVERSION:
state_timer = g_ms_counter;
80018c2: 4b32 ldr r3, [pc, #200] @ (800198c <ADS1015_Process_System+0x108>)
80018c4: 681b ldr r3, [r3, #0]
80018c6: 4a32 ldr r2, [pc, #200] @ (8001990 <ADS1015_Process_System+0x10c>)
80018c8: 6013 str r3, [r2, #0]
/* Escreve no Config Register (P[1:0]=01b) com OS=1 para
* iniciar a conversão single-shot. O bit OS só tem efeito
* quando o dispositivo está em power-down (seção 7.4.2.1) */
// Write config register to the ADC
writeRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG, ADS1015_CONFIG_START_SINGLE);
80018ca: f648 3203 movw r2, #35587 @ 0x8b03
80018ce: 2101 movs r1, #1
80018d0: 4830 ldr r0, [pc, #192] @ (8001994 <ADS1015_Process_System+0x110>)
80018d2: f7ff ff6f bl 80017b4 <writeRegister>
ads1015_state = ADS1015_WAIT_CONVERSION;
80018d6: 4b2b ldr r3, [pc, #172] @ (8001984 <ADS1015_Process_System+0x100>)
80018d8: 2202 movs r2, #2
80018da: 701a strb r2, [r3, #0]
break;
80018dc: e04d b.n 800197a <ADS1015_Process_System+0xf6>
* 0b = dispositivo ainda convertendo
* 1b = conversão concluída, dado pronto no Conversion Register
* (Tabela 8-4, descrição do bit OS)
*/
config_reg = readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG);
80018de: 2101 movs r1, #1
80018e0: 482c ldr r0, [pc, #176] @ (8001994 <ADS1015_Process_System+0x110>)
80018e2: f7ff ff88 bl 80017f6 <readRegister>
80018e6: 4603 mov r3, r0
80018e8: 80fb strh r3, [r7, #6]
if (((config_reg & ADS1015_REG_CONFIG_OS_SINGLE) != 0) && (g_ms_counter - state_timer)>ADS1015_TIME_PER_SAMPLE)
80018ea: f9b7 3006 ldrsh.w r3, [r7, #6]
80018ee: 2b00 cmp r3, #0
80018f0: da40 bge.n 8001974 <ADS1015_Process_System+0xf0>
80018f2: 4b26 ldr r3, [pc, #152] @ (800198c <ADS1015_Process_System+0x108>)
80018f4: 681a ldr r2, [r3, #0]
80018f6: 4b26 ldr r3, [pc, #152] @ (8001990 <ADS1015_Process_System+0x10c>)
80018f8: 681b ldr r3, [r3, #0]
80018fa: 1ad3 subs r3, r2, r3
80018fc: 2b09 cmp r3, #9
80018fe: d939 bls.n 8001974 <ADS1015_Process_System+0xf0>
{
ads1015_state = ADS1015_READ_DATA;
8001900: 4b20 ldr r3, [pc, #128] @ (8001984 <ADS1015_Process_System+0x100>)
8001902: 2203 movs r2, #3
8001904: 701a strb r2, [r3, #0]
}
// (opcional) tratar timeout comparando g_ms_counter - state_timer
// Datasheet: conversão single-cycle, tempo = 1/DR (ex: 1600SPS ≈ 625µs)
break;
8001906: e035 b.n 8001974 <ADS1015_Process_System+0xf0>
case ADS1015_READ_DATA:
{
/* Muda o Address Pointer para o Conversion Register (P[1:0]=00b)
* e lê os 16 bits. Dado é 12 bits em complemento de 2,
* left-justified em D[15:4]; D[3:0] sempre lê 0h (Tabela 8-3) */
int16_t raw = (int16_t)readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONVERT);
8001908: 2100 movs r1, #0
800190a: 4822 ldr r0, [pc, #136] @ (8001994 <ADS1015_Process_System+0x110>)
800190c: f7ff ff73 bl 80017f6 <readRegister>
8001910: 4603 mov r3, r0
8001912: 80bb strh r3, [r7, #4]
raw >>= 4; // remove os 4 bits reservados (D[3:0]), resultado = 12 bits signed
8001914: f9b7 3004 ldrsh.w r3, [r7, #4]
8001918: 111b asrs r3, r3, #4
800191a: 80bb strh r3, [r7, #4]
float value = (float)(4096 - raw); // ((float)raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX; // usa FSR configurado no PGA
800191c: f9b7 3004 ldrsh.w r3, [r7, #4]
8001920: f5c3 5380 rsb r3, r3, #4096 @ 0x1000
8001924: 4618 mov r0, r3
8001926: f7ff f869 bl 80009fc <__aeabi_i2f>
800192a: 4603 mov r3, r0
800192c: 603b str r3, [r7, #0]
ADS1015_pH_NewSample(value);
800192e: 6838 ldr r0, [r7, #0]
8001930: f000 f986 bl 8001c40 <ADS1015_pH_NewSample>
sample_count++;
8001934: 4b14 ldr r3, [pc, #80] @ (8001988 <ADS1015_Process_System+0x104>)
8001936: 681b ldr r3, [r3, #0]
8001938: 3301 adds r3, #1
800193a: 4a13 ldr r2, [pc, #76] @ (8001988 <ADS1015_Process_System+0x104>)
800193c: 6013 str r3, [r2, #0]
if (sample_count >= ADS1015_BURST_SIZE)
800193e: 4b12 ldr r3, [pc, #72] @ (8001988 <ADS1015_Process_System+0x104>)
8001940: 681b ldr r3, [r3, #0]
8001942: 2b04 cmp r3, #4
8001944: d903 bls.n 800194e <ADS1015_Process_System+0xca>
{
ads1015_state = ADS1015_IDLE;
8001946: 4b0f ldr r3, [pc, #60] @ (8001984 <ADS1015_Process_System+0x100>)
8001948: 2200 movs r2, #0
800194a: 701a strb r2, [r3, #0]
{
state_timer = g_ms_counter;
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
}
}
break;
800194c: e015 b.n 800197a <ADS1015_Process_System+0xf6>
state_timer = g_ms_counter;
800194e: 4b0f ldr r3, [pc, #60] @ (800198c <ADS1015_Process_System+0x108>)
8001950: 681b ldr r3, [r3, #0]
8001952: 4a0f ldr r2, [pc, #60] @ (8001990 <ADS1015_Process_System+0x10c>)
8001954: 6013 str r3, [r2, #0]
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
8001956: 4b0b ldr r3, [pc, #44] @ (8001984 <ADS1015_Process_System+0x100>)
8001958: 2204 movs r2, #4
800195a: 701a strb r2, [r3, #0]
break;
800195c: e00d b.n 800197a <ADS1015_Process_System+0xf6>
case ADS1015_WAIT_NEXT_SAMPLE:
if ((g_ms_counter - state_timer) >= ADS1015_TIME_PER_SAMPLE)
800195e: 4b0b ldr r3, [pc, #44] @ (800198c <ADS1015_Process_System+0x108>)
8001960: 681a ldr r2, [r3, #0]
8001962: 4b0b ldr r3, [pc, #44] @ (8001990 <ADS1015_Process_System+0x10c>)
8001964: 681b ldr r3, [r3, #0]
8001966: 1ad3 subs r3, r2, r3
8001968: 2b08 cmp r3, #8
800196a: d905 bls.n 8001978 <ADS1015_Process_System+0xf4>
{
ads1015_state = ADS1015_START_CONVERSION;
800196c: 4b05 ldr r3, [pc, #20] @ (8001984 <ADS1015_Process_System+0x100>)
800196e: 2201 movs r2, #1
8001970: 701a strb r2, [r3, #0]
}
break;
8001972: e001 b.n 8001978 <ADS1015_Process_System+0xf4>
break;
8001974: bf00 nop
8001976: e000 b.n 800197a <ADS1015_Process_System+0xf6>
break;
8001978: bf00 nop
}
}
800197a: bf00 nop
800197c: 3708 adds r7, #8
800197e: 46bd mov sp, r7
8001980: bd80 pop {r7, pc}
8001982: bf00 nop
8001984: 20000278 .word 0x20000278
8001988: 2000027c .word 0x2000027c
800198c: 200000b4 .word 0x200000b4
8001990: 20000280 .word 0x20000280
8001994: 2000021c .word 0x2000021c
08001998 <ADS1015_Sort_Array>:
/**
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
* and it avoids depending on qsort/heap allocation.
**/
void ADS1015_Sort_Array(float *v, uint8_t n)
{
8001998: b580 push {r7, lr}
800199a: b084 sub sp, #16
800199c: af00 add r7, sp, #0
800199e: 6078 str r0, [r7, #4]
80019a0: 460b mov r3, r1
80019a2: 70fb strb r3, [r7, #3]
for (uint8_t i = 1; i < n; i++)
80019a4: 2301 movs r3, #1
80019a6: 73fb strb r3, [r7, #15]
80019a8: e039 b.n 8001a1e <ADS1015_Sort_Array+0x86>
{
float key = v[i];
80019aa: 7bfb ldrb r3, [r7, #15]
80019ac: 009b lsls r3, r3, #2
80019ae: 687a ldr r2, [r7, #4]
80019b0: 4413 add r3, r2
80019b2: 681b ldr r3, [r3, #0]
80019b4: 60bb str r3, [r7, #8]
int8_t j = (int8_t)i - 1;
80019b6: 7bfb ldrb r3, [r7, #15]
80019b8: 3b01 subs r3, #1
80019ba: b2db uxtb r3, r3
80019bc: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
80019be: e012 b.n 80019e6 <ADS1015_Sort_Array+0x4e>
{
v[j + 1] = v[j];
80019c0: f997 300e ldrsb.w r3, [r7, #14]
80019c4: 009b lsls r3, r3, #2
80019c6: 687a ldr r2, [r7, #4]
80019c8: 441a add r2, r3
80019ca: f997 300e ldrsb.w r3, [r7, #14]
80019ce: 3301 adds r3, #1
80019d0: 009b lsls r3, r3, #2
80019d2: 6879 ldr r1, [r7, #4]
80019d4: 440b add r3, r1
80019d6: 6812 ldr r2, [r2, #0]
80019d8: 601a str r2, [r3, #0]
j--;
80019da: f997 300e ldrsb.w r3, [r7, #14]
80019de: b2db uxtb r3, r3
80019e0: 3b01 subs r3, #1
80019e2: b2db uxtb r3, r3
80019e4: 73bb strb r3, [r7, #14]
while (j >= 0 && v[j] > key)
80019e6: f997 300e ldrsb.w r3, [r7, #14]
80019ea: 2b00 cmp r3, #0
80019ec: db0c blt.n 8001a08 <ADS1015_Sort_Array+0x70>
80019ee: f997 300e ldrsb.w r3, [r7, #14]
80019f2: 009b lsls r3, r3, #2
80019f4: 687a ldr r2, [r7, #4]
80019f6: 4413 add r3, r2
80019f8: 681b ldr r3, [r3, #0]
80019fa: 4619 mov r1, r3
80019fc: 68b8 ldr r0, [r7, #8]
80019fe: f7ff f9ef bl 8000de0 <__aeabi_fcmplt>
8001a02: 4603 mov r3, r0
8001a04: 2b00 cmp r3, #0
8001a06: d1db bne.n 80019c0 <ADS1015_Sort_Array+0x28>
}
v[j + 1] = key;
8001a08: f997 300e ldrsb.w r3, [r7, #14]
8001a0c: 3301 adds r3, #1
8001a0e: 009b lsls r3, r3, #2
8001a10: 687a ldr r2, [r7, #4]
8001a12: 4413 add r3, r2
8001a14: 68ba ldr r2, [r7, #8]
8001a16: 601a str r2, [r3, #0]
for (uint8_t i = 1; i < n; i++)
8001a18: 7bfb ldrb r3, [r7, #15]
8001a1a: 3301 adds r3, #1
8001a1c: 73fb strb r3, [r7, #15]
8001a1e: 7bfa ldrb r2, [r7, #15]
8001a20: 78fb ldrb r3, [r7, #3]
8001a22: 429a cmp r2, r3
8001a24: d3c1 bcc.n 80019aa <ADS1015_Sort_Array+0x12>
}
}
8001a26: bf00 nop
8001a28: bf00 nop
8001a2a: 3710 adds r7, #16
8001a2c: 46bd mov sp, r7
8001a2e: bd80 pop {r7, pc}
08001a30 <ADS1015_Trimmed_Mean>:
* original order is not needed), discards TRIM_COUNT values from each
* end, and averages the remainder. Sorting in place avoids a temporary
* array and removes the need for memcpy()/string.h entirely.
**/
float ADS1015_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
{
8001a30: b580 push {r7, lr}
8001a32: b086 sub sp, #24
8001a34: af00 add r7, sp, #0
8001a36: 6078 str r0, [r7, #4]
8001a38: 460b mov r3, r1
8001a3a: 70fb strb r3, [r7, #3]
8001a3c: 4613 mov r3, r2
8001a3e: 70bb strb r3, [r7, #2]
ADS1015_Sort_Array(buffer, n);
8001a40: 78fb ldrb r3, [r7, #3]
8001a42: 4619 mov r1, r3
8001a44: 6878 ldr r0, [r7, #4]
8001a46: f7ff ffa7 bl 8001998 <ADS1015_Sort_Array>
uint8_t start = trim;
8001a4a: 78bb ldrb r3, [r7, #2]
8001a4c: 75fb strb r3, [r7, #23]
uint8_t end = n - trim; /* exclusive */
8001a4e: 78fa ldrb r2, [r7, #3]
8001a50: 78bb ldrb r3, [r7, #2]
8001a52: 1ad3 subs r3, r2, r3
8001a54: 75bb strb r3, [r7, #22]
if (end <= start) /* guard against a misconfigured trim value */
8001a56: 7dba ldrb r2, [r7, #22]
8001a58: 7dfb ldrb r3, [r7, #23]
8001a5a: 429a cmp r2, r3
8001a5c: d803 bhi.n 8001a66 <ADS1015_Trimmed_Mean+0x36>
{
start = 0;
8001a5e: 2300 movs r3, #0
8001a60: 75fb strb r3, [r7, #23]
end = n;
8001a62: 78fb ldrb r3, [r7, #3]
8001a64: 75bb strb r3, [r7, #22]
}
float sum = 0.0f;
8001a66: f04f 0300 mov.w r3, #0
8001a6a: 613b str r3, [r7, #16]
uint8_t count = 0;
8001a6c: 2300 movs r3, #0
8001a6e: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001a70: 7dfb ldrb r3, [r7, #23]
8001a72: 73bb strb r3, [r7, #14]
8001a74: e010 b.n 8001a98 <ADS1015_Trimmed_Mean+0x68>
{
sum += buffer[i];
8001a76: 7bbb ldrb r3, [r7, #14]
8001a78: 009b lsls r3, r3, #2
8001a7a: 687a ldr r2, [r7, #4]
8001a7c: 4413 add r3, r2
8001a7e: 681b ldr r3, [r3, #0]
8001a80: 4619 mov r1, r3
8001a82: 6938 ldr r0, [r7, #16]
8001a84: f7fe ff06 bl 8000894 <__addsf3>
8001a88: 4603 mov r3, r0
8001a8a: 613b str r3, [r7, #16]
count++;
8001a8c: 7bfb ldrb r3, [r7, #15]
8001a8e: 3301 adds r3, #1
8001a90: 73fb strb r3, [r7, #15]
for (uint8_t i = start; i < end; i++)
8001a92: 7bbb ldrb r3, [r7, #14]
8001a94: 3301 adds r3, #1
8001a96: 73bb strb r3, [r7, #14]
8001a98: 7bba ldrb r2, [r7, #14]
8001a9a: 7dbb ldrb r3, [r7, #22]
8001a9c: 429a cmp r2, r3
8001a9e: d3ea bcc.n 8001a76 <ADS1015_Trimmed_Mean+0x46>
}
return sum / (float)count;
8001aa0: 7bfb ldrb r3, [r7, #15]
8001aa2: 4618 mov r0, r3
8001aa4: f7fe ffa6 bl 80009f4 <__aeabi_ui2f>
8001aa8: 4603 mov r3, r0
8001aaa: 4619 mov r1, r3
8001aac: 6938 ldr r0, [r7, #16]
8001aae: f7ff f8ad bl 8000c0c <__aeabi_fdiv>
8001ab2: 4603 mov r3, r0
}
8001ab4: 4618 mov r0, r3
8001ab6: 3718 adds r7, #24
8001ab8: 46bd mov sp, r7
8001aba: bd80 pop {r7, pc}
08001abc <ADS1015_History_Average>:
/*
* Simple average of the history buffer (stage-2 sliding window)
*/
float ADS1015_History_Average(const float *hist, uint8_t n)
{
8001abc: b580 push {r7, lr}
8001abe: b084 sub sp, #16
8001ac0: af00 add r7, sp, #0
8001ac2: 6078 str r0, [r7, #4]
8001ac4: 460b mov r3, r1
8001ac6: 70fb strb r3, [r7, #3]
float sum = 0.0f;
8001ac8: f04f 0300 mov.w r3, #0
8001acc: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
8001ace: 2300 movs r3, #0
8001ad0: 72fb strb r3, [r7, #11]
8001ad2: e00d b.n 8001af0 <ADS1015_History_Average+0x34>
sum += hist[i];
8001ad4: 7afb ldrb r3, [r7, #11]
8001ad6: 009b lsls r3, r3, #2
8001ad8: 687a ldr r2, [r7, #4]
8001ada: 4413 add r3, r2
8001adc: 681b ldr r3, [r3, #0]
8001ade: 4619 mov r1, r3
8001ae0: 68f8 ldr r0, [r7, #12]
8001ae2: f7fe fed7 bl 8000894 <__addsf3>
8001ae6: 4603 mov r3, r0
8001ae8: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < n; i++)
8001aea: 7afb ldrb r3, [r7, #11]
8001aec: 3301 adds r3, #1
8001aee: 72fb strb r3, [r7, #11]
8001af0: 7afa ldrb r2, [r7, #11]
8001af2: 78fb ldrb r3, [r7, #3]
8001af4: 429a cmp r2, r3
8001af6: d3ed bcc.n 8001ad4 <ADS1015_History_Average+0x18>
return sum / (float)n;
8001af8: 78fb ldrb r3, [r7, #3]
8001afa: 4618 mov r0, r3
8001afc: f7fe ff7a bl 80009f4 <__aeabi_ui2f>
8001b00: 4603 mov r3, r0
8001b02: 4619 mov r1, r3
8001b04: 68f8 ldr r0, [r7, #12]
8001b06: f7ff f881 bl 8000c0c <__aeabi_fdiv>
8001b0a: 4603 mov r3, r0
}
8001b0c: 4618 mov r0, r3
8001b0e: 3710 adds r7, #16
8001b10: 46bd mov sp, r7
8001b12: bd80 pop {r7, pc}
08001b14 <ADS1015_Process_Sample>:
* Common processing core: applied identically to all 3 channels.
* Receives the current raw reading and the channel's state (global
* arrays/struct).
**/
void ADS1015_Process_Sample(ADS1015_filter_t *ch, float raw)
{
8001b14: b590 push {r4, r7, lr}
8001b16: b085 sub sp, #20
8001b18: af00 add r7, sp, #0
8001b1a: 6078 str r0, [r7, #4]
8001b1c: 6039 str r1, [r7, #0]
/* --- Stage 1: accumulate into the current burst --- */
ch->burst[ch->burst_index] = raw;
8001b1e: 687b ldr r3, [r7, #4]
8001b20: 7d1b ldrb r3, [r3, #20]
8001b22: 4619 mov r1, r3
8001b24: 687b ldr r3, [r7, #4]
8001b26: 683a ldr r2, [r7, #0]
8001b28: f843 2021 str.w r2, [r3, r1, lsl #2]
ch->burst_index++;
8001b2c: 687b ldr r3, [r7, #4]
8001b2e: 7d1b ldrb r3, [r3, #20]
8001b30: 3301 adds r3, #1
8001b32: b2da uxtb r2, r3
8001b34: 687b ldr r3, [r7, #4]
8001b36: 751a strb r2, [r3, #20]
if (ch->burst_index < ADS1015_BURST_SIZE)
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 7d1b ldrb r3, [r3, #20]
8001b3c: 2b04 cmp r3, #4
8001b3e: d977 bls.n 8001c30 <ADS1015_Process_Sample+0x11c>
return; /* still collecting the burst, nothing else to do */
/* Burst complete: compute the trimmed mean */
float burst_result = ADS1015_Trimmed_Mean(ch->burst, ADS1015_BURST_SIZE, ADS1015_TRIM_COUNT);
8001b40: 687b ldr r3, [r7, #4]
8001b42: 2201 movs r2, #1
8001b44: 2105 movs r1, #5
8001b46: 4618 mov r0, r3
8001b48: f7ff ff72 bl 8001a30 <ADS1015_Trimmed_Mean>
8001b4c: 60f8 str r0, [r7, #12]
ch->burst_index = 0; /* reset for the next burst */
8001b4e: 687b ldr r3, [r7, #4]
8001b50: 2200 movs r2, #0
8001b52: 751a strb r2, [r3, #20]
/* --- Stage 2a: rolling history / sliding window --- */
ch->history[ch->history_index] = burst_result;
8001b54: 687b ldr r3, [r7, #4]
8001b56: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8001b5a: 461a mov r2, r3
8001b5c: 687b ldr r3, [r7, #4]
8001b5e: 3206 adds r2, #6
8001b60: 68f9 ldr r1, [r7, #12]
8001b62: f843 1022 str.w r1, [r3, r2, lsl #2]
ch->history_index = (uint8_t)((ch->history_index + 1) % ADS1015_HISTORY_SIZE);
8001b66: 687b ldr r3, [r7, #4]
8001b68: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8001b6c: 3301 adds r3, #1
8001b6e: 425a negs r2, r3
8001b70: f003 0307 and.w r3, r3, #7
8001b74: f002 0207 and.w r2, r2, #7
8001b78: bf58 it pl
8001b7a: 4253 negpl r3, r2
8001b7c: b2da uxtb r2, r3
8001b7e: 687b ldr r3, [r7, #4]
8001b80: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (ch->history_count < ADS1015_HISTORY_SIZE)
8001b84: 687b ldr r3, [r7, #4]
8001b86: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8001b8a: 2b07 cmp r3, #7
8001b8c: d807 bhi.n 8001b9e <ADS1015_Process_Sample+0x8a>
ch->history_count++;
8001b8e: 687b ldr r3, [r7, #4]
8001b90: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8001b94: 3301 adds r3, #1
8001b96: b2da uxtb r2, r3
8001b98: 687b ldr r3, [r7, #4]
8001b9a: f883 2039 strb.w r2, [r3, #57] @ 0x39
float window_average = ADS1015_History_Average(ch->history, ch->history_count);
8001b9e: 687b ldr r3, [r7, #4]
8001ba0: f103 0218 add.w r2, r3, #24
8001ba4: 687b ldr r3, [r7, #4]
8001ba6: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8001baa: 4619 mov r1, r3
8001bac: 4610 mov r0, r2
8001bae: f7ff ff85 bl 8001abc <ADS1015_History_Average>
8001bb2: 60b8 str r0, [r7, #8]
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
if (!ch->iir_initialized)
8001bb4: 687b ldr r3, [r7, #4]
8001bb6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001bba: 2b00 cmp r3, #0
8001bbc: d107 bne.n 8001bce <ADS1015_Process_Sample+0xba>
{
ch->iir_state = burst_result;
8001bbe: 687b ldr r3, [r7, #4]
8001bc0: 68fa ldr r2, [r7, #12]
8001bc2: 63da str r2, [r3, #60] @ 0x3c
ch->iir_initialized = 1;
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 2201 movs r2, #1
8001bc8: f883 2040 strb.w r2, [r3, #64] @ 0x40
8001bcc: e014 b.n 8001bf8 <ADS1015_Process_Sample+0xe4>
}
else
{
ch->iir_state = ADS1015_IIR_ALPHA * burst_result + (1.0f - ADS1015_IIR_ALPHA) * ch->iir_state;
8001bce: 491a ldr r1, [pc, #104] @ (8001c38 <ADS1015_Process_Sample+0x124>)
8001bd0: 68f8 ldr r0, [r7, #12]
8001bd2: f7fe ff67 bl 8000aa4 <__aeabi_fmul>
8001bd6: 4603 mov r3, r0
8001bd8: 461c mov r4, r3
8001bda: 687b ldr r3, [r7, #4]
8001bdc: 6bdb ldr r3, [r3, #60] @ 0x3c
8001bde: 4917 ldr r1, [pc, #92] @ (8001c3c <ADS1015_Process_Sample+0x128>)
8001be0: 4618 mov r0, r3
8001be2: f7fe ff5f bl 8000aa4 <__aeabi_fmul>
8001be6: 4603 mov r3, r0
8001be8: 4619 mov r1, r3
8001bea: 4620 mov r0, r4
8001bec: f7fe fe52 bl 8000894 <__addsf3>
8001bf0: 4603 mov r3, r0
8001bf2: 461a mov r2, r3
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 63da str r2, [r3, #60] @ 0x3c
}
/* Final output: combines the IIR state (fast response to real drift)
* with the window average (more stable, slower response). Adjust
* the weighting per channel if needed. */
ch->filtered_value = 0.5f * ch->iir_state + 0.5f * window_average;
8001bf8: 687b ldr r3, [r7, #4]
8001bfa: 6bdb ldr r3, [r3, #60] @ 0x3c
8001bfc: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
8001c00: 4618 mov r0, r3
8001c02: f7fe ff4f bl 8000aa4 <__aeabi_fmul>
8001c06: 4603 mov r3, r0
8001c08: 461c mov r4, r3
8001c0a: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
8001c0e: 68b8 ldr r0, [r7, #8]
8001c10: f7fe ff48 bl 8000aa4 <__aeabi_fmul>
8001c14: 4603 mov r3, r0
8001c16: 4619 mov r1, r3
8001c18: 4620 mov r0, r4
8001c1a: f7fe fe3b bl 8000894 <__addsf3>
8001c1e: 4603 mov r3, r0
8001c20: 461a mov r2, r3
8001c22: 687b ldr r3, [r7, #4]
8001c24: 645a str r2, [r3, #68] @ 0x44
ch->value_valid = 1;
8001c26: 687b ldr r3, [r7, #4]
8001c28: 2201 movs r2, #1
8001c2a: f883 2048 strb.w r2, [r3, #72] @ 0x48
8001c2e: e000 b.n 8001c32 <ADS1015_Process_Sample+0x11e>
return; /* still collecting the burst, nothing else to do */
8001c30: bf00 nop
}
8001c32: 3714 adds r7, #20
8001c34: 46bd mov sp, r7
8001c36: bd90 pop {r4, r7, pc}
8001c38: 3e99999a .word 0x3e99999a
8001c3c: 3f333333 .word 0x3f333333
08001c40 <ADS1015_pH_NewSample>:
/* PUBLIC FUNCTIONS - ONE PER CHANNEL */
/* ---------------------------------------------------------------------- */
void ADS1015_pH_NewSample(float raw)
{
8001c40: b580 push {r7, lr}
8001c42: b082 sub sp, #8
8001c44: af00 add r7, sp, #0
8001c46: 6078 str r0, [r7, #4]
ADS1015_Process_Sample(&g_ph_filter, raw);
8001c48: 6879 ldr r1, [r7, #4]
8001c4a: 4803 ldr r0, [pc, #12] @ (8001c58 <ADS1015_pH_NewSample+0x18>)
8001c4c: f7ff ff62 bl 8001b14 <ADS1015_Process_Sample>
}
8001c50: bf00 nop
8001c52: 3708 adds r7, #8
8001c54: 46bd mov sp, r7
8001c56: bd80 pop {r7, pc}
8001c58: 2000022c .word 0x2000022c
08001c5c <digital_outputs_init>:
* @brief Initializes the GPIO hardware and sets initial states.
* @note This function replaces the handle-based init.
* @retval None
*/
void digital_outputs_init(void)
{
8001c5c: b580 push {r7, lr}
8001c5e: b086 sub sp, #24
8001c60: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001c62: 1d3b adds r3, r7, #4
8001c64: 2200 movs r2, #0
8001c66: 601a str r2, [r3, #0]
8001c68: 605a str r2, [r3, #4]
8001c6a: 609a str r2, [r3, #8]
8001c6c: 60da str r2, [r3, #12]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001c6e: 2300 movs r3, #0
8001c70: 617b str r3, [r7, #20]
8001c72: e029 b.n 8001cc8 <digital_outputs_init+0x6c>
GPIO_InitStruct.Pin = output_pins[i].pin;
8001c74: 4a18 ldr r2, [pc, #96] @ (8001cd8 <digital_outputs_init+0x7c>)
8001c76: 697b ldr r3, [r7, #20]
8001c78: 00db lsls r3, r3, #3
8001c7a: 4413 add r3, r2
8001c7c: 889b ldrh r3, [r3, #4]
8001c7e: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain
8001c80: 2311 movs r3, #17
8001c82: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c84: 2300 movs r3, #0
8001c86: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c88: 2302 movs r3, #2
8001c8a: 613b str r3, [r7, #16]
HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
8001c8c: 4a12 ldr r2, [pc, #72] @ (8001cd8 <digital_outputs_init+0x7c>)
8001c8e: 697b ldr r3, [r7, #20]
8001c90: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8001c94: 1d3a adds r2, r7, #4
8001c96: 4611 mov r1, r2
8001c98: 4618 mov r0, r3
8001c9a: f001 fb65 bl 8003368 <HAL_GPIO_Init>
// Force initial state to LOW (Reset)
HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET);
8001c9e: 4a0e ldr r2, [pc, #56] @ (8001cd8 <digital_outputs_init+0x7c>)
8001ca0: 697b ldr r3, [r7, #20]
8001ca2: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8001ca6: 4a0c ldr r2, [pc, #48] @ (8001cd8 <digital_outputs_init+0x7c>)
8001ca8: 697b ldr r3, [r7, #20]
8001caa: 00db lsls r3, r3, #3
8001cac: 4413 add r3, r2
8001cae: 889b ldrh r3, [r3, #4]
8001cb0: 2200 movs r2, #0
8001cb2: 4619 mov r1, r3
8001cb4: f001 fcf3 bl 800369e <HAL_GPIO_WritePin>
pin_states[i] = 0;
8001cb8: 4a08 ldr r2, [pc, #32] @ (8001cdc <digital_outputs_init+0x80>)
8001cba: 697b ldr r3, [r7, #20]
8001cbc: 4413 add r3, r2
8001cbe: 2200 movs r2, #0
8001cc0: 701a strb r2, [r3, #0]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001cc2: 697b ldr r3, [r7, #20]
8001cc4: 3301 adds r3, #1
8001cc6: 617b str r3, [r7, #20]
8001cc8: 697b ldr r3, [r7, #20]
8001cca: 2b07 cmp r3, #7
8001ccc: ddd2 ble.n 8001c74 <digital_outputs_init+0x18>
}
}
8001cce: bf00 nop
8001cd0: bf00 nop
8001cd2: 3718 adds r7, #24
8001cd4: 46bd mov sp, r7
8001cd6: bd80 pop {r7, pc}
8001cd8: 080066d0 .word 0x080066d0
8001cdc: 20000284 .word 0x20000284
08001ce0 <Flash_Load_Page>:
}
/**
* @brief Lê a página da Flash para a RAM.
*/
HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest) {
8001ce0: b580 push {r7, lr}
8001ce2: b082 sub sp, #8
8001ce4: af00 add r7, sp, #0
8001ce6: 6078 str r0, [r7, #4]
if (pDest == NULL) return HAL_ERROR;
8001ce8: 687b ldr r3, [r7, #4]
8001cea: 2b00 cmp r3, #0
8001cec: d101 bne.n 8001cf2 <Flash_Load_Page+0x12>
8001cee: 2301 movs r3, #1
8001cf0: e00d b.n 8001d0e <Flash_Load_Page+0x2e>
// Leitura direta por memcpy (A Flash é mapeada no espaço de endereçamento comum)
memcpy(pDest, (void *)FLASH_PAGE_ADDR, FLASH_PAGE_SIZE);
8001cf2: f44f 6280 mov.w r2, #1024 @ 0x400
8001cf6: 4908 ldr r1, [pc, #32] @ (8001d18 <Flash_Load_Page+0x38>)
8001cf8: 6878 ldr r0, [r7, #4]
8001cfa: f004 fc37 bl 800656c <memcpy>
// Validação da integridade através do Magic Number
if (pDest->magic_number != 0xDEADBEEF) {
8001cfe: 687b ldr r3, [r7, #4]
8001d00: 681b ldr r3, [r3, #0]
8001d02: 4a06 ldr r2, [pc, #24] @ (8001d1c <Flash_Load_Page+0x3c>)
8001d04: 4293 cmp r3, r2
8001d06: d001 beq.n 8001d0c <Flash_Load_Page+0x2c>
return HAL_ERROR;
8001d08: 2301 movs r3, #1
8001d0a: e000 b.n 8001d0e <Flash_Load_Page+0x2e>
}
return HAL_OK;
8001d0c: 2300 movs r3, #0
}
8001d0e: 4618 mov r0, r3
8001d10: 3708 adds r7, #8
8001d12: 46bd mov sp, r7
8001d14: bd80 pop {r7, pc}
8001d16: bf00 nop
8001d18: 0800fc00 .word 0x0800fc00
8001d1c: deadbeef .word 0xdeadbeef
08001d20 <MX_GPIO_Init>:
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
8001d20: b580 push {r7, lr}
8001d22: b088 sub sp, #32
8001d24: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001d26: f107 0310 add.w r3, r7, #16
8001d2a: 2200 movs r2, #0
8001d2c: 601a str r2, [r3, #0]
8001d2e: 605a str r2, [r3, #4]
8001d30: 609a str r2, [r3, #8]
8001d32: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8001d34: 4b46 ldr r3, [pc, #280] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d36: 699b ldr r3, [r3, #24]
8001d38: 4a45 ldr r2, [pc, #276] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d3a: f043 0310 orr.w r3, r3, #16
8001d3e: 6193 str r3, [r2, #24]
8001d40: 4b43 ldr r3, [pc, #268] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d42: 699b ldr r3, [r3, #24]
8001d44: f003 0310 and.w r3, r3, #16
8001d48: 60fb str r3, [r7, #12]
8001d4a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001d4c: 4b40 ldr r3, [pc, #256] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d4e: 699b ldr r3, [r3, #24]
8001d50: 4a3f ldr r2, [pc, #252] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d52: f043 0320 orr.w r3, r3, #32
8001d56: 6193 str r3, [r2, #24]
8001d58: 4b3d ldr r3, [pc, #244] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d5a: 699b ldr r3, [r3, #24]
8001d5c: f003 0320 and.w r3, r3, #32
8001d60: 60bb str r3, [r7, #8]
8001d62: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001d64: 4b3a ldr r3, [pc, #232] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d66: 699b ldr r3, [r3, #24]
8001d68: 4a39 ldr r2, [pc, #228] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d6a: f043 0304 orr.w r3, r3, #4
8001d6e: 6193 str r3, [r2, #24]
8001d70: 4b37 ldr r3, [pc, #220] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d72: 699b ldr r3, [r3, #24]
8001d74: f003 0304 and.w r3, r3, #4
8001d78: 607b str r3, [r7, #4]
8001d7a: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001d7c: 4b34 ldr r3, [pc, #208] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d7e: 699b ldr r3, [r3, #24]
8001d80: 4a33 ldr r2, [pc, #204] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d82: f043 0308 orr.w r3, r3, #8
8001d86: 6193 str r3, [r2, #24]
8001d88: 4b31 ldr r3, [pc, #196] @ (8001e50 <MX_GPIO_Init+0x130>)
8001d8a: 699b ldr r3, [r3, #24]
8001d8c: f003 0308 and.w r3, r3, #8
8001d90: 603b str r3, [r7, #0]
8001d92: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
8001d94: 2200 movs r2, #0
8001d96: f44f 4160 mov.w r1, #57344 @ 0xe000
8001d9a: 482e ldr r0, [pc, #184] @ (8001e54 <MX_GPIO_Init+0x134>)
8001d9c: f001 fc7f bl 800369e <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
8001da0: 2200 movs r2, #0
8001da2: f240 3137 movw r1, #823 @ 0x337
8001da6: 482c ldr r0, [pc, #176] @ (8001e58 <MX_GPIO_Init+0x138>)
8001da8: f001 fc79 bl 800369e <HAL_GPIO_WritePin>
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
8001dac: 2200 movs r2, #0
8001dae: f44f 5180 mov.w r1, #4096 @ 0x1000
8001db2: 482a ldr r0, [pc, #168] @ (8001e5c <MX_GPIO_Init+0x13c>)
8001db4: f001 fc73 bl 800369e <HAL_GPIO_WritePin>
/*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
8001db8: f44f 4360 mov.w r3, #57344 @ 0xe000
8001dbc: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001dbe: 2311 movs r3, #17
8001dc0: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001dc2: 2300 movs r3, #0
8001dc4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001dc6: 2302 movs r3, #2
8001dc8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001dca: f107 0310 add.w r3, r7, #16
8001dce: 4619 mov r1, r3
8001dd0: 4820 ldr r0, [pc, #128] @ (8001e54 <MX_GPIO_Init+0x134>)
8001dd2: f001 fac9 bl 8003368 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
PG_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
8001dd6: f648 13fc movw r3, #35324 @ 0x89fc
8001dda: 613b str r3, [r7, #16]
|SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
|PG_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001ddc: 2300 movs r3, #0
8001dde: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001de0: 2301 movs r3, #1
8001de2: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001de4: f107 0310 add.w r3, r7, #16
8001de8: 4619 mov r1, r3
8001dea: 481c ldr r0, [pc, #112] @ (8001e5c <MX_GPIO_Init+0x13c>)
8001dec: f001 fabc bl 8003368 <HAL_GPIO_Init>
/*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
8001df0: f240 3337 movw r3, #823 @ 0x337
8001df4: 613b str r3, [r7, #16]
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001df6: 2311 movs r3, #17
8001df8: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001dfa: 2300 movs r3, #0
8001dfc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001dfe: 2302 movs r3, #2
8001e00: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001e02: f107 0310 add.w r3, r7, #16
8001e06: 4619 mov r1, r3
8001e08: 4813 ldr r0, [pc, #76] @ (8001e58 <MX_GPIO_Init+0x138>)
8001e0a: f001 faad bl 8003368 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin
Calib_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin
8001e0e: f24f 0308 movw r3, #61448 @ 0xf008
8001e12: 613b str r3, [r7, #16]
|Calib_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001e14: 2300 movs r3, #0
8001e16: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001e18: 2301 movs r3, #1
8001e1a: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001e1c: f107 0310 add.w r3, r7, #16
8001e20: 4619 mov r1, r3
8001e22: 480d ldr r0, [pc, #52] @ (8001e58 <MX_GPIO_Init+0x138>)
8001e24: f001 faa0 bl 8003368 <HAL_GPIO_Init>
/*Configure GPIO pin : TX_EN_RS485_Pin */
GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
8001e28: f44f 5380 mov.w r3, #4096 @ 0x1000
8001e2c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001e2e: 2301 movs r3, #1
8001e30: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e32: 2300 movs r3, #0
8001e34: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001e36: 2302 movs r3, #2
8001e38: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
8001e3a: f107 0310 add.w r3, r7, #16
8001e3e: 4619 mov r1, r3
8001e40: 4806 ldr r0, [pc, #24] @ (8001e5c <MX_GPIO_Init+0x13c>)
8001e42: f001 fa91 bl 8003368 <HAL_GPIO_Init>
}
8001e46: bf00 nop
8001e48: 3720 adds r7, #32
8001e4a: 46bd mov sp, r7
8001e4c: bd80 pop {r7, pc}
8001e4e: bf00 nop
8001e50: 40021000 .word 0x40021000
8001e54: 40011000 .word 0x40011000
8001e58: 40010c00 .word 0x40010c00
8001e5c: 40010800 .word 0x40010800
08001e60 <MX_I2C1_Init>:
I2C_HandleTypeDef hi2c1;
I2C_HandleTypeDef hi2c2;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
8001e60: b580 push {r7, lr}
8001e62: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8001e64: 4b12 ldr r3, [pc, #72] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e66: 4a13 ldr r2, [pc, #76] @ (8001eb4 <MX_I2C1_Init+0x54>)
8001e68: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
8001e6a: 4b11 ldr r3, [pc, #68] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e6c: 4a12 ldr r2, [pc, #72] @ (8001eb8 <MX_I2C1_Init+0x58>)
8001e6e: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
8001e70: 4b0f ldr r3, [pc, #60] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e72: 2200 movs r2, #0
8001e74: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
8001e76: 4b0e ldr r3, [pc, #56] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e78: 2200 movs r2, #0
8001e7a: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8001e7c: 4b0c ldr r3, [pc, #48] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e7e: f44f 4280 mov.w r2, #16384 @ 0x4000
8001e82: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001e84: 4b0a ldr r3, [pc, #40] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e86: 2200 movs r2, #0
8001e88: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
8001e8a: 4b09 ldr r3, [pc, #36] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e8c: 2200 movs r2, #0
8001e8e: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8001e90: 4b07 ldr r3, [pc, #28] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e92: 2200 movs r2, #0
8001e94: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8001e96: 4b06 ldr r3, [pc, #24] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e98: 2200 movs r2, #0
8001e9a: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8001e9c: 4804 ldr r0, [pc, #16] @ (8001eb0 <MX_I2C1_Init+0x50>)
8001e9e: f001 fc2f bl 8003700 <HAL_I2C_Init>
8001ea2: 4603 mov r3, r0
8001ea4: 2b00 cmp r3, #0
8001ea6: d001 beq.n 8001eac <MX_I2C1_Init+0x4c>
{
Error_Handler();
8001ea8: f000 fb7c bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8001eac: bf00 nop
8001eae: bd80 pop {r7, pc}
8001eb0: 2000068c .word 0x2000068c
8001eb4: 40005400 .word 0x40005400
8001eb8: 000186a0 .word 0x000186a0
08001ebc <MX_I2C2_Init>:
/* I2C2 init function */
void MX_I2C2_Init(void)
{
8001ebc: b580 push {r7, lr}
8001ebe: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
8001ec0: 4b12 ldr r3, [pc, #72] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ec2: 4a13 ldr r2, [pc, #76] @ (8001f10 <MX_I2C2_Init+0x54>)
8001ec4: 601a str r2, [r3, #0]
hi2c2.Init.ClockSpeed = 100000;
8001ec6: 4b11 ldr r3, [pc, #68] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ec8: 4a12 ldr r2, [pc, #72] @ (8001f14 <MX_I2C2_Init+0x58>)
8001eca: 605a str r2, [r3, #4]
hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
8001ecc: 4b0f ldr r3, [pc, #60] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ece: 2200 movs r2, #0
8001ed0: 609a str r2, [r3, #8]
hi2c2.Init.OwnAddress1 = 0;
8001ed2: 4b0e ldr r3, [pc, #56] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ed4: 2200 movs r2, #0
8001ed6: 60da str r2, [r3, #12]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8001ed8: 4b0c ldr r3, [pc, #48] @ (8001f0c <MX_I2C2_Init+0x50>)
8001eda: f44f 4280 mov.w r2, #16384 @ 0x4000
8001ede: 611a str r2, [r3, #16]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001ee0: 4b0a ldr r3, [pc, #40] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ee2: 2200 movs r2, #0
8001ee4: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2 = 0;
8001ee6: 4b09 ldr r3, [pc, #36] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ee8: 2200 movs r2, #0
8001eea: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8001eec: 4b07 ldr r3, [pc, #28] @ (8001f0c <MX_I2C2_Init+0x50>)
8001eee: 2200 movs r2, #0
8001ef0: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8001ef2: 4b06 ldr r3, [pc, #24] @ (8001f0c <MX_I2C2_Init+0x50>)
8001ef4: 2200 movs r2, #0
8001ef6: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
8001ef8: 4804 ldr r0, [pc, #16] @ (8001f0c <MX_I2C2_Init+0x50>)
8001efa: f001 fc01 bl 8003700 <HAL_I2C_Init>
8001efe: 4603 mov r3, r0
8001f00: 2b00 cmp r3, #0
8001f02: d001 beq.n 8001f08 <MX_I2C2_Init+0x4c>
{
Error_Handler();
8001f04: f000 fb4e bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
8001f08: bf00 nop
8001f0a: bd80 pop {r7, pc}
8001f0c: 200006e0 .word 0x200006e0
8001f10: 40005800 .word 0x40005800
8001f14: 000186a0 .word 0x000186a0
08001f18 <HAL_I2C_MspInit>:
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
8001f18: b580 push {r7, lr}
8001f1a: b08a sub sp, #40 @ 0x28
8001f1c: af00 add r7, sp, #0
8001f1e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001f20: f107 0318 add.w r3, r7, #24
8001f24: 2200 movs r2, #0
8001f26: 601a str r2, [r3, #0]
8001f28: 605a str r2, [r3, #4]
8001f2a: 609a str r2, [r3, #8]
8001f2c: 60da str r2, [r3, #12]
if(i2cHandle->Instance==I2C1)
8001f2e: 687b ldr r3, [r7, #4]
8001f30: 681b ldr r3, [r3, #0]
8001f32: 4a2b ldr r2, [pc, #172] @ (8001fe0 <HAL_I2C_MspInit+0xc8>)
8001f34: 4293 cmp r3, r2
8001f36: d124 bne.n 8001f82 <HAL_I2C_MspInit+0x6a>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8001f38: 4b2a ldr r3, [pc, #168] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f3a: 699b ldr r3, [r3, #24]
8001f3c: 4a29 ldr r2, [pc, #164] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f3e: f043 0308 orr.w r3, r3, #8
8001f42: 6193 str r3, [r2, #24]
8001f44: 4b27 ldr r3, [pc, #156] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f46: 699b ldr r3, [r3, #24]
8001f48: f003 0308 and.w r3, r3, #8
8001f4c: 617b str r3, [r7, #20]
8001f4e: 697b ldr r3, [r7, #20]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
8001f50: 23c0 movs r3, #192 @ 0xc0
8001f52: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001f54: 2312 movs r3, #18
8001f56: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f58: 2302 movs r3, #2
8001f5a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001f5c: f107 0318 add.w r3, r7, #24
8001f60: 4619 mov r1, r3
8001f62: 4821 ldr r0, [pc, #132] @ (8001fe8 <HAL_I2C_MspInit+0xd0>)
8001f64: f001 fa00 bl 8003368 <HAL_GPIO_Init>
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8001f68: 4b1e ldr r3, [pc, #120] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f6a: 69db ldr r3, [r3, #28]
8001f6c: 4a1d ldr r2, [pc, #116] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f6e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
8001f72: 61d3 str r3, [r2, #28]
8001f74: 4b1b ldr r3, [pc, #108] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f76: 69db ldr r3, [r3, #28]
8001f78: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001f7c: 613b str r3, [r7, #16]
8001f7e: 693b ldr r3, [r7, #16]
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
}
8001f80: e029 b.n 8001fd6 <HAL_I2C_MspInit+0xbe>
else if(i2cHandle->Instance==I2C2)
8001f82: 687b ldr r3, [r7, #4]
8001f84: 681b ldr r3, [r3, #0]
8001f86: 4a19 ldr r2, [pc, #100] @ (8001fec <HAL_I2C_MspInit+0xd4>)
8001f88: 4293 cmp r3, r2
8001f8a: d124 bne.n 8001fd6 <HAL_I2C_MspInit+0xbe>
__HAL_RCC_GPIOB_CLK_ENABLE();
8001f8c: 4b15 ldr r3, [pc, #84] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f8e: 699b ldr r3, [r3, #24]
8001f90: 4a14 ldr r2, [pc, #80] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f92: f043 0308 orr.w r3, r3, #8
8001f96: 6193 str r3, [r2, #24]
8001f98: 4b12 ldr r3, [pc, #72] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001f9a: 699b ldr r3, [r3, #24]
8001f9c: f003 0308 and.w r3, r3, #8
8001fa0: 60fb str r3, [r7, #12]
8001fa2: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
8001fa4: f44f 6340 mov.w r3, #3072 @ 0xc00
8001fa8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001faa: 2312 movs r3, #18
8001fac: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001fae: 2302 movs r3, #2
8001fb0: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001fb2: f107 0318 add.w r3, r7, #24
8001fb6: 4619 mov r1, r3
8001fb8: 480b ldr r0, [pc, #44] @ (8001fe8 <HAL_I2C_MspInit+0xd0>)
8001fba: f001 f9d5 bl 8003368 <HAL_GPIO_Init>
__HAL_RCC_I2C2_CLK_ENABLE();
8001fbe: 4b09 ldr r3, [pc, #36] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001fc0: 69db ldr r3, [r3, #28]
8001fc2: 4a08 ldr r2, [pc, #32] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001fc4: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8001fc8: 61d3 str r3, [r2, #28]
8001fca: 4b06 ldr r3, [pc, #24] @ (8001fe4 <HAL_I2C_MspInit+0xcc>)
8001fcc: 69db ldr r3, [r3, #28]
8001fce: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001fd2: 60bb str r3, [r7, #8]
8001fd4: 68bb ldr r3, [r7, #8]
}
8001fd6: bf00 nop
8001fd8: 3728 adds r7, #40 @ 0x28
8001fda: 46bd mov sp, r7
8001fdc: bd80 pop {r7, pc}
8001fde: bf00 nop
8001fe0: 40005400 .word 0x40005400
8001fe4: 40021000 .word 0x40021000
8001fe8: 40010c00 .word 0x40010c00
8001fec: 40005800 .word 0x40005800
08001ff0 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8001ff0: b580 push {r7, lr}
8001ff2: b08e sub sp, #56 @ 0x38
8001ff4: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
HAL_StatusTypeDef status0,status1;
// Variables to store previous LED states
uint8_t previous_green_state = 0;
8001ff6: 2300 movs r3, #0
8001ff8: f887 3037 strb.w r3, [r7, #55] @ 0x37
uint8_t previous_red_state = 0;
8001ffc: 2300 movs r3, #0
8001ffe: f887 3036 strb.w r3, [r7, #54] @ 0x36
// Variables for timing
uint32_t previous_millis_green = 0;
8002002: 2300 movs r3, #0
8002004: 633b str r3, [r7, #48] @ 0x30
uint32_t previous_millis_red = 0;
8002006: 2300 movs r3, #0
8002008: 62fb str r3, [r7, #44] @ 0x2c
/*! Temporary variables */
uint8_t tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
800200a: f107 0308 add.w r3, r7, #8
800200e: 2200 movs r2, #0
8002010: 601a str r2, [r3, #0]
8002012: 605a str r2, [r3, #4]
8002014: 811a strh r2, [r3, #8]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8002016: f000 fd4f bl 8002ab8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800201a: f000 f947 bl 80022ac <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800201e: f7ff fe7f bl 8001d20 <MX_GPIO_Init>
MX_ADC1_Init();
8002022: f7ff fae5 bl 80015f0 <MX_ADC1_Init>
MX_ADC2_Init();
8002026: f7ff fb21 bl 800166c <MX_ADC2_Init>
MX_I2C1_Init();
800202a: f7ff ff19 bl 8001e60 <MX_I2C1_Init>
MX_I2C2_Init();
800202e: f7ff ff45 bl 8001ebc <MX_I2C2_Init>
MX_USART1_UART_Init();
8002032: f000 fc9d bl 8002970 <MX_USART1_UART_Init>
MX_TIM3_Init();
8002036: f000 fc27 bl 8002888 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
Flash_Load_Page(&flash_data);
800203a: 488b ldr r0, [pc, #556] @ (8002268 <main+0x278>)
800203c: f7ff fe50 bl 8001ce0 <Flash_Load_Page>
HAL_TIM_Base_Start_IT(&htim3);
8002040: 488a ldr r0, [pc, #552] @ (800226c <main+0x27c>)
8002042: f003 f8a9 bl 8005198 <HAL_TIM_Base_Start_IT>
/*
HAL_ADCEx_Calibration_Start(&hadc1);
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2); // Internal Temperature conversion
*/
digital_outputs_init();
8002046: f7ff fe09 bl 8001c5c <digital_outputs_init>
// Initialize RS-485 driver
rs485_init();
800204a: f000 fabd bl 80025c8 <rs485_init>
ADS1015(&i2c_ads1015, &hi2c1, ADS1015_ADDR_GND);
800204e: 2290 movs r2, #144 @ 0x90
8002050: 4987 ldr r1, [pc, #540] @ (8002270 <main+0x280>)
8002052: 4888 ldr r0, [pc, #544] @ (8002274 <main+0x284>)
8002054: f7ff fbf9 bl 800184a <ADS1015>
ADG715_ResetChannels();
8002058: f7ff faa2 bl 80015a0 <ADG715_ResetChannels>
// Start CE and RTD Measurement
AD5934_Init();
800205c: f7fe ff78 bl 8000f50 <AD5934_Init>
*/
while (1)
{
AD5934_Process_System();
8002060: f7ff f800 bl 8001064 <AD5934_Process_System>
ADS1015_Process_System();
8002064: f7ff fc0e bl 8001884 <ADS1015_Process_System>
current_millis = g_ms_counter;
8002068: 4b83 ldr r3, [pc, #524] @ (8002278 <main+0x288>)
800206a: 681b ldr r3, [r3, #0]
800206c: 62bb str r3, [r7, #40] @ 0x28
// Piscar LED verde em PB5 a cada 0,5 segundos
if ((current_millis - previous_millis_green) >= 500)
800206e: 6aba ldr r2, [r7, #40] @ 0x28
8002070: 6b3b ldr r3, [r7, #48] @ 0x30
8002072: 1ad3 subs r3, r2, r3
8002074: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
8002078: d31b bcc.n 80020b2 <main+0xc2>
{
previous_millis_green = current_millis;
800207a: 6abb ldr r3, [r7, #40] @ 0x28
800207c: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_5);
800207e: 2120 movs r1, #32
8002080: 487e ldr r0, [pc, #504] @ (800227c <main+0x28c>)
8002082: f001 fb24 bl 80036ce <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_green_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_5);
8002086: 2120 movs r1, #32
8002088: 487c ldr r0, [pc, #496] @ (800227c <main+0x28c>)
800208a: f001 faf1 bl 8003670 <HAL_GPIO_ReadPin>
800208e: 4603 mov r3, r0
8002090: f887 3027 strb.w r3, [r7, #39] @ 0x27
if (current_green_state != previous_green_state)
8002094: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
8002098: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
800209c: 429a cmp r2, r3
800209e: d008 beq.n 80020b2 <main+0xc2>
{
previous_green_state = current_green_state;
80020a0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80020a4: f887 3037 strb.w r3, [r7, #55] @ 0x37
uint8_t led_data[2] = {0x01, current_green_state}; // Command 0x01 for green LED
80020a8: 2301 movs r3, #1
80020aa: 713b strb r3, [r7, #4]
80020ac: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80020b0: 717b strb r3, [r7, #5]
*/
}
// Piscar LED vermelho em PB4 a cada 1 segundo
if ((current_millis - previous_millis_red) >= 1000)
80020b2: 6aba ldr r2, [r7, #40] @ 0x28
80020b4: 6afb ldr r3, [r7, #44] @ 0x2c
80020b6: 1ad3 subs r3, r2, r3
80020b8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
80020bc: d3d0 bcc.n 8002060 <main+0x70>
{
previous_millis_red = current_millis;
80020be: 6abb ldr r3, [r7, #40] @ 0x28
80020c0: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4);
80020c2: 2110 movs r1, #16
80020c4: 486d ldr r0, [pc, #436] @ (800227c <main+0x28c>)
80020c6: f001 fb02 bl 80036ce <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_red_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_4);
80020ca: 2110 movs r1, #16
80020cc: 486b ldr r0, [pc, #428] @ (800227c <main+0x28c>)
80020ce: f001 facf bl 8003670 <HAL_GPIO_ReadPin>
80020d2: 4603 mov r3, r0
80020d4: f887 3026 strb.w r3, [r7, #38] @ 0x26
if (current_red_state != previous_red_state)
80020d8: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
80020dc: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
80020e0: 429a cmp r2, r3
80020e2: d008 beq.n 80020f6 <main+0x106>
{
previous_red_state = current_red_state;
80020e4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
80020e8: f887 3036 strb.w r3, [r7, #54] @ 0x36
uint8_t led_data[2] = {0x02, current_red_state}; // Command 0x02 for red LED
80020ec: 2302 movs r3, #2
80020ee: 703b strb r3, [r7, #0]
80020f0: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
80020f4: 707b strb r3, [r7, #1]
}
if (g_rtd_filter.value_valid)
80020f6: 4b62 ldr r3, [pc, #392] @ (8002280 <main+0x290>)
80020f8: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
80020fc: 2b00 cmp r3, #0
80020fe: d033 beq.n 8002168 <main+0x178>
{
float rtd_final = g_rtd_filter.filtered_value;
8002100: 4b5f ldr r3, [pc, #380] @ (8002280 <main+0x290>)
8002102: 6cdb ldr r3, [r3, #76] @ 0x4c
8002104: 623b str r3, [r7, #32]
status1 = rs485_send_broadcast(tm_t, strlen((char*)tm_t));
8002106: 485f ldr r0, [pc, #380] @ (8002284 <main+0x294>)
8002108: f7fe f820 bl 800014c <strlen>
800210c: 4603 mov r3, r0
800210e: b29b uxth r3, r3
8002110: 4619 mov r1, r3
8002112: 485c ldr r0, [pc, #368] @ (8002284 <main+0x294>)
8002114: f000 fa84 bl 8002620 <rs485_send_broadcast>
8002118: 4603 mov r3, r0
800211a: 77fb strb r3, [r7, #31]
//temperature_RTD = AD5934_GetTemperature(refResistance);
FloatToString(tempString, rtd_final);
800211c: 6a38 ldr r0, [r7, #32]
800211e: f7fe faab bl 8000678 <__aeabi_f2d>
8002122: 4602 mov r2, r0
8002124: 460b mov r3, r1
8002126: f107 0108 add.w r1, r7, #8
800212a: 4608 mov r0, r1
800212c: f000 f90e bl 800234c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
8002130: f107 0308 add.w r3, r7, #8
8002134: 4618 mov r0, r3
8002136: f7fe f809 bl 800014c <strlen>
800213a: 4603 mov r3, r0
800213c: b29b uxth r3, r3
800213e: 3b01 subs r3, #1
8002140: b29a uxth r2, r3
8002142: f107 0308 add.w r3, r7, #8
8002146: 4611 mov r1, r2
8002148: 4618 mov r0, r3
800214a: f000 fa69 bl 8002620 <rs485_send_broadcast>
800214e: 4603 mov r3, r0
8002150: 77bb strb r3, [r7, #30]
status1 = rs485_send_broadcast(newline_temp, strlen((char*)newline_temp));
8002152: 484d ldr r0, [pc, #308] @ (8002288 <main+0x298>)
8002154: f7fd fffa bl 800014c <strlen>
8002158: 4603 mov r3, r0
800215a: b29b uxth r3, r3
800215c: 4619 mov r1, r3
800215e: 484a ldr r0, [pc, #296] @ (8002288 <main+0x298>)
8002160: f000 fa5e bl 8002620 <rs485_send_broadcast>
8002164: 4603 mov r3, r0
8002166: 77fb strb r3, [r7, #31]
}
if (g_ec_filter.value_valid)
8002168: 4b48 ldr r3, [pc, #288] @ (800228c <main+0x29c>)
800216a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
800216e: 2b00 cmp r3, #0
8002170: d033 beq.n 80021da <main+0x1ea>
{
float ec_final = g_ec_filter.filtered_value;
8002172: 4b46 ldr r3, [pc, #280] @ (800228c <main+0x29c>)
8002174: 6cdb ldr r3, [r3, #76] @ 0x4c
8002176: 61bb str r3, [r7, #24]
status1 = rs485_send_broadcast(ad_t, strlen((char*)ad_t));
8002178: 4845 ldr r0, [pc, #276] @ (8002290 <main+0x2a0>)
800217a: f7fd ffe7 bl 800014c <strlen>
800217e: 4603 mov r3, r0
8002180: b29b uxth r3, r3
8002182: 4619 mov r1, r3
8002184: 4842 ldr r0, [pc, #264] @ (8002290 <main+0x2a0>)
8002186: f000 fa4b bl 8002620 <rs485_send_broadcast>
800218a: 4603 mov r3, r0
800218c: 77fb strb r3, [r7, #31]
//admittance_EC = AD5934_GetImpedance(temperature_RTD);
FloatToString(tempString, ec_final);
800218e: 69b8 ldr r0, [r7, #24]
8002190: f7fe fa72 bl 8000678 <__aeabi_f2d>
8002194: 4602 mov r2, r0
8002196: 460b mov r3, r1
8002198: f107 0108 add.w r1, r7, #8
800219c: 4608 mov r0, r1
800219e: f000 f8d5 bl 800234c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
80021a2: f107 0308 add.w r3, r7, #8
80021a6: 4618 mov r0, r3
80021a8: f7fd ffd0 bl 800014c <strlen>
80021ac: 4603 mov r3, r0
80021ae: b29b uxth r3, r3
80021b0: 3b01 subs r3, #1
80021b2: b29a uxth r2, r3
80021b4: f107 0308 add.w r3, r7, #8
80021b8: 4611 mov r1, r2
80021ba: 4618 mov r0, r3
80021bc: f000 fa30 bl 8002620 <rs485_send_broadcast>
80021c0: 4603 mov r3, r0
80021c2: 77bb strb r3, [r7, #30]
status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi));
80021c4: 4833 ldr r0, [pc, #204] @ (8002294 <main+0x2a4>)
80021c6: f7fd ffc1 bl 800014c <strlen>
80021ca: 4603 mov r3, r0
80021cc: b29b uxth r3, r3
80021ce: 4619 mov r1, r3
80021d0: 4830 ldr r0, [pc, #192] @ (8002294 <main+0x2a4>)
80021d2: f000 fa25 bl 8002620 <rs485_send_broadcast>
80021d6: 4603 mov r3, r0
80021d8: 77fb strb r3, [r7, #31]
}
if (g_ref_filter.value_valid)
80021da: 4b2f ldr r3, [pc, #188] @ (8002298 <main+0x2a8>)
80021dc: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
80021e0: 2b00 cmp r3, #0
80021e2: f43f af3d beq.w 8002060 <main+0x70>
{
//float reference_final = g_ref_filter.filtered_value;
status1 = rs485_send_broadcast(ph_t, strlen((char*)ph_t));
80021e6: 482d ldr r0, [pc, #180] @ (800229c <main+0x2ac>)
80021e8: f7fd ffb0 bl 800014c <strlen>
80021ec: 4603 mov r3, r0
80021ee: b29b uxth r3, r3
80021f0: 4619 mov r1, r3
80021f2: 482a ldr r0, [pc, #168] @ (800229c <main+0x2ac>)
80021f4: f000 fa14 bl 8002620 <rs485_send_broadcast>
80021f8: 4603 mov r3, r0
80021fa: 77fb strb r3, [r7, #31]
ph_compensated = g_ph_filter.filtered_value;
80021fc: 4b28 ldr r3, [pc, #160] @ (80022a0 <main+0x2b0>)
80021fe: 6c5b ldr r3, [r3, #68] @ 0x44
8002200: 617b str r3, [r7, #20]
FloatToString(tempString, ph_compensated);
8002202: 6978 ldr r0, [r7, #20]
8002204: f7fe fa38 bl 8000678 <__aeabi_f2d>
8002208: 4602 mov r2, r0
800220a: 460b mov r3, r1
800220c: f107 0108 add.w r1, r7, #8
8002210: 4608 mov r0, r1
8002212: f000 f89b bl 800234c <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
8002216: f107 0308 add.w r3, r7, #8
800221a: 4618 mov r0, r3
800221c: f7fd ff96 bl 800014c <strlen>
8002220: 4603 mov r3, r0
8002222: b29b uxth r3, r3
8002224: 3b01 subs r3, #1
8002226: b29a uxth r2, r3
8002228: f107 0308 add.w r3, r7, #8
800222c: 4611 mov r1, r2
800222e: 4618 mov r0, r3
8002230: f000 f9f6 bl 8002620 <rs485_send_broadcast>
8002234: 4603 mov r3, r0
8002236: 77bb strb r3, [r7, #30]
status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph));
8002238: 481a ldr r0, [pc, #104] @ (80022a4 <main+0x2b4>)
800223a: f7fd ff87 bl 800014c <strlen>
800223e: 4603 mov r3, r0
8002240: b29b uxth r3, r3
8002242: 4619 mov r1, r3
8002244: 4817 ldr r0, [pc, #92] @ (80022a4 <main+0x2b4>)
8002246: f000 f9eb bl 8002620 <rs485_send_broadcast>
800224a: 4603 mov r3, r0
800224c: 77fb strb r3, [r7, #31]
status1 = rs485_send_broadcast(newline, strlen((char*)newline));
800224e: 4816 ldr r0, [pc, #88] @ (80022a8 <main+0x2b8>)
8002250: f7fd ff7c bl 800014c <strlen>
8002254: 4603 mov r3, r0
8002256: b29b uxth r3, r3
8002258: 4619 mov r1, r3
800225a: 4813 ldr r0, [pc, #76] @ (80022a8 <main+0x2b8>)
800225c: f000 f9e0 bl 8002620 <rs485_send_broadcast>
8002260: 4603 mov r3, r0
8002262: 77fb strb r3, [r7, #31]
AD5934_Process_System();
8002264: e6fc b.n 8002060 <main+0x70>
8002266: bf00 nop
8002268: 2000028c .word 0x2000028c
800226c: 20000780 .word 0x20000780
8002270: 2000068c .word 0x2000068c
8002274: 2000021c .word 0x2000021c
8002278: 200000b4 .word 0x200000b4
800227c: 40010c00 .word 0x40010c00
8002280: 200000bc .word 0x200000bc
8002284: 20000030 .word 0x20000030
8002288: 20000018 .word 0x20000018
800228c: 20000110 .word 0x20000110
8002290: 20000020 .word 0x20000020
8002294: 20000010 .word 0x20000010
8002298: 20000164 .word 0x20000164
800229c: 20000028 .word 0x20000028
80022a0: 2000022c .word 0x2000022c
80022a4: 20000008 .word 0x20000008
80022a8: 20000004 .word 0x20000004
080022ac <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80022ac: b580 push {r7, lr}
80022ae: b094 sub sp, #80 @ 0x50
80022b0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80022b2: f107 0328 add.w r3, r7, #40 @ 0x28
80022b6: 2228 movs r2, #40 @ 0x28
80022b8: 2100 movs r1, #0
80022ba: 4618 mov r0, r3
80022bc: f004 f924 bl 8006508 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80022c0: f107 0314 add.w r3, r7, #20
80022c4: 2200 movs r2, #0
80022c6: 601a str r2, [r3, #0]
80022c8: 605a str r2, [r3, #4]
80022ca: 609a str r2, [r3, #8]
80022cc: 60da str r2, [r3, #12]
80022ce: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80022d0: 1d3b adds r3, r7, #4
80022d2: 2200 movs r2, #0
80022d4: 601a str r2, [r3, #0]
80022d6: 605a str r2, [r3, #4]
80022d8: 609a str r2, [r3, #8]
80022da: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80022dc: 2301 movs r3, #1
80022de: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80022e0: f44f 3380 mov.w r3, #65536 @ 0x10000
80022e4: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80022e6: 2300 movs r3, #0
80022e8: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80022ea: f107 0328 add.w r3, r7, #40 @ 0x28
80022ee: 4618 mov r0, r3
80022f0: f002 fa3a bl 8004768 <HAL_RCC_OscConfig>
80022f4: 4603 mov r3, r0
80022f6: 2b00 cmp r3, #0
80022f8: d001 beq.n 80022fe <SystemClock_Config+0x52>
{
Error_Handler();
80022fa: f000 f953 bl 80025a4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80022fe: 230f movs r3, #15
8002300: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
8002302: 2301 movs r3, #1
8002304: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8002306: 2300 movs r3, #0
8002308: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800230a: 2300 movs r3, #0
800230c: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800230e: 2300 movs r3, #0
8002310: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8002312: f107 0314 add.w r3, r7, #20
8002316: 2100 movs r1, #0
8002318: 4618 mov r0, r3
800231a: f002 fca7 bl 8004c6c <HAL_RCC_ClockConfig>
800231e: 4603 mov r3, r0
8002320: 2b00 cmp r3, #0
8002322: d001 beq.n 8002328 <SystemClock_Config+0x7c>
{
Error_Handler();
8002324: f000 f93e bl 80025a4 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
8002328: 2302 movs r3, #2
800232a: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
800232c: f44f 4340 mov.w r3, #49152 @ 0xc000
8002330: 60fb str r3, [r7, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002332: 1d3b adds r3, r7, #4
8002334: 4618 mov r0, r3
8002336: f002 fe29 bl 8004f8c <HAL_RCCEx_PeriphCLKConfig>
800233a: 4603 mov r3, r0
800233c: 2b00 cmp r3, #0
800233e: d001 beq.n 8002344 <SystemClock_Config+0x98>
{
Error_Handler();
8002340: f000 f930 bl 80025a4 <Error_Handler>
}
}
8002344: bf00 nop
8002346: 3750 adds r7, #80 @ 0x50
8002348: 46bd mov sp, r7
800234a: bd80 pop {r7, pc}
0800234c <FloatToString>:
* @param val - value to be converted
*
* @return None.
*******************************************************************************/
void FloatToString(char *buf, double val)
{
800234c: b5b0 push {r4, r5, r7, lr}
800234e: b096 sub sp, #88 @ 0x58
8002350: af00 add r7, sp, #0
8002352: 60f8 str r0, [r7, #12]
8002354: e9c7 2300 strd r2, r3, [r7]
char temp[20]; // Buffer auxiliar para construção segura
int i = 0;
8002358: 2300 movs r3, #0
800235a: 657b str r3, [r7, #84] @ 0x54
// 1. Tratar sinal negativo
if (val < 0) {
800235c: f04f 0200 mov.w r2, #0
8002360: f04f 0300 mov.w r3, #0
8002364: e9d7 0100 ldrd r0, r1, [r7]
8002368: f7fe fa3e bl 80007e8 <__aeabi_dcmplt>
800236c: 4603 mov r3, r0
800236e: 2b00 cmp r3, #0
8002370: d00d beq.n 800238e <FloatToString+0x42>
temp[i++] = '-';
8002372: 6d7b ldr r3, [r7, #84] @ 0x54
8002374: 1c5a adds r2, r3, #1
8002376: 657a str r2, [r7, #84] @ 0x54
8002378: 3358 adds r3, #88 @ 0x58
800237a: 443b add r3, r7
800237c: 222d movs r2, #45 @ 0x2d
800237e: f803 2c30 strb.w r2, [r3, #-48]
val = -val;
8002382: 683c ldr r4, [r7, #0]
8002384: 687b ldr r3, [r7, #4]
8002386: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000
800238a: e9c7 4500 strd r4, r5, [r7]
}
// 2. Separar parte inteira e fracionária
long intPart = (long)val;
800238e: e9d7 0100 ldrd r0, r1, [r7]
8002392: f7fe fa51 bl 8000838 <__aeabi_d2iz>
8002396: 4603 mov r3, r0
8002398: 653b str r3, [r7, #80] @ 0x50
// Multiplicamos por 1000 para obter 3 casas decimais fixas
int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
800239a: 6d38 ldr r0, [r7, #80] @ 0x50
800239c: f7fe f95a bl 8000654 <__aeabi_i2d>
80023a0: 4602 mov r2, r0
80023a2: 460b mov r3, r1
80023a4: e9d7 0100 ldrd r0, r1, [r7]
80023a8: f7fe f806 bl 80003b8 <__aeabi_dsub>
80023ac: 4602 mov r2, r0
80023ae: 460b mov r3, r1
80023b0: 4610 mov r0, r2
80023b2: 4619 mov r1, r3
80023b4: f04f 0200 mov.w r2, #0
80023b8: 4b6a ldr r3, [pc, #424] @ (8002564 <FloatToString+0x218>)
80023ba: f7fd fecf bl 800015c <__aeabi_dmul>
80023be: 4602 mov r2, r0
80023c0: 460b mov r3, r1
80023c2: 4610 mov r0, r2
80023c4: 4619 mov r1, r3
80023c6: f04f 0200 mov.w r2, #0
80023ca: 4b67 ldr r3, [pc, #412] @ (8002568 <FloatToString+0x21c>)
80023cc: f7fd fff6 bl 80003bc <__adddf3>
80023d0: 4602 mov r2, r0
80023d2: 460b mov r3, r1
80023d4: 4610 mov r0, r2
80023d6: 4619 mov r1, r3
80023d8: f7fe fa2e bl 8000838 <__aeabi_d2iz>
80023dc: 4603 mov r3, r0
80023de: 63fb str r3, [r7, #60] @ 0x3c
// 3. Converter a parte inteira para o buffer temp
// Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
char intRev[12];
int j = 0;
80023e0: 2300 movs r3, #0
80023e2: 64fb str r3, [r7, #76] @ 0x4c
if (intPart == 0) {
80023e4: 6d3b ldr r3, [r7, #80] @ 0x50
80023e6: 2b00 cmp r3, #0
80023e8: d126 bne.n 8002438 <FloatToString+0xec>
intRev[j++] = '0';
80023ea: 6cfb ldr r3, [r7, #76] @ 0x4c
80023ec: 1c5a adds r2, r3, #1
80023ee: 64fa str r2, [r7, #76] @ 0x4c
80023f0: 3358 adds r3, #88 @ 0x58
80023f2: 443b add r3, r7
80023f4: 2230 movs r2, #48 @ 0x30
80023f6: f803 2c3c strb.w r2, [r3, #-60]
80023fa: e020 b.n 800243e <FloatToString+0xf2>
} else {
while (intPart > 0) {
intRev[j++] = (intPart % 10) + '0';
80023fc: 6d3a ldr r2, [r7, #80] @ 0x50
80023fe: 4b5b ldr r3, [pc, #364] @ (800256c <FloatToString+0x220>)
8002400: fb83 1302 smull r1, r3, r3, r2
8002404: 1099 asrs r1, r3, #2
8002406: 17d3 asrs r3, r2, #31
8002408: 1ac9 subs r1, r1, r3
800240a: 460b mov r3, r1
800240c: 009b lsls r3, r3, #2
800240e: 440b add r3, r1
8002410: 005b lsls r3, r3, #1
8002412: 1ad1 subs r1, r2, r3
8002414: b2ca uxtb r2, r1
8002416: 6cfb ldr r3, [r7, #76] @ 0x4c
8002418: 1c59 adds r1, r3, #1
800241a: 64f9 str r1, [r7, #76] @ 0x4c
800241c: 3230 adds r2, #48 @ 0x30
800241e: b2d2 uxtb r2, r2
8002420: 3358 adds r3, #88 @ 0x58
8002422: 443b add r3, r7
8002424: f803 2c3c strb.w r2, [r3, #-60]
intPart /= 10;
8002428: 6d3b ldr r3, [r7, #80] @ 0x50
800242a: 4a50 ldr r2, [pc, #320] @ (800256c <FloatToString+0x220>)
800242c: fb82 1203 smull r1, r2, r2, r3
8002430: 1092 asrs r2, r2, #2
8002432: 17db asrs r3, r3, #31
8002434: 1ad3 subs r3, r2, r3
8002436: 653b str r3, [r7, #80] @ 0x50
while (intPart > 0) {
8002438: 6d3b ldr r3, [r7, #80] @ 0x50
800243a: 2b00 cmp r3, #0
800243c: dcde bgt.n 80023fc <FloatToString+0xb0>
}
}
// Inverter a parte inteira de volta para o buffer principal
for (int k = j - 1; k >= 0; k--) {
800243e: 6cfb ldr r3, [r7, #76] @ 0x4c
8002440: 3b01 subs r3, #1
8002442: 64bb str r3, [r7, #72] @ 0x48
8002444: e00e b.n 8002464 <FloatToString+0x118>
temp[i++] = intRev[k];
8002446: 6d7b ldr r3, [r7, #84] @ 0x54
8002448: 1c5a adds r2, r3, #1
800244a: 657a str r2, [r7, #84] @ 0x54
800244c: f107 011c add.w r1, r7, #28
8002450: 6cba ldr r2, [r7, #72] @ 0x48
8002452: 440a add r2, r1
8002454: 7812 ldrb r2, [r2, #0]
8002456: 3358 adds r3, #88 @ 0x58
8002458: 443b add r3, r7
800245a: f803 2c30 strb.w r2, [r3, #-48]
for (int k = j - 1; k >= 0; k--) {
800245e: 6cbb ldr r3, [r7, #72] @ 0x48
8002460: 3b01 subs r3, #1
8002462: 64bb str r3, [r7, #72] @ 0x48
8002464: 6cbb ldr r3, [r7, #72] @ 0x48
8002466: 2b00 cmp r3, #0
8002468: daed bge.n 8002446 <FloatToString+0xfa>
}
// 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
temp[i++] = '.';
800246a: 6d7b ldr r3, [r7, #84] @ 0x54
800246c: 1c5a adds r2, r3, #1
800246e: 657a str r2, [r7, #84] @ 0x54
8002470: 3358 adds r3, #88 @ 0x58
8002472: 443b add r3, r7
8002474: 222e movs r2, #46 @ 0x2e
8002476: f803 2c30 strb.w r2, [r3, #-48]
// Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
int fracBuffer[3];
fracBuffer[2] = fracPart % 10; // Unidade
800247a: 6bf9 ldr r1, [r7, #60] @ 0x3c
800247c: 4b3b ldr r3, [pc, #236] @ (800256c <FloatToString+0x220>)
800247e: fb83 2301 smull r2, r3, r3, r1
8002482: 109a asrs r2, r3, #2
8002484: 17cb asrs r3, r1, #31
8002486: 1ad2 subs r2, r2, r3
8002488: 4613 mov r3, r2
800248a: 009b lsls r3, r3, #2
800248c: 4413 add r3, r2
800248e: 005b lsls r3, r3, #1
8002490: 1aca subs r2, r1, r3
8002492: 61ba str r2, [r7, #24]
fracBuffer[1] = (fracPart / 10) % 10; // Dezena
8002494: 6bfb ldr r3, [r7, #60] @ 0x3c
8002496: 4a35 ldr r2, [pc, #212] @ (800256c <FloatToString+0x220>)
8002498: fb82 1203 smull r1, r2, r2, r3
800249c: 1092 asrs r2, r2, #2
800249e: 17db asrs r3, r3, #31
80024a0: 1ad1 subs r1, r2, r3
80024a2: 4b32 ldr r3, [pc, #200] @ (800256c <FloatToString+0x220>)
80024a4: fb83 2301 smull r2, r3, r3, r1
80024a8: 109a asrs r2, r3, #2
80024aa: 17cb asrs r3, r1, #31
80024ac: 1ad2 subs r2, r2, r3
80024ae: 4613 mov r3, r2
80024b0: 009b lsls r3, r3, #2
80024b2: 4413 add r3, r2
80024b4: 005b lsls r3, r3, #1
80024b6: 1aca subs r2, r1, r3
80024b8: 617a str r2, [r7, #20]
fracBuffer[0] = (fracPart / 100) % 10; // Centena
80024ba: 6bfb ldr r3, [r7, #60] @ 0x3c
80024bc: 4a2c ldr r2, [pc, #176] @ (8002570 <FloatToString+0x224>)
80024be: fb82 1203 smull r1, r2, r2, r3
80024c2: 1152 asrs r2, r2, #5
80024c4: 17db asrs r3, r3, #31
80024c6: 1ad1 subs r1, r2, r3
80024c8: 4b28 ldr r3, [pc, #160] @ (800256c <FloatToString+0x220>)
80024ca: fb83 2301 smull r2, r3, r3, r1
80024ce: 109a asrs r2, r3, #2
80024d0: 17cb asrs r3, r1, #31
80024d2: 1ad2 subs r2, r2, r3
80024d4: 4613 mov r3, r2
80024d6: 009b lsls r3, r3, #2
80024d8: 4413 add r3, r2
80024da: 005b lsls r3, r3, #1
80024dc: 1aca subs r2, r1, r3
80024de: 613a str r2, [r7, #16]
for (int k = 2; k >= 0; k--) {
80024e0: 2302 movs r3, #2
80024e2: 647b str r3, [r7, #68] @ 0x44
80024e4: e012 b.n 800250c <FloatToString+0x1c0>
temp[i++] = fracBuffer[k] + '0';
80024e6: 6c7b ldr r3, [r7, #68] @ 0x44
80024e8: 009b lsls r3, r3, #2
80024ea: 3358 adds r3, #88 @ 0x58
80024ec: 443b add r3, r7
80024ee: f853 3c48 ldr.w r3, [r3, #-72]
80024f2: b2da uxtb r2, r3
80024f4: 6d7b ldr r3, [r7, #84] @ 0x54
80024f6: 1c59 adds r1, r3, #1
80024f8: 6579 str r1, [r7, #84] @ 0x54
80024fa: 3230 adds r2, #48 @ 0x30
80024fc: b2d2 uxtb r2, r2
80024fe: 3358 adds r3, #88 @ 0x58
8002500: 443b add r3, r7
8002502: f803 2c30 strb.w r2, [r3, #-48]
for (int k = 2; k >= 0; k--) {
8002506: 6c7b ldr r3, [r7, #68] @ 0x44
8002508: 3b01 subs r3, #1
800250a: 647b str r3, [r7, #68] @ 0x44
800250c: 6c7b ldr r3, [r7, #68] @ 0x44
800250e: 2b00 cmp r3, #0
8002510: dae9 bge.n 80024e6 <FloatToString+0x19a>
}
// 5. Finalizar a string com o caractere nulo
temp[i] = '\0';
8002512: f107 0228 add.w r2, r7, #40 @ 0x28
8002516: 6d7b ldr r3, [r7, #84] @ 0x54
8002518: 4413 add r3, r2
800251a: 2200 movs r2, #0
800251c: 701a strb r2, [r3, #0]
// 6. Copiar para o buffer de destino final (sem risco de lixo)
int destIdx = 0;
800251e: 2300 movs r3, #0
8002520: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
8002522: e00b b.n 800253c <FloatToString+0x1f0>
buf[destIdx] = temp[destIdx];
8002524: 6c3b ldr r3, [r7, #64] @ 0x40
8002526: 68fa ldr r2, [r7, #12]
8002528: 4413 add r3, r2
800252a: f107 0128 add.w r1, r7, #40 @ 0x28
800252e: 6c3a ldr r2, [r7, #64] @ 0x40
8002530: 440a add r2, r1
8002532: 7812 ldrb r2, [r2, #0]
8002534: 701a strb r2, [r3, #0]
destIdx++;
8002536: 6c3b ldr r3, [r7, #64] @ 0x40
8002538: 3301 adds r3, #1
800253a: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
800253c: f107 0228 add.w r2, r7, #40 @ 0x28
8002540: 6c3b ldr r3, [r7, #64] @ 0x40
8002542: 4413 add r3, r2
8002544: 781b ldrb r3, [r3, #0]
8002546: 2b00 cmp r3, #0
8002548: d002 beq.n 8002550 <FloatToString+0x204>
800254a: 6c3b ldr r3, [r7, #64] @ 0x40
800254c: 2b0e cmp r3, #14
800254e: dde9 ble.n 8002524 <FloatToString+0x1d8>
}
buf[destIdx] = '\0';
8002550: 6c3b ldr r3, [r7, #64] @ 0x40
8002552: 68fa ldr r2, [r7, #12]
8002554: 4413 add r3, r2
8002556: 2200 movs r2, #0
8002558: 701a strb r2, [r3, #0]
}
800255a: bf00 nop
800255c: 3758 adds r7, #88 @ 0x58
800255e: 46bd mov sp, r7
8002560: bdb0 pop {r4, r5, r7, pc}
8002562: bf00 nop
8002564: 408f4000 .word 0x408f4000
8002568: 3fe00000 .word 0x3fe00000
800256c: 66666667 .word 0x66666667
8002570: 51eb851f .word 0x51eb851f
08002574 <HAL_TIM_PeriodElapsedCallback>:
}
}
/* TIM3 Timer Interrupt */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002574: b480 push {r7}
8002576: b083 sub sp, #12
8002578: af00 add r7, sp, #0
800257a: 6078 str r0, [r7, #4]
if (htim->Instance == TIM3)
800257c: 687b ldr r3, [r7, #4]
800257e: 681b ldr r3, [r3, #0]
8002580: 4a06 ldr r2, [pc, #24] @ (800259c <HAL_TIM_PeriodElapsedCallback+0x28>)
8002582: 4293 cmp r3, r2
8002584: d104 bne.n 8002590 <HAL_TIM_PeriodElapsedCallback+0x1c>
{
g_ms_counter++; /* Relógio global do sistema */
8002586: 4b06 ldr r3, [pc, #24] @ (80025a0 <HAL_TIM_PeriodElapsedCallback+0x2c>)
8002588: 681b ldr r3, [r3, #0]
800258a: 3301 adds r3, #1
800258c: 4a04 ldr r2, [pc, #16] @ (80025a0 <HAL_TIM_PeriodElapsedCallback+0x2c>)
800258e: 6013 str r3, [r2, #0]
}
}
8002590: bf00 nop
8002592: 370c adds r7, #12
8002594: 46bd mov sp, r7
8002596: bc80 pop {r7}
8002598: 4770 bx lr
800259a: bf00 nop
800259c: 40000400 .word 0x40000400
80025a0: 200000b4 .word 0x200000b4
080025a4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80025a4: b480 push {r7}
80025a6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80025a8: b672 cpsid i
}
80025aa: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80025ac: bf00 nop
80025ae: e7fd b.n 80025ac <Error_Handler+0x8>
080025b0 <LL_GPIO_ReadInputPort>:
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
80025b0: b480 push {r7}
80025b2: b083 sub sp, #12
80025b4: af00 add r7, sp, #0
80025b6: 6078 str r0, [r7, #4]
return (READ_REG(GPIOx->IDR));
80025b8: 687b ldr r3, [r7, #4]
80025ba: 689b ldr r3, [r3, #8]
}
80025bc: 4618 mov r0, r3
80025be: 370c adds r7, #12
80025c0: 46bd mov sp, r7
80025c2: bc80 pop {r7}
80025c4: 4770 bx lr
...
080025c8 <rs485_init>:
/**
* @brief Initializes the RS-485 driver.
* @note This function configures GPIOs for address detection and USART1 for communication.
*/
void rs485_init(void)
{
80025c8: b580 push {r7, lr}
80025ca: af00 add r7, sp, #0
/* Configure GPIOs for address detection */
rs485_configure_gpio_address();
80025cc: f000 f864 bl 8002698 <rs485_configure_gpio_address>
/* Configure USART1 for RS-485 communication */
rs485_configure_usart1();
80025d0: f000 f8a8 bl 8002724 <rs485_configure_usart1>
/* Get the current device address from GPIOs */
device_address.full_address = rs485_get_address();
80025d4: f000 f808 bl 80025e8 <rs485_get_address>
80025d8: 4603 mov r3, r0
80025da: 461a mov r2, r3
80025dc: 4b01 ldr r3, [pc, #4] @ (80025e4 <rs485_init+0x1c>)
80025de: 709a strb r2, [r3, #2]
}
80025e0: bf00 nop
80025e2: bd80 pop {r7, pc}
80025e4: 20000734 .word 0x20000734
080025e8 <rs485_get_address>:
/**
* @brief Gets the current device address from GPIOs.
* @return The 8-bit device address.
*/
uint8_t rs485_get_address(void)
{
80025e8: b598 push {r3, r4, r7, lr}
80025ea: af00 add r7, sp, #0
return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
80025ec: 480a ldr r0, [pc, #40] @ (8002618 <rs485_get_address+0x30>)
80025ee: f7ff ffdf bl 80025b0 <LL_GPIO_ReadInputPort>
80025f2: 4603 mov r3, r0
80025f4: 0a1b lsrs r3, r3, #8
80025f6: b2db uxtb r3, r3
80025f8: f023 030f bic.w r3, r3, #15
80025fc: b2dc uxtb r4, r3
80025fe: 4807 ldr r0, [pc, #28] @ (800261c <rs485_get_address+0x34>)
8002600: f7ff ffd6 bl 80025b0 <LL_GPIO_ReadInputPort>
8002604: 4603 mov r3, r0
8002606: 089b lsrs r3, r3, #2
8002608: b2db uxtb r3, r3
800260a: f003 030f and.w r3, r3, #15
800260e: b2db uxtb r3, r3
8002610: 4323 orrs r3, r4
8002612: b2db uxtb r3, r3
}
8002614: 4618 mov r0, r3
8002616: bd98 pop {r3, r4, r7, pc}
8002618: 40010c00 .word 0x40010c00
800261c: 40010800 .word 0x40010800
08002620 <rs485_send_broadcast>:
* @param data Pointer to the data buffer.
* @param length Number of bytes to send.
* @retval HAL_OK on success, otherwise error code.
*/
HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
{
8002620: b580 push {r7, lr}
8002622: b084 sub sp, #16
8002624: af00 add r7, sp, #0
8002626: 6078 str r0, [r7, #4]
8002628: 460b mov r3, r1
800262a: 807b strh r3, [r7, #2]
/* Enable transmission mode */
rs485_enable_tx();
800262c: f000 f81c bl 8002668 <rs485_enable_tx>
/* Send the broadcast address (0x00) first */
uint8_t broadcast_address = 0x00;
8002630: 2300 movs r3, #0
8002632: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
8002634: f107 010e add.w r1, r7, #14
8002638: f04f 33ff mov.w r3, #4294967295
800263c: 2201 movs r2, #1
800263e: 4809 ldr r0, [pc, #36] @ (8002664 <rs485_send_broadcast+0x44>)
8002640: f003 f99c bl 800597c <HAL_UART_Transmit>
/* Send the data */
HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
8002644: 887a ldrh r2, [r7, #2]
8002646: f04f 33ff mov.w r3, #4294967295
800264a: 6879 ldr r1, [r7, #4]
800264c: 4805 ldr r0, [pc, #20] @ (8002664 <rs485_send_broadcast+0x44>)
800264e: f003 f995 bl 800597c <HAL_UART_Transmit>
8002652: 4603 mov r3, r0
8002654: 73fb strb r3, [r7, #15]
/* Disable transmission mode after sending */
rs485_disable_tx();
8002656: f000 f813 bl 8002680 <rs485_disable_tx>
return status;
800265a: 7bfb ldrb r3, [r7, #15]
}
800265c: 4618 mov r0, r3
800265e: 3710 adds r7, #16
8002660: 46bd mov sp, r7
8002662: bd80 pop {r7, pc}
8002664: 20000738 .word 0x20000738
08002668 <rs485_enable_tx>:
/**
* @brief Enables transmission mode on RS-485 transceiver.
*/
void rs485_enable_tx(void)
{
8002668: b580 push {r7, lr}
800266a: af00 add r7, sp, #0
/* Set TX EN pin high to enable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
800266c: 2201 movs r2, #1
800266e: f44f 5180 mov.w r1, #4096 @ 0x1000
8002672: 4802 ldr r0, [pc, #8] @ (800267c <rs485_enable_tx+0x14>)
8002674: f001 f813 bl 800369e <HAL_GPIO_WritePin>
}
8002678: bf00 nop
800267a: bd80 pop {r7, pc}
800267c: 40010800 .word 0x40010800
08002680 <rs485_disable_tx>:
/**
* @brief Disables transmission mode on RS-485 transceiver.
*/
void rs485_disable_tx(void)
{
8002680: b580 push {r7, lr}
8002682: af00 add r7, sp, #0
/* Set TX EN pin low to disable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
8002684: 2200 movs r2, #0
8002686: f44f 5180 mov.w r1, #4096 @ 0x1000
800268a: 4802 ldr r0, [pc, #8] @ (8002694 <rs485_disable_tx+0x14>)
800268c: f001 f807 bl 800369e <HAL_GPIO_WritePin>
}
8002690: bf00 nop
8002692: bd80 pop {r7, pc}
8002694: 40010800 .word 0x40010800
08002698 <rs485_configure_gpio_address>:
/**
* @brief Configures GPIOs for address detection.
*/
static void rs485_configure_gpio_address(void)
{
8002698: b580 push {r7, lr}
800269a: b086 sub sp, #24
800269c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800269e: f107 0308 add.w r3, r7, #8
80026a2: 2200 movs r2, #0
80026a4: 601a str r2, [r3, #0]
80026a6: 605a str r2, [r3, #4]
80026a8: 609a str r2, [r3, #8]
80026aa: 60da str r2, [r3, #12]
/* Enable clock for GPIOA and GPIOB */
__HAL_RCC_GPIOA_CLK_ENABLE();
80026ac: 4b1a ldr r3, [pc, #104] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026ae: 699b ldr r3, [r3, #24]
80026b0: 4a19 ldr r2, [pc, #100] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026b2: f043 0304 orr.w r3, r3, #4
80026b6: 6193 str r3, [r2, #24]
80026b8: 4b17 ldr r3, [pc, #92] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026ba: 699b ldr r3, [r3, #24]
80026bc: f003 0304 and.w r3, r3, #4
80026c0: 607b str r3, [r7, #4]
80026c2: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80026c4: 4b14 ldr r3, [pc, #80] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026c6: 699b ldr r3, [r3, #24]
80026c8: 4a13 ldr r2, [pc, #76] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026ca: f043 0308 orr.w r3, r3, #8
80026ce: 6193 str r3, [r2, #24]
80026d0: 4b11 ldr r3, [pc, #68] @ (8002718 <rs485_configure_gpio_address+0x80>)
80026d2: 699b ldr r3, [r3, #24]
80026d4: f003 0308 and.w r3, r3, #8
80026d8: 603b str r3, [r7, #0]
80026da: 683b ldr r3, [r7, #0]
/* Configure PA2-PA5 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
80026dc: 233c movs r3, #60 @ 0x3c
80026de: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80026e0: 2300 movs r3, #0
80026e2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80026e4: 2301 movs r3, #1
80026e6: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80026e8: f107 0308 add.w r3, r7, #8
80026ec: 4619 mov r1, r3
80026ee: 480b ldr r0, [pc, #44] @ (800271c <rs485_configure_gpio_address+0x84>)
80026f0: f000 fe3a bl 8003368 <HAL_GPIO_Init>
/* Configure PB12-PB15 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
80026f4: f44f 4370 mov.w r3, #61440 @ 0xf000
80026f8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80026fa: 2300 movs r3, #0
80026fc: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80026fe: 2301 movs r3, #1
8002700: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002702: f107 0308 add.w r3, r7, #8
8002706: 4619 mov r1, r3
8002708: 4805 ldr r0, [pc, #20] @ (8002720 <rs485_configure_gpio_address+0x88>)
800270a: f000 fe2d bl 8003368 <HAL_GPIO_Init>
}
800270e: bf00 nop
8002710: 3718 adds r7, #24
8002712: 46bd mov sp, r7
8002714: bd80 pop {r7, pc}
8002716: bf00 nop
8002718: 40021000 .word 0x40021000
800271c: 40010800 .word 0x40010800
8002720: 40010c00 .word 0x40010c00
08002724 <rs485_configure_usart1>:
/**
* @brief Configures USART1 for RS-485 communication.
*/
static void rs485_configure_usart1(void)
{
8002724: b580 push {r7, lr}
8002726: b082 sub sp, #8
8002728: af00 add r7, sp, #0
/* Enable clock for USART1 */
__HAL_RCC_USART1_CLK_ENABLE();
800272a: 4b18 ldr r3, [pc, #96] @ (800278c <rs485_configure_usart1+0x68>)
800272c: 699b ldr r3, [r3, #24]
800272e: 4a17 ldr r2, [pc, #92] @ (800278c <rs485_configure_usart1+0x68>)
8002730: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002734: 6193 str r3, [r2, #24]
8002736: 4b15 ldr r3, [pc, #84] @ (800278c <rs485_configure_usart1+0x68>)
8002738: 699b ldr r3, [r3, #24]
800273a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800273e: 607b str r3, [r7, #4]
8002740: 687b ldr r3, [r7, #4]
huart1.Instance = USART1;
8002742: 4b13 ldr r3, [pc, #76] @ (8002790 <rs485_configure_usart1+0x6c>)
8002744: 4a13 ldr r2, [pc, #76] @ (8002794 <rs485_configure_usart1+0x70>)
8002746: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */
8002748: 4b11 ldr r3, [pc, #68] @ (8002790 <rs485_configure_usart1+0x6c>)
800274a: f44f 5216 mov.w r2, #9600 @ 0x2580
800274e: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002750: 4b0f ldr r3, [pc, #60] @ (8002790 <rs485_configure_usart1+0x6c>)
8002752: 2200 movs r2, #0
8002754: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002756: 4b0e ldr r3, [pc, #56] @ (8002790 <rs485_configure_usart1+0x6c>)
8002758: 2200 movs r2, #0
800275a: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800275c: 4b0c ldr r3, [pc, #48] @ (8002790 <rs485_configure_usart1+0x6c>)
800275e: 2200 movs r2, #0
8002760: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002762: 4b0b ldr r3, [pc, #44] @ (8002790 <rs485_configure_usart1+0x6c>)
8002764: 220c movs r2, #12
8002766: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
8002768: 4b09 ldr r3, [pc, #36] @ (8002790 <rs485_configure_usart1+0x6c>)
800276a: 2200 movs r2, #0
800276c: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
800276e: 4b08 ldr r3, [pc, #32] @ (8002790 <rs485_configure_usart1+0x6c>)
8002770: 2200 movs r2, #0
8002772: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002774: 4806 ldr r0, [pc, #24] @ (8002790 <rs485_configure_usart1+0x6c>)
8002776: f003 f8b1 bl 80058dc <HAL_UART_Init>
800277a: 4603 mov r3, r0
800277c: 2b00 cmp r3, #0
800277e: d001 beq.n 8002784 <rs485_configure_usart1+0x60>
{
/* Initialization Error */
while(1);
8002780: bf00 nop
8002782: e7fd b.n 8002780 <rs485_configure_usart1+0x5c>
}
}
8002784: bf00 nop
8002786: 3708 adds r7, #8
8002788: 46bd mov sp, r7
800278a: bd80 pop {r7, pc}
800278c: 40021000 .word 0x40021000
8002790: 20000738 .word 0x20000738
8002794: 40013800 .word 0x40013800
08002798 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8002798: b480 push {r7}
800279a: b085 sub sp, #20
800279c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
800279e: 4b15 ldr r3, [pc, #84] @ (80027f4 <HAL_MspInit+0x5c>)
80027a0: 699b ldr r3, [r3, #24]
80027a2: 4a14 ldr r2, [pc, #80] @ (80027f4 <HAL_MspInit+0x5c>)
80027a4: f043 0301 orr.w r3, r3, #1
80027a8: 6193 str r3, [r2, #24]
80027aa: 4b12 ldr r3, [pc, #72] @ (80027f4 <HAL_MspInit+0x5c>)
80027ac: 699b ldr r3, [r3, #24]
80027ae: f003 0301 and.w r3, r3, #1
80027b2: 60bb str r3, [r7, #8]
80027b4: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
80027b6: 4b0f ldr r3, [pc, #60] @ (80027f4 <HAL_MspInit+0x5c>)
80027b8: 69db ldr r3, [r3, #28]
80027ba: 4a0e ldr r2, [pc, #56] @ (80027f4 <HAL_MspInit+0x5c>)
80027bc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80027c0: 61d3 str r3, [r2, #28]
80027c2: 4b0c ldr r3, [pc, #48] @ (80027f4 <HAL_MspInit+0x5c>)
80027c4: 69db ldr r3, [r3, #28]
80027c6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80027ca: 607b str r3, [r7, #4]
80027cc: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
80027ce: 4b0a ldr r3, [pc, #40] @ (80027f8 <HAL_MspInit+0x60>)
80027d0: 685b ldr r3, [r3, #4]
80027d2: 60fb str r3, [r7, #12]
80027d4: 68fb ldr r3, [r7, #12]
80027d6: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
80027da: 60fb str r3, [r7, #12]
80027dc: 68fb ldr r3, [r7, #12]
80027de: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80027e2: 60fb str r3, [r7, #12]
80027e4: 4a04 ldr r2, [pc, #16] @ (80027f8 <HAL_MspInit+0x60>)
80027e6: 68fb ldr r3, [r7, #12]
80027e8: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80027ea: bf00 nop
80027ec: 3714 adds r7, #20
80027ee: 46bd mov sp, r7
80027f0: bc80 pop {r7}
80027f2: 4770 bx lr
80027f4: 40021000 .word 0x40021000
80027f8: 40010000 .word 0x40010000
080027fc <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80027fc: b480 push {r7}
80027fe: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8002800: bf00 nop
8002802: e7fd b.n 8002800 <NMI_Handler+0x4>
08002804 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8002804: b480 push {r7}
8002806: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8002808: bf00 nop
800280a: e7fd b.n 8002808 <HardFault_Handler+0x4>
0800280c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800280c: b480 push {r7}
800280e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8002810: bf00 nop
8002812: e7fd b.n 8002810 <MemManage_Handler+0x4>
08002814 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8002814: b480 push {r7}
8002816: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8002818: bf00 nop
800281a: e7fd b.n 8002818 <BusFault_Handler+0x4>
0800281c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800281c: b480 push {r7}
800281e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8002820: bf00 nop
8002822: e7fd b.n 8002820 <UsageFault_Handler+0x4>
08002824 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8002824: b480 push {r7}
8002826: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8002828: bf00 nop
800282a: 46bd mov sp, r7
800282c: bc80 pop {r7}
800282e: 4770 bx lr
08002830 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8002830: b480 push {r7}
8002832: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8002834: bf00 nop
8002836: 46bd mov sp, r7
8002838: bc80 pop {r7}
800283a: 4770 bx lr
0800283c <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800283c: b480 push {r7}
800283e: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8002840: bf00 nop
8002842: 46bd mov sp, r7
8002844: bc80 pop {r7}
8002846: 4770 bx lr
08002848 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002848: b580 push {r7, lr}
800284a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800284c: f000 f97a bl 8002b44 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8002850: bf00 nop
8002852: bd80 pop {r7, pc}
08002854 <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
8002854: b580 push {r7, lr}
8002856: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
8002858: 4802 ldr r0, [pc, #8] @ (8002864 <TIM3_IRQHandler+0x10>)
800285a: f002 fcef bl 800523c <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
800285e: bf00 nop
8002860: bd80 pop {r7, pc}
8002862: bf00 nop
8002864: 20000780 .word 0x20000780
08002868 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8002868: b580 push {r7, lr}
800286a: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
800286c: 4802 ldr r0, [pc, #8] @ (8002878 <USART1_IRQHandler+0x10>)
800286e: f003 f911 bl 8005a94 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8002872: bf00 nop
8002874: bd80 pop {r7, pc}
8002876: bf00 nop
8002878: 200007c8 .word 0x200007c8
0800287c <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
800287c: b480 push {r7}
800287e: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8002880: bf00 nop
8002882: 46bd mov sp, r7
8002884: bc80 pop {r7}
8002886: 4770 bx lr
08002888 <MX_TIM3_Init>:
TIM_HandleTypeDef htim3;
/* TIM3 init function */
void MX_TIM3_Init(void)
{
8002888: b580 push {r7, lr}
800288a: b086 sub sp, #24
800288c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800288e: f107 0308 add.w r3, r7, #8
8002892: 2200 movs r2, #0
8002894: 601a str r2, [r3, #0]
8002896: 605a str r2, [r3, #4]
8002898: 609a str r2, [r3, #8]
800289a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800289c: 463b mov r3, r7
800289e: 2200 movs r2, #0
80028a0: 601a str r2, [r3, #0]
80028a2: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80028a4: 4b1d ldr r3, [pc, #116] @ (800291c <MX_TIM3_Init+0x94>)
80028a6: 4a1e ldr r2, [pc, #120] @ (8002920 <MX_TIM3_Init+0x98>)
80028a8: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 2;
80028aa: 4b1c ldr r3, [pc, #112] @ (800291c <MX_TIM3_Init+0x94>)
80028ac: 2202 movs r2, #2
80028ae: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80028b0: 4b1a ldr r3, [pc, #104] @ (800291c <MX_TIM3_Init+0x94>)
80028b2: 2200 movs r2, #0
80028b4: 609a str r2, [r3, #8]
htim3.Init.Period = 999;
80028b6: 4b19 ldr r3, [pc, #100] @ (800291c <MX_TIM3_Init+0x94>)
80028b8: f240 32e7 movw r2, #999 @ 0x3e7
80028bc: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80028be: 4b17 ldr r3, [pc, #92] @ (800291c <MX_TIM3_Init+0x94>)
80028c0: 2200 movs r2, #0
80028c2: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
80028c4: 4b15 ldr r3, [pc, #84] @ (800291c <MX_TIM3_Init+0x94>)
80028c6: 2280 movs r2, #128 @ 0x80
80028c8: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
80028ca: 4814 ldr r0, [pc, #80] @ (800291c <MX_TIM3_Init+0x94>)
80028cc: f002 fc14 bl 80050f8 <HAL_TIM_Base_Init>
80028d0: 4603 mov r3, r0
80028d2: 2b00 cmp r3, #0
80028d4: d001 beq.n 80028da <MX_TIM3_Init+0x52>
{
Error_Handler();
80028d6: f7ff fe65 bl 80025a4 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80028da: f44f 5380 mov.w r3, #4096 @ 0x1000
80028de: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
80028e0: f107 0308 add.w r3, r7, #8
80028e4: 4619 mov r1, r3
80028e6: 480d ldr r0, [pc, #52] @ (800291c <MX_TIM3_Init+0x94>)
80028e8: f002 fd98 bl 800541c <HAL_TIM_ConfigClockSource>
80028ec: 4603 mov r3, r0
80028ee: 2b00 cmp r3, #0
80028f0: d001 beq.n 80028f6 <MX_TIM3_Init+0x6e>
{
Error_Handler();
80028f2: f7ff fe57 bl 80025a4 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80028f6: 2300 movs r3, #0
80028f8: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80028fa: 2300 movs r3, #0
80028fc: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80028fe: 463b mov r3, r7
8002900: 4619 mov r1, r3
8002902: 4806 ldr r0, [pc, #24] @ (800291c <MX_TIM3_Init+0x94>)
8002904: f002 ff7a bl 80057fc <HAL_TIMEx_MasterConfigSynchronization>
8002908: 4603 mov r3, r0
800290a: 2b00 cmp r3, #0
800290c: d001 beq.n 8002912 <MX_TIM3_Init+0x8a>
{
Error_Handler();
800290e: f7ff fe49 bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
8002912: bf00 nop
8002914: 3718 adds r7, #24
8002916: 46bd mov sp, r7
8002918: bd80 pop {r7, pc}
800291a: bf00 nop
800291c: 20000780 .word 0x20000780
8002920: 40000400 .word 0x40000400
08002924 <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
8002924: b580 push {r7, lr}
8002926: b084 sub sp, #16
8002928: af00 add r7, sp, #0
800292a: 6078 str r0, [r7, #4]
if(tim_baseHandle->Instance==TIM3)
800292c: 687b ldr r3, [r7, #4]
800292e: 681b ldr r3, [r3, #0]
8002930: 4a0d ldr r2, [pc, #52] @ (8002968 <HAL_TIM_Base_MspInit+0x44>)
8002932: 4293 cmp r3, r2
8002934: d113 bne.n 800295e <HAL_TIM_Base_MspInit+0x3a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
8002936: 4b0d ldr r3, [pc, #52] @ (800296c <HAL_TIM_Base_MspInit+0x48>)
8002938: 69db ldr r3, [r3, #28]
800293a: 4a0c ldr r2, [pc, #48] @ (800296c <HAL_TIM_Base_MspInit+0x48>)
800293c: f043 0302 orr.w r3, r3, #2
8002940: 61d3 str r3, [r2, #28]
8002942: 4b0a ldr r3, [pc, #40] @ (800296c <HAL_TIM_Base_MspInit+0x48>)
8002944: 69db ldr r3, [r3, #28]
8002946: f003 0302 and.w r3, r3, #2
800294a: 60fb str r3, [r7, #12]
800294c: 68fb ldr r3, [r7, #12]
/* TIM3 interrupt Init */
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
800294e: 2200 movs r2, #0
8002950: 2100 movs r1, #0
8002952: 201d movs r0, #29
8002954: f000 fc1f bl 8003196 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
8002958: 201d movs r0, #29
800295a: f000 fc38 bl 80031ce <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
800295e: bf00 nop
8002960: 3710 adds r7, #16
8002962: 46bd mov sp, r7
8002964: bd80 pop {r7, pc}
8002966: bf00 nop
8002968: 40000400 .word 0x40000400
800296c: 40021000 .word 0x40021000
08002970 <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8002970: b580 push {r7, lr}
8002972: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8002974: 4b11 ldr r3, [pc, #68] @ (80029bc <MX_USART1_UART_Init+0x4c>)
8002976: 4a12 ldr r2, [pc, #72] @ (80029c0 <MX_USART1_UART_Init+0x50>)
8002978: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
800297a: 4b10 ldr r3, [pc, #64] @ (80029bc <MX_USART1_UART_Init+0x4c>)
800297c: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8002980: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002982: 4b0e ldr r3, [pc, #56] @ (80029bc <MX_USART1_UART_Init+0x4c>)
8002984: 2200 movs r2, #0
8002986: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002988: 4b0c ldr r3, [pc, #48] @ (80029bc <MX_USART1_UART_Init+0x4c>)
800298a: 2200 movs r2, #0
800298c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800298e: 4b0b ldr r3, [pc, #44] @ (80029bc <MX_USART1_UART_Init+0x4c>)
8002990: 2200 movs r2, #0
8002992: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002994: 4b09 ldr r3, [pc, #36] @ (80029bc <MX_USART1_UART_Init+0x4c>)
8002996: 220c movs r2, #12
8002998: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800299a: 4b08 ldr r3, [pc, #32] @ (80029bc <MX_USART1_UART_Init+0x4c>)
800299c: 2200 movs r2, #0
800299e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80029a0: 4b06 ldr r3, [pc, #24] @ (80029bc <MX_USART1_UART_Init+0x4c>)
80029a2: 2200 movs r2, #0
80029a4: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
80029a6: 4805 ldr r0, [pc, #20] @ (80029bc <MX_USART1_UART_Init+0x4c>)
80029a8: f002 ff98 bl 80058dc <HAL_UART_Init>
80029ac: 4603 mov r3, r0
80029ae: 2b00 cmp r3, #0
80029b0: d001 beq.n 80029b6 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
80029b2: f7ff fdf7 bl 80025a4 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80029b6: bf00 nop
80029b8: bd80 pop {r7, pc}
80029ba: bf00 nop
80029bc: 200007c8 .word 0x200007c8
80029c0: 40013800 .word 0x40013800
080029c4 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
80029c4: b580 push {r7, lr}
80029c6: b088 sub sp, #32
80029c8: af00 add r7, sp, #0
80029ca: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80029cc: f107 0310 add.w r3, r7, #16
80029d0: 2200 movs r2, #0
80029d2: 601a str r2, [r3, #0]
80029d4: 605a str r2, [r3, #4]
80029d6: 609a str r2, [r3, #8]
80029d8: 60da str r2, [r3, #12]
if(uartHandle->Instance==USART1)
80029da: 687b ldr r3, [r7, #4]
80029dc: 681b ldr r3, [r3, #0]
80029de: 4a20 ldr r2, [pc, #128] @ (8002a60 <HAL_UART_MspInit+0x9c>)
80029e0: 4293 cmp r3, r2
80029e2: d139 bne.n 8002a58 <HAL_UART_MspInit+0x94>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
80029e4: 4b1f ldr r3, [pc, #124] @ (8002a64 <HAL_UART_MspInit+0xa0>)
80029e6: 699b ldr r3, [r3, #24]
80029e8: 4a1e ldr r2, [pc, #120] @ (8002a64 <HAL_UART_MspInit+0xa0>)
80029ea: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80029ee: 6193 str r3, [r2, #24]
80029f0: 4b1c ldr r3, [pc, #112] @ (8002a64 <HAL_UART_MspInit+0xa0>)
80029f2: 699b ldr r3, [r3, #24]
80029f4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80029f8: 60fb str r3, [r7, #12]
80029fa: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80029fc: 4b19 ldr r3, [pc, #100] @ (8002a64 <HAL_UART_MspInit+0xa0>)
80029fe: 699b ldr r3, [r3, #24]
8002a00: 4a18 ldr r2, [pc, #96] @ (8002a64 <HAL_UART_MspInit+0xa0>)
8002a02: f043 0304 orr.w r3, r3, #4
8002a06: 6193 str r3, [r2, #24]
8002a08: 4b16 ldr r3, [pc, #88] @ (8002a64 <HAL_UART_MspInit+0xa0>)
8002a0a: 699b ldr r3, [r3, #24]
8002a0c: f003 0304 and.w r3, r3, #4
8002a10: 60bb str r3, [r7, #8]
8002a12: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = TX_RS485_Pin;
8002a14: f44f 7300 mov.w r3, #512 @ 0x200
8002a18: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8002a1a: 2302 movs r3, #2
8002a1c: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
8002a1e: 2301 movs r3, #1
8002a20: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
8002a22: f107 0310 add.w r3, r7, #16
8002a26: 4619 mov r1, r3
8002a28: 480f ldr r0, [pc, #60] @ (8002a68 <HAL_UART_MspInit+0xa4>)
8002a2a: f000 fc9d bl 8003368 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RX_RS485_Pin;
8002a2e: f44f 6380 mov.w r3, #1024 @ 0x400
8002a32: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002a34: 2300 movs r3, #0
8002a36: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002a38: 2300 movs r3, #0
8002a3a: 61bb str r3, [r7, #24]
HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
8002a3c: f107 0310 add.w r3, r7, #16
8002a40: 4619 mov r1, r3
8002a42: 4809 ldr r0, [pc, #36] @ (8002a68 <HAL_UART_MspInit+0xa4>)
8002a44: f000 fc90 bl 8003368 <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8002a48: 2200 movs r2, #0
8002a4a: 2100 movs r1, #0
8002a4c: 2025 movs r0, #37 @ 0x25
8002a4e: f000 fba2 bl 8003196 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8002a52: 2025 movs r0, #37 @ 0x25
8002a54: f000 fbbb bl 80031ce <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8002a58: bf00 nop
8002a5a: 3720 adds r7, #32
8002a5c: 46bd mov sp, r7
8002a5e: bd80 pop {r7, pc}
8002a60: 40013800 .word 0x40013800
8002a64: 40021000 .word 0x40021000
8002a68: 40010800 .word 0x40010800
08002a6c <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8002a6c: f7ff ff06 bl 800287c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8002a70: 480b ldr r0, [pc, #44] @ (8002aa0 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8002a72: 490c ldr r1, [pc, #48] @ (8002aa4 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8002a74: 4a0c ldr r2, [pc, #48] @ (8002aa8 <LoopFillZerobss+0x16>)
movs r3, #0
8002a76: 2300 movs r3, #0
b LoopCopyDataInit
8002a78: e002 b.n 8002a80 <LoopCopyDataInit>
08002a7a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8002a7a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8002a7c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8002a7e: 3304 adds r3, #4
08002a80 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002a80: 18c4 adds r4, r0, r3
cmp r4, r1
8002a82: 428c cmp r4, r1
bcc CopyDataInit
8002a84: d3f9 bcc.n 8002a7a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8002a86: 4a09 ldr r2, [pc, #36] @ (8002aac <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8002a88: 4c09 ldr r4, [pc, #36] @ (8002ab0 <LoopFillZerobss+0x1e>)
movs r3, #0
8002a8a: 2300 movs r3, #0
b LoopFillZerobss
8002a8c: e001 b.n 8002a92 <LoopFillZerobss>
08002a8e <FillZerobss>:
FillZerobss:
str r3, [r2]
8002a8e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002a90: 3204 adds r2, #4
08002a92 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002a92: 42a2 cmp r2, r4
bcc FillZerobss
8002a94: d3fb bcc.n 8002a8e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8002a96: f003 fd45 bl 8006524 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8002a9a: f7ff faa9 bl 8001ff0 <main>
bx lr
8002a9e: 4770 bx lr
ldr r0, =_sdata
8002aa0: 20000000 .word 0x20000000
ldr r1, =_edata
8002aa4: 20000094 .word 0x20000094
ldr r2, =_sidata
8002aa8: 08006754 .word 0x08006754
ldr r2, =_sbss
8002aac: 20000094 .word 0x20000094
ldr r4, =_ebss
8002ab0: 2000094c .word 0x2000094c
08002ab4 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002ab4: e7fe b.n 8002ab4 <ADC1_2_IRQHandler>
...
08002ab8 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8002ab8: b580 push {r7, lr}
8002aba: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002abc: 4b08 ldr r3, [pc, #32] @ (8002ae0 <HAL_Init+0x28>)
8002abe: 681b ldr r3, [r3, #0]
8002ac0: 4a07 ldr r2, [pc, #28] @ (8002ae0 <HAL_Init+0x28>)
8002ac2: f043 0310 orr.w r3, r3, #16
8002ac6: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8002ac8: 2003 movs r0, #3
8002aca: f000 fb59 bl 8003180 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002ace: 200f movs r0, #15
8002ad0: f000 f808 bl 8002ae4 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002ad4: f7ff fe60 bl 8002798 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8002ad8: 2300 movs r3, #0
}
8002ada: 4618 mov r0, r3
8002adc: bd80 pop {r7, pc}
8002ade: bf00 nop
8002ae0: 40022000 .word 0x40022000
08002ae4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002ae4: b580 push {r7, lr}
8002ae6: b082 sub sp, #8
8002ae8: af00 add r7, sp, #0
8002aea: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002aec: 4b12 ldr r3, [pc, #72] @ (8002b38 <HAL_InitTick+0x54>)
8002aee: 681a ldr r2, [r3, #0]
8002af0: 4b12 ldr r3, [pc, #72] @ (8002b3c <HAL_InitTick+0x58>)
8002af2: 781b ldrb r3, [r3, #0]
8002af4: 4619 mov r1, r3
8002af6: f44f 737a mov.w r3, #1000 @ 0x3e8
8002afa: fbb3 f3f1 udiv r3, r3, r1
8002afe: fbb2 f3f3 udiv r3, r2, r3
8002b02: 4618 mov r0, r3
8002b04: f000 fb71 bl 80031ea <HAL_SYSTICK_Config>
8002b08: 4603 mov r3, r0
8002b0a: 2b00 cmp r3, #0
8002b0c: d001 beq.n 8002b12 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002b0e: 2301 movs r3, #1
8002b10: e00e b.n 8002b30 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002b12: 687b ldr r3, [r7, #4]
8002b14: 2b0f cmp r3, #15
8002b16: d80a bhi.n 8002b2e <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8002b18: 2200 movs r2, #0
8002b1a: 6879 ldr r1, [r7, #4]
8002b1c: f04f 30ff mov.w r0, #4294967295
8002b20: f000 fb39 bl 8003196 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8002b24: 4a06 ldr r2, [pc, #24] @ (8002b40 <HAL_InitTick+0x5c>)
8002b26: 687b ldr r3, [r7, #4]
8002b28: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8002b2a: 2300 movs r3, #0
8002b2c: e000 b.n 8002b30 <HAL_InitTick+0x4c>
return HAL_ERROR;
8002b2e: 2301 movs r3, #1
}
8002b30: 4618 mov r0, r3
8002b32: 3708 adds r7, #8
8002b34: 46bd mov sp, r7
8002b36: bd80 pop {r7, pc}
8002b38: 20000038 .word 0x20000038
8002b3c: 20000040 .word 0x20000040
8002b40: 2000003c .word 0x2000003c
08002b44 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8002b44: b480 push {r7}
8002b46: af00 add r7, sp, #0
uwTick += uwTickFreq;
8002b48: 4b05 ldr r3, [pc, #20] @ (8002b60 <HAL_IncTick+0x1c>)
8002b4a: 781b ldrb r3, [r3, #0]
8002b4c: 461a mov r2, r3
8002b4e: 4b05 ldr r3, [pc, #20] @ (8002b64 <HAL_IncTick+0x20>)
8002b50: 681b ldr r3, [r3, #0]
8002b52: 4413 add r3, r2
8002b54: 4a03 ldr r2, [pc, #12] @ (8002b64 <HAL_IncTick+0x20>)
8002b56: 6013 str r3, [r2, #0]
}
8002b58: bf00 nop
8002b5a: 46bd mov sp, r7
8002b5c: bc80 pop {r7}
8002b5e: 4770 bx lr
8002b60: 20000040 .word 0x20000040
8002b64: 20000810 .word 0x20000810
08002b68 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8002b68: b480 push {r7}
8002b6a: af00 add r7, sp, #0
return uwTick;
8002b6c: 4b02 ldr r3, [pc, #8] @ (8002b78 <HAL_GetTick+0x10>)
8002b6e: 681b ldr r3, [r3, #0]
}
8002b70: 4618 mov r0, r3
8002b72: 46bd mov sp, r7
8002b74: bc80 pop {r7}
8002b76: 4770 bx lr
8002b78: 20000810 .word 0x20000810
08002b7c <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8002b7c: b580 push {r7, lr}
8002b7e: b084 sub sp, #16
8002b80: af00 add r7, sp, #0
8002b82: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8002b84: f7ff fff0 bl 8002b68 <HAL_GetTick>
8002b88: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8002b8a: 687b ldr r3, [r7, #4]
8002b8c: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8002b8e: 68fb ldr r3, [r7, #12]
8002b90: f1b3 3fff cmp.w r3, #4294967295
8002b94: d005 beq.n 8002ba2 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8002b96: 4b0a ldr r3, [pc, #40] @ (8002bc0 <HAL_Delay+0x44>)
8002b98: 781b ldrb r3, [r3, #0]
8002b9a: 461a mov r2, r3
8002b9c: 68fb ldr r3, [r7, #12]
8002b9e: 4413 add r3, r2
8002ba0: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8002ba2: bf00 nop
8002ba4: f7ff ffe0 bl 8002b68 <HAL_GetTick>
8002ba8: 4602 mov r2, r0
8002baa: 68bb ldr r3, [r7, #8]
8002bac: 1ad3 subs r3, r2, r3
8002bae: 68fa ldr r2, [r7, #12]
8002bb0: 429a cmp r2, r3
8002bb2: d8f7 bhi.n 8002ba4 <HAL_Delay+0x28>
{
}
}
8002bb4: bf00 nop
8002bb6: bf00 nop
8002bb8: 3710 adds r7, #16
8002bba: 46bd mov sp, r7
8002bbc: bd80 pop {r7, pc}
8002bbe: bf00 nop
8002bc0: 20000040 .word 0x20000040
08002bc4 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8002bc4: b580 push {r7, lr}
8002bc6: b086 sub sp, #24
8002bc8: af00 add r7, sp, #0
8002bca: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002bcc: 2300 movs r3, #0
8002bce: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
8002bd0: 2300 movs r3, #0
8002bd2: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8002bd4: 2300 movs r3, #0
8002bd6: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
8002bd8: 2300 movs r3, #0
8002bda: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8002bdc: 687b ldr r3, [r7, #4]
8002bde: 2b00 cmp r3, #0
8002be0: d101 bne.n 8002be6 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
8002be2: 2301 movs r3, #1
8002be4: e0be b.n 8002d64 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8002be6: 687b ldr r3, [r7, #4]
8002be8: 689b ldr r3, [r3, #8]
8002bea: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002bec: 687b ldr r3, [r7, #4]
8002bee: 6a9b ldr r3, [r3, #40] @ 0x28
8002bf0: 2b00 cmp r3, #0
8002bf2: d109 bne.n 8002c08 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8002bf4: 687b ldr r3, [r7, #4]
8002bf6: 2200 movs r2, #0
8002bf8: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8002bfa: 687b ldr r3, [r7, #4]
8002bfc: 2200 movs r2, #0
8002bfe: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8002c02: 6878 ldr r0, [r7, #4]
8002c04: f7fe fd70 bl 80016e8 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8002c08: 6878 ldr r0, [r7, #4]
8002c0a: f000 f9ab bl 8002f64 <ADC_ConversionStop_Disable>
8002c0e: 4603 mov r3, r0
8002c10: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8002c12: 687b ldr r3, [r7, #4]
8002c14: 6a9b ldr r3, [r3, #40] @ 0x28
8002c16: f003 0310 and.w r3, r3, #16
8002c1a: 2b00 cmp r3, #0
8002c1c: f040 8099 bne.w 8002d52 <HAL_ADC_Init+0x18e>
8002c20: 7dfb ldrb r3, [r7, #23]
8002c22: 2b00 cmp r3, #0
8002c24: f040 8095 bne.w 8002d52 <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002c28: 687b ldr r3, [r7, #4]
8002c2a: 6a9b ldr r3, [r3, #40] @ 0x28
8002c2c: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002c30: f023 0302 bic.w r3, r3, #2
8002c34: f043 0202 orr.w r2, r3, #2
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8002c3c: 687b ldr r3, [r7, #4]
8002c3e: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002c40: 687b ldr r3, [r7, #4]
8002c42: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8002c44: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8002c46: 687b ldr r3, [r7, #4]
8002c48: 7b1b ldrb r3, [r3, #12]
8002c4a: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002c4c: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8002c4e: 68ba ldr r2, [r7, #8]
8002c50: 4313 orrs r3, r2
8002c52: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8002c54: 687b ldr r3, [r7, #4]
8002c56: 689b ldr r3, [r3, #8]
8002c58: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002c5c: d003 beq.n 8002c66 <HAL_ADC_Init+0xa2>
8002c5e: 687b ldr r3, [r7, #4]
8002c60: 689b ldr r3, [r3, #8]
8002c62: 2b01 cmp r3, #1
8002c64: d102 bne.n 8002c6c <HAL_ADC_Init+0xa8>
8002c66: f44f 7380 mov.w r3, #256 @ 0x100
8002c6a: e000 b.n 8002c6e <HAL_ADC_Init+0xaa>
8002c6c: 2300 movs r3, #0
8002c6e: 693a ldr r2, [r7, #16]
8002c70: 4313 orrs r3, r2
8002c72: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002c74: 687b ldr r3, [r7, #4]
8002c76: 7d1b ldrb r3, [r3, #20]
8002c78: 2b01 cmp r3, #1
8002c7a: d119 bne.n 8002cb0 <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8002c7c: 687b ldr r3, [r7, #4]
8002c7e: 7b1b ldrb r3, [r3, #12]
8002c80: 2b00 cmp r3, #0
8002c82: d109 bne.n 8002c98 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8002c84: 687b ldr r3, [r7, #4]
8002c86: 699b ldr r3, [r3, #24]
8002c88: 3b01 subs r3, #1
8002c8a: 035a lsls r2, r3, #13
8002c8c: 693b ldr r3, [r7, #16]
8002c8e: 4313 orrs r3, r2
8002c90: f443 6300 orr.w r3, r3, #2048 @ 0x800
8002c94: 613b str r3, [r7, #16]
8002c96: e00b b.n 8002cb0 <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002c98: 687b ldr r3, [r7, #4]
8002c9a: 6a9b ldr r3, [r3, #40] @ 0x28
8002c9c: f043 0220 orr.w r2, r3, #32
8002ca0: 687b ldr r3, [r7, #4]
8002ca2: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002ca4: 687b ldr r3, [r7, #4]
8002ca6: 6adb ldr r3, [r3, #44] @ 0x2c
8002ca8: f043 0201 orr.w r2, r3, #1
8002cac: 687b ldr r3, [r7, #4]
8002cae: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
8002cb0: 687b ldr r3, [r7, #4]
8002cb2: 681b ldr r3, [r3, #0]
8002cb4: 685b ldr r3, [r3, #4]
8002cb6: f423 4169 bic.w r1, r3, #59648 @ 0xe900
8002cba: 687b ldr r3, [r7, #4]
8002cbc: 681b ldr r3, [r3, #0]
8002cbe: 693a ldr r2, [r7, #16]
8002cc0: 430a orrs r2, r1
8002cc2: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
8002cc4: 687b ldr r3, [r7, #4]
8002cc6: 681b ldr r3, [r3, #0]
8002cc8: 689a ldr r2, [r3, #8]
8002cca: 4b28 ldr r3, [pc, #160] @ (8002d6c <HAL_ADC_Init+0x1a8>)
8002ccc: 4013 ands r3, r2
8002cce: 687a ldr r2, [r7, #4]
8002cd0: 6812 ldr r2, [r2, #0]
8002cd2: 68b9 ldr r1, [r7, #8]
8002cd4: 430b orrs r3, r1
8002cd6: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8002cd8: 687b ldr r3, [r7, #4]
8002cda: 689b ldr r3, [r3, #8]
8002cdc: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002ce0: d003 beq.n 8002cea <HAL_ADC_Init+0x126>
8002ce2: 687b ldr r3, [r7, #4]
8002ce4: 689b ldr r3, [r3, #8]
8002ce6: 2b01 cmp r3, #1
8002ce8: d104 bne.n 8002cf4 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
8002cea: 687b ldr r3, [r7, #4]
8002cec: 691b ldr r3, [r3, #16]
8002cee: 3b01 subs r3, #1
8002cf0: 051b lsls r3, r3, #20
8002cf2: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8002cf4: 687b ldr r3, [r7, #4]
8002cf6: 681b ldr r3, [r3, #0]
8002cf8: 6adb ldr r3, [r3, #44] @ 0x2c
8002cfa: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
8002cfe: 687b ldr r3, [r7, #4]
8002d00: 681b ldr r3, [r3, #0]
8002d02: 68fa ldr r2, [r7, #12]
8002d04: 430a orrs r2, r1
8002d06: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 681b ldr r3, [r3, #0]
8002d0c: 689a ldr r2, [r3, #8]
8002d0e: 4b18 ldr r3, [pc, #96] @ (8002d70 <HAL_ADC_Init+0x1ac>)
8002d10: 4013 ands r3, r2
8002d12: 68ba ldr r2, [r7, #8]
8002d14: 429a cmp r2, r3
8002d16: d10b bne.n 8002d30 <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002d18: 687b ldr r3, [r7, #4]
8002d1a: 2200 movs r2, #0
8002d1c: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002d1e: 687b ldr r3, [r7, #4]
8002d20: 6a9b ldr r3, [r3, #40] @ 0x28
8002d22: f023 0303 bic.w r3, r3, #3
8002d26: f043 0201 orr.w r2, r3, #1
8002d2a: 687b ldr r3, [r7, #4]
8002d2c: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002d2e: e018 b.n 8002d62 <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002d30: 687b ldr r3, [r7, #4]
8002d32: 6a9b ldr r3, [r3, #40] @ 0x28
8002d34: f023 0312 bic.w r3, r3, #18
8002d38: f043 0210 orr.w r2, r3, #16
8002d3c: 687b ldr r3, [r7, #4]
8002d3e: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002d40: 687b ldr r3, [r7, #4]
8002d42: 6adb ldr r3, [r3, #44] @ 0x2c
8002d44: f043 0201 orr.w r2, r3, #1
8002d48: 687b ldr r3, [r7, #4]
8002d4a: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8002d4c: 2301 movs r3, #1
8002d4e: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002d50: e007 b.n 8002d62 <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002d52: 687b ldr r3, [r7, #4]
8002d54: 6a9b ldr r3, [r3, #40] @ 0x28
8002d56: f043 0210 orr.w r2, r3, #16
8002d5a: 687b ldr r3, [r7, #4]
8002d5c: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8002d5e: 2301 movs r3, #1
8002d60: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8002d62: 7dfb ldrb r3, [r7, #23]
}
8002d64: 4618 mov r0, r3
8002d66: 3718 adds r7, #24
8002d68: 46bd mov sp, r7
8002d6a: bd80 pop {r7, pc}
8002d6c: ffe1f7fd .word 0xffe1f7fd
8002d70: ff1f0efe .word 0xff1f0efe
08002d74 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002d74: b480 push {r7}
8002d76: b085 sub sp, #20
8002d78: af00 add r7, sp, #0
8002d7a: 6078 str r0, [r7, #4]
8002d7c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002d7e: 2300 movs r3, #0
8002d80: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
8002d82: 2300 movs r3, #0
8002d84: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8002d86: 687b ldr r3, [r7, #4]
8002d88: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8002d8c: 2b01 cmp r3, #1
8002d8e: d101 bne.n 8002d94 <HAL_ADC_ConfigChannel+0x20>
8002d90: 2302 movs r3, #2
8002d92: e0dc b.n 8002f4e <HAL_ADC_ConfigChannel+0x1da>
8002d94: 687b ldr r3, [r7, #4]
8002d96: 2201 movs r2, #1
8002d98: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
8002d9c: 683b ldr r3, [r7, #0]
8002d9e: 685b ldr r3, [r3, #4]
8002da0: 2b06 cmp r3, #6
8002da2: d81c bhi.n 8002dde <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8002da4: 687b ldr r3, [r7, #4]
8002da6: 681b ldr r3, [r3, #0]
8002da8: 6b59 ldr r1, [r3, #52] @ 0x34
8002daa: 683b ldr r3, [r7, #0]
8002dac: 685a ldr r2, [r3, #4]
8002dae: 4613 mov r3, r2
8002db0: 009b lsls r3, r3, #2
8002db2: 4413 add r3, r2
8002db4: 3b05 subs r3, #5
8002db6: 221f movs r2, #31
8002db8: fa02 f303 lsl.w r3, r2, r3
8002dbc: 43db mvns r3, r3
8002dbe: 4019 ands r1, r3
8002dc0: 683b ldr r3, [r7, #0]
8002dc2: 6818 ldr r0, [r3, #0]
8002dc4: 683b ldr r3, [r7, #0]
8002dc6: 685a ldr r2, [r3, #4]
8002dc8: 4613 mov r3, r2
8002dca: 009b lsls r3, r3, #2
8002dcc: 4413 add r3, r2
8002dce: 3b05 subs r3, #5
8002dd0: fa00 f203 lsl.w r2, r0, r3
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 681b ldr r3, [r3, #0]
8002dd8: 430a orrs r2, r1
8002dda: 635a str r2, [r3, #52] @ 0x34
8002ddc: e03c b.n 8002e58 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
8002dde: 683b ldr r3, [r7, #0]
8002de0: 685b ldr r3, [r3, #4]
8002de2: 2b0c cmp r3, #12
8002de4: d81c bhi.n 8002e20 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
8002de6: 687b ldr r3, [r7, #4]
8002de8: 681b ldr r3, [r3, #0]
8002dea: 6b19 ldr r1, [r3, #48] @ 0x30
8002dec: 683b ldr r3, [r7, #0]
8002dee: 685a ldr r2, [r3, #4]
8002df0: 4613 mov r3, r2
8002df2: 009b lsls r3, r3, #2
8002df4: 4413 add r3, r2
8002df6: 3b23 subs r3, #35 @ 0x23
8002df8: 221f movs r2, #31
8002dfa: fa02 f303 lsl.w r3, r2, r3
8002dfe: 43db mvns r3, r3
8002e00: 4019 ands r1, r3
8002e02: 683b ldr r3, [r7, #0]
8002e04: 6818 ldr r0, [r3, #0]
8002e06: 683b ldr r3, [r7, #0]
8002e08: 685a ldr r2, [r3, #4]
8002e0a: 4613 mov r3, r2
8002e0c: 009b lsls r3, r3, #2
8002e0e: 4413 add r3, r2
8002e10: 3b23 subs r3, #35 @ 0x23
8002e12: fa00 f203 lsl.w r2, r0, r3
8002e16: 687b ldr r3, [r7, #4]
8002e18: 681b ldr r3, [r3, #0]
8002e1a: 430a orrs r2, r1
8002e1c: 631a str r2, [r3, #48] @ 0x30
8002e1e: e01b b.n 8002e58 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
8002e20: 687b ldr r3, [r7, #4]
8002e22: 681b ldr r3, [r3, #0]
8002e24: 6ad9 ldr r1, [r3, #44] @ 0x2c
8002e26: 683b ldr r3, [r7, #0]
8002e28: 685a ldr r2, [r3, #4]
8002e2a: 4613 mov r3, r2
8002e2c: 009b lsls r3, r3, #2
8002e2e: 4413 add r3, r2
8002e30: 3b41 subs r3, #65 @ 0x41
8002e32: 221f movs r2, #31
8002e34: fa02 f303 lsl.w r3, r2, r3
8002e38: 43db mvns r3, r3
8002e3a: 4019 ands r1, r3
8002e3c: 683b ldr r3, [r7, #0]
8002e3e: 6818 ldr r0, [r3, #0]
8002e40: 683b ldr r3, [r7, #0]
8002e42: 685a ldr r2, [r3, #4]
8002e44: 4613 mov r3, r2
8002e46: 009b lsls r3, r3, #2
8002e48: 4413 add r3, r2
8002e4a: 3b41 subs r3, #65 @ 0x41
8002e4c: fa00 f203 lsl.w r2, r0, r3
8002e50: 687b ldr r3, [r7, #4]
8002e52: 681b ldr r3, [r3, #0]
8002e54: 430a orrs r2, r1
8002e56: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8002e58: 683b ldr r3, [r7, #0]
8002e5a: 681b ldr r3, [r3, #0]
8002e5c: 2b09 cmp r3, #9
8002e5e: d91c bls.n 8002e9a <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8002e60: 687b ldr r3, [r7, #4]
8002e62: 681b ldr r3, [r3, #0]
8002e64: 68d9 ldr r1, [r3, #12]
8002e66: 683b ldr r3, [r7, #0]
8002e68: 681a ldr r2, [r3, #0]
8002e6a: 4613 mov r3, r2
8002e6c: 005b lsls r3, r3, #1
8002e6e: 4413 add r3, r2
8002e70: 3b1e subs r3, #30
8002e72: 2207 movs r2, #7
8002e74: fa02 f303 lsl.w r3, r2, r3
8002e78: 43db mvns r3, r3
8002e7a: 4019 ands r1, r3
8002e7c: 683b ldr r3, [r7, #0]
8002e7e: 6898 ldr r0, [r3, #8]
8002e80: 683b ldr r3, [r7, #0]
8002e82: 681a ldr r2, [r3, #0]
8002e84: 4613 mov r3, r2
8002e86: 005b lsls r3, r3, #1
8002e88: 4413 add r3, r2
8002e8a: 3b1e subs r3, #30
8002e8c: fa00 f203 lsl.w r2, r0, r3
8002e90: 687b ldr r3, [r7, #4]
8002e92: 681b ldr r3, [r3, #0]
8002e94: 430a orrs r2, r1
8002e96: 60da str r2, [r3, #12]
8002e98: e019 b.n 8002ece <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
8002e9a: 687b ldr r3, [r7, #4]
8002e9c: 681b ldr r3, [r3, #0]
8002e9e: 6919 ldr r1, [r3, #16]
8002ea0: 683b ldr r3, [r7, #0]
8002ea2: 681a ldr r2, [r3, #0]
8002ea4: 4613 mov r3, r2
8002ea6: 005b lsls r3, r3, #1
8002ea8: 4413 add r3, r2
8002eaa: 2207 movs r2, #7
8002eac: fa02 f303 lsl.w r3, r2, r3
8002eb0: 43db mvns r3, r3
8002eb2: 4019 ands r1, r3
8002eb4: 683b ldr r3, [r7, #0]
8002eb6: 6898 ldr r0, [r3, #8]
8002eb8: 683b ldr r3, [r7, #0]
8002eba: 681a ldr r2, [r3, #0]
8002ebc: 4613 mov r3, r2
8002ebe: 005b lsls r3, r3, #1
8002ec0: 4413 add r3, r2
8002ec2: fa00 f203 lsl.w r2, r0, r3
8002ec6: 687b ldr r3, [r7, #4]
8002ec8: 681b ldr r3, [r3, #0]
8002eca: 430a orrs r2, r1
8002ecc: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8002ece: 683b ldr r3, [r7, #0]
8002ed0: 681b ldr r3, [r3, #0]
8002ed2: 2b10 cmp r3, #16
8002ed4: d003 beq.n 8002ede <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
8002ed6: 683b ldr r3, [r7, #0]
8002ed8: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8002eda: 2b11 cmp r3, #17
8002edc: d132 bne.n 8002f44 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 681b ldr r3, [r3, #0]
8002ee2: 4a1d ldr r2, [pc, #116] @ (8002f58 <HAL_ADC_ConfigChannel+0x1e4>)
8002ee4: 4293 cmp r3, r2
8002ee6: d125 bne.n 8002f34 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
8002ee8: 687b ldr r3, [r7, #4]
8002eea: 681b ldr r3, [r3, #0]
8002eec: 689b ldr r3, [r3, #8]
8002eee: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002ef2: 2b00 cmp r3, #0
8002ef4: d126 bne.n 8002f44 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8002ef6: 687b ldr r3, [r7, #4]
8002ef8: 681b ldr r3, [r3, #0]
8002efa: 689a ldr r2, [r3, #8]
8002efc: 687b ldr r3, [r7, #4]
8002efe: 681b ldr r3, [r3, #0]
8002f00: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8002f04: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8002f06: 683b ldr r3, [r7, #0]
8002f08: 681b ldr r3, [r3, #0]
8002f0a: 2b10 cmp r3, #16
8002f0c: d11a bne.n 8002f44 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8002f0e: 4b13 ldr r3, [pc, #76] @ (8002f5c <HAL_ADC_ConfigChannel+0x1e8>)
8002f10: 681b ldr r3, [r3, #0]
8002f12: 4a13 ldr r2, [pc, #76] @ (8002f60 <HAL_ADC_ConfigChannel+0x1ec>)
8002f14: fba2 2303 umull r2, r3, r2, r3
8002f18: 0c9a lsrs r2, r3, #18
8002f1a: 4613 mov r3, r2
8002f1c: 009b lsls r3, r3, #2
8002f1e: 4413 add r3, r2
8002f20: 005b lsls r3, r3, #1
8002f22: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002f24: e002 b.n 8002f2c <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8002f26: 68bb ldr r3, [r7, #8]
8002f28: 3b01 subs r3, #1
8002f2a: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002f2c: 68bb ldr r3, [r7, #8]
8002f2e: 2b00 cmp r3, #0
8002f30: d1f9 bne.n 8002f26 <HAL_ADC_ConfigChannel+0x1b2>
8002f32: e007 b.n 8002f44 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002f34: 687b ldr r3, [r7, #4]
8002f36: 6a9b ldr r3, [r3, #40] @ 0x28
8002f38: f043 0220 orr.w r2, r3, #32
8002f3c: 687b ldr r3, [r7, #4]
8002f3e: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8002f40: 2301 movs r3, #1
8002f42: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002f44: 687b ldr r3, [r7, #4]
8002f46: 2200 movs r2, #0
8002f48: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
8002f4c: 7bfb ldrb r3, [r7, #15]
}
8002f4e: 4618 mov r0, r3
8002f50: 3714 adds r7, #20
8002f52: 46bd mov sp, r7
8002f54: bc80 pop {r7}
8002f56: 4770 bx lr
8002f58: 40012400 .word 0x40012400
8002f5c: 20000038 .word 0x20000038
8002f60: 431bde83 .word 0x431bde83
08002f64 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8002f64: b580 push {r7, lr}
8002f66: b084 sub sp, #16
8002f68: af00 add r7, sp, #0
8002f6a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002f6c: 2300 movs r3, #0
8002f6e: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
8002f70: 687b ldr r3, [r7, #4]
8002f72: 681b ldr r3, [r3, #0]
8002f74: 689b ldr r3, [r3, #8]
8002f76: f003 0301 and.w r3, r3, #1
8002f7a: 2b01 cmp r3, #1
8002f7c: d12e bne.n 8002fdc <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8002f7e: 687b ldr r3, [r7, #4]
8002f80: 681b ldr r3, [r3, #0]
8002f82: 689a ldr r2, [r3, #8]
8002f84: 687b ldr r3, [r7, #4]
8002f86: 681b ldr r3, [r3, #0]
8002f88: f022 0201 bic.w r2, r2, #1
8002f8c: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
8002f8e: f7ff fdeb bl 8002b68 <HAL_GetTick>
8002f92: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8002f94: e01b b.n 8002fce <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002f96: f7ff fde7 bl 8002b68 <HAL_GetTick>
8002f9a: 4602 mov r2, r0
8002f9c: 68fb ldr r3, [r7, #12]
8002f9e: 1ad3 subs r3, r2, r3
8002fa0: 2b02 cmp r3, #2
8002fa2: d914 bls.n 8002fce <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8002fa4: 687b ldr r3, [r7, #4]
8002fa6: 681b ldr r3, [r3, #0]
8002fa8: 689b ldr r3, [r3, #8]
8002faa: f003 0301 and.w r3, r3, #1
8002fae: 2b01 cmp r3, #1
8002fb0: d10d bne.n 8002fce <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002fb2: 687b ldr r3, [r7, #4]
8002fb4: 6a9b ldr r3, [r3, #40] @ 0x28
8002fb6: f043 0210 orr.w r2, r3, #16
8002fba: 687b ldr r3, [r7, #4]
8002fbc: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002fbe: 687b ldr r3, [r7, #4]
8002fc0: 6adb ldr r3, [r3, #44] @ 0x2c
8002fc2: f043 0201 orr.w r2, r3, #1
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
8002fca: 2301 movs r3, #1
8002fcc: e007 b.n 8002fde <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 681b ldr r3, [r3, #0]
8002fd2: 689b ldr r3, [r3, #8]
8002fd4: f003 0301 and.w r3, r3, #1
8002fd8: 2b01 cmp r3, #1
8002fda: d0dc beq.n 8002f96 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
8002fdc: 2300 movs r3, #0
}
8002fde: 4618 mov r0, r3
8002fe0: 3710 adds r7, #16
8002fe2: 46bd mov sp, r7
8002fe4: bd80 pop {r7, pc}
...
08002fe8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002fe8: b480 push {r7}
8002fea: b085 sub sp, #20
8002fec: af00 add r7, sp, #0
8002fee: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002ff0: 687b ldr r3, [r7, #4]
8002ff2: f003 0307 and.w r3, r3, #7
8002ff6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002ff8: 4b0c ldr r3, [pc, #48] @ (800302c <__NVIC_SetPriorityGrouping+0x44>)
8002ffa: 68db ldr r3, [r3, #12]
8002ffc: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8002ffe: 68ba ldr r2, [r7, #8]
8003000: f64f 03ff movw r3, #63743 @ 0xf8ff
8003004: 4013 ands r3, r2
8003006: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003008: 68fb ldr r3, [r7, #12]
800300a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800300c: 68bb ldr r3, [r7, #8]
800300e: 4313 orrs r3, r2
reg_value = (reg_value |
8003010: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003014: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003018: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800301a: 4a04 ldr r2, [pc, #16] @ (800302c <__NVIC_SetPriorityGrouping+0x44>)
800301c: 68bb ldr r3, [r7, #8]
800301e: 60d3 str r3, [r2, #12]
}
8003020: bf00 nop
8003022: 3714 adds r7, #20
8003024: 46bd mov sp, r7
8003026: bc80 pop {r7}
8003028: 4770 bx lr
800302a: bf00 nop
800302c: e000ed00 .word 0xe000ed00
08003030 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8003030: b480 push {r7}
8003032: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003034: 4b04 ldr r3, [pc, #16] @ (8003048 <__NVIC_GetPriorityGrouping+0x18>)
8003036: 68db ldr r3, [r3, #12]
8003038: 0a1b lsrs r3, r3, #8
800303a: f003 0307 and.w r3, r3, #7
}
800303e: 4618 mov r0, r3
8003040: 46bd mov sp, r7
8003042: bc80 pop {r7}
8003044: 4770 bx lr
8003046: bf00 nop
8003048: e000ed00 .word 0xe000ed00
0800304c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800304c: b480 push {r7}
800304e: b083 sub sp, #12
8003050: af00 add r7, sp, #0
8003052: 4603 mov r3, r0
8003054: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003056: f997 3007 ldrsb.w r3, [r7, #7]
800305a: 2b00 cmp r3, #0
800305c: db0b blt.n 8003076 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800305e: 79fb ldrb r3, [r7, #7]
8003060: f003 021f and.w r2, r3, #31
8003064: 4906 ldr r1, [pc, #24] @ (8003080 <__NVIC_EnableIRQ+0x34>)
8003066: f997 3007 ldrsb.w r3, [r7, #7]
800306a: 095b lsrs r3, r3, #5
800306c: 2001 movs r0, #1
800306e: fa00 f202 lsl.w r2, r0, r2
8003072: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8003076: bf00 nop
8003078: 370c adds r7, #12
800307a: 46bd mov sp, r7
800307c: bc80 pop {r7}
800307e: 4770 bx lr
8003080: e000e100 .word 0xe000e100
08003084 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003084: b480 push {r7}
8003086: b083 sub sp, #12
8003088: af00 add r7, sp, #0
800308a: 4603 mov r3, r0
800308c: 6039 str r1, [r7, #0]
800308e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003090: f997 3007 ldrsb.w r3, [r7, #7]
8003094: 2b00 cmp r3, #0
8003096: db0a blt.n 80030ae <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003098: 683b ldr r3, [r7, #0]
800309a: b2da uxtb r2, r3
800309c: 490c ldr r1, [pc, #48] @ (80030d0 <__NVIC_SetPriority+0x4c>)
800309e: f997 3007 ldrsb.w r3, [r7, #7]
80030a2: 0112 lsls r2, r2, #4
80030a4: b2d2 uxtb r2, r2
80030a6: 440b add r3, r1
80030a8: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80030ac: e00a b.n 80030c4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80030ae: 683b ldr r3, [r7, #0]
80030b0: b2da uxtb r2, r3
80030b2: 4908 ldr r1, [pc, #32] @ (80030d4 <__NVIC_SetPriority+0x50>)
80030b4: 79fb ldrb r3, [r7, #7]
80030b6: f003 030f and.w r3, r3, #15
80030ba: 3b04 subs r3, #4
80030bc: 0112 lsls r2, r2, #4
80030be: b2d2 uxtb r2, r2
80030c0: 440b add r3, r1
80030c2: 761a strb r2, [r3, #24]
}
80030c4: bf00 nop
80030c6: 370c adds r7, #12
80030c8: 46bd mov sp, r7
80030ca: bc80 pop {r7}
80030cc: 4770 bx lr
80030ce: bf00 nop
80030d0: e000e100 .word 0xe000e100
80030d4: e000ed00 .word 0xe000ed00
080030d8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80030d8: b480 push {r7}
80030da: b089 sub sp, #36 @ 0x24
80030dc: af00 add r7, sp, #0
80030de: 60f8 str r0, [r7, #12]
80030e0: 60b9 str r1, [r7, #8]
80030e2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80030e4: 68fb ldr r3, [r7, #12]
80030e6: f003 0307 and.w r3, r3, #7
80030ea: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80030ec: 69fb ldr r3, [r7, #28]
80030ee: f1c3 0307 rsb r3, r3, #7
80030f2: 2b04 cmp r3, #4
80030f4: bf28 it cs
80030f6: 2304 movcs r3, #4
80030f8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80030fa: 69fb ldr r3, [r7, #28]
80030fc: 3304 adds r3, #4
80030fe: 2b06 cmp r3, #6
8003100: d902 bls.n 8003108 <NVIC_EncodePriority+0x30>
8003102: 69fb ldr r3, [r7, #28]
8003104: 3b03 subs r3, #3
8003106: e000 b.n 800310a <NVIC_EncodePriority+0x32>
8003108: 2300 movs r3, #0
800310a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800310c: f04f 32ff mov.w r2, #4294967295
8003110: 69bb ldr r3, [r7, #24]
8003112: fa02 f303 lsl.w r3, r2, r3
8003116: 43da mvns r2, r3
8003118: 68bb ldr r3, [r7, #8]
800311a: 401a ands r2, r3
800311c: 697b ldr r3, [r7, #20]
800311e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003120: f04f 31ff mov.w r1, #4294967295
8003124: 697b ldr r3, [r7, #20]
8003126: fa01 f303 lsl.w r3, r1, r3
800312a: 43d9 mvns r1, r3
800312c: 687b ldr r3, [r7, #4]
800312e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003130: 4313 orrs r3, r2
);
}
8003132: 4618 mov r0, r3
8003134: 3724 adds r7, #36 @ 0x24
8003136: 46bd mov sp, r7
8003138: bc80 pop {r7}
800313a: 4770 bx lr
0800313c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800313c: b580 push {r7, lr}
800313e: b082 sub sp, #8
8003140: af00 add r7, sp, #0
8003142: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003144: 687b ldr r3, [r7, #4]
8003146: 3b01 subs r3, #1
8003148: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
800314c: d301 bcc.n 8003152 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800314e: 2301 movs r3, #1
8003150: e00f b.n 8003172 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003152: 4a0a ldr r2, [pc, #40] @ (800317c <SysTick_Config+0x40>)
8003154: 687b ldr r3, [r7, #4]
8003156: 3b01 subs r3, #1
8003158: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800315a: 210f movs r1, #15
800315c: f04f 30ff mov.w r0, #4294967295
8003160: f7ff ff90 bl 8003084 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003164: 4b05 ldr r3, [pc, #20] @ (800317c <SysTick_Config+0x40>)
8003166: 2200 movs r2, #0
8003168: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800316a: 4b04 ldr r3, [pc, #16] @ (800317c <SysTick_Config+0x40>)
800316c: 2207 movs r2, #7
800316e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003170: 2300 movs r3, #0
}
8003172: 4618 mov r0, r3
8003174: 3708 adds r7, #8
8003176: 46bd mov sp, r7
8003178: bd80 pop {r7, pc}
800317a: bf00 nop
800317c: e000e010 .word 0xe000e010
08003180 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003180: b580 push {r7, lr}
8003182: b082 sub sp, #8
8003184: af00 add r7, sp, #0
8003186: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003188: 6878 ldr r0, [r7, #4]
800318a: f7ff ff2d bl 8002fe8 <__NVIC_SetPriorityGrouping>
}
800318e: bf00 nop
8003190: 3708 adds r7, #8
8003192: 46bd mov sp, r7
8003194: bd80 pop {r7, pc}
08003196 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003196: b580 push {r7, lr}
8003198: b086 sub sp, #24
800319a: af00 add r7, sp, #0
800319c: 4603 mov r3, r0
800319e: 60b9 str r1, [r7, #8]
80031a0: 607a str r2, [r7, #4]
80031a2: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80031a4: 2300 movs r3, #0
80031a6: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80031a8: f7ff ff42 bl 8003030 <__NVIC_GetPriorityGrouping>
80031ac: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80031ae: 687a ldr r2, [r7, #4]
80031b0: 68b9 ldr r1, [r7, #8]
80031b2: 6978 ldr r0, [r7, #20]
80031b4: f7ff ff90 bl 80030d8 <NVIC_EncodePriority>
80031b8: 4602 mov r2, r0
80031ba: f997 300f ldrsb.w r3, [r7, #15]
80031be: 4611 mov r1, r2
80031c0: 4618 mov r0, r3
80031c2: f7ff ff5f bl 8003084 <__NVIC_SetPriority>
}
80031c6: bf00 nop
80031c8: 3718 adds r7, #24
80031ca: 46bd mov sp, r7
80031cc: bd80 pop {r7, pc}
080031ce <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80031ce: b580 push {r7, lr}
80031d0: b082 sub sp, #8
80031d2: af00 add r7, sp, #0
80031d4: 4603 mov r3, r0
80031d6: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80031d8: f997 3007 ldrsb.w r3, [r7, #7]
80031dc: 4618 mov r0, r3
80031de: f7ff ff35 bl 800304c <__NVIC_EnableIRQ>
}
80031e2: bf00 nop
80031e4: 3708 adds r7, #8
80031e6: 46bd mov sp, r7
80031e8: bd80 pop {r7, pc}
080031ea <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80031ea: b580 push {r7, lr}
80031ec: b082 sub sp, #8
80031ee: af00 add r7, sp, #0
80031f0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80031f2: 6878 ldr r0, [r7, #4]
80031f4: f7ff ffa2 bl 800313c <SysTick_Config>
80031f8: 4603 mov r3, r0
}
80031fa: 4618 mov r0, r3
80031fc: 3708 adds r7, #8
80031fe: 46bd mov sp, r7
8003200: bd80 pop {r7, pc}
08003202 <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003202: b480 push {r7}
8003204: b085 sub sp, #20
8003206: af00 add r7, sp, #0
8003208: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800320a: 2300 movs r3, #0
800320c: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
800320e: 687b ldr r3, [r7, #4]
8003210: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003214: b2db uxtb r3, r3
8003216: 2b02 cmp r3, #2
8003218: d008 beq.n 800322c <HAL_DMA_Abort+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800321a: 687b ldr r3, [r7, #4]
800321c: 2204 movs r2, #4
800321e: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003220: 687b ldr r3, [r7, #4]
8003222: 2200 movs r2, #0
8003224: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8003228: 2301 movs r3, #1
800322a: e020 b.n 800326e <HAL_DMA_Abort+0x6c>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800322c: 687b ldr r3, [r7, #4]
800322e: 681b ldr r3, [r3, #0]
8003230: 681a ldr r2, [r3, #0]
8003232: 687b ldr r3, [r7, #4]
8003234: 681b ldr r3, [r3, #0]
8003236: f022 020e bic.w r2, r2, #14
800323a: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800323c: 687b ldr r3, [r7, #4]
800323e: 681b ldr r3, [r3, #0]
8003240: 681a ldr r2, [r3, #0]
8003242: 687b ldr r3, [r7, #4]
8003244: 681b ldr r3, [r3, #0]
8003246: f022 0201 bic.w r2, r2, #1
800324a: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
800324c: 687b ldr r3, [r7, #4]
800324e: 6c1a ldr r2, [r3, #64] @ 0x40
8003250: 687b ldr r3, [r7, #4]
8003252: 6bdb ldr r3, [r3, #60] @ 0x3c
8003254: 2101 movs r1, #1
8003256: fa01 f202 lsl.w r2, r1, r2
800325a: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800325c: 687b ldr r3, [r7, #4]
800325e: 2201 movs r2, #1
8003260: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003264: 687b ldr r3, [r7, #4]
8003266: 2200 movs r2, #0
8003268: f883 2020 strb.w r2, [r3, #32]
return status;
800326c: 7bfb ldrb r3, [r7, #15]
}
800326e: 4618 mov r0, r3
8003270: 3714 adds r7, #20
8003272: 46bd mov sp, r7
8003274: bc80 pop {r7}
8003276: 4770 bx lr
08003278 <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8003278: b580 push {r7, lr}
800327a: b084 sub sp, #16
800327c: af00 add r7, sp, #0
800327e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003280: 2300 movs r3, #0
8003282: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8003284: 687b ldr r3, [r7, #4]
8003286: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
800328a: b2db uxtb r3, r3
800328c: 2b02 cmp r3, #2
800328e: d005 beq.n 800329c <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003290: 687b ldr r3, [r7, #4]
8003292: 2204 movs r2, #4
8003294: 639a str r2, [r3, #56] @ 0x38
status = HAL_ERROR;
8003296: 2301 movs r3, #1
8003298: 73fb strb r3, [r7, #15]
800329a: e051 b.n 8003340 <HAL_DMA_Abort_IT+0xc8>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800329c: 687b ldr r3, [r7, #4]
800329e: 681b ldr r3, [r3, #0]
80032a0: 681a ldr r2, [r3, #0]
80032a2: 687b ldr r3, [r7, #4]
80032a4: 681b ldr r3, [r3, #0]
80032a6: f022 020e bic.w r2, r2, #14
80032aa: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80032ac: 687b ldr r3, [r7, #4]
80032ae: 681b ldr r3, [r3, #0]
80032b0: 681a ldr r2, [r3, #0]
80032b2: 687b ldr r3, [r7, #4]
80032b4: 681b ldr r3, [r3, #0]
80032b6: f022 0201 bic.w r2, r2, #1
80032ba: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
80032bc: 687b ldr r3, [r7, #4]
80032be: 681b ldr r3, [r3, #0]
80032c0: 4a22 ldr r2, [pc, #136] @ (800334c <HAL_DMA_Abort_IT+0xd4>)
80032c2: 4293 cmp r3, r2
80032c4: d029 beq.n 800331a <HAL_DMA_Abort_IT+0xa2>
80032c6: 687b ldr r3, [r7, #4]
80032c8: 681b ldr r3, [r3, #0]
80032ca: 4a21 ldr r2, [pc, #132] @ (8003350 <HAL_DMA_Abort_IT+0xd8>)
80032cc: 4293 cmp r3, r2
80032ce: d022 beq.n 8003316 <HAL_DMA_Abort_IT+0x9e>
80032d0: 687b ldr r3, [r7, #4]
80032d2: 681b ldr r3, [r3, #0]
80032d4: 4a1f ldr r2, [pc, #124] @ (8003354 <HAL_DMA_Abort_IT+0xdc>)
80032d6: 4293 cmp r3, r2
80032d8: d01a beq.n 8003310 <HAL_DMA_Abort_IT+0x98>
80032da: 687b ldr r3, [r7, #4]
80032dc: 681b ldr r3, [r3, #0]
80032de: 4a1e ldr r2, [pc, #120] @ (8003358 <HAL_DMA_Abort_IT+0xe0>)
80032e0: 4293 cmp r3, r2
80032e2: d012 beq.n 800330a <HAL_DMA_Abort_IT+0x92>
80032e4: 687b ldr r3, [r7, #4]
80032e6: 681b ldr r3, [r3, #0]
80032e8: 4a1c ldr r2, [pc, #112] @ (800335c <HAL_DMA_Abort_IT+0xe4>)
80032ea: 4293 cmp r3, r2
80032ec: d00a beq.n 8003304 <HAL_DMA_Abort_IT+0x8c>
80032ee: 687b ldr r3, [r7, #4]
80032f0: 681b ldr r3, [r3, #0]
80032f2: 4a1b ldr r2, [pc, #108] @ (8003360 <HAL_DMA_Abort_IT+0xe8>)
80032f4: 4293 cmp r3, r2
80032f6: d102 bne.n 80032fe <HAL_DMA_Abort_IT+0x86>
80032f8: f44f 1380 mov.w r3, #1048576 @ 0x100000
80032fc: e00e b.n 800331c <HAL_DMA_Abort_IT+0xa4>
80032fe: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8003302: e00b b.n 800331c <HAL_DMA_Abort_IT+0xa4>
8003304: f44f 3380 mov.w r3, #65536 @ 0x10000
8003308: e008 b.n 800331c <HAL_DMA_Abort_IT+0xa4>
800330a: f44f 5380 mov.w r3, #4096 @ 0x1000
800330e: e005 b.n 800331c <HAL_DMA_Abort_IT+0xa4>
8003310: f44f 7380 mov.w r3, #256 @ 0x100
8003314: e002 b.n 800331c <HAL_DMA_Abort_IT+0xa4>
8003316: 2310 movs r3, #16
8003318: e000 b.n 800331c <HAL_DMA_Abort_IT+0xa4>
800331a: 2301 movs r3, #1
800331c: 4a11 ldr r2, [pc, #68] @ (8003364 <HAL_DMA_Abort_IT+0xec>)
800331e: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003320: 687b ldr r3, [r7, #4]
8003322: 2201 movs r2, #1
8003324: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003328: 687b ldr r3, [r7, #4]
800332a: 2200 movs r2, #0
800332c: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
8003330: 687b ldr r3, [r7, #4]
8003332: 6b5b ldr r3, [r3, #52] @ 0x34
8003334: 2b00 cmp r3, #0
8003336: d003 beq.n 8003340 <HAL_DMA_Abort_IT+0xc8>
{
hdma->XferAbortCallback(hdma);
8003338: 687b ldr r3, [r7, #4]
800333a: 6b5b ldr r3, [r3, #52] @ 0x34
800333c: 6878 ldr r0, [r7, #4]
800333e: 4798 blx r3
}
}
return status;
8003340: 7bfb ldrb r3, [r7, #15]
}
8003342: 4618 mov r0, r3
8003344: 3710 adds r7, #16
8003346: 46bd mov sp, r7
8003348: bd80 pop {r7, pc}
800334a: bf00 nop
800334c: 40020008 .word 0x40020008
8003350: 4002001c .word 0x4002001c
8003354: 40020030 .word 0x40020030
8003358: 40020044 .word 0x40020044
800335c: 40020058 .word 0x40020058
8003360: 4002006c .word 0x4002006c
8003364: 40020000 .word 0x40020000
08003368 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003368: b480 push {r7}
800336a: b08b sub sp, #44 @ 0x2c
800336c: af00 add r7, sp, #0
800336e: 6078 str r0, [r7, #4]
8003370: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003372: 2300 movs r3, #0
8003374: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8003376: 2300 movs r3, #0
8003378: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800337a: e169 b.n 8003650 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
800337c: 2201 movs r2, #1
800337e: 6a7b ldr r3, [r7, #36] @ 0x24
8003380: fa02 f303 lsl.w r3, r2, r3
8003384: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8003386: 683b ldr r3, [r7, #0]
8003388: 681b ldr r3, [r3, #0]
800338a: 69fa ldr r2, [r7, #28]
800338c: 4013 ands r3, r2
800338e: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8003390: 69ba ldr r2, [r7, #24]
8003392: 69fb ldr r3, [r7, #28]
8003394: 429a cmp r2, r3
8003396: f040 8158 bne.w 800364a <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800339a: 683b ldr r3, [r7, #0]
800339c: 685b ldr r3, [r3, #4]
800339e: 4a9a ldr r2, [pc, #616] @ (8003608 <HAL_GPIO_Init+0x2a0>)
80033a0: 4293 cmp r3, r2
80033a2: d05e beq.n 8003462 <HAL_GPIO_Init+0xfa>
80033a4: 4a98 ldr r2, [pc, #608] @ (8003608 <HAL_GPIO_Init+0x2a0>)
80033a6: 4293 cmp r3, r2
80033a8: d875 bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033aa: 4a98 ldr r2, [pc, #608] @ (800360c <HAL_GPIO_Init+0x2a4>)
80033ac: 4293 cmp r3, r2
80033ae: d058 beq.n 8003462 <HAL_GPIO_Init+0xfa>
80033b0: 4a96 ldr r2, [pc, #600] @ (800360c <HAL_GPIO_Init+0x2a4>)
80033b2: 4293 cmp r3, r2
80033b4: d86f bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033b6: 4a96 ldr r2, [pc, #600] @ (8003610 <HAL_GPIO_Init+0x2a8>)
80033b8: 4293 cmp r3, r2
80033ba: d052 beq.n 8003462 <HAL_GPIO_Init+0xfa>
80033bc: 4a94 ldr r2, [pc, #592] @ (8003610 <HAL_GPIO_Init+0x2a8>)
80033be: 4293 cmp r3, r2
80033c0: d869 bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033c2: 4a94 ldr r2, [pc, #592] @ (8003614 <HAL_GPIO_Init+0x2ac>)
80033c4: 4293 cmp r3, r2
80033c6: d04c beq.n 8003462 <HAL_GPIO_Init+0xfa>
80033c8: 4a92 ldr r2, [pc, #584] @ (8003614 <HAL_GPIO_Init+0x2ac>)
80033ca: 4293 cmp r3, r2
80033cc: d863 bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033ce: 4a92 ldr r2, [pc, #584] @ (8003618 <HAL_GPIO_Init+0x2b0>)
80033d0: 4293 cmp r3, r2
80033d2: d046 beq.n 8003462 <HAL_GPIO_Init+0xfa>
80033d4: 4a90 ldr r2, [pc, #576] @ (8003618 <HAL_GPIO_Init+0x2b0>)
80033d6: 4293 cmp r3, r2
80033d8: d85d bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033da: 2b12 cmp r3, #18
80033dc: d82a bhi.n 8003434 <HAL_GPIO_Init+0xcc>
80033de: 2b12 cmp r3, #18
80033e0: d859 bhi.n 8003496 <HAL_GPIO_Init+0x12e>
80033e2: a201 add r2, pc, #4 @ (adr r2, 80033e8 <HAL_GPIO_Init+0x80>)
80033e4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80033e8: 08003463 .word 0x08003463
80033ec: 0800343d .word 0x0800343d
80033f0: 0800344f .word 0x0800344f
80033f4: 08003491 .word 0x08003491
80033f8: 08003497 .word 0x08003497
80033fc: 08003497 .word 0x08003497
8003400: 08003497 .word 0x08003497
8003404: 08003497 .word 0x08003497
8003408: 08003497 .word 0x08003497
800340c: 08003497 .word 0x08003497
8003410: 08003497 .word 0x08003497
8003414: 08003497 .word 0x08003497
8003418: 08003497 .word 0x08003497
800341c: 08003497 .word 0x08003497
8003420: 08003497 .word 0x08003497
8003424: 08003497 .word 0x08003497
8003428: 08003497 .word 0x08003497
800342c: 08003445 .word 0x08003445
8003430: 08003459 .word 0x08003459
8003434: 4a79 ldr r2, [pc, #484] @ (800361c <HAL_GPIO_Init+0x2b4>)
8003436: 4293 cmp r3, r2
8003438: d013 beq.n 8003462 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800343a: e02c b.n 8003496 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
800343c: 683b ldr r3, [r7, #0]
800343e: 68db ldr r3, [r3, #12]
8003440: 623b str r3, [r7, #32]
break;
8003442: e029 b.n 8003498 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003444: 683b ldr r3, [r7, #0]
8003446: 68db ldr r3, [r3, #12]
8003448: 3304 adds r3, #4
800344a: 623b str r3, [r7, #32]
break;
800344c: e024 b.n 8003498 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800344e: 683b ldr r3, [r7, #0]
8003450: 68db ldr r3, [r3, #12]
8003452: 3308 adds r3, #8
8003454: 623b str r3, [r7, #32]
break;
8003456: e01f b.n 8003498 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8003458: 683b ldr r3, [r7, #0]
800345a: 68db ldr r3, [r3, #12]
800345c: 330c adds r3, #12
800345e: 623b str r3, [r7, #32]
break;
8003460: e01a b.n 8003498 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8003462: 683b ldr r3, [r7, #0]
8003464: 689b ldr r3, [r3, #8]
8003466: 2b00 cmp r3, #0
8003468: d102 bne.n 8003470 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800346a: 2304 movs r3, #4
800346c: 623b str r3, [r7, #32]
break;
800346e: e013 b.n 8003498 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8003470: 683b ldr r3, [r7, #0]
8003472: 689b ldr r3, [r3, #8]
8003474: 2b01 cmp r3, #1
8003476: d105 bne.n 8003484 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003478: 2308 movs r3, #8
800347a: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
800347c: 687b ldr r3, [r7, #4]
800347e: 69fa ldr r2, [r7, #28]
8003480: 611a str r2, [r3, #16]
break;
8003482: e009 b.n 8003498 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003484: 2308 movs r3, #8
8003486: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8003488: 687b ldr r3, [r7, #4]
800348a: 69fa ldr r2, [r7, #28]
800348c: 615a str r2, [r3, #20]
break;
800348e: e003 b.n 8003498 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8003490: 2300 movs r3, #0
8003492: 623b str r3, [r7, #32]
break;
8003494: e000 b.n 8003498 <HAL_GPIO_Init+0x130>
break;
8003496: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8003498: 69bb ldr r3, [r7, #24]
800349a: 2bff cmp r3, #255 @ 0xff
800349c: d801 bhi.n 80034a2 <HAL_GPIO_Init+0x13a>
800349e: 687b ldr r3, [r7, #4]
80034a0: e001 b.n 80034a6 <HAL_GPIO_Init+0x13e>
80034a2: 687b ldr r3, [r7, #4]
80034a4: 3304 adds r3, #4
80034a6: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80034a8: 69bb ldr r3, [r7, #24]
80034aa: 2bff cmp r3, #255 @ 0xff
80034ac: d802 bhi.n 80034b4 <HAL_GPIO_Init+0x14c>
80034ae: 6a7b ldr r3, [r7, #36] @ 0x24
80034b0: 009b lsls r3, r3, #2
80034b2: e002 b.n 80034ba <HAL_GPIO_Init+0x152>
80034b4: 6a7b ldr r3, [r7, #36] @ 0x24
80034b6: 3b08 subs r3, #8
80034b8: 009b lsls r3, r3, #2
80034ba: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80034bc: 697b ldr r3, [r7, #20]
80034be: 681a ldr r2, [r3, #0]
80034c0: 210f movs r1, #15
80034c2: 693b ldr r3, [r7, #16]
80034c4: fa01 f303 lsl.w r3, r1, r3
80034c8: 43db mvns r3, r3
80034ca: 401a ands r2, r3
80034cc: 6a39 ldr r1, [r7, #32]
80034ce: 693b ldr r3, [r7, #16]
80034d0: fa01 f303 lsl.w r3, r1, r3
80034d4: 431a orrs r2, r3
80034d6: 697b ldr r3, [r7, #20]
80034d8: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80034da: 683b ldr r3, [r7, #0]
80034dc: 685b ldr r3, [r3, #4]
80034de: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80034e2: 2b00 cmp r3, #0
80034e4: f000 80b1 beq.w 800364a <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80034e8: 4b4d ldr r3, [pc, #308] @ (8003620 <HAL_GPIO_Init+0x2b8>)
80034ea: 699b ldr r3, [r3, #24]
80034ec: 4a4c ldr r2, [pc, #304] @ (8003620 <HAL_GPIO_Init+0x2b8>)
80034ee: f043 0301 orr.w r3, r3, #1
80034f2: 6193 str r3, [r2, #24]
80034f4: 4b4a ldr r3, [pc, #296] @ (8003620 <HAL_GPIO_Init+0x2b8>)
80034f6: 699b ldr r3, [r3, #24]
80034f8: f003 0301 and.w r3, r3, #1
80034fc: 60bb str r3, [r7, #8]
80034fe: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8003500: 4a48 ldr r2, [pc, #288] @ (8003624 <HAL_GPIO_Init+0x2bc>)
8003502: 6a7b ldr r3, [r7, #36] @ 0x24
8003504: 089b lsrs r3, r3, #2
8003506: 3302 adds r3, #2
8003508: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800350c: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
800350e: 6a7b ldr r3, [r7, #36] @ 0x24
8003510: f003 0303 and.w r3, r3, #3
8003514: 009b lsls r3, r3, #2
8003516: 220f movs r2, #15
8003518: fa02 f303 lsl.w r3, r2, r3
800351c: 43db mvns r3, r3
800351e: 68fa ldr r2, [r7, #12]
8003520: 4013 ands r3, r2
8003522: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003524: 687b ldr r3, [r7, #4]
8003526: 4a40 ldr r2, [pc, #256] @ (8003628 <HAL_GPIO_Init+0x2c0>)
8003528: 4293 cmp r3, r2
800352a: d013 beq.n 8003554 <HAL_GPIO_Init+0x1ec>
800352c: 687b ldr r3, [r7, #4]
800352e: 4a3f ldr r2, [pc, #252] @ (800362c <HAL_GPIO_Init+0x2c4>)
8003530: 4293 cmp r3, r2
8003532: d00d beq.n 8003550 <HAL_GPIO_Init+0x1e8>
8003534: 687b ldr r3, [r7, #4]
8003536: 4a3e ldr r2, [pc, #248] @ (8003630 <HAL_GPIO_Init+0x2c8>)
8003538: 4293 cmp r3, r2
800353a: d007 beq.n 800354c <HAL_GPIO_Init+0x1e4>
800353c: 687b ldr r3, [r7, #4]
800353e: 4a3d ldr r2, [pc, #244] @ (8003634 <HAL_GPIO_Init+0x2cc>)
8003540: 4293 cmp r3, r2
8003542: d101 bne.n 8003548 <HAL_GPIO_Init+0x1e0>
8003544: 2303 movs r3, #3
8003546: e006 b.n 8003556 <HAL_GPIO_Init+0x1ee>
8003548: 2304 movs r3, #4
800354a: e004 b.n 8003556 <HAL_GPIO_Init+0x1ee>
800354c: 2302 movs r3, #2
800354e: e002 b.n 8003556 <HAL_GPIO_Init+0x1ee>
8003550: 2301 movs r3, #1
8003552: e000 b.n 8003556 <HAL_GPIO_Init+0x1ee>
8003554: 2300 movs r3, #0
8003556: 6a7a ldr r2, [r7, #36] @ 0x24
8003558: f002 0203 and.w r2, r2, #3
800355c: 0092 lsls r2, r2, #2
800355e: 4093 lsls r3, r2
8003560: 68fa ldr r2, [r7, #12]
8003562: 4313 orrs r3, r2
8003564: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8003566: 492f ldr r1, [pc, #188] @ (8003624 <HAL_GPIO_Init+0x2bc>)
8003568: 6a7b ldr r3, [r7, #36] @ 0x24
800356a: 089b lsrs r3, r3, #2
800356c: 3302 adds r3, #2
800356e: 68fa ldr r2, [r7, #12]
8003570: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003574: 683b ldr r3, [r7, #0]
8003576: 685b ldr r3, [r3, #4]
8003578: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800357c: 2b00 cmp r3, #0
800357e: d006 beq.n 800358e <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8003580: 4b2d ldr r3, [pc, #180] @ (8003638 <HAL_GPIO_Init+0x2d0>)
8003582: 689a ldr r2, [r3, #8]
8003584: 492c ldr r1, [pc, #176] @ (8003638 <HAL_GPIO_Init+0x2d0>)
8003586: 69bb ldr r3, [r7, #24]
8003588: 4313 orrs r3, r2
800358a: 608b str r3, [r1, #8]
800358c: e006 b.n 800359c <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
800358e: 4b2a ldr r3, [pc, #168] @ (8003638 <HAL_GPIO_Init+0x2d0>)
8003590: 689a ldr r2, [r3, #8]
8003592: 69bb ldr r3, [r7, #24]
8003594: 43db mvns r3, r3
8003596: 4928 ldr r1, [pc, #160] @ (8003638 <HAL_GPIO_Init+0x2d0>)
8003598: 4013 ands r3, r2
800359a: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
800359c: 683b ldr r3, [r7, #0]
800359e: 685b ldr r3, [r3, #4]
80035a0: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80035a4: 2b00 cmp r3, #0
80035a6: d006 beq.n 80035b6 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
80035a8: 4b23 ldr r3, [pc, #140] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035aa: 68da ldr r2, [r3, #12]
80035ac: 4922 ldr r1, [pc, #136] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035ae: 69bb ldr r3, [r7, #24]
80035b0: 4313 orrs r3, r2
80035b2: 60cb str r3, [r1, #12]
80035b4: e006 b.n 80035c4 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
80035b6: 4b20 ldr r3, [pc, #128] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035b8: 68da ldr r2, [r3, #12]
80035ba: 69bb ldr r3, [r7, #24]
80035bc: 43db mvns r3, r3
80035be: 491e ldr r1, [pc, #120] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035c0: 4013 ands r3, r2
80035c2: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80035c4: 683b ldr r3, [r7, #0]
80035c6: 685b ldr r3, [r3, #4]
80035c8: f403 3300 and.w r3, r3, #131072 @ 0x20000
80035cc: 2b00 cmp r3, #0
80035ce: d006 beq.n 80035de <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
80035d0: 4b19 ldr r3, [pc, #100] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035d2: 685a ldr r2, [r3, #4]
80035d4: 4918 ldr r1, [pc, #96] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035d6: 69bb ldr r3, [r7, #24]
80035d8: 4313 orrs r3, r2
80035da: 604b str r3, [r1, #4]
80035dc: e006 b.n 80035ec <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
80035de: 4b16 ldr r3, [pc, #88] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035e0: 685a ldr r2, [r3, #4]
80035e2: 69bb ldr r3, [r7, #24]
80035e4: 43db mvns r3, r3
80035e6: 4914 ldr r1, [pc, #80] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035e8: 4013 ands r3, r2
80035ea: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80035ec: 683b ldr r3, [r7, #0]
80035ee: 685b ldr r3, [r3, #4]
80035f0: f403 3380 and.w r3, r3, #65536 @ 0x10000
80035f4: 2b00 cmp r3, #0
80035f6: d021 beq.n 800363c <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
80035f8: 4b0f ldr r3, [pc, #60] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035fa: 681a ldr r2, [r3, #0]
80035fc: 490e ldr r1, [pc, #56] @ (8003638 <HAL_GPIO_Init+0x2d0>)
80035fe: 69bb ldr r3, [r7, #24]
8003600: 4313 orrs r3, r2
8003602: 600b str r3, [r1, #0]
8003604: e021 b.n 800364a <HAL_GPIO_Init+0x2e2>
8003606: bf00 nop
8003608: 10320000 .word 0x10320000
800360c: 10310000 .word 0x10310000
8003610: 10220000 .word 0x10220000
8003614: 10210000 .word 0x10210000
8003618: 10120000 .word 0x10120000
800361c: 10110000 .word 0x10110000
8003620: 40021000 .word 0x40021000
8003624: 40010000 .word 0x40010000
8003628: 40010800 .word 0x40010800
800362c: 40010c00 .word 0x40010c00
8003630: 40011000 .word 0x40011000
8003634: 40011400 .word 0x40011400
8003638: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
800363c: 4b0b ldr r3, [pc, #44] @ (800366c <HAL_GPIO_Init+0x304>)
800363e: 681a ldr r2, [r3, #0]
8003640: 69bb ldr r3, [r7, #24]
8003642: 43db mvns r3, r3
8003644: 4909 ldr r1, [pc, #36] @ (800366c <HAL_GPIO_Init+0x304>)
8003646: 4013 ands r3, r2
8003648: 600b str r3, [r1, #0]
}
}
}
position++;
800364a: 6a7b ldr r3, [r7, #36] @ 0x24
800364c: 3301 adds r3, #1
800364e: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003650: 683b ldr r3, [r7, #0]
8003652: 681a ldr r2, [r3, #0]
8003654: 6a7b ldr r3, [r7, #36] @ 0x24
8003656: fa22 f303 lsr.w r3, r2, r3
800365a: 2b00 cmp r3, #0
800365c: f47f ae8e bne.w 800337c <HAL_GPIO_Init+0x14>
}
}
8003660: bf00 nop
8003662: bf00 nop
8003664: 372c adds r7, #44 @ 0x2c
8003666: 46bd mov sp, r7
8003668: bc80 pop {r7}
800366a: 4770 bx lr
800366c: 40010400 .word 0x40010400
08003670 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003670: b480 push {r7}
8003672: b085 sub sp, #20
8003674: af00 add r7, sp, #0
8003676: 6078 str r0, [r7, #4]
8003678: 460b mov r3, r1
800367a: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
800367c: 687b ldr r3, [r7, #4]
800367e: 689a ldr r2, [r3, #8]
8003680: 887b ldrh r3, [r7, #2]
8003682: 4013 ands r3, r2
8003684: 2b00 cmp r3, #0
8003686: d002 beq.n 800368e <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8003688: 2301 movs r3, #1
800368a: 73fb strb r3, [r7, #15]
800368c: e001 b.n 8003692 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
800368e: 2300 movs r3, #0
8003690: 73fb strb r3, [r7, #15]
}
return bitstatus;
8003692: 7bfb ldrb r3, [r7, #15]
}
8003694: 4618 mov r0, r3
8003696: 3714 adds r7, #20
8003698: 46bd mov sp, r7
800369a: bc80 pop {r7}
800369c: 4770 bx lr
0800369e <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800369e: b480 push {r7}
80036a0: b083 sub sp, #12
80036a2: af00 add r7, sp, #0
80036a4: 6078 str r0, [r7, #4]
80036a6: 460b mov r3, r1
80036a8: 807b strh r3, [r7, #2]
80036aa: 4613 mov r3, r2
80036ac: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80036ae: 787b ldrb r3, [r7, #1]
80036b0: 2b00 cmp r3, #0
80036b2: d003 beq.n 80036bc <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80036b4: 887a ldrh r2, [r7, #2]
80036b6: 687b ldr r3, [r7, #4]
80036b8: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
80036ba: e003 b.n 80036c4 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
80036bc: 887b ldrh r3, [r7, #2]
80036be: 041a lsls r2, r3, #16
80036c0: 687b ldr r3, [r7, #4]
80036c2: 611a str r2, [r3, #16]
}
80036c4: bf00 nop
80036c6: 370c adds r7, #12
80036c8: 46bd mov sp, r7
80036ca: bc80 pop {r7}
80036cc: 4770 bx lr
080036ce <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80036ce: b480 push {r7}
80036d0: b085 sub sp, #20
80036d2: af00 add r7, sp, #0
80036d4: 6078 str r0, [r7, #4]
80036d6: 460b mov r3, r1
80036d8: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
80036da: 687b ldr r3, [r7, #4]
80036dc: 68db ldr r3, [r3, #12]
80036de: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
80036e0: 887a ldrh r2, [r7, #2]
80036e2: 68fb ldr r3, [r7, #12]
80036e4: 4013 ands r3, r2
80036e6: 041a lsls r2, r3, #16
80036e8: 68fb ldr r3, [r7, #12]
80036ea: 43d9 mvns r1, r3
80036ec: 887b ldrh r3, [r7, #2]
80036ee: 400b ands r3, r1
80036f0: 431a orrs r2, r3
80036f2: 687b ldr r3, [r7, #4]
80036f4: 611a str r2, [r3, #16]
}
80036f6: bf00 nop
80036f8: 3714 adds r7, #20
80036fa: 46bd mov sp, r7
80036fc: bc80 pop {r7}
80036fe: 4770 bx lr
08003700 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003700: b580 push {r7, lr}
8003702: b084 sub sp, #16
8003704: af00 add r7, sp, #0
8003706: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003708: 687b ldr r3, [r7, #4]
800370a: 2b00 cmp r3, #0
800370c: d101 bne.n 8003712 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800370e: 2301 movs r3, #1
8003710: e12b b.n 800396a <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003712: 687b ldr r3, [r7, #4]
8003714: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003718: b2db uxtb r3, r3
800371a: 2b00 cmp r3, #0
800371c: d106 bne.n 800372c <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
800371e: 687b ldr r3, [r7, #4]
8003720: 2200 movs r2, #0
8003722: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003726: 6878 ldr r0, [r7, #4]
8003728: f7fe fbf6 bl 8001f18 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
800372c: 687b ldr r3, [r7, #4]
800372e: 2224 movs r2, #36 @ 0x24
8003730: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003734: 687b ldr r3, [r7, #4]
8003736: 681b ldr r3, [r3, #0]
8003738: 681a ldr r2, [r3, #0]
800373a: 687b ldr r3, [r7, #4]
800373c: 681b ldr r3, [r3, #0]
800373e: f022 0201 bic.w r2, r2, #1
8003742: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003744: 687b ldr r3, [r7, #4]
8003746: 681b ldr r3, [r3, #0]
8003748: 681a ldr r2, [r3, #0]
800374a: 687b ldr r3, [r7, #4]
800374c: 681b ldr r3, [r3, #0]
800374e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003752: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003754: 687b ldr r3, [r7, #4]
8003756: 681b ldr r3, [r3, #0]
8003758: 681a ldr r2, [r3, #0]
800375a: 687b ldr r3, [r7, #4]
800375c: 681b ldr r3, [r3, #0]
800375e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003762: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003764: f001 fbcc bl 8004f00 <HAL_RCC_GetPCLK1Freq>
8003768: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
800376a: 687b ldr r3, [r7, #4]
800376c: 685b ldr r3, [r3, #4]
800376e: 4a81 ldr r2, [pc, #516] @ (8003974 <HAL_I2C_Init+0x274>)
8003770: 4293 cmp r3, r2
8003772: d807 bhi.n 8003784 <HAL_I2C_Init+0x84>
8003774: 68fb ldr r3, [r7, #12]
8003776: 4a80 ldr r2, [pc, #512] @ (8003978 <HAL_I2C_Init+0x278>)
8003778: 4293 cmp r3, r2
800377a: bf94 ite ls
800377c: 2301 movls r3, #1
800377e: 2300 movhi r3, #0
8003780: b2db uxtb r3, r3
8003782: e006 b.n 8003792 <HAL_I2C_Init+0x92>
8003784: 68fb ldr r3, [r7, #12]
8003786: 4a7d ldr r2, [pc, #500] @ (800397c <HAL_I2C_Init+0x27c>)
8003788: 4293 cmp r3, r2
800378a: bf94 ite ls
800378c: 2301 movls r3, #1
800378e: 2300 movhi r3, #0
8003790: b2db uxtb r3, r3
8003792: 2b00 cmp r3, #0
8003794: d001 beq.n 800379a <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003796: 2301 movs r3, #1
8003798: e0e7 b.n 800396a <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
800379a: 68fb ldr r3, [r7, #12]
800379c: 4a78 ldr r2, [pc, #480] @ (8003980 <HAL_I2C_Init+0x280>)
800379e: fba2 2303 umull r2, r3, r2, r3
80037a2: 0c9b lsrs r3, r3, #18
80037a4: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
80037a6: 687b ldr r3, [r7, #4]
80037a8: 681b ldr r3, [r3, #0]
80037aa: 685b ldr r3, [r3, #4]
80037ac: f023 013f bic.w r1, r3, #63 @ 0x3f
80037b0: 687b ldr r3, [r7, #4]
80037b2: 681b ldr r3, [r3, #0]
80037b4: 68ba ldr r2, [r7, #8]
80037b6: 430a orrs r2, r1
80037b8: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
80037ba: 687b ldr r3, [r7, #4]
80037bc: 681b ldr r3, [r3, #0]
80037be: 6a1b ldr r3, [r3, #32]
80037c0: f023 013f bic.w r1, r3, #63 @ 0x3f
80037c4: 687b ldr r3, [r7, #4]
80037c6: 685b ldr r3, [r3, #4]
80037c8: 4a6a ldr r2, [pc, #424] @ (8003974 <HAL_I2C_Init+0x274>)
80037ca: 4293 cmp r3, r2
80037cc: d802 bhi.n 80037d4 <HAL_I2C_Init+0xd4>
80037ce: 68bb ldr r3, [r7, #8]
80037d0: 3301 adds r3, #1
80037d2: e009 b.n 80037e8 <HAL_I2C_Init+0xe8>
80037d4: 68bb ldr r3, [r7, #8]
80037d6: f44f 7296 mov.w r2, #300 @ 0x12c
80037da: fb02 f303 mul.w r3, r2, r3
80037de: 4a69 ldr r2, [pc, #420] @ (8003984 <HAL_I2C_Init+0x284>)
80037e0: fba2 2303 umull r2, r3, r2, r3
80037e4: 099b lsrs r3, r3, #6
80037e6: 3301 adds r3, #1
80037e8: 687a ldr r2, [r7, #4]
80037ea: 6812 ldr r2, [r2, #0]
80037ec: 430b orrs r3, r1
80037ee: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
80037f0: 687b ldr r3, [r7, #4]
80037f2: 681b ldr r3, [r3, #0]
80037f4: 69db ldr r3, [r3, #28]
80037f6: f423 424f bic.w r2, r3, #52992 @ 0xcf00
80037fa: f022 02ff bic.w r2, r2, #255 @ 0xff
80037fe: 687b ldr r3, [r7, #4]
8003800: 685b ldr r3, [r3, #4]
8003802: 495c ldr r1, [pc, #368] @ (8003974 <HAL_I2C_Init+0x274>)
8003804: 428b cmp r3, r1
8003806: d819 bhi.n 800383c <HAL_I2C_Init+0x13c>
8003808: 68fb ldr r3, [r7, #12]
800380a: 1e59 subs r1, r3, #1
800380c: 687b ldr r3, [r7, #4]
800380e: 685b ldr r3, [r3, #4]
8003810: 005b lsls r3, r3, #1
8003812: fbb1 f3f3 udiv r3, r1, r3
8003816: 1c59 adds r1, r3, #1
8003818: f640 73fc movw r3, #4092 @ 0xffc
800381c: 400b ands r3, r1
800381e: 2b00 cmp r3, #0
8003820: d00a beq.n 8003838 <HAL_I2C_Init+0x138>
8003822: 68fb ldr r3, [r7, #12]
8003824: 1e59 subs r1, r3, #1
8003826: 687b ldr r3, [r7, #4]
8003828: 685b ldr r3, [r3, #4]
800382a: 005b lsls r3, r3, #1
800382c: fbb1 f3f3 udiv r3, r1, r3
8003830: 3301 adds r3, #1
8003832: f3c3 030b ubfx r3, r3, #0, #12
8003836: e051 b.n 80038dc <HAL_I2C_Init+0x1dc>
8003838: 2304 movs r3, #4
800383a: e04f b.n 80038dc <HAL_I2C_Init+0x1dc>
800383c: 687b ldr r3, [r7, #4]
800383e: 689b ldr r3, [r3, #8]
8003840: 2b00 cmp r3, #0
8003842: d111 bne.n 8003868 <HAL_I2C_Init+0x168>
8003844: 68fb ldr r3, [r7, #12]
8003846: 1e58 subs r0, r3, #1
8003848: 687b ldr r3, [r7, #4]
800384a: 6859 ldr r1, [r3, #4]
800384c: 460b mov r3, r1
800384e: 005b lsls r3, r3, #1
8003850: 440b add r3, r1
8003852: fbb0 f3f3 udiv r3, r0, r3
8003856: 3301 adds r3, #1
8003858: f3c3 030b ubfx r3, r3, #0, #12
800385c: 2b00 cmp r3, #0
800385e: bf0c ite eq
8003860: 2301 moveq r3, #1
8003862: 2300 movne r3, #0
8003864: b2db uxtb r3, r3
8003866: e012 b.n 800388e <HAL_I2C_Init+0x18e>
8003868: 68fb ldr r3, [r7, #12]
800386a: 1e58 subs r0, r3, #1
800386c: 687b ldr r3, [r7, #4]
800386e: 6859 ldr r1, [r3, #4]
8003870: 460b mov r3, r1
8003872: 009b lsls r3, r3, #2
8003874: 440b add r3, r1
8003876: 0099 lsls r1, r3, #2
8003878: 440b add r3, r1
800387a: fbb0 f3f3 udiv r3, r0, r3
800387e: 3301 adds r3, #1
8003880: f3c3 030b ubfx r3, r3, #0, #12
8003884: 2b00 cmp r3, #0
8003886: bf0c ite eq
8003888: 2301 moveq r3, #1
800388a: 2300 movne r3, #0
800388c: b2db uxtb r3, r3
800388e: 2b00 cmp r3, #0
8003890: d001 beq.n 8003896 <HAL_I2C_Init+0x196>
8003892: 2301 movs r3, #1
8003894: e022 b.n 80038dc <HAL_I2C_Init+0x1dc>
8003896: 687b ldr r3, [r7, #4]
8003898: 689b ldr r3, [r3, #8]
800389a: 2b00 cmp r3, #0
800389c: d10e bne.n 80038bc <HAL_I2C_Init+0x1bc>
800389e: 68fb ldr r3, [r7, #12]
80038a0: 1e58 subs r0, r3, #1
80038a2: 687b ldr r3, [r7, #4]
80038a4: 6859 ldr r1, [r3, #4]
80038a6: 460b mov r3, r1
80038a8: 005b lsls r3, r3, #1
80038aa: 440b add r3, r1
80038ac: fbb0 f3f3 udiv r3, r0, r3
80038b0: 3301 adds r3, #1
80038b2: f3c3 030b ubfx r3, r3, #0, #12
80038b6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80038ba: e00f b.n 80038dc <HAL_I2C_Init+0x1dc>
80038bc: 68fb ldr r3, [r7, #12]
80038be: 1e58 subs r0, r3, #1
80038c0: 687b ldr r3, [r7, #4]
80038c2: 6859 ldr r1, [r3, #4]
80038c4: 460b mov r3, r1
80038c6: 009b lsls r3, r3, #2
80038c8: 440b add r3, r1
80038ca: 0099 lsls r1, r3, #2
80038cc: 440b add r3, r1
80038ce: fbb0 f3f3 udiv r3, r0, r3
80038d2: 3301 adds r3, #1
80038d4: f3c3 030b ubfx r3, r3, #0, #12
80038d8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80038dc: 6879 ldr r1, [r7, #4]
80038de: 6809 ldr r1, [r1, #0]
80038e0: 4313 orrs r3, r2
80038e2: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
80038e4: 687b ldr r3, [r7, #4]
80038e6: 681b ldr r3, [r3, #0]
80038e8: 681b ldr r3, [r3, #0]
80038ea: f023 01c0 bic.w r1, r3, #192 @ 0xc0
80038ee: 687b ldr r3, [r7, #4]
80038f0: 69da ldr r2, [r3, #28]
80038f2: 687b ldr r3, [r7, #4]
80038f4: 6a1b ldr r3, [r3, #32]
80038f6: 431a orrs r2, r3
80038f8: 687b ldr r3, [r7, #4]
80038fa: 681b ldr r3, [r3, #0]
80038fc: 430a orrs r2, r1
80038fe: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8003900: 687b ldr r3, [r7, #4]
8003902: 681b ldr r3, [r3, #0]
8003904: 689b ldr r3, [r3, #8]
8003906: f423 4303 bic.w r3, r3, #33536 @ 0x8300
800390a: f023 03ff bic.w r3, r3, #255 @ 0xff
800390e: 687a ldr r2, [r7, #4]
8003910: 6911 ldr r1, [r2, #16]
8003912: 687a ldr r2, [r7, #4]
8003914: 68d2 ldr r2, [r2, #12]
8003916: 4311 orrs r1, r2
8003918: 687a ldr r2, [r7, #4]
800391a: 6812 ldr r2, [r2, #0]
800391c: 430b orrs r3, r1
800391e: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
8003920: 687b ldr r3, [r7, #4]
8003922: 681b ldr r3, [r3, #0]
8003924: 68db ldr r3, [r3, #12]
8003926: f023 01ff bic.w r1, r3, #255 @ 0xff
800392a: 687b ldr r3, [r7, #4]
800392c: 695a ldr r2, [r3, #20]
800392e: 687b ldr r3, [r7, #4]
8003930: 699b ldr r3, [r3, #24]
8003932: 431a orrs r2, r3
8003934: 687b ldr r3, [r7, #4]
8003936: 681b ldr r3, [r3, #0]
8003938: 430a orrs r2, r1
800393a: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800393c: 687b ldr r3, [r7, #4]
800393e: 681b ldr r3, [r3, #0]
8003940: 681a ldr r2, [r3, #0]
8003942: 687b ldr r3, [r7, #4]
8003944: 681b ldr r3, [r3, #0]
8003946: f042 0201 orr.w r2, r2, #1
800394a: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800394c: 687b ldr r3, [r7, #4]
800394e: 2200 movs r2, #0
8003950: 641a str r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_READY;
8003952: 687b ldr r3, [r7, #4]
8003954: 2220 movs r2, #32
8003956: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
800395a: 687b ldr r3, [r7, #4]
800395c: 2200 movs r2, #0
800395e: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8003960: 687b ldr r3, [r7, #4]
8003962: 2200 movs r2, #0
8003964: f883 203e strb.w r2, [r3, #62] @ 0x3e
return HAL_OK;
8003968: 2300 movs r3, #0
}
800396a: 4618 mov r0, r3
800396c: 3710 adds r7, #16
800396e: 46bd mov sp, r7
8003970: bd80 pop {r7, pc}
8003972: bf00 nop
8003974: 000186a0 .word 0x000186a0
8003978: 001e847f .word 0x001e847f
800397c: 003d08ff .word 0x003d08ff
8003980: 431bde83 .word 0x431bde83
8003984: 10624dd3 .word 0x10624dd3
08003988 <HAL_I2C_Master_Transmit>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003988: b580 push {r7, lr}
800398a: b088 sub sp, #32
800398c: af02 add r7, sp, #8
800398e: 60f8 str r0, [r7, #12]
8003990: 607a str r2, [r7, #4]
8003992: 461a mov r2, r3
8003994: 460b mov r3, r1
8003996: 817b strh r3, [r7, #10]
8003998: 4613 mov r3, r2
800399a: 813b strh r3, [r7, #8]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
800399c: f7ff f8e4 bl 8002b68 <HAL_GetTick>
80039a0: 6178 str r0, [r7, #20]
if (hi2c->State == HAL_I2C_STATE_READY)
80039a2: 68fb ldr r3, [r7, #12]
80039a4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80039a8: b2db uxtb r3, r3
80039aa: 2b20 cmp r3, #32
80039ac: f040 80e0 bne.w 8003b70 <HAL_I2C_Master_Transmit+0x1e8>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
80039b0: 697b ldr r3, [r7, #20]
80039b2: 9300 str r3, [sp, #0]
80039b4: 2319 movs r3, #25
80039b6: 2201 movs r2, #1
80039b8: 4970 ldr r1, [pc, #448] @ (8003b7c <HAL_I2C_Master_Transmit+0x1f4>)
80039ba: 68f8 ldr r0, [r7, #12]
80039bc: f000 fc9e bl 80042fc <I2C_WaitOnFlagUntilTimeout>
80039c0: 4603 mov r3, r0
80039c2: 2b00 cmp r3, #0
80039c4: d001 beq.n 80039ca <HAL_I2C_Master_Transmit+0x42>
{
return HAL_BUSY;
80039c6: 2302 movs r3, #2
80039c8: e0d3 b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80039ca: 68fb ldr r3, [r7, #12]
80039cc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80039d0: 2b01 cmp r3, #1
80039d2: d101 bne.n 80039d8 <HAL_I2C_Master_Transmit+0x50>
80039d4: 2302 movs r3, #2
80039d6: e0cc b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
80039d8: 68fb ldr r3, [r7, #12]
80039da: 2201 movs r2, #1
80039dc: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
80039e0: 68fb ldr r3, [r7, #12]
80039e2: 681b ldr r3, [r3, #0]
80039e4: 681b ldr r3, [r3, #0]
80039e6: f003 0301 and.w r3, r3, #1
80039ea: 2b01 cmp r3, #1
80039ec: d007 beq.n 80039fe <HAL_I2C_Master_Transmit+0x76>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80039ee: 68fb ldr r3, [r7, #12]
80039f0: 681b ldr r3, [r3, #0]
80039f2: 681a ldr r2, [r3, #0]
80039f4: 68fb ldr r3, [r7, #12]
80039f6: 681b ldr r3, [r3, #0]
80039f8: f042 0201 orr.w r2, r2, #1
80039fc: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
80039fe: 68fb ldr r3, [r7, #12]
8003a00: 681b ldr r3, [r3, #0]
8003a02: 681a ldr r2, [r3, #0]
8003a04: 68fb ldr r3, [r7, #12]
8003a06: 681b ldr r3, [r3, #0]
8003a08: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003a0c: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8003a0e: 68fb ldr r3, [r7, #12]
8003a10: 2221 movs r2, #33 @ 0x21
8003a12: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8003a16: 68fb ldr r3, [r7, #12]
8003a18: 2210 movs r2, #16
8003a1a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003a1e: 68fb ldr r3, [r7, #12]
8003a20: 2200 movs r2, #0
8003a22: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8003a24: 68fb ldr r3, [r7, #12]
8003a26: 687a ldr r2, [r7, #4]
8003a28: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8003a2a: 68fb ldr r3, [r7, #12]
8003a2c: 893a ldrh r2, [r7, #8]
8003a2e: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8003a30: 68fb ldr r3, [r7, #12]
8003a32: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003a34: b29a uxth r2, r3
8003a36: 68fb ldr r3, [r7, #12]
8003a38: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8003a3a: 68fb ldr r3, [r7, #12]
8003a3c: 4a50 ldr r2, [pc, #320] @ (8003b80 <HAL_I2C_Master_Transmit+0x1f8>)
8003a3e: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
8003a40: 8979 ldrh r1, [r7, #10]
8003a42: 697b ldr r3, [r7, #20]
8003a44: 6a3a ldr r2, [r7, #32]
8003a46: 68f8 ldr r0, [r7, #12]
8003a48: f000 fb08 bl 800405c <I2C_MasterRequestWrite>
8003a4c: 4603 mov r3, r0
8003a4e: 2b00 cmp r3, #0
8003a50: d001 beq.n 8003a56 <HAL_I2C_Master_Transmit+0xce>
{
return HAL_ERROR;
8003a52: 2301 movs r3, #1
8003a54: e08d b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003a56: 2300 movs r3, #0
8003a58: 613b str r3, [r7, #16]
8003a5a: 68fb ldr r3, [r7, #12]
8003a5c: 681b ldr r3, [r3, #0]
8003a5e: 695b ldr r3, [r3, #20]
8003a60: 613b str r3, [r7, #16]
8003a62: 68fb ldr r3, [r7, #12]
8003a64: 681b ldr r3, [r3, #0]
8003a66: 699b ldr r3, [r3, #24]
8003a68: 613b str r3, [r7, #16]
8003a6a: 693b ldr r3, [r7, #16]
while (hi2c->XferSize > 0U)
8003a6c: e066 b.n 8003b3c <HAL_I2C_Master_Transmit+0x1b4>
{
/* Wait until TXE flag is set */
if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003a6e: 697a ldr r2, [r7, #20]
8003a70: 6a39 ldr r1, [r7, #32]
8003a72: 68f8 ldr r0, [r7, #12]
8003a74: f000 fd5c bl 8004530 <I2C_WaitOnTXEFlagUntilTimeout>
8003a78: 4603 mov r3, r0
8003a7a: 2b00 cmp r3, #0
8003a7c: d00d beq.n 8003a9a <HAL_I2C_Master_Transmit+0x112>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
8003a7e: 68fb ldr r3, [r7, #12]
8003a80: 6c1b ldr r3, [r3, #64] @ 0x40
8003a82: 2b04 cmp r3, #4
8003a84: d107 bne.n 8003a96 <HAL_I2C_Master_Transmit+0x10e>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003a86: 68fb ldr r3, [r7, #12]
8003a88: 681b ldr r3, [r3, #0]
8003a8a: 681a ldr r2, [r3, #0]
8003a8c: 68fb ldr r3, [r7, #12]
8003a8e: 681b ldr r3, [r3, #0]
8003a90: f442 7200 orr.w r2, r2, #512 @ 0x200
8003a94: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8003a96: 2301 movs r3, #1
8003a98: e06b b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003a9a: 68fb ldr r3, [r7, #12]
8003a9c: 6a5b ldr r3, [r3, #36] @ 0x24
8003a9e: 781a ldrb r2, [r3, #0]
8003aa0: 68fb ldr r3, [r7, #12]
8003aa2: 681b ldr r3, [r3, #0]
8003aa4: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003aa6: 68fb ldr r3, [r7, #12]
8003aa8: 6a5b ldr r3, [r3, #36] @ 0x24
8003aaa: 1c5a adds r2, r3, #1
8003aac: 68fb ldr r3, [r7, #12]
8003aae: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003ab0: 68fb ldr r3, [r7, #12]
8003ab2: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003ab4: b29b uxth r3, r3
8003ab6: 3b01 subs r3, #1
8003ab8: b29a uxth r2, r3
8003aba: 68fb ldr r3, [r7, #12]
8003abc: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8003abe: 68fb ldr r3, [r7, #12]
8003ac0: 8d1b ldrh r3, [r3, #40] @ 0x28
8003ac2: 3b01 subs r3, #1
8003ac4: b29a uxth r2, r3
8003ac6: 68fb ldr r3, [r7, #12]
8003ac8: 851a strh r2, [r3, #40] @ 0x28
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
8003aca: 68fb ldr r3, [r7, #12]
8003acc: 681b ldr r3, [r3, #0]
8003ace: 695b ldr r3, [r3, #20]
8003ad0: f003 0304 and.w r3, r3, #4
8003ad4: 2b04 cmp r3, #4
8003ad6: d11b bne.n 8003b10 <HAL_I2C_Master_Transmit+0x188>
8003ad8: 68fb ldr r3, [r7, #12]
8003ada: 8d1b ldrh r3, [r3, #40] @ 0x28
8003adc: 2b00 cmp r3, #0
8003ade: d017 beq.n 8003b10 <HAL_I2C_Master_Transmit+0x188>
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8003ae0: 68fb ldr r3, [r7, #12]
8003ae2: 6a5b ldr r3, [r3, #36] @ 0x24
8003ae4: 781a ldrb r2, [r3, #0]
8003ae6: 68fb ldr r3, [r7, #12]
8003ae8: 681b ldr r3, [r3, #0]
8003aea: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003aec: 68fb ldr r3, [r7, #12]
8003aee: 6a5b ldr r3, [r3, #36] @ 0x24
8003af0: 1c5a adds r2, r3, #1
8003af2: 68fb ldr r3, [r7, #12]
8003af4: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8003af6: 68fb ldr r3, [r7, #12]
8003af8: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003afa: b29b uxth r3, r3
8003afc: 3b01 subs r3, #1
8003afe: b29a uxth r2, r3
8003b00: 68fb ldr r3, [r7, #12]
8003b02: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8003b04: 68fb ldr r3, [r7, #12]
8003b06: 8d1b ldrh r3, [r3, #40] @ 0x28
8003b08: 3b01 subs r3, #1
8003b0a: b29a uxth r2, r3
8003b0c: 68fb ldr r3, [r7, #12]
8003b0e: 851a strh r2, [r3, #40] @ 0x28
}
/* Wait until BTF flag is set */
if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003b10: 697a ldr r2, [r7, #20]
8003b12: 6a39 ldr r1, [r7, #32]
8003b14: 68f8 ldr r0, [r7, #12]
8003b16: f000 fd53 bl 80045c0 <I2C_WaitOnBTFFlagUntilTimeout>
8003b1a: 4603 mov r3, r0
8003b1c: 2b00 cmp r3, #0
8003b1e: d00d beq.n 8003b3c <HAL_I2C_Master_Transmit+0x1b4>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
8003b20: 68fb ldr r3, [r7, #12]
8003b22: 6c1b ldr r3, [r3, #64] @ 0x40
8003b24: 2b04 cmp r3, #4
8003b26: d107 bne.n 8003b38 <HAL_I2C_Master_Transmit+0x1b0>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003b28: 68fb ldr r3, [r7, #12]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: 681a ldr r2, [r3, #0]
8003b2e: 68fb ldr r3, [r7, #12]
8003b30: 681b ldr r3, [r3, #0]
8003b32: f442 7200 orr.w r2, r2, #512 @ 0x200
8003b36: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8003b38: 2301 movs r3, #1
8003b3a: e01a b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
while (hi2c->XferSize > 0U)
8003b3c: 68fb ldr r3, [r7, #12]
8003b3e: 8d1b ldrh r3, [r3, #40] @ 0x28
8003b40: 2b00 cmp r3, #0
8003b42: d194 bne.n 8003a6e <HAL_I2C_Master_Transmit+0xe6>
}
}
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003b44: 68fb ldr r3, [r7, #12]
8003b46: 681b ldr r3, [r3, #0]
8003b48: 681a ldr r2, [r3, #0]
8003b4a: 68fb ldr r3, [r7, #12]
8003b4c: 681b ldr r3, [r3, #0]
8003b4e: f442 7200 orr.w r2, r2, #512 @ 0x200
8003b52: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003b54: 68fb ldr r3, [r7, #12]
8003b56: 2220 movs r2, #32
8003b58: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8003b5c: 68fb ldr r3, [r7, #12]
8003b5e: 2200 movs r2, #0
8003b60: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8003b64: 68fb ldr r3, [r7, #12]
8003b66: 2200 movs r2, #0
8003b68: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8003b6c: 2300 movs r3, #0
8003b6e: e000 b.n 8003b72 <HAL_I2C_Master_Transmit+0x1ea>
}
else
{
return HAL_BUSY;
8003b70: 2302 movs r3, #2
}
}
8003b72: 4618 mov r0, r3
8003b74: 3718 adds r7, #24
8003b76: 46bd mov sp, r7
8003b78: bd80 pop {r7, pc}
8003b7a: bf00 nop
8003b7c: 00100002 .word 0x00100002
8003b80: ffff0000 .word 0xffff0000
08003b84 <HAL_I2C_Master_Receive>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003b84: b580 push {r7, lr}
8003b86: b08c sub sp, #48 @ 0x30
8003b88: af02 add r7, sp, #8
8003b8a: 60f8 str r0, [r7, #12]
8003b8c: 607a str r2, [r7, #4]
8003b8e: 461a mov r2, r3
8003b90: 460b mov r3, r1
8003b92: 817b strh r3, [r7, #10]
8003b94: 4613 mov r3, r2
8003b96: 813b strh r3, [r7, #8]
__IO uint32_t count = 0U;
8003b98: 2300 movs r3, #0
8003b9a: 623b str r3, [r7, #32]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
8003b9c: f7fe ffe4 bl 8002b68 <HAL_GetTick>
8003ba0: 6278 str r0, [r7, #36] @ 0x24
if (hi2c->State == HAL_I2C_STATE_READY)
8003ba2: 68fb ldr r3, [r7, #12]
8003ba4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003ba8: b2db uxtb r3, r3
8003baa: 2b20 cmp r3, #32
8003bac: f040 824b bne.w 8004046 <HAL_I2C_Master_Receive+0x4c2>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
8003bb0: 6a7b ldr r3, [r7, #36] @ 0x24
8003bb2: 9300 str r3, [sp, #0]
8003bb4: 2319 movs r3, #25
8003bb6: 2201 movs r2, #1
8003bb8: 497f ldr r1, [pc, #508] @ (8003db8 <HAL_I2C_Master_Receive+0x234>)
8003bba: 68f8 ldr r0, [r7, #12]
8003bbc: f000 fb9e bl 80042fc <I2C_WaitOnFlagUntilTimeout>
8003bc0: 4603 mov r3, r0
8003bc2: 2b00 cmp r3, #0
8003bc4: d001 beq.n 8003bca <HAL_I2C_Master_Receive+0x46>
{
return HAL_BUSY;
8003bc6: 2302 movs r3, #2
8003bc8: e23e b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8003bca: 68fb ldr r3, [r7, #12]
8003bcc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8003bd0: 2b01 cmp r3, #1
8003bd2: d101 bne.n 8003bd8 <HAL_I2C_Master_Receive+0x54>
8003bd4: 2302 movs r3, #2
8003bd6: e237 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
8003bd8: 68fb ldr r3, [r7, #12]
8003bda: 2201 movs r2, #1
8003bdc: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
8003be0: 68fb ldr r3, [r7, #12]
8003be2: 681b ldr r3, [r3, #0]
8003be4: 681b ldr r3, [r3, #0]
8003be6: f003 0301 and.w r3, r3, #1
8003bea: 2b01 cmp r3, #1
8003bec: d007 beq.n 8003bfe <HAL_I2C_Master_Receive+0x7a>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003bee: 68fb ldr r3, [r7, #12]
8003bf0: 681b ldr r3, [r3, #0]
8003bf2: 681a ldr r2, [r3, #0]
8003bf4: 68fb ldr r3, [r7, #12]
8003bf6: 681b ldr r3, [r3, #0]
8003bf8: f042 0201 orr.w r2, r2, #1
8003bfc: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8003bfe: 68fb ldr r3, [r7, #12]
8003c00: 681b ldr r3, [r3, #0]
8003c02: 681a ldr r2, [r3, #0]
8003c04: 68fb ldr r3, [r7, #12]
8003c06: 681b ldr r3, [r3, #0]
8003c08: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003c0c: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_RX;
8003c0e: 68fb ldr r3, [r7, #12]
8003c10: 2222 movs r2, #34 @ 0x22
8003c12: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8003c16: 68fb ldr r3, [r7, #12]
8003c18: 2210 movs r2, #16
8003c1a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003c1e: 68fb ldr r3, [r7, #12]
8003c20: 2200 movs r2, #0
8003c22: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8003c24: 68fb ldr r3, [r7, #12]
8003c26: 687a ldr r2, [r7, #4]
8003c28: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8003c2a: 68fb ldr r3, [r7, #12]
8003c2c: 893a ldrh r2, [r7, #8]
8003c2e: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8003c30: 68fb ldr r3, [r7, #12]
8003c32: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003c34: b29a uxth r2, r3
8003c36: 68fb ldr r3, [r7, #12]
8003c38: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8003c3a: 68fb ldr r3, [r7, #12]
8003c3c: 4a5f ldr r2, [pc, #380] @ (8003dbc <HAL_I2C_Master_Receive+0x238>)
8003c3e: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
8003c40: 8979 ldrh r1, [r7, #10]
8003c42: 6a7b ldr r3, [r7, #36] @ 0x24
8003c44: 6b3a ldr r2, [r7, #48] @ 0x30
8003c46: 68f8 ldr r0, [r7, #12]
8003c48: f000 fa8a bl 8004160 <I2C_MasterRequestRead>
8003c4c: 4603 mov r3, r0
8003c4e: 2b00 cmp r3, #0
8003c50: d001 beq.n 8003c56 <HAL_I2C_Master_Receive+0xd2>
{
return HAL_ERROR;
8003c52: 2301 movs r3, #1
8003c54: e1f8 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
if (hi2c->XferSize == 0U)
8003c56: 68fb ldr r3, [r7, #12]
8003c58: 8d1b ldrh r3, [r3, #40] @ 0x28
8003c5a: 2b00 cmp r3, #0
8003c5c: d113 bne.n 8003c86 <HAL_I2C_Master_Receive+0x102>
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003c5e: 2300 movs r3, #0
8003c60: 61fb str r3, [r7, #28]
8003c62: 68fb ldr r3, [r7, #12]
8003c64: 681b ldr r3, [r3, #0]
8003c66: 695b ldr r3, [r3, #20]
8003c68: 61fb str r3, [r7, #28]
8003c6a: 68fb ldr r3, [r7, #12]
8003c6c: 681b ldr r3, [r3, #0]
8003c6e: 699b ldr r3, [r3, #24]
8003c70: 61fb str r3, [r7, #28]
8003c72: 69fb ldr r3, [r7, #28]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003c74: 68fb ldr r3, [r7, #12]
8003c76: 681b ldr r3, [r3, #0]
8003c78: 681a ldr r2, [r3, #0]
8003c7a: 68fb ldr r3, [r7, #12]
8003c7c: 681b ldr r3, [r3, #0]
8003c7e: f442 7200 orr.w r2, r2, #512 @ 0x200
8003c82: 601a str r2, [r3, #0]
8003c84: e1cc b.n 8004020 <HAL_I2C_Master_Receive+0x49c>
}
else if (hi2c->XferSize == 1U)
8003c86: 68fb ldr r3, [r7, #12]
8003c88: 8d1b ldrh r3, [r3, #40] @ 0x28
8003c8a: 2b01 cmp r3, #1
8003c8c: d11e bne.n 8003ccc <HAL_I2C_Master_Receive+0x148>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8003c8e: 68fb ldr r3, [r7, #12]
8003c90: 681b ldr r3, [r3, #0]
8003c92: 681a ldr r2, [r3, #0]
8003c94: 68fb ldr r3, [r7, #12]
8003c96: 681b ldr r3, [r3, #0]
8003c98: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003c9c: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8003c9e: b672 cpsid i
}
8003ca0: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003ca2: 2300 movs r3, #0
8003ca4: 61bb str r3, [r7, #24]
8003ca6: 68fb ldr r3, [r7, #12]
8003ca8: 681b ldr r3, [r3, #0]
8003caa: 695b ldr r3, [r3, #20]
8003cac: 61bb str r3, [r7, #24]
8003cae: 68fb ldr r3, [r7, #12]
8003cb0: 681b ldr r3, [r3, #0]
8003cb2: 699b ldr r3, [r3, #24]
8003cb4: 61bb str r3, [r7, #24]
8003cb6: 69bb ldr r3, [r7, #24]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003cb8: 68fb ldr r3, [r7, #12]
8003cba: 681b ldr r3, [r3, #0]
8003cbc: 681a ldr r2, [r3, #0]
8003cbe: 68fb ldr r3, [r7, #12]
8003cc0: 681b ldr r3, [r3, #0]
8003cc2: f442 7200 orr.w r2, r2, #512 @ 0x200
8003cc6: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
8003cc8: b662 cpsie i
}
8003cca: e035 b.n 8003d38 <HAL_I2C_Master_Receive+0x1b4>
/* Re-enable IRQs */
__enable_irq();
}
else if (hi2c->XferSize == 2U)
8003ccc: 68fb ldr r3, [r7, #12]
8003cce: 8d1b ldrh r3, [r3, #40] @ 0x28
8003cd0: 2b02 cmp r3, #2
8003cd2: d11e bne.n 8003d12 <HAL_I2C_Master_Receive+0x18e>
{
/* Enable Pos */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8003cd4: 68fb ldr r3, [r7, #12]
8003cd6: 681b ldr r3, [r3, #0]
8003cd8: 681a ldr r2, [r3, #0]
8003cda: 68fb ldr r3, [r7, #12]
8003cdc: 681b ldr r3, [r3, #0]
8003cde: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003ce2: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8003ce4: b672 cpsid i
}
8003ce6: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003ce8: 2300 movs r3, #0
8003cea: 617b str r3, [r7, #20]
8003cec: 68fb ldr r3, [r7, #12]
8003cee: 681b ldr r3, [r3, #0]
8003cf0: 695b ldr r3, [r3, #20]
8003cf2: 617b str r3, [r7, #20]
8003cf4: 68fb ldr r3, [r7, #12]
8003cf6: 681b ldr r3, [r3, #0]
8003cf8: 699b ldr r3, [r3, #24]
8003cfa: 617b str r3, [r7, #20]
8003cfc: 697b ldr r3, [r7, #20]
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8003cfe: 68fb ldr r3, [r7, #12]
8003d00: 681b ldr r3, [r3, #0]
8003d02: 681a ldr r2, [r3, #0]
8003d04: 68fb ldr r3, [r7, #12]
8003d06: 681b ldr r3, [r3, #0]
8003d08: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003d0c: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
8003d0e: b662 cpsie i
}
8003d10: e012 b.n 8003d38 <HAL_I2C_Master_Receive+0x1b4>
__enable_irq();
}
else
{
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8003d12: 68fb ldr r3, [r7, #12]
8003d14: 681b ldr r3, [r3, #0]
8003d16: 681a ldr r2, [r3, #0]
8003d18: 68fb ldr r3, [r7, #12]
8003d1a: 681b ldr r3, [r3, #0]
8003d1c: f442 6280 orr.w r2, r2, #1024 @ 0x400
8003d20: 601a str r2, [r3, #0]
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8003d22: 2300 movs r3, #0
8003d24: 613b str r3, [r7, #16]
8003d26: 68fb ldr r3, [r7, #12]
8003d28: 681b ldr r3, [r3, #0]
8003d2a: 695b ldr r3, [r3, #20]
8003d2c: 613b str r3, [r7, #16]
8003d2e: 68fb ldr r3, [r7, #12]
8003d30: 681b ldr r3, [r3, #0]
8003d32: 699b ldr r3, [r3, #24]
8003d34: 613b str r3, [r7, #16]
8003d36: 693b ldr r3, [r7, #16]
}
while (hi2c->XferSize > 0U)
8003d38: e172 b.n 8004020 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize <= 3U)
8003d3a: 68fb ldr r3, [r7, #12]
8003d3c: 8d1b ldrh r3, [r3, #40] @ 0x28
8003d3e: 2b03 cmp r3, #3
8003d40: f200 811f bhi.w 8003f82 <HAL_I2C_Master_Receive+0x3fe>
{
/* One byte */
if (hi2c->XferSize == 1U)
8003d44: 68fb ldr r3, [r7, #12]
8003d46: 8d1b ldrh r3, [r3, #40] @ 0x28
8003d48: 2b01 cmp r3, #1
8003d4a: d123 bne.n 8003d94 <HAL_I2C_Master_Receive+0x210>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003d4c: 6a7a ldr r2, [r7, #36] @ 0x24
8003d4e: 6b39 ldr r1, [r7, #48] @ 0x30
8003d50: 68f8 ldr r0, [r7, #12]
8003d52: f000 fc7d bl 8004650 <I2C_WaitOnRXNEFlagUntilTimeout>
8003d56: 4603 mov r3, r0
8003d58: 2b00 cmp r3, #0
8003d5a: d001 beq.n 8003d60 <HAL_I2C_Master_Receive+0x1dc>
{
return HAL_ERROR;
8003d5c: 2301 movs r3, #1
8003d5e: e173 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003d60: 68fb ldr r3, [r7, #12]
8003d62: 681b ldr r3, [r3, #0]
8003d64: 691a ldr r2, [r3, #16]
8003d66: 68fb ldr r3, [r7, #12]
8003d68: 6a5b ldr r3, [r3, #36] @ 0x24
8003d6a: b2d2 uxtb r2, r2
8003d6c: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003d6e: 68fb ldr r3, [r7, #12]
8003d70: 6a5b ldr r3, [r3, #36] @ 0x24
8003d72: 1c5a adds r2, r3, #1
8003d74: 68fb ldr r3, [r7, #12]
8003d76: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003d78: 68fb ldr r3, [r7, #12]
8003d7a: 8d1b ldrh r3, [r3, #40] @ 0x28
8003d7c: 3b01 subs r3, #1
8003d7e: b29a uxth r2, r3
8003d80: 68fb ldr r3, [r7, #12]
8003d82: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003d84: 68fb ldr r3, [r7, #12]
8003d86: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003d88: b29b uxth r3, r3
8003d8a: 3b01 subs r3, #1
8003d8c: b29a uxth r2, r3
8003d8e: 68fb ldr r3, [r7, #12]
8003d90: 855a strh r2, [r3, #42] @ 0x2a
8003d92: e145 b.n 8004020 <HAL_I2C_Master_Receive+0x49c>
}
/* Two bytes */
else if (hi2c->XferSize == 2U)
8003d94: 68fb ldr r3, [r7, #12]
8003d96: 8d1b ldrh r3, [r3, #40] @ 0x28
8003d98: 2b02 cmp r3, #2
8003d9a: d152 bne.n 8003e42 <HAL_I2C_Master_Receive+0x2be>
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
8003d9c: 6a7b ldr r3, [r7, #36] @ 0x24
8003d9e: 9300 str r3, [sp, #0]
8003da0: 6b3b ldr r3, [r7, #48] @ 0x30
8003da2: 2200 movs r2, #0
8003da4: 4906 ldr r1, [pc, #24] @ (8003dc0 <HAL_I2C_Master_Receive+0x23c>)
8003da6: 68f8 ldr r0, [r7, #12]
8003da8: f000 faa8 bl 80042fc <I2C_WaitOnFlagUntilTimeout>
8003dac: 4603 mov r3, r0
8003dae: 2b00 cmp r3, #0
8003db0: d008 beq.n 8003dc4 <HAL_I2C_Master_Receive+0x240>
{
return HAL_ERROR;
8003db2: 2301 movs r3, #1
8003db4: e148 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
8003db6: bf00 nop
8003db8: 00100002 .word 0x00100002
8003dbc: ffff0000 .word 0xffff0000
8003dc0: 00010004 .word 0x00010004
__ASM volatile ("cpsid i" : : : "memory");
8003dc4: b672 cpsid i
}
8003dc6: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003dc8: 68fb ldr r3, [r7, #12]
8003dca: 681b ldr r3, [r3, #0]
8003dcc: 681a ldr r2, [r3, #0]
8003dce: 68fb ldr r3, [r7, #12]
8003dd0: 681b ldr r3, [r3, #0]
8003dd2: f442 7200 orr.w r2, r2, #512 @ 0x200
8003dd6: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003dd8: 68fb ldr r3, [r7, #12]
8003dda: 681b ldr r3, [r3, #0]
8003ddc: 691a ldr r2, [r3, #16]
8003dde: 68fb ldr r3, [r7, #12]
8003de0: 6a5b ldr r3, [r3, #36] @ 0x24
8003de2: b2d2 uxtb r2, r2
8003de4: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003de6: 68fb ldr r3, [r7, #12]
8003de8: 6a5b ldr r3, [r3, #36] @ 0x24
8003dea: 1c5a adds r2, r3, #1
8003dec: 68fb ldr r3, [r7, #12]
8003dee: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003df0: 68fb ldr r3, [r7, #12]
8003df2: 8d1b ldrh r3, [r3, #40] @ 0x28
8003df4: 3b01 subs r3, #1
8003df6: b29a uxth r2, r3
8003df8: 68fb ldr r3, [r7, #12]
8003dfa: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003dfc: 68fb ldr r3, [r7, #12]
8003dfe: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003e00: b29b uxth r3, r3
8003e02: 3b01 subs r3, #1
8003e04: b29a uxth r2, r3
8003e06: 68fb ldr r3, [r7, #12]
8003e08: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
8003e0a: b662 cpsie i
}
8003e0c: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003e0e: 68fb ldr r3, [r7, #12]
8003e10: 681b ldr r3, [r3, #0]
8003e12: 691a ldr r2, [r3, #16]
8003e14: 68fb ldr r3, [r7, #12]
8003e16: 6a5b ldr r3, [r3, #36] @ 0x24
8003e18: b2d2 uxtb r2, r2
8003e1a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003e1c: 68fb ldr r3, [r7, #12]
8003e1e: 6a5b ldr r3, [r3, #36] @ 0x24
8003e20: 1c5a adds r2, r3, #1
8003e22: 68fb ldr r3, [r7, #12]
8003e24: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003e26: 68fb ldr r3, [r7, #12]
8003e28: 8d1b ldrh r3, [r3, #40] @ 0x28
8003e2a: 3b01 subs r3, #1
8003e2c: b29a uxth r2, r3
8003e2e: 68fb ldr r3, [r7, #12]
8003e30: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003e32: 68fb ldr r3, [r7, #12]
8003e34: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003e36: b29b uxth r3, r3
8003e38: 3b01 subs r3, #1
8003e3a: b29a uxth r2, r3
8003e3c: 68fb ldr r3, [r7, #12]
8003e3e: 855a strh r2, [r3, #42] @ 0x2a
8003e40: e0ee b.n 8004020 <HAL_I2C_Master_Receive+0x49c>
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
8003e42: 6a7b ldr r3, [r7, #36] @ 0x24
8003e44: 9300 str r3, [sp, #0]
8003e46: 6b3b ldr r3, [r7, #48] @ 0x30
8003e48: 2200 movs r2, #0
8003e4a: 4981 ldr r1, [pc, #516] @ (8004050 <HAL_I2C_Master_Receive+0x4cc>)
8003e4c: 68f8 ldr r0, [r7, #12]
8003e4e: f000 fa55 bl 80042fc <I2C_WaitOnFlagUntilTimeout>
8003e52: 4603 mov r3, r0
8003e54: 2b00 cmp r3, #0
8003e56: d001 beq.n 8003e5c <HAL_I2C_Master_Receive+0x2d8>
{
return HAL_ERROR;
8003e58: 2301 movs r3, #1
8003e5a: e0f5 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8003e5c: 68fb ldr r3, [r7, #12]
8003e5e: 681b ldr r3, [r3, #0]
8003e60: 681a ldr r2, [r3, #0]
8003e62: 68fb ldr r3, [r7, #12]
8003e64: 681b ldr r3, [r3, #0]
8003e66: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003e6a: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8003e6c: b672 cpsid i
}
8003e6e: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003e70: 68fb ldr r3, [r7, #12]
8003e72: 681b ldr r3, [r3, #0]
8003e74: 691a ldr r2, [r3, #16]
8003e76: 68fb ldr r3, [r7, #12]
8003e78: 6a5b ldr r3, [r3, #36] @ 0x24
8003e7a: b2d2 uxtb r2, r2
8003e7c: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003e7e: 68fb ldr r3, [r7, #12]
8003e80: 6a5b ldr r3, [r3, #36] @ 0x24
8003e82: 1c5a adds r2, r3, #1
8003e84: 68fb ldr r3, [r7, #12]
8003e86: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003e88: 68fb ldr r3, [r7, #12]
8003e8a: 8d1b ldrh r3, [r3, #40] @ 0x28
8003e8c: 3b01 subs r3, #1
8003e8e: b29a uxth r2, r3
8003e90: 68fb ldr r3, [r7, #12]
8003e92: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003e94: 68fb ldr r3, [r7, #12]
8003e96: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003e98: b29b uxth r3, r3
8003e9a: 3b01 subs r3, #1
8003e9c: b29a uxth r2, r3
8003e9e: 68fb ldr r3, [r7, #12]
8003ea0: 855a strh r2, [r3, #42] @ 0x2a
/* Wait until BTF flag is set */
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
8003ea2: 4b6c ldr r3, [pc, #432] @ (8004054 <HAL_I2C_Master_Receive+0x4d0>)
8003ea4: 681b ldr r3, [r3, #0]
8003ea6: 08db lsrs r3, r3, #3
8003ea8: 4a6b ldr r2, [pc, #428] @ (8004058 <HAL_I2C_Master_Receive+0x4d4>)
8003eaa: fba2 2303 umull r2, r3, r2, r3
8003eae: 0a1a lsrs r2, r3, #8
8003eb0: 4613 mov r3, r2
8003eb2: 009b lsls r3, r3, #2
8003eb4: 4413 add r3, r2
8003eb6: 00da lsls r2, r3, #3
8003eb8: 1ad3 subs r3, r2, r3
8003eba: 623b str r3, [r7, #32]
do
{
count--;
8003ebc: 6a3b ldr r3, [r7, #32]
8003ebe: 3b01 subs r3, #1
8003ec0: 623b str r3, [r7, #32]
if (count == 0U)
8003ec2: 6a3b ldr r3, [r7, #32]
8003ec4: 2b00 cmp r3, #0
8003ec6: d118 bne.n 8003efa <HAL_I2C_Master_Receive+0x376>
{
hi2c->PreviousState = I2C_STATE_NONE;
8003ec8: 68fb ldr r3, [r7, #12]
8003eca: 2200 movs r2, #0
8003ecc: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8003ece: 68fb ldr r3, [r7, #12]
8003ed0: 2220 movs r2, #32
8003ed2: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8003ed6: 68fb ldr r3, [r7, #12]
8003ed8: 2200 movs r2, #0
8003eda: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8003ede: 68fb ldr r3, [r7, #12]
8003ee0: 6c1b ldr r3, [r3, #64] @ 0x40
8003ee2: f043 0220 orr.w r2, r3, #32
8003ee6: 68fb ldr r3, [r7, #12]
8003ee8: 641a str r2, [r3, #64] @ 0x40
__ASM volatile ("cpsie i" : : : "memory");
8003eea: b662 cpsie i
}
8003eec: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8003eee: 68fb ldr r3, [r7, #12]
8003ef0: 2200 movs r2, #0
8003ef2: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8003ef6: 2301 movs r3, #1
8003ef8: e0a6 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
8003efa: 68fb ldr r3, [r7, #12]
8003efc: 681b ldr r3, [r3, #0]
8003efe: 695b ldr r3, [r3, #20]
8003f00: f003 0304 and.w r3, r3, #4
8003f04: 2b04 cmp r3, #4
8003f06: d1d9 bne.n 8003ebc <HAL_I2C_Master_Receive+0x338>
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8003f08: 68fb ldr r3, [r7, #12]
8003f0a: 681b ldr r3, [r3, #0]
8003f0c: 681a ldr r2, [r3, #0]
8003f0e: 68fb ldr r3, [r7, #12]
8003f10: 681b ldr r3, [r3, #0]
8003f12: f442 7200 orr.w r2, r2, #512 @ 0x200
8003f16: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003f18: 68fb ldr r3, [r7, #12]
8003f1a: 681b ldr r3, [r3, #0]
8003f1c: 691a ldr r2, [r3, #16]
8003f1e: 68fb ldr r3, [r7, #12]
8003f20: 6a5b ldr r3, [r3, #36] @ 0x24
8003f22: b2d2 uxtb r2, r2
8003f24: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003f26: 68fb ldr r3, [r7, #12]
8003f28: 6a5b ldr r3, [r3, #36] @ 0x24
8003f2a: 1c5a adds r2, r3, #1
8003f2c: 68fb ldr r3, [r7, #12]
8003f2e: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003f30: 68fb ldr r3, [r7, #12]
8003f32: 8d1b ldrh r3, [r3, #40] @ 0x28
8003f34: 3b01 subs r3, #1
8003f36: b29a uxth r2, r3
8003f38: 68fb ldr r3, [r7, #12]
8003f3a: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003f3c: 68fb ldr r3, [r7, #12]
8003f3e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003f40: b29b uxth r3, r3
8003f42: 3b01 subs r3, #1
8003f44: b29a uxth r2, r3
8003f46: 68fb ldr r3, [r7, #12]
8003f48: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
8003f4a: b662 cpsie i
}
8003f4c: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003f4e: 68fb ldr r3, [r7, #12]
8003f50: 681b ldr r3, [r3, #0]
8003f52: 691a ldr r2, [r3, #16]
8003f54: 68fb ldr r3, [r7, #12]
8003f56: 6a5b ldr r3, [r3, #36] @ 0x24
8003f58: b2d2 uxtb r2, r2
8003f5a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003f5c: 68fb ldr r3, [r7, #12]
8003f5e: 6a5b ldr r3, [r3, #36] @ 0x24
8003f60: 1c5a adds r2, r3, #1
8003f62: 68fb ldr r3, [r7, #12]
8003f64: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003f66: 68fb ldr r3, [r7, #12]
8003f68: 8d1b ldrh r3, [r3, #40] @ 0x28
8003f6a: 3b01 subs r3, #1
8003f6c: b29a uxth r2, r3
8003f6e: 68fb ldr r3, [r7, #12]
8003f70: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003f72: 68fb ldr r3, [r7, #12]
8003f74: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003f76: b29b uxth r3, r3
8003f78: 3b01 subs r3, #1
8003f7a: b29a uxth r2, r3
8003f7c: 68fb ldr r3, [r7, #12]
8003f7e: 855a strh r2, [r3, #42] @ 0x2a
8003f80: e04e b.n 8004020 <HAL_I2C_Master_Receive+0x49c>
}
}
else
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8003f82: 6a7a ldr r2, [r7, #36] @ 0x24
8003f84: 6b39 ldr r1, [r7, #48] @ 0x30
8003f86: 68f8 ldr r0, [r7, #12]
8003f88: f000 fb62 bl 8004650 <I2C_WaitOnRXNEFlagUntilTimeout>
8003f8c: 4603 mov r3, r0
8003f8e: 2b00 cmp r3, #0
8003f90: d001 beq.n 8003f96 <HAL_I2C_Master_Receive+0x412>
{
return HAL_ERROR;
8003f92: 2301 movs r3, #1
8003f94: e058 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003f96: 68fb ldr r3, [r7, #12]
8003f98: 681b ldr r3, [r3, #0]
8003f9a: 691a ldr r2, [r3, #16]
8003f9c: 68fb ldr r3, [r7, #12]
8003f9e: 6a5b ldr r3, [r3, #36] @ 0x24
8003fa0: b2d2 uxtb r2, r2
8003fa2: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003fa4: 68fb ldr r3, [r7, #12]
8003fa6: 6a5b ldr r3, [r3, #36] @ 0x24
8003fa8: 1c5a adds r2, r3, #1
8003faa: 68fb ldr r3, [r7, #12]
8003fac: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8003fae: 68fb ldr r3, [r7, #12]
8003fb0: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fb2: 3b01 subs r3, #1
8003fb4: b29a uxth r2, r3
8003fb6: 68fb ldr r3, [r7, #12]
8003fb8: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8003fba: 68fb ldr r3, [r7, #12]
8003fbc: 8d5b ldrh r3, [r3, #42] @ 0x2a
8003fbe: b29b uxth r3, r3
8003fc0: 3b01 subs r3, #1
8003fc2: b29a uxth r2, r3
8003fc4: 68fb ldr r3, [r7, #12]
8003fc6: 855a strh r2, [r3, #42] @ 0x2a
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
8003fc8: 68fb ldr r3, [r7, #12]
8003fca: 681b ldr r3, [r3, #0]
8003fcc: 695b ldr r3, [r3, #20]
8003fce: f003 0304 and.w r3, r3, #4
8003fd2: 2b04 cmp r3, #4
8003fd4: d124 bne.n 8004020 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize == 3U)
8003fd6: 68fb ldr r3, [r7, #12]
8003fd8: 8d1b ldrh r3, [r3, #40] @ 0x28
8003fda: 2b03 cmp r3, #3
8003fdc: d107 bne.n 8003fee <HAL_I2C_Master_Receive+0x46a>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8003fde: 68fb ldr r3, [r7, #12]
8003fe0: 681b ldr r3, [r3, #0]
8003fe2: 681a ldr r2, [r3, #0]
8003fe4: 68fb ldr r3, [r7, #12]
8003fe6: 681b ldr r3, [r3, #0]
8003fe8: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003fec: 601a str r2, [r3, #0]
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8003fee: 68fb ldr r3, [r7, #12]
8003ff0: 681b ldr r3, [r3, #0]
8003ff2: 691a ldr r2, [r3, #16]
8003ff4: 68fb ldr r3, [r7, #12]
8003ff6: 6a5b ldr r3, [r3, #36] @ 0x24
8003ff8: b2d2 uxtb r2, r2
8003ffa: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8003ffc: 68fb ldr r3, [r7, #12]
8003ffe: 6a5b ldr r3, [r3, #36] @ 0x24
8004000: 1c5a adds r2, r3, #1
8004002: 68fb ldr r3, [r7, #12]
8004004: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004006: 68fb ldr r3, [r7, #12]
8004008: 8d1b ldrh r3, [r3, #40] @ 0x28
800400a: 3b01 subs r3, #1
800400c: b29a uxth r2, r3
800400e: 68fb ldr r3, [r7, #12]
8004010: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004012: 68fb ldr r3, [r7, #12]
8004014: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004016: b29b uxth r3, r3
8004018: 3b01 subs r3, #1
800401a: b29a uxth r2, r3
800401c: 68fb ldr r3, [r7, #12]
800401e: 855a strh r2, [r3, #42] @ 0x2a
while (hi2c->XferSize > 0U)
8004020: 68fb ldr r3, [r7, #12]
8004022: 8d1b ldrh r3, [r3, #40] @ 0x28
8004024: 2b00 cmp r3, #0
8004026: f47f ae88 bne.w 8003d3a <HAL_I2C_Master_Receive+0x1b6>
}
}
}
hi2c->State = HAL_I2C_STATE_READY;
800402a: 68fb ldr r3, [r7, #12]
800402c: 2220 movs r2, #32
800402e: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004032: 68fb ldr r3, [r7, #12]
8004034: 2200 movs r2, #0
8004036: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800403a: 68fb ldr r3, [r7, #12]
800403c: 2200 movs r2, #0
800403e: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8004042: 2300 movs r3, #0
8004044: e000 b.n 8004048 <HAL_I2C_Master_Receive+0x4c4>
}
else
{
return HAL_BUSY;
8004046: 2302 movs r3, #2
}
}
8004048: 4618 mov r0, r3
800404a: 3728 adds r7, #40 @ 0x28
800404c: 46bd mov sp, r7
800404e: bd80 pop {r7, pc}
8004050: 00010004 .word 0x00010004
8004054: 20000038 .word 0x20000038
8004058: 14f8b589 .word 0x14f8b589
0800405c <I2C_MasterRequestWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
800405c: b580 push {r7, lr}
800405e: b088 sub sp, #32
8004060: af02 add r7, sp, #8
8004062: 60f8 str r0, [r7, #12]
8004064: 607a str r2, [r7, #4]
8004066: 603b str r3, [r7, #0]
8004068: 460b mov r3, r1
800406a: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
800406c: 68fb ldr r3, [r7, #12]
800406e: 6adb ldr r3, [r3, #44] @ 0x2c
8004070: 617b str r3, [r7, #20]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
8004072: 697b ldr r3, [r7, #20]
8004074: 2b08 cmp r3, #8
8004076: d006 beq.n 8004086 <I2C_MasterRequestWrite+0x2a>
8004078: 697b ldr r3, [r7, #20]
800407a: 2b01 cmp r3, #1
800407c: d003 beq.n 8004086 <I2C_MasterRequestWrite+0x2a>
800407e: 697b ldr r3, [r7, #20]
8004080: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004084: d108 bne.n 8004098 <I2C_MasterRequestWrite+0x3c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004086: 68fb ldr r3, [r7, #12]
8004088: 681b ldr r3, [r3, #0]
800408a: 681a ldr r2, [r3, #0]
800408c: 68fb ldr r3, [r7, #12]
800408e: 681b ldr r3, [r3, #0]
8004090: f442 7280 orr.w r2, r2, #256 @ 0x100
8004094: 601a str r2, [r3, #0]
8004096: e00b b.n 80040b0 <I2C_MasterRequestWrite+0x54>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
8004098: 68fb ldr r3, [r7, #12]
800409a: 6b1b ldr r3, [r3, #48] @ 0x30
800409c: 2b12 cmp r3, #18
800409e: d107 bne.n 80040b0 <I2C_MasterRequestWrite+0x54>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80040a0: 68fb ldr r3, [r7, #12]
80040a2: 681b ldr r3, [r3, #0]
80040a4: 681a ldr r2, [r3, #0]
80040a6: 68fb ldr r3, [r7, #12]
80040a8: 681b ldr r3, [r3, #0]
80040aa: f442 7280 orr.w r2, r2, #256 @ 0x100
80040ae: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
80040b0: 683b ldr r3, [r7, #0]
80040b2: 9300 str r3, [sp, #0]
80040b4: 687b ldr r3, [r7, #4]
80040b6: 2200 movs r2, #0
80040b8: f04f 1101 mov.w r1, #65537 @ 0x10001
80040bc: 68f8 ldr r0, [r7, #12]
80040be: f000 f91d bl 80042fc <I2C_WaitOnFlagUntilTimeout>
80040c2: 4603 mov r3, r0
80040c4: 2b00 cmp r3, #0
80040c6: d00d beq.n 80040e4 <I2C_MasterRequestWrite+0x88>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80040c8: 68fb ldr r3, [r7, #12]
80040ca: 681b ldr r3, [r3, #0]
80040cc: 681b ldr r3, [r3, #0]
80040ce: f403 7380 and.w r3, r3, #256 @ 0x100
80040d2: f5b3 7f80 cmp.w r3, #256 @ 0x100
80040d6: d103 bne.n 80040e0 <I2C_MasterRequestWrite+0x84>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80040d8: 68fb ldr r3, [r7, #12]
80040da: f44f 7200 mov.w r2, #512 @ 0x200
80040de: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80040e0: 2303 movs r3, #3
80040e2: e035 b.n 8004150 <I2C_MasterRequestWrite+0xf4>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80040e4: 68fb ldr r3, [r7, #12]
80040e6: 691b ldr r3, [r3, #16]
80040e8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80040ec: d108 bne.n 8004100 <I2C_MasterRequestWrite+0xa4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
80040ee: 897b ldrh r3, [r7, #10]
80040f0: b2db uxtb r3, r3
80040f2: 461a mov r2, r3
80040f4: 68fb ldr r3, [r7, #12]
80040f6: 681b ldr r3, [r3, #0]
80040f8: f002 02fe and.w r2, r2, #254 @ 0xfe
80040fc: 611a str r2, [r3, #16]
80040fe: e01b b.n 8004138 <I2C_MasterRequestWrite+0xdc>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004100: 897b ldrh r3, [r7, #10]
8004102: 11db asrs r3, r3, #7
8004104: b2db uxtb r3, r3
8004106: f003 0306 and.w r3, r3, #6
800410a: b2db uxtb r3, r3
800410c: f063 030f orn r3, r3, #15
8004110: b2da uxtb r2, r3
8004112: 68fb ldr r3, [r7, #12]
8004114: 681b ldr r3, [r3, #0]
8004116: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
8004118: 683b ldr r3, [r7, #0]
800411a: 687a ldr r2, [r7, #4]
800411c: 490e ldr r1, [pc, #56] @ (8004158 <I2C_MasterRequestWrite+0xfc>)
800411e: 68f8 ldr r0, [r7, #12]
8004120: f000 f966 bl 80043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004124: 4603 mov r3, r0
8004126: 2b00 cmp r3, #0
8004128: d001 beq.n 800412e <I2C_MasterRequestWrite+0xd2>
{
return HAL_ERROR;
800412a: 2301 movs r3, #1
800412c: e010 b.n 8004150 <I2C_MasterRequestWrite+0xf4>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
800412e: 897b ldrh r3, [r7, #10]
8004130: b2da uxtb r2, r3
8004132: 68fb ldr r3, [r7, #12]
8004134: 681b ldr r3, [r3, #0]
8004136: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
8004138: 683b ldr r3, [r7, #0]
800413a: 687a ldr r2, [r7, #4]
800413c: 4907 ldr r1, [pc, #28] @ (800415c <I2C_MasterRequestWrite+0x100>)
800413e: 68f8 ldr r0, [r7, #12]
8004140: f000 f956 bl 80043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004144: 4603 mov r3, r0
8004146: 2b00 cmp r3, #0
8004148: d001 beq.n 800414e <I2C_MasterRequestWrite+0xf2>
{
return HAL_ERROR;
800414a: 2301 movs r3, #1
800414c: e000 b.n 8004150 <I2C_MasterRequestWrite+0xf4>
}
return HAL_OK;
800414e: 2300 movs r3, #0
}
8004150: 4618 mov r0, r3
8004152: 3718 adds r7, #24
8004154: 46bd mov sp, r7
8004156: bd80 pop {r7, pc}
8004158: 00010008 .word 0x00010008
800415c: 00010002 .word 0x00010002
08004160 <I2C_MasterRequestRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
8004160: b580 push {r7, lr}
8004162: b088 sub sp, #32
8004164: af02 add r7, sp, #8
8004166: 60f8 str r0, [r7, #12]
8004168: 607a str r2, [r7, #4]
800416a: 603b str r3, [r7, #0]
800416c: 460b mov r3, r1
800416e: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
8004170: 68fb ldr r3, [r7, #12]
8004172: 6adb ldr r3, [r3, #44] @ 0x2c
8004174: 617b str r3, [r7, #20]
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004176: 68fb ldr r3, [r7, #12]
8004178: 681b ldr r3, [r3, #0]
800417a: 681a ldr r2, [r3, #0]
800417c: 68fb ldr r3, [r7, #12]
800417e: 681b ldr r3, [r3, #0]
8004180: f442 6280 orr.w r2, r2, #1024 @ 0x400
8004184: 601a str r2, [r3, #0]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
8004186: 697b ldr r3, [r7, #20]
8004188: 2b08 cmp r3, #8
800418a: d006 beq.n 800419a <I2C_MasterRequestRead+0x3a>
800418c: 697b ldr r3, [r7, #20]
800418e: 2b01 cmp r3, #1
8004190: d003 beq.n 800419a <I2C_MasterRequestRead+0x3a>
8004192: 697b ldr r3, [r7, #20]
8004194: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004198: d108 bne.n 80041ac <I2C_MasterRequestRead+0x4c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800419a: 68fb ldr r3, [r7, #12]
800419c: 681b ldr r3, [r3, #0]
800419e: 681a ldr r2, [r3, #0]
80041a0: 68fb ldr r3, [r7, #12]
80041a2: 681b ldr r3, [r3, #0]
80041a4: f442 7280 orr.w r2, r2, #256 @ 0x100
80041a8: 601a str r2, [r3, #0]
80041aa: e00b b.n 80041c4 <I2C_MasterRequestRead+0x64>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
80041ac: 68fb ldr r3, [r7, #12]
80041ae: 6b1b ldr r3, [r3, #48] @ 0x30
80041b0: 2b11 cmp r3, #17
80041b2: d107 bne.n 80041c4 <I2C_MasterRequestRead+0x64>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80041b4: 68fb ldr r3, [r7, #12]
80041b6: 681b ldr r3, [r3, #0]
80041b8: 681a ldr r2, [r3, #0]
80041ba: 68fb ldr r3, [r7, #12]
80041bc: 681b ldr r3, [r3, #0]
80041be: f442 7280 orr.w r2, r2, #256 @ 0x100
80041c2: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
80041c4: 683b ldr r3, [r7, #0]
80041c6: 9300 str r3, [sp, #0]
80041c8: 687b ldr r3, [r7, #4]
80041ca: 2200 movs r2, #0
80041cc: f04f 1101 mov.w r1, #65537 @ 0x10001
80041d0: 68f8 ldr r0, [r7, #12]
80041d2: f000 f893 bl 80042fc <I2C_WaitOnFlagUntilTimeout>
80041d6: 4603 mov r3, r0
80041d8: 2b00 cmp r3, #0
80041da: d00d beq.n 80041f8 <I2C_MasterRequestRead+0x98>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80041dc: 68fb ldr r3, [r7, #12]
80041de: 681b ldr r3, [r3, #0]
80041e0: 681b ldr r3, [r3, #0]
80041e2: f403 7380 and.w r3, r3, #256 @ 0x100
80041e6: f5b3 7f80 cmp.w r3, #256 @ 0x100
80041ea: d103 bne.n 80041f4 <I2C_MasterRequestRead+0x94>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80041ec: 68fb ldr r3, [r7, #12]
80041ee: f44f 7200 mov.w r2, #512 @ 0x200
80041f2: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80041f4: 2303 movs r3, #3
80041f6: e079 b.n 80042ec <I2C_MasterRequestRead+0x18c>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80041f8: 68fb ldr r3, [r7, #12]
80041fa: 691b ldr r3, [r3, #16]
80041fc: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8004200: d108 bne.n 8004214 <I2C_MasterRequestRead+0xb4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
8004202: 897b ldrh r3, [r7, #10]
8004204: b2db uxtb r3, r3
8004206: f043 0301 orr.w r3, r3, #1
800420a: b2da uxtb r2, r3
800420c: 68fb ldr r3, [r7, #12]
800420e: 681b ldr r3, [r3, #0]
8004210: 611a str r2, [r3, #16]
8004212: e05f b.n 80042d4 <I2C_MasterRequestRead+0x174>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004214: 897b ldrh r3, [r7, #10]
8004216: 11db asrs r3, r3, #7
8004218: b2db uxtb r3, r3
800421a: f003 0306 and.w r3, r3, #6
800421e: b2db uxtb r3, r3
8004220: f063 030f orn r3, r3, #15
8004224: b2da uxtb r2, r3
8004226: 68fb ldr r3, [r7, #12]
8004228: 681b ldr r3, [r3, #0]
800422a: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
800422c: 683b ldr r3, [r7, #0]
800422e: 687a ldr r2, [r7, #4]
8004230: 4930 ldr r1, [pc, #192] @ (80042f4 <I2C_MasterRequestRead+0x194>)
8004232: 68f8 ldr r0, [r7, #12]
8004234: f000 f8dc bl 80043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004238: 4603 mov r3, r0
800423a: 2b00 cmp r3, #0
800423c: d001 beq.n 8004242 <I2C_MasterRequestRead+0xe2>
{
return HAL_ERROR;
800423e: 2301 movs r3, #1
8004240: e054 b.n 80042ec <I2C_MasterRequestRead+0x18c>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
8004242: 897b ldrh r3, [r7, #10]
8004244: b2da uxtb r2, r3
8004246: 68fb ldr r3, [r7, #12]
8004248: 681b ldr r3, [r3, #0]
800424a: 611a str r2, [r3, #16]
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
800424c: 683b ldr r3, [r7, #0]
800424e: 687a ldr r2, [r7, #4]
8004250: 4929 ldr r1, [pc, #164] @ (80042f8 <I2C_MasterRequestRead+0x198>)
8004252: 68f8 ldr r0, [r7, #12]
8004254: f000 f8cc bl 80043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004258: 4603 mov r3, r0
800425a: 2b00 cmp r3, #0
800425c: d001 beq.n 8004262 <I2C_MasterRequestRead+0x102>
{
return HAL_ERROR;
800425e: 2301 movs r3, #1
8004260: e044 b.n 80042ec <I2C_MasterRequestRead+0x18c>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004262: 2300 movs r3, #0
8004264: 613b str r3, [r7, #16]
8004266: 68fb ldr r3, [r7, #12]
8004268: 681b ldr r3, [r3, #0]
800426a: 695b ldr r3, [r3, #20]
800426c: 613b str r3, [r7, #16]
800426e: 68fb ldr r3, [r7, #12]
8004270: 681b ldr r3, [r3, #0]
8004272: 699b ldr r3, [r3, #24]
8004274: 613b str r3, [r7, #16]
8004276: 693b ldr r3, [r7, #16]
/* Generate Restart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004278: 68fb ldr r3, [r7, #12]
800427a: 681b ldr r3, [r3, #0]
800427c: 681a ldr r2, [r3, #0]
800427e: 68fb ldr r3, [r7, #12]
8004280: 681b ldr r3, [r3, #0]
8004282: f442 7280 orr.w r2, r2, #256 @ 0x100
8004286: 601a str r2, [r3, #0]
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
8004288: 683b ldr r3, [r7, #0]
800428a: 9300 str r3, [sp, #0]
800428c: 687b ldr r3, [r7, #4]
800428e: 2200 movs r2, #0
8004290: f04f 1101 mov.w r1, #65537 @ 0x10001
8004294: 68f8 ldr r0, [r7, #12]
8004296: f000 f831 bl 80042fc <I2C_WaitOnFlagUntilTimeout>
800429a: 4603 mov r3, r0
800429c: 2b00 cmp r3, #0
800429e: d00d beq.n 80042bc <I2C_MasterRequestRead+0x15c>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
80042a0: 68fb ldr r3, [r7, #12]
80042a2: 681b ldr r3, [r3, #0]
80042a4: 681b ldr r3, [r3, #0]
80042a6: f403 7380 and.w r3, r3, #256 @ 0x100
80042aa: f5b3 7f80 cmp.w r3, #256 @ 0x100
80042ae: d103 bne.n 80042b8 <I2C_MasterRequestRead+0x158>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
80042b0: 68fb ldr r3, [r7, #12]
80042b2: f44f 7200 mov.w r2, #512 @ 0x200
80042b6: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
80042b8: 2303 movs r3, #3
80042ba: e017 b.n 80042ec <I2C_MasterRequestRead+0x18c>
}
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
80042bc: 897b ldrh r3, [r7, #10]
80042be: 11db asrs r3, r3, #7
80042c0: b2db uxtb r3, r3
80042c2: f003 0306 and.w r3, r3, #6
80042c6: b2db uxtb r3, r3
80042c8: f063 030e orn r3, r3, #14
80042cc: b2da uxtb r2, r3
80042ce: 68fb ldr r3, [r7, #12]
80042d0: 681b ldr r3, [r3, #0]
80042d2: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
80042d4: 683b ldr r3, [r7, #0]
80042d6: 687a ldr r2, [r7, #4]
80042d8: 4907 ldr r1, [pc, #28] @ (80042f8 <I2C_MasterRequestRead+0x198>)
80042da: 68f8 ldr r0, [r7, #12]
80042dc: f000 f888 bl 80043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80042e0: 4603 mov r3, r0
80042e2: 2b00 cmp r3, #0
80042e4: d001 beq.n 80042ea <I2C_MasterRequestRead+0x18a>
{
return HAL_ERROR;
80042e6: 2301 movs r3, #1
80042e8: e000 b.n 80042ec <I2C_MasterRequestRead+0x18c>
}
return HAL_OK;
80042ea: 2300 movs r3, #0
}
80042ec: 4618 mov r0, r3
80042ee: 3718 adds r7, #24
80042f0: 46bd mov sp, r7
80042f2: bd80 pop {r7, pc}
80042f4: 00010008 .word 0x00010008
80042f8: 00010002 .word 0x00010002
080042fc <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
80042fc: b580 push {r7, lr}
80042fe: b084 sub sp, #16
8004300: af00 add r7, sp, #0
8004302: 60f8 str r0, [r7, #12]
8004304: 60b9 str r1, [r7, #8]
8004306: 603b str r3, [r7, #0]
8004308: 4613 mov r3, r2
800430a: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
800430c: e048 b.n 80043a0 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800430e: 683b ldr r3, [r7, #0]
8004310: f1b3 3fff cmp.w r3, #4294967295
8004314: d044 beq.n 80043a0 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004316: f7fe fc27 bl 8002b68 <HAL_GetTick>
800431a: 4602 mov r2, r0
800431c: 69bb ldr r3, [r7, #24]
800431e: 1ad3 subs r3, r2, r3
8004320: 683a ldr r2, [r7, #0]
8004322: 429a cmp r2, r3
8004324: d302 bcc.n 800432c <I2C_WaitOnFlagUntilTimeout+0x30>
8004326: 683b ldr r3, [r7, #0]
8004328: 2b00 cmp r3, #0
800432a: d139 bne.n 80043a0 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
800432c: 68bb ldr r3, [r7, #8]
800432e: 0c1b lsrs r3, r3, #16
8004330: b2db uxtb r3, r3
8004332: 2b01 cmp r3, #1
8004334: d10d bne.n 8004352 <I2C_WaitOnFlagUntilTimeout+0x56>
8004336: 68fb ldr r3, [r7, #12]
8004338: 681b ldr r3, [r3, #0]
800433a: 695b ldr r3, [r3, #20]
800433c: 43da mvns r2, r3
800433e: 68bb ldr r3, [r7, #8]
8004340: 4013 ands r3, r2
8004342: b29b uxth r3, r3
8004344: 2b00 cmp r3, #0
8004346: bf0c ite eq
8004348: 2301 moveq r3, #1
800434a: 2300 movne r3, #0
800434c: b2db uxtb r3, r3
800434e: 461a mov r2, r3
8004350: e00c b.n 800436c <I2C_WaitOnFlagUntilTimeout+0x70>
8004352: 68fb ldr r3, [r7, #12]
8004354: 681b ldr r3, [r3, #0]
8004356: 699b ldr r3, [r3, #24]
8004358: 43da mvns r2, r3
800435a: 68bb ldr r3, [r7, #8]
800435c: 4013 ands r3, r2
800435e: b29b uxth r3, r3
8004360: 2b00 cmp r3, #0
8004362: bf0c ite eq
8004364: 2301 moveq r3, #1
8004366: 2300 movne r3, #0
8004368: b2db uxtb r3, r3
800436a: 461a mov r2, r3
800436c: 79fb ldrb r3, [r7, #7]
800436e: 429a cmp r2, r3
8004370: d116 bne.n 80043a0 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004372: 68fb ldr r3, [r7, #12]
8004374: 2200 movs r2, #0
8004376: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004378: 68fb ldr r3, [r7, #12]
800437a: 2220 movs r2, #32
800437c: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004380: 68fb ldr r3, [r7, #12]
8004382: 2200 movs r2, #0
8004384: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004388: 68fb ldr r3, [r7, #12]
800438a: 6c1b ldr r3, [r3, #64] @ 0x40
800438c: f043 0220 orr.w r2, r3, #32
8004390: 68fb ldr r3, [r7, #12]
8004392: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004394: 68fb ldr r3, [r7, #12]
8004396: 2200 movs r2, #0
8004398: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
800439c: 2301 movs r3, #1
800439e: e023 b.n 80043e8 <I2C_WaitOnFlagUntilTimeout+0xec>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80043a0: 68bb ldr r3, [r7, #8]
80043a2: 0c1b lsrs r3, r3, #16
80043a4: b2db uxtb r3, r3
80043a6: 2b01 cmp r3, #1
80043a8: d10d bne.n 80043c6 <I2C_WaitOnFlagUntilTimeout+0xca>
80043aa: 68fb ldr r3, [r7, #12]
80043ac: 681b ldr r3, [r3, #0]
80043ae: 695b ldr r3, [r3, #20]
80043b0: 43da mvns r2, r3
80043b2: 68bb ldr r3, [r7, #8]
80043b4: 4013 ands r3, r2
80043b6: b29b uxth r3, r3
80043b8: 2b00 cmp r3, #0
80043ba: bf0c ite eq
80043bc: 2301 moveq r3, #1
80043be: 2300 movne r3, #0
80043c0: b2db uxtb r3, r3
80043c2: 461a mov r2, r3
80043c4: e00c b.n 80043e0 <I2C_WaitOnFlagUntilTimeout+0xe4>
80043c6: 68fb ldr r3, [r7, #12]
80043c8: 681b ldr r3, [r3, #0]
80043ca: 699b ldr r3, [r3, #24]
80043cc: 43da mvns r2, r3
80043ce: 68bb ldr r3, [r7, #8]
80043d0: 4013 ands r3, r2
80043d2: b29b uxth r3, r3
80043d4: 2b00 cmp r3, #0
80043d6: bf0c ite eq
80043d8: 2301 moveq r3, #1
80043da: 2300 movne r3, #0
80043dc: b2db uxtb r3, r3
80043de: 461a mov r2, r3
80043e0: 79fb ldrb r3, [r7, #7]
80043e2: 429a cmp r2, r3
80043e4: d093 beq.n 800430e <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80043e6: 2300 movs r3, #0
}
80043e8: 4618 mov r0, r3
80043ea: 3710 adds r7, #16
80043ec: 46bd mov sp, r7
80043ee: bd80 pop {r7, pc}
080043f0 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
80043f0: b580 push {r7, lr}
80043f2: b084 sub sp, #16
80043f4: af00 add r7, sp, #0
80043f6: 60f8 str r0, [r7, #12]
80043f8: 60b9 str r1, [r7, #8]
80043fa: 607a str r2, [r7, #4]
80043fc: 603b str r3, [r7, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
80043fe: e071 b.n 80044e4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004400: 68fb ldr r3, [r7, #12]
8004402: 681b ldr r3, [r3, #0]
8004404: 695b ldr r3, [r3, #20]
8004406: f403 6380 and.w r3, r3, #1024 @ 0x400
800440a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800440e: d123 bne.n 8004458 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004410: 68fb ldr r3, [r7, #12]
8004412: 681b ldr r3, [r3, #0]
8004414: 681a ldr r2, [r3, #0]
8004416: 68fb ldr r3, [r7, #12]
8004418: 681b ldr r3, [r3, #0]
800441a: f442 7200 orr.w r2, r2, #512 @ 0x200
800441e: 601a str r2, [r3, #0]
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004420: 68fb ldr r3, [r7, #12]
8004422: 681b ldr r3, [r3, #0]
8004424: f46f 6280 mvn.w r2, #1024 @ 0x400
8004428: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
800442a: 68fb ldr r3, [r7, #12]
800442c: 2200 movs r2, #0
800442e: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004430: 68fb ldr r3, [r7, #12]
8004432: 2220 movs r2, #32
8004434: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004438: 68fb ldr r3, [r7, #12]
800443a: 2200 movs r2, #0
800443c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004440: 68fb ldr r3, [r7, #12]
8004442: 6c1b ldr r3, [r3, #64] @ 0x40
8004444: f043 0204 orr.w r2, r3, #4
8004448: 68fb ldr r3, [r7, #12]
800444a: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800444c: 68fb ldr r3, [r7, #12]
800444e: 2200 movs r2, #0
8004450: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004454: 2301 movs r3, #1
8004456: e067 b.n 8004528 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004458: 687b ldr r3, [r7, #4]
800445a: f1b3 3fff cmp.w r3, #4294967295
800445e: d041 beq.n 80044e4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004460: f7fe fb82 bl 8002b68 <HAL_GetTick>
8004464: 4602 mov r2, r0
8004466: 683b ldr r3, [r7, #0]
8004468: 1ad3 subs r3, r2, r3
800446a: 687a ldr r2, [r7, #4]
800446c: 429a cmp r2, r3
800446e: d302 bcc.n 8004476 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
8004470: 687b ldr r3, [r7, #4]
8004472: 2b00 cmp r3, #0
8004474: d136 bne.n 80044e4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
8004476: 68bb ldr r3, [r7, #8]
8004478: 0c1b lsrs r3, r3, #16
800447a: b2db uxtb r3, r3
800447c: 2b01 cmp r3, #1
800447e: d10c bne.n 800449a <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
8004480: 68fb ldr r3, [r7, #12]
8004482: 681b ldr r3, [r3, #0]
8004484: 695b ldr r3, [r3, #20]
8004486: 43da mvns r2, r3
8004488: 68bb ldr r3, [r7, #8]
800448a: 4013 ands r3, r2
800448c: b29b uxth r3, r3
800448e: 2b00 cmp r3, #0
8004490: bf14 ite ne
8004492: 2301 movne r3, #1
8004494: 2300 moveq r3, #0
8004496: b2db uxtb r3, r3
8004498: e00b b.n 80044b2 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
800449a: 68fb ldr r3, [r7, #12]
800449c: 681b ldr r3, [r3, #0]
800449e: 699b ldr r3, [r3, #24]
80044a0: 43da mvns r2, r3
80044a2: 68bb ldr r3, [r7, #8]
80044a4: 4013 ands r3, r2
80044a6: b29b uxth r3, r3
80044a8: 2b00 cmp r3, #0
80044aa: bf14 ite ne
80044ac: 2301 movne r3, #1
80044ae: 2300 moveq r3, #0
80044b0: b2db uxtb r3, r3
80044b2: 2b00 cmp r3, #0
80044b4: d016 beq.n 80044e4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
hi2c->PreviousState = I2C_STATE_NONE;
80044b6: 68fb ldr r3, [r7, #12]
80044b8: 2200 movs r2, #0
80044ba: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80044bc: 68fb ldr r3, [r7, #12]
80044be: 2220 movs r2, #32
80044c0: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80044c4: 68fb ldr r3, [r7, #12]
80044c6: 2200 movs r2, #0
80044c8: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80044cc: 68fb ldr r3, [r7, #12]
80044ce: 6c1b ldr r3, [r3, #64] @ 0x40
80044d0: f043 0220 orr.w r2, r3, #32
80044d4: 68fb ldr r3, [r7, #12]
80044d6: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80044d8: 68fb ldr r3, [r7, #12]
80044da: 2200 movs r2, #0
80044dc: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80044e0: 2301 movs r3, #1
80044e2: e021 b.n 8004528 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
80044e4: 68bb ldr r3, [r7, #8]
80044e6: 0c1b lsrs r3, r3, #16
80044e8: b2db uxtb r3, r3
80044ea: 2b01 cmp r3, #1
80044ec: d10c bne.n 8004508 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 681b ldr r3, [r3, #0]
80044f2: 695b ldr r3, [r3, #20]
80044f4: 43da mvns r2, r3
80044f6: 68bb ldr r3, [r7, #8]
80044f8: 4013 ands r3, r2
80044fa: b29b uxth r3, r3
80044fc: 2b00 cmp r3, #0
80044fe: bf14 ite ne
8004500: 2301 movne r3, #1
8004502: 2300 moveq r3, #0
8004504: b2db uxtb r3, r3
8004506: e00b b.n 8004520 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
8004508: 68fb ldr r3, [r7, #12]
800450a: 681b ldr r3, [r3, #0]
800450c: 699b ldr r3, [r3, #24]
800450e: 43da mvns r2, r3
8004510: 68bb ldr r3, [r7, #8]
8004512: 4013 ands r3, r2
8004514: b29b uxth r3, r3
8004516: 2b00 cmp r3, #0
8004518: bf14 ite ne
800451a: 2301 movne r3, #1
800451c: 2300 moveq r3, #0
800451e: b2db uxtb r3, r3
8004520: 2b00 cmp r3, #0
8004522: f47f af6d bne.w 8004400 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
}
}
}
}
return HAL_OK;
8004526: 2300 movs r3, #0
}
8004528: 4618 mov r0, r3
800452a: 3710 adds r7, #16
800452c: 46bd mov sp, r7
800452e: bd80 pop {r7, pc}
08004530 <I2C_WaitOnTXEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004530: b580 push {r7, lr}
8004532: b084 sub sp, #16
8004534: af00 add r7, sp, #0
8004536: 60f8 str r0, [r7, #12]
8004538: 60b9 str r1, [r7, #8]
800453a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
800453c: e034 b.n 80045a8 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
800453e: 68f8 ldr r0, [r7, #12]
8004540: f000 f8e3 bl 800470a <I2C_IsAcknowledgeFailed>
8004544: 4603 mov r3, r0
8004546: 2b00 cmp r3, #0
8004548: d001 beq.n 800454e <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
800454a: 2301 movs r3, #1
800454c: e034 b.n 80045b8 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800454e: 68bb ldr r3, [r7, #8]
8004550: f1b3 3fff cmp.w r3, #4294967295
8004554: d028 beq.n 80045a8 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004556: f7fe fb07 bl 8002b68 <HAL_GetTick>
800455a: 4602 mov r2, r0
800455c: 687b ldr r3, [r7, #4]
800455e: 1ad3 subs r3, r2, r3
8004560: 68ba ldr r2, [r7, #8]
8004562: 429a cmp r2, r3
8004564: d302 bcc.n 800456c <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
8004566: 68bb ldr r3, [r7, #8]
8004568: 2b00 cmp r3, #0
800456a: d11d bne.n 80045a8 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
800456c: 68fb ldr r3, [r7, #12]
800456e: 681b ldr r3, [r3, #0]
8004570: 695b ldr r3, [r3, #20]
8004572: f003 0380 and.w r3, r3, #128 @ 0x80
8004576: 2b80 cmp r3, #128 @ 0x80
8004578: d016 beq.n 80045a8 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
800457a: 68fb ldr r3, [r7, #12]
800457c: 2200 movs r2, #0
800457e: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004580: 68fb ldr r3, [r7, #12]
8004582: 2220 movs r2, #32
8004584: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004588: 68fb ldr r3, [r7, #12]
800458a: 2200 movs r2, #0
800458c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004590: 68fb ldr r3, [r7, #12]
8004592: 6c1b ldr r3, [r3, #64] @ 0x40
8004594: f043 0220 orr.w r2, r3, #32
8004598: 68fb ldr r3, [r7, #12]
800459a: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800459c: 68fb ldr r3, [r7, #12]
800459e: 2200 movs r2, #0
80045a0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80045a4: 2301 movs r3, #1
80045a6: e007 b.n 80045b8 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
80045a8: 68fb ldr r3, [r7, #12]
80045aa: 681b ldr r3, [r3, #0]
80045ac: 695b ldr r3, [r3, #20]
80045ae: f003 0380 and.w r3, r3, #128 @ 0x80
80045b2: 2b80 cmp r3, #128 @ 0x80
80045b4: d1c3 bne.n 800453e <I2C_WaitOnTXEFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
80045b6: 2300 movs r3, #0
}
80045b8: 4618 mov r0, r3
80045ba: 3710 adds r7, #16
80045bc: 46bd mov sp, r7
80045be: bd80 pop {r7, pc}
080045c0 <I2C_WaitOnBTFFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
80045c0: b580 push {r7, lr}
80045c2: b084 sub sp, #16
80045c4: af00 add r7, sp, #0
80045c6: 60f8 str r0, [r7, #12]
80045c8: 60b9 str r1, [r7, #8]
80045ca: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
80045cc: e034 b.n 8004638 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
80045ce: 68f8 ldr r0, [r7, #12]
80045d0: f000 f89b bl 800470a <I2C_IsAcknowledgeFailed>
80045d4: 4603 mov r3, r0
80045d6: 2b00 cmp r3, #0
80045d8: d001 beq.n 80045de <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
80045da: 2301 movs r3, #1
80045dc: e034 b.n 8004648 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80045de: 68bb ldr r3, [r7, #8]
80045e0: f1b3 3fff cmp.w r3, #4294967295
80045e4: d028 beq.n 8004638 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80045e6: f7fe fabf bl 8002b68 <HAL_GetTick>
80045ea: 4602 mov r2, r0
80045ec: 687b ldr r3, [r7, #4]
80045ee: 1ad3 subs r3, r2, r3
80045f0: 68ba ldr r2, [r7, #8]
80045f2: 429a cmp r2, r3
80045f4: d302 bcc.n 80045fc <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
80045f6: 68bb ldr r3, [r7, #8]
80045f8: 2b00 cmp r3, #0
80045fa: d11d bne.n 8004638 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
80045fc: 68fb ldr r3, [r7, #12]
80045fe: 681b ldr r3, [r3, #0]
8004600: 695b ldr r3, [r3, #20]
8004602: f003 0304 and.w r3, r3, #4
8004606: 2b04 cmp r3, #4
8004608: d016 beq.n 8004638 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
800460a: 68fb ldr r3, [r7, #12]
800460c: 2200 movs r2, #0
800460e: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004610: 68fb ldr r3, [r7, #12]
8004612: 2220 movs r2, #32
8004614: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004618: 68fb ldr r3, [r7, #12]
800461a: 2200 movs r2, #0
800461c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004620: 68fb ldr r3, [r7, #12]
8004622: 6c1b ldr r3, [r3, #64] @ 0x40
8004624: f043 0220 orr.w r2, r3, #32
8004628: 68fb ldr r3, [r7, #12]
800462a: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800462c: 68fb ldr r3, [r7, #12]
800462e: 2200 movs r2, #0
8004630: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004634: 2301 movs r3, #1
8004636: e007 b.n 8004648 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004638: 68fb ldr r3, [r7, #12]
800463a: 681b ldr r3, [r3, #0]
800463c: 695b ldr r3, [r3, #20]
800463e: f003 0304 and.w r3, r3, #4
8004642: 2b04 cmp r3, #4
8004644: d1c3 bne.n 80045ce <I2C_WaitOnBTFFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004646: 2300 movs r3, #0
}
8004648: 4618 mov r0, r3
800464a: 3710 adds r7, #16
800464c: 46bd mov sp, r7
800464e: bd80 pop {r7, pc}
08004650 <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004650: b580 push {r7, lr}
8004652: b084 sub sp, #16
8004654: af00 add r7, sp, #0
8004656: 60f8 str r0, [r7, #12]
8004658: 60b9 str r1, [r7, #8]
800465a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
800465c: e049 b.n 80046f2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
800465e: 68fb ldr r3, [r7, #12]
8004660: 681b ldr r3, [r3, #0]
8004662: 695b ldr r3, [r3, #20]
8004664: f003 0310 and.w r3, r3, #16
8004668: 2b10 cmp r3, #16
800466a: d119 bne.n 80046a0 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800466c: 68fb ldr r3, [r7, #12]
800466e: 681b ldr r3, [r3, #0]
8004670: f06f 0210 mvn.w r2, #16
8004674: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004676: 68fb ldr r3, [r7, #12]
8004678: 2200 movs r2, #0
800467a: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
800467c: 68fb ldr r3, [r7, #12]
800467e: 2220 movs r2, #32
8004680: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004684: 68fb ldr r3, [r7, #12]
8004686: 2200 movs r2, #0
8004688: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
800468c: 68fb ldr r3, [r7, #12]
800468e: 6c1a ldr r2, [r3, #64] @ 0x40
8004690: 68fb ldr r3, [r7, #12]
8004692: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004694: 68fb ldr r3, [r7, #12]
8004696: 2200 movs r2, #0
8004698: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
800469c: 2301 movs r3, #1
800469e: e030 b.n 8004702 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80046a0: f7fe fa62 bl 8002b68 <HAL_GetTick>
80046a4: 4602 mov r2, r0
80046a6: 687b ldr r3, [r7, #4]
80046a8: 1ad3 subs r3, r2, r3
80046aa: 68ba ldr r2, [r7, #8]
80046ac: 429a cmp r2, r3
80046ae: d302 bcc.n 80046b6 <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
80046b0: 68bb ldr r3, [r7, #8]
80046b2: 2b00 cmp r3, #0
80046b4: d11d bne.n 80046f2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
80046b6: 68fb ldr r3, [r7, #12]
80046b8: 681b ldr r3, [r3, #0]
80046ba: 695b ldr r3, [r3, #20]
80046bc: f003 0340 and.w r3, r3, #64 @ 0x40
80046c0: 2b40 cmp r3, #64 @ 0x40
80046c2: d016 beq.n 80046f2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
hi2c->PreviousState = I2C_STATE_NONE;
80046c4: 68fb ldr r3, [r7, #12]
80046c6: 2200 movs r2, #0
80046c8: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80046ca: 68fb ldr r3, [r7, #12]
80046cc: 2220 movs r2, #32
80046ce: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80046d2: 68fb ldr r3, [r7, #12]
80046d4: 2200 movs r2, #0
80046d6: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80046da: 68fb ldr r3, [r7, #12]
80046dc: 6c1b ldr r3, [r3, #64] @ 0x40
80046de: f043 0220 orr.w r2, r3, #32
80046e2: 68fb ldr r3, [r7, #12]
80046e4: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80046e6: 68fb ldr r3, [r7, #12]
80046e8: 2200 movs r2, #0
80046ea: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80046ee: 2301 movs r3, #1
80046f0: e007 b.n 8004702 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
80046f2: 68fb ldr r3, [r7, #12]
80046f4: 681b ldr r3, [r3, #0]
80046f6: 695b ldr r3, [r3, #20]
80046f8: f003 0340 and.w r3, r3, #64 @ 0x40
80046fc: 2b40 cmp r3, #64 @ 0x40
80046fe: d1ae bne.n 800465e <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8004700: 2300 movs r3, #0
}
8004702: 4618 mov r0, r3
8004704: 3710 adds r7, #16
8004706: 46bd mov sp, r7
8004708: bd80 pop {r7, pc}
0800470a <I2C_IsAcknowledgeFailed>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
800470a: b480 push {r7}
800470c: b083 sub sp, #12
800470e: af00 add r7, sp, #0
8004710: 6078 str r0, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004712: 687b ldr r3, [r7, #4]
8004714: 681b ldr r3, [r3, #0]
8004716: 695b ldr r3, [r3, #20]
8004718: f403 6380 and.w r3, r3, #1024 @ 0x400
800471c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004720: d11b bne.n 800475a <I2C_IsAcknowledgeFailed+0x50>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004722: 687b ldr r3, [r7, #4]
8004724: 681b ldr r3, [r3, #0]
8004726: f46f 6280 mvn.w r2, #1024 @ 0x400
800472a: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
800472c: 687b ldr r3, [r7, #4]
800472e: 2200 movs r2, #0
8004730: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004732: 687b ldr r3, [r7, #4]
8004734: 2220 movs r2, #32
8004736: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
800473a: 687b ldr r3, [r7, #4]
800473c: 2200 movs r2, #0
800473e: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004742: 687b ldr r3, [r7, #4]
8004744: 6c1b ldr r3, [r3, #64] @ 0x40
8004746: f043 0204 orr.w r2, r3, #4
800474a: 687b ldr r3, [r7, #4]
800474c: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800474e: 687b ldr r3, [r7, #4]
8004750: 2200 movs r2, #0
8004752: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004756: 2301 movs r3, #1
8004758: e000 b.n 800475c <I2C_IsAcknowledgeFailed+0x52>
}
return HAL_OK;
800475a: 2300 movs r3, #0
}
800475c: 4618 mov r0, r3
800475e: 370c adds r7, #12
8004760: 46bd mov sp, r7
8004762: bc80 pop {r7}
8004764: 4770 bx lr
...
08004768 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004768: b580 push {r7, lr}
800476a: b086 sub sp, #24
800476c: af00 add r7, sp, #0
800476e: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004770: 687b ldr r3, [r7, #4]
8004772: 2b00 cmp r3, #0
8004774: d101 bne.n 800477a <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8004776: 2301 movs r3, #1
8004778: e272 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800477a: 687b ldr r3, [r7, #4]
800477c: 681b ldr r3, [r3, #0]
800477e: f003 0301 and.w r3, r3, #1
8004782: 2b00 cmp r3, #0
8004784: f000 8087 beq.w 8004896 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8004788: 4b92 ldr r3, [pc, #584] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800478a: 685b ldr r3, [r3, #4]
800478c: f003 030c and.w r3, r3, #12
8004790: 2b04 cmp r3, #4
8004792: d00c beq.n 80047ae <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8004794: 4b8f ldr r3, [pc, #572] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004796: 685b ldr r3, [r3, #4]
8004798: f003 030c and.w r3, r3, #12
800479c: 2b08 cmp r3, #8
800479e: d112 bne.n 80047c6 <HAL_RCC_OscConfig+0x5e>
80047a0: 4b8c ldr r3, [pc, #560] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047a2: 685b ldr r3, [r3, #4]
80047a4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80047a8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80047ac: d10b bne.n 80047c6 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80047ae: 4b89 ldr r3, [pc, #548] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047b0: 681b ldr r3, [r3, #0]
80047b2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80047b6: 2b00 cmp r3, #0
80047b8: d06c beq.n 8004894 <HAL_RCC_OscConfig+0x12c>
80047ba: 687b ldr r3, [r7, #4]
80047bc: 685b ldr r3, [r3, #4]
80047be: 2b00 cmp r3, #0
80047c0: d168 bne.n 8004894 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
80047c2: 2301 movs r3, #1
80047c4: e24c b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80047c6: 687b ldr r3, [r7, #4]
80047c8: 685b ldr r3, [r3, #4]
80047ca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80047ce: d106 bne.n 80047de <HAL_RCC_OscConfig+0x76>
80047d0: 4b80 ldr r3, [pc, #512] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047d2: 681b ldr r3, [r3, #0]
80047d4: 4a7f ldr r2, [pc, #508] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047d6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80047da: 6013 str r3, [r2, #0]
80047dc: e02e b.n 800483c <HAL_RCC_OscConfig+0xd4>
80047de: 687b ldr r3, [r7, #4]
80047e0: 685b ldr r3, [r3, #4]
80047e2: 2b00 cmp r3, #0
80047e4: d10c bne.n 8004800 <HAL_RCC_OscConfig+0x98>
80047e6: 4b7b ldr r3, [pc, #492] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047e8: 681b ldr r3, [r3, #0]
80047ea: 4a7a ldr r2, [pc, #488] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047ec: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80047f0: 6013 str r3, [r2, #0]
80047f2: 4b78 ldr r3, [pc, #480] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047f4: 681b ldr r3, [r3, #0]
80047f6: 4a77 ldr r2, [pc, #476] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80047f8: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80047fc: 6013 str r3, [r2, #0]
80047fe: e01d b.n 800483c <HAL_RCC_OscConfig+0xd4>
8004800: 687b ldr r3, [r7, #4]
8004802: 685b ldr r3, [r3, #4]
8004804: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004808: d10c bne.n 8004824 <HAL_RCC_OscConfig+0xbc>
800480a: 4b72 ldr r3, [pc, #456] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800480c: 681b ldr r3, [r3, #0]
800480e: 4a71 ldr r2, [pc, #452] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004810: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8004814: 6013 str r3, [r2, #0]
8004816: 4b6f ldr r3, [pc, #444] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004818: 681b ldr r3, [r3, #0]
800481a: 4a6e ldr r2, [pc, #440] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800481c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004820: 6013 str r3, [r2, #0]
8004822: e00b b.n 800483c <HAL_RCC_OscConfig+0xd4>
8004824: 4b6b ldr r3, [pc, #428] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004826: 681b ldr r3, [r3, #0]
8004828: 4a6a ldr r2, [pc, #424] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800482a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800482e: 6013 str r3, [r2, #0]
8004830: 4b68 ldr r3, [pc, #416] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004832: 681b ldr r3, [r3, #0]
8004834: 4a67 ldr r2, [pc, #412] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004836: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800483a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800483c: 687b ldr r3, [r7, #4]
800483e: 685b ldr r3, [r3, #4]
8004840: 2b00 cmp r3, #0
8004842: d013 beq.n 800486c <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004844: f7fe f990 bl 8002b68 <HAL_GetTick>
8004848: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800484a: e008 b.n 800485e <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800484c: f7fe f98c bl 8002b68 <HAL_GetTick>
8004850: 4602 mov r2, r0
8004852: 693b ldr r3, [r7, #16]
8004854: 1ad3 subs r3, r2, r3
8004856: 2b64 cmp r3, #100 @ 0x64
8004858: d901 bls.n 800485e <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
800485a: 2303 movs r3, #3
800485c: e200 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800485e: 4b5d ldr r3, [pc, #372] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004860: 681b ldr r3, [r3, #0]
8004862: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004866: 2b00 cmp r3, #0
8004868: d0f0 beq.n 800484c <HAL_RCC_OscConfig+0xe4>
800486a: e014 b.n 8004896 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800486c: f7fe f97c bl 8002b68 <HAL_GetTick>
8004870: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004872: e008 b.n 8004886 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004874: f7fe f978 bl 8002b68 <HAL_GetTick>
8004878: 4602 mov r2, r0
800487a: 693b ldr r3, [r7, #16]
800487c: 1ad3 subs r3, r2, r3
800487e: 2b64 cmp r3, #100 @ 0x64
8004880: d901 bls.n 8004886 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8004882: 2303 movs r3, #3
8004884: e1ec b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004886: 4b53 ldr r3, [pc, #332] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004888: 681b ldr r3, [r3, #0]
800488a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800488e: 2b00 cmp r3, #0
8004890: d1f0 bne.n 8004874 <HAL_RCC_OscConfig+0x10c>
8004892: e000 b.n 8004896 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004894: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8004896: 687b ldr r3, [r7, #4]
8004898: 681b ldr r3, [r3, #0]
800489a: f003 0302 and.w r3, r3, #2
800489e: 2b00 cmp r3, #0
80048a0: d063 beq.n 800496a <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80048a2: 4b4c ldr r3, [pc, #304] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048a4: 685b ldr r3, [r3, #4]
80048a6: f003 030c and.w r3, r3, #12
80048aa: 2b00 cmp r3, #0
80048ac: d00b beq.n 80048c6 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
80048ae: 4b49 ldr r3, [pc, #292] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048b0: 685b ldr r3, [r3, #4]
80048b2: f003 030c and.w r3, r3, #12
80048b6: 2b08 cmp r3, #8
80048b8: d11c bne.n 80048f4 <HAL_RCC_OscConfig+0x18c>
80048ba: 4b46 ldr r3, [pc, #280] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048bc: 685b ldr r3, [r3, #4]
80048be: f403 3380 and.w r3, r3, #65536 @ 0x10000
80048c2: 2b00 cmp r3, #0
80048c4: d116 bne.n 80048f4 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80048c6: 4b43 ldr r3, [pc, #268] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048c8: 681b ldr r3, [r3, #0]
80048ca: f003 0302 and.w r3, r3, #2
80048ce: 2b00 cmp r3, #0
80048d0: d005 beq.n 80048de <HAL_RCC_OscConfig+0x176>
80048d2: 687b ldr r3, [r7, #4]
80048d4: 691b ldr r3, [r3, #16]
80048d6: 2b01 cmp r3, #1
80048d8: d001 beq.n 80048de <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
80048da: 2301 movs r3, #1
80048dc: e1c0 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80048de: 4b3d ldr r3, [pc, #244] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048e0: 681b ldr r3, [r3, #0]
80048e2: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80048e6: 687b ldr r3, [r7, #4]
80048e8: 695b ldr r3, [r3, #20]
80048ea: 00db lsls r3, r3, #3
80048ec: 4939 ldr r1, [pc, #228] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80048ee: 4313 orrs r3, r2
80048f0: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80048f2: e03a b.n 800496a <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80048f4: 687b ldr r3, [r7, #4]
80048f6: 691b ldr r3, [r3, #16]
80048f8: 2b00 cmp r3, #0
80048fa: d020 beq.n 800493e <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80048fc: 4b36 ldr r3, [pc, #216] @ (80049d8 <HAL_RCC_OscConfig+0x270>)
80048fe: 2201 movs r2, #1
8004900: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004902: f7fe f931 bl 8002b68 <HAL_GetTick>
8004906: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004908: e008 b.n 800491c <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800490a: f7fe f92d bl 8002b68 <HAL_GetTick>
800490e: 4602 mov r2, r0
8004910: 693b ldr r3, [r7, #16]
8004912: 1ad3 subs r3, r2, r3
8004914: 2b02 cmp r3, #2
8004916: d901 bls.n 800491c <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8004918: 2303 movs r3, #3
800491a: e1a1 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800491c: 4b2d ldr r3, [pc, #180] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800491e: 681b ldr r3, [r3, #0]
8004920: f003 0302 and.w r3, r3, #2
8004924: 2b00 cmp r3, #0
8004926: d0f0 beq.n 800490a <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004928: 4b2a ldr r3, [pc, #168] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
800492a: 681b ldr r3, [r3, #0]
800492c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8004930: 687b ldr r3, [r7, #4]
8004932: 695b ldr r3, [r3, #20]
8004934: 00db lsls r3, r3, #3
8004936: 4927 ldr r1, [pc, #156] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004938: 4313 orrs r3, r2
800493a: 600b str r3, [r1, #0]
800493c: e015 b.n 800496a <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800493e: 4b26 ldr r3, [pc, #152] @ (80049d8 <HAL_RCC_OscConfig+0x270>)
8004940: 2200 movs r2, #0
8004942: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004944: f7fe f910 bl 8002b68 <HAL_GetTick>
8004948: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800494a: e008 b.n 800495e <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800494c: f7fe f90c bl 8002b68 <HAL_GetTick>
8004950: 4602 mov r2, r0
8004952: 693b ldr r3, [r7, #16]
8004954: 1ad3 subs r3, r2, r3
8004956: 2b02 cmp r3, #2
8004958: d901 bls.n 800495e <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
800495a: 2303 movs r3, #3
800495c: e180 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800495e: 4b1d ldr r3, [pc, #116] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
8004960: 681b ldr r3, [r3, #0]
8004962: f003 0302 and.w r3, r3, #2
8004966: 2b00 cmp r3, #0
8004968: d1f0 bne.n 800494c <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800496a: 687b ldr r3, [r7, #4]
800496c: 681b ldr r3, [r3, #0]
800496e: f003 0308 and.w r3, r3, #8
8004972: 2b00 cmp r3, #0
8004974: d03a beq.n 80049ec <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8004976: 687b ldr r3, [r7, #4]
8004978: 699b ldr r3, [r3, #24]
800497a: 2b00 cmp r3, #0
800497c: d019 beq.n 80049b2 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800497e: 4b17 ldr r3, [pc, #92] @ (80049dc <HAL_RCC_OscConfig+0x274>)
8004980: 2201 movs r2, #1
8004982: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004984: f7fe f8f0 bl 8002b68 <HAL_GetTick>
8004988: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800498a: e008 b.n 800499e <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800498c: f7fe f8ec bl 8002b68 <HAL_GetTick>
8004990: 4602 mov r2, r0
8004992: 693b ldr r3, [r7, #16]
8004994: 1ad3 subs r3, r2, r3
8004996: 2b02 cmp r3, #2
8004998: d901 bls.n 800499e <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
800499a: 2303 movs r3, #3
800499c: e160 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800499e: 4b0d ldr r3, [pc, #52] @ (80049d4 <HAL_RCC_OscConfig+0x26c>)
80049a0: 6a5b ldr r3, [r3, #36] @ 0x24
80049a2: f003 0302 and.w r3, r3, #2
80049a6: 2b00 cmp r3, #0
80049a8: d0f0 beq.n 800498c <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
80049aa: 2001 movs r0, #1
80049ac: f000 fad0 bl 8004f50 <RCC_Delay>
80049b0: e01c b.n 80049ec <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80049b2: 4b0a ldr r3, [pc, #40] @ (80049dc <HAL_RCC_OscConfig+0x274>)
80049b4: 2200 movs r2, #0
80049b6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80049b8: f7fe f8d6 bl 8002b68 <HAL_GetTick>
80049bc: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80049be: e00f b.n 80049e0 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80049c0: f7fe f8d2 bl 8002b68 <HAL_GetTick>
80049c4: 4602 mov r2, r0
80049c6: 693b ldr r3, [r7, #16]
80049c8: 1ad3 subs r3, r2, r3
80049ca: 2b02 cmp r3, #2
80049cc: d908 bls.n 80049e0 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
80049ce: 2303 movs r3, #3
80049d0: e146 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
80049d2: bf00 nop
80049d4: 40021000 .word 0x40021000
80049d8: 42420000 .word 0x42420000
80049dc: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80049e0: 4b92 ldr r3, [pc, #584] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
80049e2: 6a5b ldr r3, [r3, #36] @ 0x24
80049e4: f003 0302 and.w r3, r3, #2
80049e8: 2b00 cmp r3, #0
80049ea: d1e9 bne.n 80049c0 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80049ec: 687b ldr r3, [r7, #4]
80049ee: 681b ldr r3, [r3, #0]
80049f0: f003 0304 and.w r3, r3, #4
80049f4: 2b00 cmp r3, #0
80049f6: f000 80a6 beq.w 8004b46 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
80049fa: 2300 movs r3, #0
80049fc: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80049fe: 4b8b ldr r3, [pc, #556] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a00: 69db ldr r3, [r3, #28]
8004a02: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004a06: 2b00 cmp r3, #0
8004a08: d10d bne.n 8004a26 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004a0a: 4b88 ldr r3, [pc, #544] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a0c: 69db ldr r3, [r3, #28]
8004a0e: 4a87 ldr r2, [pc, #540] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004a14: 61d3 str r3, [r2, #28]
8004a16: 4b85 ldr r3, [pc, #532] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a18: 69db ldr r3, [r3, #28]
8004a1a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004a1e: 60bb str r3, [r7, #8]
8004a20: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004a22: 2301 movs r3, #1
8004a24: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004a26: 4b82 ldr r3, [pc, #520] @ (8004c30 <HAL_RCC_OscConfig+0x4c8>)
8004a28: 681b ldr r3, [r3, #0]
8004a2a: f403 7380 and.w r3, r3, #256 @ 0x100
8004a2e: 2b00 cmp r3, #0
8004a30: d118 bne.n 8004a64 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8004a32: 4b7f ldr r3, [pc, #508] @ (8004c30 <HAL_RCC_OscConfig+0x4c8>)
8004a34: 681b ldr r3, [r3, #0]
8004a36: 4a7e ldr r2, [pc, #504] @ (8004c30 <HAL_RCC_OscConfig+0x4c8>)
8004a38: f443 7380 orr.w r3, r3, #256 @ 0x100
8004a3c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004a3e: f7fe f893 bl 8002b68 <HAL_GetTick>
8004a42: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004a44: e008 b.n 8004a58 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004a46: f7fe f88f bl 8002b68 <HAL_GetTick>
8004a4a: 4602 mov r2, r0
8004a4c: 693b ldr r3, [r7, #16]
8004a4e: 1ad3 subs r3, r2, r3
8004a50: 2b64 cmp r3, #100 @ 0x64
8004a52: d901 bls.n 8004a58 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8004a54: 2303 movs r3, #3
8004a56: e103 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004a58: 4b75 ldr r3, [pc, #468] @ (8004c30 <HAL_RCC_OscConfig+0x4c8>)
8004a5a: 681b ldr r3, [r3, #0]
8004a5c: f403 7380 and.w r3, r3, #256 @ 0x100
8004a60: 2b00 cmp r3, #0
8004a62: d0f0 beq.n 8004a46 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8004a64: 687b ldr r3, [r7, #4]
8004a66: 68db ldr r3, [r3, #12]
8004a68: 2b01 cmp r3, #1
8004a6a: d106 bne.n 8004a7a <HAL_RCC_OscConfig+0x312>
8004a6c: 4b6f ldr r3, [pc, #444] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a6e: 6a1b ldr r3, [r3, #32]
8004a70: 4a6e ldr r2, [pc, #440] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a72: f043 0301 orr.w r3, r3, #1
8004a76: 6213 str r3, [r2, #32]
8004a78: e02d b.n 8004ad6 <HAL_RCC_OscConfig+0x36e>
8004a7a: 687b ldr r3, [r7, #4]
8004a7c: 68db ldr r3, [r3, #12]
8004a7e: 2b00 cmp r3, #0
8004a80: d10c bne.n 8004a9c <HAL_RCC_OscConfig+0x334>
8004a82: 4b6a ldr r3, [pc, #424] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a84: 6a1b ldr r3, [r3, #32]
8004a86: 4a69 ldr r2, [pc, #420] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a88: f023 0301 bic.w r3, r3, #1
8004a8c: 6213 str r3, [r2, #32]
8004a8e: 4b67 ldr r3, [pc, #412] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a90: 6a1b ldr r3, [r3, #32]
8004a92: 4a66 ldr r2, [pc, #408] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004a94: f023 0304 bic.w r3, r3, #4
8004a98: 6213 str r3, [r2, #32]
8004a9a: e01c b.n 8004ad6 <HAL_RCC_OscConfig+0x36e>
8004a9c: 687b ldr r3, [r7, #4]
8004a9e: 68db ldr r3, [r3, #12]
8004aa0: 2b05 cmp r3, #5
8004aa2: d10c bne.n 8004abe <HAL_RCC_OscConfig+0x356>
8004aa4: 4b61 ldr r3, [pc, #388] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004aa6: 6a1b ldr r3, [r3, #32]
8004aa8: 4a60 ldr r2, [pc, #384] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004aaa: f043 0304 orr.w r3, r3, #4
8004aae: 6213 str r3, [r2, #32]
8004ab0: 4b5e ldr r3, [pc, #376] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ab2: 6a1b ldr r3, [r3, #32]
8004ab4: 4a5d ldr r2, [pc, #372] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ab6: f043 0301 orr.w r3, r3, #1
8004aba: 6213 str r3, [r2, #32]
8004abc: e00b b.n 8004ad6 <HAL_RCC_OscConfig+0x36e>
8004abe: 4b5b ldr r3, [pc, #364] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ac0: 6a1b ldr r3, [r3, #32]
8004ac2: 4a5a ldr r2, [pc, #360] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ac4: f023 0301 bic.w r3, r3, #1
8004ac8: 6213 str r3, [r2, #32]
8004aca: 4b58 ldr r3, [pc, #352] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004acc: 6a1b ldr r3, [r3, #32]
8004ace: 4a57 ldr r2, [pc, #348] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ad0: f023 0304 bic.w r3, r3, #4
8004ad4: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8004ad6: 687b ldr r3, [r7, #4]
8004ad8: 68db ldr r3, [r3, #12]
8004ada: 2b00 cmp r3, #0
8004adc: d015 beq.n 8004b0a <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004ade: f7fe f843 bl 8002b68 <HAL_GetTick>
8004ae2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004ae4: e00a b.n 8004afc <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004ae6: f7fe f83f bl 8002b68 <HAL_GetTick>
8004aea: 4602 mov r2, r0
8004aec: 693b ldr r3, [r7, #16]
8004aee: 1ad3 subs r3, r2, r3
8004af0: f241 3288 movw r2, #5000 @ 0x1388
8004af4: 4293 cmp r3, r2
8004af6: d901 bls.n 8004afc <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8004af8: 2303 movs r3, #3
8004afa: e0b1 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004afc: 4b4b ldr r3, [pc, #300] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004afe: 6a1b ldr r3, [r3, #32]
8004b00: f003 0302 and.w r3, r3, #2
8004b04: 2b00 cmp r3, #0
8004b06: d0ee beq.n 8004ae6 <HAL_RCC_OscConfig+0x37e>
8004b08: e014 b.n 8004b34 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004b0a: f7fe f82d bl 8002b68 <HAL_GetTick>
8004b0e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004b10: e00a b.n 8004b28 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004b12: f7fe f829 bl 8002b68 <HAL_GetTick>
8004b16: 4602 mov r2, r0
8004b18: 693b ldr r3, [r7, #16]
8004b1a: 1ad3 subs r3, r2, r3
8004b1c: f241 3288 movw r2, #5000 @ 0x1388
8004b20: 4293 cmp r3, r2
8004b22: d901 bls.n 8004b28 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8004b24: 2303 movs r3, #3
8004b26: e09b b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004b28: 4b40 ldr r3, [pc, #256] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b2a: 6a1b ldr r3, [r3, #32]
8004b2c: f003 0302 and.w r3, r3, #2
8004b30: 2b00 cmp r3, #0
8004b32: d1ee bne.n 8004b12 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8004b34: 7dfb ldrb r3, [r7, #23]
8004b36: 2b01 cmp r3, #1
8004b38: d105 bne.n 8004b46 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004b3a: 4b3c ldr r3, [pc, #240] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b3c: 69db ldr r3, [r3, #28]
8004b3e: 4a3b ldr r2, [pc, #236] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b40: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8004b44: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8004b46: 687b ldr r3, [r7, #4]
8004b48: 69db ldr r3, [r3, #28]
8004b4a: 2b00 cmp r3, #0
8004b4c: f000 8087 beq.w 8004c5e <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8004b50: 4b36 ldr r3, [pc, #216] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b52: 685b ldr r3, [r3, #4]
8004b54: f003 030c and.w r3, r3, #12
8004b58: 2b08 cmp r3, #8
8004b5a: d061 beq.n 8004c20 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8004b5c: 687b ldr r3, [r7, #4]
8004b5e: 69db ldr r3, [r3, #28]
8004b60: 2b02 cmp r3, #2
8004b62: d146 bne.n 8004bf2 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8004b64: 4b33 ldr r3, [pc, #204] @ (8004c34 <HAL_RCC_OscConfig+0x4cc>)
8004b66: 2200 movs r2, #0
8004b68: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004b6a: f7fd fffd bl 8002b68 <HAL_GetTick>
8004b6e: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004b70: e008 b.n 8004b84 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004b72: f7fd fff9 bl 8002b68 <HAL_GetTick>
8004b76: 4602 mov r2, r0
8004b78: 693b ldr r3, [r7, #16]
8004b7a: 1ad3 subs r3, r2, r3
8004b7c: 2b02 cmp r3, #2
8004b7e: d901 bls.n 8004b84 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8004b80: 2303 movs r3, #3
8004b82: e06d b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004b84: 4b29 ldr r3, [pc, #164] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b86: 681b ldr r3, [r3, #0]
8004b88: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004b8c: 2b00 cmp r3, #0
8004b8e: d1f0 bne.n 8004b72 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8004b90: 687b ldr r3, [r7, #4]
8004b92: 6a1b ldr r3, [r3, #32]
8004b94: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004b98: d108 bne.n 8004bac <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8004b9a: 4b24 ldr r3, [pc, #144] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004b9c: 685b ldr r3, [r3, #4]
8004b9e: f423 3200 bic.w r2, r3, #131072 @ 0x20000
8004ba2: 687b ldr r3, [r7, #4]
8004ba4: 689b ldr r3, [r3, #8]
8004ba6: 4921 ldr r1, [pc, #132] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004ba8: 4313 orrs r3, r2
8004baa: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8004bac: 4b1f ldr r3, [pc, #124] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004bae: 685b ldr r3, [r3, #4]
8004bb0: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8004bb4: 687b ldr r3, [r7, #4]
8004bb6: 6a19 ldr r1, [r3, #32]
8004bb8: 687b ldr r3, [r7, #4]
8004bba: 6a5b ldr r3, [r3, #36] @ 0x24
8004bbc: 430b orrs r3, r1
8004bbe: 491b ldr r1, [pc, #108] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004bc0: 4313 orrs r3, r2
8004bc2: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8004bc4: 4b1b ldr r3, [pc, #108] @ (8004c34 <HAL_RCC_OscConfig+0x4cc>)
8004bc6: 2201 movs r2, #1
8004bc8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004bca: f7fd ffcd bl 8002b68 <HAL_GetTick>
8004bce: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004bd0: e008 b.n 8004be4 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004bd2: f7fd ffc9 bl 8002b68 <HAL_GetTick>
8004bd6: 4602 mov r2, r0
8004bd8: 693b ldr r3, [r7, #16]
8004bda: 1ad3 subs r3, r2, r3
8004bdc: 2b02 cmp r3, #2
8004bde: d901 bls.n 8004be4 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8004be0: 2303 movs r3, #3
8004be2: e03d b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004be4: 4b11 ldr r3, [pc, #68] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004be6: 681b ldr r3, [r3, #0]
8004be8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004bec: 2b00 cmp r3, #0
8004bee: d0f0 beq.n 8004bd2 <HAL_RCC_OscConfig+0x46a>
8004bf0: e035 b.n 8004c5e <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8004bf2: 4b10 ldr r3, [pc, #64] @ (8004c34 <HAL_RCC_OscConfig+0x4cc>)
8004bf4: 2200 movs r2, #0
8004bf6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004bf8: f7fd ffb6 bl 8002b68 <HAL_GetTick>
8004bfc: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004bfe: e008 b.n 8004c12 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004c00: f7fd ffb2 bl 8002b68 <HAL_GetTick>
8004c04: 4602 mov r2, r0
8004c06: 693b ldr r3, [r7, #16]
8004c08: 1ad3 subs r3, r2, r3
8004c0a: 2b02 cmp r3, #2
8004c0c: d901 bls.n 8004c12 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8004c0e: 2303 movs r3, #3
8004c10: e026 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004c12: 4b06 ldr r3, [pc, #24] @ (8004c2c <HAL_RCC_OscConfig+0x4c4>)
8004c14: 681b ldr r3, [r3, #0]
8004c16: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004c1a: 2b00 cmp r3, #0
8004c1c: d1f0 bne.n 8004c00 <HAL_RCC_OscConfig+0x498>
8004c1e: e01e b.n 8004c5e <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8004c20: 687b ldr r3, [r7, #4]
8004c22: 69db ldr r3, [r3, #28]
8004c24: 2b01 cmp r3, #1
8004c26: d107 bne.n 8004c38 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8004c28: 2301 movs r3, #1
8004c2a: e019 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
8004c2c: 40021000 .word 0x40021000
8004c30: 40007000 .word 0x40007000
8004c34: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8004c38: 4b0b ldr r3, [pc, #44] @ (8004c68 <HAL_RCC_OscConfig+0x500>)
8004c3a: 685b ldr r3, [r3, #4]
8004c3c: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004c3e: 68fb ldr r3, [r7, #12]
8004c40: f403 3280 and.w r2, r3, #65536 @ 0x10000
8004c44: 687b ldr r3, [r7, #4]
8004c46: 6a1b ldr r3, [r3, #32]
8004c48: 429a cmp r2, r3
8004c4a: d106 bne.n 8004c5a <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8004c4c: 68fb ldr r3, [r7, #12]
8004c4e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8004c52: 687b ldr r3, [r7, #4]
8004c54: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004c56: 429a cmp r2, r3
8004c58: d001 beq.n 8004c5e <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
8004c5a: 2301 movs r3, #1
8004c5c: e000 b.n 8004c60 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
8004c5e: 2300 movs r3, #0
}
8004c60: 4618 mov r0, r3
8004c62: 3718 adds r7, #24
8004c64: 46bd mov sp, r7
8004c66: bd80 pop {r7, pc}
8004c68: 40021000 .word 0x40021000
08004c6c <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8004c6c: b580 push {r7, lr}
8004c6e: b084 sub sp, #16
8004c70: af00 add r7, sp, #0
8004c72: 6078 str r0, [r7, #4]
8004c74: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8004c76: 687b ldr r3, [r7, #4]
8004c78: 2b00 cmp r3, #0
8004c7a: d101 bne.n 8004c80 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8004c7c: 2301 movs r3, #1
8004c7e: e0d0 b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8004c80: 4b6a ldr r3, [pc, #424] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004c82: 681b ldr r3, [r3, #0]
8004c84: f003 0307 and.w r3, r3, #7
8004c88: 683a ldr r2, [r7, #0]
8004c8a: 429a cmp r2, r3
8004c8c: d910 bls.n 8004cb0 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004c8e: 4b67 ldr r3, [pc, #412] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004c90: 681b ldr r3, [r3, #0]
8004c92: f023 0207 bic.w r2, r3, #7
8004c96: 4965 ldr r1, [pc, #404] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004c98: 683b ldr r3, [r7, #0]
8004c9a: 4313 orrs r3, r2
8004c9c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8004c9e: 4b63 ldr r3, [pc, #396] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004ca0: 681b ldr r3, [r3, #0]
8004ca2: f003 0307 and.w r3, r3, #7
8004ca6: 683a ldr r2, [r7, #0]
8004ca8: 429a cmp r2, r3
8004caa: d001 beq.n 8004cb0 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8004cac: 2301 movs r3, #1
8004cae: e0b8 b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8004cb0: 687b ldr r3, [r7, #4]
8004cb2: 681b ldr r3, [r3, #0]
8004cb4: f003 0302 and.w r3, r3, #2
8004cb8: 2b00 cmp r3, #0
8004cba: d020 beq.n 8004cfe <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004cbc: 687b ldr r3, [r7, #4]
8004cbe: 681b ldr r3, [r3, #0]
8004cc0: f003 0304 and.w r3, r3, #4
8004cc4: 2b00 cmp r3, #0
8004cc6: d005 beq.n 8004cd4 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8004cc8: 4b59 ldr r3, [pc, #356] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004cca: 685b ldr r3, [r3, #4]
8004ccc: 4a58 ldr r2, [pc, #352] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004cce: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8004cd2: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004cd4: 687b ldr r3, [r7, #4]
8004cd6: 681b ldr r3, [r3, #0]
8004cd8: f003 0308 and.w r3, r3, #8
8004cdc: 2b00 cmp r3, #0
8004cde: d005 beq.n 8004cec <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8004ce0: 4b53 ldr r3, [pc, #332] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004ce2: 685b ldr r3, [r3, #4]
8004ce4: 4a52 ldr r2, [pc, #328] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004ce6: f443 5360 orr.w r3, r3, #14336 @ 0x3800
8004cea: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8004cec: 4b50 ldr r3, [pc, #320] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004cee: 685b ldr r3, [r3, #4]
8004cf0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8004cf4: 687b ldr r3, [r7, #4]
8004cf6: 689b ldr r3, [r3, #8]
8004cf8: 494d ldr r1, [pc, #308] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004cfa: 4313 orrs r3, r2
8004cfc: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 681b ldr r3, [r3, #0]
8004d02: f003 0301 and.w r3, r3, #1
8004d06: 2b00 cmp r3, #0
8004d08: d040 beq.n 8004d8c <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8004d0a: 687b ldr r3, [r7, #4]
8004d0c: 685b ldr r3, [r3, #4]
8004d0e: 2b01 cmp r3, #1
8004d10: d107 bne.n 8004d22 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004d12: 4b47 ldr r3, [pc, #284] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d14: 681b ldr r3, [r3, #0]
8004d16: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004d1a: 2b00 cmp r3, #0
8004d1c: d115 bne.n 8004d4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004d1e: 2301 movs r3, #1
8004d20: e07f b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8004d22: 687b ldr r3, [r7, #4]
8004d24: 685b ldr r3, [r3, #4]
8004d26: 2b02 cmp r3, #2
8004d28: d107 bne.n 8004d3a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004d2a: 4b41 ldr r3, [pc, #260] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d2c: 681b ldr r3, [r3, #0]
8004d2e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004d32: 2b00 cmp r3, #0
8004d34: d109 bne.n 8004d4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004d36: 2301 movs r3, #1
8004d38: e073 b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004d3a: 4b3d ldr r3, [pc, #244] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d3c: 681b ldr r3, [r3, #0]
8004d3e: f003 0302 and.w r3, r3, #2
8004d42: 2b00 cmp r3, #0
8004d44: d101 bne.n 8004d4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004d46: 2301 movs r3, #1
8004d48: e06b b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8004d4a: 4b39 ldr r3, [pc, #228] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d4c: 685b ldr r3, [r3, #4]
8004d4e: f023 0203 bic.w r2, r3, #3
8004d52: 687b ldr r3, [r7, #4]
8004d54: 685b ldr r3, [r3, #4]
8004d56: 4936 ldr r1, [pc, #216] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d58: 4313 orrs r3, r2
8004d5a: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004d5c: f7fd ff04 bl 8002b68 <HAL_GetTick>
8004d60: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004d62: e00a b.n 8004d7a <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004d64: f7fd ff00 bl 8002b68 <HAL_GetTick>
8004d68: 4602 mov r2, r0
8004d6a: 68fb ldr r3, [r7, #12]
8004d6c: 1ad3 subs r3, r2, r3
8004d6e: f241 3288 movw r2, #5000 @ 0x1388
8004d72: 4293 cmp r3, r2
8004d74: d901 bls.n 8004d7a <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8004d76: 2303 movs r3, #3
8004d78: e053 b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004d7a: 4b2d ldr r3, [pc, #180] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004d7c: 685b ldr r3, [r3, #4]
8004d7e: f003 020c and.w r2, r3, #12
8004d82: 687b ldr r3, [r7, #4]
8004d84: 685b ldr r3, [r3, #4]
8004d86: 009b lsls r3, r3, #2
8004d88: 429a cmp r2, r3
8004d8a: d1eb bne.n 8004d64 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8004d8c: 4b27 ldr r3, [pc, #156] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004d8e: 681b ldr r3, [r3, #0]
8004d90: f003 0307 and.w r3, r3, #7
8004d94: 683a ldr r2, [r7, #0]
8004d96: 429a cmp r2, r3
8004d98: d210 bcs.n 8004dbc <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004d9a: 4b24 ldr r3, [pc, #144] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004d9c: 681b ldr r3, [r3, #0]
8004d9e: f023 0207 bic.w r2, r3, #7
8004da2: 4922 ldr r1, [pc, #136] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004da4: 683b ldr r3, [r7, #0]
8004da6: 4313 orrs r3, r2
8004da8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8004daa: 4b20 ldr r3, [pc, #128] @ (8004e2c <HAL_RCC_ClockConfig+0x1c0>)
8004dac: 681b ldr r3, [r3, #0]
8004dae: f003 0307 and.w r3, r3, #7
8004db2: 683a ldr r2, [r7, #0]
8004db4: 429a cmp r2, r3
8004db6: d001 beq.n 8004dbc <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8004db8: 2301 movs r3, #1
8004dba: e032 b.n 8004e22 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004dbc: 687b ldr r3, [r7, #4]
8004dbe: 681b ldr r3, [r3, #0]
8004dc0: f003 0304 and.w r3, r3, #4
8004dc4: 2b00 cmp r3, #0
8004dc6: d008 beq.n 8004dda <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8004dc8: 4b19 ldr r3, [pc, #100] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004dca: 685b ldr r3, [r3, #4]
8004dcc: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8004dd0: 687b ldr r3, [r7, #4]
8004dd2: 68db ldr r3, [r3, #12]
8004dd4: 4916 ldr r1, [pc, #88] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004dd6: 4313 orrs r3, r2
8004dd8: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004dda: 687b ldr r3, [r7, #4]
8004ddc: 681b ldr r3, [r3, #0]
8004dde: f003 0308 and.w r3, r3, #8
8004de2: 2b00 cmp r3, #0
8004de4: d009 beq.n 8004dfa <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8004de6: 4b12 ldr r3, [pc, #72] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004de8: 685b ldr r3, [r3, #4]
8004dea: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8004dee: 687b ldr r3, [r7, #4]
8004df0: 691b ldr r3, [r3, #16]
8004df2: 00db lsls r3, r3, #3
8004df4: 490e ldr r1, [pc, #56] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004df6: 4313 orrs r3, r2
8004df8: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8004dfa: f000 f821 bl 8004e40 <HAL_RCC_GetSysClockFreq>
8004dfe: 4602 mov r2, r0
8004e00: 4b0b ldr r3, [pc, #44] @ (8004e30 <HAL_RCC_ClockConfig+0x1c4>)
8004e02: 685b ldr r3, [r3, #4]
8004e04: 091b lsrs r3, r3, #4
8004e06: f003 030f and.w r3, r3, #15
8004e0a: 490a ldr r1, [pc, #40] @ (8004e34 <HAL_RCC_ClockConfig+0x1c8>)
8004e0c: 5ccb ldrb r3, [r1, r3]
8004e0e: fa22 f303 lsr.w r3, r2, r3
8004e12: 4a09 ldr r2, [pc, #36] @ (8004e38 <HAL_RCC_ClockConfig+0x1cc>)
8004e14: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8004e16: 4b09 ldr r3, [pc, #36] @ (8004e3c <HAL_RCC_ClockConfig+0x1d0>)
8004e18: 681b ldr r3, [r3, #0]
8004e1a: 4618 mov r0, r3
8004e1c: f7fd fe62 bl 8002ae4 <HAL_InitTick>
return HAL_OK;
8004e20: 2300 movs r3, #0
}
8004e22: 4618 mov r0, r3
8004e24: 3710 adds r7, #16
8004e26: 46bd mov sp, r7
8004e28: bd80 pop {r7, pc}
8004e2a: bf00 nop
8004e2c: 40022000 .word 0x40022000
8004e30: 40021000 .word 0x40021000
8004e34: 08006710 .word 0x08006710
8004e38: 20000038 .word 0x20000038
8004e3c: 2000003c .word 0x2000003c
08004e40 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004e40: b480 push {r7}
8004e42: b087 sub sp, #28
8004e44: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8004e46: 2300 movs r3, #0
8004e48: 60fb str r3, [r7, #12]
8004e4a: 2300 movs r3, #0
8004e4c: 60bb str r3, [r7, #8]
8004e4e: 2300 movs r3, #0
8004e50: 617b str r3, [r7, #20]
8004e52: 2300 movs r3, #0
8004e54: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
8004e56: 2300 movs r3, #0
8004e58: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8004e5a: 4b1e ldr r3, [pc, #120] @ (8004ed4 <HAL_RCC_GetSysClockFreq+0x94>)
8004e5c: 685b ldr r3, [r3, #4]
8004e5e: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8004e60: 68fb ldr r3, [r7, #12]
8004e62: f003 030c and.w r3, r3, #12
8004e66: 2b04 cmp r3, #4
8004e68: d002 beq.n 8004e70 <HAL_RCC_GetSysClockFreq+0x30>
8004e6a: 2b08 cmp r3, #8
8004e6c: d003 beq.n 8004e76 <HAL_RCC_GetSysClockFreq+0x36>
8004e6e: e027 b.n 8004ec0 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8004e70: 4b19 ldr r3, [pc, #100] @ (8004ed8 <HAL_RCC_GetSysClockFreq+0x98>)
8004e72: 613b str r3, [r7, #16]
break;
8004e74: e027 b.n 8004ec6 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8004e76: 68fb ldr r3, [r7, #12]
8004e78: 0c9b lsrs r3, r3, #18
8004e7a: f003 030f and.w r3, r3, #15
8004e7e: 4a17 ldr r2, [pc, #92] @ (8004edc <HAL_RCC_GetSysClockFreq+0x9c>)
8004e80: 5cd3 ldrb r3, [r2, r3]
8004e82: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8004e84: 68fb ldr r3, [r7, #12]
8004e86: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004e8a: 2b00 cmp r3, #0
8004e8c: d010 beq.n 8004eb0 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8004e8e: 4b11 ldr r3, [pc, #68] @ (8004ed4 <HAL_RCC_GetSysClockFreq+0x94>)
8004e90: 685b ldr r3, [r3, #4]
8004e92: 0c5b lsrs r3, r3, #17
8004e94: f003 0301 and.w r3, r3, #1
8004e98: 4a11 ldr r2, [pc, #68] @ (8004ee0 <HAL_RCC_GetSysClockFreq+0xa0>)
8004e9a: 5cd3 ldrb r3, [r2, r3]
8004e9c: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8004e9e: 687b ldr r3, [r7, #4]
8004ea0: 4a0d ldr r2, [pc, #52] @ (8004ed8 <HAL_RCC_GetSysClockFreq+0x98>)
8004ea2: fb03 f202 mul.w r2, r3, r2
8004ea6: 68bb ldr r3, [r7, #8]
8004ea8: fbb2 f3f3 udiv r3, r2, r3
8004eac: 617b str r3, [r7, #20]
8004eae: e004 b.n 8004eba <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8004eb0: 687b ldr r3, [r7, #4]
8004eb2: 4a0c ldr r2, [pc, #48] @ (8004ee4 <HAL_RCC_GetSysClockFreq+0xa4>)
8004eb4: fb02 f303 mul.w r3, r2, r3
8004eb8: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8004eba: 697b ldr r3, [r7, #20]
8004ebc: 613b str r3, [r7, #16]
break;
8004ebe: e002 b.n 8004ec6 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8004ec0: 4b09 ldr r3, [pc, #36] @ (8004ee8 <HAL_RCC_GetSysClockFreq+0xa8>)
8004ec2: 613b str r3, [r7, #16]
break;
8004ec4: bf00 nop
}
}
return sysclockfreq;
8004ec6: 693b ldr r3, [r7, #16]
}
8004ec8: 4618 mov r0, r3
8004eca: 371c adds r7, #28
8004ecc: 46bd mov sp, r7
8004ece: bc80 pop {r7}
8004ed0: 4770 bx lr
8004ed2: bf00 nop
8004ed4: 40021000 .word 0x40021000
8004ed8: 00b71b00 .word 0x00b71b00
8004edc: 08006728 .word 0x08006728
8004ee0: 08006738 .word 0x08006738
8004ee4: 003d0900 .word 0x003d0900
8004ee8: 007a1200 .word 0x007a1200
08004eec <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8004eec: b480 push {r7}
8004eee: af00 add r7, sp, #0
return SystemCoreClock;
8004ef0: 4b02 ldr r3, [pc, #8] @ (8004efc <HAL_RCC_GetHCLKFreq+0x10>)
8004ef2: 681b ldr r3, [r3, #0]
}
8004ef4: 4618 mov r0, r3
8004ef6: 46bd mov sp, r7
8004ef8: bc80 pop {r7}
8004efa: 4770 bx lr
8004efc: 20000038 .word 0x20000038
08004f00 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8004f00: b580 push {r7, lr}
8004f02: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8004f04: f7ff fff2 bl 8004eec <HAL_RCC_GetHCLKFreq>
8004f08: 4602 mov r2, r0
8004f0a: 4b05 ldr r3, [pc, #20] @ (8004f20 <HAL_RCC_GetPCLK1Freq+0x20>)
8004f0c: 685b ldr r3, [r3, #4]
8004f0e: 0a1b lsrs r3, r3, #8
8004f10: f003 0307 and.w r3, r3, #7
8004f14: 4903 ldr r1, [pc, #12] @ (8004f24 <HAL_RCC_GetPCLK1Freq+0x24>)
8004f16: 5ccb ldrb r3, [r1, r3]
8004f18: fa22 f303 lsr.w r3, r2, r3
}
8004f1c: 4618 mov r0, r3
8004f1e: bd80 pop {r7, pc}
8004f20: 40021000 .word 0x40021000
8004f24: 08006720 .word 0x08006720
08004f28 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8004f28: b580 push {r7, lr}
8004f2a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8004f2c: f7ff ffde bl 8004eec <HAL_RCC_GetHCLKFreq>
8004f30: 4602 mov r2, r0
8004f32: 4b05 ldr r3, [pc, #20] @ (8004f48 <HAL_RCC_GetPCLK2Freq+0x20>)
8004f34: 685b ldr r3, [r3, #4]
8004f36: 0adb lsrs r3, r3, #11
8004f38: f003 0307 and.w r3, r3, #7
8004f3c: 4903 ldr r1, [pc, #12] @ (8004f4c <HAL_RCC_GetPCLK2Freq+0x24>)
8004f3e: 5ccb ldrb r3, [r1, r3]
8004f40: fa22 f303 lsr.w r3, r2, r3
}
8004f44: 4618 mov r0, r3
8004f46: bd80 pop {r7, pc}
8004f48: 40021000 .word 0x40021000
8004f4c: 08006720 .word 0x08006720
08004f50 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8004f50: b480 push {r7}
8004f52: b085 sub sp, #20
8004f54: af00 add r7, sp, #0
8004f56: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8004f58: 4b0a ldr r3, [pc, #40] @ (8004f84 <RCC_Delay+0x34>)
8004f5a: 681b ldr r3, [r3, #0]
8004f5c: 4a0a ldr r2, [pc, #40] @ (8004f88 <RCC_Delay+0x38>)
8004f5e: fba2 2303 umull r2, r3, r2, r3
8004f62: 0a5b lsrs r3, r3, #9
8004f64: 687a ldr r2, [r7, #4]
8004f66: fb02 f303 mul.w r3, r2, r3
8004f6a: 60fb str r3, [r7, #12]
do
{
__NOP();
8004f6c: bf00 nop
}
while (Delay --);
8004f6e: 68fb ldr r3, [r7, #12]
8004f70: 1e5a subs r2, r3, #1
8004f72: 60fa str r2, [r7, #12]
8004f74: 2b00 cmp r3, #0
8004f76: d1f9 bne.n 8004f6c <RCC_Delay+0x1c>
}
8004f78: bf00 nop
8004f7a: bf00 nop
8004f7c: 3714 adds r7, #20
8004f7e: 46bd mov sp, r7
8004f80: bc80 pop {r7}
8004f82: 4770 bx lr
8004f84: 20000038 .word 0x20000038
8004f88: 10624dd3 .word 0x10624dd3
08004f8c <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004f8c: b580 push {r7, lr}
8004f8e: b086 sub sp, #24
8004f90: af00 add r7, sp, #0
8004f92: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8004f94: 2300 movs r3, #0
8004f96: 613b str r3, [r7, #16]
8004f98: 2300 movs r3, #0
8004f9a: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8004f9c: 687b ldr r3, [r7, #4]
8004f9e: 681b ldr r3, [r3, #0]
8004fa0: f003 0301 and.w r3, r3, #1
8004fa4: 2b00 cmp r3, #0
8004fa6: d07d beq.n 80050a4 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8004fa8: 2300 movs r3, #0
8004faa: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8004fac: 4b4f ldr r3, [pc, #316] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004fae: 69db ldr r3, [r3, #28]
8004fb0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004fb4: 2b00 cmp r3, #0
8004fb6: d10d bne.n 8004fd4 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004fb8: 4b4c ldr r3, [pc, #304] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004fba: 69db ldr r3, [r3, #28]
8004fbc: 4a4b ldr r2, [pc, #300] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004fbe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004fc2: 61d3 str r3, [r2, #28]
8004fc4: 4b49 ldr r3, [pc, #292] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004fc6: 69db ldr r3, [r3, #28]
8004fc8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004fcc: 60bb str r3, [r7, #8]
8004fce: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004fd0: 2301 movs r3, #1
8004fd2: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004fd4: 4b46 ldr r3, [pc, #280] @ (80050f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004fd6: 681b ldr r3, [r3, #0]
8004fd8: f403 7380 and.w r3, r3, #256 @ 0x100
8004fdc: 2b00 cmp r3, #0
8004fde: d118 bne.n 8005012 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8004fe0: 4b43 ldr r3, [pc, #268] @ (80050f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004fe2: 681b ldr r3, [r3, #0]
8004fe4: 4a42 ldr r2, [pc, #264] @ (80050f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004fe6: f443 7380 orr.w r3, r3, #256 @ 0x100
8004fea: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004fec: f7fd fdbc bl 8002b68 <HAL_GetTick>
8004ff0: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004ff2: e008 b.n 8005006 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004ff4: f7fd fdb8 bl 8002b68 <HAL_GetTick>
8004ff8: 4602 mov r2, r0
8004ffa: 693b ldr r3, [r7, #16]
8004ffc: 1ad3 subs r3, r2, r3
8004ffe: 2b64 cmp r3, #100 @ 0x64
8005000: d901 bls.n 8005006 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8005002: 2303 movs r3, #3
8005004: e06d b.n 80050e2 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005006: 4b3a ldr r3, [pc, #232] @ (80050f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005008: 681b ldr r3, [r3, #0]
800500a: f403 7380 and.w r3, r3, #256 @ 0x100
800500e: 2b00 cmp r3, #0
8005010: d0f0 beq.n 8004ff4 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8005012: 4b36 ldr r3, [pc, #216] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005014: 6a1b ldr r3, [r3, #32]
8005016: f403 7340 and.w r3, r3, #768 @ 0x300
800501a: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
800501c: 68fb ldr r3, [r7, #12]
800501e: 2b00 cmp r3, #0
8005020: d02e beq.n 8005080 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8005022: 687b ldr r3, [r7, #4]
8005024: 685b ldr r3, [r3, #4]
8005026: f403 7340 and.w r3, r3, #768 @ 0x300
800502a: 68fa ldr r2, [r7, #12]
800502c: 429a cmp r2, r3
800502e: d027 beq.n 8005080 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8005030: 4b2e ldr r3, [pc, #184] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005032: 6a1b ldr r3, [r3, #32]
8005034: f423 7340 bic.w r3, r3, #768 @ 0x300
8005038: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800503a: 4b2e ldr r3, [pc, #184] @ (80050f4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
800503c: 2201 movs r2, #1
800503e: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8005040: 4b2c ldr r3, [pc, #176] @ (80050f4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005042: 2200 movs r2, #0
8005044: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8005046: 4a29 ldr r2, [pc, #164] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005048: 68fb ldr r3, [r7, #12]
800504a: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
800504c: 68fb ldr r3, [r7, #12]
800504e: f003 0301 and.w r3, r3, #1
8005052: 2b00 cmp r3, #0
8005054: d014 beq.n 8005080 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005056: f7fd fd87 bl 8002b68 <HAL_GetTick>
800505a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800505c: e00a b.n 8005074 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800505e: f7fd fd83 bl 8002b68 <HAL_GetTick>
8005062: 4602 mov r2, r0
8005064: 693b ldr r3, [r7, #16]
8005066: 1ad3 subs r3, r2, r3
8005068: f241 3288 movw r2, #5000 @ 0x1388
800506c: 4293 cmp r3, r2
800506e: d901 bls.n 8005074 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8005070: 2303 movs r3, #3
8005072: e036 b.n 80050e2 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005074: 4b1d ldr r3, [pc, #116] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005076: 6a1b ldr r3, [r3, #32]
8005078: f003 0302 and.w r3, r3, #2
800507c: 2b00 cmp r3, #0
800507e: d0ee beq.n 800505e <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005080: 4b1a ldr r3, [pc, #104] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005082: 6a1b ldr r3, [r3, #32]
8005084: f423 7240 bic.w r2, r3, #768 @ 0x300
8005088: 687b ldr r3, [r7, #4]
800508a: 685b ldr r3, [r3, #4]
800508c: 4917 ldr r1, [pc, #92] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800508e: 4313 orrs r3, r2
8005090: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005092: 7dfb ldrb r3, [r7, #23]
8005094: 2b01 cmp r3, #1
8005096: d105 bne.n 80050a4 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005098: 4b14 ldr r3, [pc, #80] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800509a: 69db ldr r3, [r3, #28]
800509c: 4a13 ldr r2, [pc, #76] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800509e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80050a2: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80050a4: 687b ldr r3, [r7, #4]
80050a6: 681b ldr r3, [r3, #0]
80050a8: f003 0302 and.w r3, r3, #2
80050ac: 2b00 cmp r3, #0
80050ae: d008 beq.n 80050c2 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80050b0: 4b0e ldr r3, [pc, #56] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80050b2: 685b ldr r3, [r3, #4]
80050b4: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80050b8: 687b ldr r3, [r7, #4]
80050ba: 689b ldr r3, [r3, #8]
80050bc: 490b ldr r1, [pc, #44] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80050be: 4313 orrs r3, r2
80050c0: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80050c2: 687b ldr r3, [r7, #4]
80050c4: 681b ldr r3, [r3, #0]
80050c6: f003 0310 and.w r3, r3, #16
80050ca: 2b00 cmp r3, #0
80050cc: d008 beq.n 80050e0 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80050ce: 4b07 ldr r3, [pc, #28] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80050d0: 685b ldr r3, [r3, #4]
80050d2: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
80050d6: 687b ldr r3, [r7, #4]
80050d8: 68db ldr r3, [r3, #12]
80050da: 4904 ldr r1, [pc, #16] @ (80050ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80050dc: 4313 orrs r3, r2
80050de: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
80050e0: 2300 movs r3, #0
}
80050e2: 4618 mov r0, r3
80050e4: 3718 adds r7, #24
80050e6: 46bd mov sp, r7
80050e8: bd80 pop {r7, pc}
80050ea: bf00 nop
80050ec: 40021000 .word 0x40021000
80050f0: 40007000 .word 0x40007000
80050f4: 42420440 .word 0x42420440
080050f8 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80050f8: b580 push {r7, lr}
80050fa: b082 sub sp, #8
80050fc: af00 add r7, sp, #0
80050fe: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8005100: 687b ldr r3, [r7, #4]
8005102: 2b00 cmp r3, #0
8005104: d101 bne.n 800510a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8005106: 2301 movs r3, #1
8005108: e041 b.n 800518e <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800510a: 687b ldr r3, [r7, #4]
800510c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005110: b2db uxtb r3, r3
8005112: 2b00 cmp r3, #0
8005114: d106 bne.n 8005124 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005116: 687b ldr r3, [r7, #4]
8005118: 2200 movs r2, #0
800511a: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800511e: 6878 ldr r0, [r7, #4]
8005120: f7fd fc00 bl 8002924 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005124: 687b ldr r3, [r7, #4]
8005126: 2202 movs r2, #2
8005128: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800512c: 687b ldr r3, [r7, #4]
800512e: 681a ldr r2, [r3, #0]
8005130: 687b ldr r3, [r7, #4]
8005132: 3304 adds r3, #4
8005134: 4619 mov r1, r3
8005136: 4610 mov r0, r2
8005138: f000 fa5c bl 80055f4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800513c: 687b ldr r3, [r7, #4]
800513e: 2201 movs r2, #1
8005140: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005144: 687b ldr r3, [r7, #4]
8005146: 2201 movs r2, #1
8005148: f883 203e strb.w r2, [r3, #62] @ 0x3e
800514c: 687b ldr r3, [r7, #4]
800514e: 2201 movs r2, #1
8005150: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005154: 687b ldr r3, [r7, #4]
8005156: 2201 movs r2, #1
8005158: f883 2040 strb.w r2, [r3, #64] @ 0x40
800515c: 687b ldr r3, [r7, #4]
800515e: 2201 movs r2, #1
8005160: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005164: 687b ldr r3, [r7, #4]
8005166: 2201 movs r2, #1
8005168: f883 2042 strb.w r2, [r3, #66] @ 0x42
800516c: 687b ldr r3, [r7, #4]
800516e: 2201 movs r2, #1
8005170: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005174: 687b ldr r3, [r7, #4]
8005176: 2201 movs r2, #1
8005178: f883 2044 strb.w r2, [r3, #68] @ 0x44
800517c: 687b ldr r3, [r7, #4]
800517e: 2201 movs r2, #1
8005180: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005184: 687b ldr r3, [r7, #4]
8005186: 2201 movs r2, #1
8005188: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800518c: 2300 movs r3, #0
}
800518e: 4618 mov r0, r3
8005190: 3708 adds r7, #8
8005192: 46bd mov sp, r7
8005194: bd80 pop {r7, pc}
...
08005198 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8005198: b480 push {r7}
800519a: b085 sub sp, #20
800519c: af00 add r7, sp, #0
800519e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
80051a0: 687b ldr r3, [r7, #4]
80051a2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80051a6: b2db uxtb r3, r3
80051a8: 2b01 cmp r3, #1
80051aa: d001 beq.n 80051b0 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
80051ac: 2301 movs r3, #1
80051ae: e03a b.n 8005226 <HAL_TIM_Base_Start_IT+0x8e>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80051b0: 687b ldr r3, [r7, #4]
80051b2: 2202 movs r2, #2
80051b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
80051b8: 687b ldr r3, [r7, #4]
80051ba: 681b ldr r3, [r3, #0]
80051bc: 68da ldr r2, [r3, #12]
80051be: 687b ldr r3, [r7, #4]
80051c0: 681b ldr r3, [r3, #0]
80051c2: f042 0201 orr.w r2, r2, #1
80051c6: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80051c8: 687b ldr r3, [r7, #4]
80051ca: 681b ldr r3, [r3, #0]
80051cc: 4a18 ldr r2, [pc, #96] @ (8005230 <HAL_TIM_Base_Start_IT+0x98>)
80051ce: 4293 cmp r3, r2
80051d0: d00e beq.n 80051f0 <HAL_TIM_Base_Start_IT+0x58>
80051d2: 687b ldr r3, [r7, #4]
80051d4: 681b ldr r3, [r3, #0]
80051d6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80051da: d009 beq.n 80051f0 <HAL_TIM_Base_Start_IT+0x58>
80051dc: 687b ldr r3, [r7, #4]
80051de: 681b ldr r3, [r3, #0]
80051e0: 4a14 ldr r2, [pc, #80] @ (8005234 <HAL_TIM_Base_Start_IT+0x9c>)
80051e2: 4293 cmp r3, r2
80051e4: d004 beq.n 80051f0 <HAL_TIM_Base_Start_IT+0x58>
80051e6: 687b ldr r3, [r7, #4]
80051e8: 681b ldr r3, [r3, #0]
80051ea: 4a13 ldr r2, [pc, #76] @ (8005238 <HAL_TIM_Base_Start_IT+0xa0>)
80051ec: 4293 cmp r3, r2
80051ee: d111 bne.n 8005214 <HAL_TIM_Base_Start_IT+0x7c>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80051f0: 687b ldr r3, [r7, #4]
80051f2: 681b ldr r3, [r3, #0]
80051f4: 689b ldr r3, [r3, #8]
80051f6: f003 0307 and.w r3, r3, #7
80051fa: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80051fc: 68fb ldr r3, [r7, #12]
80051fe: 2b06 cmp r3, #6
8005200: d010 beq.n 8005224 <HAL_TIM_Base_Start_IT+0x8c>
{
__HAL_TIM_ENABLE(htim);
8005202: 687b ldr r3, [r7, #4]
8005204: 681b ldr r3, [r3, #0]
8005206: 681a ldr r2, [r3, #0]
8005208: 687b ldr r3, [r7, #4]
800520a: 681b ldr r3, [r3, #0]
800520c: f042 0201 orr.w r2, r2, #1
8005210: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005212: e007 b.n 8005224 <HAL_TIM_Base_Start_IT+0x8c>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8005214: 687b ldr r3, [r7, #4]
8005216: 681b ldr r3, [r3, #0]
8005218: 681a ldr r2, [r3, #0]
800521a: 687b ldr r3, [r7, #4]
800521c: 681b ldr r3, [r3, #0]
800521e: f042 0201 orr.w r2, r2, #1
8005222: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8005224: 2300 movs r3, #0
}
8005226: 4618 mov r0, r3
8005228: 3714 adds r7, #20
800522a: 46bd mov sp, r7
800522c: bc80 pop {r7}
800522e: 4770 bx lr
8005230: 40012c00 .word 0x40012c00
8005234: 40000400 .word 0x40000400
8005238: 40000800 .word 0x40000800
0800523c <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
800523c: b580 push {r7, lr}
800523e: b084 sub sp, #16
8005240: af00 add r7, sp, #0
8005242: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8005244: 687b ldr r3, [r7, #4]
8005246: 681b ldr r3, [r3, #0]
8005248: 68db ldr r3, [r3, #12]
800524a: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800524c: 687b ldr r3, [r7, #4]
800524e: 681b ldr r3, [r3, #0]
8005250: 691b ldr r3, [r3, #16]
8005252: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8005254: 68bb ldr r3, [r7, #8]
8005256: f003 0302 and.w r3, r3, #2
800525a: 2b00 cmp r3, #0
800525c: d020 beq.n 80052a0 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800525e: 68fb ldr r3, [r7, #12]
8005260: f003 0302 and.w r3, r3, #2
8005264: 2b00 cmp r3, #0
8005266: d01b beq.n 80052a0 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8005268: 687b ldr r3, [r7, #4]
800526a: 681b ldr r3, [r3, #0]
800526c: f06f 0202 mvn.w r2, #2
8005270: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8005272: 687b ldr r3, [r7, #4]
8005274: 2201 movs r2, #1
8005276: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8005278: 687b ldr r3, [r7, #4]
800527a: 681b ldr r3, [r3, #0]
800527c: 699b ldr r3, [r3, #24]
800527e: f003 0303 and.w r3, r3, #3
8005282: 2b00 cmp r3, #0
8005284: d003 beq.n 800528e <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005286: 6878 ldr r0, [r7, #4]
8005288: f000 f998 bl 80055bc <HAL_TIM_IC_CaptureCallback>
800528c: e005 b.n 800529a <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800528e: 6878 ldr r0, [r7, #4]
8005290: f000 f98b bl 80055aa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005294: 6878 ldr r0, [r7, #4]
8005296: f000 f99a bl 80055ce <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800529a: 687b ldr r3, [r7, #4]
800529c: 2200 movs r2, #0
800529e: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
80052a0: 68bb ldr r3, [r7, #8]
80052a2: f003 0304 and.w r3, r3, #4
80052a6: 2b00 cmp r3, #0
80052a8: d020 beq.n 80052ec <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
80052aa: 68fb ldr r3, [r7, #12]
80052ac: f003 0304 and.w r3, r3, #4
80052b0: 2b00 cmp r3, #0
80052b2: d01b beq.n 80052ec <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80052b4: 687b ldr r3, [r7, #4]
80052b6: 681b ldr r3, [r3, #0]
80052b8: f06f 0204 mvn.w r2, #4
80052bc: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80052be: 687b ldr r3, [r7, #4]
80052c0: 2202 movs r2, #2
80052c2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80052c4: 687b ldr r3, [r7, #4]
80052c6: 681b ldr r3, [r3, #0]
80052c8: 699b ldr r3, [r3, #24]
80052ca: f403 7340 and.w r3, r3, #768 @ 0x300
80052ce: 2b00 cmp r3, #0
80052d0: d003 beq.n 80052da <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80052d2: 6878 ldr r0, [r7, #4]
80052d4: f000 f972 bl 80055bc <HAL_TIM_IC_CaptureCallback>
80052d8: e005 b.n 80052e6 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80052da: 6878 ldr r0, [r7, #4]
80052dc: f000 f965 bl 80055aa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80052e0: 6878 ldr r0, [r7, #4]
80052e2: f000 f974 bl 80055ce <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80052e6: 687b ldr r3, [r7, #4]
80052e8: 2200 movs r2, #0
80052ea: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80052ec: 68bb ldr r3, [r7, #8]
80052ee: f003 0308 and.w r3, r3, #8
80052f2: 2b00 cmp r3, #0
80052f4: d020 beq.n 8005338 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80052f6: 68fb ldr r3, [r7, #12]
80052f8: f003 0308 and.w r3, r3, #8
80052fc: 2b00 cmp r3, #0
80052fe: d01b beq.n 8005338 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8005300: 687b ldr r3, [r7, #4]
8005302: 681b ldr r3, [r3, #0]
8005304: f06f 0208 mvn.w r2, #8
8005308: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
800530a: 687b ldr r3, [r7, #4]
800530c: 2204 movs r2, #4
800530e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8005310: 687b ldr r3, [r7, #4]
8005312: 681b ldr r3, [r3, #0]
8005314: 69db ldr r3, [r3, #28]
8005316: f003 0303 and.w r3, r3, #3
800531a: 2b00 cmp r3, #0
800531c: d003 beq.n 8005326 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800531e: 6878 ldr r0, [r7, #4]
8005320: f000 f94c bl 80055bc <HAL_TIM_IC_CaptureCallback>
8005324: e005 b.n 8005332 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005326: 6878 ldr r0, [r7, #4]
8005328: f000 f93f bl 80055aa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800532c: 6878 ldr r0, [r7, #4]
800532e: f000 f94e bl 80055ce <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005332: 687b ldr r3, [r7, #4]
8005334: 2200 movs r2, #0
8005336: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8005338: 68bb ldr r3, [r7, #8]
800533a: f003 0310 and.w r3, r3, #16
800533e: 2b00 cmp r3, #0
8005340: d020 beq.n 8005384 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8005342: 68fb ldr r3, [r7, #12]
8005344: f003 0310 and.w r3, r3, #16
8005348: 2b00 cmp r3, #0
800534a: d01b beq.n 8005384 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800534c: 687b ldr r3, [r7, #4]
800534e: 681b ldr r3, [r3, #0]
8005350: f06f 0210 mvn.w r2, #16
8005354: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8005356: 687b ldr r3, [r7, #4]
8005358: 2208 movs r2, #8
800535a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800535c: 687b ldr r3, [r7, #4]
800535e: 681b ldr r3, [r3, #0]
8005360: 69db ldr r3, [r3, #28]
8005362: f403 7340 and.w r3, r3, #768 @ 0x300
8005366: 2b00 cmp r3, #0
8005368: d003 beq.n 8005372 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800536a: 6878 ldr r0, [r7, #4]
800536c: f000 f926 bl 80055bc <HAL_TIM_IC_CaptureCallback>
8005370: e005 b.n 800537e <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005372: 6878 ldr r0, [r7, #4]
8005374: f000 f919 bl 80055aa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005378: 6878 ldr r0, [r7, #4]
800537a: f000 f928 bl 80055ce <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800537e: 687b ldr r3, [r7, #4]
8005380: 2200 movs r2, #0
8005382: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8005384: 68bb ldr r3, [r7, #8]
8005386: f003 0301 and.w r3, r3, #1
800538a: 2b00 cmp r3, #0
800538c: d00c beq.n 80053a8 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800538e: 68fb ldr r3, [r7, #12]
8005390: f003 0301 and.w r3, r3, #1
8005394: 2b00 cmp r3, #0
8005396: d007 beq.n 80053a8 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8005398: 687b ldr r3, [r7, #4]
800539a: 681b ldr r3, [r3, #0]
800539c: f06f 0201 mvn.w r2, #1
80053a0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80053a2: 6878 ldr r0, [r7, #4]
80053a4: f7fd f8e6 bl 8002574 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
80053a8: 68bb ldr r3, [r7, #8]
80053aa: f003 0380 and.w r3, r3, #128 @ 0x80
80053ae: 2b00 cmp r3, #0
80053b0: d00c beq.n 80053cc <HAL_TIM_IRQHandler+0x190>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80053b2: 68fb ldr r3, [r7, #12]
80053b4: f003 0380 and.w r3, r3, #128 @ 0x80
80053b8: 2b00 cmp r3, #0
80053ba: d007 beq.n 80053cc <HAL_TIM_IRQHandler+0x190>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
80053bc: 687b ldr r3, [r7, #4]
80053be: 681b ldr r3, [r3, #0]
80053c0: f06f 0280 mvn.w r2, #128 @ 0x80
80053c4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80053c6: 6878 ldr r0, [r7, #4]
80053c8: f000 fa7f bl 80058ca <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80053cc: 68bb ldr r3, [r7, #8]
80053ce: f003 0340 and.w r3, r3, #64 @ 0x40
80053d2: 2b00 cmp r3, #0
80053d4: d00c beq.n 80053f0 <HAL_TIM_IRQHandler+0x1b4>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80053d6: 68fb ldr r3, [r7, #12]
80053d8: f003 0340 and.w r3, r3, #64 @ 0x40
80053dc: 2b00 cmp r3, #0
80053de: d007 beq.n 80053f0 <HAL_TIM_IRQHandler+0x1b4>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80053e0: 687b ldr r3, [r7, #4]
80053e2: 681b ldr r3, [r3, #0]
80053e4: f06f 0240 mvn.w r2, #64 @ 0x40
80053e8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80053ea: 6878 ldr r0, [r7, #4]
80053ec: f000 f8f8 bl 80055e0 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80053f0: 68bb ldr r3, [r7, #8]
80053f2: f003 0320 and.w r3, r3, #32
80053f6: 2b00 cmp r3, #0
80053f8: d00c beq.n 8005414 <HAL_TIM_IRQHandler+0x1d8>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80053fa: 68fb ldr r3, [r7, #12]
80053fc: f003 0320 and.w r3, r3, #32
8005400: 2b00 cmp r3, #0
8005402: d007 beq.n 8005414 <HAL_TIM_IRQHandler+0x1d8>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8005404: 687b ldr r3, [r7, #4]
8005406: 681b ldr r3, [r3, #0]
8005408: f06f 0220 mvn.w r2, #32
800540c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
800540e: 6878 ldr r0, [r7, #4]
8005410: f000 fa52 bl 80058b8 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8005414: bf00 nop
8005416: 3710 adds r7, #16
8005418: 46bd mov sp, r7
800541a: bd80 pop {r7, pc}
0800541c <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800541c: b580 push {r7, lr}
800541e: b084 sub sp, #16
8005420: af00 add r7, sp, #0
8005422: 6078 str r0, [r7, #4]
8005424: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8005426: 2300 movs r3, #0
8005428: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800542a: 687b ldr r3, [r7, #4]
800542c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005430: 2b01 cmp r3, #1
8005432: d101 bne.n 8005438 <HAL_TIM_ConfigClockSource+0x1c>
8005434: 2302 movs r3, #2
8005436: e0b4 b.n 80055a2 <HAL_TIM_ConfigClockSource+0x186>
8005438: 687b ldr r3, [r7, #4]
800543a: 2201 movs r2, #1
800543c: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8005440: 687b ldr r3, [r7, #4]
8005442: 2202 movs r2, #2
8005444: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8005448: 687b ldr r3, [r7, #4]
800544a: 681b ldr r3, [r3, #0]
800544c: 689b ldr r3, [r3, #8]
800544e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8005450: 68bb ldr r3, [r7, #8]
8005452: f023 0377 bic.w r3, r3, #119 @ 0x77
8005456: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005458: 68bb ldr r3, [r7, #8]
800545a: f423 437f bic.w r3, r3, #65280 @ 0xff00
800545e: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8005460: 687b ldr r3, [r7, #4]
8005462: 681b ldr r3, [r3, #0]
8005464: 68ba ldr r2, [r7, #8]
8005466: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005468: 683b ldr r3, [r7, #0]
800546a: 681b ldr r3, [r3, #0]
800546c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005470: d03e beq.n 80054f0 <HAL_TIM_ConfigClockSource+0xd4>
8005472: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005476: f200 8087 bhi.w 8005588 <HAL_TIM_ConfigClockSource+0x16c>
800547a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800547e: f000 8086 beq.w 800558e <HAL_TIM_ConfigClockSource+0x172>
8005482: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005486: d87f bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
8005488: 2b70 cmp r3, #112 @ 0x70
800548a: d01a beq.n 80054c2 <HAL_TIM_ConfigClockSource+0xa6>
800548c: 2b70 cmp r3, #112 @ 0x70
800548e: d87b bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
8005490: 2b60 cmp r3, #96 @ 0x60
8005492: d050 beq.n 8005536 <HAL_TIM_ConfigClockSource+0x11a>
8005494: 2b60 cmp r3, #96 @ 0x60
8005496: d877 bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
8005498: 2b50 cmp r3, #80 @ 0x50
800549a: d03c beq.n 8005516 <HAL_TIM_ConfigClockSource+0xfa>
800549c: 2b50 cmp r3, #80 @ 0x50
800549e: d873 bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
80054a0: 2b40 cmp r3, #64 @ 0x40
80054a2: d058 beq.n 8005556 <HAL_TIM_ConfigClockSource+0x13a>
80054a4: 2b40 cmp r3, #64 @ 0x40
80054a6: d86f bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
80054a8: 2b30 cmp r3, #48 @ 0x30
80054aa: d064 beq.n 8005576 <HAL_TIM_ConfigClockSource+0x15a>
80054ac: 2b30 cmp r3, #48 @ 0x30
80054ae: d86b bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
80054b0: 2b20 cmp r3, #32
80054b2: d060 beq.n 8005576 <HAL_TIM_ConfigClockSource+0x15a>
80054b4: 2b20 cmp r3, #32
80054b6: d867 bhi.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
80054b8: 2b00 cmp r3, #0
80054ba: d05c beq.n 8005576 <HAL_TIM_ConfigClockSource+0x15a>
80054bc: 2b10 cmp r3, #16
80054be: d05a beq.n 8005576 <HAL_TIM_ConfigClockSource+0x15a>
80054c0: e062 b.n 8005588 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80054c2: 687b ldr r3, [r7, #4]
80054c4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80054c6: 683b ldr r3, [r7, #0]
80054c8: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80054ca: 683b ldr r3, [r7, #0]
80054cc: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80054ce: 683b ldr r3, [r7, #0]
80054d0: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80054d2: f000 f974 bl 80057be <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80054d6: 687b ldr r3, [r7, #4]
80054d8: 681b ldr r3, [r3, #0]
80054da: 689b ldr r3, [r3, #8]
80054dc: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80054de: 68bb ldr r3, [r7, #8]
80054e0: f043 0377 orr.w r3, r3, #119 @ 0x77
80054e4: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80054e6: 687b ldr r3, [r7, #4]
80054e8: 681b ldr r3, [r3, #0]
80054ea: 68ba ldr r2, [r7, #8]
80054ec: 609a str r2, [r3, #8]
break;
80054ee: e04f b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80054f0: 687b ldr r3, [r7, #4]
80054f2: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80054f4: 683b ldr r3, [r7, #0]
80054f6: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80054f8: 683b ldr r3, [r7, #0]
80054fa: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80054fc: 683b ldr r3, [r7, #0]
80054fe: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8005500: f000 f95d bl 80057be <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8005504: 687b ldr r3, [r7, #4]
8005506: 681b ldr r3, [r3, #0]
8005508: 689a ldr r2, [r3, #8]
800550a: 687b ldr r3, [r7, #4]
800550c: 681b ldr r3, [r3, #0]
800550e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8005512: 609a str r2, [r3, #8]
break;
8005514: e03c b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005516: 687b ldr r3, [r7, #4]
8005518: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800551a: 683b ldr r3, [r7, #0]
800551c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800551e: 683b ldr r3, [r7, #0]
8005520: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005522: 461a mov r2, r3
8005524: f000 f8d4 bl 80056d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8005528: 687b ldr r3, [r7, #4]
800552a: 681b ldr r3, [r3, #0]
800552c: 2150 movs r1, #80 @ 0x50
800552e: 4618 mov r0, r3
8005530: f000 f92b bl 800578a <TIM_ITRx_SetConfig>
break;
8005534: e02c b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8005536: 687b ldr r3, [r7, #4]
8005538: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800553a: 683b ldr r3, [r7, #0]
800553c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800553e: 683b ldr r3, [r7, #0]
8005540: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8005542: 461a mov r2, r3
8005544: f000 f8f2 bl 800572c <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8005548: 687b ldr r3, [r7, #4]
800554a: 681b ldr r3, [r3, #0]
800554c: 2160 movs r1, #96 @ 0x60
800554e: 4618 mov r0, r3
8005550: f000 f91b bl 800578a <TIM_ITRx_SetConfig>
break;
8005554: e01c b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005556: 687b ldr r3, [r7, #4]
8005558: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800555a: 683b ldr r3, [r7, #0]
800555c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800555e: 683b ldr r3, [r7, #0]
8005560: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005562: 461a mov r2, r3
8005564: f000 f8b4 bl 80056d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8005568: 687b ldr r3, [r7, #4]
800556a: 681b ldr r3, [r3, #0]
800556c: 2140 movs r1, #64 @ 0x40
800556e: 4618 mov r0, r3
8005570: f000 f90b bl 800578a <TIM_ITRx_SetConfig>
break;
8005574: e00c b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8005576: 687b ldr r3, [r7, #4]
8005578: 681a ldr r2, [r3, #0]
800557a: 683b ldr r3, [r7, #0]
800557c: 681b ldr r3, [r3, #0]
800557e: 4619 mov r1, r3
8005580: 4610 mov r0, r2
8005582: f000 f902 bl 800578a <TIM_ITRx_SetConfig>
break;
8005586: e003 b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8005588: 2301 movs r3, #1
800558a: 73fb strb r3, [r7, #15]
break;
800558c: e000 b.n 8005590 <HAL_TIM_ConfigClockSource+0x174>
break;
800558e: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8005590: 687b ldr r3, [r7, #4]
8005592: 2201 movs r2, #1
8005594: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005598: 687b ldr r3, [r7, #4]
800559a: 2200 movs r2, #0
800559c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80055a0: 7bfb ldrb r3, [r7, #15]
}
80055a2: 4618 mov r0, r3
80055a4: 3710 adds r7, #16
80055a6: 46bd mov sp, r7
80055a8: bd80 pop {r7, pc}
080055aa <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
80055aa: b480 push {r7}
80055ac: b083 sub sp, #12
80055ae: af00 add r7, sp, #0
80055b0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80055b2: bf00 nop
80055b4: 370c adds r7, #12
80055b6: 46bd mov sp, r7
80055b8: bc80 pop {r7}
80055ba: 4770 bx lr
080055bc <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80055bc: b480 push {r7}
80055be: b083 sub sp, #12
80055c0: af00 add r7, sp, #0
80055c2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80055c4: bf00 nop
80055c6: 370c adds r7, #12
80055c8: 46bd mov sp, r7
80055ca: bc80 pop {r7}
80055cc: 4770 bx lr
080055ce <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80055ce: b480 push {r7}
80055d0: b083 sub sp, #12
80055d2: af00 add r7, sp, #0
80055d4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80055d6: bf00 nop
80055d8: 370c adds r7, #12
80055da: 46bd mov sp, r7
80055dc: bc80 pop {r7}
80055de: 4770 bx lr
080055e0 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
80055e0: b480 push {r7}
80055e2: b083 sub sp, #12
80055e4: af00 add r7, sp, #0
80055e6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80055e8: bf00 nop
80055ea: 370c adds r7, #12
80055ec: 46bd mov sp, r7
80055ee: bc80 pop {r7}
80055f0: 4770 bx lr
...
080055f4 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
80055f4: b480 push {r7}
80055f6: b085 sub sp, #20
80055f8: af00 add r7, sp, #0
80055fa: 6078 str r0, [r7, #4]
80055fc: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80055fe: 687b ldr r3, [r7, #4]
8005600: 681b ldr r3, [r3, #0]
8005602: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8005604: 687b ldr r3, [r7, #4]
8005606: 4a2f ldr r2, [pc, #188] @ (80056c4 <TIM_Base_SetConfig+0xd0>)
8005608: 4293 cmp r3, r2
800560a: d00b beq.n 8005624 <TIM_Base_SetConfig+0x30>
800560c: 687b ldr r3, [r7, #4]
800560e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005612: d007 beq.n 8005624 <TIM_Base_SetConfig+0x30>
8005614: 687b ldr r3, [r7, #4]
8005616: 4a2c ldr r2, [pc, #176] @ (80056c8 <TIM_Base_SetConfig+0xd4>)
8005618: 4293 cmp r3, r2
800561a: d003 beq.n 8005624 <TIM_Base_SetConfig+0x30>
800561c: 687b ldr r3, [r7, #4]
800561e: 4a2b ldr r2, [pc, #172] @ (80056cc <TIM_Base_SetConfig+0xd8>)
8005620: 4293 cmp r3, r2
8005622: d108 bne.n 8005636 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8005624: 68fb ldr r3, [r7, #12]
8005626: f023 0370 bic.w r3, r3, #112 @ 0x70
800562a: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800562c: 683b ldr r3, [r7, #0]
800562e: 685b ldr r3, [r3, #4]
8005630: 68fa ldr r2, [r7, #12]
8005632: 4313 orrs r3, r2
8005634: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8005636: 687b ldr r3, [r7, #4]
8005638: 4a22 ldr r2, [pc, #136] @ (80056c4 <TIM_Base_SetConfig+0xd0>)
800563a: 4293 cmp r3, r2
800563c: d00b beq.n 8005656 <TIM_Base_SetConfig+0x62>
800563e: 687b ldr r3, [r7, #4]
8005640: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005644: d007 beq.n 8005656 <TIM_Base_SetConfig+0x62>
8005646: 687b ldr r3, [r7, #4]
8005648: 4a1f ldr r2, [pc, #124] @ (80056c8 <TIM_Base_SetConfig+0xd4>)
800564a: 4293 cmp r3, r2
800564c: d003 beq.n 8005656 <TIM_Base_SetConfig+0x62>
800564e: 687b ldr r3, [r7, #4]
8005650: 4a1e ldr r2, [pc, #120] @ (80056cc <TIM_Base_SetConfig+0xd8>)
8005652: 4293 cmp r3, r2
8005654: d108 bne.n 8005668 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8005656: 68fb ldr r3, [r7, #12]
8005658: f423 7340 bic.w r3, r3, #768 @ 0x300
800565c: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800565e: 683b ldr r3, [r7, #0]
8005660: 68db ldr r3, [r3, #12]
8005662: 68fa ldr r2, [r7, #12]
8005664: 4313 orrs r3, r2
8005666: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8005668: 68fb ldr r3, [r7, #12]
800566a: f023 0280 bic.w r2, r3, #128 @ 0x80
800566e: 683b ldr r3, [r7, #0]
8005670: 695b ldr r3, [r3, #20]
8005672: 4313 orrs r3, r2
8005674: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8005676: 687b ldr r3, [r7, #4]
8005678: 68fa ldr r2, [r7, #12]
800567a: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800567c: 683b ldr r3, [r7, #0]
800567e: 689a ldr r2, [r3, #8]
8005680: 687b ldr r3, [r7, #4]
8005682: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8005684: 683b ldr r3, [r7, #0]
8005686: 681a ldr r2, [r3, #0]
8005688: 687b ldr r3, [r7, #4]
800568a: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800568c: 687b ldr r3, [r7, #4]
800568e: 4a0d ldr r2, [pc, #52] @ (80056c4 <TIM_Base_SetConfig+0xd0>)
8005690: 4293 cmp r3, r2
8005692: d103 bne.n 800569c <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005694: 683b ldr r3, [r7, #0]
8005696: 691a ldr r2, [r3, #16]
8005698: 687b ldr r3, [r7, #4]
800569a: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800569c: 687b ldr r3, [r7, #4]
800569e: 2201 movs r2, #1
80056a0: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80056a2: 687b ldr r3, [r7, #4]
80056a4: 691b ldr r3, [r3, #16]
80056a6: f003 0301 and.w r3, r3, #1
80056aa: 2b00 cmp r3, #0
80056ac: d005 beq.n 80056ba <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80056ae: 687b ldr r3, [r7, #4]
80056b0: 691b ldr r3, [r3, #16]
80056b2: f023 0201 bic.w r2, r3, #1
80056b6: 687b ldr r3, [r7, #4]
80056b8: 611a str r2, [r3, #16]
}
}
80056ba: bf00 nop
80056bc: 3714 adds r7, #20
80056be: 46bd mov sp, r7
80056c0: bc80 pop {r7}
80056c2: 4770 bx lr
80056c4: 40012c00 .word 0x40012c00
80056c8: 40000400 .word 0x40000400
80056cc: 40000800 .word 0x40000800
080056d0 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80056d0: b480 push {r7}
80056d2: b087 sub sp, #28
80056d4: af00 add r7, sp, #0
80056d6: 60f8 str r0, [r7, #12]
80056d8: 60b9 str r1, [r7, #8]
80056da: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80056dc: 68fb ldr r3, [r7, #12]
80056de: 6a1b ldr r3, [r3, #32]
80056e0: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
80056e2: 68fb ldr r3, [r7, #12]
80056e4: 6a1b ldr r3, [r3, #32]
80056e6: f023 0201 bic.w r2, r3, #1
80056ea: 68fb ldr r3, [r7, #12]
80056ec: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80056ee: 68fb ldr r3, [r7, #12]
80056f0: 699b ldr r3, [r3, #24]
80056f2: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
80056f4: 693b ldr r3, [r7, #16]
80056f6: f023 03f0 bic.w r3, r3, #240 @ 0xf0
80056fa: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
80056fc: 687b ldr r3, [r7, #4]
80056fe: 011b lsls r3, r3, #4
8005700: 693a ldr r2, [r7, #16]
8005702: 4313 orrs r3, r2
8005704: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8005706: 697b ldr r3, [r7, #20]
8005708: f023 030a bic.w r3, r3, #10
800570c: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800570e: 697a ldr r2, [r7, #20]
8005710: 68bb ldr r3, [r7, #8]
8005712: 4313 orrs r3, r2
8005714: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8005716: 68fb ldr r3, [r7, #12]
8005718: 693a ldr r2, [r7, #16]
800571a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800571c: 68fb ldr r3, [r7, #12]
800571e: 697a ldr r2, [r7, #20]
8005720: 621a str r2, [r3, #32]
}
8005722: bf00 nop
8005724: 371c adds r7, #28
8005726: 46bd mov sp, r7
8005728: bc80 pop {r7}
800572a: 4770 bx lr
0800572c <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800572c: b480 push {r7}
800572e: b087 sub sp, #28
8005730: af00 add r7, sp, #0
8005732: 60f8 str r0, [r7, #12]
8005734: 60b9 str r1, [r7, #8]
8005736: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8005738: 68fb ldr r3, [r7, #12]
800573a: 6a1b ldr r3, [r3, #32]
800573c: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
800573e: 68fb ldr r3, [r7, #12]
8005740: 6a1b ldr r3, [r3, #32]
8005742: f023 0210 bic.w r2, r3, #16
8005746: 68fb ldr r3, [r7, #12]
8005748: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800574a: 68fb ldr r3, [r7, #12]
800574c: 699b ldr r3, [r3, #24]
800574e: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8005750: 693b ldr r3, [r7, #16]
8005752: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8005756: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8005758: 687b ldr r3, [r7, #4]
800575a: 031b lsls r3, r3, #12
800575c: 693a ldr r2, [r7, #16]
800575e: 4313 orrs r3, r2
8005760: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8005762: 697b ldr r3, [r7, #20]
8005764: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8005768: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
800576a: 68bb ldr r3, [r7, #8]
800576c: 011b lsls r3, r3, #4
800576e: 697a ldr r2, [r7, #20]
8005770: 4313 orrs r3, r2
8005772: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8005774: 68fb ldr r3, [r7, #12]
8005776: 693a ldr r2, [r7, #16]
8005778: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800577a: 68fb ldr r3, [r7, #12]
800577c: 697a ldr r2, [r7, #20]
800577e: 621a str r2, [r3, #32]
}
8005780: bf00 nop
8005782: 371c adds r7, #28
8005784: 46bd mov sp, r7
8005786: bc80 pop {r7}
8005788: 4770 bx lr
0800578a <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
800578a: b480 push {r7}
800578c: b085 sub sp, #20
800578e: af00 add r7, sp, #0
8005790: 6078 str r0, [r7, #4]
8005792: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8005794: 687b ldr r3, [r7, #4]
8005796: 689b ldr r3, [r3, #8]
8005798: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800579a: 68fb ldr r3, [r7, #12]
800579c: f023 0370 bic.w r3, r3, #112 @ 0x70
80057a0: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80057a2: 683a ldr r2, [r7, #0]
80057a4: 68fb ldr r3, [r7, #12]
80057a6: 4313 orrs r3, r2
80057a8: f043 0307 orr.w r3, r3, #7
80057ac: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80057ae: 687b ldr r3, [r7, #4]
80057b0: 68fa ldr r2, [r7, #12]
80057b2: 609a str r2, [r3, #8]
}
80057b4: bf00 nop
80057b6: 3714 adds r7, #20
80057b8: 46bd mov sp, r7
80057ba: bc80 pop {r7}
80057bc: 4770 bx lr
080057be <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80057be: b480 push {r7}
80057c0: b087 sub sp, #28
80057c2: af00 add r7, sp, #0
80057c4: 60f8 str r0, [r7, #12]
80057c6: 60b9 str r1, [r7, #8]
80057c8: 607a str r2, [r7, #4]
80057ca: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
80057cc: 68fb ldr r3, [r7, #12]
80057ce: 689b ldr r3, [r3, #8]
80057d0: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80057d2: 697b ldr r3, [r7, #20]
80057d4: f423 437f bic.w r3, r3, #65280 @ 0xff00
80057d8: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
80057da: 683b ldr r3, [r7, #0]
80057dc: 021a lsls r2, r3, #8
80057de: 687b ldr r3, [r7, #4]
80057e0: 431a orrs r2, r3
80057e2: 68bb ldr r3, [r7, #8]
80057e4: 4313 orrs r3, r2
80057e6: 697a ldr r2, [r7, #20]
80057e8: 4313 orrs r3, r2
80057ea: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80057ec: 68fb ldr r3, [r7, #12]
80057ee: 697a ldr r2, [r7, #20]
80057f0: 609a str r2, [r3, #8]
}
80057f2: bf00 nop
80057f4: 371c adds r7, #28
80057f6: 46bd mov sp, r7
80057f8: bc80 pop {r7}
80057fa: 4770 bx lr
080057fc <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80057fc: b480 push {r7}
80057fe: b085 sub sp, #20
8005800: af00 add r7, sp, #0
8005802: 6078 str r0, [r7, #4]
8005804: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005806: 687b ldr r3, [r7, #4]
8005808: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800580c: 2b01 cmp r3, #1
800580e: d101 bne.n 8005814 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8005810: 2302 movs r3, #2
8005812: e046 b.n 80058a2 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8005814: 687b ldr r3, [r7, #4]
8005816: 2201 movs r2, #1
8005818: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800581c: 687b ldr r3, [r7, #4]
800581e: 2202 movs r2, #2
8005820: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005824: 687b ldr r3, [r7, #4]
8005826: 681b ldr r3, [r3, #0]
8005828: 685b ldr r3, [r3, #4]
800582a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800582c: 687b ldr r3, [r7, #4]
800582e: 681b ldr r3, [r3, #0]
8005830: 689b ldr r3, [r3, #8]
8005832: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005834: 68fb ldr r3, [r7, #12]
8005836: f023 0370 bic.w r3, r3, #112 @ 0x70
800583a: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800583c: 683b ldr r3, [r7, #0]
800583e: 681b ldr r3, [r3, #0]
8005840: 68fa ldr r2, [r7, #12]
8005842: 4313 orrs r3, r2
8005844: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8005846: 687b ldr r3, [r7, #4]
8005848: 681b ldr r3, [r3, #0]
800584a: 68fa ldr r2, [r7, #12]
800584c: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800584e: 687b ldr r3, [r7, #4]
8005850: 681b ldr r3, [r3, #0]
8005852: 4a16 ldr r2, [pc, #88] @ (80058ac <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8005854: 4293 cmp r3, r2
8005856: d00e beq.n 8005876 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8005858: 687b ldr r3, [r7, #4]
800585a: 681b ldr r3, [r3, #0]
800585c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005860: d009 beq.n 8005876 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8005862: 687b ldr r3, [r7, #4]
8005864: 681b ldr r3, [r3, #0]
8005866: 4a12 ldr r2, [pc, #72] @ (80058b0 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8005868: 4293 cmp r3, r2
800586a: d004 beq.n 8005876 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
800586c: 687b ldr r3, [r7, #4]
800586e: 681b ldr r3, [r3, #0]
8005870: 4a10 ldr r2, [pc, #64] @ (80058b4 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8005872: 4293 cmp r3, r2
8005874: d10c bne.n 8005890 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005876: 68bb ldr r3, [r7, #8]
8005878: f023 0380 bic.w r3, r3, #128 @ 0x80
800587c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800587e: 683b ldr r3, [r7, #0]
8005880: 685b ldr r3, [r3, #4]
8005882: 68ba ldr r2, [r7, #8]
8005884: 4313 orrs r3, r2
8005886: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005888: 687b ldr r3, [r7, #4]
800588a: 681b ldr r3, [r3, #0]
800588c: 68ba ldr r2, [r7, #8]
800588e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005890: 687b ldr r3, [r7, #4]
8005892: 2201 movs r2, #1
8005894: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005898: 687b ldr r3, [r7, #4]
800589a: 2200 movs r2, #0
800589c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80058a0: 2300 movs r3, #0
}
80058a2: 4618 mov r0, r3
80058a4: 3714 adds r7, #20
80058a6: 46bd mov sp, r7
80058a8: bc80 pop {r7}
80058aa: 4770 bx lr
80058ac: 40012c00 .word 0x40012c00
80058b0: 40000400 .word 0x40000400
80058b4: 40000800 .word 0x40000800
080058b8 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
80058b8: b480 push {r7}
80058ba: b083 sub sp, #12
80058bc: af00 add r7, sp, #0
80058be: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80058c0: bf00 nop
80058c2: 370c adds r7, #12
80058c4: 46bd mov sp, r7
80058c6: bc80 pop {r7}
80058c8: 4770 bx lr
080058ca <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80058ca: b480 push {r7}
80058cc: b083 sub sp, #12
80058ce: af00 add r7, sp, #0
80058d0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80058d2: bf00 nop
80058d4: 370c adds r7, #12
80058d6: 46bd mov sp, r7
80058d8: bc80 pop {r7}
80058da: 4770 bx lr
080058dc <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80058dc: b580 push {r7, lr}
80058de: b082 sub sp, #8
80058e0: af00 add r7, sp, #0
80058e2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80058e4: 687b ldr r3, [r7, #4]
80058e6: 2b00 cmp r3, #0
80058e8: d101 bne.n 80058ee <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80058ea: 2301 movs r3, #1
80058ec: e042 b.n 8005974 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
80058ee: 687b ldr r3, [r7, #4]
80058f0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80058f4: b2db uxtb r3, r3
80058f6: 2b00 cmp r3, #0
80058f8: d106 bne.n 8005908 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80058fa: 687b ldr r3, [r7, #4]
80058fc: 2200 movs r2, #0
80058fe: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005902: 6878 ldr r0, [r7, #4]
8005904: f7fd f85e bl 80029c4 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8005908: 687b ldr r3, [r7, #4]
800590a: 2224 movs r2, #36 @ 0x24
800590c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8005910: 687b ldr r3, [r7, #4]
8005912: 681b ldr r3, [r3, #0]
8005914: 68da ldr r2, [r3, #12]
8005916: 687b ldr r3, [r7, #4]
8005918: 681b ldr r3, [r3, #0]
800591a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800591e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8005920: 6878 ldr r0, [r7, #4]
8005922: f000 fd63 bl 80063ec <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005926: 687b ldr r3, [r7, #4]
8005928: 681b ldr r3, [r3, #0]
800592a: 691a ldr r2, [r3, #16]
800592c: 687b ldr r3, [r7, #4]
800592e: 681b ldr r3, [r3, #0]
8005930: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005934: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005936: 687b ldr r3, [r7, #4]
8005938: 681b ldr r3, [r3, #0]
800593a: 695a ldr r2, [r3, #20]
800593c: 687b ldr r3, [r7, #4]
800593e: 681b ldr r3, [r3, #0]
8005940: f022 022a bic.w r2, r2, #42 @ 0x2a
8005944: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8005946: 687b ldr r3, [r7, #4]
8005948: 681b ldr r3, [r3, #0]
800594a: 68da ldr r2, [r3, #12]
800594c: 687b ldr r3, [r7, #4]
800594e: 681b ldr r3, [r3, #0]
8005950: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8005954: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005956: 687b ldr r3, [r7, #4]
8005958: 2200 movs r2, #0
800595a: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
800595c: 687b ldr r3, [r7, #4]
800595e: 2220 movs r2, #32
8005960: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8005964: 687b ldr r3, [r7, #4]
8005966: 2220 movs r2, #32
8005968: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
800596c: 687b ldr r3, [r7, #4]
800596e: 2200 movs r2, #0
8005970: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8005972: 2300 movs r3, #0
}
8005974: 4618 mov r0, r3
8005976: 3708 adds r7, #8
8005978: 46bd mov sp, r7
800597a: bd80 pop {r7, pc}
0800597c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800597c: b580 push {r7, lr}
800597e: b08a sub sp, #40 @ 0x28
8005980: af02 add r7, sp, #8
8005982: 60f8 str r0, [r7, #12]
8005984: 60b9 str r1, [r7, #8]
8005986: 603b str r3, [r7, #0]
8005988: 4613 mov r3, r2
800598a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
800598c: 2300 movs r3, #0
800598e: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8005990: 68fb ldr r3, [r7, #12]
8005992: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005996: b2db uxtb r3, r3
8005998: 2b20 cmp r3, #32
800599a: d175 bne.n 8005a88 <HAL_UART_Transmit+0x10c>
{
if ((pData == NULL) || (Size == 0U))
800599c: 68bb ldr r3, [r7, #8]
800599e: 2b00 cmp r3, #0
80059a0: d002 beq.n 80059a8 <HAL_UART_Transmit+0x2c>
80059a2: 88fb ldrh r3, [r7, #6]
80059a4: 2b00 cmp r3, #0
80059a6: d101 bne.n 80059ac <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
80059a8: 2301 movs r3, #1
80059aa: e06e b.n 8005a8a <HAL_UART_Transmit+0x10e>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
80059ac: 68fb ldr r3, [r7, #12]
80059ae: 2200 movs r2, #0
80059b0: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_BUSY_TX;
80059b2: 68fb ldr r3, [r7, #12]
80059b4: 2221 movs r2, #33 @ 0x21
80059b6: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80059ba: f7fd f8d5 bl 8002b68 <HAL_GetTick>
80059be: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80059c0: 68fb ldr r3, [r7, #12]
80059c2: 88fa ldrh r2, [r7, #6]
80059c4: 849a strh r2, [r3, #36] @ 0x24
huart->TxXferCount = Size;
80059c6: 68fb ldr r3, [r7, #12]
80059c8: 88fa ldrh r2, [r7, #6]
80059ca: 84da strh r2, [r3, #38] @ 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80059cc: 68fb ldr r3, [r7, #12]
80059ce: 689b ldr r3, [r3, #8]
80059d0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80059d4: d108 bne.n 80059e8 <HAL_UART_Transmit+0x6c>
80059d6: 68fb ldr r3, [r7, #12]
80059d8: 691b ldr r3, [r3, #16]
80059da: 2b00 cmp r3, #0
80059dc: d104 bne.n 80059e8 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
80059de: 2300 movs r3, #0
80059e0: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
80059e2: 68bb ldr r3, [r7, #8]
80059e4: 61bb str r3, [r7, #24]
80059e6: e003 b.n 80059f0 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
80059e8: 68bb ldr r3, [r7, #8]
80059ea: 61fb str r3, [r7, #28]
pdata16bits = NULL;
80059ec: 2300 movs r3, #0
80059ee: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
80059f0: e02e b.n 8005a50 <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80059f2: 683b ldr r3, [r7, #0]
80059f4: 9300 str r3, [sp, #0]
80059f6: 697b ldr r3, [r7, #20]
80059f8: 2200 movs r2, #0
80059fa: 2180 movs r1, #128 @ 0x80
80059fc: 68f8 ldr r0, [r7, #12]
80059fe: f000 fb01 bl 8006004 <UART_WaitOnFlagUntilTimeout>
8005a02: 4603 mov r3, r0
8005a04: 2b00 cmp r3, #0
8005a06: d005 beq.n 8005a14 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8005a08: 68fb ldr r3, [r7, #12]
8005a0a: 2220 movs r2, #32
8005a0c: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005a10: 2303 movs r3, #3
8005a12: e03a b.n 8005a8a <HAL_UART_Transmit+0x10e>
}
if (pdata8bits == NULL)
8005a14: 69fb ldr r3, [r7, #28]
8005a16: 2b00 cmp r3, #0
8005a18: d10b bne.n 8005a32 <HAL_UART_Transmit+0xb6>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8005a1a: 69bb ldr r3, [r7, #24]
8005a1c: 881b ldrh r3, [r3, #0]
8005a1e: 461a mov r2, r3
8005a20: 68fb ldr r3, [r7, #12]
8005a22: 681b ldr r3, [r3, #0]
8005a24: f3c2 0208 ubfx r2, r2, #0, #9
8005a28: 605a str r2, [r3, #4]
pdata16bits++;
8005a2a: 69bb ldr r3, [r7, #24]
8005a2c: 3302 adds r3, #2
8005a2e: 61bb str r3, [r7, #24]
8005a30: e007 b.n 8005a42 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8005a32: 69fb ldr r3, [r7, #28]
8005a34: 781a ldrb r2, [r3, #0]
8005a36: 68fb ldr r3, [r7, #12]
8005a38: 681b ldr r3, [r3, #0]
8005a3a: 605a str r2, [r3, #4]
pdata8bits++;
8005a3c: 69fb ldr r3, [r7, #28]
8005a3e: 3301 adds r3, #1
8005a40: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8005a42: 68fb ldr r3, [r7, #12]
8005a44: 8cdb ldrh r3, [r3, #38] @ 0x26
8005a46: b29b uxth r3, r3
8005a48: 3b01 subs r3, #1
8005a4a: b29a uxth r2, r3
8005a4c: 68fb ldr r3, [r7, #12]
8005a4e: 84da strh r2, [r3, #38] @ 0x26
while (huart->TxXferCount > 0U)
8005a50: 68fb ldr r3, [r7, #12]
8005a52: 8cdb ldrh r3, [r3, #38] @ 0x26
8005a54: b29b uxth r3, r3
8005a56: 2b00 cmp r3, #0
8005a58: d1cb bne.n 80059f2 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8005a5a: 683b ldr r3, [r7, #0]
8005a5c: 9300 str r3, [sp, #0]
8005a5e: 697b ldr r3, [r7, #20]
8005a60: 2200 movs r2, #0
8005a62: 2140 movs r1, #64 @ 0x40
8005a64: 68f8 ldr r0, [r7, #12]
8005a66: f000 facd bl 8006004 <UART_WaitOnFlagUntilTimeout>
8005a6a: 4603 mov r3, r0
8005a6c: 2b00 cmp r3, #0
8005a6e: d005 beq.n 8005a7c <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8005a70: 68fb ldr r3, [r7, #12]
8005a72: 2220 movs r2, #32
8005a74: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005a78: 2303 movs r3, #3
8005a7a: e006 b.n 8005a8a <HAL_UART_Transmit+0x10e>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8005a7c: 68fb ldr r3, [r7, #12]
8005a7e: 2220 movs r2, #32
8005a80: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_OK;
8005a84: 2300 movs r3, #0
8005a86: e000 b.n 8005a8a <HAL_UART_Transmit+0x10e>
}
else
{
return HAL_BUSY;
8005a88: 2302 movs r3, #2
}
}
8005a8a: 4618 mov r0, r3
8005a8c: 3720 adds r7, #32
8005a8e: 46bd mov sp, r7
8005a90: bd80 pop {r7, pc}
...
08005a94 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8005a94: b580 push {r7, lr}
8005a96: b0ba sub sp, #232 @ 0xe8
8005a98: af00 add r7, sp, #0
8005a9a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
8005a9c: 687b ldr r3, [r7, #4]
8005a9e: 681b ldr r3, [r3, #0]
8005aa0: 681b ldr r3, [r3, #0]
8005aa2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8005aa6: 687b ldr r3, [r7, #4]
8005aa8: 681b ldr r3, [r3, #0]
8005aaa: 68db ldr r3, [r3, #12]
8005aac: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8005ab0: 687b ldr r3, [r7, #4]
8005ab2: 681b ldr r3, [r3, #0]
8005ab4: 695b ldr r3, [r3, #20]
8005ab6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags = 0x00U;
8005aba: 2300 movs r3, #0
8005abc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
uint32_t dmarequest = 0x00U;
8005ac0: 2300 movs r3, #0
8005ac2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
8005ac6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005aca: f003 030f and.w r3, r3, #15
8005ace: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == RESET)
8005ad2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005ad6: 2b00 cmp r3, #0
8005ad8: d10f bne.n 8005afa <HAL_UART_IRQHandler+0x66>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8005ada: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005ade: f003 0320 and.w r3, r3, #32
8005ae2: 2b00 cmp r3, #0
8005ae4: d009 beq.n 8005afa <HAL_UART_IRQHandler+0x66>
8005ae6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005aea: f003 0320 and.w r3, r3, #32
8005aee: 2b00 cmp r3, #0
8005af0: d003 beq.n 8005afa <HAL_UART_IRQHandler+0x66>
{
UART_Receive_IT(huart);
8005af2: 6878 ldr r0, [r7, #4]
8005af4: f000 fbbc bl 8006270 <UART_Receive_IT>
return;
8005af8: e25b b.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
8005afa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005afe: 2b00 cmp r3, #0
8005b00: f000 80de beq.w 8005cc0 <HAL_UART_IRQHandler+0x22c>
8005b04: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005b08: f003 0301 and.w r3, r3, #1
8005b0c: 2b00 cmp r3, #0
8005b0e: d106 bne.n 8005b1e <HAL_UART_IRQHandler+0x8a>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8005b10: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005b14: f403 7390 and.w r3, r3, #288 @ 0x120
8005b18: 2b00 cmp r3, #0
8005b1a: f000 80d1 beq.w 8005cc0 <HAL_UART_IRQHandler+0x22c>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
8005b1e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b22: f003 0301 and.w r3, r3, #1
8005b26: 2b00 cmp r3, #0
8005b28: d00b beq.n 8005b42 <HAL_UART_IRQHandler+0xae>
8005b2a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005b2e: f403 7380 and.w r3, r3, #256 @ 0x100
8005b32: 2b00 cmp r3, #0
8005b34: d005 beq.n 8005b42 <HAL_UART_IRQHandler+0xae>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
8005b36: 687b ldr r3, [r7, #4]
8005b38: 6c5b ldr r3, [r3, #68] @ 0x44
8005b3a: f043 0201 orr.w r2, r3, #1
8005b3e: 687b ldr r3, [r7, #4]
8005b40: 645a str r2, [r3, #68] @ 0x44
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005b42: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b46: f003 0304 and.w r3, r3, #4
8005b4a: 2b00 cmp r3, #0
8005b4c: d00b beq.n 8005b66 <HAL_UART_IRQHandler+0xd2>
8005b4e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005b52: f003 0301 and.w r3, r3, #1
8005b56: 2b00 cmp r3, #0
8005b58: d005 beq.n 8005b66 <HAL_UART_IRQHandler+0xd2>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
8005b5a: 687b ldr r3, [r7, #4]
8005b5c: 6c5b ldr r3, [r3, #68] @ 0x44
8005b5e: f043 0202 orr.w r2, r3, #2
8005b62: 687b ldr r3, [r7, #4]
8005b64: 645a str r2, [r3, #68] @ 0x44
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005b66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b6a: f003 0302 and.w r3, r3, #2
8005b6e: 2b00 cmp r3, #0
8005b70: d00b beq.n 8005b8a <HAL_UART_IRQHandler+0xf6>
8005b72: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005b76: f003 0301 and.w r3, r3, #1
8005b7a: 2b00 cmp r3, #0
8005b7c: d005 beq.n 8005b8a <HAL_UART_IRQHandler+0xf6>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 6c5b ldr r3, [r3, #68] @ 0x44
8005b82: f043 0204 orr.w r2, r3, #4
8005b86: 687b ldr r3, [r7, #4]
8005b88: 645a str r2, [r3, #68] @ 0x44
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
8005b8a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b8e: f003 0308 and.w r3, r3, #8
8005b92: 2b00 cmp r3, #0
8005b94: d011 beq.n 8005bba <HAL_UART_IRQHandler+0x126>
8005b96: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005b9a: f003 0320 and.w r3, r3, #32
8005b9e: 2b00 cmp r3, #0
8005ba0: d105 bne.n 8005bae <HAL_UART_IRQHandler+0x11a>
|| ((cr3its & USART_CR3_EIE) != RESET)))
8005ba2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005ba6: f003 0301 and.w r3, r3, #1
8005baa: 2b00 cmp r3, #0
8005bac: d005 beq.n 8005bba <HAL_UART_IRQHandler+0x126>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8005bae: 687b ldr r3, [r7, #4]
8005bb0: 6c5b ldr r3, [r3, #68] @ 0x44
8005bb2: f043 0208 orr.w r2, r3, #8
8005bb6: 687b ldr r3, [r7, #4]
8005bb8: 645a str r2, [r3, #68] @ 0x44
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8005bba: 687b ldr r3, [r7, #4]
8005bbc: 6c5b ldr r3, [r3, #68] @ 0x44
8005bbe: 2b00 cmp r3, #0
8005bc0: f000 81f2 beq.w 8005fa8 <HAL_UART_IRQHandler+0x514>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8005bc4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005bc8: f003 0320 and.w r3, r3, #32
8005bcc: 2b00 cmp r3, #0
8005bce: d008 beq.n 8005be2 <HAL_UART_IRQHandler+0x14e>
8005bd0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005bd4: f003 0320 and.w r3, r3, #32
8005bd8: 2b00 cmp r3, #0
8005bda: d002 beq.n 8005be2 <HAL_UART_IRQHandler+0x14e>
{
UART_Receive_IT(huart);
8005bdc: 6878 ldr r0, [r7, #4]
8005bde: f000 fb47 bl 8006270 <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
8005be2: 687b ldr r3, [r7, #4]
8005be4: 681b ldr r3, [r3, #0]
8005be6: 695b ldr r3, [r3, #20]
8005be8: f003 0340 and.w r3, r3, #64 @ 0x40
8005bec: 2b00 cmp r3, #0
8005bee: bf14 ite ne
8005bf0: 2301 movne r3, #1
8005bf2: 2300 moveq r3, #0
8005bf4: b2db uxtb r3, r3
8005bf6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
8005bfa: 687b ldr r3, [r7, #4]
8005bfc: 6c5b ldr r3, [r3, #68] @ 0x44
8005bfe: f003 0308 and.w r3, r3, #8
8005c02: 2b00 cmp r3, #0
8005c04: d103 bne.n 8005c0e <HAL_UART_IRQHandler+0x17a>
8005c06: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8005c0a: 2b00 cmp r3, #0
8005c0c: d04f beq.n 8005cae <HAL_UART_IRQHandler+0x21a>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8005c0e: 6878 ldr r0, [r7, #4]
8005c10: f000 fa51 bl 80060b6 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c14: 687b ldr r3, [r7, #4]
8005c16: 681b ldr r3, [r3, #0]
8005c18: 695b ldr r3, [r3, #20]
8005c1a: f003 0340 and.w r3, r3, #64 @ 0x40
8005c1e: 2b00 cmp r3, #0
8005c20: d041 beq.n 8005ca6 <HAL_UART_IRQHandler+0x212>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005c22: 687b ldr r3, [r7, #4]
8005c24: 681b ldr r3, [r3, #0]
8005c26: 3314 adds r3, #20
8005c28: f8c7 309c str.w r3, [r7, #156] @ 0x9c
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005c2c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8005c30: e853 3f00 ldrex r3, [r3]
8005c34: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8005c38: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8005c3c: f023 0340 bic.w r3, r3, #64 @ 0x40
8005c40: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8005c44: 687b ldr r3, [r7, #4]
8005c46: 681b ldr r3, [r3, #0]
8005c48: 3314 adds r3, #20
8005c4a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
8005c4e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
8005c52: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005c56: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
8005c5a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
8005c5e: e841 2300 strex r3, r2, [r1]
8005c62: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8005c66: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8005c6a: 2b00 cmp r3, #0
8005c6c: d1d9 bne.n 8005c22 <HAL_UART_IRQHandler+0x18e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8005c6e: 687b ldr r3, [r7, #4]
8005c70: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c72: 2b00 cmp r3, #0
8005c74: d013 beq.n 8005c9e <HAL_UART_IRQHandler+0x20a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8005c76: 687b ldr r3, [r7, #4]
8005c78: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c7a: 4a7e ldr r2, [pc, #504] @ (8005e74 <HAL_UART_IRQHandler+0x3e0>)
8005c7c: 635a str r2, [r3, #52] @ 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8005c7e: 687b ldr r3, [r7, #4]
8005c80: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c82: 4618 mov r0, r3
8005c84: f7fd faf8 bl 8003278 <HAL_DMA_Abort_IT>
8005c88: 4603 mov r3, r0
8005c8a: 2b00 cmp r3, #0
8005c8c: d016 beq.n 8005cbc <HAL_UART_IRQHandler+0x228>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8005c8e: 687b ldr r3, [r7, #4]
8005c90: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c92: 6b5b ldr r3, [r3, #52] @ 0x34
8005c94: 687a ldr r2, [r7, #4]
8005c96: 6bd2 ldr r2, [r2, #60] @ 0x3c
8005c98: 4610 mov r0, r2
8005c9a: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c9c: e00e b.n 8005cbc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005c9e: 6878 ldr r0, [r7, #4]
8005ca0: f000 f99c bl 8005fdc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005ca4: e00a b.n 8005cbc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005ca6: 6878 ldr r0, [r7, #4]
8005ca8: f000 f998 bl 8005fdc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005cac: e006 b.n 8005cbc <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005cae: 6878 ldr r0, [r7, #4]
8005cb0: f000 f994 bl 8005fdc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005cb4: 687b ldr r3, [r7, #4]
8005cb6: 2200 movs r2, #0
8005cb8: 645a str r2, [r3, #68] @ 0x44
}
}
return;
8005cba: e175 b.n 8005fa8 <HAL_UART_IRQHandler+0x514>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005cbc: bf00 nop
return;
8005cbe: e173 b.n 8005fa8 <HAL_UART_IRQHandler+0x514>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005cc0: 687b ldr r3, [r7, #4]
8005cc2: 6b1b ldr r3, [r3, #48] @ 0x30
8005cc4: 2b01 cmp r3, #1
8005cc6: f040 814f bne.w 8005f68 <HAL_UART_IRQHandler+0x4d4>
&& ((isrflags & USART_SR_IDLE) != 0U)
8005cca: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005cce: f003 0310 and.w r3, r3, #16
8005cd2: 2b00 cmp r3, #0
8005cd4: f000 8148 beq.w 8005f68 <HAL_UART_IRQHandler+0x4d4>
&& ((cr1its & USART_SR_IDLE) != 0U))
8005cd8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005cdc: f003 0310 and.w r3, r3, #16
8005ce0: 2b00 cmp r3, #0
8005ce2: f000 8141 beq.w 8005f68 <HAL_UART_IRQHandler+0x4d4>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
8005ce6: 2300 movs r3, #0
8005ce8: 60bb str r3, [r7, #8]
8005cea: 687b ldr r3, [r7, #4]
8005cec: 681b ldr r3, [r3, #0]
8005cee: 681b ldr r3, [r3, #0]
8005cf0: 60bb str r3, [r7, #8]
8005cf2: 687b ldr r3, [r7, #4]
8005cf4: 681b ldr r3, [r3, #0]
8005cf6: 685b ldr r3, [r3, #4]
8005cf8: 60bb str r3, [r7, #8]
8005cfa: 68bb ldr r3, [r7, #8]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005cfc: 687b ldr r3, [r7, #4]
8005cfe: 681b ldr r3, [r3, #0]
8005d00: 695b ldr r3, [r3, #20]
8005d02: f003 0340 and.w r3, r3, #64 @ 0x40
8005d06: 2b00 cmp r3, #0
8005d08: f000 80b6 beq.w 8005e78 <HAL_UART_IRQHandler+0x3e4>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8005d0c: 687b ldr r3, [r7, #4]
8005d0e: 6bdb ldr r3, [r3, #60] @ 0x3c
8005d10: 681b ldr r3, [r3, #0]
8005d12: 685b ldr r3, [r3, #4]
8005d14: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
8005d18: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8005d1c: 2b00 cmp r3, #0
8005d1e: f000 8145 beq.w 8005fac <HAL_UART_IRQHandler+0x518>
&& (nb_remaining_rx_data < huart->RxXferSize))
8005d22: 687b ldr r3, [r7, #4]
8005d24: 8d9b ldrh r3, [r3, #44] @ 0x2c
8005d26: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005d2a: 429a cmp r2, r3
8005d2c: f080 813e bcs.w 8005fac <HAL_UART_IRQHandler+0x518>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8005d30: 687b ldr r3, [r7, #4]
8005d32: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005d36: 85da strh r2, [r3, #46] @ 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8005d38: 687b ldr r3, [r7, #4]
8005d3a: 6bdb ldr r3, [r3, #60] @ 0x3c
8005d3c: 699b ldr r3, [r3, #24]
8005d3e: 2b20 cmp r3, #32
8005d40: f000 8088 beq.w 8005e54 <HAL_UART_IRQHandler+0x3c0>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8005d44: 687b ldr r3, [r7, #4]
8005d46: 681b ldr r3, [r3, #0]
8005d48: 330c adds r3, #12
8005d4a: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d4e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8005d52: e853 3f00 ldrex r3, [r3]
8005d56: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8005d5a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8005d5e: f423 7380 bic.w r3, r3, #256 @ 0x100
8005d62: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8005d66: 687b ldr r3, [r7, #4]
8005d68: 681b ldr r3, [r3, #0]
8005d6a: 330c adds r3, #12
8005d6c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
8005d70: f8c7 2094 str.w r2, [r7, #148] @ 0x94
8005d74: f8c7 3090 str.w r3, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d78: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8005d7c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8005d80: e841 2300 strex r3, r2, [r1]
8005d84: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
8005d88: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005d8c: 2b00 cmp r3, #0
8005d8e: d1d9 bne.n 8005d44 <HAL_UART_IRQHandler+0x2b0>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005d90: 687b ldr r3, [r7, #4]
8005d92: 681b ldr r3, [r3, #0]
8005d94: 3314 adds r3, #20
8005d96: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d98: 6f7b ldr r3, [r7, #116] @ 0x74
8005d9a: e853 3f00 ldrex r3, [r3]
8005d9e: 673b str r3, [r7, #112] @ 0x70
return(result);
8005da0: 6f3b ldr r3, [r7, #112] @ 0x70
8005da2: f023 0301 bic.w r3, r3, #1
8005da6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8005daa: 687b ldr r3, [r7, #4]
8005dac: 681b ldr r3, [r3, #0]
8005dae: 3314 adds r3, #20
8005db0: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8005db4: f8c7 2080 str.w r2, [r7, #128] @ 0x80
8005db8: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005dba: 6ff9 ldr r1, [r7, #124] @ 0x7c
8005dbc: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
8005dc0: e841 2300 strex r3, r2, [r1]
8005dc4: 67bb str r3, [r7, #120] @ 0x78
return(result);
8005dc6: 6fbb ldr r3, [r7, #120] @ 0x78
8005dc8: 2b00 cmp r3, #0
8005dca: d1e1 bne.n 8005d90 <HAL_UART_IRQHandler+0x2fc>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005dcc: 687b ldr r3, [r7, #4]
8005dce: 681b ldr r3, [r3, #0]
8005dd0: 3314 adds r3, #20
8005dd2: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005dd4: 6e3b ldr r3, [r7, #96] @ 0x60
8005dd6: e853 3f00 ldrex r3, [r3]
8005dda: 65fb str r3, [r7, #92] @ 0x5c
return(result);
8005ddc: 6dfb ldr r3, [r7, #92] @ 0x5c
8005dde: f023 0340 bic.w r3, r3, #64 @ 0x40
8005de2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8005de6: 687b ldr r3, [r7, #4]
8005de8: 681b ldr r3, [r3, #0]
8005dea: 3314 adds r3, #20
8005dec: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
8005df0: 66fa str r2, [r7, #108] @ 0x6c
8005df2: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005df4: 6eb9 ldr r1, [r7, #104] @ 0x68
8005df6: 6efa ldr r2, [r7, #108] @ 0x6c
8005df8: e841 2300 strex r3, r2, [r1]
8005dfc: 667b str r3, [r7, #100] @ 0x64
return(result);
8005dfe: 6e7b ldr r3, [r7, #100] @ 0x64
8005e00: 2b00 cmp r3, #0
8005e02: d1e3 bne.n 8005dcc <HAL_UART_IRQHandler+0x338>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005e04: 687b ldr r3, [r7, #4]
8005e06: 2220 movs r2, #32
8005e08: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005e0c: 687b ldr r3, [r7, #4]
8005e0e: 2200 movs r2, #0
8005e10: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005e12: 687b ldr r3, [r7, #4]
8005e14: 681b ldr r3, [r3, #0]
8005e16: 330c adds r3, #12
8005e18: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005e1a: 6cfb ldr r3, [r7, #76] @ 0x4c
8005e1c: e853 3f00 ldrex r3, [r3]
8005e20: 64bb str r3, [r7, #72] @ 0x48
return(result);
8005e22: 6cbb ldr r3, [r7, #72] @ 0x48
8005e24: f023 0310 bic.w r3, r3, #16
8005e28: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8005e2c: 687b ldr r3, [r7, #4]
8005e2e: 681b ldr r3, [r3, #0]
8005e30: 330c adds r3, #12
8005e32: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
8005e36: 65ba str r2, [r7, #88] @ 0x58
8005e38: 657b str r3, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e3a: 6d79 ldr r1, [r7, #84] @ 0x54
8005e3c: 6dba ldr r2, [r7, #88] @ 0x58
8005e3e: e841 2300 strex r3, r2, [r1]
8005e42: 653b str r3, [r7, #80] @ 0x50
return(result);
8005e44: 6d3b ldr r3, [r7, #80] @ 0x50
8005e46: 2b00 cmp r3, #0
8005e48: d1e3 bne.n 8005e12 <HAL_UART_IRQHandler+0x37e>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8005e4a: 687b ldr r3, [r7, #4]
8005e4c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005e4e: 4618 mov r0, r3
8005e50: f7fd f9d7 bl 8003202 <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005e54: 687b ldr r3, [r7, #4]
8005e56: 2202 movs r2, #2
8005e58: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8005e5a: 687b ldr r3, [r7, #4]
8005e5c: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005e5e: 687b ldr r3, [r7, #4]
8005e60: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005e62: b29b uxth r3, r3
8005e64: 1ad3 subs r3, r2, r3
8005e66: b29b uxth r3, r3
8005e68: 4619 mov r1, r3
8005e6a: 6878 ldr r0, [r7, #4]
8005e6c: f000 f8bf bl 8005fee <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005e70: e09c b.n 8005fac <HAL_UART_IRQHandler+0x518>
8005e72: bf00 nop
8005e74: 0800617b .word 0x0800617b
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8005e78: 687b ldr r3, [r7, #4]
8005e7a: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005e7c: 687b ldr r3, [r7, #4]
8005e7e: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005e80: b29b uxth r3, r3
8005e82: 1ad3 subs r3, r2, r3
8005e84: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8005e88: 687b ldr r3, [r7, #4]
8005e8a: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005e8c: b29b uxth r3, r3
8005e8e: 2b00 cmp r3, #0
8005e90: f000 808e beq.w 8005fb0 <HAL_UART_IRQHandler+0x51c>
&& (nb_rx_data > 0U))
8005e94: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005e98: 2b00 cmp r3, #0
8005e9a: f000 8089 beq.w 8005fb0 <HAL_UART_IRQHandler+0x51c>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005e9e: 687b ldr r3, [r7, #4]
8005ea0: 681b ldr r3, [r3, #0]
8005ea2: 330c adds r3, #12
8005ea4: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005ea6: 6bbb ldr r3, [r7, #56] @ 0x38
8005ea8: e853 3f00 ldrex r3, [r3]
8005eac: 637b str r3, [r7, #52] @ 0x34
return(result);
8005eae: 6b7b ldr r3, [r7, #52] @ 0x34
8005eb0: f423 7390 bic.w r3, r3, #288 @ 0x120
8005eb4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8005eb8: 687b ldr r3, [r7, #4]
8005eba: 681b ldr r3, [r3, #0]
8005ebc: 330c adds r3, #12
8005ebe: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
8005ec2: 647a str r2, [r7, #68] @ 0x44
8005ec4: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005ec6: 6c39 ldr r1, [r7, #64] @ 0x40
8005ec8: 6c7a ldr r2, [r7, #68] @ 0x44
8005eca: e841 2300 strex r3, r2, [r1]
8005ece: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8005ed0: 6bfb ldr r3, [r7, #60] @ 0x3c
8005ed2: 2b00 cmp r3, #0
8005ed4: d1e3 bne.n 8005e9e <HAL_UART_IRQHandler+0x40a>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005ed6: 687b ldr r3, [r7, #4]
8005ed8: 681b ldr r3, [r3, #0]
8005eda: 3314 adds r3, #20
8005edc: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005ede: 6a7b ldr r3, [r7, #36] @ 0x24
8005ee0: e853 3f00 ldrex r3, [r3]
8005ee4: 623b str r3, [r7, #32]
return(result);
8005ee6: 6a3b ldr r3, [r7, #32]
8005ee8: f023 0301 bic.w r3, r3, #1
8005eec: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8005ef0: 687b ldr r3, [r7, #4]
8005ef2: 681b ldr r3, [r3, #0]
8005ef4: 3314 adds r3, #20
8005ef6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8005efa: 633a str r2, [r7, #48] @ 0x30
8005efc: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005efe: 6af9 ldr r1, [r7, #44] @ 0x2c
8005f00: 6b3a ldr r2, [r7, #48] @ 0x30
8005f02: e841 2300 strex r3, r2, [r1]
8005f06: 62bb str r3, [r7, #40] @ 0x28
return(result);
8005f08: 6abb ldr r3, [r7, #40] @ 0x28
8005f0a: 2b00 cmp r3, #0
8005f0c: d1e3 bne.n 8005ed6 <HAL_UART_IRQHandler+0x442>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005f0e: 687b ldr r3, [r7, #4]
8005f10: 2220 movs r2, #32
8005f12: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005f16: 687b ldr r3, [r7, #4]
8005f18: 2200 movs r2, #0
8005f1a: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005f1c: 687b ldr r3, [r7, #4]
8005f1e: 681b ldr r3, [r3, #0]
8005f20: 330c adds r3, #12
8005f22: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005f24: 693b ldr r3, [r7, #16]
8005f26: e853 3f00 ldrex r3, [r3]
8005f2a: 60fb str r3, [r7, #12]
return(result);
8005f2c: 68fb ldr r3, [r7, #12]
8005f2e: f023 0310 bic.w r3, r3, #16
8005f32: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8005f36: 687b ldr r3, [r7, #4]
8005f38: 681b ldr r3, [r3, #0]
8005f3a: 330c adds r3, #12
8005f3c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
8005f40: 61fa str r2, [r7, #28]
8005f42: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005f44: 69b9 ldr r1, [r7, #24]
8005f46: 69fa ldr r2, [r7, #28]
8005f48: e841 2300 strex r3, r2, [r1]
8005f4c: 617b str r3, [r7, #20]
return(result);
8005f4e: 697b ldr r3, [r7, #20]
8005f50: 2b00 cmp r3, #0
8005f52: d1e3 bne.n 8005f1c <HAL_UART_IRQHandler+0x488>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005f54: 687b ldr r3, [r7, #4]
8005f56: 2202 movs r2, #2
8005f58: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8005f5a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005f5e: 4619 mov r1, r3
8005f60: 6878 ldr r0, [r7, #4]
8005f62: f000 f844 bl 8005fee <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005f66: e023 b.n 8005fb0 <HAL_UART_IRQHandler+0x51c>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
8005f68: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005f6c: f003 0380 and.w r3, r3, #128 @ 0x80
8005f70: 2b00 cmp r3, #0
8005f72: d009 beq.n 8005f88 <HAL_UART_IRQHandler+0x4f4>
8005f74: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005f78: f003 0380 and.w r3, r3, #128 @ 0x80
8005f7c: 2b00 cmp r3, #0
8005f7e: d003 beq.n 8005f88 <HAL_UART_IRQHandler+0x4f4>
{
UART_Transmit_IT(huart);
8005f80: 6878 ldr r0, [r7, #4]
8005f82: f000 f90e bl 80061a2 <UART_Transmit_IT>
return;
8005f86: e014 b.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
8005f88: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005f8c: f003 0340 and.w r3, r3, #64 @ 0x40
8005f90: 2b00 cmp r3, #0
8005f92: d00e beq.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
8005f94: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005f98: f003 0340 and.w r3, r3, #64 @ 0x40
8005f9c: 2b00 cmp r3, #0
8005f9e: d008 beq.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
{
UART_EndTransmit_IT(huart);
8005fa0: 6878 ldr r0, [r7, #4]
8005fa2: f000 f94d bl 8006240 <UART_EndTransmit_IT>
return;
8005fa6: e004 b.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
return;
8005fa8: bf00 nop
8005faa: e002 b.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
return;
8005fac: bf00 nop
8005fae: e000 b.n 8005fb2 <HAL_UART_IRQHandler+0x51e>
return;
8005fb0: bf00 nop
}
}
8005fb2: 37e8 adds r7, #232 @ 0xe8
8005fb4: 46bd mov sp, r7
8005fb6: bd80 pop {r7, pc}
08005fb8 <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8005fb8: b480 push {r7}
8005fba: b083 sub sp, #12
8005fbc: af00 add r7, sp, #0
8005fbe: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
8005fc0: bf00 nop
8005fc2: 370c adds r7, #12
8005fc4: 46bd mov sp, r7
8005fc6: bc80 pop {r7}
8005fc8: 4770 bx lr
08005fca <HAL_UART_RxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8005fca: b480 push {r7}
8005fcc: b083 sub sp, #12
8005fce: af00 add r7, sp, #0
8005fd0: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
8005fd2: bf00 nop
8005fd4: 370c adds r7, #12
8005fd6: 46bd mov sp, r7
8005fd8: bc80 pop {r7}
8005fda: 4770 bx lr
08005fdc <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8005fdc: b480 push {r7}
8005fde: b083 sub sp, #12
8005fe0: af00 add r7, sp, #0
8005fe2: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8005fe4: bf00 nop
8005fe6: 370c adds r7, #12
8005fe8: 46bd mov sp, r7
8005fea: bc80 pop {r7}
8005fec: 4770 bx lr
08005fee <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8005fee: b480 push {r7}
8005ff0: b083 sub sp, #12
8005ff2: af00 add r7, sp, #0
8005ff4: 6078 str r0, [r7, #4]
8005ff6: 460b mov r3, r1
8005ff8: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8005ffa: bf00 nop
8005ffc: 370c adds r7, #12
8005ffe: 46bd mov sp, r7
8006000: bc80 pop {r7}
8006002: 4770 bx lr
08006004 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8006004: b580 push {r7, lr}
8006006: b086 sub sp, #24
8006008: af00 add r7, sp, #0
800600a: 60f8 str r0, [r7, #12]
800600c: 60b9 str r1, [r7, #8]
800600e: 603b str r3, [r7, #0]
8006010: 4613 mov r3, r2
8006012: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8006014: e03b b.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8006016: 6a3b ldr r3, [r7, #32]
8006018: f1b3 3fff cmp.w r3, #4294967295
800601c: d037 beq.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800601e: f7fc fda3 bl 8002b68 <HAL_GetTick>
8006022: 4602 mov r2, r0
8006024: 683b ldr r3, [r7, #0]
8006026: 1ad3 subs r3, r2, r3
8006028: 6a3a ldr r2, [r7, #32]
800602a: 429a cmp r2, r3
800602c: d302 bcc.n 8006034 <UART_WaitOnFlagUntilTimeout+0x30>
800602e: 6a3b ldr r3, [r7, #32]
8006030: 2b00 cmp r3, #0
8006032: d101 bne.n 8006038 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8006034: 2303 movs r3, #3
8006036: e03a b.n 80060ae <UART_WaitOnFlagUntilTimeout+0xaa>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8006038: 68fb ldr r3, [r7, #12]
800603a: 681b ldr r3, [r3, #0]
800603c: 68db ldr r3, [r3, #12]
800603e: f003 0304 and.w r3, r3, #4
8006042: 2b00 cmp r3, #0
8006044: d023 beq.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
8006046: 68bb ldr r3, [r7, #8]
8006048: 2b80 cmp r3, #128 @ 0x80
800604a: d020 beq.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
800604c: 68bb ldr r3, [r7, #8]
800604e: 2b40 cmp r3, #64 @ 0x40
8006050: d01d beq.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8006052: 68fb ldr r3, [r7, #12]
8006054: 681b ldr r3, [r3, #0]
8006056: 681b ldr r3, [r3, #0]
8006058: f003 0308 and.w r3, r3, #8
800605c: 2b08 cmp r3, #8
800605e: d116 bne.n 800608e <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_OREFLAG(huart);
8006060: 2300 movs r3, #0
8006062: 617b str r3, [r7, #20]
8006064: 68fb ldr r3, [r7, #12]
8006066: 681b ldr r3, [r3, #0]
8006068: 681b ldr r3, [r3, #0]
800606a: 617b str r3, [r7, #20]
800606c: 68fb ldr r3, [r7, #12]
800606e: 681b ldr r3, [r3, #0]
8006070: 685b ldr r3, [r3, #4]
8006072: 617b str r3, [r7, #20]
8006074: 697b ldr r3, [r7, #20]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8006076: 68f8 ldr r0, [r7, #12]
8006078: f000 f81d bl 80060b6 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
800607c: 68fb ldr r3, [r7, #12]
800607e: 2208 movs r2, #8
8006080: 645a str r2, [r3, #68] @ 0x44
/* Process Unlocked */
__HAL_UNLOCK(huart);
8006082: 68fb ldr r3, [r7, #12]
8006084: 2200 movs r2, #0
8006086: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
800608a: 2301 movs r3, #1
800608c: e00f b.n 80060ae <UART_WaitOnFlagUntilTimeout+0xaa>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800608e: 68fb ldr r3, [r7, #12]
8006090: 681b ldr r3, [r3, #0]
8006092: 681a ldr r2, [r3, #0]
8006094: 68bb ldr r3, [r7, #8]
8006096: 4013 ands r3, r2
8006098: 68ba ldr r2, [r7, #8]
800609a: 429a cmp r2, r3
800609c: bf0c ite eq
800609e: 2301 moveq r3, #1
80060a0: 2300 movne r3, #0
80060a2: b2db uxtb r3, r3
80060a4: 461a mov r2, r3
80060a6: 79fb ldrb r3, [r7, #7]
80060a8: 429a cmp r2, r3
80060aa: d0b4 beq.n 8006016 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80060ac: 2300 movs r3, #0
}
80060ae: 4618 mov r0, r3
80060b0: 3718 adds r7, #24
80060b2: 46bd mov sp, r7
80060b4: bd80 pop {r7, pc}
080060b6 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80060b6: b480 push {r7}
80060b8: b095 sub sp, #84 @ 0x54
80060ba: af00 add r7, sp, #0
80060bc: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80060be: 687b ldr r3, [r7, #4]
80060c0: 681b ldr r3, [r3, #0]
80060c2: 330c adds r3, #12
80060c4: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80060c6: 6b7b ldr r3, [r7, #52] @ 0x34
80060c8: e853 3f00 ldrex r3, [r3]
80060cc: 633b str r3, [r7, #48] @ 0x30
return(result);
80060ce: 6b3b ldr r3, [r7, #48] @ 0x30
80060d0: f423 7390 bic.w r3, r3, #288 @ 0x120
80060d4: 64fb str r3, [r7, #76] @ 0x4c
80060d6: 687b ldr r3, [r7, #4]
80060d8: 681b ldr r3, [r3, #0]
80060da: 330c adds r3, #12
80060dc: 6cfa ldr r2, [r7, #76] @ 0x4c
80060de: 643a str r2, [r7, #64] @ 0x40
80060e0: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80060e2: 6bf9 ldr r1, [r7, #60] @ 0x3c
80060e4: 6c3a ldr r2, [r7, #64] @ 0x40
80060e6: e841 2300 strex r3, r2, [r1]
80060ea: 63bb str r3, [r7, #56] @ 0x38
return(result);
80060ec: 6bbb ldr r3, [r7, #56] @ 0x38
80060ee: 2b00 cmp r3, #0
80060f0: d1e5 bne.n 80060be <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80060f2: 687b ldr r3, [r7, #4]
80060f4: 681b ldr r3, [r3, #0]
80060f6: 3314 adds r3, #20
80060f8: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80060fa: 6a3b ldr r3, [r7, #32]
80060fc: e853 3f00 ldrex r3, [r3]
8006100: 61fb str r3, [r7, #28]
return(result);
8006102: 69fb ldr r3, [r7, #28]
8006104: f023 0301 bic.w r3, r3, #1
8006108: 64bb str r3, [r7, #72] @ 0x48
800610a: 687b ldr r3, [r7, #4]
800610c: 681b ldr r3, [r3, #0]
800610e: 3314 adds r3, #20
8006110: 6cba ldr r2, [r7, #72] @ 0x48
8006112: 62fa str r2, [r7, #44] @ 0x2c
8006114: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006116: 6ab9 ldr r1, [r7, #40] @ 0x28
8006118: 6afa ldr r2, [r7, #44] @ 0x2c
800611a: e841 2300 strex r3, r2, [r1]
800611e: 627b str r3, [r7, #36] @ 0x24
return(result);
8006120: 6a7b ldr r3, [r7, #36] @ 0x24
8006122: 2b00 cmp r3, #0
8006124: d1e5 bne.n 80060f2 <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006126: 687b ldr r3, [r7, #4]
8006128: 6b1b ldr r3, [r3, #48] @ 0x30
800612a: 2b01 cmp r3, #1
800612c: d119 bne.n 8006162 <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800612e: 687b ldr r3, [r7, #4]
8006130: 681b ldr r3, [r3, #0]
8006132: 330c adds r3, #12
8006134: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006136: 68fb ldr r3, [r7, #12]
8006138: e853 3f00 ldrex r3, [r3]
800613c: 60bb str r3, [r7, #8]
return(result);
800613e: 68bb ldr r3, [r7, #8]
8006140: f023 0310 bic.w r3, r3, #16
8006144: 647b str r3, [r7, #68] @ 0x44
8006146: 687b ldr r3, [r7, #4]
8006148: 681b ldr r3, [r3, #0]
800614a: 330c adds r3, #12
800614c: 6c7a ldr r2, [r7, #68] @ 0x44
800614e: 61ba str r2, [r7, #24]
8006150: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006152: 6979 ldr r1, [r7, #20]
8006154: 69ba ldr r2, [r7, #24]
8006156: e841 2300 strex r3, r2, [r1]
800615a: 613b str r3, [r7, #16]
return(result);
800615c: 693b ldr r3, [r7, #16]
800615e: 2b00 cmp r3, #0
8006160: d1e5 bne.n 800612e <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006162: 687b ldr r3, [r7, #4]
8006164: 2220 movs r2, #32
8006166: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800616a: 687b ldr r3, [r7, #4]
800616c: 2200 movs r2, #0
800616e: 631a str r2, [r3, #48] @ 0x30
}
8006170: bf00 nop
8006172: 3754 adds r7, #84 @ 0x54
8006174: 46bd mov sp, r7
8006176: bc80 pop {r7}
8006178: 4770 bx lr
0800617a <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
800617a: b580 push {r7, lr}
800617c: b084 sub sp, #16
800617e: af00 add r7, sp, #0
8006180: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8006182: 687b ldr r3, [r7, #4]
8006184: 6a5b ldr r3, [r3, #36] @ 0x24
8006186: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8006188: 68fb ldr r3, [r7, #12]
800618a: 2200 movs r2, #0
800618c: 85da strh r2, [r3, #46] @ 0x2e
huart->TxXferCount = 0x00U;
800618e: 68fb ldr r3, [r7, #12]
8006190: 2200 movs r2, #0
8006192: 84da strh r2, [r3, #38] @ 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006194: 68f8 ldr r0, [r7, #12]
8006196: f7ff ff21 bl 8005fdc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800619a: bf00 nop
800619c: 3710 adds r7, #16
800619e: 46bd mov sp, r7
80061a0: bd80 pop {r7, pc}
080061a2 <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
80061a2: b480 push {r7}
80061a4: b085 sub sp, #20
80061a6: af00 add r7, sp, #0
80061a8: 6078 str r0, [r7, #4]
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
80061aa: 687b ldr r3, [r7, #4]
80061ac: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80061b0: b2db uxtb r3, r3
80061b2: 2b21 cmp r3, #33 @ 0x21
80061b4: d13e bne.n 8006234 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80061b6: 687b ldr r3, [r7, #4]
80061b8: 689b ldr r3, [r3, #8]
80061ba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80061be: d114 bne.n 80061ea <UART_Transmit_IT+0x48>
80061c0: 687b ldr r3, [r7, #4]
80061c2: 691b ldr r3, [r3, #16]
80061c4: 2b00 cmp r3, #0
80061c6: d110 bne.n 80061ea <UART_Transmit_IT+0x48>
{
tmp = (const uint16_t *) huart->pTxBuffPtr;
80061c8: 687b ldr r3, [r7, #4]
80061ca: 6a1b ldr r3, [r3, #32]
80061cc: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
80061ce: 68fb ldr r3, [r7, #12]
80061d0: 881b ldrh r3, [r3, #0]
80061d2: 461a mov r2, r3
80061d4: 687b ldr r3, [r7, #4]
80061d6: 681b ldr r3, [r3, #0]
80061d8: f3c2 0208 ubfx r2, r2, #0, #9
80061dc: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
80061de: 687b ldr r3, [r7, #4]
80061e0: 6a1b ldr r3, [r3, #32]
80061e2: 1c9a adds r2, r3, #2
80061e4: 687b ldr r3, [r7, #4]
80061e6: 621a str r2, [r3, #32]
80061e8: e008 b.n 80061fc <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
80061ea: 687b ldr r3, [r7, #4]
80061ec: 6a1b ldr r3, [r3, #32]
80061ee: 1c59 adds r1, r3, #1
80061f0: 687a ldr r2, [r7, #4]
80061f2: 6211 str r1, [r2, #32]
80061f4: 781a ldrb r2, [r3, #0]
80061f6: 687b ldr r3, [r7, #4]
80061f8: 681b ldr r3, [r3, #0]
80061fa: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
80061fc: 687b ldr r3, [r7, #4]
80061fe: 8cdb ldrh r3, [r3, #38] @ 0x26
8006200: b29b uxth r3, r3
8006202: 3b01 subs r3, #1
8006204: b29b uxth r3, r3
8006206: 687a ldr r2, [r7, #4]
8006208: 4619 mov r1, r3
800620a: 84d1 strh r1, [r2, #38] @ 0x26
800620c: 2b00 cmp r3, #0
800620e: d10f bne.n 8006230 <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
8006210: 687b ldr r3, [r7, #4]
8006212: 681b ldr r3, [r3, #0]
8006214: 68da ldr r2, [r3, #12]
8006216: 687b ldr r3, [r7, #4]
8006218: 681b ldr r3, [r3, #0]
800621a: f022 0280 bic.w r2, r2, #128 @ 0x80
800621e: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
8006220: 687b ldr r3, [r7, #4]
8006222: 681b ldr r3, [r3, #0]
8006224: 68da ldr r2, [r3, #12]
8006226: 687b ldr r3, [r7, #4]
8006228: 681b ldr r3, [r3, #0]
800622a: f042 0240 orr.w r2, r2, #64 @ 0x40
800622e: 60da str r2, [r3, #12]
}
return HAL_OK;
8006230: 2300 movs r3, #0
8006232: e000 b.n 8006236 <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
8006234: 2302 movs r3, #2
}
}
8006236: 4618 mov r0, r3
8006238: 3714 adds r7, #20
800623a: 46bd mov sp, r7
800623c: bc80 pop {r7}
800623e: 4770 bx lr
08006240 <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8006240: b580 push {r7, lr}
8006242: b082 sub sp, #8
8006244: af00 add r7, sp, #0
8006246: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
8006248: 687b ldr r3, [r7, #4]
800624a: 681b ldr r3, [r3, #0]
800624c: 68da ldr r2, [r3, #12]
800624e: 687b ldr r3, [r7, #4]
8006250: 681b ldr r3, [r3, #0]
8006252: f022 0240 bic.w r2, r2, #64 @ 0x40
8006256: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006258: 687b ldr r3, [r7, #4]
800625a: 2220 movs r2, #32
800625c: f883 2041 strb.w r2, [r3, #65] @ 0x41
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8006260: 6878 ldr r0, [r7, #4]
8006262: f7ff fea9 bl 8005fb8 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8006266: 2300 movs r3, #0
}
8006268: 4618 mov r0, r3
800626a: 3708 adds r7, #8
800626c: 46bd mov sp, r7
800626e: bd80 pop {r7, pc}
08006270 <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
8006270: b580 push {r7, lr}
8006272: b08c sub sp, #48 @ 0x30
8006274: af00 add r7, sp, #0
8006276: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006278: 687b ldr r3, [r7, #4]
800627a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800627e: b2db uxtb r3, r3
8006280: 2b22 cmp r3, #34 @ 0x22
8006282: f040 80ae bne.w 80063e2 <UART_Receive_IT+0x172>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8006286: 687b ldr r3, [r7, #4]
8006288: 689b ldr r3, [r3, #8]
800628a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800628e: d117 bne.n 80062c0 <UART_Receive_IT+0x50>
8006290: 687b ldr r3, [r7, #4]
8006292: 691b ldr r3, [r3, #16]
8006294: 2b00 cmp r3, #0
8006296: d113 bne.n 80062c0 <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
8006298: 2300 movs r3, #0
800629a: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
800629c: 687b ldr r3, [r7, #4]
800629e: 6a9b ldr r3, [r3, #40] @ 0x28
80062a0: 62bb str r3, [r7, #40] @ 0x28
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
80062a2: 687b ldr r3, [r7, #4]
80062a4: 681b ldr r3, [r3, #0]
80062a6: 685b ldr r3, [r3, #4]
80062a8: b29b uxth r3, r3
80062aa: f3c3 0308 ubfx r3, r3, #0, #9
80062ae: b29a uxth r2, r3
80062b0: 6abb ldr r3, [r7, #40] @ 0x28
80062b2: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
80062b4: 687b ldr r3, [r7, #4]
80062b6: 6a9b ldr r3, [r3, #40] @ 0x28
80062b8: 1c9a adds r2, r3, #2
80062ba: 687b ldr r3, [r7, #4]
80062bc: 629a str r2, [r3, #40] @ 0x28
80062be: e026 b.n 800630e <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
80062c0: 687b ldr r3, [r7, #4]
80062c2: 6a9b ldr r3, [r3, #40] @ 0x28
80062c4: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = NULL;
80062c6: 2300 movs r3, #0
80062c8: 62bb str r3, [r7, #40] @ 0x28
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80062ca: 687b ldr r3, [r7, #4]
80062cc: 689b ldr r3, [r3, #8]
80062ce: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80062d2: d007 beq.n 80062e4 <UART_Receive_IT+0x74>
80062d4: 687b ldr r3, [r7, #4]
80062d6: 689b ldr r3, [r3, #8]
80062d8: 2b00 cmp r3, #0
80062da: d10a bne.n 80062f2 <UART_Receive_IT+0x82>
80062dc: 687b ldr r3, [r7, #4]
80062de: 691b ldr r3, [r3, #16]
80062e0: 2b00 cmp r3, #0
80062e2: d106 bne.n 80062f2 <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80062e4: 687b ldr r3, [r7, #4]
80062e6: 681b ldr r3, [r3, #0]
80062e8: 685b ldr r3, [r3, #4]
80062ea: b2da uxtb r2, r3
80062ec: 6afb ldr r3, [r7, #44] @ 0x2c
80062ee: 701a strb r2, [r3, #0]
80062f0: e008 b.n 8006304 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
80062f2: 687b ldr r3, [r7, #4]
80062f4: 681b ldr r3, [r3, #0]
80062f6: 685b ldr r3, [r3, #4]
80062f8: b2db uxtb r3, r3
80062fa: f003 037f and.w r3, r3, #127 @ 0x7f
80062fe: b2da uxtb r2, r3
8006300: 6afb ldr r3, [r7, #44] @ 0x2c
8006302: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
8006304: 687b ldr r3, [r7, #4]
8006306: 6a9b ldr r3, [r3, #40] @ 0x28
8006308: 1c5a adds r2, r3, #1
800630a: 687b ldr r3, [r7, #4]
800630c: 629a str r2, [r3, #40] @ 0x28
}
if (--huart->RxXferCount == 0U)
800630e: 687b ldr r3, [r7, #4]
8006310: 8ddb ldrh r3, [r3, #46] @ 0x2e
8006312: b29b uxth r3, r3
8006314: 3b01 subs r3, #1
8006316: b29b uxth r3, r3
8006318: 687a ldr r2, [r7, #4]
800631a: 4619 mov r1, r3
800631c: 85d1 strh r1, [r2, #46] @ 0x2e
800631e: 2b00 cmp r3, #0
8006320: d15d bne.n 80063de <UART_Receive_IT+0x16e>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
8006322: 687b ldr r3, [r7, #4]
8006324: 681b ldr r3, [r3, #0]
8006326: 68da ldr r2, [r3, #12]
8006328: 687b ldr r3, [r7, #4]
800632a: 681b ldr r3, [r3, #0]
800632c: f022 0220 bic.w r2, r2, #32
8006330: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
8006332: 687b ldr r3, [r7, #4]
8006334: 681b ldr r3, [r3, #0]
8006336: 68da ldr r2, [r3, #12]
8006338: 687b ldr r3, [r7, #4]
800633a: 681b ldr r3, [r3, #0]
800633c: f422 7280 bic.w r2, r2, #256 @ 0x100
8006340: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
8006342: 687b ldr r3, [r7, #4]
8006344: 681b ldr r3, [r3, #0]
8006346: 695a ldr r2, [r3, #20]
8006348: 687b ldr r3, [r7, #4]
800634a: 681b ldr r3, [r3, #0]
800634c: f022 0201 bic.w r2, r2, #1
8006350: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006352: 687b ldr r3, [r7, #4]
8006354: 2220 movs r2, #32
8006356: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
800635a: 687b ldr r3, [r7, #4]
800635c: 2200 movs r2, #0
800635e: 635a str r2, [r3, #52] @ 0x34
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006360: 687b ldr r3, [r7, #4]
8006362: 6b1b ldr r3, [r3, #48] @ 0x30
8006364: 2b01 cmp r3, #1
8006366: d135 bne.n 80063d4 <UART_Receive_IT+0x164>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006368: 687b ldr r3, [r7, #4]
800636a: 2200 movs r2, #0
800636c: 631a str r2, [r3, #48] @ 0x30
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800636e: 687b ldr r3, [r7, #4]
8006370: 681b ldr r3, [r3, #0]
8006372: 330c adds r3, #12
8006374: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006376: 697b ldr r3, [r7, #20]
8006378: e853 3f00 ldrex r3, [r3]
800637c: 613b str r3, [r7, #16]
return(result);
800637e: 693b ldr r3, [r7, #16]
8006380: f023 0310 bic.w r3, r3, #16
8006384: 627b str r3, [r7, #36] @ 0x24
8006386: 687b ldr r3, [r7, #4]
8006388: 681b ldr r3, [r3, #0]
800638a: 330c adds r3, #12
800638c: 6a7a ldr r2, [r7, #36] @ 0x24
800638e: 623a str r2, [r7, #32]
8006390: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006392: 69f9 ldr r1, [r7, #28]
8006394: 6a3a ldr r2, [r7, #32]
8006396: e841 2300 strex r3, r2, [r1]
800639a: 61bb str r3, [r7, #24]
return(result);
800639c: 69bb ldr r3, [r7, #24]
800639e: 2b00 cmp r3, #0
80063a0: d1e5 bne.n 800636e <UART_Receive_IT+0xfe>
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
80063a2: 687b ldr r3, [r7, #4]
80063a4: 681b ldr r3, [r3, #0]
80063a6: 681b ldr r3, [r3, #0]
80063a8: f003 0310 and.w r3, r3, #16
80063ac: 2b10 cmp r3, #16
80063ae: d10a bne.n 80063c6 <UART_Receive_IT+0x156>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
80063b0: 2300 movs r3, #0
80063b2: 60fb str r3, [r7, #12]
80063b4: 687b ldr r3, [r7, #4]
80063b6: 681b ldr r3, [r3, #0]
80063b8: 681b ldr r3, [r3, #0]
80063ba: 60fb str r3, [r7, #12]
80063bc: 687b ldr r3, [r7, #4]
80063be: 681b ldr r3, [r3, #0]
80063c0: 685b ldr r3, [r3, #4]
80063c2: 60fb str r3, [r7, #12]
80063c4: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80063c6: 687b ldr r3, [r7, #4]
80063c8: 8d9b ldrh r3, [r3, #44] @ 0x2c
80063ca: 4619 mov r1, r3
80063cc: 6878 ldr r0, [r7, #4]
80063ce: f7ff fe0e bl 8005fee <HAL_UARTEx_RxEventCallback>
80063d2: e002 b.n 80063da <UART_Receive_IT+0x16a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
80063d4: 6878 ldr r0, [r7, #4]
80063d6: f7ff fdf8 bl 8005fca <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
80063da: 2300 movs r3, #0
80063dc: e002 b.n 80063e4 <UART_Receive_IT+0x174>
}
return HAL_OK;
80063de: 2300 movs r3, #0
80063e0: e000 b.n 80063e4 <UART_Receive_IT+0x174>
}
else
{
return HAL_BUSY;
80063e2: 2302 movs r3, #2
}
}
80063e4: 4618 mov r0, r3
80063e6: 3730 adds r7, #48 @ 0x30
80063e8: 46bd mov sp, r7
80063ea: bd80 pop {r7, pc}
080063ec <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
80063ec: b580 push {r7, lr}
80063ee: b084 sub sp, #16
80063f0: af00 add r7, sp, #0
80063f2: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80063f4: 687b ldr r3, [r7, #4]
80063f6: 681b ldr r3, [r3, #0]
80063f8: 691b ldr r3, [r3, #16]
80063fa: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80063fe: 687b ldr r3, [r7, #4]
8006400: 68da ldr r2, [r3, #12]
8006402: 687b ldr r3, [r7, #4]
8006404: 681b ldr r3, [r3, #0]
8006406: 430a orrs r2, r1
8006408: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
800640a: 687b ldr r3, [r7, #4]
800640c: 689a ldr r2, [r3, #8]
800640e: 687b ldr r3, [r7, #4]
8006410: 691b ldr r3, [r3, #16]
8006412: 431a orrs r2, r3
8006414: 687b ldr r3, [r7, #4]
8006416: 695b ldr r3, [r3, #20]
8006418: 4313 orrs r3, r2
800641a: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
800641c: 687b ldr r3, [r7, #4]
800641e: 681b ldr r3, [r3, #0]
8006420: 68db ldr r3, [r3, #12]
8006422: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8006426: f023 030c bic.w r3, r3, #12
800642a: 687a ldr r2, [r7, #4]
800642c: 6812 ldr r2, [r2, #0]
800642e: 68b9 ldr r1, [r7, #8]
8006430: 430b orrs r3, r1
8006432: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8006434: 687b ldr r3, [r7, #4]
8006436: 681b ldr r3, [r3, #0]
8006438: 695b ldr r3, [r3, #20]
800643a: f423 7140 bic.w r1, r3, #768 @ 0x300
800643e: 687b ldr r3, [r7, #4]
8006440: 699a ldr r2, [r3, #24]
8006442: 687b ldr r3, [r7, #4]
8006444: 681b ldr r3, [r3, #0]
8006446: 430a orrs r2, r1
8006448: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
800644a: 687b ldr r3, [r7, #4]
800644c: 681b ldr r3, [r3, #0]
800644e: 4a2c ldr r2, [pc, #176] @ (8006500 <UART_SetConfig+0x114>)
8006450: 4293 cmp r3, r2
8006452: d103 bne.n 800645c <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8006454: f7fe fd68 bl 8004f28 <HAL_RCC_GetPCLK2Freq>
8006458: 60f8 str r0, [r7, #12]
800645a: e002 b.n 8006462 <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800645c: f7fe fd50 bl 8004f00 <HAL_RCC_GetPCLK1Freq>
8006460: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8006462: 68fa ldr r2, [r7, #12]
8006464: 4613 mov r3, r2
8006466: 009b lsls r3, r3, #2
8006468: 4413 add r3, r2
800646a: 009a lsls r2, r3, #2
800646c: 441a add r2, r3
800646e: 687b ldr r3, [r7, #4]
8006470: 685b ldr r3, [r3, #4]
8006472: 009b lsls r3, r3, #2
8006474: fbb2 f3f3 udiv r3, r2, r3
8006478: 4a22 ldr r2, [pc, #136] @ (8006504 <UART_SetConfig+0x118>)
800647a: fba2 2303 umull r2, r3, r2, r3
800647e: 095b lsrs r3, r3, #5
8006480: 0119 lsls r1, r3, #4
8006482: 68fa ldr r2, [r7, #12]
8006484: 4613 mov r3, r2
8006486: 009b lsls r3, r3, #2
8006488: 4413 add r3, r2
800648a: 009a lsls r2, r3, #2
800648c: 441a add r2, r3
800648e: 687b ldr r3, [r7, #4]
8006490: 685b ldr r3, [r3, #4]
8006492: 009b lsls r3, r3, #2
8006494: fbb2 f2f3 udiv r2, r2, r3
8006498: 4b1a ldr r3, [pc, #104] @ (8006504 <UART_SetConfig+0x118>)
800649a: fba3 0302 umull r0, r3, r3, r2
800649e: 095b lsrs r3, r3, #5
80064a0: 2064 movs r0, #100 @ 0x64
80064a2: fb00 f303 mul.w r3, r0, r3
80064a6: 1ad3 subs r3, r2, r3
80064a8: 011b lsls r3, r3, #4
80064aa: 3332 adds r3, #50 @ 0x32
80064ac: 4a15 ldr r2, [pc, #84] @ (8006504 <UART_SetConfig+0x118>)
80064ae: fba2 2303 umull r2, r3, r2, r3
80064b2: 095b lsrs r3, r3, #5
80064b4: f003 03f0 and.w r3, r3, #240 @ 0xf0
80064b8: 4419 add r1, r3
80064ba: 68fa ldr r2, [r7, #12]
80064bc: 4613 mov r3, r2
80064be: 009b lsls r3, r3, #2
80064c0: 4413 add r3, r2
80064c2: 009a lsls r2, r3, #2
80064c4: 441a add r2, r3
80064c6: 687b ldr r3, [r7, #4]
80064c8: 685b ldr r3, [r3, #4]
80064ca: 009b lsls r3, r3, #2
80064cc: fbb2 f2f3 udiv r2, r2, r3
80064d0: 4b0c ldr r3, [pc, #48] @ (8006504 <UART_SetConfig+0x118>)
80064d2: fba3 0302 umull r0, r3, r3, r2
80064d6: 095b lsrs r3, r3, #5
80064d8: 2064 movs r0, #100 @ 0x64
80064da: fb00 f303 mul.w r3, r0, r3
80064de: 1ad3 subs r3, r2, r3
80064e0: 011b lsls r3, r3, #4
80064e2: 3332 adds r3, #50 @ 0x32
80064e4: 4a07 ldr r2, [pc, #28] @ (8006504 <UART_SetConfig+0x118>)
80064e6: fba2 2303 umull r2, r3, r2, r3
80064ea: 095b lsrs r3, r3, #5
80064ec: f003 020f and.w r2, r3, #15
80064f0: 687b ldr r3, [r7, #4]
80064f2: 681b ldr r3, [r3, #0]
80064f4: 440a add r2, r1
80064f6: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
80064f8: bf00 nop
80064fa: 3710 adds r7, #16
80064fc: 46bd mov sp, r7
80064fe: bd80 pop {r7, pc}
8006500: 40013800 .word 0x40013800
8006504: 51eb851f .word 0x51eb851f
08006508 <memset>:
8006508: 4603 mov r3, r0
800650a: 4402 add r2, r0
800650c: 4293 cmp r3, r2
800650e: d100 bne.n 8006512 <memset+0xa>
8006510: 4770 bx lr
8006512: f803 1b01 strb.w r1, [r3], #1
8006516: e7f9 b.n 800650c <memset+0x4>
08006518 <__errno>:
8006518: 4b01 ldr r3, [pc, #4] @ (8006520 <__errno+0x8>)
800651a: 6818 ldr r0, [r3, #0]
800651c: 4770 bx lr
800651e: bf00 nop
8006520: 20000044 .word 0x20000044
08006524 <__libc_init_array>:
8006524: b570 push {r4, r5, r6, lr}
8006526: 2600 movs r6, #0
8006528: 4d0c ldr r5, [pc, #48] @ (800655c <__libc_init_array+0x38>)
800652a: 4b0d ldr r3, [pc, #52] @ (8006560 <__libc_init_array+0x3c>)
800652c: 1b5b subs r3, r3, r5
800652e: 109c asrs r4, r3, #2
8006530: 42a6 cmp r6, r4
8006532: d109 bne.n 8006548 <__libc_init_array+0x24>
8006534: 2600 movs r6, #0
8006536: f000 f8b7 bl 80066a8 <_init>
800653a: 4d0a ldr r5, [pc, #40] @ (8006564 <__libc_init_array+0x40>)
800653c: 4b0a ldr r3, [pc, #40] @ (8006568 <__libc_init_array+0x44>)
800653e: 1b5b subs r3, r3, r5
8006540: 109c asrs r4, r3, #2
8006542: 42a6 cmp r6, r4
8006544: d105 bne.n 8006552 <__libc_init_array+0x2e>
8006546: bd70 pop {r4, r5, r6, pc}
8006548: f855 3b04 ldr.w r3, [r5], #4
800654c: 4798 blx r3
800654e: 3601 adds r6, #1
8006550: e7ee b.n 8006530 <__libc_init_array+0xc>
8006552: f855 3b04 ldr.w r3, [r5], #4
8006556: 4798 blx r3
8006558: 3601 adds r6, #1
800655a: e7f2 b.n 8006542 <__libc_init_array+0x1e>
800655c: 0800674c .word 0x0800674c
8006560: 0800674c .word 0x0800674c
8006564: 0800674c .word 0x0800674c
8006568: 08006750 .word 0x08006750
0800656c <memcpy>:
800656c: 440a add r2, r1
800656e: 4291 cmp r1, r2
8006570: f100 33ff add.w r3, r0, #4294967295
8006574: d100 bne.n 8006578 <memcpy+0xc>
8006576: 4770 bx lr
8006578: b510 push {r4, lr}
800657a: f811 4b01 ldrb.w r4, [r1], #1
800657e: 4291 cmp r1, r2
8006580: f803 4f01 strb.w r4, [r3, #1]!
8006584: d1f9 bne.n 800657a <memcpy+0xe>
8006586: bd10 pop {r4, pc}
08006588 <sqrtf>:
8006588: b538 push {r3, r4, r5, lr}
800658a: 4604 mov r4, r0
800658c: f000 f81a bl 80065c4 <__ieee754_sqrtf>
8006590: 4621 mov r1, r4
8006592: 4605 mov r5, r0
8006594: 4620 mov r0, r4
8006596: f7fa fc4b bl 8000e30 <__aeabi_fcmpun>
800659a: b920 cbnz r0, 80065a6 <sqrtf+0x1e>
800659c: 4620 mov r0, r4
800659e: 2100 movs r1, #0
80065a0: f7fa fc1e bl 8000de0 <__aeabi_fcmplt>
80065a4: b908 cbnz r0, 80065aa <sqrtf+0x22>
80065a6: 4628 mov r0, r5
80065a8: bd38 pop {r3, r4, r5, pc}
80065aa: f7ff ffb5 bl 8006518 <__errno>
80065ae: 2221 movs r2, #33 @ 0x21
80065b0: 4603 mov r3, r0
80065b2: 2100 movs r1, #0
80065b4: 601a str r2, [r3, #0]
80065b6: 4608 mov r0, r1
80065b8: f7fa fb28 bl 8000c0c <__aeabi_fdiv>
80065bc: 4605 mov r5, r0
80065be: 4628 mov r0, r5
80065c0: bd38 pop {r3, r4, r5, pc}
80065c2: bf00 nop
080065c4 <__ieee754_sqrtf>:
80065c4: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000
80065c8: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000
80065cc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80065d0: 4604 mov r4, r0
80065d2: d24f bcs.n 8006674 <__ieee754_sqrtf+0xb0>
80065d4: 2a00 cmp r2, #0
80065d6: d04b beq.n 8006670 <__ieee754_sqrtf+0xac>
80065d8: 2800 cmp r0, #0
80065da: 4603 mov r3, r0
80065dc: db54 blt.n 8006688 <__ieee754_sqrtf+0xc4>
80065de: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000
80065e2: d14f bne.n 8006684 <__ieee754_sqrtf+0xc0>
80065e4: 005b lsls r3, r3, #1
80065e6: 0218 lsls r0, r3, #8
80065e8: 4611 mov r1, r2
80065ea: f102 0201 add.w r2, r2, #1
80065ee: d5f9 bpl.n 80065e4 <__ieee754_sqrtf+0x20>
80065f0: 4249 negs r1, r1
80065f2: 2400 movs r4, #0
80065f4: f3c3 0216 ubfx r2, r3, #0, #23
80065f8: f1a1 057f sub.w r5, r1, #127 @ 0x7f
80065fc: 07cb lsls r3, r1, #31
80065fe: f04f 0e19 mov.w lr, #25
8006602: f04f 7c80 mov.w ip, #16777216 @ 0x1000000
8006606: 4621 mov r1, r4
8006608: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
800660c: bf58 it pl
800660e: 0052 lslpl r2, r2, #1
8006610: 106d asrs r5, r5, #1
8006612: 0052 lsls r2, r2, #1
8006614: eb01 030c add.w r3, r1, ip
8006618: 4293 cmp r3, r2
800661a: bfcf iteee gt
800661c: 4613 movgt r3, r2
800661e: eb03 010c addle.w r1, r3, ip
8006622: 4464 addle r4, ip
8006624: 1ad3 suble r3, r2, r3
8006626: f1be 0e01 subs.w lr, lr, #1
800662a: ea4f 0243 mov.w r2, r3, lsl #1
800662e: ea4f 0c5c mov.w ip, ip, lsr #1
8006632: d1ef bne.n 8006614 <__ieee754_sqrtf+0x50>
8006634: b1bb cbz r3, 8006666 <__ieee754_sqrtf+0xa2>
8006636: 4e1a ldr r6, [pc, #104] @ (80066a0 <__ieee754_sqrtf+0xdc>)
8006638: 4f1a ldr r7, [pc, #104] @ (80066a4 <__ieee754_sqrtf+0xe0>)
800663a: 6830 ldr r0, [r6, #0]
800663c: 6839 ldr r1, [r7, #0]
800663e: f7fa f927 bl 8000890 <__aeabi_fsub>
8006642: f8d6 8000 ldr.w r8, [r6]
8006646: 4601 mov r1, r0
8006648: 4640 mov r0, r8
800664a: f7fa fbd3 bl 8000df4 <__aeabi_fcmple>
800664e: b150 cbz r0, 8006666 <__ieee754_sqrtf+0xa2>
8006650: 6830 ldr r0, [r6, #0]
8006652: 6839 ldr r1, [r7, #0]
8006654: f7fa f91e bl 8000894 <__addsf3>
8006658: 6836 ldr r6, [r6, #0]
800665a: 4601 mov r1, r0
800665c: 4630 mov r0, r6
800665e: f7fa fbbf bl 8000de0 <__aeabi_fcmplt>
8006662: b1c8 cbz r0, 8006698 <__ieee754_sqrtf+0xd4>
8006664: 3402 adds r4, #2
8006666: 1060 asrs r0, r4, #1
8006668: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000
800666c: eb00 50c5 add.w r0, r0, r5, lsl #23
8006670: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006674: 4601 mov r1, r0
8006676: f7fa fa15 bl 8000aa4 <__aeabi_fmul>
800667a: 4621 mov r1, r4
800667c: f7fa f90a bl 8000894 <__addsf3>
8006680: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006684: 15c1 asrs r1, r0, #23
8006686: e7b4 b.n 80065f2 <__ieee754_sqrtf+0x2e>
8006688: 4601 mov r1, r0
800668a: f7fa f901 bl 8000890 <__aeabi_fsub>
800668e: 4601 mov r1, r0
8006690: f7fa fabc bl 8000c0c <__aeabi_fdiv>
8006694: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006698: 3401 adds r4, #1
800669a: f024 0401 bic.w r4, r4, #1
800669e: e7e2 b.n 8006666 <__ieee754_sqrtf+0xa2>
80066a0: 08006740 .word 0x08006740
80066a4: 0800673c .word 0x0800673c
080066a8 <_init>:
80066a8: b5f8 push {r3, r4, r5, r6, r7, lr}
80066aa: bf00 nop
80066ac: bcf8 pop {r3, r4, r5, r6, r7}
80066ae: bc08 pop {r3}
80066b0: 469e mov lr, r3
80066b2: 4770 bx lr
080066b4 <_fini>:
80066b4: b5f8 push {r3, r4, r5, r6, r7, lr}
80066b6: bf00 nop
80066b8: bcf8 pop {r3, r4, r5, r6, r7}
80066ba: bc08 pop {r3}
80066bc: 469e mov lr, r3
80066be: 4770 bx lr
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