hardware/fertirrega_v6
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e65f787c34c43f509a59ac8a1372ec308247d216
fertirrega_v6/Fertirrega_v6/Debug/Fertirrega_v6.list
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Fertirrega_v6.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00006598 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000174 080066a4 080066a4 000076a4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08006818 08006818 00008090 2**0
CONTENTS, READONLY
4 .ARM 00000008 08006818 08006818 00007818 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08006820 08006820 00008090 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08006820 08006820 00007820 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08006824 08006824 00007824 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000090 20000000 08006828 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000830 20000090 080068b8 00008090 2**3
ALLOC
10 ._user_heap_stack 00000600 200008c0 080068b8 000088c0 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00008090 2**0
CONTENTS, READONLY
12 .debug_info 0000ff7c 00000000 00000000 000080b9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003374 00000000 00000000 00018035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000e30 00000000 00000000 0001b3b0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000ae8 00000000 00000000 0001c1e0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00019a99 00000000 00000000 0001ccc8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001439d 00000000 00000000 00036761 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008d606 00000000 00000000 0004aafe 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000d8104 2**0
CONTENTS, READONLY
20 .debug_frame 00003af8 00000000 00000000 000d8148 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000dbc40 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000090 .word 0x20000090
8000128: 00000000 .word 0x00000000
800012c: 0800668c .word 0x0800668c
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000094 .word 0x20000094
8000148: 0800668c .word 0x0800668c
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <__aeabi_dmul>:
800015c: b570 push {r4, r5, r6, lr}
800015e: f04f 0cff mov.w ip, #255 @ 0xff
8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20
800016a: bf1d ittte ne
800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000170: ea94 0f0c teqne r4, ip
8000174: ea95 0f0c teqne r5, ip
8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc>
800017c: 442c add r4, r5
800017e: ea81 0603 eor.w r6, r1, r3
8000182: ea21 514c bic.w r1, r1, ip, lsl #21
8000186: ea23 534c bic.w r3, r3, ip, lsl #21
800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12
800018e: bf18 it ne
8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4>
800019e: fba0 ce02 umull ip, lr, r0, r2
80001a2: f04f 0500 mov.w r5, #0
80001a6: fbe1 e502 umlal lr, r5, r1, r2
80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80001ae: fbe0 e503 umlal lr, r5, r0, r3
80001b2: f04f 0600 mov.w r6, #0
80001b6: fbe1 5603 umlal r5, r6, r1, r3
80001ba: f09c 0f00 teq ip, #0
80001be: bf18 it ne
80001c0: f04e 0e01 orrne.w lr, lr, #1
80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff
80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200
80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300
80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80>
80001d2: ea5f 0e4e movs.w lr, lr, lsl #1
80001d6: 416d adcs r5, r5
80001d8: eb46 0606 adc.w r6, r6, r6
80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11
80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21
80001e4: ea4f 20c5 mov.w r0, r5, lsl #11
80001e8: ea40 505e orr.w r0, r0, lr, lsr #21
80001ec: ea4f 2ece mov.w lr, lr, lsl #11
80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80001f4: bf88 it hi
80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde>
80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
8000200: bf08 it eq
8000202: ea5f 0e50 movseq.w lr, r0, lsr #1
8000206: f150 0000 adcs.w r0, r0, #0
800020a: eb41 5104 adc.w r1, r1, r4, lsl #20
800020e: bd70 pop {r4, r5, r6, pc}
8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000214: ea46 0101 orr.w r1, r6, r1
8000218: ea40 0002 orr.w r0, r0, r2
800021c: ea81 0103 eor.w r1, r1, r3
8000220: ebb4 045c subs.w r4, r4, ip, lsr #1
8000224: bfc2 ittt gt
8000226: ebd4 050c rsbsgt r5, r4, ip
800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800022e: bd70 popgt {r4, r5, r6, pc}
8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000234: f04f 0e00 mov.w lr, #0
8000238: 3c01 subs r4, #1
800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238>
800023e: f114 0f36 cmn.w r4, #54 @ 0x36
8000242: bfde ittt le
8000244: 2000 movle r0, #0
8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
800024a: bd70 pople {r4, r5, r6, pc}
800024c: f1c4 0400 rsb r4, r4, #0
8000250: 3c20 subs r4, #32
8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164>
8000254: 340c adds r4, #12
8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134>
8000258: f104 0414 add.w r4, r4, #20
800025c: f1c4 0520 rsb r5, r4, #32
8000260: fa00 f305 lsl.w r3, r0, r5
8000264: fa20 f004 lsr.w r0, r0, r4
8000268: fa01 f205 lsl.w r2, r1, r5
800026c: ea40 0002 orr.w r0, r0, r2
8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31
800027c: fa21 f604 lsr.w r6, r1, r4
8000280: eb42 0106 adc.w r1, r2, r6
8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000288: bf08 it eq
800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800028e: bd70 pop {r4, r5, r6, pc}
8000290: f1c4 040c rsb r4, r4, #12
8000294: f1c4 0520 rsb r5, r4, #32
8000298: fa00 f304 lsl.w r3, r0, r4
800029c: fa20 f005 lsr.w r0, r0, r5
80002a0: fa01 f204 lsl.w r2, r1, r4
80002a4: ea40 0002 orr.w r0, r0, r2
80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002b0: f141 0100 adc.w r1, r1, #0
80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002b8: bf08 it eq
80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002be: bd70 pop {r4, r5, r6, pc}
80002c0: f1c4 0520 rsb r5, r4, #32
80002c4: fa00 f205 lsl.w r2, r0, r5
80002c8: ea4e 0e02 orr.w lr, lr, r2
80002cc: fa20 f304 lsr.w r3, r0, r4
80002d0: fa01 f205 lsl.w r2, r1, r5
80002d4: ea43 0302 orr.w r3, r3, r2
80002d8: fa21 f004 lsr.w r0, r1, r4
80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002e0: fa21 f204 lsr.w r2, r1, r4
80002e4: ea20 0002 bic.w r0, r0, r2
80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31
80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002f0: bf08 it eq
80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002f6: bd70 pop {r4, r5, r6, pc}
80002f8: f094 0f00 teq r4, #0
80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2>
80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
8000302: 0040 lsls r0, r0, #1
8000304: eb41 0101 adc.w r1, r1, r1
8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000
800030c: bf08 it eq
800030e: 3c01 subeq r4, #1
8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6>
8000312: ea41 0106 orr.w r1, r1, r6
8000316: f095 0f00 teq r5, #0
800031a: bf18 it ne
800031c: 4770 bxne lr
800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
8000322: 0052 lsls r2, r2, #1
8000324: eb43 0303 adc.w r3, r3, r3
8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000
800032c: bf08 it eq
800032e: 3d01 subeq r5, #1
8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6>
8000332: ea43 0306 orr.w r3, r3, r6
8000336: 4770 bx lr
8000338: ea94 0f0c teq r4, ip
800033c: ea0c 5513 and.w r5, ip, r3, lsr #20
8000340: bf18 it ne
8000342: ea95 0f0c teqne r5, ip
8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206>
8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1
800034c: bf18 it ne
800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c>
8000354: ea81 0103 eor.w r1, r1, r3
8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800035c: f04f 0000 mov.w r0, #0
8000360: bd70 pop {r4, r5, r6, pc}
8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000366: bf06 itte eq
8000368: 4610 moveq r0, r2
800036a: 4619 moveq r1, r3
800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a>
8000372: ea94 0f0c teq r4, ip
8000376: d102 bne.n 800037e <__aeabi_dmul+0x222>
8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12
800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a>
800037e: ea95 0f0c teq r5, ip
8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234>
8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000388: bf1c itt ne
800038a: 4610 movne r0, r2
800038c: 4619 movne r1, r3
800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a>
8000390: ea81 0103 eor.w r1, r1, r3
8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003a0: f04f 0000 mov.w r0, #0
80003a4: bd70 pop {r4, r5, r6, pc}
80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80003ae: bd70 pop {r4, r5, r6, pc}
080003b0 <__aeabi_drsub>:
80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
80003b4: e002 b.n 80003bc <__adddf3>
80003b6: bf00 nop
080003b8 <__aeabi_dsub>:
80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
080003bc <__adddf3>:
80003bc: b530 push {r4, r5, lr}
80003be: ea4f 0441 mov.w r4, r1, lsl #1
80003c2: ea4f 0543 mov.w r5, r3, lsl #1
80003c6: ea94 0f05 teq r4, r5
80003ca: bf08 it eq
80003cc: ea90 0f02 teqeq r0, r2
80003d0: bf1f itttt ne
80003d2: ea54 0c00 orrsne.w ip, r4, r0
80003d6: ea55 0c02 orrsne.w ip, r5, r2
80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21
80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21
80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee>
80003e6: ea4f 5454 mov.w r4, r4, lsr #21
80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21
80003ee: bfb8 it lt
80003f0: 426d neglt r5, r5
80003f2: dd0c ble.n 800040e <__adddf3+0x52>
80003f4: 442c add r4, r5
80003f6: ea80 0202 eor.w r2, r0, r2
80003fa: ea81 0303 eor.w r3, r1, r3
80003fe: ea82 0000 eor.w r0, r2, r0
8000402: ea83 0101 eor.w r1, r3, r1
8000406: ea80 0202 eor.w r2, r0, r2
800040a: ea81 0303 eor.w r3, r1, r3
800040e: 2d36 cmp r5, #54 @ 0x36
8000410: bf88 it hi
8000412: bd30 pophi {r4, r5, pc}
8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000418: ea4f 3101 mov.w r1, r1, lsl #12
800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000424: d002 beq.n 800042c <__adddf3+0x70>
8000426: 4240 negs r0, r0
8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1
800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000430: ea4f 3303 mov.w r3, r3, lsl #12
8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000438: d002 beq.n 8000440 <__adddf3+0x84>
800043a: 4252 negs r2, r2
800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000440: ea94 0f05 teq r4, r5
8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da>
8000448: f1a4 0401 sub.w r4, r4, #1
800044c: f1d5 0e20 rsbs lr, r5, #32
8000450: db0d blt.n 800046e <__adddf3+0xb2>
8000452: fa02 fc0e lsl.w ip, r2, lr
8000456: fa22 f205 lsr.w r2, r2, r5
800045a: 1880 adds r0, r0, r2
800045c: f141 0100 adc.w r1, r1, #0
8000460: fa03 f20e lsl.w r2, r3, lr
8000464: 1880 adds r0, r0, r2
8000466: fa43 f305 asr.w r3, r3, r5
800046a: 4159 adcs r1, r3
800046c: e00e b.n 800048c <__adddf3+0xd0>
800046e: f1a5 0520 sub.w r5, r5, #32
8000472: f10e 0e20 add.w lr, lr, #32
8000476: 2a01 cmp r2, #1
8000478: fa03 fc0e lsl.w ip, r3, lr
800047c: bf28 it cs
800047e: f04c 0c02 orrcs.w ip, ip, #2
8000482: fa43 f305 asr.w r3, r3, r5
8000486: 18c0 adds r0, r0, r3
8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31
800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000490: d507 bpl.n 80004a2 <__adddf3+0xe6>
8000492: f04f 0e00 mov.w lr, #0
8000496: f1dc 0c00 rsbs ip, ip, #0
800049a: eb7e 0000 sbcs.w r0, lr, r0
800049e: eb6e 0101 sbc.w r1, lr, r1
80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80004a6: d31b bcc.n 80004e0 <__adddf3+0x124>
80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c>
80004ae: 0849 lsrs r1, r1, #1
80004b0: ea5f 0030 movs.w r0, r0, rrx
80004b4: ea4f 0c3c mov.w ip, ip, rrx
80004b8: f104 0401 add.w r4, r4, #1
80004bc: ea4f 5244 mov.w r2, r4, lsl #21
80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240>
80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80004cc: bf08 it eq
80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1
80004d2: f150 0000 adcs.w r0, r0, #0
80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20
80004da: ea41 0105 orr.w r1, r1, r5
80004de: bd30 pop {r4, r5, pc}
80004e0: ea5f 0c4c movs.w ip, ip, lsl #1
80004e4: 4140 adcs r0, r0
80004e6: eb41 0101 adc.w r1, r1, r1
80004ea: 3c01 subs r4, #1
80004ec: bf28 it cs
80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c>
80004f4: f091 0f00 teq r1, #0
80004f8: bf04 itt eq
80004fa: 4601 moveq r1, r0
80004fc: 2000 moveq r0, #0
80004fe: fab1 f381 clz r3, r1
8000502: bf08 it eq
8000504: 3320 addeq r3, #32
8000506: f1a3 030b sub.w r3, r3, #11
800050a: f1b3 0220 subs.w r2, r3, #32
800050e: da0c bge.n 800052a <__adddf3+0x16e>
8000510: 320c adds r2, #12
8000512: dd08 ble.n 8000526 <__adddf3+0x16a>
8000514: f102 0c14 add.w ip, r2, #20
8000518: f1c2 020c rsb r2, r2, #12
800051c: fa01 f00c lsl.w r0, r1, ip
8000520: fa21 f102 lsr.w r1, r1, r2
8000524: e00c b.n 8000540 <__adddf3+0x184>
8000526: f102 0214 add.w r2, r2, #20
800052a: bfd8 it le
800052c: f1c2 0c20 rsble ip, r2, #32
8000530: fa01 f102 lsl.w r1, r1, r2
8000534: fa20 fc0c lsr.w ip, r0, ip
8000538: bfdc itt le
800053a: ea41 010c orrle.w r1, r1, ip
800053e: 4090 lslle r0, r2
8000540: 1ae4 subs r4, r4, r3
8000542: bfa2 ittt ge
8000544: eb01 5104 addge.w r1, r1, r4, lsl #20
8000548: 4329 orrge r1, r5
800054a: bd30 popge {r4, r5, pc}
800054c: ea6f 0404 mvn.w r4, r4
8000550: 3c1f subs r4, #31
8000552: da1c bge.n 800058e <__adddf3+0x1d2>
8000554: 340c adds r4, #12
8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba>
8000558: f104 0414 add.w r4, r4, #20
800055c: f1c4 0220 rsb r2, r4, #32
8000560: fa20 f004 lsr.w r0, r0, r4
8000564: fa01 f302 lsl.w r3, r1, r2
8000568: ea40 0003 orr.w r0, r0, r3
800056c: fa21 f304 lsr.w r3, r1, r4
8000570: ea45 0103 orr.w r1, r5, r3
8000574: bd30 pop {r4, r5, pc}
8000576: f1c4 040c rsb r4, r4, #12
800057a: f1c4 0220 rsb r2, r4, #32
800057e: fa20 f002 lsr.w r0, r0, r2
8000582: fa01 f304 lsl.w r3, r1, r4
8000586: ea40 0003 orr.w r0, r0, r3
800058a: 4629 mov r1, r5
800058c: bd30 pop {r4, r5, pc}
800058e: fa21 f004 lsr.w r0, r1, r4
8000592: 4629 mov r1, r5
8000594: bd30 pop {r4, r5, pc}
8000596: f094 0f00 teq r4, #0
800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800059e: bf06 itte eq
80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
80005a4: 3401 addeq r4, #1
80005a6: 3d01 subne r5, #1
80005a8: e74e b.n 8000448 <__adddf3+0x8c>
80005aa: ea7f 5c64 mvns.w ip, r4, asr #21
80005ae: bf18 it ne
80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21
80005b4: d029 beq.n 800060a <__adddf3+0x24e>
80005b6: ea94 0f05 teq r4, r5
80005ba: bf08 it eq
80005bc: ea90 0f02 teqeq r0, r2
80005c0: d005 beq.n 80005ce <__adddf3+0x212>
80005c2: ea54 0c00 orrs.w ip, r4, r0
80005c6: bf04 itt eq
80005c8: 4619 moveq r1, r3
80005ca: 4610 moveq r0, r2
80005cc: bd30 pop {r4, r5, pc}
80005ce: ea91 0f03 teq r1, r3
80005d2: bf1e ittt ne
80005d4: 2100 movne r1, #0
80005d6: 2000 movne r0, #0
80005d8: bd30 popne {r4, r5, pc}
80005da: ea5f 5c54 movs.w ip, r4, lsr #21
80005de: d105 bne.n 80005ec <__adddf3+0x230>
80005e0: 0040 lsls r0, r0, #1
80005e2: 4149 adcs r1, r1
80005e4: bf28 it cs
80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80005ea: bd30 pop {r4, r5, pc}
80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80005f0: bf3c itt cc
80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80005f6: bd30 popcc {r4, r5, pc}
80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000604: f04f 0000 mov.w r0, #0
8000608: bd30 pop {r4, r5, pc}
800060a: ea7f 5c64 mvns.w ip, r4, asr #21
800060e: bf1a itte ne
8000610: 4619 movne r1, r3
8000612: 4610 movne r0, r2
8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000618: bf1c itt ne
800061a: 460b movne r3, r1
800061c: 4602 movne r2, r0
800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000622: bf06 itte eq
8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12
8000628: ea91 0f03 teqeq r1, r3
800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000630: bd30 pop {r4, r5, pc}
8000632: bf00 nop
08000634 <__aeabi_ui2d>:
8000634: f090 0f00 teq r0, #0
8000638: bf04 itt eq
800063a: 2100 moveq r1, #0
800063c: 4770 bxeq lr
800063e: b530 push {r4, r5, lr}
8000640: f44f 6480 mov.w r4, #1024 @ 0x400
8000644: f104 0432 add.w r4, r4, #50 @ 0x32
8000648: f04f 0500 mov.w r5, #0
800064c: f04f 0100 mov.w r1, #0
8000650: e750 b.n 80004f4 <__adddf3+0x138>
8000652: bf00 nop
08000654 <__aeabi_i2d>:
8000654: f090 0f00 teq r0, #0
8000658: bf04 itt eq
800065a: 2100 moveq r1, #0
800065c: 4770 bxeq lr
800065e: b530 push {r4, r5, lr}
8000660: f44f 6480 mov.w r4, #1024 @ 0x400
8000664: f104 0432 add.w r4, r4, #50 @ 0x32
8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800066c: bf48 it mi
800066e: 4240 negmi r0, r0
8000670: f04f 0100 mov.w r1, #0
8000674: e73e b.n 80004f4 <__adddf3+0x138>
8000676: bf00 nop
08000678 <__aeabi_f2d>:
8000678: 0042 lsls r2, r0, #1
800067a: ea4f 01e2 mov.w r1, r2, asr #3
800067e: ea4f 0131 mov.w r1, r1, rrx
8000682: ea4f 7002 mov.w r0, r2, lsl #28
8000686: bf1f itttt ne
8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000694: 4770 bxne lr
8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800069a: bf08 it eq
800069c: 4770 bxeq lr
800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000
80006a2: bf04 itt eq
80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
80006a8: 4770 bxeq lr
80006aa: b530 push {r4, r5, lr}
80006ac: f44f 7460 mov.w r4, #896 @ 0x380
80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006b8: e71c b.n 80004f4 <__adddf3+0x138>
80006ba: bf00 nop
080006bc <__aeabi_ul2d>:
80006bc: ea50 0201 orrs.w r2, r0, r1
80006c0: bf08 it eq
80006c2: 4770 bxeq lr
80006c4: b530 push {r4, r5, lr}
80006c6: f04f 0500 mov.w r5, #0
80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16>
080006cc <__aeabi_l2d>:
80006cc: ea50 0201 orrs.w r2, r0, r1
80006d0: bf08 it eq
80006d2: 4770 bxeq lr
80006d4: b530 push {r4, r5, lr}
80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16>
80006dc: 4240 negs r0, r0
80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1
80006e2: f44f 6480 mov.w r4, #1024 @ 0x400
80006e6: f104 0432 add.w r4, r4, #50 @ 0x32
80006ea: ea5f 5c91 movs.w ip, r1, lsr #22
80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6>
80006f2: f04f 0203 mov.w r2, #3
80006f6: ea5f 0cdc movs.w ip, ip, lsr #3
80006fa: bf18 it ne
80006fc: 3203 addne r2, #3
80006fe: ea5f 0cdc movs.w ip, ip, lsr #3
8000702: bf18 it ne
8000704: 3203 addne r2, #3
8000706: eb02 02dc add.w r2, r2, ip, lsr #3
800070a: f1c2 0320 rsb r3, r2, #32
800070e: fa00 fc03 lsl.w ip, r0, r3
8000712: fa20 f002 lsr.w r0, r0, r2
8000716: fa01 fe03 lsl.w lr, r1, r3
800071a: ea40 000e orr.w r0, r0, lr
800071e: fa21 f102 lsr.w r1, r1, r2
8000722: 4414 add r4, r2
8000724: e6bd b.n 80004a2 <__adddf3+0xe6>
8000726: bf00 nop
08000728 <__gedf2>:
8000728: f04f 3cff mov.w ip, #4294967295
800072c: e006 b.n 800073c <__cmpdf2+0x4>
800072e: bf00 nop
08000730 <__ledf2>:
8000730: f04f 0c01 mov.w ip, #1
8000734: e002 b.n 800073c <__cmpdf2+0x4>
8000736: bf00 nop
08000738 <__cmpdf2>:
8000738: f04f 0c01 mov.w ip, #1
800073c: f84d cd04 str.w ip, [sp, #-4]!
8000740: ea4f 0c41 mov.w ip, r1, lsl #1
8000744: ea7f 5c6c mvns.w ip, ip, asr #21
8000748: ea4f 0c43 mov.w ip, r3, lsl #1
800074c: bf18 it ne
800074e: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000752: d01b beq.n 800078c <__cmpdf2+0x54>
8000754: b001 add sp, #4
8000756: ea50 0c41 orrs.w ip, r0, r1, lsl #1
800075a: bf0c ite eq
800075c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000760: ea91 0f03 teqne r1, r3
8000764: bf02 ittt eq
8000766: ea90 0f02 teqeq r0, r2
800076a: 2000 moveq r0, #0
800076c: 4770 bxeq lr
800076e: f110 0f00 cmn.w r0, #0
8000772: ea91 0f03 teq r1, r3
8000776: bf58 it pl
8000778: 4299 cmppl r1, r3
800077a: bf08 it eq
800077c: 4290 cmpeq r0, r2
800077e: bf2c ite cs
8000780: 17d8 asrcs r0, r3, #31
8000782: ea6f 70e3 mvncc.w r0, r3, asr #31
8000786: f040 0001 orr.w r0, r0, #1
800078a: 4770 bx lr
800078c: ea4f 0c41 mov.w ip, r1, lsl #1
8000790: ea7f 5c6c mvns.w ip, ip, asr #21
8000794: d102 bne.n 800079c <__cmpdf2+0x64>
8000796: ea50 3c01 orrs.w ip, r0, r1, lsl #12
800079a: d107 bne.n 80007ac <__cmpdf2+0x74>
800079c: ea4f 0c43 mov.w ip, r3, lsl #1
80007a0: ea7f 5c6c mvns.w ip, ip, asr #21
80007a4: d1d6 bne.n 8000754 <__cmpdf2+0x1c>
80007a6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
80007aa: d0d3 beq.n 8000754 <__cmpdf2+0x1c>
80007ac: f85d 0b04 ldr.w r0, [sp], #4
80007b0: 4770 bx lr
80007b2: bf00 nop
080007b4 <__aeabi_cdrcmple>:
80007b4: 4684 mov ip, r0
80007b6: 4610 mov r0, r2
80007b8: 4662 mov r2, ip
80007ba: 468c mov ip, r1
80007bc: 4619 mov r1, r3
80007be: 4663 mov r3, ip
80007c0: e000 b.n 80007c4 <__aeabi_cdcmpeq>
80007c2: bf00 nop
080007c4 <__aeabi_cdcmpeq>:
80007c4: b501 push {r0, lr}
80007c6: f7ff ffb7 bl 8000738 <__cmpdf2>
80007ca: 2800 cmp r0, #0
80007cc: bf48 it mi
80007ce: f110 0f00 cmnmi.w r0, #0
80007d2: bd01 pop {r0, pc}
080007d4 <__aeabi_dcmpeq>:
80007d4: f84d ed08 str.w lr, [sp, #-8]!
80007d8: f7ff fff4 bl 80007c4 <__aeabi_cdcmpeq>
80007dc: bf0c ite eq
80007de: 2001 moveq r0, #1
80007e0: 2000 movne r0, #0
80007e2: f85d fb08 ldr.w pc, [sp], #8
80007e6: bf00 nop
080007e8 <__aeabi_dcmplt>:
80007e8: f84d ed08 str.w lr, [sp, #-8]!
80007ec: f7ff ffea bl 80007c4 <__aeabi_cdcmpeq>
80007f0: bf34 ite cc
80007f2: 2001 movcc r0, #1
80007f4: 2000 movcs r0, #0
80007f6: f85d fb08 ldr.w pc, [sp], #8
80007fa: bf00 nop
080007fc <__aeabi_dcmple>:
80007fc: f84d ed08 str.w lr, [sp, #-8]!
8000800: f7ff ffe0 bl 80007c4 <__aeabi_cdcmpeq>
8000804: bf94 ite ls
8000806: 2001 movls r0, #1
8000808: 2000 movhi r0, #0
800080a: f85d fb08 ldr.w pc, [sp], #8
800080e: bf00 nop
08000810 <__aeabi_dcmpge>:
8000810: f84d ed08 str.w lr, [sp, #-8]!
8000814: f7ff ffce bl 80007b4 <__aeabi_cdrcmple>
8000818: bf94 ite ls
800081a: 2001 movls r0, #1
800081c: 2000 movhi r0, #0
800081e: f85d fb08 ldr.w pc, [sp], #8
8000822: bf00 nop
08000824 <__aeabi_dcmpgt>:
8000824: f84d ed08 str.w lr, [sp, #-8]!
8000828: f7ff ffc4 bl 80007b4 <__aeabi_cdrcmple>
800082c: bf34 ite cc
800082e: 2001 movcc r0, #1
8000830: 2000 movcs r0, #0
8000832: f85d fb08 ldr.w pc, [sp], #8
8000836: bf00 nop
08000838 <__aeabi_d2iz>:
8000838: ea4f 0241 mov.w r2, r1, lsl #1
800083c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000840: d215 bcs.n 800086e <__aeabi_d2iz+0x36>
8000842: d511 bpl.n 8000868 <__aeabi_d2iz+0x30>
8000844: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000848: ebb3 5262 subs.w r2, r3, r2, asr #21
800084c: d912 bls.n 8000874 <__aeabi_d2iz+0x3c>
800084e: ea4f 23c1 mov.w r3, r1, lsl #11
8000852: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000856: ea43 5350 orr.w r3, r3, r0, lsr #21
800085a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
800085e: fa23 f002 lsr.w r0, r3, r2
8000862: bf18 it ne
8000864: 4240 negne r0, r0
8000866: 4770 bx lr
8000868: f04f 0000 mov.w r0, #0
800086c: 4770 bx lr
800086e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000872: d105 bne.n 8000880 <__aeabi_d2iz+0x48>
8000874: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000878: bf08 it eq
800087a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
800087e: 4770 bx lr
8000880: f04f 0000 mov.w r0, #0
8000884: 4770 bx lr
8000886: bf00 nop
08000888 <__aeabi_frsub>:
8000888: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
800088c: e002 b.n 8000894 <__addsf3>
800088e: bf00 nop
08000890 <__aeabi_fsub>:
8000890: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
08000894 <__addsf3>:
8000894: 0042 lsls r2, r0, #1
8000896: bf1f itttt ne
8000898: ea5f 0341 movsne.w r3, r1, lsl #1
800089c: ea92 0f03 teqne r2, r3
80008a0: ea7f 6c22 mvnsne.w ip, r2, asr #24
80008a4: ea7f 6c23 mvnsne.w ip, r3, asr #24
80008a8: d06a beq.n 8000980 <__addsf3+0xec>
80008aa: ea4f 6212 mov.w r2, r2, lsr #24
80008ae: ebd2 6313 rsbs r3, r2, r3, lsr #24
80008b2: bfc1 itttt gt
80008b4: 18d2 addgt r2, r2, r3
80008b6: 4041 eorgt r1, r0
80008b8: 4048 eorgt r0, r1
80008ba: 4041 eorgt r1, r0
80008bc: bfb8 it lt
80008be: 425b neglt r3, r3
80008c0: 2b19 cmp r3, #25
80008c2: bf88 it hi
80008c4: 4770 bxhi lr
80008c6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
80008ca: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80008ce: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
80008d2: bf18 it ne
80008d4: 4240 negne r0, r0
80008d6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80008da: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
80008de: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
80008e2: bf18 it ne
80008e4: 4249 negne r1, r1
80008e6: ea92 0f03 teq r2, r3
80008ea: d03f beq.n 800096c <__addsf3+0xd8>
80008ec: f1a2 0201 sub.w r2, r2, #1
80008f0: fa41 fc03 asr.w ip, r1, r3
80008f4: eb10 000c adds.w r0, r0, ip
80008f8: f1c3 0320 rsb r3, r3, #32
80008fc: fa01 f103 lsl.w r1, r1, r3
8000900: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
8000904: d502 bpl.n 800090c <__addsf3+0x78>
8000906: 4249 negs r1, r1
8000908: eb60 0040 sbc.w r0, r0, r0, lsl #1
800090c: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
8000910: d313 bcc.n 800093a <__addsf3+0xa6>
8000912: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
8000916: d306 bcc.n 8000926 <__addsf3+0x92>
8000918: 0840 lsrs r0, r0, #1
800091a: ea4f 0131 mov.w r1, r1, rrx
800091e: f102 0201 add.w r2, r2, #1
8000922: 2afe cmp r2, #254 @ 0xfe
8000924: d251 bcs.n 80009ca <__addsf3+0x136>
8000926: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
800092a: eb40 50c2 adc.w r0, r0, r2, lsl #23
800092e: bf08 it eq
8000930: f020 0001 biceq.w r0, r0, #1
8000934: ea40 0003 orr.w r0, r0, r3
8000938: 4770 bx lr
800093a: 0049 lsls r1, r1, #1
800093c: eb40 0000 adc.w r0, r0, r0
8000940: 3a01 subs r2, #1
8000942: bf28 it cs
8000944: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
8000948: d2ed bcs.n 8000926 <__addsf3+0x92>
800094a: fab0 fc80 clz ip, r0
800094e: f1ac 0c08 sub.w ip, ip, #8
8000952: ebb2 020c subs.w r2, r2, ip
8000956: fa00 f00c lsl.w r0, r0, ip
800095a: bfaa itet ge
800095c: eb00 50c2 addge.w r0, r0, r2, lsl #23
8000960: 4252 neglt r2, r2
8000962: 4318 orrge r0, r3
8000964: bfbc itt lt
8000966: 40d0 lsrlt r0, r2
8000968: 4318 orrlt r0, r3
800096a: 4770 bx lr
800096c: f092 0f00 teq r2, #0
8000970: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
8000974: bf06 itte eq
8000976: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
800097a: 3201 addeq r2, #1
800097c: 3b01 subne r3, #1
800097e: e7b5 b.n 80008ec <__addsf3+0x58>
8000980: ea4f 0341 mov.w r3, r1, lsl #1
8000984: ea7f 6c22 mvns.w ip, r2, asr #24
8000988: bf18 it ne
800098a: ea7f 6c23 mvnsne.w ip, r3, asr #24
800098e: d021 beq.n 80009d4 <__addsf3+0x140>
8000990: ea92 0f03 teq r2, r3
8000994: d004 beq.n 80009a0 <__addsf3+0x10c>
8000996: f092 0f00 teq r2, #0
800099a: bf08 it eq
800099c: 4608 moveq r0, r1
800099e: 4770 bx lr
80009a0: ea90 0f01 teq r0, r1
80009a4: bf1c itt ne
80009a6: 2000 movne r0, #0
80009a8: 4770 bxne lr
80009aa: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
80009ae: d104 bne.n 80009ba <__addsf3+0x126>
80009b0: 0040 lsls r0, r0, #1
80009b2: bf28 it cs
80009b4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
80009b8: 4770 bx lr
80009ba: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
80009be: bf3c itt cc
80009c0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
80009c4: 4770 bxcc lr
80009c6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
80009ca: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
80009ce: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80009d2: 4770 bx lr
80009d4: ea7f 6222 mvns.w r2, r2, asr #24
80009d8: bf16 itet ne
80009da: 4608 movne r0, r1
80009dc: ea7f 6323 mvnseq.w r3, r3, asr #24
80009e0: 4601 movne r1, r0
80009e2: 0242 lsls r2, r0, #9
80009e4: bf06 itte eq
80009e6: ea5f 2341 movseq.w r3, r1, lsl #9
80009ea: ea90 0f01 teqeq r0, r1
80009ee: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
80009f2: 4770 bx lr
080009f4 <__aeabi_ui2f>:
80009f4: f04f 0300 mov.w r3, #0
80009f8: e004 b.n 8000a04 <__aeabi_i2f+0x8>
80009fa: bf00 nop
080009fc <__aeabi_i2f>:
80009fc: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
8000a00: bf48 it mi
8000a02: 4240 negmi r0, r0
8000a04: ea5f 0c00 movs.w ip, r0
8000a08: bf08 it eq
8000a0a: 4770 bxeq lr
8000a0c: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
8000a10: 4601 mov r1, r0
8000a12: f04f 0000 mov.w r0, #0
8000a16: e01c b.n 8000a52 <__aeabi_l2f+0x2a>
08000a18 <__aeabi_ul2f>:
8000a18: ea50 0201 orrs.w r2, r0, r1
8000a1c: bf08 it eq
8000a1e: 4770 bxeq lr
8000a20: f04f 0300 mov.w r3, #0
8000a24: e00a b.n 8000a3c <__aeabi_l2f+0x14>
8000a26: bf00 nop
08000a28 <__aeabi_l2f>:
8000a28: ea50 0201 orrs.w r2, r0, r1
8000a2c: bf08 it eq
8000a2e: 4770 bxeq lr
8000a30: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
8000a34: d502 bpl.n 8000a3c <__aeabi_l2f+0x14>
8000a36: 4240 negs r0, r0
8000a38: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000a3c: ea5f 0c01 movs.w ip, r1
8000a40: bf02 ittt eq
8000a42: 4684 moveq ip, r0
8000a44: 4601 moveq r1, r0
8000a46: 2000 moveq r0, #0
8000a48: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
8000a4c: bf08 it eq
8000a4e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
8000a52: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
8000a56: fabc f28c clz r2, ip
8000a5a: 3a08 subs r2, #8
8000a5c: eba3 53c2 sub.w r3, r3, r2, lsl #23
8000a60: db10 blt.n 8000a84 <__aeabi_l2f+0x5c>
8000a62: fa01 fc02 lsl.w ip, r1, r2
8000a66: 4463 add r3, ip
8000a68: fa00 fc02 lsl.w ip, r0, r2
8000a6c: f1c2 0220 rsb r2, r2, #32
8000a70: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000a74: fa20 f202 lsr.w r2, r0, r2
8000a78: eb43 0002 adc.w r0, r3, r2
8000a7c: bf08 it eq
8000a7e: f020 0001 biceq.w r0, r0, #1
8000a82: 4770 bx lr
8000a84: f102 0220 add.w r2, r2, #32
8000a88: fa01 fc02 lsl.w ip, r1, r2
8000a8c: f1c2 0220 rsb r2, r2, #32
8000a90: ea50 004c orrs.w r0, r0, ip, lsl #1
8000a94: fa21 f202 lsr.w r2, r1, r2
8000a98: eb43 0002 adc.w r0, r3, r2
8000a9c: bf08 it eq
8000a9e: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000aa2: 4770 bx lr
08000aa4 <__aeabi_fmul>:
8000aa4: f04f 0cff mov.w ip, #255 @ 0xff
8000aa8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000aac: bf1e ittt ne
8000aae: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000ab2: ea92 0f0c teqne r2, ip
8000ab6: ea93 0f0c teqne r3, ip
8000aba: d06f beq.n 8000b9c <__aeabi_fmul+0xf8>
8000abc: 441a add r2, r3
8000abe: ea80 0c01 eor.w ip, r0, r1
8000ac2: 0240 lsls r0, r0, #9
8000ac4: bf18 it ne
8000ac6: ea5f 2141 movsne.w r1, r1, lsl #9
8000aca: d01e beq.n 8000b0a <__aeabi_fmul+0x66>
8000acc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000ad0: ea43 1050 orr.w r0, r3, r0, lsr #5
8000ad4: ea43 1151 orr.w r1, r3, r1, lsr #5
8000ad8: fba0 3101 umull r3, r1, r0, r1
8000adc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000ae0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8000ae4: bf3e ittt cc
8000ae6: 0049 lslcc r1, r1, #1
8000ae8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
8000aec: 005b lslcc r3, r3, #1
8000aee: ea40 0001 orr.w r0, r0, r1
8000af2: f162 027f sbc.w r2, r2, #127 @ 0x7f
8000af6: 2afd cmp r2, #253 @ 0xfd
8000af8: d81d bhi.n 8000b36 <__aeabi_fmul+0x92>
8000afa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8000afe: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000b02: bf08 it eq
8000b04: f020 0001 biceq.w r0, r0, #1
8000b08: 4770 bx lr
8000b0a: f090 0f00 teq r0, #0
8000b0e: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000b12: bf08 it eq
8000b14: 0249 lsleq r1, r1, #9
8000b16: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000b1a: ea40 2051 orr.w r0, r0, r1, lsr #9
8000b1e: 3a7f subs r2, #127 @ 0x7f
8000b20: bfc2 ittt gt
8000b22: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000b26: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000b2a: 4770 bxgt lr
8000b2c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000b30: f04f 0300 mov.w r3, #0
8000b34: 3a01 subs r2, #1
8000b36: dc5d bgt.n 8000bf4 <__aeabi_fmul+0x150>
8000b38: f112 0f19 cmn.w r2, #25
8000b3c: bfdc itt le
8000b3e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
8000b42: 4770 bxle lr
8000b44: f1c2 0200 rsb r2, r2, #0
8000b48: 0041 lsls r1, r0, #1
8000b4a: fa21 f102 lsr.w r1, r1, r2
8000b4e: f1c2 0220 rsb r2, r2, #32
8000b52: fa00 fc02 lsl.w ip, r0, r2
8000b56: ea5f 0031 movs.w r0, r1, rrx
8000b5a: f140 0000 adc.w r0, r0, #0
8000b5e: ea53 034c orrs.w r3, r3, ip, lsl #1
8000b62: bf08 it eq
8000b64: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000b68: 4770 bx lr
8000b6a: f092 0f00 teq r2, #0
8000b6e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000b72: bf02 ittt eq
8000b74: 0040 lsleq r0, r0, #1
8000b76: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000b7a: 3a01 subeq r2, #1
8000b7c: d0f9 beq.n 8000b72 <__aeabi_fmul+0xce>
8000b7e: ea40 000c orr.w r0, r0, ip
8000b82: f093 0f00 teq r3, #0
8000b86: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000b8a: bf02 ittt eq
8000b8c: 0049 lsleq r1, r1, #1
8000b8e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000b92: 3b01 subeq r3, #1
8000b94: d0f9 beq.n 8000b8a <__aeabi_fmul+0xe6>
8000b96: ea41 010c orr.w r1, r1, ip
8000b9a: e78f b.n 8000abc <__aeabi_fmul+0x18>
8000b9c: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000ba0: ea92 0f0c teq r2, ip
8000ba4: bf18 it ne
8000ba6: ea93 0f0c teqne r3, ip
8000baa: d00a beq.n 8000bc2 <__aeabi_fmul+0x11e>
8000bac: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000bb0: bf18 it ne
8000bb2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000bb6: d1d8 bne.n 8000b6a <__aeabi_fmul+0xc6>
8000bb8: ea80 0001 eor.w r0, r0, r1
8000bbc: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bc0: 4770 bx lr
8000bc2: f090 0f00 teq r0, #0
8000bc6: bf17 itett ne
8000bc8: f090 4f00 teqne r0, #2147483648 @ 0x80000000
8000bcc: 4608 moveq r0, r1
8000bce: f091 0f00 teqne r1, #0
8000bd2: f091 4f00 teqne r1, #2147483648 @ 0x80000000
8000bd6: d014 beq.n 8000c02 <__aeabi_fmul+0x15e>
8000bd8: ea92 0f0c teq r2, ip
8000bdc: d101 bne.n 8000be2 <__aeabi_fmul+0x13e>
8000bde: 0242 lsls r2, r0, #9
8000be0: d10f bne.n 8000c02 <__aeabi_fmul+0x15e>
8000be2: ea93 0f0c teq r3, ip
8000be6: d103 bne.n 8000bf0 <__aeabi_fmul+0x14c>
8000be8: 024b lsls r3, r1, #9
8000bea: bf18 it ne
8000bec: 4608 movne r0, r1
8000bee: d108 bne.n 8000c02 <__aeabi_fmul+0x15e>
8000bf0: ea80 0001 eor.w r0, r0, r1
8000bf4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000bf8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000bfc: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c00: 4770 bx lr
8000c02: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000c06: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
8000c0a: 4770 bx lr
08000c0c <__aeabi_fdiv>:
8000c0c: f04f 0cff mov.w ip, #255 @ 0xff
8000c10: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000c14: bf1e ittt ne
8000c16: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000c1a: ea92 0f0c teqne r2, ip
8000c1e: ea93 0f0c teqne r3, ip
8000c22: d069 beq.n 8000cf8 <__aeabi_fdiv+0xec>
8000c24: eba2 0203 sub.w r2, r2, r3
8000c28: ea80 0c01 eor.w ip, r0, r1
8000c2c: 0249 lsls r1, r1, #9
8000c2e: ea4f 2040 mov.w r0, r0, lsl #9
8000c32: d037 beq.n 8000ca4 <__aeabi_fdiv+0x98>
8000c34: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8000c38: ea43 1111 orr.w r1, r3, r1, lsr #4
8000c3c: ea43 1310 orr.w r3, r3, r0, lsr #4
8000c40: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000c44: 428b cmp r3, r1
8000c46: bf38 it cc
8000c48: 005b lslcc r3, r3, #1
8000c4a: f142 027d adc.w r2, r2, #125 @ 0x7d
8000c4e: f44f 0c00 mov.w ip, #8388608 @ 0x800000
8000c52: 428b cmp r3, r1
8000c54: bf24 itt cs
8000c56: 1a5b subcs r3, r3, r1
8000c58: ea40 000c orrcs.w r0, r0, ip
8000c5c: ebb3 0f51 cmp.w r3, r1, lsr #1
8000c60: bf24 itt cs
8000c62: eba3 0351 subcs.w r3, r3, r1, lsr #1
8000c66: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000c6a: ebb3 0f91 cmp.w r3, r1, lsr #2
8000c6e: bf24 itt cs
8000c70: eba3 0391 subcs.w r3, r3, r1, lsr #2
8000c74: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000c78: ebb3 0fd1 cmp.w r3, r1, lsr #3
8000c7c: bf24 itt cs
8000c7e: eba3 03d1 subcs.w r3, r3, r1, lsr #3
8000c82: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000c86: 011b lsls r3, r3, #4
8000c88: bf18 it ne
8000c8a: ea5f 1c1c movsne.w ip, ip, lsr #4
8000c8e: d1e0 bne.n 8000c52 <__aeabi_fdiv+0x46>
8000c90: 2afd cmp r2, #253 @ 0xfd
8000c92: f63f af50 bhi.w 8000b36 <__aeabi_fmul+0x92>
8000c96: 428b cmp r3, r1
8000c98: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000c9c: bf08 it eq
8000c9e: f020 0001 biceq.w r0, r0, #1
8000ca2: 4770 bx lr
8000ca4: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000ca8: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000cac: 327f adds r2, #127 @ 0x7f
8000cae: bfc2 ittt gt
8000cb0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000cb4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000cb8: 4770 bxgt lr
8000cba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000cbe: f04f 0300 mov.w r3, #0
8000cc2: 3a01 subs r2, #1
8000cc4: e737 b.n 8000b36 <__aeabi_fmul+0x92>
8000cc6: f092 0f00 teq r2, #0
8000cca: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000cce: bf02 ittt eq
8000cd0: 0040 lsleq r0, r0, #1
8000cd2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000cd6: 3a01 subeq r2, #1
8000cd8: d0f9 beq.n 8000cce <__aeabi_fdiv+0xc2>
8000cda: ea40 000c orr.w r0, r0, ip
8000cde: f093 0f00 teq r3, #0
8000ce2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000ce6: bf02 ittt eq
8000ce8: 0049 lsleq r1, r1, #1
8000cea: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000cee: 3b01 subeq r3, #1
8000cf0: d0f9 beq.n 8000ce6 <__aeabi_fdiv+0xda>
8000cf2: ea41 010c orr.w r1, r1, ip
8000cf6: e795 b.n 8000c24 <__aeabi_fdiv+0x18>
8000cf8: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000cfc: ea92 0f0c teq r2, ip
8000d00: d108 bne.n 8000d14 <__aeabi_fdiv+0x108>
8000d02: 0242 lsls r2, r0, #9
8000d04: f47f af7d bne.w 8000c02 <__aeabi_fmul+0x15e>
8000d08: ea93 0f0c teq r3, ip
8000d0c: f47f af70 bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d10: 4608 mov r0, r1
8000d12: e776 b.n 8000c02 <__aeabi_fmul+0x15e>
8000d14: ea93 0f0c teq r3, ip
8000d18: d104 bne.n 8000d24 <__aeabi_fdiv+0x118>
8000d1a: 024b lsls r3, r1, #9
8000d1c: f43f af4c beq.w 8000bb8 <__aeabi_fmul+0x114>
8000d20: 4608 mov r0, r1
8000d22: e76e b.n 8000c02 <__aeabi_fmul+0x15e>
8000d24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000d28: bf18 it ne
8000d2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000d2e: d1ca bne.n 8000cc6 <__aeabi_fdiv+0xba>
8000d30: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
8000d34: f47f af5c bne.w 8000bf0 <__aeabi_fmul+0x14c>
8000d38: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
8000d3c: f47f af3c bne.w 8000bb8 <__aeabi_fmul+0x114>
8000d40: e75f b.n 8000c02 <__aeabi_fmul+0x15e>
8000d42: bf00 nop
08000d44 <__gesf2>:
8000d44: f04f 3cff mov.w ip, #4294967295
8000d48: e006 b.n 8000d58 <__cmpsf2+0x4>
8000d4a: bf00 nop
08000d4c <__lesf2>:
8000d4c: f04f 0c01 mov.w ip, #1
8000d50: e002 b.n 8000d58 <__cmpsf2+0x4>
8000d52: bf00 nop
08000d54 <__cmpsf2>:
8000d54: f04f 0c01 mov.w ip, #1
8000d58: f84d cd04 str.w ip, [sp, #-4]!
8000d5c: ea4f 0240 mov.w r2, r0, lsl #1
8000d60: ea4f 0341 mov.w r3, r1, lsl #1
8000d64: ea7f 6c22 mvns.w ip, r2, asr #24
8000d68: bf18 it ne
8000d6a: ea7f 6c23 mvnsne.w ip, r3, asr #24
8000d6e: d011 beq.n 8000d94 <__cmpsf2+0x40>
8000d70: b001 add sp, #4
8000d72: ea52 0c53 orrs.w ip, r2, r3, lsr #1
8000d76: bf18 it ne
8000d78: ea90 0f01 teqne r0, r1
8000d7c: bf58 it pl
8000d7e: ebb2 0003 subspl.w r0, r2, r3
8000d82: bf88 it hi
8000d84: 17c8 asrhi r0, r1, #31
8000d86: bf38 it cc
8000d88: ea6f 70e1 mvncc.w r0, r1, asr #31
8000d8c: bf18 it ne
8000d8e: f040 0001 orrne.w r0, r0, #1
8000d92: 4770 bx lr
8000d94: ea7f 6c22 mvns.w ip, r2, asr #24
8000d98: d102 bne.n 8000da0 <__cmpsf2+0x4c>
8000d9a: ea5f 2c40 movs.w ip, r0, lsl #9
8000d9e: d105 bne.n 8000dac <__cmpsf2+0x58>
8000da0: ea7f 6c23 mvns.w ip, r3, asr #24
8000da4: d1e4 bne.n 8000d70 <__cmpsf2+0x1c>
8000da6: ea5f 2c41 movs.w ip, r1, lsl #9
8000daa: d0e1 beq.n 8000d70 <__cmpsf2+0x1c>
8000dac: f85d 0b04 ldr.w r0, [sp], #4
8000db0: 4770 bx lr
8000db2: bf00 nop
08000db4 <__aeabi_cfrcmple>:
8000db4: 4684 mov ip, r0
8000db6: 4608 mov r0, r1
8000db8: 4661 mov r1, ip
8000dba: e7ff b.n 8000dbc <__aeabi_cfcmpeq>
08000dbc <__aeabi_cfcmpeq>:
8000dbc: b50f push {r0, r1, r2, r3, lr}
8000dbe: f7ff ffc9 bl 8000d54 <__cmpsf2>
8000dc2: 2800 cmp r0, #0
8000dc4: bf48 it mi
8000dc6: f110 0f00 cmnmi.w r0, #0
8000dca: bd0f pop {r0, r1, r2, r3, pc}
08000dcc <__aeabi_fcmpeq>:
8000dcc: f84d ed08 str.w lr, [sp, #-8]!
8000dd0: f7ff fff4 bl 8000dbc <__aeabi_cfcmpeq>
8000dd4: bf0c ite eq
8000dd6: 2001 moveq r0, #1
8000dd8: 2000 movne r0, #0
8000dda: f85d fb08 ldr.w pc, [sp], #8
8000dde: bf00 nop
08000de0 <__aeabi_fcmplt>:
8000de0: f84d ed08 str.w lr, [sp, #-8]!
8000de4: f7ff ffea bl 8000dbc <__aeabi_cfcmpeq>
8000de8: bf34 ite cc
8000dea: 2001 movcc r0, #1
8000dec: 2000 movcs r0, #0
8000dee: f85d fb08 ldr.w pc, [sp], #8
8000df2: bf00 nop
08000df4 <__aeabi_fcmple>:
8000df4: f84d ed08 str.w lr, [sp, #-8]!
8000df8: f7ff ffe0 bl 8000dbc <__aeabi_cfcmpeq>
8000dfc: bf94 ite ls
8000dfe: 2001 movls r0, #1
8000e00: 2000 movhi r0, #0
8000e02: f85d fb08 ldr.w pc, [sp], #8
8000e06: bf00 nop
08000e08 <__aeabi_fcmpge>:
8000e08: f84d ed08 str.w lr, [sp, #-8]!
8000e0c: f7ff ffd2 bl 8000db4 <__aeabi_cfrcmple>
8000e10: bf94 ite ls
8000e12: 2001 movls r0, #1
8000e14: 2000 movhi r0, #0
8000e16: f85d fb08 ldr.w pc, [sp], #8
8000e1a: bf00 nop
08000e1c <__aeabi_fcmpgt>:
8000e1c: f84d ed08 str.w lr, [sp, #-8]!
8000e20: f7ff ffc8 bl 8000db4 <__aeabi_cfrcmple>
8000e24: bf34 ite cc
8000e26: 2001 movcc r0, #1
8000e28: 2000 movcs r0, #0
8000e2a: f85d fb08 ldr.w pc, [sp], #8
8000e2e: bf00 nop
08000e30 <__aeabi_fcmpun>:
8000e30: ea4f 0240 mov.w r2, r0, lsl #1
8000e34: ea4f 0341 mov.w r3, r1, lsl #1
8000e38: ea7f 6c22 mvns.w ip, r2, asr #24
8000e3c: d102 bne.n 8000e44 <__aeabi_fcmpun+0x14>
8000e3e: ea5f 2c40 movs.w ip, r0, lsl #9
8000e42: d108 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e44: ea7f 6c23 mvns.w ip, r3, asr #24
8000e48: d102 bne.n 8000e50 <__aeabi_fcmpun+0x20>
8000e4a: ea5f 2c41 movs.w ip, r1, lsl #9
8000e4e: d102 bne.n 8000e56 <__aeabi_fcmpun+0x26>
8000e50: f04f 0000 mov.w r0, #0
8000e54: 4770 bx lr
8000e56: f04f 0001 mov.w r0, #1
8000e5a: 4770 bx lr
08000e5c <__aeabi_f2iz>:
8000e5c: ea4f 0240 mov.w r2, r0, lsl #1
8000e60: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
8000e64: d30f bcc.n 8000e86 <__aeabi_f2iz+0x2a>
8000e66: f04f 039e mov.w r3, #158 @ 0x9e
8000e6a: ebb3 6212 subs.w r2, r3, r2, lsr #24
8000e6e: d90d bls.n 8000e8c <__aeabi_f2iz+0x30>
8000e70: ea4f 2300 mov.w r3, r0, lsl #8
8000e74: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000e78: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
8000e7c: fa23 f002 lsr.w r0, r3, r2
8000e80: bf18 it ne
8000e82: 4240 negne r0, r0
8000e84: 4770 bx lr
8000e86: f04f 0000 mov.w r0, #0
8000e8a: 4770 bx lr
8000e8c: f112 0f61 cmn.w r2, #97 @ 0x61
8000e90: d101 bne.n 8000e96 <__aeabi_f2iz+0x3a>
8000e92: 0242 lsls r2, r0, #9
8000e94: d105 bne.n 8000ea2 <__aeabi_f2iz+0x46>
8000e96: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000
8000e9a: bf08 it eq
8000e9c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000ea0: 4770 bx lr
8000ea2: f04f 0000 mov.w r0, #0
8000ea6: 4770 bx lr
08000ea8 <AD5934_SetRegisterValue>:
* @param numberOfBytes - Number of bytes to be written in the register
*
* @return None.
******************************************************************************/
void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
{
8000ea8: b580 push {r7, lr}
8000eaa: b086 sub sp, #24
8000eac: af02 add r7, sp, #8
8000eae: 4603 mov r3, r0
8000eb0: 6039 str r1, [r7, #0]
8000eb2: 71fb strb r3, [r7, #7]
8000eb4: 4613 mov r3, r2
8000eb6: 71bb strb r3, [r7, #6]
uint8_t writeData[2] = {0, 0};
8000eb8: 2300 movs r3, #0
8000eba: 81bb strh r3, [r7, #12]
HAL_StatusTypeDef status;
union Bytes2Long AD5934_reg;
AD5934_reg.number = registerValue;
8000ebc: 683b ldr r3, [r7, #0]
8000ebe: 60bb str r3, [r7, #8]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ec0: 2300 movs r3, #0
8000ec2: 73fb strb r3, [r7, #15]
8000ec4: e018 b.n 8000ef8 <AD5934_SetRegisterValue+0x50>
{
writeData[0] = registerAddress - i;
8000ec6: 79fa ldrb r2, [r7, #7]
8000ec8: 7bfb ldrb r3, [r7, #15]
8000eca: 1ad3 subs r3, r2, r3
8000ecc: b2db uxtb r3, r3
8000ece: 733b strb r3, [r7, #12]
writeData[1] = AD5934_reg.bytes[i];
8000ed0: 7bfb ldrb r3, [r7, #15]
8000ed2: 3310 adds r3, #16
8000ed4: 443b add r3, r7
8000ed6: f813 3c08 ldrb.w r3, [r3, #-8]
8000eda: 737b strb r3, [r7, #13]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000edc: f107 020c add.w r2, r7, #12
8000ee0: 2305 movs r3, #5
8000ee2: 9300 str r3, [sp, #0]
8000ee4: 2302 movs r3, #2
8000ee6: 211a movs r1, #26
8000ee8: 4807 ldr r0, [pc, #28] @ (8000f08 <AD5934_SetRegisterValue+0x60>)
8000eea: f003 f90d bl 8004108 <HAL_I2C_Master_Transmit>
8000eee: 4603 mov r3, r0
8000ef0: 73bb strb r3, [r7, #14]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000ef2: 7bfb ldrb r3, [r7, #15]
8000ef4: 3301 adds r3, #1
8000ef6: 73fb strb r3, [r7, #15]
8000ef8: 7bfa ldrb r2, [r7, #15]
8000efa: 79bb ldrb r3, [r7, #6]
8000efc: 429a cmp r2, r3
8000efe: d3e2 bcc.n 8000ec6 <AD5934_SetRegisterValue+0x1e>
}
return;
8000f00: bf00 nop
}
8000f02: 3710 adds r7, #16
8000f04: 46bd mov sp, r7
8000f06: bd80 pop {r7, pc}
8000f08: 20000678 .word 0x20000678
08000f0c <AD5934_GetRegisterValue>:
* @param numberOfBytes - Number of bytes to be read from the register.
*
* @return Register value.
******************************************************************************/
uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
{
8000f0c: b580 push {r7, lr}
8000f0e: b088 sub sp, #32
8000f10: af02 add r7, sp, #8
8000f12: 4603 mov r3, r0
8000f14: 460a mov r2, r1
8000f16: 71fb strb r3, [r7, #7]
8000f18: 4613 mov r3, r2
8000f1a: 71bb strb r3, [r7, #6]
uint8_t readData[1] = {0};
8000f1c: 2300 movs r3, #0
8000f1e: 753b strb r3, [r7, #20]
uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
union Bytes2Long AD5934_reg;
HAL_StatusTypeDef status;
if(numberOfBytes > 4)
8000f20: 79bb ldrb r3, [r7, #6]
8000f22: 2b04 cmp r3, #4
8000f24: d902 bls.n 8000f2c <AD5934_GetRegisterValue+0x20>
return 0xFFFFFFFF; //Overflow
8000f26: f04f 33ff mov.w r3, #4294967295
8000f2a: e031 b.n 8000f90 <AD5934_GetRegisterValue+0x84>
AD5934_reg.number = 0;
8000f2c: 2300 movs r3, #0
8000f2e: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f30: 2300 movs r3, #0
8000f32: 75fb strb r3, [r7, #23]
8000f34: e027 b.n 8000f86 <AD5934_GetRegisterValue+0x7a>
{
writeData[0] = AD5934_ADDR_POINTER;
8000f36: 23b0 movs r3, #176 @ 0xb0
8000f38: 743b strb r3, [r7, #16]
writeData[1] = registerAddress - i;
8000f3a: 79fa ldrb r2, [r7, #7]
8000f3c: 7dfb ldrb r3, [r7, #23]
8000f3e: 1ad3 subs r3, r2, r3
8000f40: b2db uxtb r3, r3
8000f42: 747b strb r3, [r7, #17]
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
8000f44: f107 0210 add.w r2, r7, #16
8000f48: 2305 movs r3, #5
8000f4a: 9300 str r3, [sp, #0]
8000f4c: 2302 movs r3, #2
8000f4e: 211a movs r1, #26
8000f50: 4811 ldr r0, [pc, #68] @ (8000f98 <AD5934_GetRegisterValue+0x8c>)
8000f52: f003 f8d9 bl 8004108 <HAL_I2C_Master_Transmit>
8000f56: 4603 mov r3, r0
8000f58: 75bb strb r3, [r7, #22]
//HAL_Delay(1);
readData[0] = 0;
8000f5a: 2300 movs r3, #0
8000f5c: 753b strb r3, [r7, #20]
status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
8000f5e: f107 0214 add.w r2, r7, #20
8000f62: 2305 movs r3, #5
8000f64: 9300 str r3, [sp, #0]
8000f66: 2301 movs r3, #1
8000f68: 211a movs r1, #26
8000f6a: 480b ldr r0, [pc, #44] @ (8000f98 <AD5934_GetRegisterValue+0x8c>)
8000f6c: f003 f9ca bl 8004304 <HAL_I2C_Master_Receive>
8000f70: 4603 mov r3, r0
8000f72: 75bb strb r3, [r7, #22]
AD5934_reg.bytes[i]=readData[0];
8000f74: 7dfb ldrb r3, [r7, #23]
8000f76: 7d3a ldrb r2, [r7, #20]
8000f78: 3318 adds r3, #24
8000f7a: 443b add r3, r7
8000f7c: f803 2c0c strb.w r2, [r3, #-12]
for (uint8_t i = 0; i < numberOfBytes; i++)
8000f80: 7dfb ldrb r3, [r7, #23]
8000f82: 3301 adds r3, #1
8000f84: 75fb strb r3, [r7, #23]
8000f86: 7dfa ldrb r2, [r7, #23]
8000f88: 79bb ldrb r3, [r7, #6]
8000f8a: 429a cmp r2, r3
8000f8c: d3d3 bcc.n 8000f36 <AD5934_GetRegisterValue+0x2a>
/*
AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048;
AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048;
*/
return AD5934_reg.number;
8000f8e: 68fb ldr r3, [r7, #12]
}
8000f90: 4618 mov r0, r3
8000f92: 3718 adds r7, #24
8000f94: 46bd mov sp, r7
8000f96: bd80 pop {r7, pc}
8000f98: 20000678 .word 0x20000678
08000f9c <AD5934_Init>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_Init(void)
{
8000f9c: b580 push {r7, lr}
8000f9e: af00 add r7, sp, #0
/************ Config Sweep******************/
// Place AD5934 in reset
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
8000fa0: 2201 movs r2, #1
8000fa2: f44f 7180 mov.w r1, #256 @ 0x100
8000fa6: 2081 movs r0, #129 @ 0x81
8000fa8: f7ff ff7e bl 8000ea8 <AD5934_SetRegisterValue>
// Configure starting frequency
AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_2K5HZ, 3);
8000fac: 2203 movs r2, #3
8000fae: 490a ldr r1, [pc, #40] @ (8000fd8 <AD5934_Init+0x3c>)
8000fb0: 2084 movs r0, #132 @ 0x84
8000fb2: f7ff ff79 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure frequency increment step
AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
8000fb6: 2203 movs r2, #3
8000fb8: 2100 movs r1, #0
8000fba: 2087 movs r0, #135 @ 0x87
8000fbc: f7ff ff74 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure number of steps
AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
8000fc0: 2202 movs r2, #2
8000fc2: 2100 movs r1, #0
8000fc4: 2089 movs r0, #137 @ 0x89
8000fc6: f7ff ff6f bl 8000ea8 <AD5934_SetRegisterValue>
// Set 128 Settling Time
AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_0S01, 2);
8000fca: 2202 movs r2, #2
8000fcc: 2180 movs r1, #128 @ 0x80
8000fce: 208b movs r0, #139 @ 0x8b
8000fd0: f7ff ff6a bl 8000ea8 <AD5934_SetRegisterValue>
}
8000fd4: bf00 nop
8000fd6: bd80 pop {r7, pc}
8000fd8: 0051eb86 .word 0x0051eb86
08000fdc <AD5934_RestartSweep>:
* @param None.
*
* @return None.
******************************************************************************/
void AD5934_RestartSweep(void)
{
8000fdc: b580 push {r7, lr}
8000fde: af00 add r7, sp, #0
// Place AD5934 in standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000fe0: 2201 movs r2, #1
8000fe2: 21b5 movs r1, #181 @ 0xb5
8000fe4: 2080 movs r0, #128 @ 0x80
8000fe6: f7ff ff5f bl 8000ea8 <AD5934_SetRegisterValue>
// Initialize starting frequency, Start frequency sweep, standby
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000fea: 2201 movs r2, #1
8000fec: 2115 movs r1, #21
8000fee: 2080 movs r0, #128 @ 0x80
8000ff0: f7ff ff5a bl 8000ea8 <AD5934_SetRegisterValue>
// Disable Internal Reset State
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, AD5934_CONTROL_FUNCTION(AD5934_RESERVED), 1);
8000ff4: 2201 movs r2, #1
8000ff6: 2180 movs r1, #128 @ 0x80
8000ff8: 2081 movs r0, #129 @ 0x81
8000ffa: f7ff ff55 bl 8000ea8 <AD5934_SetRegisterValue>
// Configure Range Output, PGA gain andPlace AD5934 in sweep
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
8000ffe: 2201 movs r2, #1
8001000: 2125 movs r1, #37 @ 0x25
8001002: 2080 movs r0, #128 @ 0x80
8001004: f7ff ff50 bl 8000ea8 <AD5934_SetRegisterValue>
// Wait for data to be valid
AD5934_Wait_For_Data_Valid();
8001008: f000 faa8 bl 800155c <AD5934_Wait_For_Data_Valid>
// Power Down
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
800100c: 2201 movs r2, #1
800100e: 21a5 movs r1, #165 @ 0xa5
8001010: 2080 movs r0, #128 @ 0x80
8001012: f7ff ff49 bl 8000ea8 <AD5934_SetRegisterValue>
}
8001016: bf00 nop
8001018: bd80 pop {r7, pc}
0800101a <AD5934_Sweep>:
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC
*
* @return Real(int16) and Imaginary(int16) numbers into a int32.
******************************************************************************/
uint32_t AD5934_Sweep(void)
{
800101a: b580 push {r7, lr}
800101c: b082 sub sp, #8
800101e: af00 add r7, sp, #0
int16_t real_value, imag_value;
uint32_t value=0;
8001020: 2300 movs r3, #0
8001022: 607b str r3, [r7, #4]
// Restart Sweeping
AD5934_RestartSweep();
8001024: f7ff ffda bl 8000fdc <AD5934_RestartSweep>
real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2)));
8001028: 2102 movs r1, #2
800102a: 2095 movs r0, #149 @ 0x95
800102c: f7ff ff6e bl 8000f0c <AD5934_GetRegisterValue>
8001030: 4603 mov r3, r0
8001032: 807b strh r3, [r7, #2]
imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2)));
8001034: 2102 movs r1, #2
8001036: 2097 movs r0, #151 @ 0x97
8001038: f7ff ff68 bl 8000f0c <AD5934_GetRegisterValue>
800103c: 4603 mov r3, r0
800103e: 803b strh r3, [r7, #0]
// Get Real (16-bit) and Imaginary (16-bit) values into an unsigned 32-bit
value = ((((uint16_t)(imag_value))<<16) | ((uint16_t)(real_value)));
8001040: 883b ldrh r3, [r7, #0]
8001042: 041b lsls r3, r3, #16
8001044: 887a ldrh r2, [r7, #2]
8001046: 4313 orrs r3, r2
8001048: 607b str r3, [r7, #4]
return value;
800104a: 687b ldr r3, [r7, #4]
}
800104c: 4618 mov r0, r3
800104e: 3708 adds r7, #8
8001050: 46bd mov sp, r7
8001052: bd80 pop {r7, pc}
08001054 <AD5934_Get_Ref_Resistance>:
* @param channel - AD5934_CH_PT100 or AD5934_CH_PT1000.
*
* @return impedance.
******************************************************************************/
float AD5934_Get_Ref_Resistance(void)
{
8001054: b590 push {r4, r7, lr}
8001056: b089 sub sp, #36 @ 0x24
8001058: af00 add r7, sp, #0
uint8_t i;
uint32_t sample;
int32_t ref_sum[2];
float real_ref,imag_ref, real_dut, mag_ref;
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
800105a: 2180 movs r1, #128 @ 0x80
800105c: 4841 ldr r0, [pc, #260] @ (8001164 <AD5934_Get_Ref_Resistance+0x110>)
800105e: f002 fec7 bl 8003df0 <HAL_GPIO_ReadPin>
8001062: 4603 mov r3, r0
8001064: 2b01 cmp r3, #1
8001066: d103 bne.n 8001070 <AD5934_Get_Ref_Resistance+0x1c>
ADG715_Update(AD5934_CH_REF100R_LOW_GAIN); // Set the Reference Resistor on board in the Analog Mux
8001068: 2000 movs r0, #0
800106a: f000 fbd5 bl 8001818 <ADG715_Update>
800106e: e002 b.n 8001076 <AD5934_Get_Ref_Resistance+0x22>
else
ADG715_Update(AD5934_CH_REF1K_MID_GAIN); // Set the Reference Resistor on board in the Analog Mux
8001070: 2004 movs r0, #4
8001072: f000 fbd1 bl 8001818 <ADG715_Update>
sample = AD5934_Sweep(); // Get Reference Resistor Values from ADC
8001076: f7ff ffd0 bl 800101a <AD5934_Sweep>
800107a: 61b8 str r0, [r7, #24]
// Move values in the vectors
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
800107c: 230f movs r3, #15
800107e: 77fb strb r3, [r7, #31]
8001080: e016 b.n 80010b0 <AD5934_Get_Ref_Resistance+0x5c>
{
temperature_ref_samples[0][i] = temperature_ref_samples[0][i-1]; //real
8001082: 7ffb ldrb r3, [r7, #31]
8001084: 1e5a subs r2, r3, #1
8001086: 7ffb ldrb r3, [r7, #31]
8001088: 4937 ldr r1, [pc, #220] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
800108a: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
800108e: 4a36 ldr r2, [pc, #216] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
8001090: f822 1013 strh.w r1, [r2, r3, lsl #1]
temperature_ref_samples[1][i] = temperature_ref_samples[1][i-1]; //imag
8001094: 7ffb ldrb r3, [r7, #31]
8001096: 1e5a subs r2, r3, #1
8001098: 7ffb ldrb r3, [r7, #31]
800109a: 4933 ldr r1, [pc, #204] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
800109c: 3210 adds r2, #16
800109e: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
80010a2: 4a31 ldr r2, [pc, #196] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
80010a4: 3310 adds r3, #16
80010a6: f822 1013 strh.w r1, [r2, r3, lsl #1]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80010aa: 7ffb ldrb r3, [r7, #31]
80010ac: 3b01 subs r3, #1
80010ae: 77fb strb r3, [r7, #31]
80010b0: 7ffb ldrb r3, [r7, #31]
80010b2: 2b00 cmp r3, #0
80010b4: d1e5 bne.n 8001082 <AD5934_Get_Ref_Resistance+0x2e>
}
// Read real and imaginary data
temperature_ref_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
80010b6: 69bb ldr r3, [r7, #24]
80010b8: b21a sxth r2, r3
80010ba: 4b2b ldr r3, [pc, #172] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
80010bc: 801a strh r2, [r3, #0]
//temperature_ref_samples[1][0] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
temperature_ref_samples[1][0] = (int16_t)((sample & 0xFFFF0000)>>16); //imag
80010be: 69bb ldr r3, [r7, #24]
80010c0: 0c1b lsrs r3, r3, #16
80010c2: b21a sxth r2, r3
80010c4: 4b28 ldr r3, [pc, #160] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
80010c6: 841a strh r2, [r3, #32]
// Sum values in the vectors
for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
80010c8: 2300 movs r3, #0
80010ca: 77fb strb r3, [r7, #31]
80010cc: 2300 movs r3, #0
80010ce: 607b str r3, [r7, #4]
80010d0: 2300 movs r3, #0
80010d2: 60bb str r3, [r7, #8]
80010d4: e011 b.n 80010fa <AD5934_Get_Ref_Resistance+0xa6>
{
ref_sum[0] += (int32_t)temperature_ref_samples[0][i]; //real
80010d6: 687b ldr r3, [r7, #4]
80010d8: 7ffa ldrb r2, [r7, #31]
80010da: 4923 ldr r1, [pc, #140] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
80010dc: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
80010e0: 4413 add r3, r2
80010e2: 607b str r3, [r7, #4]
ref_sum[1] += (int32_t)temperature_ref_samples[1][i]; //imag
80010e4: 68bb ldr r3, [r7, #8]
80010e6: 7ffa ldrb r2, [r7, #31]
80010e8: 491f ldr r1, [pc, #124] @ (8001168 <AD5934_Get_Ref_Resistance+0x114>)
80010ea: 3210 adds r2, #16
80010ec: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
80010f0: 4413 add r3, r2
80010f2: 60bb str r3, [r7, #8]
for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
80010f4: 7ffb ldrb r3, [r7, #31]
80010f6: 3301 adds r3, #1
80010f8: 77fb strb r3, [r7, #31]
80010fa: 7ffb ldrb r3, [r7, #31]
80010fc: 2b0f cmp r3, #15
80010fe: d9ea bls.n 80010d6 <AD5934_Get_Ref_Resistance+0x82>
}
real_ref = ((float)ref_sum[0])/((float)AD5934_TEMP_AVERAGES);
8001100: 687b ldr r3, [r7, #4]
8001102: 4618 mov r0, r3
8001104: f7ff fc7a bl 80009fc <__aeabi_i2f>
8001108: 4603 mov r3, r0
800110a: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
800110e: 4618 mov r0, r3
8001110: f7ff fd7c bl 8000c0c <__aeabi_fdiv>
8001114: 4603 mov r3, r0
8001116: 617b str r3, [r7, #20]
imag_ref = ((float)ref_sum[1])/((float)AD5934_TEMP_AVERAGES);
8001118: 68bb ldr r3, [r7, #8]
800111a: 4618 mov r0, r3
800111c: f7ff fc6e bl 80009fc <__aeabi_i2f>
8001120: 4603 mov r3, r0
8001122: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
8001126: 4618 mov r0, r3
8001128: f7ff fd70 bl 8000c0c <__aeabi_fdiv>
800112c: 4603 mov r3, r0
800112e: 613b str r3, [r7, #16]
// Calculate gain factor impedance
mag_ref = sqrtf((real_ref * real_ref) + (imag_ref * imag_ref));
8001130: 6979 ldr r1, [r7, #20]
8001132: 6978 ldr r0, [r7, #20]
8001134: f7ff fcb6 bl 8000aa4 <__aeabi_fmul>
8001138: 4603 mov r3, r0
800113a: 461c mov r4, r3
800113c: 6939 ldr r1, [r7, #16]
800113e: 6938 ldr r0, [r7, #16]
8001140: f7ff fcb0 bl 8000aa4 <__aeabi_fmul>
8001144: 4603 mov r3, r0
8001146: 4619 mov r1, r3
8001148: 4620 mov r0, r4
800114a: f7ff fba3 bl 8000894 <__addsf3>
800114e: 4603 mov r3, r0
8001150: 4618 mov r0, r3
8001152: f005 f9e7 bl 8006524 <sqrtf>
8001156: 60f8 str r0, [r7, #12]
return mag_ref;
8001158: 68fb ldr r3, [r7, #12]
}
800115a: 4618 mov r0, r3
800115c: 3724 adds r7, #36 @ 0x24
800115e: 46bd mov sp, r7
8001160: bd90 pop {r4, r7, pc}
8001162: bf00 nop
8001164: 40010800 .word 0x40010800
8001168: 200000ec .word 0x200000ec
0800116c <AD5934_GetTemperature>:
* @param channel - Magnitude of the Reference Resistor.
*
* @return impedance.
******************************************************************************/
float AD5934_GetTemperature(float mag_ref)
{
800116c: b590 push {r4, r7, lr}
800116e: b08f sub sp, #60 @ 0x3c
8001170: af00 add r7, sp, #0
8001172: 6078 str r0, [r7, #4]
uint8_t i, ch_ref;
uint32_t sample;
int32_t dut_sum[2];
float real_dut, imag_dut, ratio, discriminant, mag_dut, ratio_mag, impedance_dut, temperature_sum, gain_factor, temp_result;
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
8001174: 2180 movs r1, #128 @ 0x80
8001176: 486e ldr r0, [pc, #440] @ (8001330 <AD5934_GetTemperature+0x1c4>)
8001178: f002 fe3a bl 8003df0 <HAL_GPIO_ReadPin>
800117c: 4603 mov r3, r0
800117e: 2b01 cmp r3, #1
8001180: d105 bne.n 800118e <AD5934_GetTemperature+0x22>
{
ch_ref = AD5934_CH_RTD_LOW_GAIN; //PT100
8001182: 2309 movs r3, #9
8001184: f887 3036 strb.w r3, [r7, #54] @ 0x36
gain_factor = AD5934_GAIN_FACTOR_100R;
8001188: 4b6a ldr r3, [pc, #424] @ (8001334 <AD5934_GetTemperature+0x1c8>)
800118a: 62fb str r3, [r7, #44] @ 0x2c
800118c: e004 b.n 8001198 <AD5934_GetTemperature+0x2c>
}
else
{
ch_ref = AD5934_CH_RTD_MID_GAIN; //PT1000
800118e: 230a movs r3, #10
8001190: f887 3036 strb.w r3, [r7, #54] @ 0x36
gain_factor = AD5934_GAIN_FACTOR_1K;
8001194: 4b68 ldr r3, [pc, #416] @ (8001338 <AD5934_GetTemperature+0x1cc>)
8001196: 62fb str r3, [r7, #44] @ 0x2c
}
ADG715_Update(ch_ref);
8001198: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
800119c: 4618 mov r0, r3
800119e: f000 fb3b bl 8001818 <ADG715_Update>
sample = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
80011a2: f7ff ff3a bl 800101a <AD5934_Sweep>
80011a6: 62b8 str r0, [r7, #40] @ 0x28
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80011a8: 230f movs r3, #15
80011aa: f887 3037 strb.w r3, [r7, #55] @ 0x37
80011ae: e01c b.n 80011ea <AD5934_GetTemperature+0x7e>
{
temperature_dut_samples[0][i] = temperature_dut_samples[0][i-1]; //real
80011b0: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011b4: 1e5a subs r2, r3, #1
80011b6: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011ba: 4960 ldr r1, [pc, #384] @ (800133c <AD5934_GetTemperature+0x1d0>)
80011bc: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
80011c0: 4a5e ldr r2, [pc, #376] @ (800133c <AD5934_GetTemperature+0x1d0>)
80011c2: f822 1013 strh.w r1, [r2, r3, lsl #1]
temperature_dut_samples[1][i] = temperature_dut_samples[1][i-1]; //imag
80011c6: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011ca: 1e5a subs r2, r3, #1
80011cc: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011d0: 495a ldr r1, [pc, #360] @ (800133c <AD5934_GetTemperature+0x1d0>)
80011d2: 3210 adds r2, #16
80011d4: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
80011d8: 4a58 ldr r2, [pc, #352] @ (800133c <AD5934_GetTemperature+0x1d0>)
80011da: 3310 adds r3, #16
80011dc: f822 1013 strh.w r1, [r2, r3, lsl #1]
for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
80011e0: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011e4: 3b01 subs r3, #1
80011e6: f887 3037 strb.w r3, [r7, #55] @ 0x37
80011ea: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80011ee: 2b00 cmp r3, #0
80011f0: d1de bne.n 80011b0 <AD5934_GetTemperature+0x44>
}
// Read real and imaginary data
temperature_dut_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
80011f2: 6abb ldr r3, [r7, #40] @ 0x28
80011f4: b21a sxth r2, r3
80011f6: 4b51 ldr r3, [pc, #324] @ (800133c <AD5934_GetTemperature+0x1d0>)
80011f8: 801a strh r2, [r3, #0]
//temperature_dut_samples[0][1] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
temperature_dut_samples[1][0] = (int16_t)((sample & 0xFFFF0000)>>16); //imag
80011fa: 6abb ldr r3, [r7, #40] @ 0x28
80011fc: 0c1b lsrs r3, r3, #16
80011fe: b21a sxth r2, r3
8001200: 4b4e ldr r3, [pc, #312] @ (800133c <AD5934_GetTemperature+0x1d0>)
8001202: 841a strh r2, [r3, #32]
for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001204: 2300 movs r3, #0
8001206: f887 3037 strb.w r3, [r7, #55] @ 0x37
800120a: 2300 movs r3, #0
800120c: 60bb str r3, [r7, #8]
800120e: 2300 movs r3, #0
8001210: 60fb str r3, [r7, #12]
8001212: e015 b.n 8001240 <AD5934_GetTemperature+0xd4>
{
dut_sum[0] += (int32_t)temperature_dut_samples[0][i]; //real
8001214: 68bb ldr r3, [r7, #8]
8001216: f897 2037 ldrb.w r2, [r7, #55] @ 0x37
800121a: 4948 ldr r1, [pc, #288] @ (800133c <AD5934_GetTemperature+0x1d0>)
800121c: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
8001220: 4413 add r3, r2
8001222: 60bb str r3, [r7, #8]
dut_sum[1] += (int32_t)temperature_dut_samples[1][i]; //imag
8001224: 68fb ldr r3, [r7, #12]
8001226: f897 2037 ldrb.w r2, [r7, #55] @ 0x37
800122a: 4944 ldr r1, [pc, #272] @ (800133c <AD5934_GetTemperature+0x1d0>)
800122c: 3210 adds r2, #16
800122e: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
8001232: 4413 add r3, r2
8001234: 60fb str r3, [r7, #12]
for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
8001236: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
800123a: 3301 adds r3, #1
800123c: f887 3037 strb.w r3, [r7, #55] @ 0x37
8001240: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
8001244: 2b0f cmp r3, #15
8001246: d9e5 bls.n 8001214 <AD5934_GetTemperature+0xa8>
}
real_dut = ((float)dut_sum[0])/((float)AD5934_TEMP_AVERAGES);
8001248: 68bb ldr r3, [r7, #8]
800124a: 4618 mov r0, r3
800124c: f7ff fbd6 bl 80009fc <__aeabi_i2f>
8001250: 4603 mov r3, r0
8001252: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
8001256: 4618 mov r0, r3
8001258: f7ff fcd8 bl 8000c0c <__aeabi_fdiv>
800125c: 4603 mov r3, r0
800125e: 627b str r3, [r7, #36] @ 0x24
imag_dut = ((float)dut_sum[1])/((float)AD5934_TEMP_AVERAGES);
8001260: 68fb ldr r3, [r7, #12]
8001262: 4618 mov r0, r3
8001264: f7ff fbca bl 80009fc <__aeabi_i2f>
8001268: 4603 mov r3, r0
800126a: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
800126e: 4618 mov r0, r3
8001270: f7ff fccc bl 8000c0c <__aeabi_fdiv>
8001274: 4603 mov r3, r0
8001276: 623b str r3, [r7, #32]
// Calculate magnitude
mag_dut = sqrtf((real_dut * real_dut) + (imag_dut * imag_dut));
8001278: 6a79 ldr r1, [r7, #36] @ 0x24
800127a: 6a78 ldr r0, [r7, #36] @ 0x24
800127c: f7ff fc12 bl 8000aa4 <__aeabi_fmul>
8001280: 4603 mov r3, r0
8001282: 461c mov r4, r3
8001284: 6a39 ldr r1, [r7, #32]
8001286: 6a38 ldr r0, [r7, #32]
8001288: f7ff fc0c bl 8000aa4 <__aeabi_fmul>
800128c: 4603 mov r3, r0
800128e: 4619 mov r1, r3
8001290: 4620 mov r0, r4
8001292: f7ff faff bl 8000894 <__addsf3>
8001296: 4603 mov r3, r0
8001298: 4618 mov r0, r3
800129a: f005 f943 bl 8006524 <sqrtf>
800129e: 61f8 str r0, [r7, #28]
//for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
//temperature_display[i] = temperature_display[i-1];
ratio_mag = mag_ref / mag_dut;
80012a0: 69f9 ldr r1, [r7, #28]
80012a2: 6878 ldr r0, [r7, #4]
80012a4: f7ff fcb2 bl 8000c0c <__aeabi_fdiv>
80012a8: 4603 mov r3, r0
80012aa: 61bb str r3, [r7, #24]
if(ch_ref==AD5934_CH_REF100R_LOW_GAIN) // only for PT100
80012ac: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
80012b0: 2b00 cmp r3, #0
80012b2: d109 bne.n 80012c8 <AD5934_GetTemperature+0x15c>
impedance_dut = AD5934_Linear_Correction(gain_factor * ratio_mag);
80012b4: 69b9 ldr r1, [r7, #24]
80012b6: 6af8 ldr r0, [r7, #44] @ 0x2c
80012b8: f7ff fbf4 bl 8000aa4 <__aeabi_fmul>
80012bc: 4603 mov r3, r0
80012be: 4618 mov r0, r3
80012c0: f000 f9a0 bl 8001604 <AD5934_Linear_Correction>
80012c4: 6338 str r0, [r7, #48] @ 0x30
80012c6: e005 b.n 80012d4 <AD5934_GetTemperature+0x168>
else
impedance_dut = gain_factor * ratio_mag;
80012c8: 69b9 ldr r1, [r7, #24]
80012ca: 6af8 ldr r0, [r7, #44] @ 0x2c
80012cc: f7ff fbea bl 8000aa4 <__aeabi_fmul>
80012d0: 4603 mov r3, r0
80012d2: 633b str r3, [r7, #48] @ 0x30
// Calculate impedance ratio with the Reference Resistor
ratio = impedance_dut / gain_factor;
80012d4: 6af9 ldr r1, [r7, #44] @ 0x2c
80012d6: 6b38 ldr r0, [r7, #48] @ 0x30
80012d8: f7ff fc98 bl 8000c0c <__aeabi_fdiv>
80012dc: 4603 mov r3, r0
80012de: 617b str r3, [r7, #20]
// Calculate impedance discriminant with the ratio
discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio));
80012e0: 6979 ldr r1, [r7, #20]
80012e2: f04f 507e mov.w r0, #1065353216 @ 0x3f800000
80012e6: f7ff fad3 bl 8000890 <__aeabi_fsub>
80012ea: 4603 mov r3, r0
80012ec: 4914 ldr r1, [pc, #80] @ (8001340 <AD5934_GetTemperature+0x1d4>)
80012ee: 4618 mov r0, r3
80012f0: f7ff fbd8 bl 8000aa4 <__aeabi_fmul>
80012f4: 4603 mov r3, r0
80012f6: 4913 ldr r1, [pc, #76] @ (8001344 <AD5934_GetTemperature+0x1d8>)
80012f8: 4618 mov r0, r3
80012fa: f7ff facb bl 8000894 <__addsf3>
80012fe: 4603 mov r3, r0
8001300: 613b str r3, [r7, #16]
//temp_result = (-AD5934_RTD_A + sqrtf(discriminant)/(2.0f * AD5934_RTD_B));
return (AD5934_Round_Float_Precision(((-AD5934_RTD_A + sqrtf(discriminant))/(2.0f * AD5934_RTD_B)),2));
8001302: 6938 ldr r0, [r7, #16]
8001304: f005 f90e bl 8006524 <sqrtf>
8001308: 4603 mov r3, r0
800130a: 490f ldr r1, [pc, #60] @ (8001348 <AD5934_GetTemperature+0x1dc>)
800130c: 4618 mov r0, r3
800130e: f7ff fabf bl 8000890 <__aeabi_fsub>
8001312: 4603 mov r3, r0
8001314: 490d ldr r1, [pc, #52] @ (800134c <AD5934_GetTemperature+0x1e0>)
8001316: 4618 mov r0, r3
8001318: f7ff fc78 bl 8000c0c <__aeabi_fdiv>
800131c: 4603 mov r3, r0
800131e: 2102 movs r1, #2
8001320: 4618 mov r0, r3
8001322: f000 f941 bl 80015a8 <AD5934_Round_Float_Precision>
8001326: 4603 mov r3, r0
// Is the temperature stable?
//if(temperature_display[0]>0.0f && (abs(temperature_display[0]-temperature_display[AD5934_TEMP_AVERAGES-1])/temperature_display[0])<0.1f)
//return(AD5934_Round_Float_Precision(temperature_sum/((float)AD5934_TEMP_AVERAGES),1)); // Sum / number of averages
//else
//return 0.0f; //instable values return always 0
}
8001328: 4618 mov r0, r3
800132a: 373c adds r7, #60 @ 0x3c
800132c: 46bd mov sp, r7
800132e: bd90 pop {r4, r7, pc}
8001330: 40010800 .word 0x40010800
8001334: 42c80000 .word 0x42c80000
8001338: 447a0000 .word 0x447a0000
800133c: 200000ac .word 0x200000ac
8001340: 361b057f .word 0x361b057f
8001344: 37802266 .word 0x37802266
8001348: 3b801132 .word 0x3b801132
800134c: b59b057f .word 0xb59b057f
08001350 <AD5934_GetImpedance>:
*
* @param temperature_dut The current temperature of the DUT (Device Under Test).
* @return float Calculated conductivity in uS/cm.
*/
float AD5934_GetImpedance(float temperature_dut)
{
8001350: b590 push {r4, r7, lr}
8001352: b08b sub sp, #44 @ 0x2c
8001354: af00 add r7, sp, #0
8001356: 6078 str r0, [r7, #4]
uint8_t i, ec_gain;
uint32_t sample_dut;
int32_t dut_sum[2] = {0, 0};
8001358: 2300 movs r3, #0
800135a: 60bb str r3, [r7, #8]
800135c: 2300 movs r3, #0
800135e: 60fb str r3, [r7, #12]
float real_avg, imag_avg, mag_dut, slope, target_cond;
/* 1. Hardware Setup: Gain Selection (PA6) */
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET)
8001360: 2140 movs r1, #64 @ 0x40
8001362: 4878 ldr r0, [pc, #480] @ (8001544 <AD5934_GetImpedance+0x1f4>)
8001364: f002 fd44 bl 8003df0 <HAL_GPIO_ReadPin>
8001368: 4603 mov r3, r0
800136a: 2b01 cmp r3, #1
800136c: d103 bne.n 8001376 <AD5934_GetImpedance+0x26>
ec_gain = AD5934_CH_EC_HIGH_GAIN;
800136e: 230e movs r3, #14
8001370: f887 3026 strb.w r3, [r7, #38] @ 0x26
8001374: e002 b.n 800137c <AD5934_GetImpedance+0x2c>
else
ec_gain = AD5934_CH_EC_MID_GAIN;
8001376: 230d movs r3, #13
8001378: f887 3026 strb.w r3, [r7, #38] @ 0x26
if((ec_gain != flash_data.EC10mS_EC5mS_switch) && (main_state != STATE_PH4_DRY_EC_CALIBRATION || main_state != STATE_PH7_WET_EC_CALIBRATION))
800137c: 4b72 ldr r3, [pc, #456] @ (8001548 <AD5934_GetImpedance+0x1f8>)
800137e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8001382: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
8001386: 429a cmp r2, r3
8001388: d009 beq.n 800139e <AD5934_GetImpedance+0x4e>
800138a: 4b70 ldr r3, [pc, #448] @ (800154c <AD5934_GetImpedance+0x1fc>)
800138c: 781b ldrb r3, [r3, #0]
800138e: 2b02 cmp r3, #2
8001390: d103 bne.n 800139a <AD5934_GetImpedance+0x4a>
8001392: 4b6e ldr r3, [pc, #440] @ (800154c <AD5934_GetImpedance+0x1fc>)
8001394: 781b ldrb r3, [r3, #0]
8001396: 2b03 cmp r3, #3
8001398: d001 beq.n 800139e <AD5934_GetImpedance+0x4e>
return -1.0f; // Fatal error because the gain used in calibration is different
800139a: 4b6d ldr r3, [pc, #436] @ (8001550 <AD5934_GetImpedance+0x200>)
800139c: e0ce b.n 800153c <AD5934_GetImpedance+0x1ec>
ADG715_Update(ec_gain);
800139e: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
80013a2: 4618 mov r0, r3
80013a4: f000 fa38 bl 8001818 <ADG715_Update>
//HAL_Delay(5);
/* 2. Data Acquisition */
sample_dut = AD5934_Sweep();
80013a8: f7ff fe37 bl 800101a <AD5934_Sweep>
80013ac: 6238 str r0, [r7, #32]
// Shift buffer for moving average
for (i = (AD5934_EC_AVERAGES - 1); i > 0; i--)
80013ae: 230f movs r3, #15
80013b0: f887 3027 strb.w r3, [r7, #39] @ 0x27
80013b4: e01c b.n 80013f0 <AD5934_GetImpedance+0xa0>
{
ec_dut_samples[0][i] = ec_dut_samples[0][i-1];
80013b6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013ba: 1e5a subs r2, r3, #1
80013bc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013c0: 4964 ldr r1, [pc, #400] @ (8001554 <AD5934_GetImpedance+0x204>)
80013c2: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
80013c6: 4a63 ldr r2, [pc, #396] @ (8001554 <AD5934_GetImpedance+0x204>)
80013c8: f822 1013 strh.w r1, [r2, r3, lsl #1]
ec_dut_samples[1][i] = ec_dut_samples[1][i-1];
80013cc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013d0: 1e5a subs r2, r3, #1
80013d2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013d6: 495f ldr r1, [pc, #380] @ (8001554 <AD5934_GetImpedance+0x204>)
80013d8: 3210 adds r2, #16
80013da: f931 1012 ldrsh.w r1, [r1, r2, lsl #1]
80013de: 4a5d ldr r2, [pc, #372] @ (8001554 <AD5934_GetImpedance+0x204>)
80013e0: 3310 adds r3, #16
80013e2: f822 1013 strh.w r1, [r2, r3, lsl #1]
for (i = (AD5934_EC_AVERAGES - 1); i > 0; i--)
80013e6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013ea: 3b01 subs r3, #1
80013ec: f887 3027 strb.w r3, [r7, #39] @ 0x27
80013f0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80013f4: 2b00 cmp r3, #0
80013f6: d1de bne.n 80013b6 <AD5934_GetImpedance+0x66>
}
// Deconstruct 32-bit sample into Real and Imaginary components
ec_dut_samples[0][0] = (float)(int16_t)(sample_dut & 0xFFFF);
80013f8: 6a3b ldr r3, [r7, #32]
80013fa: b21b sxth r3, r3
80013fc: 4618 mov r0, r3
80013fe: f7ff fafd bl 80009fc <__aeabi_i2f>
8001402: 4603 mov r3, r0
8001404: 4618 mov r0, r3
8001406: f7ff fd29 bl 8000e5c <__aeabi_f2iz>
800140a: 4603 mov r3, r0
800140c: b21a sxth r2, r3
800140e: 4b51 ldr r3, [pc, #324] @ (8001554 <AD5934_GetImpedance+0x204>)
8001410: 801a strh r2, [r3, #0]
ec_dut_samples[1][0] = (float)(int16_t)((sample_dut >> 16) & 0xFFFF);
8001412: 6a3b ldr r3, [r7, #32]
8001414: 0c1b lsrs r3, r3, #16
8001416: b21b sxth r3, r3
8001418: 4618 mov r0, r3
800141a: f7ff faef bl 80009fc <__aeabi_i2f>
800141e: 4603 mov r3, r0
8001420: 4618 mov r0, r3
8001422: f7ff fd1b bl 8000e5c <__aeabi_f2iz>
8001426: 4603 mov r3, r0
8001428: b21a sxth r2, r3
800142a: 4b4a ldr r3, [pc, #296] @ (8001554 <AD5934_GetImpedance+0x204>)
800142c: 841a strh r2, [r3, #32]
/* 3. Compute Averages */
for (i = 0; i < AD5934_EC_AVERAGES; i++)
800142e: 2300 movs r3, #0
8001430: f887 3027 strb.w r3, [r7, #39] @ 0x27
8001434: e015 b.n 8001462 <AD5934_GetImpedance+0x112>
{
dut_sum[0] += (int32_t)ec_dut_samples[0][i];
8001436: 68bb ldr r3, [r7, #8]
8001438: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
800143c: 4945 ldr r1, [pc, #276] @ (8001554 <AD5934_GetImpedance+0x204>)
800143e: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
8001442: 4413 add r3, r2
8001444: 60bb str r3, [r7, #8]
dut_sum[1] += (int32_t)ec_dut_samples[1][i];
8001446: 68fb ldr r3, [r7, #12]
8001448: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
800144c: 4941 ldr r1, [pc, #260] @ (8001554 <AD5934_GetImpedance+0x204>)
800144e: 3210 adds r2, #16
8001450: f931 2012 ldrsh.w r2, [r1, r2, lsl #1]
8001454: 4413 add r3, r2
8001456: 60fb str r3, [r7, #12]
for (i = 0; i < AD5934_EC_AVERAGES; i++)
8001458: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
800145c: 3301 adds r3, #1
800145e: f887 3027 strb.w r3, [r7, #39] @ 0x27
8001462: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001466: 2b0f cmp r3, #15
8001468: d9e5 bls.n 8001436 <AD5934_GetImpedance+0xe6>
}
real_avg = (float)dut_sum[0] / (float)AD5934_EC_AVERAGES;
800146a: 68bb ldr r3, [r7, #8]
800146c: 4618 mov r0, r3
800146e: f7ff fac5 bl 80009fc <__aeabi_i2f>
8001472: 4603 mov r3, r0
8001474: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
8001478: 4618 mov r0, r3
800147a: f7ff fbc7 bl 8000c0c <__aeabi_fdiv>
800147e: 4603 mov r3, r0
8001480: 61fb str r3, [r7, #28]
imag_avg = (float)dut_sum[1] / (float)AD5934_EC_AVERAGES;
8001482: 68fb ldr r3, [r7, #12]
8001484: 4618 mov r0, r3
8001486: f7ff fab9 bl 80009fc <__aeabi_i2f>
800148a: 4603 mov r3, r0
800148c: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
8001490: 4618 mov r0, r3
8001492: f7ff fbbb bl 8000c0c <__aeabi_fdiv>
8001496: 4603 mov r3, r0
8001498: 61bb str r3, [r7, #24]
/* 4. Magnitude Calculation */
mag_dut = sqrtf((real_avg * real_avg) + (imag_avg * imag_avg));
800149a: 69f9 ldr r1, [r7, #28]
800149c: 69f8 ldr r0, [r7, #28]
800149e: f7ff fb01 bl 8000aa4 <__aeabi_fmul>
80014a2: 4603 mov r3, r0
80014a4: 461c mov r4, r3
80014a6: 69b9 ldr r1, [r7, #24]
80014a8: 69b8 ldr r0, [r7, #24]
80014aa: f7ff fafb bl 8000aa4 <__aeabi_fmul>
80014ae: 4603 mov r3, r0
80014b0: 4619 mov r1, r3
80014b2: 4620 mov r0, r4
80014b4: f7ff f9ee bl 8000894 <__addsf3>
80014b8: 4603 mov r3, r0
80014ba: 4618 mov r0, r3
80014bc: f005 f832 bl 8006524 <sqrtf>
80014c0: 6178 str r0, [r7, #20]
/* 5. Calibration Logic Implementation */
// Mode: CALIBRATION SETUP (User is defining the reference magnitude)
if(main_state == STATE_PH4_DRY_EC_CALIBRATION || main_state == STATE_PH7_WET_EC_CALIBRATION)
80014c2: 4b22 ldr r3, [pc, #136] @ (800154c <AD5934_GetImpedance+0x1fc>)
80014c4: 781b ldrb r3, [r3, #0]
80014c6: 2b02 cmp r3, #2
80014c8: d003 beq.n 80014d2 <AD5934_GetImpedance+0x182>
80014ca: 4b20 ldr r3, [pc, #128] @ (800154c <AD5934_GetImpedance+0x1fc>)
80014cc: 781b ldrb r3, [r3, #0]
80014ce: 2b03 cmp r3, #3
80014d0: d101 bne.n 80014d6 <AD5934_GetImpedance+0x186>
{
return mag_dut;
80014d2: 697b ldr r3, [r7, #20]
80014d4: e032 b.n 800153c <AD5934_GetImpedance+0x1ec>
}
// Mode: MEASUREMENT (Applying temperature compensation)
else if(flash_data.ec0_mag != flash_data.ec1413_mag)
80014d6: 4b1c ldr r3, [pc, #112] @ (8001548 <AD5934_GetImpedance+0x1f8>)
80014d8: 69db ldr r3, [r3, #28]
80014da: 4a1b ldr r2, [pc, #108] @ (8001548 <AD5934_GetImpedance+0x1f8>)
80014dc: 6992 ldr r2, [r2, #24]
80014de: 4611 mov r1, r2
80014e0: 4618 mov r0, r3
80014e2: f7ff fc73 bl 8000dcc <__aeabi_fcmpeq>
80014e6: 4603 mov r3, r0
80014e8: 2b00 cmp r3, #0
80014ea: d125 bne.n 8001538 <AD5934_GetImpedance+0x1e8>
{
slope = (AD5934_GAIN_FACTOR_1413US/(flash_data.ec1413_mag-flash_data.ec0_mag));
80014ec: 4b16 ldr r3, [pc, #88] @ (8001548 <AD5934_GetImpedance+0x1f8>)
80014ee: 699b ldr r3, [r3, #24]
80014f0: 4a15 ldr r2, [pc, #84] @ (8001548 <AD5934_GetImpedance+0x1f8>)
80014f2: 69d2 ldr r2, [r2, #28]
80014f4: 4611 mov r1, r2
80014f6: 4618 mov r0, r3
80014f8: f7ff f9ca bl 8000890 <__aeabi_fsub>
80014fc: 4603 mov r3, r0
80014fe: 4619 mov r1, r3
8001500: 4815 ldr r0, [pc, #84] @ (8001558 <AD5934_GetImpedance+0x208>)
8001502: f7ff fb83 bl 8000c0c <__aeabi_fdiv>
8001506: 4603 mov r3, r0
8001508: 613b str r3, [r7, #16]
return(AD5934_GAIN_FACTOR_1413US + (AD5934_EC_Compensate_To_25C(mag_dut,temperature_dut) - flash_data.ec1413_mag) * slope);
800150a: 6879 ldr r1, [r7, #4]
800150c: 6978 ldr r0, [r7, #20]
800150e: f000 f893 bl 8001638 <AD5934_EC_Compensate_To_25C>
8001512: 4602 mov r2, r0
8001514: 4b0c ldr r3, [pc, #48] @ (8001548 <AD5934_GetImpedance+0x1f8>)
8001516: 699b ldr r3, [r3, #24]
8001518: 4619 mov r1, r3
800151a: 4610 mov r0, r2
800151c: f7ff f9b8 bl 8000890 <__aeabi_fsub>
8001520: 4603 mov r3, r0
8001522: 6939 ldr r1, [r7, #16]
8001524: 4618 mov r0, r3
8001526: f7ff fabd bl 8000aa4 <__aeabi_fmul>
800152a: 4603 mov r3, r0
800152c: 490a ldr r1, [pc, #40] @ (8001558 <AD5934_GetImpedance+0x208>)
800152e: 4618 mov r0, r3
8001530: f7ff f9b0 bl 8000894 <__addsf3>
8001534: 4603 mov r3, r0
8001536: e001 b.n 800153c <AD5934_GetImpedance+0x1ec>
}
else
return 0.0f; // Calibration error fallback
8001538: f04f 0300 mov.w r3, #0
}
800153c: 4618 mov r0, r3
800153e: 372c adds r7, #44 @ 0x2c
8001540: 46bd mov sp, r7
8001542: bd90 pop {r4, r7, pc}
8001544: 40010800 .word 0x40010800
8001548: 20000224 .word 0x20000224
800154c: 200006cc .word 0x200006cc
8001550: bf800000 .word 0xbf800000
8001554: 2000012c .word 0x2000012c
8001558: 44b0a000 .word 0x44b0a000
0800155c <AD5934_Wait_For_Data_Valid>:
/**
* @brief Monitora o status com TIMEOUT para evitar travamento do sistema.
*/
void AD5934_Wait_For_Data_Valid(void)
{
800155c: b580 push {r7, lr}
800155e: b084 sub sp, #16
8001560: af00 add r7, sp, #0
uint32_t timeout_counter = 0;
8001562: 2300 movs r3, #0
8001564: 60fb str r3, [r7, #12]
const uint32_t MAX_TIMEOUT = 10000; // Limite de tentativas
8001566: f242 7310 movw r3, #10000 @ 0x2710
800156a: 60bb str r3, [r7, #8]
uint8_t status;
while (1)
{
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
800156c: 2101 movs r1, #1
800156e: 208f movs r0, #143 @ 0x8f
8001570: f7ff fccc bl 8000f0c <AD5934_GetRegisterValue>
8001574: 4603 mov r3, r0
8001576: 71fb strb r3, [r7, #7]
if ((status & AD5934_STATUS_DATA_VALID) != 0)
8001578: 79fb ldrb r3, [r7, #7]
800157a: f003 0302 and.w r3, r3, #2
800157e: 2b00 cmp r3, #0
8001580: d10a bne.n 8001598 <AD5934_Wait_For_Data_Valid+0x3c>
{
break; // Sucesso!
}
timeout_counter++;
8001582: 68fb ldr r3, [r7, #12]
8001584: 3301 adds r3, #1
8001586: 60fb str r3, [r7, #12]
if (timeout_counter >= MAX_TIMEOUT)
8001588: 68fa ldr r2, [r7, #12]
800158a: 68bb ldr r3, [r7, #8]
800158c: 429a cmp r2, r3
800158e: d205 bcs.n 800159c <AD5934_Wait_For_Data_Valid+0x40>
{
// TRATAMENTO DE ERRO: O sistema não travou, mas o chip falhou.
break;
}
HAL_Delay(1); // Pequeno delay para não sobrecarregar o barramento I2C
8001590: 2001 movs r0, #1
8001592: f001 fcb3 bl 8002efc <HAL_Delay>
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
8001596: e7e9 b.n 800156c <AD5934_Wait_For_Data_Valid+0x10>
break; // Sucesso!
8001598: bf00 nop
800159a: e000 b.n 800159e <AD5934_Wait_For_Data_Valid+0x42>
break;
800159c: bf00 nop
}
}
800159e: bf00 nop
80015a0: 3710 adds r7, #16
80015a2: 46bd mov sp, r7
80015a4: bd80 pop {r7, pc}
...
080015a8 <AD5934_Round_Float_Precision>:
* @param valor O valor float original.
* @param casas_decimais Quantidade de casas que devem permanecer após a vírgula.
* @return float O valor com as casas decimais excedentes removidas.
*/
float AD5934_Round_Float_Precision(float value, uint8_t number_of_decimals)
{
80015a8: b580 push {r7, lr}
80015aa: b084 sub sp, #16
80015ac: af00 add r7, sp, #0
80015ae: 6078 str r0, [r7, #4]
80015b0: 460b mov r3, r1
80015b2: 70fb strb r3, [r7, #3]
float multiply = 1.0f;
80015b4: f04f 537e mov.w r3, #1065353216 @ 0x3f800000
80015b8: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
80015ba: 2300 movs r3, #0
80015bc: 72fb strb r3, [r7, #11]
80015be: e008 b.n 80015d2 <AD5934_Round_Float_Precision+0x2a>
multiply *= 10.0f;
80015c0: 490f ldr r1, [pc, #60] @ (8001600 <AD5934_Round_Float_Precision+0x58>)
80015c2: 68f8 ldr r0, [r7, #12]
80015c4: f7ff fa6e bl 8000aa4 <__aeabi_fmul>
80015c8: 4603 mov r3, r0
80015ca: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
80015cc: 7afb ldrb r3, [r7, #11]
80015ce: 3301 adds r3, #1
80015d0: 72fb strb r3, [r7, #11]
80015d2: 7afa ldrb r2, [r7, #11]
80015d4: 78fb ldrb r3, [r7, #3]
80015d6: 429a cmp r2, r3
80015d8: d3f2 bcc.n 80015c0 <AD5934_Round_Float_Precision+0x18>
return roundf(value * multiply) / multiply;
80015da: 68f9 ldr r1, [r7, #12]
80015dc: 6878 ldr r0, [r7, #4]
80015de: f7ff fa61 bl 8000aa4 <__aeabi_fmul>
80015e2: 4603 mov r3, r0
80015e4: 4618 mov r0, r3
80015e6: f005 f82d bl 8006644 <roundf>
80015ea: 4603 mov r3, r0
80015ec: 68f9 ldr r1, [r7, #12]
80015ee: 4618 mov r0, r3
80015f0: f7ff fb0c bl 8000c0c <__aeabi_fdiv>
80015f4: 4603 mov r3, r0
}
80015f6: 4618 mov r0, r3
80015f8: 3710 adds r7, #16
80015fa: 46bd mov sp, r7
80015fc: bd80 pop {r7, pc}
80015fe: bf00 nop
8001600: 41200000 .word 0x41200000
08001604 <AD5934_Linear_Correction>:
*
* @param input_val The raw float value from sensor/ADC.
* @return float The transformed value following the requested trend.
*/
float AD5934_Linear_Correction(float raw_value)
{
8001604: b580 push {r7, lr}
8001606: b084 sub sp, #16
8001608: af00 add r7, sp, #0
800160a: 6078 str r0, [r7, #4]
/* Pre-calculated constants from regression analysis */
const float slope = 1.02281f;
800160c: 4b08 ldr r3, [pc, #32] @ (8001630 <AD5934_Linear_Correction+0x2c>)
800160e: 60fb str r3, [r7, #12]
const float offset = (-2.1409f);
8001610: 4b08 ldr r3, [pc, #32] @ (8001634 <AD5934_Linear_Correction+0x30>)
8001612: 60bb str r3, [r7, #8]
/* Single FPU instruction (if FPU available) or optimized software float mul/add */
return (raw_value * slope) + offset;
8001614: 68f9 ldr r1, [r7, #12]
8001616: 6878 ldr r0, [r7, #4]
8001618: f7ff fa44 bl 8000aa4 <__aeabi_fmul>
800161c: 4603 mov r3, r0
800161e: 68b9 ldr r1, [r7, #8]
8001620: 4618 mov r0, r3
8001622: f7ff f937 bl 8000894 <__addsf3>
8001626: 4603 mov r3, r0
}
8001628: 4618 mov r0, r3
800162a: 3710 adds r7, #16
800162c: 46bd mov sp, r7
800162e: bd80 pop {r7, pc}
8001630: 3f82eb70 .word 0x3f82eb70
8001634: c0090481 .word 0xc0090481
08001638 <AD5934_EC_Compensate_To_25C>:
* @param admittance raw in uS/cm
* @param temperature_celsius Temperature in degrees Celsius
* @return admittance compensated
*/
float AD5934_EC_Compensate_To_25C(float ec_raw_uScm, float temp_C)
{
8001638: b580 push {r7, lr}
800163a: b084 sub sp, #16
800163c: af00 add r7, sp, #0
800163e: 6078 str r0, [r7, #4]
8001640: 6039 str r1, [r7, #0]
float factor = 1.0f + AD5934_EC_ALPHA_PER_C * (temp_C - AD5934_EC_TEMP_REF_C);
8001642: 4911 ldr r1, [pc, #68] @ (8001688 <AD5934_EC_Compensate_To_25C+0x50>)
8001644: 6838 ldr r0, [r7, #0]
8001646: f7ff f923 bl 8000890 <__aeabi_fsub>
800164a: 4603 mov r3, r0
800164c: 490f ldr r1, [pc, #60] @ (800168c <AD5934_EC_Compensate_To_25C+0x54>)
800164e: 4618 mov r0, r3
8001650: f7ff fa28 bl 8000aa4 <__aeabi_fmul>
8001654: 4603 mov r3, r0
8001656: f04f 517e mov.w r1, #1065353216 @ 0x3f800000
800165a: 4618 mov r0, r3
800165c: f7ff f91a bl 8000894 <__addsf3>
8001660: 4603 mov r3, r0
8001662: 60fb str r3, [r7, #12]
if (factor < 0.1f)
8001664: 490a ldr r1, [pc, #40] @ (8001690 <AD5934_EC_Compensate_To_25C+0x58>)
8001666: 68f8 ldr r0, [r7, #12]
8001668: f7ff fbba bl 8000de0 <__aeabi_fcmplt>
800166c: 4603 mov r3, r0
800166e: 2b00 cmp r3, #0
8001670: d001 beq.n 8001676 <AD5934_EC_Compensate_To_25C+0x3e>
factor = 0.1f;
8001672: 4b07 ldr r3, [pc, #28] @ (8001690 <AD5934_EC_Compensate_To_25C+0x58>)
8001674: 60fb str r3, [r7, #12]
return (ec_raw_uScm / factor);
8001676: 68f9 ldr r1, [r7, #12]
8001678: 6878 ldr r0, [r7, #4]
800167a: f7ff fac7 bl 8000c0c <__aeabi_fdiv>
800167e: 4603 mov r3, r0
}
8001680: 4618 mov r0, r3
8001682: 3710 adds r7, #16
8001684: 46bd mov sp, r7
8001686: bd80 pop {r7, pc}
8001688: 41c80000 .word 0x41c80000
800168c: 3ca3d70a .word 0x3ca3d70a
8001690: 3dcccccd .word 0x3dcccccd
08001694 <AD5934_EC_Calibrate_Temperature>:
* @brief Calibrates EC sensor reading to 25°C reference point
* @param temp_C Temperature of the liquid in Celsius
* @return Temperature-compensated Correction factor value at 25°C reference
*/
float AD5934_EC_Calibrate_Temperature(float temp_C)
{
8001694: b5b0 push {r4, r5, r7, lr}
8001696: b0a2 sub sp, #136 @ 0x88
8001698: af00 add r7, sp, #0
800169a: 6078 str r0, [r7, #4]
// Calibration data points for standard solution (1413 uS/cm)
const float temps[] = {5, 10, 15, 18, 20, 22, 25, 30, 35, 40, 45, 50};
800169c: 4b4b ldr r3, [pc, #300] @ (80017cc <AD5934_EC_Calibrate_Temperature+0x138>)
800169e: f107 043c add.w r4, r7, #60 @ 0x3c
80016a2: 461d mov r5, r3
80016a4: cd0f ldmia r5!, {r0, r1, r2, r3}
80016a6: c40f stmia r4!, {r0, r1, r2, r3}
80016a8: cd0f ldmia r5!, {r0, r1, r2, r3}
80016aa: c40f stmia r4!, {r0, r1, r2, r3}
80016ac: e895 000f ldmia.w r5, {r0, r1, r2, r3}
80016b0: e884 000f stmia.w r4, {r0, r1, r2, r3}
const float conductivities[] = {893, 1018, 1149, 1225, 1278, 1329, 1413, 1552, 1691, 1843, 1988, 2145};
80016b4: 4b46 ldr r3, [pc, #280] @ (80017d0 <AD5934_EC_Calibrate_Temperature+0x13c>)
80016b6: f107 040c add.w r4, r7, #12
80016ba: 461d mov r5, r3
80016bc: cd0f ldmia r5!, {r0, r1, r2, r3}
80016be: c40f stmia r4!, {r0, r1, r2, r3}
80016c0: cd0f ldmia r5!, {r0, r1, r2, r3}
80016c2: c40f stmia r4!, {r0, r1, r2, r3}
80016c4: e895 000f ldmia.w r5, {r0, r1, r2, r3}
80016c8: e884 000f stmia.w r4, {r0, r1, r2, r3}
// Find the two nearest temperature points for interpolation
int32_t temp_index = -1;
80016cc: f04f 33ff mov.w r3, #4294967295
80016d0: f8c7 3084 str.w r3, [r7, #132] @ 0x84
for (int i = 0; i < 12; i++)
80016d4: 2300 movs r3, #0
80016d6: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80016da: e017 b.n 800170c <AD5934_EC_Calibrate_Temperature+0x78>
{
if (temps[i] >= temp_C)
80016dc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80016e0: 009b lsls r3, r3, #2
80016e2: 3388 adds r3, #136 @ 0x88
80016e4: 443b add r3, r7
80016e6: f853 3c4c ldr.w r3, [r3, #-76]
80016ea: 4619 mov r1, r3
80016ec: 6878 ldr r0, [r7, #4]
80016ee: f7ff fb81 bl 8000df4 <__aeabi_fcmple>
80016f2: 4603 mov r3, r0
80016f4: 2b00 cmp r3, #0
80016f6: d004 beq.n 8001702 <AD5934_EC_Calibrate_Temperature+0x6e>
{
temp_index = i;
80016f8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80016fc: f8c7 3084 str.w r3, [r7, #132] @ 0x84
break;
8001700: e008 b.n 8001714 <AD5934_EC_Calibrate_Temperature+0x80>
for (int i = 0; i < 12; i++)
8001702: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8001706: 3301 adds r3, #1
8001708: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800170c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8001710: 2b0b cmp r3, #11
8001712: dde3 ble.n 80016dc <AD5934_EC_Calibrate_Temperature+0x48>
}
}
// Handle boundary cases
if (temp_index == -1) {
8001714: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8001718: f1b3 3fff cmp.w r3, #4294967295
800171c: d103 bne.n 8001726 <AD5934_EC_Calibrate_Temperature+0x92>
// Temperature higher than max point (50°C)
temp_index = 10;
800171e: 230a movs r3, #10
8001720: f8c7 3084 str.w r3, [r7, #132] @ 0x84
8001724: e006 b.n 8001734 <AD5934_EC_Calibrate_Temperature+0xa0>
} else if (temp_index == 0) {
8001726: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800172a: 2b00 cmp r3, #0
800172c: d102 bne.n 8001734 <AD5934_EC_Calibrate_Temperature+0xa0>
// Temperature lower than min point (5°C)
temp_index = 0;
800172e: 2300 movs r3, #0
8001730: f8c7 3084 str.w r3, [r7, #132] @ 0x84
}
// Interpolate conductivity at measured temperature
float temp1 = temps[temp_index - 1];
8001734: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8001738: 3b01 subs r3, #1
800173a: 009b lsls r3, r3, #2
800173c: 3388 adds r3, #136 @ 0x88
800173e: 443b add r3, r7
8001740: f853 3c4c ldr.w r3, [r3, #-76]
8001744: 67fb str r3, [r7, #124] @ 0x7c
float temp2 = temps[temp_index];
8001746: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800174a: 009b lsls r3, r3, #2
800174c: 3388 adds r3, #136 @ 0x88
800174e: 443b add r3, r7
8001750: f853 3c4c ldr.w r3, [r3, #-76]
8001754: 67bb str r3, [r7, #120] @ 0x78
float cond1 = conductivities[temp_index - 1];
8001756: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800175a: 3b01 subs r3, #1
800175c: 009b lsls r3, r3, #2
800175e: 3388 adds r3, #136 @ 0x88
8001760: 443b add r3, r7
8001762: f853 3c7c ldr.w r3, [r3, #-124]
8001766: 677b str r3, [r7, #116] @ 0x74
float cond2 = conductivities[temp_index];
8001768: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800176c: 009b lsls r3, r3, #2
800176e: 3388 adds r3, #136 @ 0x88
8001770: 443b add r3, r7
8001772: f853 3c7c ldr.w r3, [r3, #-124]
8001776: 673b str r3, [r7, #112] @ 0x70
// Linear interpolation to get conductivity at measured temperature
float interpolated_cond = cond1 + (cond2 - cond1) * (temp_C - temp1) / (temp2 - temp1);
8001778: 6f79 ldr r1, [r7, #116] @ 0x74
800177a: 6f38 ldr r0, [r7, #112] @ 0x70
800177c: f7ff f888 bl 8000890 <__aeabi_fsub>
8001780: 4603 mov r3, r0
8001782: 461c mov r4, r3
8001784: 6ff9 ldr r1, [r7, #124] @ 0x7c
8001786: 6878 ldr r0, [r7, #4]
8001788: f7ff f882 bl 8000890 <__aeabi_fsub>
800178c: 4603 mov r3, r0
800178e: 4619 mov r1, r3
8001790: 4620 mov r0, r4
8001792: f7ff f987 bl 8000aa4 <__aeabi_fmul>
8001796: 4603 mov r3, r0
8001798: 461c mov r4, r3
800179a: 6ff9 ldr r1, [r7, #124] @ 0x7c
800179c: 6fb8 ldr r0, [r7, #120] @ 0x78
800179e: f7ff f877 bl 8000890 <__aeabi_fsub>
80017a2: 4603 mov r3, r0
80017a4: 4619 mov r1, r3
80017a6: 4620 mov r0, r4
80017a8: f7ff fa30 bl 8000c0c <__aeabi_fdiv>
80017ac: 4603 mov r3, r0
80017ae: 4619 mov r1, r3
80017b0: 6f78 ldr r0, [r7, #116] @ 0x74
80017b2: f7ff f86f bl 8000894 <__addsf3>
80017b6: 4603 mov r3, r0
80017b8: 66fb str r3, [r7, #108] @ 0x6c
// Return real conductivity at the temperature
return(interpolated_cond/1413.0f);
80017ba: 4906 ldr r1, [pc, #24] @ (80017d4 <AD5934_EC_Calibrate_Temperature+0x140>)
80017bc: 6ef8 ldr r0, [r7, #108] @ 0x6c
80017be: f7ff fa25 bl 8000c0c <__aeabi_fdiv>
80017c2: 4603 mov r3, r0
}
80017c4: 4618 mov r0, r3
80017c6: 3788 adds r7, #136 @ 0x88
80017c8: 46bd mov sp, r7
80017ca: bdb0 pop {r4, r5, r7, pc}
80017cc: 080066a4 .word 0x080066a4
80017d0: 080066d4 .word 0x080066d4
80017d4: 44b0a000 .word 0x44b0a000
080017d8 <ADG715_SetRegisterValue>:
*
* @return None.
*******************************************************************************/
void ADG715_SetRegisterValue(char value)
{
80017d8: b580 push {r7, lr}
80017da: b086 sub sp, #24
80017dc: af02 add r7, sp, #8
80017de: 4603 mov r3, r0
80017e0: 71fb strb r3, [r7, #7]
uint8_t writeData[1] = {value};
80017e2: 79fb ldrb r3, [r7, #7]
80017e4: 733b strb r3, [r7, #12]
HAL_StatusTypeDef status;
status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
80017e6: f107 020c add.w r2, r7, #12
80017ea: 2301 movs r3, #1
80017ec: 9300 str r3, [sp, #0]
80017ee: 2301 movs r3, #1
80017f0: 2190 movs r1, #144 @ 0x90
80017f2: 4804 ldr r0, [pc, #16] @ (8001804 <ADG715_SetRegisterValue+0x2c>)
80017f4: f002 fc88 bl 8004108 <HAL_I2C_Master_Transmit>
80017f8: 4603 mov r3, r0
80017fa: 73fb strb r3, [r7, #15]
return;
80017fc: bf00 nop
}
80017fe: 3710 adds r7, #16
8001800: 46bd mov sp, r7
8001802: bd80 pop {r7, pc}
8001804: 20000678 .word 0x20000678
08001808 <ADG715_ResetChannels>:
{
ADG715_SetRegisterValue(ch1+ch2);
}
void ADG715_ResetChannels(void)
{
8001808: b580 push {r7, lr}
800180a: af00 add r7, sp, #0
ADG715_SetRegisterValue(0);
800180c: 2000 movs r0, #0
800180e: f7ff ffe3 bl 80017d8 <ADG715_SetRegisterValue>
}
8001812: bf00 nop
8001814: bd80 pop {r7, pc}
...
08001818 <ADG715_Update>:
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000, AD5934_CH_EC, ...
*
* @return none.
******************************************************************************/
void ADG715_Update(AD5934_Channel_t channel)
{
8001818: b580 push {r7, lr}
800181a: b082 sub sp, #8
800181c: af00 add r7, sp, #0
800181e: 4603 mov r3, r0
8001820: 71fb strb r3, [r7, #7]
// Garante que o índice recebido não ultrapassa os limites do vetor
if (channel >= AD5934_CH_MAX)
8001822: 79fb ldrb r3, [r7, #7]
8001824: 2b0e cmp r3, #14
8001826: d810 bhi.n 800184a <ADG715_Update+0x32>
return;
// Envia o byte combinado via I2C (Make-before-break nativo por barramento)
ADG715_SetRegisterValue(ADG715_Channel_Map[channel]);
8001828: 79fb ldrb r3, [r7, #7]
800182a: 4a0a ldr r2, [pc, #40] @ (8001854 <ADG715_Update+0x3c>)
800182c: 5cd3 ldrb r3, [r2, r3]
800182e: 4618 mov r0, r3
8001830: f7ff ffd2 bl 80017d8 <ADG715_SetRegisterValue>
// Gestão inteligente do delay de acomodação
if (channel >= AD5934_CH_EC_LOW_GAIN)
8001834: 79fb ldrb r3, [r7, #7]
8001836: 2b0b cmp r3, #11
8001838: d903 bls.n 8001842 <ADG715_Update+0x2a>
HAL_Delay(20); // Canais de Condutividade Elétrica (CE) necessitam de maior estabilização química
800183a: 2014 movs r0, #20
800183c: f001 fb5e bl 8002efc <HAL_Delay>
8001840: e004 b.n 800184c <ADG715_Update+0x34>
else
HAL_Delay(10); // Resistores puros e RTD estabilizam mais rapidamente
8001842: 200a movs r0, #10
8001844: f001 fb5a bl 8002efc <HAL_Delay>
8001848: e000 b.n 800184c <ADG715_Update+0x34>
return;
800184a: bf00 nop
}
800184c: 3708 adds r7, #8
800184e: 46bd mov sp, r7
8001850: bd80 pop {r7, pc}
8001852: bf00 nop
8001854: 08006794 .word 0x08006794
08001858 <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
8001858: b580 push {r7, lr}
800185a: b084 sub sp, #16
800185c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800185e: 1d3b adds r3, r7, #4
8001860: 2200 movs r2, #0
8001862: 601a str r2, [r3, #0]
8001864: 605a str r2, [r3, #4]
8001866: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8001868: 4b18 ldr r3, [pc, #96] @ (80018cc <MX_ADC1_Init+0x74>)
800186a: 4a19 ldr r2, [pc, #100] @ (80018d0 <MX_ADC1_Init+0x78>)
800186c: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
800186e: 4b17 ldr r3, [pc, #92] @ (80018cc <MX_ADC1_Init+0x74>)
8001870: 2200 movs r2, #0
8001872: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
8001874: 4b15 ldr r3, [pc, #84] @ (80018cc <MX_ADC1_Init+0x74>)
8001876: 2201 movs r2, #1
8001878: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
800187a: 4b14 ldr r3, [pc, #80] @ (80018cc <MX_ADC1_Init+0x74>)
800187c: 2200 movs r2, #0
800187e: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001880: 4b12 ldr r3, [pc, #72] @ (80018cc <MX_ADC1_Init+0x74>)
8001882: f44f 2260 mov.w r2, #917504 @ 0xe0000
8001886: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001888: 4b10 ldr r3, [pc, #64] @ (80018cc <MX_ADC1_Init+0x74>)
800188a: 2200 movs r2, #0
800188c: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 1;
800188e: 4b0f ldr r3, [pc, #60] @ (80018cc <MX_ADC1_Init+0x74>)
8001890: 2201 movs r2, #1
8001892: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8001894: 480d ldr r0, [pc, #52] @ (80018cc <MX_ADC1_Init+0x74>)
8001896: f001 fb55 bl 8002f44 <HAL_ADC_Init>
800189a: 4603 mov r3, r0
800189c: 2b00 cmp r3, #0
800189e: d001 beq.n 80018a4 <MX_ADC1_Init+0x4c>
{
Error_Handler();
80018a0: f001 f8be bl 8002a20 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_0;
80018a4: 2300 movs r3, #0
80018a6: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80018a8: 2301 movs r3, #1
80018aa: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80018ac: 2300 movs r3, #0
80018ae: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80018b0: 1d3b adds r3, r7, #4
80018b2: 4619 mov r1, r3
80018b4: 4805 ldr r0, [pc, #20] @ (80018cc <MX_ADC1_Init+0x74>)
80018b6: f001 fc1d bl 80030f4 <HAL_ADC_ConfigChannel>
80018ba: 4603 mov r3, r0
80018bc: 2b00 cmp r3, #0
80018be: d001 beq.n 80018c4 <MX_ADC1_Init+0x6c>
{
Error_Handler();
80018c0: f001 f8ae bl 8002a20 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80018c4: bf00 nop
80018c6: 3710 adds r7, #16
80018c8: 46bd mov sp, r7
80018ca: bd80 pop {r7, pc}
80018cc: 2000016c .word 0x2000016c
80018d0: 40012400 .word 0x40012400
080018d4 <MX_ADC2_Init>:
/* ADC2 init function */
void MX_ADC2_Init(void)
{
80018d4: b580 push {r7, lr}
80018d6: b084 sub sp, #16
80018d8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80018da: 1d3b adds r3, r7, #4
80018dc: 2200 movs r2, #0
80018de: 601a str r2, [r3, #0]
80018e0: 605a str r2, [r3, #4]
80018e2: 609a str r2, [r3, #8]
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
80018e4: 4b18 ldr r3, [pc, #96] @ (8001948 <MX_ADC2_Init+0x74>)
80018e6: 4a19 ldr r2, [pc, #100] @ (800194c <MX_ADC2_Init+0x78>)
80018e8: 601a str r2, [r3, #0]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
80018ea: 4b17 ldr r3, [pc, #92] @ (8001948 <MX_ADC2_Init+0x74>)
80018ec: 2200 movs r2, #0
80018ee: 609a str r2, [r3, #8]
hadc2.Init.ContinuousConvMode = ENABLE;
80018f0: 4b15 ldr r3, [pc, #84] @ (8001948 <MX_ADC2_Init+0x74>)
80018f2: 2201 movs r2, #1
80018f4: 731a strb r2, [r3, #12]
hadc2.Init.DiscontinuousConvMode = DISABLE;
80018f6: 4b14 ldr r3, [pc, #80] @ (8001948 <MX_ADC2_Init+0x74>)
80018f8: 2200 movs r2, #0
80018fa: 751a strb r2, [r3, #20]
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80018fc: 4b12 ldr r3, [pc, #72] @ (8001948 <MX_ADC2_Init+0x74>)
80018fe: f44f 2260 mov.w r2, #917504 @ 0xe0000
8001902: 61da str r2, [r3, #28]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001904: 4b10 ldr r3, [pc, #64] @ (8001948 <MX_ADC2_Init+0x74>)
8001906: 2200 movs r2, #0
8001908: 605a str r2, [r3, #4]
hadc2.Init.NbrOfConversion = 1;
800190a: 4b0f ldr r3, [pc, #60] @ (8001948 <MX_ADC2_Init+0x74>)
800190c: 2201 movs r2, #1
800190e: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8001910: 480d ldr r0, [pc, #52] @ (8001948 <MX_ADC2_Init+0x74>)
8001912: f001 fb17 bl 8002f44 <HAL_ADC_Init>
8001916: 4603 mov r3, r0
8001918: 2b00 cmp r3, #0
800191a: d001 beq.n 8001920 <MX_ADC2_Init+0x4c>
{
Error_Handler();
800191c: f001 f880 bl 8002a20 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
8001920: 2301 movs r3, #1
8001922: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001924: 2301 movs r3, #1
8001926: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
8001928: 2300 movs r3, #0
800192a: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
800192c: 1d3b adds r3, r7, #4
800192e: 4619 mov r1, r3
8001930: 4805 ldr r0, [pc, #20] @ (8001948 <MX_ADC2_Init+0x74>)
8001932: f001 fbdf bl 80030f4 <HAL_ADC_ConfigChannel>
8001936: 4603 mov r3, r0
8001938: 2b00 cmp r3, #0
800193a: d001 beq.n 8001940 <MX_ADC2_Init+0x6c>
{
Error_Handler();
800193c: f001 f870 bl 8002a20 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8001940: bf00 nop
8001942: 3710 adds r7, #16
8001944: 46bd mov sp, r7
8001946: bd80 pop {r7, pc}
8001948: 2000019c .word 0x2000019c
800194c: 40012800 .word 0x40012800
08001950 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
8001950: b580 push {r7, lr}
8001952: b08a sub sp, #40 @ 0x28
8001954: af00 add r7, sp, #0
8001956: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001958: f107 0318 add.w r3, r7, #24
800195c: 2200 movs r2, #0
800195e: 601a str r2, [r3, #0]
8001960: 605a str r2, [r3, #4]
8001962: 609a str r2, [r3, #8]
8001964: 60da str r2, [r3, #12]
if(adcHandle->Instance==ADC1)
8001966: 687b ldr r3, [r7, #4]
8001968: 681b ldr r3, [r3, #0]
800196a: 4a28 ldr r2, [pc, #160] @ (8001a0c <HAL_ADC_MspInit+0xbc>)
800196c: 4293 cmp r3, r2
800196e: d122 bne.n 80019b6 <HAL_ADC_MspInit+0x66>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001970: 4b27 ldr r3, [pc, #156] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
8001972: 699b ldr r3, [r3, #24]
8001974: 4a26 ldr r2, [pc, #152] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
8001976: f443 7300 orr.w r3, r3, #512 @ 0x200
800197a: 6193 str r3, [r2, #24]
800197c: 4b24 ldr r3, [pc, #144] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
800197e: 699b ldr r3, [r3, #24]
8001980: f403 7300 and.w r3, r3, #512 @ 0x200
8001984: 617b str r3, [r7, #20]
8001986: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001988: 4b21 ldr r3, [pc, #132] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
800198a: 699b ldr r3, [r3, #24]
800198c: 4a20 ldr r2, [pc, #128] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
800198e: f043 0304 orr.w r3, r3, #4
8001992: 6193 str r3, [r2, #24]
8001994: 4b1e ldr r3, [pc, #120] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
8001996: 699b ldr r3, [r3, #24]
8001998: f003 0304 and.w r3, r3, #4
800199c: 613b str r3, [r7, #16]
800199e: 693b ldr r3, [r7, #16]
/**ADC1 GPIO Configuration
PA0-WKUP ------> ADC1_IN0
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
80019a0: 2303 movs r3, #3
80019a2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80019a4: 2303 movs r3, #3
80019a6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80019a8: f107 0318 add.w r3, r7, #24
80019ac: 4619 mov r1, r3
80019ae: 4819 ldr r0, [pc, #100] @ (8001a14 <HAL_ADC_MspInit+0xc4>)
80019b0: f002 f89a bl 8003ae8 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80019b4: e026 b.n 8001a04 <HAL_ADC_MspInit+0xb4>
else if(adcHandle->Instance==ADC2)
80019b6: 687b ldr r3, [r7, #4]
80019b8: 681b ldr r3, [r3, #0]
80019ba: 4a17 ldr r2, [pc, #92] @ (8001a18 <HAL_ADC_MspInit+0xc8>)
80019bc: 4293 cmp r3, r2
80019be: d121 bne.n 8001a04 <HAL_ADC_MspInit+0xb4>
__HAL_RCC_ADC2_CLK_ENABLE();
80019c0: 4b13 ldr r3, [pc, #76] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019c2: 699b ldr r3, [r3, #24]
80019c4: 4a12 ldr r2, [pc, #72] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019c6: f443 6380 orr.w r3, r3, #1024 @ 0x400
80019ca: 6193 str r3, [r2, #24]
80019cc: 4b10 ldr r3, [pc, #64] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019ce: 699b ldr r3, [r3, #24]
80019d0: f403 6380 and.w r3, r3, #1024 @ 0x400
80019d4: 60fb str r3, [r7, #12]
80019d6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80019d8: 4b0d ldr r3, [pc, #52] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019da: 699b ldr r3, [r3, #24]
80019dc: 4a0c ldr r2, [pc, #48] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019de: f043 0304 orr.w r3, r3, #4
80019e2: 6193 str r3, [r2, #24]
80019e4: 4b0a ldr r3, [pc, #40] @ (8001a10 <HAL_ADC_MspInit+0xc0>)
80019e6: 699b ldr r3, [r3, #24]
80019e8: f003 0304 and.w r3, r3, #4
80019ec: 60bb str r3, [r7, #8]
80019ee: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
80019f0: 2303 movs r3, #3
80019f2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80019f4: 2303 movs r3, #3
80019f6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80019f8: f107 0318 add.w r3, r7, #24
80019fc: 4619 mov r1, r3
80019fe: 4805 ldr r0, [pc, #20] @ (8001a14 <HAL_ADC_MspInit+0xc4>)
8001a00: f002 f872 bl 8003ae8 <HAL_GPIO_Init>
}
8001a04: bf00 nop
8001a06: 3728 adds r7, #40 @ 0x28
8001a08: 46bd mov sp, r7
8001a0a: bd80 pop {r7, pc}
8001a0c: 40012400 .word 0x40012400
8001a10: 40021000 .word 0x40021000
8001a14: 40010800 .word 0x40010800
8001a18: 40012800 .word 0x40012800
08001a1c <writeRegister>:
ADS1015_I2C i2c;
float ph_dut_samples[ADS1015_PH_AVERAGES]={0};
// Write the register
static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
8001a1c: b580 push {r7, lr}
8001a1e: b086 sub sp, #24
8001a20: af02 add r7, sp, #8
8001a22: 6078 str r0, [r7, #4]
8001a24: 460b mov r3, r1
8001a26: 70fb strb r3, [r7, #3]
8001a28: 4613 mov r3, r2
8001a2a: 803b strh r3, [r7, #0]
uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
8001a2c: 78fb ldrb r3, [r7, #3]
8001a2e: 733b strb r3, [r7, #12]
8001a30: 883b ldrh r3, [r7, #0]
8001a32: 0a1b lsrs r3, r3, #8
8001a34: b29b uxth r3, r3
8001a36: b2db uxtb r3, r3
8001a38: 737b strb r3, [r7, #13]
8001a3a: 883b ldrh r3, [r7, #0]
8001a3c: b2db uxtb r3, r3
8001a3e: 73bb strb r3, [r7, #14]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
8001a40: 687b ldr r3, [r7, #4]
8001a42: 68d8 ldr r0, [r3, #12]
8001a44: 687b ldr r3, [r7, #4]
8001a46: 8819 ldrh r1, [r3, #0]
8001a48: f107 020c add.w r2, r7, #12
8001a4c: 230a movs r3, #10
8001a4e: 9300 str r3, [sp, #0]
8001a50: 2303 movs r3, #3
8001a52: f002 fb59 bl 8004108 <HAL_I2C_Master_Transmit>
}
8001a56: bf00 nop
8001a58: 3710 adds r7, #16
8001a5a: 46bd mov sp, r7
8001a5c: bd80 pop {r7, pc}
08001a5e <readRegister>:
// Read the register
static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
8001a5e: b580 push {r7, lr}
8001a60: b086 sub sp, #24
8001a62: af02 add r7, sp, #8
8001a64: 6078 str r0, [r7, #4]
8001a66: 460b mov r3, r1
8001a68: 70fb strb r3, [r7, #3]
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, &reg, 1, 10);
8001a6a: 687b ldr r3, [r7, #4]
8001a6c: 68d8 ldr r0, [r3, #12]
8001a6e: 687b ldr r3, [r7, #4]
8001a70: 8819 ldrh r1, [r3, #0]
8001a72: 1cfa adds r2, r7, #3
8001a74: 230a movs r3, #10
8001a76: 9300 str r3, [sp, #0]
8001a78: 2301 movs r3, #1
8001a7a: f002 fb45 bl 8004108 <HAL_I2C_Master_Transmit>
uint8_t pData[2] = { 0, 0 };
8001a7e: 2300 movs r3, #0
8001a80: 81bb strh r3, [r7, #12]
HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
8001a82: 687b ldr r3, [r7, #4]
8001a84: 68d8 ldr r0, [r3, #12]
8001a86: 687b ldr r3, [r7, #4]
8001a88: 8819 ldrh r1, [r3, #0]
8001a8a: f107 020c add.w r2, r7, #12
8001a8e: 230a movs r3, #10
8001a90: 9300 str r3, [sp, #0]
8001a92: 2302 movs r3, #2
8001a94: f002 fc36 bl 8004304 <HAL_I2C_Master_Receive>
return ((pData[0] << 8) | pData[1]);
8001a98: 7b3b ldrb r3, [r7, #12]
8001a9a: b21b sxth r3, r3
8001a9c: 021b lsls r3, r3, #8
8001a9e: b21a sxth r2, r3
8001aa0: 7b7b ldrb r3, [r7, #13]
8001aa2: b21b sxth r3, r3
8001aa4: 4313 orrs r3, r2
8001aa6: b21b sxth r3, r3
8001aa8: b29b uxth r3, r3
}
8001aaa: 4618 mov r0, r3
8001aac: 3710 adds r7, #16
8001aae: 46bd mov sp, r7
8001ab0: bd80 pop {r7, pc}
08001ab2 <ADS1015>:
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // This MUST have GPIO PA5 ready to use - ERROR I2C - Wrong address
}
// Declare an ADS1015 structure
void ADS1015(ADS1015_I2C *i2c, I2C_HandleTypeDef *hi2c, uint8_t i2cAddress) {
8001ab2: b480 push {r7}
8001ab4: b085 sub sp, #20
8001ab6: af00 add r7, sp, #0
8001ab8: 60f8 str r0, [r7, #12]
8001aba: 60b9 str r1, [r7, #8]
8001abc: 4613 mov r3, r2
8001abe: 71fb strb r3, [r7, #7]
i2c->hi2c = hi2c;
8001ac0: 68fb ldr r3, [r7, #12]
8001ac2: 68ba ldr r2, [r7, #8]
8001ac4: 60da str r2, [r3, #12]
i2c->m_i2cAddress = i2cAddress << 1; // It's Important to shift the address << 1
8001ac6: 79fb ldrb r3, [r7, #7]
8001ac8: b29b uxth r3, r3
8001aca: 005b lsls r3, r3, #1
8001acc: b29a uxth r2, r3
8001ace: 68fb ldr r3, [r7, #12]
8001ad0: 801a strh r2, [r3, #0]
i2c->m_conversionDelay = ADS1015_CONVERSIONDELAY;
8001ad2: 68fb ldr r3, [r7, #12]
8001ad4: 2204 movs r2, #4
8001ad6: 605a str r2, [r3, #4]
i2c->m_bitShift = 4;
8001ad8: 68fb ldr r3, [r7, #12]
8001ada: 2204 movs r2, #4
8001adc: 721a strb r2, [r3, #8]
i2c->m_gain = GAIN_TWOTHIRDS; /* +/- 6.144V range (limited to VDD +0.3V max!) */
8001ade: 68fb ldr r3, [r7, #12]
8001ae0: 2200 movs r2, #0
8001ae2: 815a strh r2, [r3, #10]
//ADSbegin(i2c); //Ready is not used
}
8001ae4: bf00 nop
8001ae6: 3714 adds r7, #20
8001ae8: 46bd mov sp, r7
8001aea: bc80 pop {r7}
8001aec: 4770 bx lr
08001aee <ADSsetGain>:
// ADSsetGain(GAIN_TWO); // 2x gain +/- 2.048V 1 bit = 1mV 0.0625mV
// ADSsetGain(GAIN_FOUR); // 4x gain +/- 1.024V 1 bit = 0.5mV 0.03125mV
// ADSsetGain(GAIN_EIGHT); // 8x gain +/- 0.512V 1 bit = 0.25mV 0.015625mV
// ADSsetGain(GAIN_SIXTEEN); // 16x gain +/- 0.256V 1 bit = 0.125mV 0.0078125mV
*/
void ADSsetGain(ADS1015_I2C *i2c, adsGain_t gain) {
8001aee: b480 push {r7}
8001af0: b083 sub sp, #12
8001af2: af00 add r7, sp, #0
8001af4: 6078 str r0, [r7, #4]
8001af6: 460b mov r3, r1
8001af8: 807b strh r3, [r7, #2]
i2c->m_gain = gain;
8001afa: 687b ldr r3, [r7, #4]
8001afc: 887a ldrh r2, [r7, #2]
8001afe: 815a strh r2, [r3, #10]
}
8001b00: bf00 nop
8001b02: 370c adds r7, #12
8001b04: 46bd mov sp, r7
8001b06: bc80 pop {r7}
8001b08: 4770 bx lr
08001b0a <ADSreadADC_Differential_0_1>:
/*
* Reads the conversion results, measuring the voltage
* difference between the P (AIN0) and N (AIN1) input. Generates
* a signed value since the difference can be either positive or negative.
*/
int16_t ADSreadADC_Differential_0_1(ADS1015_I2C *i2c) {
8001b0a: b580 push {r7, lr}
8001b0c: b084 sub sp, #16
8001b0e: af00 add r7, sp, #0
8001b10: 6078 str r0, [r7, #4]
// Start with default values
uint16_t config =
8001b12: f240 1303 movw r3, #259 @ 0x103
8001b16: 81bb strh r3, [r7, #12]
ADS1015_REG_CONFIG_CMODE_TRAD | // Traditional comparator (default val)
ADS1015_REG_CONFIG_DR_128SPS | // 128 samples per second (default)
ADS1015_REG_CONFIG_MODE_SINGLE; // Single-shot mode (default)
// Set PGA/voltage range
config |= i2c->m_gain;
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 895a ldrh r2, [r3, #10]
8001b1c: 89bb ldrh r3, [r7, #12]
8001b1e: 4313 orrs r3, r2
8001b20: 81bb strh r3, [r7, #12]
// Set channels
config |= ADS1015_REG_CONFIG_MUX_DIFF_0_1; // AIN0 = P, AIN1 = N
// Set 'start single-conversion' bit
config |= ADS1015_REG_CONFIG_OS_SINGLE;
8001b22: 89bb ldrh r3, [r7, #12]
8001b24: ea6f 4343 mvn.w r3, r3, lsl #17
8001b28: ea6f 4353 mvn.w r3, r3, lsr #17
8001b2c: 81bb strh r3, [r7, #12]
// Write config register to the ADC
writeRegister(i2c, ADS1015_REG_POINTER_CONFIG, config);
8001b2e: 89bb ldrh r3, [r7, #12]
8001b30: 461a mov r2, r3
8001b32: 2101 movs r1, #1
8001b34: 6878 ldr r0, [r7, #4]
8001b36: f7ff ff71 bl 8001a1c <writeRegister>
// Wait for the conversion to complete
HAL_Delay(i2c->m_conversionDelay);
8001b3a: 687b ldr r3, [r7, #4]
8001b3c: 685b ldr r3, [r3, #4]
8001b3e: 4618 mov r0, r3
8001b40: f001 f9dc bl 8002efc <HAL_Delay>
// Read the conversion results
uint16_t res = readRegister(i2c, ADS1015_REG_POINTER_CONVERT) >> i2c->m_bitShift;
8001b44: 2100 movs r1, #0
8001b46: 6878 ldr r0, [r7, #4]
8001b48: f7ff ff89 bl 8001a5e <readRegister>
8001b4c: 4603 mov r3, r0
8001b4e: 461a mov r2, r3
8001b50: 687b ldr r3, [r7, #4]
8001b52: 7a1b ldrb r3, [r3, #8]
8001b54: fa42 f303 asr.w r3, r2, r3
8001b58: 81fb strh r3, [r7, #14]
if (i2c->m_bitShift == 0) {
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 7a1b ldrb r3, [r3, #8]
8001b5e: 2b00 cmp r3, #0
8001b60: d102 bne.n 8001b68 <ADSreadADC_Differential_0_1+0x5e>
return (int16_t) res;
8001b62: f9b7 300e ldrsh.w r3, [r7, #14]
8001b66: e00b b.n 8001b80 <ADSreadADC_Differential_0_1+0x76>
} else {
// Shift 12-bit results right 4 bits for the ADS1015,
// making sure we keep the sign bit intact
if (res > 0x07FF) {
8001b68: 89fb ldrh r3, [r7, #14]
8001b6a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8001b6e: d305 bcc.n 8001b7c <ADSreadADC_Differential_0_1+0x72>
// negative number - extend the sign to 16th bit
res |= 0xF000;
8001b70: 89fb ldrh r3, [r7, #14]
8001b72: ea6f 5303 mvn.w r3, r3, lsl #20
8001b76: ea6f 5313 mvn.w r3, r3, lsr #20
8001b7a: 81fb strh r3, [r7, #14]
}
return (int16_t) res;
8001b7c: f9b7 300e ldrsh.w r3, [r7, #14]
}
}
8001b80: 4618 mov r0, r3
8001b82: 3710 adds r7, #16
8001b84: 46bd mov sp, r7
8001b86: bd80 pop {r7, pc}
08001b88 <ADSCalculate_ph_mV>:
return (int16_t) res;
}
}
float ADSCalculate_ph_mV(void) // pH in mV
{
8001b88: b580 push {r7, lr}
8001b8a: b082 sub sp, #8
8001b8c: af00 add r7, sp, #0
float ph_dut_sum;
uint8_t i;
for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
8001b8e: 230f movs r3, #15
8001b90: 70fb strb r3, [r7, #3]
8001b92: e00b b.n 8001bac <ADSCalculate_ph_mV+0x24>
ph_dut_samples[i] = ph_dut_samples[i-1];
8001b94: 78fb ldrb r3, [r7, #3]
8001b96: 1e5a subs r2, r3, #1
8001b98: 78fb ldrb r3, [r7, #3]
8001b9a: 4923 ldr r1, [pc, #140] @ (8001c28 <ADSCalculate_ph_mV+0xa0>)
8001b9c: f851 2022 ldr.w r2, [r1, r2, lsl #2]
8001ba0: 4921 ldr r1, [pc, #132] @ (8001c28 <ADSCalculate_ph_mV+0xa0>)
8001ba2: f841 2023 str.w r2, [r1, r3, lsl #2]
for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
8001ba6: 78fb ldrb r3, [r7, #3]
8001ba8: 3b01 subs r3, #1
8001baa: 70fb strb r3, [r7, #3]
8001bac: 78fb ldrb r3, [r7, #3]
8001bae: 2b00 cmp r3, #0
8001bb0: d1f0 bne.n 8001b94 <ADSCalculate_ph_mV+0xc>
ph_dut_samples[0] = (((float)(ADSreadADC_Differential_0_1(&i2c)) * ADS1015_ADC_VREF) / ADS1015_ADC_MAX); // 1. Converter leitura bruta do ADC para tensão real (mV)
8001bb2: 481e ldr r0, [pc, #120] @ (8001c2c <ADSCalculate_ph_mV+0xa4>)
8001bb4: f7ff ffa9 bl 8001b0a <ADSreadADC_Differential_0_1>
8001bb8: 4603 mov r3, r0
8001bba: 4618 mov r0, r3
8001bbc: f7fe ff1e bl 80009fc <__aeabi_i2f>
8001bc0: 4603 mov r3, r0
8001bc2: f04f 4189 mov.w r1, #1149239296 @ 0x44800000
8001bc6: 4618 mov r0, r3
8001bc8: f7fe ff6c bl 8000aa4 <__aeabi_fmul>
8001bcc: 4603 mov r3, r0
8001bce: 4918 ldr r1, [pc, #96] @ (8001c30 <ADSCalculate_ph_mV+0xa8>)
8001bd0: 4618 mov r0, r3
8001bd2: f7ff f81b bl 8000c0c <__aeabi_fdiv>
8001bd6: 4603 mov r3, r0
8001bd8: 461a mov r2, r3
8001bda: 4b13 ldr r3, [pc, #76] @ (8001c28 <ADSCalculate_ph_mV+0xa0>)
8001bdc: 601a str r2, [r3, #0]
for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
8001bde: 2300 movs r3, #0
8001be0: 70fb strb r3, [r7, #3]
8001be2: f04f 0300 mov.w r3, #0
8001be6: 607b str r3, [r7, #4]
8001be8: e00c b.n 8001c04 <ADSCalculate_ph_mV+0x7c>
ph_dut_sum += ph_dut_samples[i];
8001bea: 78fb ldrb r3, [r7, #3]
8001bec: 4a0e ldr r2, [pc, #56] @ (8001c28 <ADSCalculate_ph_mV+0xa0>)
8001bee: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001bf2: 4619 mov r1, r3
8001bf4: 6878 ldr r0, [r7, #4]
8001bf6: f7fe fe4d bl 8000894 <__addsf3>
8001bfa: 4603 mov r3, r0
8001bfc: 607b str r3, [r7, #4]
for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
8001bfe: 78fb ldrb r3, [r7, #3]
8001c00: 3301 adds r3, #1
8001c02: 70fb strb r3, [r7, #3]
8001c04: 78fb ldrb r3, [r7, #3]
8001c06: 2b0f cmp r3, #15
8001c08: d9ef bls.n 8001bea <ADSCalculate_ph_mV+0x62>
return (ADSRound_Float_Precision((ph_dut_sum/ADS1015_PH_AVERAGES),2));
8001c0a: f04f 4183 mov.w r1, #1098907648 @ 0x41800000
8001c0e: 6878 ldr r0, [r7, #4]
8001c10: f7fe fffc bl 8000c0c <__aeabi_fdiv>
8001c14: 4603 mov r3, r0
8001c16: 2102 movs r1, #2
8001c18: 4618 mov r0, r3
8001c1a: f000 f8fb bl 8001e14 <ADSRound_Float_Precision>
8001c1e: 4603 mov r3, r0
}
8001c20: 4618 mov r0, r3
8001c22: 3708 adds r7, #8
8001c24: 46bd mov sp, r7
8001c26: bd80 pop {r7, pc}
8001c28: 200001dc .word 0x200001dc
8001c2c: 200001cc .word 0x200001cc
8001c30: 457ff000 .word 0x457ff000
08001c34 <ADSCalculate_ph_Compensated>:
*
* @return float Valor de pH calculado (0.0 a 14.0).
*/
float ADSCalculate_ph_Compensated(float temp_dut)
{
8001c34: b590 push {r4, r7, lr}
8001c36: b089 sub sp, #36 @ 0x24
8001c38: af00 add r7, sp, #0
8001c3a: 6078 str r0, [r7, #4]
float dut_mV = ADSCalculate_ph_mV();
8001c3c: f7ff ffa4 bl 8001b88 <ADSCalculate_ph_mV>
8001c40: 61f8 str r0, [r7, #28]
float t_cal_k = flash_data.ph_temperature + 273.15f;
8001c42: 4b1c ldr r3, [pc, #112] @ (8001cb4 <ADSCalculate_ph_Compensated+0x80>)
8001c44: 68db ldr r3, [r3, #12]
8001c46: 491c ldr r1, [pc, #112] @ (8001cb8 <ADSCalculate_ph_Compensated+0x84>)
8001c48: 4618 mov r0, r3
8001c4a: f7fe fe23 bl 8000894 <__addsf3>
8001c4e: 4603 mov r3, r0
8001c50: 61bb str r3, [r7, #24]
float t_dut_k = temp_dut + 273.15f;
8001c52: 4919 ldr r1, [pc, #100] @ (8001cb8 <ADSCalculate_ph_Compensated+0x84>)
8001c54: 6878 ldr r0, [r7, #4]
8001c56: f7fe fe1d bl 8000894 <__addsf3>
8001c5a: 4603 mov r3, r0
8001c5c: 617b str r3, [r7, #20]
float slope_dut = flash_data.ph_slope_mV * (t_dut_k / t_cal_k);
8001c5e: 4b15 ldr r3, [pc, #84] @ (8001cb4 <ADSCalculate_ph_Compensated+0x80>)
8001c60: 691c ldr r4, [r3, #16]
8001c62: 69b9 ldr r1, [r7, #24]
8001c64: 6978 ldr r0, [r7, #20]
8001c66: f7fe ffd1 bl 8000c0c <__aeabi_fdiv>
8001c6a: 4603 mov r3, r0
8001c6c: 4619 mov r1, r3
8001c6e: 4620 mov r0, r4
8001c70: f7fe ff18 bl 8000aa4 <__aeabi_fmul>
8001c74: 4603 mov r3, r0
8001c76: 613b str r3, [r7, #16]
float ph_result = (flash_data.ph7_real + ((dut_mV - flash_data.ph7_mV) / slope_dut));
8001c78: 4b0e ldr r3, [pc, #56] @ (8001cb4 <ADSCalculate_ph_Compensated+0x80>)
8001c7a: 695c ldr r4, [r3, #20]
8001c7c: 4b0d ldr r3, [pc, #52] @ (8001cb4 <ADSCalculate_ph_Compensated+0x80>)
8001c7e: 689b ldr r3, [r3, #8]
8001c80: 4619 mov r1, r3
8001c82: 69f8 ldr r0, [r7, #28]
8001c84: f7fe fe04 bl 8000890 <__aeabi_fsub>
8001c88: 4603 mov r3, r0
8001c8a: 6939 ldr r1, [r7, #16]
8001c8c: 4618 mov r0, r3
8001c8e: f7fe ffbd bl 8000c0c <__aeabi_fdiv>
8001c92: 4603 mov r3, r0
8001c94: 4619 mov r1, r3
8001c96: 4620 mov r0, r4
8001c98: f7fe fdfc bl 8000894 <__addsf3>
8001c9c: 4603 mov r3, r0
8001c9e: 60fb str r3, [r7, #12]
return (ADSRound_Float_Precision(ph_result,2));
8001ca0: 2102 movs r1, #2
8001ca2: 68f8 ldr r0, [r7, #12]
8001ca4: f000 f8b6 bl 8001e14 <ADSRound_Float_Precision>
8001ca8: 4603 mov r3, r0
}
8001caa: 4618 mov r0, r3
8001cac: 3724 adds r7, #36 @ 0x24
8001cae: 46bd mov sp, r7
8001cb0: bd90 pop {r4, r7, pc}
8001cb2: bf00 nop
8001cb4: 20000224 .word 0x20000224
8001cb8: 43889333 .word 0x43889333
08001cbc <ADSinterpolate_ph>:
* @param temp_target The target temperature to interpolate for.
* @param row_index Index of the buffer row (1 for pH4, 2 for pH7).
* @return float Interpolated value from the matrix.
*/
float ADSinterpolate_ph(float temp_target, uint8_t row_index)
{
8001cbc: b5b0 push {r4, r5, r7, lr}
8001cbe: b0ac sub sp, #176 @ 0xb0
8001cc0: af00 add r7, sp, #0
8001cc2: 6078 str r0, [r7, #4]
8001cc4: 460b mov r3, r1
8001cc6: 70fb strb r3, [r7, #3]
/* Matrix with {Temperature, Ph 4 Buffer, Ph 7 Buffer} */
const float lut_matrix_buffer_ph[ADS1015_INTERPOLATION_ROWS][ADS1015_PH_TEMP_INTER_POINTS] = {
8001cc8: 4a51 ldr r2, [pc, #324] @ (8001e10 <ADSinterpolate_ph+0x154>)
8001cca: f107 030c add.w r3, r7, #12
8001cce: 4611 mov r1, r2
8001cd0: 2290 movs r2, #144 @ 0x90
8001cd2: 4618 mov r0, r3
8001cd4: f004 fc18 bl 8006508 <memcpy>
{0.0f, 5.0f, 10.0f, 15.0f, 20.0f, 25.0f, 30.0f, 35.0f, 40.0f, 45.0f, 50.0f, 55.0f}, // Temperature
{4.01f, 4.00f, 4.00f, 4.00f, 4.00f, 4.01f, 4.01f, 4.02f, 4.03f, 4.05f, 4.06f, 4.10f}, // Buffer ph 4
{7.12f, 7.07f, 7.05f, 7.03f, 7.01f, 7.00f, 6.98f, 6.97f, 6.96f, 6.96f, 6.96f, 6.96f},}; // Buffer ph 7
uint8_t i = 0;
8001cd8: 2300 movs r3, #0
8001cda: f887 30af strb.w r3, [r7, #175] @ 0xaf
/* Boundary Check: Clamp to first or last index if out of range */
if (temp_target <= lut_matrix_buffer_ph[0][0])
8001cde: 68fb ldr r3, [r7, #12]
8001ce0: 4619 mov r1, r3
8001ce2: 6878 ldr r0, [r7, #4]
8001ce4: f7ff f886 bl 8000df4 <__aeabi_fcmple>
8001ce8: 4603 mov r3, r0
8001cea: 2b00 cmp r3, #0
8001cec: d009 beq.n 8001d02 <ADSinterpolate_ph+0x46>
return lut_matrix_buffer_ph[row_index][0];
8001cee: 78fa ldrb r2, [r7, #3]
8001cf0: 4613 mov r3, r2
8001cf2: 005b lsls r3, r3, #1
8001cf4: 4413 add r3, r2
8001cf6: 011b lsls r3, r3, #4
8001cf8: 33b0 adds r3, #176 @ 0xb0
8001cfa: 443b add r3, r7
8001cfc: 3ba4 subs r3, #164 @ 0xa4
8001cfe: 681b ldr r3, [r3, #0]
8001d00: e082 b.n 8001e08 <ADSinterpolate_ph+0x14c>
if (temp_target >= lut_matrix_buffer_ph[0][ADS1015_PH_TEMP_INTER_POINTS-1])
8001d02: 6bbb ldr r3, [r7, #56] @ 0x38
8001d04: 4619 mov r1, r3
8001d06: 6878 ldr r0, [r7, #4]
8001d08: f7ff f87e bl 8000e08 <__aeabi_fcmpge>
8001d0c: 4603 mov r3, r0
8001d0e: 2b00 cmp r3, #0
8001d10: d009 beq.n 8001d26 <ADSinterpolate_ph+0x6a>
return lut_matrix_buffer_ph[row_index][ADS1015_PH_TEMP_INTER_POINTS-1];
8001d12: 78fa ldrb r2, [r7, #3]
8001d14: 4613 mov r3, r2
8001d16: 005b lsls r3, r3, #1
8001d18: 4413 add r3, r2
8001d1a: 011b lsls r3, r3, #4
8001d1c: 33b0 adds r3, #176 @ 0xb0
8001d1e: 443b add r3, r7
8001d20: 3b78 subs r3, #120 @ 0x78
8001d22: 681b ldr r3, [r3, #0]
8001d24: e070 b.n 8001e08 <ADSinterpolate_ph+0x14c>
/* Find interpolation interval */
while (i < (ADS1015_PH_TEMP_INTER_POINTS-1) && lut_matrix_buffer_ph[0][i+1] < temp_target)
8001d26: e004 b.n 8001d32 <ADSinterpolate_ph+0x76>
{
i++;
8001d28: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001d2c: 3301 adds r3, #1
8001d2e: f887 30af strb.w r3, [r7, #175] @ 0xaf
while (i < (ADS1015_PH_TEMP_INTER_POINTS-1) && lut_matrix_buffer_ph[0][i+1] < temp_target)
8001d32: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001d36: 2b0a cmp r3, #10
8001d38: d80e bhi.n 8001d58 <ADSinterpolate_ph+0x9c>
8001d3a: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001d3e: 3301 adds r3, #1
8001d40: 009b lsls r3, r3, #2
8001d42: 33b0 adds r3, #176 @ 0xb0
8001d44: 443b add r3, r7
8001d46: f853 3ca4 ldr.w r3, [r3, #-164]
8001d4a: 4619 mov r1, r3
8001d4c: 6878 ldr r0, [r7, #4]
8001d4e: f7ff f865 bl 8000e1c <__aeabi_fcmpgt>
8001d52: 4603 mov r3, r0
8001d54: 2b00 cmp r3, #0
8001d56: d1e7 bne.n 8001d28 <ADSinterpolate_ph+0x6c>
}
float x0 = lut_matrix_buffer_ph[0][i];
8001d58: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001d5c: 009b lsls r3, r3, #2
8001d5e: 33b0 adds r3, #176 @ 0xb0
8001d60: 443b add r3, r7
8001d62: f853 3ca4 ldr.w r3, [r3, #-164]
8001d66: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
float x1 = lut_matrix_buffer_ph[0][i+1];
8001d6a: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001d6e: 3301 adds r3, #1
8001d70: 009b lsls r3, r3, #2
8001d72: 33b0 adds r3, #176 @ 0xb0
8001d74: 443b add r3, r7
8001d76: f853 3ca4 ldr.w r3, [r3, #-164]
8001d7a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
float y0 = lut_matrix_buffer_ph[row_index][i];
8001d7e: 78fa ldrb r2, [r7, #3]
8001d80: f897 10af ldrb.w r1, [r7, #175] @ 0xaf
8001d84: 4613 mov r3, r2
8001d86: 005b lsls r3, r3, #1
8001d88: 4413 add r3, r2
8001d8a: 009b lsls r3, r3, #2
8001d8c: 440b add r3, r1
8001d8e: 009b lsls r3, r3, #2
8001d90: 33b0 adds r3, #176 @ 0xb0
8001d92: 443b add r3, r7
8001d94: f853 3ca4 ldr.w r3, [r3, #-164]
8001d98: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
float y1 = lut_matrix_buffer_ph[row_index][i+1];
8001d9c: 78fa ldrb r2, [r7, #3]
8001d9e: f897 30af ldrb.w r3, [r7, #175] @ 0xaf
8001da2: 1c59 adds r1, r3, #1
8001da4: 4613 mov r3, r2
8001da6: 005b lsls r3, r3, #1
8001da8: 4413 add r3, r2
8001daa: 009b lsls r3, r3, #2
8001dac: 440b add r3, r1
8001dae: 009b lsls r3, r3, #2
8001db0: 33b0 adds r3, #176 @ 0xb0
8001db2: 443b add r3, r7
8001db4: f853 3ca4 ldr.w r3, [r3, #-164]
8001db8: f8c7 309c str.w r3, [r7, #156] @ 0x9c
/* Linear Interpolation: y = y0 + (x - x0) * ((y1 - y_0) / (x1 - x0)) */
return y0 + (temp_target - x0) * ((y1 - y0) / (x1 - x0));
8001dbc: f8d7 10a8 ldr.w r1, [r7, #168] @ 0xa8
8001dc0: 6878 ldr r0, [r7, #4]
8001dc2: f7fe fd65 bl 8000890 <__aeabi_fsub>
8001dc6: 4603 mov r3, r0
8001dc8: 461c mov r4, r3
8001dca: f8d7 10a0 ldr.w r1, [r7, #160] @ 0xa0
8001dce: f8d7 009c ldr.w r0, [r7, #156] @ 0x9c
8001dd2: f7fe fd5d bl 8000890 <__aeabi_fsub>
8001dd6: 4603 mov r3, r0
8001dd8: 461d mov r5, r3
8001dda: f8d7 10a8 ldr.w r1, [r7, #168] @ 0xa8
8001dde: f8d7 00a4 ldr.w r0, [r7, #164] @ 0xa4
8001de2: f7fe fd55 bl 8000890 <__aeabi_fsub>
8001de6: 4603 mov r3, r0
8001de8: 4619 mov r1, r3
8001dea: 4628 mov r0, r5
8001dec: f7fe ff0e bl 8000c0c <__aeabi_fdiv>
8001df0: 4603 mov r3, r0
8001df2: 4619 mov r1, r3
8001df4: 4620 mov r0, r4
8001df6: f7fe fe55 bl 8000aa4 <__aeabi_fmul>
8001dfa: 4603 mov r3, r0
8001dfc: f8d7 10a0 ldr.w r1, [r7, #160] @ 0xa0
8001e00: 4618 mov r0, r3
8001e02: f7fe fd47 bl 8000894 <__addsf3>
8001e06: 4603 mov r3, r0
}
8001e08: 4618 mov r0, r3
8001e0a: 37b0 adds r7, #176 @ 0xb0
8001e0c: 46bd mov sp, r7
8001e0e: bdb0 pop {r4, r5, r7, pc}
8001e10: 08006704 .word 0x08006704
08001e14 <ADSRound_Float_Precision>:
* @param valor O valor float original.
* @param casas_decimais Quantidade de casas que devem permanecer após a vírgula.
* @return float O valor com as casas decimais excedentes removidas.
*/
float ADSRound_Float_Precision(float value, uint8_t number_of_decimals)
{
8001e14: b580 push {r7, lr}
8001e16: b084 sub sp, #16
8001e18: af00 add r7, sp, #0
8001e1a: 6078 str r0, [r7, #4]
8001e1c: 460b mov r3, r1
8001e1e: 70fb strb r3, [r7, #3]
float multiply = 1.0f;
8001e20: f04f 537e mov.w r3, #1065353216 @ 0x3f800000
8001e24: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
8001e26: 2300 movs r3, #0
8001e28: 72fb strb r3, [r7, #11]
8001e2a: e008 b.n 8001e3e <ADSRound_Float_Precision+0x2a>
multiply *= 10.0f;
8001e2c: 490f ldr r1, [pc, #60] @ (8001e6c <ADSRound_Float_Precision+0x58>)
8001e2e: 68f8 ldr r0, [r7, #12]
8001e30: f7fe fe38 bl 8000aa4 <__aeabi_fmul>
8001e34: 4603 mov r3, r0
8001e36: 60fb str r3, [r7, #12]
for (uint8_t i = 0; i < number_of_decimals; i++)
8001e38: 7afb ldrb r3, [r7, #11]
8001e3a: 3301 adds r3, #1
8001e3c: 72fb strb r3, [r7, #11]
8001e3e: 7afa ldrb r2, [r7, #11]
8001e40: 78fb ldrb r3, [r7, #3]
8001e42: 429a cmp r2, r3
8001e44: d3f2 bcc.n 8001e2c <ADSRound_Float_Precision+0x18>
return roundf(value * multiply) / multiply;
8001e46: 68f9 ldr r1, [r7, #12]
8001e48: 6878 ldr r0, [r7, #4]
8001e4a: f7fe fe2b bl 8000aa4 <__aeabi_fmul>
8001e4e: 4603 mov r3, r0
8001e50: 4618 mov r0, r3
8001e52: f004 fbf7 bl 8006644 <roundf>
8001e56: 4603 mov r3, r0
8001e58: 68f9 ldr r1, [r7, #12]
8001e5a: 4618 mov r0, r3
8001e5c: f7fe fed6 bl 8000c0c <__aeabi_fdiv>
8001e60: 4603 mov r3, r0
}
8001e62: 4618 mov r0, r3
8001e64: 3710 adds r7, #16
8001e66: 46bd mov sp, r7
8001e68: bd80 pop {r7, pc}
8001e6a: bf00 nop
8001e6c: 41200000 .word 0x41200000
08001e70 <digital_outputs_init>:
* @brief Initializes the GPIO hardware and sets initial states.
* @note This function replaces the handle-based init.
* @retval None
*/
void digital_outputs_init(void)
{
8001e70: b580 push {r7, lr}
8001e72: b086 sub sp, #24
8001e74: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001e76: 1d3b adds r3, r7, #4
8001e78: 2200 movs r2, #0
8001e7a: 601a str r2, [r3, #0]
8001e7c: 605a str r2, [r3, #4]
8001e7e: 609a str r2, [r3, #8]
8001e80: 60da str r2, [r3, #12]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001e82: 2300 movs r3, #0
8001e84: 617b str r3, [r7, #20]
8001e86: e029 b.n 8001edc <digital_outputs_init+0x6c>
GPIO_InitStruct.Pin = output_pins[i].pin;
8001e88: 4a18 ldr r2, [pc, #96] @ (8001eec <digital_outputs_init+0x7c>)
8001e8a: 697b ldr r3, [r7, #20]
8001e8c: 00db lsls r3, r3, #3
8001e8e: 4413 add r3, r2
8001e90: 889b ldrh r3, [r3, #4]
8001e92: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain
8001e94: 2311 movs r3, #17
8001e96: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e98: 2300 movs r3, #0
8001e9a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001e9c: 2302 movs r3, #2
8001e9e: 613b str r3, [r7, #16]
HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
8001ea0: 4a12 ldr r2, [pc, #72] @ (8001eec <digital_outputs_init+0x7c>)
8001ea2: 697b ldr r3, [r7, #20]
8001ea4: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8001ea8: 1d3a adds r2, r7, #4
8001eaa: 4611 mov r1, r2
8001eac: 4618 mov r0, r3
8001eae: f001 fe1b bl 8003ae8 <HAL_GPIO_Init>
// Force initial state to LOW (Reset)
HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET);
8001eb2: 4a0e ldr r2, [pc, #56] @ (8001eec <digital_outputs_init+0x7c>)
8001eb4: 697b ldr r3, [r7, #20]
8001eb6: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8001eba: 4a0c ldr r2, [pc, #48] @ (8001eec <digital_outputs_init+0x7c>)
8001ebc: 697b ldr r3, [r7, #20]
8001ebe: 00db lsls r3, r3, #3
8001ec0: 4413 add r3, r2
8001ec2: 889b ldrh r3, [r3, #4]
8001ec4: 2200 movs r2, #0
8001ec6: 4619 mov r1, r3
8001ec8: f001 ffa9 bl 8003e1e <HAL_GPIO_WritePin>
pin_states[i] = 0;
8001ecc: 4a08 ldr r2, [pc, #32] @ (8001ef0 <digital_outputs_init+0x80>)
8001ece: 697b ldr r3, [r7, #20]
8001ed0: 4413 add r3, r2
8001ed2: 2200 movs r2, #0
8001ed4: 701a strb r2, [r3, #0]
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
8001ed6: 697b ldr r3, [r7, #20]
8001ed8: 3301 adds r3, #1
8001eda: 617b str r3, [r7, #20]
8001edc: 697b ldr r3, [r7, #20]
8001ede: 2b07 cmp r3, #7
8001ee0: ddd2 ble.n 8001e88 <digital_outputs_init+0x18>
}
}
8001ee2: bf00 nop
8001ee4: bf00 nop
8001ee6: 3718 adds r7, #24
8001ee8: 46bd mov sp, r7
8001eea: bd80 pop {r7, pc}
8001eec: 080067a4 .word 0x080067a4
8001ef0: 2000021c .word 0x2000021c
08001ef4 <Flash_Save_Page>:
* @return HAL_OK em caso de sucesso.
*/
FlashPage_t flash_data;
HAL_StatusTypeDef Flash_Save_Page(FlashPage_t *pPage) {
8001ef4: b5b0 push {r4, r5, r7, lr}
8001ef6: b08c sub sp, #48 @ 0x30
8001ef8: af00 add r7, sp, #0
8001efa: 6078 str r0, [r7, #4]
if (pPage == NULL) return HAL_ERROR;
8001efc: 687b ldr r3, [r7, #4]
8001efe: 2b00 cmp r3, #0
8001f00: d101 bne.n 8001f06 <Flash_Save_Page+0x12>
8001f02: 2301 movs r3, #1
8001f04: e04a b.n 8001f9c <Flash_Save_Page+0xa8>
HAL_StatusTypeDef status = HAL_OK;
8001f06: 2300 movs r3, #0
8001f08: f887 302f strb.w r3, [r7, #47] @ 0x2f
HAL_FLASH_Unlock();
8001f0c: f001 fc5c bl 80037c8 <HAL_FLASH_Unlock>
// 1. Apagar a página inteira (limpa os 1024 bytes)
FLASH_EraseInitTypeDef EraseInitStruct;
uint32_t PageError = 0;
8001f10: 2300 movs r3, #0
8001f12: 60bb str r3, [r7, #8]
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
8001f14: 2300 movs r3, #0
8001f16: 60fb str r3, [r7, #12]
EraseInitStruct.PageAddress = FLASH_PAGE_ADDR;
8001f18: 4b22 ldr r3, [pc, #136] @ (8001fa4 <Flash_Save_Page+0xb0>)
8001f1a: 617b str r3, [r7, #20]
EraseInitStruct.NbPages = 1;
8001f1c: 2301 movs r3, #1
8001f1e: 61bb str r3, [r7, #24]
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) {
8001f20: f107 0208 add.w r2, r7, #8
8001f24: f107 030c add.w r3, r7, #12
8001f28: 4611 mov r1, r2
8001f2a: 4618 mov r0, r3
8001f2c: f001 fd34 bl 8003998 <HAL_FLASHEx_Erase>
8001f30: 4603 mov r3, r0
8001f32: 2b00 cmp r3, #0
8001f34: d003 beq.n 8001f3e <Flash_Save_Page+0x4a>
status = HAL_ERROR;
8001f36: 2301 movs r3, #1
8001f38: f887 302f strb.w r3, [r7, #47] @ 0x2f
goto Exit;
8001f3c: e02a b.n 8001f94 <Flash_Save_Page+0xa0>
// 2. Gravar o bloco de 1KB
// Como a estrutura é exatamente 1KB e alinhada, podemos tratar como um array de uint32_t.
// O STM32F1 grava preferencialmente em DoubleWord (64-bit), mas HalfWord (16-bit)
// funciona de forma segura para qualquer tamanho múltiplo de 2.
uint32_t *pSrc = (uint32_t *)pPage;
8001f3e: 687b ldr r3, [r7, #4]
8001f40: 627b str r3, [r7, #36] @ 0x24
uint32_t *pDest = (uint32_t *)FLASH_PAGE_ADDR;
8001f42: 4b18 ldr r3, [pc, #96] @ (8001fa4 <Flash_Save_Page+0xb0>)
8001f44: 623b str r3, [r7, #32]
uint32_t iterations = FLASH_PAGE_SIZE / sizeof(uint32_t); // 1024 / 4 = 256 iterações
8001f46: f44f 7380 mov.w r3, #256 @ 0x100
8001f4a: 61fb str r3, [r7, #28]
for (uint32_t i = 0; i < iterations; i++) {
8001f4c: 2300 movs r3, #0
8001f4e: 62bb str r3, [r7, #40] @ 0x28
8001f50: e01b b.n 8001f8a <Flash_Save_Page+0x96>
// Usamos o modo de gravação de 32-bit (Word) se disponível,
// ou simulamos com duas gravações de 16-bit para máxima compatuidade no F1.
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, (uint32_t)&pDest[i], pSrc[i]) != HAL_OK) {
8001f52: 6abb ldr r3, [r7, #40] @ 0x28
8001f54: 009b lsls r3, r3, #2
8001f56: 6a3a ldr r2, [r7, #32]
8001f58: 4413 add r3, r2
8001f5a: 4619 mov r1, r3
8001f5c: 6abb ldr r3, [r7, #40] @ 0x28
8001f5e: 009b lsls r3, r3, #2
8001f60: 6a7a ldr r2, [r7, #36] @ 0x24
8001f62: 4413 add r3, r2
8001f64: 681b ldr r3, [r3, #0]
8001f66: 2200 movs r2, #0
8001f68: 461c mov r4, r3
8001f6a: 4615 mov r5, r2
8001f6c: 4622 mov r2, r4
8001f6e: 462b mov r3, r5
8001f70: 2002 movs r0, #2
8001f72: f001 fbb9 bl 80036e8 <HAL_FLASH_Program>
8001f76: 4603 mov r3, r0
8001f78: 2b00 cmp r3, #0
8001f7a: d003 beq.n 8001f84 <Flash_Save_Page+0x90>
status = HAL_ERROR;
8001f7c: 2301 movs r3, #1
8001f7e: f887 302f strb.w r3, [r7, #47] @ 0x2f
break;
8001f82: e007 b.n 8001f94 <Flash_Save_Page+0xa0>
for (uint32_t i = 0; i < iterations; i++) {
8001f84: 6abb ldr r3, [r7, #40] @ 0x28
8001f86: 3301 adds r3, #1
8001f88: 62bb str r3, [r7, #40] @ 0x28
8001f8a: 6aba ldr r2, [r7, #40] @ 0x28
8001f8c: 69fb ldr r3, [r7, #28]
8001f8e: 429a cmp r2, r3
8001f90: d3df bcc.n 8001f52 <Flash_Save_Page+0x5e>
}
}
Exit:
8001f92: bf00 nop
HAL_FLASH_Lock();
8001f94: f001 fc3e bl 8003814 <HAL_FLASH_Lock>
return status;
8001f98: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
}
8001f9c: 4618 mov r0, r3
8001f9e: 3730 adds r7, #48 @ 0x30
8001fa0: 46bd mov sp, r7
8001fa2: bdb0 pop {r4, r5, r7, pc}
8001fa4: 0800fc00 .word 0x0800fc00
08001fa8 <Flash_Load_Page>:
/**
* @brief Lê a página da Flash para a RAM.
*/
HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest) {
8001fa8: b580 push {r7, lr}
8001faa: b082 sub sp, #8
8001fac: af00 add r7, sp, #0
8001fae: 6078 str r0, [r7, #4]
if (pDest == NULL) return HAL_ERROR;
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 2b00 cmp r3, #0
8001fb4: d101 bne.n 8001fba <Flash_Load_Page+0x12>
8001fb6: 2301 movs r3, #1
8001fb8: e00d b.n 8001fd6 <Flash_Load_Page+0x2e>
// Leitura direta por memcpy (A Flash é mapeada no espaço de endereçamento comum)
memcpy(pDest, (void *)FLASH_PAGE_ADDR, FLASH_PAGE_SIZE);
8001fba: f44f 6280 mov.w r2, #1024 @ 0x400
8001fbe: 4908 ldr r1, [pc, #32] @ (8001fe0 <Flash_Load_Page+0x38>)
8001fc0: 6878 ldr r0, [r7, #4]
8001fc2: f004 faa1 bl 8006508 <memcpy>
// Validação da integridade através do Magic Number
if (pDest->magic_number != 0xDEADBEEF) {
8001fc6: 687b ldr r3, [r7, #4]
8001fc8: 681b ldr r3, [r3, #0]
8001fca: 4a06 ldr r2, [pc, #24] @ (8001fe4 <Flash_Load_Page+0x3c>)
8001fcc: 4293 cmp r3, r2
8001fce: d001 beq.n 8001fd4 <Flash_Load_Page+0x2c>
return HAL_ERROR;
8001fd0: 2301 movs r3, #1
8001fd2: e000 b.n 8001fd6 <Flash_Load_Page+0x2e>
}
return HAL_OK;
8001fd4: 2300 movs r3, #0
}
8001fd6: 4618 mov r0, r3
8001fd8: 3708 adds r7, #8
8001fda: 46bd mov sp, r7
8001fdc: bd80 pop {r7, pc}
8001fde: bf00 nop
8001fe0: 0800fc00 .word 0x0800fc00
8001fe4: deadbeef .word 0xdeadbeef
08001fe8 <MX_GPIO_Init>:
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
8001fe8: b580 push {r7, lr}
8001fea: b088 sub sp, #32
8001fec: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001fee: f107 0310 add.w r3, r7, #16
8001ff2: 2200 movs r2, #0
8001ff4: 601a str r2, [r3, #0]
8001ff6: 605a str r2, [r3, #4]
8001ff8: 609a str r2, [r3, #8]
8001ffa: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ffc: 4b46 ldr r3, [pc, #280] @ (8002118 <MX_GPIO_Init+0x130>)
8001ffe: 699b ldr r3, [r3, #24]
8002000: 4a45 ldr r2, [pc, #276] @ (8002118 <MX_GPIO_Init+0x130>)
8002002: f043 0310 orr.w r3, r3, #16
8002006: 6193 str r3, [r2, #24]
8002008: 4b43 ldr r3, [pc, #268] @ (8002118 <MX_GPIO_Init+0x130>)
800200a: 699b ldr r3, [r3, #24]
800200c: f003 0310 and.w r3, r3, #16
8002010: 60fb str r3, [r7, #12]
8002012: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8002014: 4b40 ldr r3, [pc, #256] @ (8002118 <MX_GPIO_Init+0x130>)
8002016: 699b ldr r3, [r3, #24]
8002018: 4a3f ldr r2, [pc, #252] @ (8002118 <MX_GPIO_Init+0x130>)
800201a: f043 0320 orr.w r3, r3, #32
800201e: 6193 str r3, [r2, #24]
8002020: 4b3d ldr r3, [pc, #244] @ (8002118 <MX_GPIO_Init+0x130>)
8002022: 699b ldr r3, [r3, #24]
8002024: f003 0320 and.w r3, r3, #32
8002028: 60bb str r3, [r7, #8]
800202a: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800202c: 4b3a ldr r3, [pc, #232] @ (8002118 <MX_GPIO_Init+0x130>)
800202e: 699b ldr r3, [r3, #24]
8002030: 4a39 ldr r2, [pc, #228] @ (8002118 <MX_GPIO_Init+0x130>)
8002032: f043 0304 orr.w r3, r3, #4
8002036: 6193 str r3, [r2, #24]
8002038: 4b37 ldr r3, [pc, #220] @ (8002118 <MX_GPIO_Init+0x130>)
800203a: 699b ldr r3, [r3, #24]
800203c: f003 0304 and.w r3, r3, #4
8002040: 607b str r3, [r7, #4]
8002042: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002044: 4b34 ldr r3, [pc, #208] @ (8002118 <MX_GPIO_Init+0x130>)
8002046: 699b ldr r3, [r3, #24]
8002048: 4a33 ldr r2, [pc, #204] @ (8002118 <MX_GPIO_Init+0x130>)
800204a: f043 0308 orr.w r3, r3, #8
800204e: 6193 str r3, [r2, #24]
8002050: 4b31 ldr r3, [pc, #196] @ (8002118 <MX_GPIO_Init+0x130>)
8002052: 699b ldr r3, [r3, #24]
8002054: f003 0308 and.w r3, r3, #8
8002058: 603b str r3, [r7, #0]
800205a: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
800205c: 2200 movs r2, #0
800205e: f44f 4160 mov.w r1, #57344 @ 0xe000
8002062: 482e ldr r0, [pc, #184] @ (800211c <MX_GPIO_Init+0x134>)
8002064: f001 fedb bl 8003e1e <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
8002068: 2200 movs r2, #0
800206a: f240 3137 movw r1, #823 @ 0x337
800206e: 482c ldr r0, [pc, #176] @ (8002120 <MX_GPIO_Init+0x138>)
8002070: f001 fed5 bl 8003e1e <HAL_GPIO_WritePin>
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
8002074: 2200 movs r2, #0
8002076: f44f 5180 mov.w r1, #4096 @ 0x1000
800207a: 482a ldr r0, [pc, #168] @ (8002124 <MX_GPIO_Init+0x13c>)
800207c: f001 fecf bl 8003e1e <HAL_GPIO_WritePin>
/*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
8002080: f44f 4360 mov.w r3, #57344 @ 0xe000
8002084: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8002086: 2311 movs r3, #17
8002088: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800208a: 2300 movs r3, #0
800208c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800208e: 2302 movs r3, #2
8002090: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8002092: f107 0310 add.w r3, r7, #16
8002096: 4619 mov r1, r3
8002098: 4820 ldr r0, [pc, #128] @ (800211c <MX_GPIO_Init+0x134>)
800209a: f001 fd25 bl 8003ae8 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
PG_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
800209e: f648 13fc movw r3, #35324 @ 0x89fc
80020a2: 613b str r3, [r7, #16]
|SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
|PG_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80020a4: 2300 movs r3, #0
80020a6: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80020a8: 2301 movs r3, #1
80020aa: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80020ac: f107 0310 add.w r3, r7, #16
80020b0: 4619 mov r1, r3
80020b2: 481c ldr r0, [pc, #112] @ (8002124 <MX_GPIO_Init+0x13c>)
80020b4: f001 fd18 bl 8003ae8 <HAL_GPIO_Init>
/*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
80020b8: f240 3337 movw r3, #823 @ 0x337
80020bc: 613b str r3, [r7, #16]
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
80020be: 2311 movs r3, #17
80020c0: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80020c2: 2300 movs r3, #0
80020c4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80020c6: 2302 movs r3, #2
80020c8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80020ca: f107 0310 add.w r3, r7, #16
80020ce: 4619 mov r1, r3
80020d0: 4813 ldr r0, [pc, #76] @ (8002120 <MX_GPIO_Init+0x138>)
80020d2: f001 fd09 bl 8003ae8 <HAL_GPIO_Init>
/*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin
Calib_PH_Pin */
GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin
80020d6: f24f 0308 movw r3, #61448 @ 0xf008
80020da: 613b str r3, [r7, #16]
|Calib_PH_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80020dc: 2300 movs r3, #0
80020de: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80020e0: 2301 movs r3, #1
80020e2: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80020e4: f107 0310 add.w r3, r7, #16
80020e8: 4619 mov r1, r3
80020ea: 480d ldr r0, [pc, #52] @ (8002120 <MX_GPIO_Init+0x138>)
80020ec: f001 fcfc bl 8003ae8 <HAL_GPIO_Init>
/*Configure GPIO pin : TX_EN_RS485_Pin */
GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
80020f0: f44f 5380 mov.w r3, #4096 @ 0x1000
80020f4: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80020f6: 2301 movs r3, #1
80020f8: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80020fa: 2300 movs r3, #0
80020fc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80020fe: 2302 movs r3, #2
8002100: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
8002102: f107 0310 add.w r3, r7, #16
8002106: 4619 mov r1, r3
8002108: 4806 ldr r0, [pc, #24] @ (8002124 <MX_GPIO_Init+0x13c>)
800210a: f001 fced bl 8003ae8 <HAL_GPIO_Init>
}
800210e: bf00 nop
8002110: 3720 adds r7, #32
8002112: 46bd mov sp, r7
8002114: bd80 pop {r7, pc}
8002116: bf00 nop
8002118: 40021000 .word 0x40021000
800211c: 40011000 .word 0x40011000
8002120: 40010c00 .word 0x40010c00
8002124: 40010800 .word 0x40010800
08002128 <MX_I2C1_Init>:
I2C_HandleTypeDef hi2c1;
I2C_HandleTypeDef hi2c2;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
8002128: b580 push {r7, lr}
800212a: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
800212c: 4b12 ldr r3, [pc, #72] @ (8002178 <MX_I2C1_Init+0x50>)
800212e: 4a13 ldr r2, [pc, #76] @ (800217c <MX_I2C1_Init+0x54>)
8002130: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
8002132: 4b11 ldr r3, [pc, #68] @ (8002178 <MX_I2C1_Init+0x50>)
8002134: 4a12 ldr r2, [pc, #72] @ (8002180 <MX_I2C1_Init+0x58>)
8002136: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
8002138: 4b0f ldr r3, [pc, #60] @ (8002178 <MX_I2C1_Init+0x50>)
800213a: 2200 movs r2, #0
800213c: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
800213e: 4b0e ldr r3, [pc, #56] @ (8002178 <MX_I2C1_Init+0x50>)
8002140: 2200 movs r2, #0
8002142: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8002144: 4b0c ldr r3, [pc, #48] @ (8002178 <MX_I2C1_Init+0x50>)
8002146: f44f 4280 mov.w r2, #16384 @ 0x4000
800214a: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800214c: 4b0a ldr r3, [pc, #40] @ (8002178 <MX_I2C1_Init+0x50>)
800214e: 2200 movs r2, #0
8002150: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
8002152: 4b09 ldr r3, [pc, #36] @ (8002178 <MX_I2C1_Init+0x50>)
8002154: 2200 movs r2, #0
8002156: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8002158: 4b07 ldr r3, [pc, #28] @ (8002178 <MX_I2C1_Init+0x50>)
800215a: 2200 movs r2, #0
800215c: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800215e: 4b06 ldr r3, [pc, #24] @ (8002178 <MX_I2C1_Init+0x50>)
8002160: 2200 movs r2, #0
8002162: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8002164: 4804 ldr r0, [pc, #16] @ (8002178 <MX_I2C1_Init+0x50>)
8002166: f001 fe8b bl 8003e80 <HAL_I2C_Init>
800216a: 4603 mov r3, r0
800216c: 2b00 cmp r3, #0
800216e: d001 beq.n 8002174 <MX_I2C1_Init+0x4c>
{
Error_Handler();
8002170: f000 fc56 bl 8002a20 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8002174: bf00 nop
8002176: bd80 pop {r7, pc}
8002178: 20000624 .word 0x20000624
800217c: 40005400 .word 0x40005400
8002180: 000186a0 .word 0x000186a0
08002184 <MX_I2C2_Init>:
/* I2C2 init function */
void MX_I2C2_Init(void)
{
8002184: b580 push {r7, lr}
8002186: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
8002188: 4b12 ldr r3, [pc, #72] @ (80021d4 <MX_I2C2_Init+0x50>)
800218a: 4a13 ldr r2, [pc, #76] @ (80021d8 <MX_I2C2_Init+0x54>)
800218c: 601a str r2, [r3, #0]
hi2c2.Init.ClockSpeed = 100000;
800218e: 4b11 ldr r3, [pc, #68] @ (80021d4 <MX_I2C2_Init+0x50>)
8002190: 4a12 ldr r2, [pc, #72] @ (80021dc <MX_I2C2_Init+0x58>)
8002192: 605a str r2, [r3, #4]
hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
8002194: 4b0f ldr r3, [pc, #60] @ (80021d4 <MX_I2C2_Init+0x50>)
8002196: 2200 movs r2, #0
8002198: 609a str r2, [r3, #8]
hi2c2.Init.OwnAddress1 = 0;
800219a: 4b0e ldr r3, [pc, #56] @ (80021d4 <MX_I2C2_Init+0x50>)
800219c: 2200 movs r2, #0
800219e: 60da str r2, [r3, #12]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80021a0: 4b0c ldr r3, [pc, #48] @ (80021d4 <MX_I2C2_Init+0x50>)
80021a2: f44f 4280 mov.w r2, #16384 @ 0x4000
80021a6: 611a str r2, [r3, #16]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80021a8: 4b0a ldr r3, [pc, #40] @ (80021d4 <MX_I2C2_Init+0x50>)
80021aa: 2200 movs r2, #0
80021ac: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2 = 0;
80021ae: 4b09 ldr r3, [pc, #36] @ (80021d4 <MX_I2C2_Init+0x50>)
80021b0: 2200 movs r2, #0
80021b2: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80021b4: 4b07 ldr r3, [pc, #28] @ (80021d4 <MX_I2C2_Init+0x50>)
80021b6: 2200 movs r2, #0
80021b8: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80021ba: 4b06 ldr r3, [pc, #24] @ (80021d4 <MX_I2C2_Init+0x50>)
80021bc: 2200 movs r2, #0
80021be: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
80021c0: 4804 ldr r0, [pc, #16] @ (80021d4 <MX_I2C2_Init+0x50>)
80021c2: f001 fe5d bl 8003e80 <HAL_I2C_Init>
80021c6: 4603 mov r3, r0
80021c8: 2b00 cmp r3, #0
80021ca: d001 beq.n 80021d0 <MX_I2C2_Init+0x4c>
{
Error_Handler();
80021cc: f000 fc28 bl 8002a20 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
80021d0: bf00 nop
80021d2: bd80 pop {r7, pc}
80021d4: 20000678 .word 0x20000678
80021d8: 40005800 .word 0x40005800
80021dc: 000186a0 .word 0x000186a0
080021e0 <HAL_I2C_MspInit>:
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
80021e0: b580 push {r7, lr}
80021e2: b08a sub sp, #40 @ 0x28
80021e4: af00 add r7, sp, #0
80021e6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80021e8: f107 0318 add.w r3, r7, #24
80021ec: 2200 movs r2, #0
80021ee: 601a str r2, [r3, #0]
80021f0: 605a str r2, [r3, #4]
80021f2: 609a str r2, [r3, #8]
80021f4: 60da str r2, [r3, #12]
if(i2cHandle->Instance==I2C1)
80021f6: 687b ldr r3, [r7, #4]
80021f8: 681b ldr r3, [r3, #0]
80021fa: 4a2b ldr r2, [pc, #172] @ (80022a8 <HAL_I2C_MspInit+0xc8>)
80021fc: 4293 cmp r3, r2
80021fe: d124 bne.n 800224a <HAL_I2C_MspInit+0x6a>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8002200: 4b2a ldr r3, [pc, #168] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002202: 699b ldr r3, [r3, #24]
8002204: 4a29 ldr r2, [pc, #164] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002206: f043 0308 orr.w r3, r3, #8
800220a: 6193 str r3, [r2, #24]
800220c: 4b27 ldr r3, [pc, #156] @ (80022ac <HAL_I2C_MspInit+0xcc>)
800220e: 699b ldr r3, [r3, #24]
8002210: f003 0308 and.w r3, r3, #8
8002214: 617b str r3, [r7, #20]
8002216: 697b ldr r3, [r7, #20]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
8002218: 23c0 movs r3, #192 @ 0xc0
800221a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800221c: 2312 movs r3, #18
800221e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002220: 2302 movs r3, #2
8002222: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002224: f107 0318 add.w r3, r7, #24
8002228: 4619 mov r1, r3
800222a: 4821 ldr r0, [pc, #132] @ (80022b0 <HAL_I2C_MspInit+0xd0>)
800222c: f001 fc5c bl 8003ae8 <HAL_GPIO_Init>
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8002230: 4b1e ldr r3, [pc, #120] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002232: 69db ldr r3, [r3, #28]
8002234: 4a1d ldr r2, [pc, #116] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002236: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
800223a: 61d3 str r3, [r2, #28]
800223c: 4b1b ldr r3, [pc, #108] @ (80022ac <HAL_I2C_MspInit+0xcc>)
800223e: 69db ldr r3, [r3, #28]
8002240: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002244: 613b str r3, [r7, #16]
8002246: 693b ldr r3, [r7, #16]
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
}
8002248: e029 b.n 800229e <HAL_I2C_MspInit+0xbe>
else if(i2cHandle->Instance==I2C2)
800224a: 687b ldr r3, [r7, #4]
800224c: 681b ldr r3, [r3, #0]
800224e: 4a19 ldr r2, [pc, #100] @ (80022b4 <HAL_I2C_MspInit+0xd4>)
8002250: 4293 cmp r3, r2
8002252: d124 bne.n 800229e <HAL_I2C_MspInit+0xbe>
__HAL_RCC_GPIOB_CLK_ENABLE();
8002254: 4b15 ldr r3, [pc, #84] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002256: 699b ldr r3, [r3, #24]
8002258: 4a14 ldr r2, [pc, #80] @ (80022ac <HAL_I2C_MspInit+0xcc>)
800225a: f043 0308 orr.w r3, r3, #8
800225e: 6193 str r3, [r2, #24]
8002260: 4b12 ldr r3, [pc, #72] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002262: 699b ldr r3, [r3, #24]
8002264: f003 0308 and.w r3, r3, #8
8002268: 60fb str r3, [r7, #12]
800226a: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
800226c: f44f 6340 mov.w r3, #3072 @ 0xc00
8002270: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8002272: 2312 movs r3, #18
8002274: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002276: 2302 movs r3, #2
8002278: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800227a: f107 0318 add.w r3, r7, #24
800227e: 4619 mov r1, r3
8002280: 480b ldr r0, [pc, #44] @ (80022b0 <HAL_I2C_MspInit+0xd0>)
8002282: f001 fc31 bl 8003ae8 <HAL_GPIO_Init>
__HAL_RCC_I2C2_CLK_ENABLE();
8002286: 4b09 ldr r3, [pc, #36] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002288: 69db ldr r3, [r3, #28]
800228a: 4a08 ldr r2, [pc, #32] @ (80022ac <HAL_I2C_MspInit+0xcc>)
800228c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002290: 61d3 str r3, [r2, #28]
8002292: 4b06 ldr r3, [pc, #24] @ (80022ac <HAL_I2C_MspInit+0xcc>)
8002294: 69db ldr r3, [r3, #28]
8002296: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800229a: 60bb str r3, [r7, #8]
800229c: 68bb ldr r3, [r7, #8]
}
800229e: bf00 nop
80022a0: 3728 adds r7, #40 @ 0x28
80022a2: 46bd mov sp, r7
80022a4: bd80 pop {r7, pc}
80022a6: bf00 nop
80022a8: 40005400 .word 0x40005400
80022ac: 40021000 .word 0x40021000
80022b0: 40010c00 .word 0x40010c00
80022b4: 40005800 .word 0x40005800
080022b8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80022b8: b590 push {r4, r7, lr}
80022ba: b093 sub sp, #76 @ 0x4c
80022bc: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
HAL_StatusTypeDef status0,status1;
// Variables to store previous LED states
uint8_t previous_green_state = 0;
80022be: 2300 movs r3, #0
80022c0: f887 3047 strb.w r3, [r7, #71] @ 0x47
uint8_t previous_red_state = 0;
80022c4: 2300 movs r3, #0
80022c6: f887 3046 strb.w r3, [r7, #70] @ 0x46
// Variables for timing
uint32_t previous_millis_green = 0;
80022ca: 2300 movs r3, #0
80022cc: 643b str r3, [r7, #64] @ 0x40
uint32_t previous_millis_red = 0;
80022ce: 2300 movs r3, #0
80022d0: 63fb str r3, [r7, #60] @ 0x3c
/*! Temporary variables */
uint8_t tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
80022d2: f107 030c add.w r3, r7, #12
80022d6: 2200 movs r2, #0
80022d8: 601a str r2, [r3, #0]
80022da: 605a str r2, [r3, #4]
80022dc: 811a strh r2, [r3, #8]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80022de: f000 fdab bl 8002e38 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80022e2: f000 fa39 bl 8002758 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80022e6: f7ff fe7f bl 8001fe8 <MX_GPIO_Init>
MX_ADC1_Init();
80022ea: f7ff fab5 bl 8001858 <MX_ADC1_Init>
MX_ADC2_Init();
80022ee: f7ff faf1 bl 80018d4 <MX_ADC2_Init>
MX_I2C1_Init();
80022f2: f7ff ff19 bl 8002128 <MX_I2C1_Init>
MX_I2C2_Init();
80022f6: f7ff ff45 bl 8002184 <MX_I2C2_Init>
MX_USART1_UART_Init();
80022fa: f000 fcf9 bl 8002cf0 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
Flash_Load_Page(&flash_data);
80022fe: 4854 ldr r0, [pc, #336] @ (8002450 <main+0x198>)
8002300: f7ff fe52 bl 8001fa8 <Flash_Load_Page>
HAL_TIM_Base_Start(&htim3);
HAL_ADCEx_Calibration_Start(&hadc1);
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2); // Internal Temperature conversion
*/
digital_outputs_init();
8002304: f7ff fdb4 bl 8001e70 <digital_outputs_init>
// Initialize RS-485 driver
rs485_init();
8002308: f000 fb9c bl 8002a44 <rs485_init>
ADS1015(&i2c, &hi2c1, ADS_ADDR_GND);
800230c: 2248 movs r2, #72 @ 0x48
800230e: 4951 ldr r1, [pc, #324] @ (8002454 <main+0x19c>)
8002310: 4851 ldr r0, [pc, #324] @ (8002458 <main+0x1a0>)
8002312: f7ff fbce bl 8001ab2 <ADS1015>
ADSsetGain(&i2c, GAIN_FOUR);
8002316: f44f 61c0 mov.w r1, #1536 @ 0x600
800231a: 484f ldr r0, [pc, #316] @ (8002458 <main+0x1a0>)
800231c: f7ff fbe7 bl 8001aee <ADSsetGain>
ADG715_ResetChannels();
8002320: f7ff fa72 bl 8001808 <ADG715_ResetChannels>
// Start CE and RTD Measurement
AD5934_Init();
8002324: f7fe fe3a bl 8000f9c <AD5934_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
for(i=0;i<AD5934_TEMP_AVERAGES;i++) // Loop to get stability and get averages
8002328: 2300 movs r3, #0
800232a: f887 3033 strb.w r3, [r7, #51] @ 0x33
800232e: e013 b.n 8002358 <main+0xa0>
{
refResistance = AD5934_Get_Ref_Resistance(); // On Board Resistor
8002330: f7fe fe90 bl 8001054 <AD5934_Get_Ref_Resistance>
8002334: 6378 str r0, [r7, #52] @ 0x34
temperature_RTD = AD5934_GetTemperature(refResistance); // Liquid Temperature is stored
8002336: 6b78 ldr r0, [r7, #52] @ 0x34
8002338: f7fe ff18 bl 800116c <AD5934_GetTemperature>
800233c: 63b8 str r0, [r7, #56] @ 0x38
admittance_EC = AD5934_GetImpedance(temperature_RTD);
800233e: 6bb8 ldr r0, [r7, #56] @ 0x38
8002340: f7ff f806 bl 8001350 <AD5934_GetImpedance>
8002344: 61f8 str r0, [r7, #28]
ph_compensated = ADSCalculate_ph_Compensated(temperature_RTD);
8002346: 6bb8 ldr r0, [r7, #56] @ 0x38
8002348: f7ff fc74 bl 8001c34 <ADSCalculate_ph_Compensated>
800234c: 61b8 str r0, [r7, #24]
for(i=0;i<AD5934_TEMP_AVERAGES;i++) // Loop to get stability and get averages
800234e: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8002352: 3301 adds r3, #1
8002354: f887 3033 strb.w r3, [r7, #51] @ 0x33
8002358: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
800235c: 2b0f cmp r3, #15
800235e: d9e7 bls.n 8002330 <main+0x78>
}
if(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET) // When PB3 (with internal pull up) in the Prog Header is set to GND
8002360: 2108 movs r1, #8
8002362: 483e ldr r0, [pc, #248] @ (800245c <main+0x1a4>)
8002364: f001 fd44 bl 8003df0 <HAL_GPIO_ReadPin>
8002368: 4603 mov r3, r0
800236a: 2b00 cmp r3, #0
800236c: f040 80dd bne.w 800252a <main+0x272>
{
main_state = STATE_PH4_DRY_EC_CALIBRATION;
8002370: 4b3b ldr r3, [pc, #236] @ (8002460 <main+0x1a8>)
8002372: 2202 movs r2, #2
8002374: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
8002376: 2201 movs r2, #1
8002378: 2110 movs r1, #16
800237a: 4838 ldr r0, [pc, #224] @ (800245c <main+0x1a4>)
800237c: f001 fd4f bl 8003e1e <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
8002380: 2200 movs r2, #0
8002382: 2120 movs r1, #32
8002384: 4835 ldr r0, [pc, #212] @ (800245c <main+0x1a4>)
8002386: f001 fd4a bl 8003e1e <HAL_GPIO_WritePin>
for(i=0;i<(2*AD5934_TEMP_AVERAGES);i++) // Loop to get stability and get averages
800238a: 2300 movs r3, #0
800238c: f887 3033 strb.w r3, [r7, #51] @ 0x33
8002390: e033 b.n 80023fa <main+0x142>
{
flash_data.ph4_mV = ADSCalculate_ph_mV();
8002392: f7ff fbf9 bl 8001b88 <ADSCalculate_ph_mV>
8002396: 4603 mov r3, r0
8002398: 4a2d ldr r2, [pc, #180] @ (8002450 <main+0x198>)
800239a: 6053 str r3, [r2, #4]
temperature_RTD = AD5934_GetTemperature(refResistance); // Air Temperature is not used in the function
800239c: 6b78 ldr r0, [r7, #52] @ 0x34
800239e: f7fe fee5 bl 800116c <AD5934_GetTemperature>
80023a2: 63b8 str r0, [r7, #56] @ 0x38
flash_data.ec0_mag = AD5934_GetImpedance(temperature_RTD); // Dry Probe
80023a4: 6bb8 ldr r0, [r7, #56] @ 0x38
80023a6: f7fe ffd3 bl 8001350 <AD5934_GetImpedance>
80023aa: 4603 mov r3, r0
80023ac: 4a28 ldr r2, [pc, #160] @ (8002450 <main+0x198>)
80023ae: 61d3 str r3, [r2, #28]
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET)
80023b0: 2140 movs r1, #64 @ 0x40
80023b2: 482c ldr r0, [pc, #176] @ (8002464 <main+0x1ac>)
80023b4: f001 fd1c bl 8003df0 <HAL_GPIO_ReadPin>
80023b8: 4603 mov r3, r0
80023ba: 2b01 cmp r3, #1
80023bc: d104 bne.n 80023c8 <main+0x110>
flash_data.EC10mS_EC5mS_switch = AD5934_CH_EC_HIGH_GAIN; // 5mS/cm option
80023be: 4b24 ldr r3, [pc, #144] @ (8002450 <main+0x198>)
80023c0: 220e movs r2, #14
80023c2: f883 2025 strb.w r2, [r3, #37] @ 0x25
80023c6: e003 b.n 80023d0 <main+0x118>
else
flash_data.EC10mS_EC5mS_switch = AD5934_CH_EC_MID_GAIN; //10ms/cm option
80023c8: 4b21 ldr r3, [pc, #132] @ (8002450 <main+0x198>)
80023ca: 220d movs r2, #13
80023cc: f883 2025 strb.w r2, [r3, #37] @ 0x25
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET)
80023d0: 2180 movs r1, #128 @ 0x80
80023d2: 4824 ldr r0, [pc, #144] @ (8002464 <main+0x1ac>)
80023d4: f001 fd0c bl 8003df0 <HAL_GPIO_ReadPin>
80023d8: 4603 mov r3, r0
80023da: 2b01 cmp r3, #1
80023dc: d104 bne.n 80023e8 <main+0x130>
flash_data.PT100_PT1000_switch = AD5934_CH_RTD_LOW_GAIN; //PT100 option
80023de: 4b1c ldr r3, [pc, #112] @ (8002450 <main+0x198>)
80023e0: 2209 movs r2, #9
80023e2: f883 2024 strb.w r2, [r3, #36] @ 0x24
80023e6: e003 b.n 80023f0 <main+0x138>
else
flash_data.PT100_PT1000_switch = AD5934_CH_RTD_MID_GAIN; //PT1000 option
80023e8: 4b19 ldr r3, [pc, #100] @ (8002450 <main+0x198>)
80023ea: 220a movs r2, #10
80023ec: f883 2024 strb.w r2, [r3, #36] @ 0x24
for(i=0;i<(2*AD5934_TEMP_AVERAGES);i++) // Loop to get stability and get averages
80023f0: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80023f4: 3301 adds r3, #1
80023f6: f887 3033 strb.w r3, [r7, #51] @ 0x33
80023fa: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80023fe: 2b1f cmp r3, #31
8002400: d9c7 bls.n 8002392 <main+0xda>
}
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
8002402: 2200 movs r2, #0
8002404: 2110 movs r1, #16
8002406: 4815 ldr r0, [pc, #84] @ (800245c <main+0x1a4>)
8002408: f001 fd09 bl 8003e1e <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
800240c: 2201 movs r2, #1
800240e: 2120 movs r1, #32
8002410: 4812 ldr r0, [pc, #72] @ (800245c <main+0x1a4>)
8002412: f001 fd04 bl 8003e1e <HAL_GPIO_WritePin>
while(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET);
8002416: bf00 nop
8002418: 2108 movs r1, #8
800241a: 4810 ldr r0, [pc, #64] @ (800245c <main+0x1a4>)
800241c: f001 fce8 bl 8003df0 <HAL_GPIO_ReadPin>
8002420: 4603 mov r3, r0
8002422: 2b00 cmp r3, #0
8002424: d0f8 beq.n 8002418 <main+0x160>
HAL_Delay(500);
8002426: f44f 70fa mov.w r0, #500 @ 0x1f4
800242a: f000 fd67 bl 8002efc <HAL_Delay>
main_state = STATE_PH7_WET_EC_CALIBRATION;
800242e: 4b0c ldr r3, [pc, #48] @ (8002460 <main+0x1a8>)
8002430: 2203 movs r2, #3
8002432: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
8002434: 2201 movs r2, #1
8002436: 2110 movs r1, #16
8002438: 4808 ldr r0, [pc, #32] @ (800245c <main+0x1a4>)
800243a: f001 fcf0 bl 8003e1e <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
800243e: 2200 movs r2, #0
8002440: 2120 movs r1, #32
8002442: 4806 ldr r0, [pc, #24] @ (800245c <main+0x1a4>)
8002444: f001 fceb bl 8003e1e <HAL_GPIO_WritePin>
for(i=0;i<(2*AD5934_TEMP_AVERAGES);i++) // Loop to get stability and get averages
8002448: 2300 movs r3, #0
800244a: f887 3033 strb.w r3, [r7, #51] @ 0x33
800244e: e02d b.n 80024ac <main+0x1f4>
8002450: 20000224 .word 0x20000224
8002454: 20000624 .word 0x20000624
8002458: 200001cc .word 0x200001cc
800245c: 40010c00 .word 0x40010c00
8002460: 200006cc .word 0x200006cc
8002464: 40010800 .word 0x40010800
{
temperature_RTD = AD5934_GetTemperature(refResistance); // Liquid Temperature is stored
8002468: 6b78 ldr r0, [r7, #52] @ 0x34
800246a: f7fe fe7f bl 800116c <AD5934_GetTemperature>
800246e: 63b8 str r0, [r7, #56] @ 0x38
flash_data.ec_factor = AD5934_EC_Calibrate_Temperature(temperature_RTD);
8002470: 6bb8 ldr r0, [r7, #56] @ 0x38
8002472: f7ff f90f bl 8001694 <AD5934_EC_Calibrate_Temperature>
8002476: 4603 mov r3, r0
8002478: 4aac ldr r2, [pc, #688] @ (800272c <main+0x474>)
800247a: 6213 str r3, [r2, #32]
flash_data.ph7_mV = ADSCalculate_ph_mV();
800247c: f7ff fb84 bl 8001b88 <ADSCalculate_ph_mV>
8002480: 4603 mov r3, r0
8002482: 4aaa ldr r2, [pc, #680] @ (800272c <main+0x474>)
8002484: 6093 str r3, [r2, #8]
flash_data.ec1413_mag = AD5934_GetImpedance(temperature_RTD)*flash_data.ec_factor; // Get the magnitude of the reference liquid and compensate it to 25ºC
8002486: 6bb8 ldr r0, [r7, #56] @ 0x38
8002488: f7fe ff62 bl 8001350 <AD5934_GetImpedance>
800248c: 4602 mov r2, r0
800248e: 4ba7 ldr r3, [pc, #668] @ (800272c <main+0x474>)
8002490: 6a1b ldr r3, [r3, #32]
8002492: 4619 mov r1, r3
8002494: 4610 mov r0, r2
8002496: f7fe fb05 bl 8000aa4 <__aeabi_fmul>
800249a: 4603 mov r3, r0
800249c: 461a mov r2, r3
800249e: 4ba3 ldr r3, [pc, #652] @ (800272c <main+0x474>)
80024a0: 619a str r2, [r3, #24]
for(i=0;i<(2*AD5934_TEMP_AVERAGES);i++) // Loop to get stability and get averages
80024a2: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80024a6: 3301 adds r3, #1
80024a8: f887 3033 strb.w r3, [r7, #51] @ 0x33
80024ac: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80024b0: 2b1f cmp r3, #31
80024b2: d9d9 bls.n 8002468 <main+0x1b0>
}
ph7_interp = ADSinterpolate_ph(temperature_RTD,ADS1015_PH_7_BUFFER_ROW);
80024b4: 2102 movs r1, #2
80024b6: 6bb8 ldr r0, [r7, #56] @ 0x38
80024b8: f7ff fc00 bl 8001cbc <ADSinterpolate_ph>
80024bc: 62f8 str r0, [r7, #44] @ 0x2c
ph4_interp = ADSinterpolate_ph(temperature_RTD,ADS1015_PH_4_BUFFER_ROW);
80024be: 2101 movs r1, #1
80024c0: 6bb8 ldr r0, [r7, #56] @ 0x38
80024c2: f7ff fbfb bl 8001cbc <ADSinterpolate_ph>
80024c6: 62b8 str r0, [r7, #40] @ 0x28
flash_data.ph_temperature = temperature_RTD;
80024c8: 4a98 ldr r2, [pc, #608] @ (800272c <main+0x474>)
80024ca: 6bbb ldr r3, [r7, #56] @ 0x38
80024cc: 60d3 str r3, [r2, #12]
flash_data.ph_slope_mV = (flash_data.ph7_mV - flash_data.ph4_mV) / (ph7_interp - ph4_interp);
80024ce: 4b97 ldr r3, [pc, #604] @ (800272c <main+0x474>)
80024d0: 689b ldr r3, [r3, #8]
80024d2: 4a96 ldr r2, [pc, #600] @ (800272c <main+0x474>)
80024d4: 6852 ldr r2, [r2, #4]
80024d6: 4611 mov r1, r2
80024d8: 4618 mov r0, r3
80024da: f7fe f9d9 bl 8000890 <__aeabi_fsub>
80024de: 4603 mov r3, r0
80024e0: 461c mov r4, r3
80024e2: 6ab9 ldr r1, [r7, #40] @ 0x28
80024e4: 6af8 ldr r0, [r7, #44] @ 0x2c
80024e6: f7fe f9d3 bl 8000890 <__aeabi_fsub>
80024ea: 4603 mov r3, r0
80024ec: 4619 mov r1, r3
80024ee: 4620 mov r0, r4
80024f0: f7fe fb8c bl 8000c0c <__aeabi_fdiv>
80024f4: 4603 mov r3, r0
80024f6: 461a mov r2, r3
80024f8: 4b8c ldr r3, [pc, #560] @ (800272c <main+0x474>)
80024fa: 611a str r2, [r3, #16]
flash_data.ph7_real = ph7_interp;
80024fc: 4a8b ldr r2, [pc, #556] @ (800272c <main+0x474>)
80024fe: 6afb ldr r3, [r7, #44] @ 0x2c
8002500: 6153 str r3, [r2, #20]
Flash_Save_Page(&flash_data); // Store Calibration parameters in Flash
8002502: 488a ldr r0, [pc, #552] @ (800272c <main+0x474>)
8002504: f7ff fcf6 bl 8001ef4 <Flash_Save_Page>
HAL_Delay(500);
8002508: f44f 70fa mov.w r0, #500 @ 0x1f4
800250c: f000 fcf6 bl 8002efc <HAL_Delay>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
8002510: 2200 movs r2, #0
8002512: 2110 movs r1, #16
8002514: 4886 ldr r0, [pc, #536] @ (8002730 <main+0x478>)
8002516: f001 fc82 bl 8003e1e <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
800251a: 2201 movs r2, #1
800251c: 2120 movs r1, #32
800251e: 4884 ldr r0, [pc, #528] @ (8002730 <main+0x478>)
8002520: f001 fc7d bl 8003e1e <HAL_GPIO_WritePin>
main_state = STATE_RUNNING_OK;
8002524: 4b83 ldr r3, [pc, #524] @ (8002734 <main+0x47c>)
8002526: 2200 movs r2, #0
8002528: 701a strb r2, [r3, #0]
{
current_millis = HAL_GetTick();
800252a: f000 fcdd bl 8002ee8 <HAL_GetTick>
800252e: 6278 str r0, [r7, #36] @ 0x24
// Piscar LED verde em PB5 a cada 0,5 segundos
if ((current_millis - previous_millis_green) >= 500)
8002530: 6a7a ldr r2, [r7, #36] @ 0x24
8002532: 6c3b ldr r3, [r7, #64] @ 0x40
8002534: 1ad3 subs r3, r2, r3
8002536: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
800253a: d31b bcc.n 8002574 <main+0x2bc>
{
previous_millis_green = current_millis;
800253c: 6a7b ldr r3, [r7, #36] @ 0x24
800253e: 643b str r3, [r7, #64] @ 0x40
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_5);
8002540: 2120 movs r1, #32
8002542: 487b ldr r0, [pc, #492] @ (8002730 <main+0x478>)
8002544: f001 fc83 bl 8003e4e <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_green_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_5);
8002548: 2120 movs r1, #32
800254a: 4879 ldr r0, [pc, #484] @ (8002730 <main+0x478>)
800254c: f001 fc50 bl 8003df0 <HAL_GPIO_ReadPin>
8002550: 4603 mov r3, r0
8002552: f887 3023 strb.w r3, [r7, #35] @ 0x23
if (current_green_state != previous_green_state)
8002556: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
800255a: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
800255e: 429a cmp r2, r3
8002560: d008 beq.n 8002574 <main+0x2bc>
{
previous_green_state = current_green_state;
8002562: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8002566: f887 3047 strb.w r3, [r7, #71] @ 0x47
uint8_t led_data[2] = {0x01, current_green_state}; // Command 0x01 for green LED
800256a: 2301 movs r3, #1
800256c: 723b strb r3, [r7, #8]
800256e: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8002572: 727b strb r3, [r7, #9]
}
// Piscar LED vermelho em PB4 a cada 1 segundo
if ((current_millis - previous_millis_red) >= 1000)
8002574: 6a7a ldr r2, [r7, #36] @ 0x24
8002576: 6bfb ldr r3, [r7, #60] @ 0x3c
8002578: 1ad3 subs r3, r2, r3
800257a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800257e: d3d4 bcc.n 800252a <main+0x272>
{
previous_millis_red = current_millis;
8002580: 6a7b ldr r3, [r7, #36] @ 0x24
8002582: 63fb str r3, [r7, #60] @ 0x3c
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4);
8002584: 2110 movs r1, #16
8002586: 486a ldr r0, [pc, #424] @ (8002730 <main+0x478>)
8002588: f001 fc61 bl 8003e4e <HAL_GPIO_TogglePin>
// Check if state changed and send via RS485
uint8_t current_red_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_4);
800258c: 2110 movs r1, #16
800258e: 4868 ldr r0, [pc, #416] @ (8002730 <main+0x478>)
8002590: f001 fc2e bl 8003df0 <HAL_GPIO_ReadPin>
8002594: 4603 mov r3, r0
8002596: f887 3022 strb.w r3, [r7, #34] @ 0x22
if (current_red_state != previous_red_state)
800259a: f897 2022 ldrb.w r2, [r7, #34] @ 0x22
800259e: f897 3046 ldrb.w r3, [r7, #70] @ 0x46
80025a2: 429a cmp r2, r3
80025a4: d008 beq.n 80025b8 <main+0x300>
{
previous_red_state = current_red_state;
80025a6: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
80025aa: f887 3046 strb.w r3, [r7, #70] @ 0x46
uint8_t led_data[2] = {0x02, current_red_state}; // Command 0x02 for red LED
80025ae: 2302 movs r3, #2
80025b0: 713b strb r3, [r7, #4]
80025b2: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
80025b6: 717b strb r3, [r7, #5]
}
status1 = rs485_send_broadcast(tm_t, strlen((char*)tm_t));
80025b8: 485f ldr r0, [pc, #380] @ (8002738 <main+0x480>)
80025ba: f7fd fdc7 bl 800014c <strlen>
80025be: 4603 mov r3, r0
80025c0: b29b uxth r3, r3
80025c2: 4619 mov r1, r3
80025c4: 485c ldr r0, [pc, #368] @ (8002738 <main+0x480>)
80025c6: f000 fa69 bl 8002a9c <rs485_send_broadcast>
80025ca: 4603 mov r3, r0
80025cc: f887 3021 strb.w r3, [r7, #33] @ 0x21
temperature_RTD = AD5934_GetTemperature(refResistance);
80025d0: 6b78 ldr r0, [r7, #52] @ 0x34
80025d2: f7fe fdcb bl 800116c <AD5934_GetTemperature>
80025d6: 63b8 str r0, [r7, #56] @ 0x38
FloatToString(tempString, temperature_RTD);
80025d8: 6bb8 ldr r0, [r7, #56] @ 0x38
80025da: f7fe f84d bl 8000678 <__aeabi_f2d>
80025de: 4602 mov r2, r0
80025e0: 460b mov r3, r1
80025e2: f107 010c add.w r1, r7, #12
80025e6: 4608 mov r0, r1
80025e8: f000 f906 bl 80027f8 <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
80025ec: f107 030c add.w r3, r7, #12
80025f0: 4618 mov r0, r3
80025f2: f7fd fdab bl 800014c <strlen>
80025f6: 4603 mov r3, r0
80025f8: b29b uxth r3, r3
80025fa: 3b01 subs r3, #1
80025fc: b29a uxth r2, r3
80025fe: f107 030c add.w r3, r7, #12
8002602: 4611 mov r1, r2
8002604: 4618 mov r0, r3
8002606: f000 fa49 bl 8002a9c <rs485_send_broadcast>
800260a: 4603 mov r3, r0
800260c: f887 3020 strb.w r3, [r7, #32]
status1 = rs485_send_broadcast(newline_temp, strlen((char*)newline_temp));
8002610: 484a ldr r0, [pc, #296] @ (800273c <main+0x484>)
8002612: f7fd fd9b bl 800014c <strlen>
8002616: 4603 mov r3, r0
8002618: b29b uxth r3, r3
800261a: 4619 mov r1, r3
800261c: 4847 ldr r0, [pc, #284] @ (800273c <main+0x484>)
800261e: f000 fa3d bl 8002a9c <rs485_send_broadcast>
8002622: 4603 mov r3, r0
8002624: f887 3021 strb.w r3, [r7, #33] @ 0x21
status1 = rs485_send_broadcast(ad_t, strlen((char*)ad_t));
8002628: 4845 ldr r0, [pc, #276] @ (8002740 <main+0x488>)
800262a: f7fd fd8f bl 800014c <strlen>
800262e: 4603 mov r3, r0
8002630: b29b uxth r3, r3
8002632: 4619 mov r1, r3
8002634: 4842 ldr r0, [pc, #264] @ (8002740 <main+0x488>)
8002636: f000 fa31 bl 8002a9c <rs485_send_broadcast>
800263a: 4603 mov r3, r0
800263c: f887 3021 strb.w r3, [r7, #33] @ 0x21
admittance_EC = AD5934_GetImpedance(temperature_RTD);
8002640: 6bb8 ldr r0, [r7, #56] @ 0x38
8002642: f7fe fe85 bl 8001350 <AD5934_GetImpedance>
8002646: 61f8 str r0, [r7, #28]
FloatToString(tempString, admittance_EC);
8002648: 69f8 ldr r0, [r7, #28]
800264a: f7fe f815 bl 8000678 <__aeabi_f2d>
800264e: 4602 mov r2, r0
8002650: 460b mov r3, r1
8002652: f107 010c add.w r1, r7, #12
8002656: 4608 mov r0, r1
8002658: f000 f8ce bl 80027f8 <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
800265c: f107 030c add.w r3, r7, #12
8002660: 4618 mov r0, r3
8002662: f7fd fd73 bl 800014c <strlen>
8002666: 4603 mov r3, r0
8002668: b29b uxth r3, r3
800266a: 3b01 subs r3, #1
800266c: b29a uxth r2, r3
800266e: f107 030c add.w r3, r7, #12
8002672: 4611 mov r1, r2
8002674: 4618 mov r0, r3
8002676: f000 fa11 bl 8002a9c <rs485_send_broadcast>
800267a: 4603 mov r3, r0
800267c: f887 3020 strb.w r3, [r7, #32]
status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi));
8002680: 4830 ldr r0, [pc, #192] @ (8002744 <main+0x48c>)
8002682: f7fd fd63 bl 800014c <strlen>
8002686: 4603 mov r3, r0
8002688: b29b uxth r3, r3
800268a: 4619 mov r1, r3
800268c: 482d ldr r0, [pc, #180] @ (8002744 <main+0x48c>)
800268e: f000 fa05 bl 8002a9c <rs485_send_broadcast>
8002692: 4603 mov r3, r0
8002694: f887 3021 strb.w r3, [r7, #33] @ 0x21
status1 = rs485_send_broadcast(ph_t, strlen((char*)ph_t));
8002698: 482b ldr r0, [pc, #172] @ (8002748 <main+0x490>)
800269a: f7fd fd57 bl 800014c <strlen>
800269e: 4603 mov r3, r0
80026a0: b29b uxth r3, r3
80026a2: 4619 mov r1, r3
80026a4: 4828 ldr r0, [pc, #160] @ (8002748 <main+0x490>)
80026a6: f000 f9f9 bl 8002a9c <rs485_send_broadcast>
80026aa: 4603 mov r3, r0
80026ac: f887 3021 strb.w r3, [r7, #33] @ 0x21
ph_compensated = 10*ADSCalculate_ph_mV();//ADSCalculate_ph_Compensated(temperature_RTD);
80026b0: f7ff fa6a bl 8001b88 <ADSCalculate_ph_mV>
80026b4: 4603 mov r3, r0
80026b6: 4925 ldr r1, [pc, #148] @ (800274c <main+0x494>)
80026b8: 4618 mov r0, r3
80026ba: f7fe f9f3 bl 8000aa4 <__aeabi_fmul>
80026be: 4603 mov r3, r0
80026c0: 61bb str r3, [r7, #24]
FloatToString(tempString, ph_compensated);
80026c2: 69b8 ldr r0, [r7, #24]
80026c4: f7fd ffd8 bl 8000678 <__aeabi_f2d>
80026c8: 4602 mov r2, r0
80026ca: 460b mov r3, r1
80026cc: f107 010c add.w r1, r7, #12
80026d0: 4608 mov r0, r1
80026d2: f000 f891 bl 80027f8 <FloatToString>
status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
80026d6: f107 030c add.w r3, r7, #12
80026da: 4618 mov r0, r3
80026dc: f7fd fd36 bl 800014c <strlen>
80026e0: 4603 mov r3, r0
80026e2: b29b uxth r3, r3
80026e4: 3b01 subs r3, #1
80026e6: b29a uxth r2, r3
80026e8: f107 030c add.w r3, r7, #12
80026ec: 4611 mov r1, r2
80026ee: 4618 mov r0, r3
80026f0: f000 f9d4 bl 8002a9c <rs485_send_broadcast>
80026f4: 4603 mov r3, r0
80026f6: f887 3020 strb.w r3, [r7, #32]
status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph));
80026fa: 4815 ldr r0, [pc, #84] @ (8002750 <main+0x498>)
80026fc: f7fd fd26 bl 800014c <strlen>
8002700: 4603 mov r3, r0
8002702: b29b uxth r3, r3
8002704: 4619 mov r1, r3
8002706: 4812 ldr r0, [pc, #72] @ (8002750 <main+0x498>)
8002708: f000 f9c8 bl 8002a9c <rs485_send_broadcast>
800270c: 4603 mov r3, r0
800270e: f887 3021 strb.w r3, [r7, #33] @ 0x21
status1 = rs485_send_broadcast(newline, strlen((char*)newline));
8002712: 4810 ldr r0, [pc, #64] @ (8002754 <main+0x49c>)
8002714: f7fd fd1a bl 800014c <strlen>
8002718: 4603 mov r3, r0
800271a: b29b uxth r3, r3
800271c: 4619 mov r1, r3
800271e: 480d ldr r0, [pc, #52] @ (8002754 <main+0x49c>)
8002720: f000 f9bc bl 8002a9c <rs485_send_broadcast>
8002724: 4603 mov r3, r0
8002726: f887 3021 strb.w r3, [r7, #33] @ 0x21
current_millis = HAL_GetTick();
800272a: e6fe b.n 800252a <main+0x272>
800272c: 20000224 .word 0x20000224
8002730: 40010c00 .word 0x40010c00
8002734: 200006cc .word 0x200006cc
8002738: 2000002c .word 0x2000002c
800273c: 20000014 .word 0x20000014
8002740: 2000001c .word 0x2000001c
8002744: 2000000c .word 0x2000000c
8002748: 20000024 .word 0x20000024
800274c: 41200000 .word 0x41200000
8002750: 20000004 .word 0x20000004
8002754: 20000000 .word 0x20000000
08002758 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8002758: b580 push {r7, lr}
800275a: b094 sub sp, #80 @ 0x50
800275c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800275e: f107 0328 add.w r3, r7, #40 @ 0x28
8002762: 2228 movs r2, #40 @ 0x28
8002764: 2100 movs r1, #0
8002766: 4618 mov r0, r3
8002768: f003 fe9c bl 80064a4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800276c: f107 0314 add.w r3, r7, #20
8002770: 2200 movs r2, #0
8002772: 601a str r2, [r3, #0]
8002774: 605a str r2, [r3, #4]
8002776: 609a str r2, [r3, #8]
8002778: 60da str r2, [r3, #12]
800277a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800277c: 1d3b adds r3, r7, #4
800277e: 2200 movs r2, #0
8002780: 601a str r2, [r3, #0]
8002782: 605a str r2, [r3, #4]
8002784: 609a str r2, [r3, #8]
8002786: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8002788: 2301 movs r3, #1
800278a: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800278c: f44f 3380 mov.w r3, #65536 @ 0x10000
8002790: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8002792: 2300 movs r3, #0
8002794: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8002796: f107 0328 add.w r3, r7, #40 @ 0x28
800279a: 4618 mov r0, r3
800279c: f002 fba4 bl 8004ee8 <HAL_RCC_OscConfig>
80027a0: 4603 mov r3, r0
80027a2: 2b00 cmp r3, #0
80027a4: d001 beq.n 80027aa <SystemClock_Config+0x52>
{
Error_Handler();
80027a6: f000 f93b bl 8002a20 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80027aa: 230f movs r3, #15
80027ac: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80027ae: 2301 movs r3, #1
80027b0: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80027b2: 2300 movs r3, #0
80027b4: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80027b6: 2300 movs r3, #0
80027b8: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80027ba: 2300 movs r3, #0
80027bc: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80027be: f107 0314 add.w r3, r7, #20
80027c2: 2100 movs r1, #0
80027c4: 4618 mov r0, r3
80027c6: f002 fe11 bl 80053ec <HAL_RCC_ClockConfig>
80027ca: 4603 mov r3, r0
80027cc: 2b00 cmp r3, #0
80027ce: d001 beq.n 80027d4 <SystemClock_Config+0x7c>
{
Error_Handler();
80027d0: f000 f926 bl 8002a20 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
80027d4: 2302 movs r3, #2
80027d6: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
80027d8: f44f 4340 mov.w r3, #49152 @ 0xc000
80027dc: 60fb str r3, [r7, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80027de: 1d3b adds r3, r7, #4
80027e0: 4618 mov r0, r3
80027e2: f002 ff93 bl 800570c <HAL_RCCEx_PeriphCLKConfig>
80027e6: 4603 mov r3, r0
80027e8: 2b00 cmp r3, #0
80027ea: d001 beq.n 80027f0 <SystemClock_Config+0x98>
{
Error_Handler();
80027ec: f000 f918 bl 8002a20 <Error_Handler>
}
}
80027f0: bf00 nop
80027f2: 3750 adds r7, #80 @ 0x50
80027f4: 46bd mov sp, r7
80027f6: bd80 pop {r7, pc}
080027f8 <FloatToString>:
* @param val - value to be converted
*
* @return None.
*******************************************************************************/
void FloatToString(char *buf, double val)
{
80027f8: b5b0 push {r4, r5, r7, lr}
80027fa: b096 sub sp, #88 @ 0x58
80027fc: af00 add r7, sp, #0
80027fe: 60f8 str r0, [r7, #12]
8002800: e9c7 2300 strd r2, r3, [r7]
char temp[20]; // Buffer auxiliar para construção segura
int i = 0;
8002804: 2300 movs r3, #0
8002806: 657b str r3, [r7, #84] @ 0x54
// 1. Tratar sinal negativo
if (val < 0) {
8002808: f04f 0200 mov.w r2, #0
800280c: f04f 0300 mov.w r3, #0
8002810: e9d7 0100 ldrd r0, r1, [r7]
8002814: f7fd ffe8 bl 80007e8 <__aeabi_dcmplt>
8002818: 4603 mov r3, r0
800281a: 2b00 cmp r3, #0
800281c: d00d beq.n 800283a <FloatToString+0x42>
temp[i++] = '-';
800281e: 6d7b ldr r3, [r7, #84] @ 0x54
8002820: 1c5a adds r2, r3, #1
8002822: 657a str r2, [r7, #84] @ 0x54
8002824: 3358 adds r3, #88 @ 0x58
8002826: 443b add r3, r7
8002828: 222d movs r2, #45 @ 0x2d
800282a: f803 2c30 strb.w r2, [r3, #-48]
val = -val;
800282e: 683c ldr r4, [r7, #0]
8002830: 687b ldr r3, [r7, #4]
8002832: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000
8002836: e9c7 4500 strd r4, r5, [r7]
}
// 2. Separar parte inteira e fracionária
long intPart = (long)val;
800283a: e9d7 0100 ldrd r0, r1, [r7]
800283e: f7fd fffb bl 8000838 <__aeabi_d2iz>
8002842: 4603 mov r3, r0
8002844: 653b str r3, [r7, #80] @ 0x50
// Multiplicamos por 1000 para obter 3 casas decimais fixas
int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
8002846: 6d38 ldr r0, [r7, #80] @ 0x50
8002848: f7fd ff04 bl 8000654 <__aeabi_i2d>
800284c: 4602 mov r2, r0
800284e: 460b mov r3, r1
8002850: e9d7 0100 ldrd r0, r1, [r7]
8002854: f7fd fdb0 bl 80003b8 <__aeabi_dsub>
8002858: 4602 mov r2, r0
800285a: 460b mov r3, r1
800285c: 4610 mov r0, r2
800285e: 4619 mov r1, r3
8002860: f04f 0200 mov.w r2, #0
8002864: 4b6a ldr r3, [pc, #424] @ (8002a10 <FloatToString+0x218>)
8002866: f7fd fc79 bl 800015c <__aeabi_dmul>
800286a: 4602 mov r2, r0
800286c: 460b mov r3, r1
800286e: 4610 mov r0, r2
8002870: 4619 mov r1, r3
8002872: f04f 0200 mov.w r2, #0
8002876: 4b67 ldr r3, [pc, #412] @ (8002a14 <FloatToString+0x21c>)
8002878: f7fd fda0 bl 80003bc <__adddf3>
800287c: 4602 mov r2, r0
800287e: 460b mov r3, r1
8002880: 4610 mov r0, r2
8002882: 4619 mov r1, r3
8002884: f7fd ffd8 bl 8000838 <__aeabi_d2iz>
8002888: 4603 mov r3, r0
800288a: 63fb str r3, [r7, #60] @ 0x3c
// 3. Converter a parte inteira para o buffer temp
// Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
char intRev[12];
int j = 0;
800288c: 2300 movs r3, #0
800288e: 64fb str r3, [r7, #76] @ 0x4c
if (intPart == 0) {
8002890: 6d3b ldr r3, [r7, #80] @ 0x50
8002892: 2b00 cmp r3, #0
8002894: d126 bne.n 80028e4 <FloatToString+0xec>
intRev[j++] = '0';
8002896: 6cfb ldr r3, [r7, #76] @ 0x4c
8002898: 1c5a adds r2, r3, #1
800289a: 64fa str r2, [r7, #76] @ 0x4c
800289c: 3358 adds r3, #88 @ 0x58
800289e: 443b add r3, r7
80028a0: 2230 movs r2, #48 @ 0x30
80028a2: f803 2c3c strb.w r2, [r3, #-60]
80028a6: e020 b.n 80028ea <FloatToString+0xf2>
} else {
while (intPart > 0) {
intRev[j++] = (intPart % 10) + '0';
80028a8: 6d3a ldr r2, [r7, #80] @ 0x50
80028aa: 4b5b ldr r3, [pc, #364] @ (8002a18 <FloatToString+0x220>)
80028ac: fb83 1302 smull r1, r3, r3, r2
80028b0: 1099 asrs r1, r3, #2
80028b2: 17d3 asrs r3, r2, #31
80028b4: 1ac9 subs r1, r1, r3
80028b6: 460b mov r3, r1
80028b8: 009b lsls r3, r3, #2
80028ba: 440b add r3, r1
80028bc: 005b lsls r3, r3, #1
80028be: 1ad1 subs r1, r2, r3
80028c0: b2ca uxtb r2, r1
80028c2: 6cfb ldr r3, [r7, #76] @ 0x4c
80028c4: 1c59 adds r1, r3, #1
80028c6: 64f9 str r1, [r7, #76] @ 0x4c
80028c8: 3230 adds r2, #48 @ 0x30
80028ca: b2d2 uxtb r2, r2
80028cc: 3358 adds r3, #88 @ 0x58
80028ce: 443b add r3, r7
80028d0: f803 2c3c strb.w r2, [r3, #-60]
intPart /= 10;
80028d4: 6d3b ldr r3, [r7, #80] @ 0x50
80028d6: 4a50 ldr r2, [pc, #320] @ (8002a18 <FloatToString+0x220>)
80028d8: fb82 1203 smull r1, r2, r2, r3
80028dc: 1092 asrs r2, r2, #2
80028de: 17db asrs r3, r3, #31
80028e0: 1ad3 subs r3, r2, r3
80028e2: 653b str r3, [r7, #80] @ 0x50
while (intPart > 0) {
80028e4: 6d3b ldr r3, [r7, #80] @ 0x50
80028e6: 2b00 cmp r3, #0
80028e8: dcde bgt.n 80028a8 <FloatToString+0xb0>
}
}
// Inverter a parte inteira de volta para o buffer principal
for (int k = j - 1; k >= 0; k--) {
80028ea: 6cfb ldr r3, [r7, #76] @ 0x4c
80028ec: 3b01 subs r3, #1
80028ee: 64bb str r3, [r7, #72] @ 0x48
80028f0: e00e b.n 8002910 <FloatToString+0x118>
temp[i++] = intRev[k];
80028f2: 6d7b ldr r3, [r7, #84] @ 0x54
80028f4: 1c5a adds r2, r3, #1
80028f6: 657a str r2, [r7, #84] @ 0x54
80028f8: f107 011c add.w r1, r7, #28
80028fc: 6cba ldr r2, [r7, #72] @ 0x48
80028fe: 440a add r2, r1
8002900: 7812 ldrb r2, [r2, #0]
8002902: 3358 adds r3, #88 @ 0x58
8002904: 443b add r3, r7
8002906: f803 2c30 strb.w r2, [r3, #-48]
for (int k = j - 1; k >= 0; k--) {
800290a: 6cbb ldr r3, [r7, #72] @ 0x48
800290c: 3b01 subs r3, #1
800290e: 64bb str r3, [r7, #72] @ 0x48
8002910: 6cbb ldr r3, [r7, #72] @ 0x48
8002912: 2b00 cmp r3, #0
8002914: daed bge.n 80028f2 <FloatToString+0xfa>
}
// 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
temp[i++] = '.';
8002916: 6d7b ldr r3, [r7, #84] @ 0x54
8002918: 1c5a adds r2, r3, #1
800291a: 657a str r2, [r7, #84] @ 0x54
800291c: 3358 adds r3, #88 @ 0x58
800291e: 443b add r3, r7
8002920: 222e movs r2, #46 @ 0x2e
8002922: f803 2c30 strb.w r2, [r3, #-48]
// Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
int fracBuffer[3];
fracBuffer[2] = fracPart % 10; // Unidade
8002926: 6bf9 ldr r1, [r7, #60] @ 0x3c
8002928: 4b3b ldr r3, [pc, #236] @ (8002a18 <FloatToString+0x220>)
800292a: fb83 2301 smull r2, r3, r3, r1
800292e: 109a asrs r2, r3, #2
8002930: 17cb asrs r3, r1, #31
8002932: 1ad2 subs r2, r2, r3
8002934: 4613 mov r3, r2
8002936: 009b lsls r3, r3, #2
8002938: 4413 add r3, r2
800293a: 005b lsls r3, r3, #1
800293c: 1aca subs r2, r1, r3
800293e: 61ba str r2, [r7, #24]
fracBuffer[1] = (fracPart / 10) % 10; // Dezena
8002940: 6bfb ldr r3, [r7, #60] @ 0x3c
8002942: 4a35 ldr r2, [pc, #212] @ (8002a18 <FloatToString+0x220>)
8002944: fb82 1203 smull r1, r2, r2, r3
8002948: 1092 asrs r2, r2, #2
800294a: 17db asrs r3, r3, #31
800294c: 1ad1 subs r1, r2, r3
800294e: 4b32 ldr r3, [pc, #200] @ (8002a18 <FloatToString+0x220>)
8002950: fb83 2301 smull r2, r3, r3, r1
8002954: 109a asrs r2, r3, #2
8002956: 17cb asrs r3, r1, #31
8002958: 1ad2 subs r2, r2, r3
800295a: 4613 mov r3, r2
800295c: 009b lsls r3, r3, #2
800295e: 4413 add r3, r2
8002960: 005b lsls r3, r3, #1
8002962: 1aca subs r2, r1, r3
8002964: 617a str r2, [r7, #20]
fracBuffer[0] = (fracPart / 100) % 10; // Centena
8002966: 6bfb ldr r3, [r7, #60] @ 0x3c
8002968: 4a2c ldr r2, [pc, #176] @ (8002a1c <FloatToString+0x224>)
800296a: fb82 1203 smull r1, r2, r2, r3
800296e: 1152 asrs r2, r2, #5
8002970: 17db asrs r3, r3, #31
8002972: 1ad1 subs r1, r2, r3
8002974: 4b28 ldr r3, [pc, #160] @ (8002a18 <FloatToString+0x220>)
8002976: fb83 2301 smull r2, r3, r3, r1
800297a: 109a asrs r2, r3, #2
800297c: 17cb asrs r3, r1, #31
800297e: 1ad2 subs r2, r2, r3
8002980: 4613 mov r3, r2
8002982: 009b lsls r3, r3, #2
8002984: 4413 add r3, r2
8002986: 005b lsls r3, r3, #1
8002988: 1aca subs r2, r1, r3
800298a: 613a str r2, [r7, #16]
for (int k = 2; k >= 0; k--) {
800298c: 2302 movs r3, #2
800298e: 647b str r3, [r7, #68] @ 0x44
8002990: e012 b.n 80029b8 <FloatToString+0x1c0>
temp[i++] = fracBuffer[k] + '0';
8002992: 6c7b ldr r3, [r7, #68] @ 0x44
8002994: 009b lsls r3, r3, #2
8002996: 3358 adds r3, #88 @ 0x58
8002998: 443b add r3, r7
800299a: f853 3c48 ldr.w r3, [r3, #-72]
800299e: b2da uxtb r2, r3
80029a0: 6d7b ldr r3, [r7, #84] @ 0x54
80029a2: 1c59 adds r1, r3, #1
80029a4: 6579 str r1, [r7, #84] @ 0x54
80029a6: 3230 adds r2, #48 @ 0x30
80029a8: b2d2 uxtb r2, r2
80029aa: 3358 adds r3, #88 @ 0x58
80029ac: 443b add r3, r7
80029ae: f803 2c30 strb.w r2, [r3, #-48]
for (int k = 2; k >= 0; k--) {
80029b2: 6c7b ldr r3, [r7, #68] @ 0x44
80029b4: 3b01 subs r3, #1
80029b6: 647b str r3, [r7, #68] @ 0x44
80029b8: 6c7b ldr r3, [r7, #68] @ 0x44
80029ba: 2b00 cmp r3, #0
80029bc: dae9 bge.n 8002992 <FloatToString+0x19a>
}
// 5. Finalizar a string com o caractere nulo
temp[i] = '\0';
80029be: f107 0228 add.w r2, r7, #40 @ 0x28
80029c2: 6d7b ldr r3, [r7, #84] @ 0x54
80029c4: 4413 add r3, r2
80029c6: 2200 movs r2, #0
80029c8: 701a strb r2, [r3, #0]
// 6. Copiar para o buffer de destino final (sem risco de lixo)
int destIdx = 0;
80029ca: 2300 movs r3, #0
80029cc: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
80029ce: e00b b.n 80029e8 <FloatToString+0x1f0>
buf[destIdx] = temp[destIdx];
80029d0: 6c3b ldr r3, [r7, #64] @ 0x40
80029d2: 68fa ldr r2, [r7, #12]
80029d4: 4413 add r3, r2
80029d6: f107 0128 add.w r1, r7, #40 @ 0x28
80029da: 6c3a ldr r2, [r7, #64] @ 0x40
80029dc: 440a add r2, r1
80029de: 7812 ldrb r2, [r2, #0]
80029e0: 701a strb r2, [r3, #0]
destIdx++;
80029e2: 6c3b ldr r3, [r7, #64] @ 0x40
80029e4: 3301 adds r3, #1
80029e6: 643b str r3, [r7, #64] @ 0x40
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
80029e8: f107 0228 add.w r2, r7, #40 @ 0x28
80029ec: 6c3b ldr r3, [r7, #64] @ 0x40
80029ee: 4413 add r3, r2
80029f0: 781b ldrb r3, [r3, #0]
80029f2: 2b00 cmp r3, #0
80029f4: d002 beq.n 80029fc <FloatToString+0x204>
80029f6: 6c3b ldr r3, [r7, #64] @ 0x40
80029f8: 2b0e cmp r3, #14
80029fa: dde9 ble.n 80029d0 <FloatToString+0x1d8>
}
buf[destIdx] = '\0';
80029fc: 6c3b ldr r3, [r7, #64] @ 0x40
80029fe: 68fa ldr r2, [r7, #12]
8002a00: 4413 add r3, r2
8002a02: 2200 movs r2, #0
8002a04: 701a strb r2, [r3, #0]
}
8002a06: bf00 nop
8002a08: 3758 adds r7, #88 @ 0x58
8002a0a: 46bd mov sp, r7
8002a0c: bdb0 pop {r4, r5, r7, pc}
8002a0e: bf00 nop
8002a10: 408f4000 .word 0x408f4000
8002a14: 3fe00000 .word 0x3fe00000
8002a18: 66666667 .word 0x66666667
8002a1c: 51eb851f .word 0x51eb851f
08002a20 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8002a20: b480 push {r7}
8002a22: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002a24: b672 cpsid i
}
8002a26: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8002a28: bf00 nop
8002a2a: e7fd b.n 8002a28 <Error_Handler+0x8>
08002a2c <LL_GPIO_ReadInputPort>:
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
8002a2c: b480 push {r7}
8002a2e: b083 sub sp, #12
8002a30: af00 add r7, sp, #0
8002a32: 6078 str r0, [r7, #4]
return (READ_REG(GPIOx->IDR));
8002a34: 687b ldr r3, [r7, #4]
8002a36: 689b ldr r3, [r3, #8]
}
8002a38: 4618 mov r0, r3
8002a3a: 370c adds r7, #12
8002a3c: 46bd mov sp, r7
8002a3e: bc80 pop {r7}
8002a40: 4770 bx lr
...
08002a44 <rs485_init>:
/**
* @brief Initializes the RS-485 driver.
* @note This function configures GPIOs for address detection and USART1 for communication.
*/
void rs485_init(void)
{
8002a44: b580 push {r7, lr}
8002a46: af00 add r7, sp, #0
/* Configure GPIOs for address detection */
rs485_configure_gpio_address();
8002a48: f000 f864 bl 8002b14 <rs485_configure_gpio_address>
/* Configure USART1 for RS-485 communication */
rs485_configure_usart1();
8002a4c: f000 f8a8 bl 8002ba0 <rs485_configure_usart1>
/* Get the current device address from GPIOs */
device_address.full_address = rs485_get_address();
8002a50: f000 f808 bl 8002a64 <rs485_get_address>
8002a54: 4603 mov r3, r0
8002a56: 461a mov r2, r3
8002a58: 4b01 ldr r3, [pc, #4] @ (8002a60 <rs485_init+0x1c>)
8002a5a: 709a strb r2, [r3, #2]
}
8002a5c: bf00 nop
8002a5e: bd80 pop {r7, pc}
8002a60: 200006d0 .word 0x200006d0
08002a64 <rs485_get_address>:
/**
* @brief Gets the current device address from GPIOs.
* @return The 8-bit device address.
*/
uint8_t rs485_get_address(void)
{
8002a64: b598 push {r3, r4, r7, lr}
8002a66: af00 add r7, sp, #0
return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
8002a68: 480a ldr r0, [pc, #40] @ (8002a94 <rs485_get_address+0x30>)
8002a6a: f7ff ffdf bl 8002a2c <LL_GPIO_ReadInputPort>
8002a6e: 4603 mov r3, r0
8002a70: 0a1b lsrs r3, r3, #8
8002a72: b2db uxtb r3, r3
8002a74: f023 030f bic.w r3, r3, #15
8002a78: b2dc uxtb r4, r3
8002a7a: 4807 ldr r0, [pc, #28] @ (8002a98 <rs485_get_address+0x34>)
8002a7c: f7ff ffd6 bl 8002a2c <LL_GPIO_ReadInputPort>
8002a80: 4603 mov r3, r0
8002a82: 089b lsrs r3, r3, #2
8002a84: b2db uxtb r3, r3
8002a86: f003 030f and.w r3, r3, #15
8002a8a: b2db uxtb r3, r3
8002a8c: 4323 orrs r3, r4
8002a8e: b2db uxtb r3, r3
}
8002a90: 4618 mov r0, r3
8002a92: bd98 pop {r3, r4, r7, pc}
8002a94: 40010c00 .word 0x40010c00
8002a98: 40010800 .word 0x40010800
08002a9c <rs485_send_broadcast>:
* @param data Pointer to the data buffer.
* @param length Number of bytes to send.
* @retval HAL_OK on success, otherwise error code.
*/
HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
{
8002a9c: b580 push {r7, lr}
8002a9e: b084 sub sp, #16
8002aa0: af00 add r7, sp, #0
8002aa2: 6078 str r0, [r7, #4]
8002aa4: 460b mov r3, r1
8002aa6: 807b strh r3, [r7, #2]
/* Enable transmission mode */
rs485_enable_tx();
8002aa8: f000 f81c bl 8002ae4 <rs485_enable_tx>
/* Send the broadcast address (0x00) first */
uint8_t broadcast_address = 0x00;
8002aac: 2300 movs r3, #0
8002aae: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
8002ab0: f107 010e add.w r1, r7, #14
8002ab4: f04f 33ff mov.w r3, #4294967295
8002ab8: 2201 movs r2, #1
8002aba: 4809 ldr r0, [pc, #36] @ (8002ae0 <rs485_send_broadcast+0x44>)
8002abc: f002 ff2c bl 8005918 <HAL_UART_Transmit>
/* Send the data */
HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
8002ac0: 887a ldrh r2, [r7, #2]
8002ac2: f04f 33ff mov.w r3, #4294967295
8002ac6: 6879 ldr r1, [r7, #4]
8002ac8: 4805 ldr r0, [pc, #20] @ (8002ae0 <rs485_send_broadcast+0x44>)
8002aca: f002 ff25 bl 8005918 <HAL_UART_Transmit>
8002ace: 4603 mov r3, r0
8002ad0: 73fb strb r3, [r7, #15]
/* Disable transmission mode after sending */
rs485_disable_tx();
8002ad2: f000 f813 bl 8002afc <rs485_disable_tx>
return status;
8002ad6: 7bfb ldrb r3, [r7, #15]
}
8002ad8: 4618 mov r0, r3
8002ada: 3710 adds r7, #16
8002adc: 46bd mov sp, r7
8002ade: bd80 pop {r7, pc}
8002ae0: 200006d4 .word 0x200006d4
08002ae4 <rs485_enable_tx>:
/**
* @brief Enables transmission mode on RS-485 transceiver.
*/
void rs485_enable_tx(void)
{
8002ae4: b580 push {r7, lr}
8002ae6: af00 add r7, sp, #0
/* Set TX EN pin high to enable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
8002ae8: 2201 movs r2, #1
8002aea: f44f 5180 mov.w r1, #4096 @ 0x1000
8002aee: 4802 ldr r0, [pc, #8] @ (8002af8 <rs485_enable_tx+0x14>)
8002af0: f001 f995 bl 8003e1e <HAL_GPIO_WritePin>
}
8002af4: bf00 nop
8002af6: bd80 pop {r7, pc}
8002af8: 40010800 .word 0x40010800
08002afc <rs485_disable_tx>:
/**
* @brief Disables transmission mode on RS-485 transceiver.
*/
void rs485_disable_tx(void)
{
8002afc: b580 push {r7, lr}
8002afe: af00 add r7, sp, #0
/* Set TX EN pin low to disable transmitter */
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
8002b00: 2200 movs r2, #0
8002b02: f44f 5180 mov.w r1, #4096 @ 0x1000
8002b06: 4802 ldr r0, [pc, #8] @ (8002b10 <rs485_disable_tx+0x14>)
8002b08: f001 f989 bl 8003e1e <HAL_GPIO_WritePin>
}
8002b0c: bf00 nop
8002b0e: bd80 pop {r7, pc}
8002b10: 40010800 .word 0x40010800
08002b14 <rs485_configure_gpio_address>:
/**
* @brief Configures GPIOs for address detection.
*/
static void rs485_configure_gpio_address(void)
{
8002b14: b580 push {r7, lr}
8002b16: b086 sub sp, #24
8002b18: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002b1a: f107 0308 add.w r3, r7, #8
8002b1e: 2200 movs r2, #0
8002b20: 601a str r2, [r3, #0]
8002b22: 605a str r2, [r3, #4]
8002b24: 609a str r2, [r3, #8]
8002b26: 60da str r2, [r3, #12]
/* Enable clock for GPIOA and GPIOB */
__HAL_RCC_GPIOA_CLK_ENABLE();
8002b28: 4b1a ldr r3, [pc, #104] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b2a: 699b ldr r3, [r3, #24]
8002b2c: 4a19 ldr r2, [pc, #100] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b2e: f043 0304 orr.w r3, r3, #4
8002b32: 6193 str r3, [r2, #24]
8002b34: 4b17 ldr r3, [pc, #92] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b36: 699b ldr r3, [r3, #24]
8002b38: f003 0304 and.w r3, r3, #4
8002b3c: 607b str r3, [r7, #4]
8002b3e: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002b40: 4b14 ldr r3, [pc, #80] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b42: 699b ldr r3, [r3, #24]
8002b44: 4a13 ldr r2, [pc, #76] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b46: f043 0308 orr.w r3, r3, #8
8002b4a: 6193 str r3, [r2, #24]
8002b4c: 4b11 ldr r3, [pc, #68] @ (8002b94 <rs485_configure_gpio_address+0x80>)
8002b4e: 699b ldr r3, [r3, #24]
8002b50: f003 0308 and.w r3, r3, #8
8002b54: 603b str r3, [r7, #0]
8002b56: 683b ldr r3, [r7, #0]
/* Configure PA2-PA5 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
8002b58: 233c movs r3, #60 @ 0x3c
8002b5a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002b5c: 2300 movs r3, #0
8002b5e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002b60: 2301 movs r3, #1
8002b62: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002b64: f107 0308 add.w r3, r7, #8
8002b68: 4619 mov r1, r3
8002b6a: 480b ldr r0, [pc, #44] @ (8002b98 <rs485_configure_gpio_address+0x84>)
8002b6c: f000 ffbc bl 8003ae8 <HAL_GPIO_Init>
/* Configure PB12-PB15 as input with pull-up */
GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
8002b70: f44f 4370 mov.w r3, #61440 @ 0xf000
8002b74: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002b76: 2300 movs r3, #0
8002b78: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002b7a: 2301 movs r3, #1
8002b7c: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002b7e: f107 0308 add.w r3, r7, #8
8002b82: 4619 mov r1, r3
8002b84: 4805 ldr r0, [pc, #20] @ (8002b9c <rs485_configure_gpio_address+0x88>)
8002b86: f000 ffaf bl 8003ae8 <HAL_GPIO_Init>
}
8002b8a: bf00 nop
8002b8c: 3718 adds r7, #24
8002b8e: 46bd mov sp, r7
8002b90: bd80 pop {r7, pc}
8002b92: bf00 nop
8002b94: 40021000 .word 0x40021000
8002b98: 40010800 .word 0x40010800
8002b9c: 40010c00 .word 0x40010c00
08002ba0 <rs485_configure_usart1>:
/**
* @brief Configures USART1 for RS-485 communication.
*/
static void rs485_configure_usart1(void)
{
8002ba0: b580 push {r7, lr}
8002ba2: b082 sub sp, #8
8002ba4: af00 add r7, sp, #0
/* Enable clock for USART1 */
__HAL_RCC_USART1_CLK_ENABLE();
8002ba6: 4b18 ldr r3, [pc, #96] @ (8002c08 <rs485_configure_usart1+0x68>)
8002ba8: 699b ldr r3, [r3, #24]
8002baa: 4a17 ldr r2, [pc, #92] @ (8002c08 <rs485_configure_usart1+0x68>)
8002bac: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002bb0: 6193 str r3, [r2, #24]
8002bb2: 4b15 ldr r3, [pc, #84] @ (8002c08 <rs485_configure_usart1+0x68>)
8002bb4: 699b ldr r3, [r3, #24]
8002bb6: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002bba: 607b str r3, [r7, #4]
8002bbc: 687b ldr r3, [r7, #4]
huart1.Instance = USART1;
8002bbe: 4b13 ldr r3, [pc, #76] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bc0: 4a13 ldr r2, [pc, #76] @ (8002c10 <rs485_configure_usart1+0x70>)
8002bc2: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */
8002bc4: 4b11 ldr r3, [pc, #68] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bc6: f44f 5216 mov.w r2, #9600 @ 0x2580
8002bca: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002bcc: 4b0f ldr r3, [pc, #60] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bce: 2200 movs r2, #0
8002bd0: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002bd2: 4b0e ldr r3, [pc, #56] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bd4: 2200 movs r2, #0
8002bd6: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8002bd8: 4b0c ldr r3, [pc, #48] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bda: 2200 movs r2, #0
8002bdc: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002bde: 4b0b ldr r3, [pc, #44] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002be0: 220c movs r2, #12
8002be2: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
8002be4: 4b09 ldr r3, [pc, #36] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002be6: 2200 movs r2, #0
8002be8: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8002bea: 4b08 ldr r3, [pc, #32] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bec: 2200 movs r2, #0
8002bee: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002bf0: 4806 ldr r0, [pc, #24] @ (8002c0c <rs485_configure_usart1+0x6c>)
8002bf2: f002 fe41 bl 8005878 <HAL_UART_Init>
8002bf6: 4603 mov r3, r0
8002bf8: 2b00 cmp r3, #0
8002bfa: d001 beq.n 8002c00 <rs485_configure_usart1+0x60>
{
/* Initialization Error */
while(1);
8002bfc: bf00 nop
8002bfe: e7fd b.n 8002bfc <rs485_configure_usart1+0x5c>
}
}
8002c00: bf00 nop
8002c02: 3708 adds r7, #8
8002c04: 46bd mov sp, r7
8002c06: bd80 pop {r7, pc}
8002c08: 40021000 .word 0x40021000
8002c0c: 200006d4 .word 0x200006d4
8002c10: 40013800 .word 0x40013800
08002c14 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8002c14: b480 push {r7}
8002c16: b085 sub sp, #20
8002c18: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8002c1a: 4b15 ldr r3, [pc, #84] @ (8002c70 <HAL_MspInit+0x5c>)
8002c1c: 699b ldr r3, [r3, #24]
8002c1e: 4a14 ldr r2, [pc, #80] @ (8002c70 <HAL_MspInit+0x5c>)
8002c20: f043 0301 orr.w r3, r3, #1
8002c24: 6193 str r3, [r2, #24]
8002c26: 4b12 ldr r3, [pc, #72] @ (8002c70 <HAL_MspInit+0x5c>)
8002c28: 699b ldr r3, [r3, #24]
8002c2a: f003 0301 and.w r3, r3, #1
8002c2e: 60bb str r3, [r7, #8]
8002c30: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8002c32: 4b0f ldr r3, [pc, #60] @ (8002c70 <HAL_MspInit+0x5c>)
8002c34: 69db ldr r3, [r3, #28]
8002c36: 4a0e ldr r2, [pc, #56] @ (8002c70 <HAL_MspInit+0x5c>)
8002c38: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002c3c: 61d3 str r3, [r2, #28]
8002c3e: 4b0c ldr r3, [pc, #48] @ (8002c70 <HAL_MspInit+0x5c>)
8002c40: 69db ldr r3, [r3, #28]
8002c42: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c46: 607b str r3, [r7, #4]
8002c48: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8002c4a: 4b0a ldr r3, [pc, #40] @ (8002c74 <HAL_MspInit+0x60>)
8002c4c: 685b ldr r3, [r3, #4]
8002c4e: 60fb str r3, [r7, #12]
8002c50: 68fb ldr r3, [r7, #12]
8002c52: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
8002c56: 60fb str r3, [r7, #12]
8002c58: 68fb ldr r3, [r7, #12]
8002c5a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002c5e: 60fb str r3, [r7, #12]
8002c60: 4a04 ldr r2, [pc, #16] @ (8002c74 <HAL_MspInit+0x60>)
8002c62: 68fb ldr r3, [r7, #12]
8002c64: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8002c66: bf00 nop
8002c68: 3714 adds r7, #20
8002c6a: 46bd mov sp, r7
8002c6c: bc80 pop {r7}
8002c6e: 4770 bx lr
8002c70: 40021000 .word 0x40021000
8002c74: 40010000 .word 0x40010000
08002c78 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8002c78: b480 push {r7}
8002c7a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8002c7c: bf00 nop
8002c7e: e7fd b.n 8002c7c <NMI_Handler+0x4>
08002c80 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8002c80: b480 push {r7}
8002c82: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8002c84: bf00 nop
8002c86: e7fd b.n 8002c84 <HardFault_Handler+0x4>
08002c88 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8002c88: b480 push {r7}
8002c8a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8002c8c: bf00 nop
8002c8e: e7fd b.n 8002c8c <MemManage_Handler+0x4>
08002c90 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8002c90: b480 push {r7}
8002c92: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8002c94: bf00 nop
8002c96: e7fd b.n 8002c94 <BusFault_Handler+0x4>
08002c98 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8002c98: b480 push {r7}
8002c9a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8002c9c: bf00 nop
8002c9e: e7fd b.n 8002c9c <UsageFault_Handler+0x4>
08002ca0 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8002ca0: b480 push {r7}
8002ca2: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8002ca4: bf00 nop
8002ca6: 46bd mov sp, r7
8002ca8: bc80 pop {r7}
8002caa: 4770 bx lr
08002cac <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8002cac: b480 push {r7}
8002cae: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8002cb0: bf00 nop
8002cb2: 46bd mov sp, r7
8002cb4: bc80 pop {r7}
8002cb6: 4770 bx lr
08002cb8 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8002cb8: b480 push {r7}
8002cba: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8002cbc: bf00 nop
8002cbe: 46bd mov sp, r7
8002cc0: bc80 pop {r7}
8002cc2: 4770 bx lr
08002cc4 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002cc4: b580 push {r7, lr}
8002cc6: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002cc8: f000 f8fc bl 8002ec4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8002ccc: bf00 nop
8002cce: bd80 pop {r7, pc}
08002cd0 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8002cd0: b580 push {r7, lr}
8002cd2: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8002cd4: 4802 ldr r0, [pc, #8] @ (8002ce0 <USART1_IRQHandler+0x10>)
8002cd6: f002 feab bl 8005a30 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8002cda: bf00 nop
8002cdc: bd80 pop {r7, pc}
8002cde: bf00 nop
8002ce0: 2000071c .word 0x2000071c
08002ce4 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8002ce4: b480 push {r7}
8002ce6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8002ce8: bf00 nop
8002cea: 46bd mov sp, r7
8002cec: bc80 pop {r7}
8002cee: 4770 bx lr
08002cf0 <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8002cf0: b580 push {r7, lr}
8002cf2: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8002cf4: 4b11 ldr r3, [pc, #68] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002cf6: 4a12 ldr r2, [pc, #72] @ (8002d40 <MX_USART1_UART_Init+0x50>)
8002cf8: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8002cfa: 4b10 ldr r3, [pc, #64] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002cfc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8002d00: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8002d02: 4b0e ldr r3, [pc, #56] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d04: 2200 movs r2, #0
8002d06: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8002d08: 4b0c ldr r3, [pc, #48] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d0a: 2200 movs r2, #0
8002d0c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8002d0e: 4b0b ldr r3, [pc, #44] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d10: 2200 movs r2, #0
8002d12: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8002d14: 4b09 ldr r3, [pc, #36] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d16: 220c movs r2, #12
8002d18: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8002d1a: 4b08 ldr r3, [pc, #32] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d1c: 2200 movs r2, #0
8002d1e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8002d20: 4b06 ldr r3, [pc, #24] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d22: 2200 movs r2, #0
8002d24: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8002d26: 4805 ldr r0, [pc, #20] @ (8002d3c <MX_USART1_UART_Init+0x4c>)
8002d28: f002 fda6 bl 8005878 <HAL_UART_Init>
8002d2c: 4603 mov r3, r0
8002d2e: 2b00 cmp r3, #0
8002d30: d001 beq.n 8002d36 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8002d32: f7ff fe75 bl 8002a20 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8002d36: bf00 nop
8002d38: bd80 pop {r7, pc}
8002d3a: bf00 nop
8002d3c: 2000071c .word 0x2000071c
8002d40: 40013800 .word 0x40013800
08002d44 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8002d44: b580 push {r7, lr}
8002d46: b088 sub sp, #32
8002d48: af00 add r7, sp, #0
8002d4a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002d4c: f107 0310 add.w r3, r7, #16
8002d50: 2200 movs r2, #0
8002d52: 601a str r2, [r3, #0]
8002d54: 605a str r2, [r3, #4]
8002d56: 609a str r2, [r3, #8]
8002d58: 60da str r2, [r3, #12]
if(uartHandle->Instance==USART1)
8002d5a: 687b ldr r3, [r7, #4]
8002d5c: 681b ldr r3, [r3, #0]
8002d5e: 4a20 ldr r2, [pc, #128] @ (8002de0 <HAL_UART_MspInit+0x9c>)
8002d60: 4293 cmp r3, r2
8002d62: d139 bne.n 8002dd8 <HAL_UART_MspInit+0x94>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8002d64: 4b1f ldr r3, [pc, #124] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d66: 699b ldr r3, [r3, #24]
8002d68: 4a1e ldr r2, [pc, #120] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d6a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002d6e: 6193 str r3, [r2, #24]
8002d70: 4b1c ldr r3, [pc, #112] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d72: 699b ldr r3, [r3, #24]
8002d74: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002d78: 60fb str r3, [r7, #12]
8002d7a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8002d7c: 4b19 ldr r3, [pc, #100] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d7e: 699b ldr r3, [r3, #24]
8002d80: 4a18 ldr r2, [pc, #96] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d82: f043 0304 orr.w r3, r3, #4
8002d86: 6193 str r3, [r2, #24]
8002d88: 4b16 ldr r3, [pc, #88] @ (8002de4 <HAL_UART_MspInit+0xa0>)
8002d8a: 699b ldr r3, [r3, #24]
8002d8c: f003 0304 and.w r3, r3, #4
8002d90: 60bb str r3, [r7, #8]
8002d92: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = TX_RS485_Pin;
8002d94: f44f 7300 mov.w r3, #512 @ 0x200
8002d98: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8002d9a: 2302 movs r3, #2
8002d9c: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
8002d9e: 2301 movs r3, #1
8002da0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
8002da2: f107 0310 add.w r3, r7, #16
8002da6: 4619 mov r1, r3
8002da8: 480f ldr r0, [pc, #60] @ (8002de8 <HAL_UART_MspInit+0xa4>)
8002daa: f000 fe9d bl 8003ae8 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RX_RS485_Pin;
8002dae: f44f 6380 mov.w r3, #1024 @ 0x400
8002db2: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002db4: 2300 movs r3, #0
8002db6: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002db8: 2300 movs r3, #0
8002dba: 61bb str r3, [r7, #24]
HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
8002dbc: f107 0310 add.w r3, r7, #16
8002dc0: 4619 mov r1, r3
8002dc2: 4809 ldr r0, [pc, #36] @ (8002de8 <HAL_UART_MspInit+0xa4>)
8002dc4: f000 fe90 bl 8003ae8 <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8002dc8: 2200 movs r2, #0
8002dca: 2100 movs r1, #0
8002dcc: 2025 movs r0, #37 @ 0x25
8002dce: f000 fba2 bl 8003516 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8002dd2: 2025 movs r0, #37 @ 0x25
8002dd4: f000 fbbb bl 800354e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8002dd8: bf00 nop
8002dda: 3720 adds r7, #32
8002ddc: 46bd mov sp, r7
8002dde: bd80 pop {r7, pc}
8002de0: 40013800 .word 0x40013800
8002de4: 40021000 .word 0x40021000
8002de8: 40010800 .word 0x40010800
08002dec <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8002dec: f7ff ff7a bl 8002ce4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8002df0: 480b ldr r0, [pc, #44] @ (8002e20 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8002df2: 490c ldr r1, [pc, #48] @ (8002e24 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8002df4: 4a0c ldr r2, [pc, #48] @ (8002e28 <LoopFillZerobss+0x16>)
movs r3, #0
8002df6: 2300 movs r3, #0
b LoopCopyDataInit
8002df8: e002 b.n 8002e00 <LoopCopyDataInit>
08002dfa <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8002dfa: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8002dfc: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8002dfe: 3304 adds r3, #4
08002e00 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002e00: 18c4 adds r4, r0, r3
cmp r4, r1
8002e02: 428c cmp r4, r1
bcc CopyDataInit
8002e04: d3f9 bcc.n 8002dfa <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8002e06: 4a09 ldr r2, [pc, #36] @ (8002e2c <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8002e08: 4c09 ldr r4, [pc, #36] @ (8002e30 <LoopFillZerobss+0x1e>)
movs r3, #0
8002e0a: 2300 movs r3, #0
b LoopFillZerobss
8002e0c: e001 b.n 8002e12 <LoopFillZerobss>
08002e0e <FillZerobss>:
FillZerobss:
str r3, [r2]
8002e0e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002e10: 3204 adds r2, #4
08002e12 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002e12: 42a2 cmp r2, r4
bcc FillZerobss
8002e14: d3fb bcc.n 8002e0e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8002e16: f003 fb53 bl 80064c0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8002e1a: f7ff fa4d bl 80022b8 <main>
bx lr
8002e1e: 4770 bx lr
ldr r0, =_sdata
8002e20: 20000000 .word 0x20000000
ldr r1, =_edata
8002e24: 20000090 .word 0x20000090
ldr r2, =_sidata
8002e28: 08006828 .word 0x08006828
ldr r2, =_sbss
8002e2c: 20000090 .word 0x20000090
ldr r4, =_ebss
8002e30: 200008c0 .word 0x200008c0
08002e34 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002e34: e7fe b.n 8002e34 <ADC1_2_IRQHandler>
...
08002e38 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8002e38: b580 push {r7, lr}
8002e3a: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002e3c: 4b08 ldr r3, [pc, #32] @ (8002e60 <HAL_Init+0x28>)
8002e3e: 681b ldr r3, [r3, #0]
8002e40: 4a07 ldr r2, [pc, #28] @ (8002e60 <HAL_Init+0x28>)
8002e42: f043 0310 orr.w r3, r3, #16
8002e46: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8002e48: 2003 movs r0, #3
8002e4a: f000 fb59 bl 8003500 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002e4e: 200f movs r0, #15
8002e50: f000 f808 bl 8002e64 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002e54: f7ff fede bl 8002c14 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8002e58: 2300 movs r3, #0
}
8002e5a: 4618 mov r0, r3
8002e5c: bd80 pop {r7, pc}
8002e5e: bf00 nop
8002e60: 40022000 .word 0x40022000
08002e64 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002e64: b580 push {r7, lr}
8002e66: b082 sub sp, #8
8002e68: af00 add r7, sp, #0
8002e6a: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002e6c: 4b12 ldr r3, [pc, #72] @ (8002eb8 <HAL_InitTick+0x54>)
8002e6e: 681a ldr r2, [r3, #0]
8002e70: 4b12 ldr r3, [pc, #72] @ (8002ebc <HAL_InitTick+0x58>)
8002e72: 781b ldrb r3, [r3, #0]
8002e74: 4619 mov r1, r3
8002e76: f44f 737a mov.w r3, #1000 @ 0x3e8
8002e7a: fbb3 f3f1 udiv r3, r3, r1
8002e7e: fbb2 f3f3 udiv r3, r2, r3
8002e82: 4618 mov r0, r3
8002e84: f000 fb71 bl 800356a <HAL_SYSTICK_Config>
8002e88: 4603 mov r3, r0
8002e8a: 2b00 cmp r3, #0
8002e8c: d001 beq.n 8002e92 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002e8e: 2301 movs r3, #1
8002e90: e00e b.n 8002eb0 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002e92: 687b ldr r3, [r7, #4]
8002e94: 2b0f cmp r3, #15
8002e96: d80a bhi.n 8002eae <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8002e98: 2200 movs r2, #0
8002e9a: 6879 ldr r1, [r7, #4]
8002e9c: f04f 30ff mov.w r0, #4294967295
8002ea0: f000 fb39 bl 8003516 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8002ea4: 4a06 ldr r2, [pc, #24] @ (8002ec0 <HAL_InitTick+0x5c>)
8002ea6: 687b ldr r3, [r7, #4]
8002ea8: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8002eaa: 2300 movs r3, #0
8002eac: e000 b.n 8002eb0 <HAL_InitTick+0x4c>
return HAL_ERROR;
8002eae: 2301 movs r3, #1
}
8002eb0: 4618 mov r0, r3
8002eb2: 3708 adds r7, #8
8002eb4: 46bd mov sp, r7
8002eb6: bd80 pop {r7, pc}
8002eb8: 20000034 .word 0x20000034
8002ebc: 2000003c .word 0x2000003c
8002ec0: 20000038 .word 0x20000038
08002ec4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8002ec4: b480 push {r7}
8002ec6: af00 add r7, sp, #0
uwTick += uwTickFreq;
8002ec8: 4b05 ldr r3, [pc, #20] @ (8002ee0 <HAL_IncTick+0x1c>)
8002eca: 781b ldrb r3, [r3, #0]
8002ecc: 461a mov r2, r3
8002ece: 4b05 ldr r3, [pc, #20] @ (8002ee4 <HAL_IncTick+0x20>)
8002ed0: 681b ldr r3, [r3, #0]
8002ed2: 4413 add r3, r2
8002ed4: 4a03 ldr r2, [pc, #12] @ (8002ee4 <HAL_IncTick+0x20>)
8002ed6: 6013 str r3, [r2, #0]
}
8002ed8: bf00 nop
8002eda: 46bd mov sp, r7
8002edc: bc80 pop {r7}
8002ede: 4770 bx lr
8002ee0: 2000003c .word 0x2000003c
8002ee4: 20000764 .word 0x20000764
08002ee8 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8002ee8: b480 push {r7}
8002eea: af00 add r7, sp, #0
return uwTick;
8002eec: 4b02 ldr r3, [pc, #8] @ (8002ef8 <HAL_GetTick+0x10>)
8002eee: 681b ldr r3, [r3, #0]
}
8002ef0: 4618 mov r0, r3
8002ef2: 46bd mov sp, r7
8002ef4: bc80 pop {r7}
8002ef6: 4770 bx lr
8002ef8: 20000764 .word 0x20000764
08002efc <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8002efc: b580 push {r7, lr}
8002efe: b084 sub sp, #16
8002f00: af00 add r7, sp, #0
8002f02: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8002f04: f7ff fff0 bl 8002ee8 <HAL_GetTick>
8002f08: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8002f0a: 687b ldr r3, [r7, #4]
8002f0c: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8002f0e: 68fb ldr r3, [r7, #12]
8002f10: f1b3 3fff cmp.w r3, #4294967295
8002f14: d005 beq.n 8002f22 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8002f16: 4b0a ldr r3, [pc, #40] @ (8002f40 <HAL_Delay+0x44>)
8002f18: 781b ldrb r3, [r3, #0]
8002f1a: 461a mov r2, r3
8002f1c: 68fb ldr r3, [r7, #12]
8002f1e: 4413 add r3, r2
8002f20: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8002f22: bf00 nop
8002f24: f7ff ffe0 bl 8002ee8 <HAL_GetTick>
8002f28: 4602 mov r2, r0
8002f2a: 68bb ldr r3, [r7, #8]
8002f2c: 1ad3 subs r3, r2, r3
8002f2e: 68fa ldr r2, [r7, #12]
8002f30: 429a cmp r2, r3
8002f32: d8f7 bhi.n 8002f24 <HAL_Delay+0x28>
{
}
}
8002f34: bf00 nop
8002f36: bf00 nop
8002f38: 3710 adds r7, #16
8002f3a: 46bd mov sp, r7
8002f3c: bd80 pop {r7, pc}
8002f3e: bf00 nop
8002f40: 2000003c .word 0x2000003c
08002f44 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8002f44: b580 push {r7, lr}
8002f46: b086 sub sp, #24
8002f48: af00 add r7, sp, #0
8002f4a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002f4c: 2300 movs r3, #0
8002f4e: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
8002f50: 2300 movs r3, #0
8002f52: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8002f54: 2300 movs r3, #0
8002f56: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
8002f58: 2300 movs r3, #0
8002f5a: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8002f5c: 687b ldr r3, [r7, #4]
8002f5e: 2b00 cmp r3, #0
8002f60: d101 bne.n 8002f66 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
8002f62: 2301 movs r3, #1
8002f64: e0be b.n 80030e4 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8002f66: 687b ldr r3, [r7, #4]
8002f68: 689b ldr r3, [r3, #8]
8002f6a: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002f6c: 687b ldr r3, [r7, #4]
8002f6e: 6a9b ldr r3, [r3, #40] @ 0x28
8002f70: 2b00 cmp r3, #0
8002f72: d109 bne.n 8002f88 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8002f74: 687b ldr r3, [r7, #4]
8002f76: 2200 movs r2, #0
8002f78: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: 2200 movs r2, #0
8002f7e: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8002f82: 6878 ldr r0, [r7, #4]
8002f84: f7fe fce4 bl 8001950 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8002f88: 6878 ldr r0, [r7, #4]
8002f8a: f000 f9ab bl 80032e4 <ADC_ConversionStop_Disable>
8002f8e: 4603 mov r3, r0
8002f90: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8002f92: 687b ldr r3, [r7, #4]
8002f94: 6a9b ldr r3, [r3, #40] @ 0x28
8002f96: f003 0310 and.w r3, r3, #16
8002f9a: 2b00 cmp r3, #0
8002f9c: f040 8099 bne.w 80030d2 <HAL_ADC_Init+0x18e>
8002fa0: 7dfb ldrb r3, [r7, #23]
8002fa2: 2b00 cmp r3, #0
8002fa4: f040 8095 bne.w 80030d2 <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002fa8: 687b ldr r3, [r7, #4]
8002faa: 6a9b ldr r3, [r3, #40] @ 0x28
8002fac: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002fb0: f023 0302 bic.w r3, r3, #2
8002fb4: f043 0202 orr.w r2, r3, #2
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8002fbc: 687b ldr r3, [r7, #4]
8002fbe: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002fc0: 687b ldr r3, [r7, #4]
8002fc2: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8002fc4: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 7b1b ldrb r3, [r3, #12]
8002fca: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002fcc: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8002fce: 68ba ldr r2, [r7, #8]
8002fd0: 4313 orrs r3, r2
8002fd2: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 689b ldr r3, [r3, #8]
8002fd8: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002fdc: d003 beq.n 8002fe6 <HAL_ADC_Init+0xa2>
8002fde: 687b ldr r3, [r7, #4]
8002fe0: 689b ldr r3, [r3, #8]
8002fe2: 2b01 cmp r3, #1
8002fe4: d102 bne.n 8002fec <HAL_ADC_Init+0xa8>
8002fe6: f44f 7380 mov.w r3, #256 @ 0x100
8002fea: e000 b.n 8002fee <HAL_ADC_Init+0xaa>
8002fec: 2300 movs r3, #0
8002fee: 693a ldr r2, [r7, #16]
8002ff0: 4313 orrs r3, r2
8002ff2: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002ff4: 687b ldr r3, [r7, #4]
8002ff6: 7d1b ldrb r3, [r3, #20]
8002ff8: 2b01 cmp r3, #1
8002ffa: d119 bne.n 8003030 <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8002ffc: 687b ldr r3, [r7, #4]
8002ffe: 7b1b ldrb r3, [r3, #12]
8003000: 2b00 cmp r3, #0
8003002: d109 bne.n 8003018 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8003004: 687b ldr r3, [r7, #4]
8003006: 699b ldr r3, [r3, #24]
8003008: 3b01 subs r3, #1
800300a: 035a lsls r2, r3, #13
800300c: 693b ldr r3, [r7, #16]
800300e: 4313 orrs r3, r2
8003010: f443 6300 orr.w r3, r3, #2048 @ 0x800
8003014: 613b str r3, [r7, #16]
8003016: e00b b.n 8003030 <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003018: 687b ldr r3, [r7, #4]
800301a: 6a9b ldr r3, [r3, #40] @ 0x28
800301c: f043 0220 orr.w r2, r3, #32
8003020: 687b ldr r3, [r7, #4]
8003022: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003024: 687b ldr r3, [r7, #4]
8003026: 6adb ldr r3, [r3, #44] @ 0x2c
8003028: f043 0201 orr.w r2, r3, #1
800302c: 687b ldr r3, [r7, #4]
800302e: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
8003030: 687b ldr r3, [r7, #4]
8003032: 681b ldr r3, [r3, #0]
8003034: 685b ldr r3, [r3, #4]
8003036: f423 4169 bic.w r1, r3, #59648 @ 0xe900
800303a: 687b ldr r3, [r7, #4]
800303c: 681b ldr r3, [r3, #0]
800303e: 693a ldr r2, [r7, #16]
8003040: 430a orrs r2, r1
8003042: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
8003044: 687b ldr r3, [r7, #4]
8003046: 681b ldr r3, [r3, #0]
8003048: 689a ldr r2, [r3, #8]
800304a: 4b28 ldr r3, [pc, #160] @ (80030ec <HAL_ADC_Init+0x1a8>)
800304c: 4013 ands r3, r2
800304e: 687a ldr r2, [r7, #4]
8003050: 6812 ldr r2, [r2, #0]
8003052: 68b9 ldr r1, [r7, #8]
8003054: 430b orrs r3, r1
8003056: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8003058: 687b ldr r3, [r7, #4]
800305a: 689b ldr r3, [r3, #8]
800305c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003060: d003 beq.n 800306a <HAL_ADC_Init+0x126>
8003062: 687b ldr r3, [r7, #4]
8003064: 689b ldr r3, [r3, #8]
8003066: 2b01 cmp r3, #1
8003068: d104 bne.n 8003074 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
800306a: 687b ldr r3, [r7, #4]
800306c: 691b ldr r3, [r3, #16]
800306e: 3b01 subs r3, #1
8003070: 051b lsls r3, r3, #20
8003072: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8003074: 687b ldr r3, [r7, #4]
8003076: 681b ldr r3, [r3, #0]
8003078: 6adb ldr r3, [r3, #44] @ 0x2c
800307a: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
800307e: 687b ldr r3, [r7, #4]
8003080: 681b ldr r3, [r3, #0]
8003082: 68fa ldr r2, [r7, #12]
8003084: 430a orrs r2, r1
8003086: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8003088: 687b ldr r3, [r7, #4]
800308a: 681b ldr r3, [r3, #0]
800308c: 689a ldr r2, [r3, #8]
800308e: 4b18 ldr r3, [pc, #96] @ (80030f0 <HAL_ADC_Init+0x1ac>)
8003090: 4013 ands r3, r2
8003092: 68ba ldr r2, [r7, #8]
8003094: 429a cmp r2, r3
8003096: d10b bne.n 80030b0 <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8003098: 687b ldr r3, [r7, #4]
800309a: 2200 movs r2, #0
800309c: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800309e: 687b ldr r3, [r7, #4]
80030a0: 6a9b ldr r3, [r3, #40] @ 0x28
80030a2: f023 0303 bic.w r3, r3, #3
80030a6: f043 0201 orr.w r2, r3, #1
80030aa: 687b ldr r3, [r7, #4]
80030ac: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
80030ae: e018 b.n 80030e2 <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
80030b0: 687b ldr r3, [r7, #4]
80030b2: 6a9b ldr r3, [r3, #40] @ 0x28
80030b4: f023 0312 bic.w r3, r3, #18
80030b8: f043 0210 orr.w r2, r3, #16
80030bc: 687b ldr r3, [r7, #4]
80030be: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80030c0: 687b ldr r3, [r7, #4]
80030c2: 6adb ldr r3, [r3, #44] @ 0x2c
80030c4: f043 0201 orr.w r2, r3, #1
80030c8: 687b ldr r3, [r7, #4]
80030ca: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
80030cc: 2301 movs r3, #1
80030ce: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
80030d0: e007 b.n 80030e2 <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80030d2: 687b ldr r3, [r7, #4]
80030d4: 6a9b ldr r3, [r3, #40] @ 0x28
80030d6: f043 0210 orr.w r2, r3, #16
80030da: 687b ldr r3, [r7, #4]
80030dc: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
80030de: 2301 movs r3, #1
80030e0: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
80030e2: 7dfb ldrb r3, [r7, #23]
}
80030e4: 4618 mov r0, r3
80030e6: 3718 adds r7, #24
80030e8: 46bd mov sp, r7
80030ea: bd80 pop {r7, pc}
80030ec: ffe1f7fd .word 0xffe1f7fd
80030f0: ff1f0efe .word 0xff1f0efe
080030f4 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
80030f4: b480 push {r7}
80030f6: b085 sub sp, #20
80030f8: af00 add r7, sp, #0
80030fa: 6078 str r0, [r7, #4]
80030fc: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80030fe: 2300 movs r3, #0
8003100: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
8003102: 2300 movs r3, #0
8003104: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8003106: 687b ldr r3, [r7, #4]
8003108: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800310c: 2b01 cmp r3, #1
800310e: d101 bne.n 8003114 <HAL_ADC_ConfigChannel+0x20>
8003110: 2302 movs r3, #2
8003112: e0dc b.n 80032ce <HAL_ADC_ConfigChannel+0x1da>
8003114: 687b ldr r3, [r7, #4]
8003116: 2201 movs r2, #1
8003118: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
800311c: 683b ldr r3, [r7, #0]
800311e: 685b ldr r3, [r3, #4]
8003120: 2b06 cmp r3, #6
8003122: d81c bhi.n 800315e <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8003124: 687b ldr r3, [r7, #4]
8003126: 681b ldr r3, [r3, #0]
8003128: 6b59 ldr r1, [r3, #52] @ 0x34
800312a: 683b ldr r3, [r7, #0]
800312c: 685a ldr r2, [r3, #4]
800312e: 4613 mov r3, r2
8003130: 009b lsls r3, r3, #2
8003132: 4413 add r3, r2
8003134: 3b05 subs r3, #5
8003136: 221f movs r2, #31
8003138: fa02 f303 lsl.w r3, r2, r3
800313c: 43db mvns r3, r3
800313e: 4019 ands r1, r3
8003140: 683b ldr r3, [r7, #0]
8003142: 6818 ldr r0, [r3, #0]
8003144: 683b ldr r3, [r7, #0]
8003146: 685a ldr r2, [r3, #4]
8003148: 4613 mov r3, r2
800314a: 009b lsls r3, r3, #2
800314c: 4413 add r3, r2
800314e: 3b05 subs r3, #5
8003150: fa00 f203 lsl.w r2, r0, r3
8003154: 687b ldr r3, [r7, #4]
8003156: 681b ldr r3, [r3, #0]
8003158: 430a orrs r2, r1
800315a: 635a str r2, [r3, #52] @ 0x34
800315c: e03c b.n 80031d8 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
800315e: 683b ldr r3, [r7, #0]
8003160: 685b ldr r3, [r3, #4]
8003162: 2b0c cmp r3, #12
8003164: d81c bhi.n 80031a0 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
8003166: 687b ldr r3, [r7, #4]
8003168: 681b ldr r3, [r3, #0]
800316a: 6b19 ldr r1, [r3, #48] @ 0x30
800316c: 683b ldr r3, [r7, #0]
800316e: 685a ldr r2, [r3, #4]
8003170: 4613 mov r3, r2
8003172: 009b lsls r3, r3, #2
8003174: 4413 add r3, r2
8003176: 3b23 subs r3, #35 @ 0x23
8003178: 221f movs r2, #31
800317a: fa02 f303 lsl.w r3, r2, r3
800317e: 43db mvns r3, r3
8003180: 4019 ands r1, r3
8003182: 683b ldr r3, [r7, #0]
8003184: 6818 ldr r0, [r3, #0]
8003186: 683b ldr r3, [r7, #0]
8003188: 685a ldr r2, [r3, #4]
800318a: 4613 mov r3, r2
800318c: 009b lsls r3, r3, #2
800318e: 4413 add r3, r2
8003190: 3b23 subs r3, #35 @ 0x23
8003192: fa00 f203 lsl.w r2, r0, r3
8003196: 687b ldr r3, [r7, #4]
8003198: 681b ldr r3, [r3, #0]
800319a: 430a orrs r2, r1
800319c: 631a str r2, [r3, #48] @ 0x30
800319e: e01b b.n 80031d8 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
80031a0: 687b ldr r3, [r7, #4]
80031a2: 681b ldr r3, [r3, #0]
80031a4: 6ad9 ldr r1, [r3, #44] @ 0x2c
80031a6: 683b ldr r3, [r7, #0]
80031a8: 685a ldr r2, [r3, #4]
80031aa: 4613 mov r3, r2
80031ac: 009b lsls r3, r3, #2
80031ae: 4413 add r3, r2
80031b0: 3b41 subs r3, #65 @ 0x41
80031b2: 221f movs r2, #31
80031b4: fa02 f303 lsl.w r3, r2, r3
80031b8: 43db mvns r3, r3
80031ba: 4019 ands r1, r3
80031bc: 683b ldr r3, [r7, #0]
80031be: 6818 ldr r0, [r3, #0]
80031c0: 683b ldr r3, [r7, #0]
80031c2: 685a ldr r2, [r3, #4]
80031c4: 4613 mov r3, r2
80031c6: 009b lsls r3, r3, #2
80031c8: 4413 add r3, r2
80031ca: 3b41 subs r3, #65 @ 0x41
80031cc: fa00 f203 lsl.w r2, r0, r3
80031d0: 687b ldr r3, [r7, #4]
80031d2: 681b ldr r3, [r3, #0]
80031d4: 430a orrs r2, r1
80031d6: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
80031d8: 683b ldr r3, [r7, #0]
80031da: 681b ldr r3, [r3, #0]
80031dc: 2b09 cmp r3, #9
80031de: d91c bls.n 800321a <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
80031e0: 687b ldr r3, [r7, #4]
80031e2: 681b ldr r3, [r3, #0]
80031e4: 68d9 ldr r1, [r3, #12]
80031e6: 683b ldr r3, [r7, #0]
80031e8: 681a ldr r2, [r3, #0]
80031ea: 4613 mov r3, r2
80031ec: 005b lsls r3, r3, #1
80031ee: 4413 add r3, r2
80031f0: 3b1e subs r3, #30
80031f2: 2207 movs r2, #7
80031f4: fa02 f303 lsl.w r3, r2, r3
80031f8: 43db mvns r3, r3
80031fa: 4019 ands r1, r3
80031fc: 683b ldr r3, [r7, #0]
80031fe: 6898 ldr r0, [r3, #8]
8003200: 683b ldr r3, [r7, #0]
8003202: 681a ldr r2, [r3, #0]
8003204: 4613 mov r3, r2
8003206: 005b lsls r3, r3, #1
8003208: 4413 add r3, r2
800320a: 3b1e subs r3, #30
800320c: fa00 f203 lsl.w r2, r0, r3
8003210: 687b ldr r3, [r7, #4]
8003212: 681b ldr r3, [r3, #0]
8003214: 430a orrs r2, r1
8003216: 60da str r2, [r3, #12]
8003218: e019 b.n 800324e <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
800321a: 687b ldr r3, [r7, #4]
800321c: 681b ldr r3, [r3, #0]
800321e: 6919 ldr r1, [r3, #16]
8003220: 683b ldr r3, [r7, #0]
8003222: 681a ldr r2, [r3, #0]
8003224: 4613 mov r3, r2
8003226: 005b lsls r3, r3, #1
8003228: 4413 add r3, r2
800322a: 2207 movs r2, #7
800322c: fa02 f303 lsl.w r3, r2, r3
8003230: 43db mvns r3, r3
8003232: 4019 ands r1, r3
8003234: 683b ldr r3, [r7, #0]
8003236: 6898 ldr r0, [r3, #8]
8003238: 683b ldr r3, [r7, #0]
800323a: 681a ldr r2, [r3, #0]
800323c: 4613 mov r3, r2
800323e: 005b lsls r3, r3, #1
8003240: 4413 add r3, r2
8003242: fa00 f203 lsl.w r2, r0, r3
8003246: 687b ldr r3, [r7, #4]
8003248: 681b ldr r3, [r3, #0]
800324a: 430a orrs r2, r1
800324c: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
800324e: 683b ldr r3, [r7, #0]
8003250: 681b ldr r3, [r3, #0]
8003252: 2b10 cmp r3, #16
8003254: d003 beq.n 800325e <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
8003256: 683b ldr r3, [r7, #0]
8003258: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
800325a: 2b11 cmp r3, #17
800325c: d132 bne.n 80032c4 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
800325e: 687b ldr r3, [r7, #4]
8003260: 681b ldr r3, [r3, #0]
8003262: 4a1d ldr r2, [pc, #116] @ (80032d8 <HAL_ADC_ConfigChannel+0x1e4>)
8003264: 4293 cmp r3, r2
8003266: d125 bne.n 80032b4 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
8003268: 687b ldr r3, [r7, #4]
800326a: 681b ldr r3, [r3, #0]
800326c: 689b ldr r3, [r3, #8]
800326e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8003272: 2b00 cmp r3, #0
8003274: d126 bne.n 80032c4 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8003276: 687b ldr r3, [r7, #4]
8003278: 681b ldr r3, [r3, #0]
800327a: 689a ldr r2, [r3, #8]
800327c: 687b ldr r3, [r7, #4]
800327e: 681b ldr r3, [r3, #0]
8003280: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8003284: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8003286: 683b ldr r3, [r7, #0]
8003288: 681b ldr r3, [r3, #0]
800328a: 2b10 cmp r3, #16
800328c: d11a bne.n 80032c4 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
800328e: 4b13 ldr r3, [pc, #76] @ (80032dc <HAL_ADC_ConfigChannel+0x1e8>)
8003290: 681b ldr r3, [r3, #0]
8003292: 4a13 ldr r2, [pc, #76] @ (80032e0 <HAL_ADC_ConfigChannel+0x1ec>)
8003294: fba2 2303 umull r2, r3, r2, r3
8003298: 0c9a lsrs r2, r3, #18
800329a: 4613 mov r3, r2
800329c: 009b lsls r3, r3, #2
800329e: 4413 add r3, r2
80032a0: 005b lsls r3, r3, #1
80032a2: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80032a4: e002 b.n 80032ac <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
80032a6: 68bb ldr r3, [r7, #8]
80032a8: 3b01 subs r3, #1
80032aa: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80032ac: 68bb ldr r3, [r7, #8]
80032ae: 2b00 cmp r3, #0
80032b0: d1f9 bne.n 80032a6 <HAL_ADC_ConfigChannel+0x1b2>
80032b2: e007 b.n 80032c4 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80032b4: 687b ldr r3, [r7, #4]
80032b6: 6a9b ldr r3, [r3, #40] @ 0x28
80032b8: f043 0220 orr.w r2, r3, #32
80032bc: 687b ldr r3, [r7, #4]
80032be: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
80032c0: 2301 movs r3, #1
80032c2: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80032c4: 687b ldr r3, [r7, #4]
80032c6: 2200 movs r2, #0
80032c8: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
80032cc: 7bfb ldrb r3, [r7, #15]
}
80032ce: 4618 mov r0, r3
80032d0: 3714 adds r7, #20
80032d2: 46bd mov sp, r7
80032d4: bc80 pop {r7}
80032d6: 4770 bx lr
80032d8: 40012400 .word 0x40012400
80032dc: 20000034 .word 0x20000034
80032e0: 431bde83 .word 0x431bde83
080032e4 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
80032e4: b580 push {r7, lr}
80032e6: b084 sub sp, #16
80032e8: af00 add r7, sp, #0
80032ea: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
80032ec: 2300 movs r3, #0
80032ee: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
80032f0: 687b ldr r3, [r7, #4]
80032f2: 681b ldr r3, [r3, #0]
80032f4: 689b ldr r3, [r3, #8]
80032f6: f003 0301 and.w r3, r3, #1
80032fa: 2b01 cmp r3, #1
80032fc: d12e bne.n 800335c <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
80032fe: 687b ldr r3, [r7, #4]
8003300: 681b ldr r3, [r3, #0]
8003302: 689a ldr r2, [r3, #8]
8003304: 687b ldr r3, [r7, #4]
8003306: 681b ldr r3, [r3, #0]
8003308: f022 0201 bic.w r2, r2, #1
800330c: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
800330e: f7ff fdeb bl 8002ee8 <HAL_GetTick>
8003312: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8003314: e01b b.n 800334e <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8003316: f7ff fde7 bl 8002ee8 <HAL_GetTick>
800331a: 4602 mov r2, r0
800331c: 68fb ldr r3, [r7, #12]
800331e: 1ad3 subs r3, r2, r3
8003320: 2b02 cmp r3, #2
8003322: d914 bls.n 800334e <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8003324: 687b ldr r3, [r7, #4]
8003326: 681b ldr r3, [r3, #0]
8003328: 689b ldr r3, [r3, #8]
800332a: f003 0301 and.w r3, r3, #1
800332e: 2b01 cmp r3, #1
8003330: d10d bne.n 800334e <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003332: 687b ldr r3, [r7, #4]
8003334: 6a9b ldr r3, [r3, #40] @ 0x28
8003336: f043 0210 orr.w r2, r3, #16
800333a: 687b ldr r3, [r7, #4]
800333c: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800333e: 687b ldr r3, [r7, #4]
8003340: 6adb ldr r3, [r3, #44] @ 0x2c
8003342: f043 0201 orr.w r2, r3, #1
8003346: 687b ldr r3, [r7, #4]
8003348: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
800334a: 2301 movs r3, #1
800334c: e007 b.n 800335e <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
800334e: 687b ldr r3, [r7, #4]
8003350: 681b ldr r3, [r3, #0]
8003352: 689b ldr r3, [r3, #8]
8003354: f003 0301 and.w r3, r3, #1
8003358: 2b01 cmp r3, #1
800335a: d0dc beq.n 8003316 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
800335c: 2300 movs r3, #0
}
800335e: 4618 mov r0, r3
8003360: 3710 adds r7, #16
8003362: 46bd mov sp, r7
8003364: bd80 pop {r7, pc}
...
08003368 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003368: b480 push {r7}
800336a: b085 sub sp, #20
800336c: af00 add r7, sp, #0
800336e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003370: 687b ldr r3, [r7, #4]
8003372: f003 0307 and.w r3, r3, #7
8003376: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003378: 4b0c ldr r3, [pc, #48] @ (80033ac <__NVIC_SetPriorityGrouping+0x44>)
800337a: 68db ldr r3, [r3, #12]
800337c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800337e: 68ba ldr r2, [r7, #8]
8003380: f64f 03ff movw r3, #63743 @ 0xf8ff
8003384: 4013 ands r3, r2
8003386: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003388: 68fb ldr r3, [r7, #12]
800338a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800338c: 68bb ldr r3, [r7, #8]
800338e: 4313 orrs r3, r2
reg_value = (reg_value |
8003390: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003394: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003398: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800339a: 4a04 ldr r2, [pc, #16] @ (80033ac <__NVIC_SetPriorityGrouping+0x44>)
800339c: 68bb ldr r3, [r7, #8]
800339e: 60d3 str r3, [r2, #12]
}
80033a0: bf00 nop
80033a2: 3714 adds r7, #20
80033a4: 46bd mov sp, r7
80033a6: bc80 pop {r7}
80033a8: 4770 bx lr
80033aa: bf00 nop
80033ac: e000ed00 .word 0xe000ed00
080033b0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80033b0: b480 push {r7}
80033b2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80033b4: 4b04 ldr r3, [pc, #16] @ (80033c8 <__NVIC_GetPriorityGrouping+0x18>)
80033b6: 68db ldr r3, [r3, #12]
80033b8: 0a1b lsrs r3, r3, #8
80033ba: f003 0307 and.w r3, r3, #7
}
80033be: 4618 mov r0, r3
80033c0: 46bd mov sp, r7
80033c2: bc80 pop {r7}
80033c4: 4770 bx lr
80033c6: bf00 nop
80033c8: e000ed00 .word 0xe000ed00
080033cc <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80033cc: b480 push {r7}
80033ce: b083 sub sp, #12
80033d0: af00 add r7, sp, #0
80033d2: 4603 mov r3, r0
80033d4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80033d6: f997 3007 ldrsb.w r3, [r7, #7]
80033da: 2b00 cmp r3, #0
80033dc: db0b blt.n 80033f6 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80033de: 79fb ldrb r3, [r7, #7]
80033e0: f003 021f and.w r2, r3, #31
80033e4: 4906 ldr r1, [pc, #24] @ (8003400 <__NVIC_EnableIRQ+0x34>)
80033e6: f997 3007 ldrsb.w r3, [r7, #7]
80033ea: 095b lsrs r3, r3, #5
80033ec: 2001 movs r0, #1
80033ee: fa00 f202 lsl.w r2, r0, r2
80033f2: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80033f6: bf00 nop
80033f8: 370c adds r7, #12
80033fa: 46bd mov sp, r7
80033fc: bc80 pop {r7}
80033fe: 4770 bx lr
8003400: e000e100 .word 0xe000e100
08003404 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003404: b480 push {r7}
8003406: b083 sub sp, #12
8003408: af00 add r7, sp, #0
800340a: 4603 mov r3, r0
800340c: 6039 str r1, [r7, #0]
800340e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003410: f997 3007 ldrsb.w r3, [r7, #7]
8003414: 2b00 cmp r3, #0
8003416: db0a blt.n 800342e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003418: 683b ldr r3, [r7, #0]
800341a: b2da uxtb r2, r3
800341c: 490c ldr r1, [pc, #48] @ (8003450 <__NVIC_SetPriority+0x4c>)
800341e: f997 3007 ldrsb.w r3, [r7, #7]
8003422: 0112 lsls r2, r2, #4
8003424: b2d2 uxtb r2, r2
8003426: 440b add r3, r1
8003428: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800342c: e00a b.n 8003444 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800342e: 683b ldr r3, [r7, #0]
8003430: b2da uxtb r2, r3
8003432: 4908 ldr r1, [pc, #32] @ (8003454 <__NVIC_SetPriority+0x50>)
8003434: 79fb ldrb r3, [r7, #7]
8003436: f003 030f and.w r3, r3, #15
800343a: 3b04 subs r3, #4
800343c: 0112 lsls r2, r2, #4
800343e: b2d2 uxtb r2, r2
8003440: 440b add r3, r1
8003442: 761a strb r2, [r3, #24]
}
8003444: bf00 nop
8003446: 370c adds r7, #12
8003448: 46bd mov sp, r7
800344a: bc80 pop {r7}
800344c: 4770 bx lr
800344e: bf00 nop
8003450: e000e100 .word 0xe000e100
8003454: e000ed00 .word 0xe000ed00
08003458 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003458: b480 push {r7}
800345a: b089 sub sp, #36 @ 0x24
800345c: af00 add r7, sp, #0
800345e: 60f8 str r0, [r7, #12]
8003460: 60b9 str r1, [r7, #8]
8003462: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003464: 68fb ldr r3, [r7, #12]
8003466: f003 0307 and.w r3, r3, #7
800346a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800346c: 69fb ldr r3, [r7, #28]
800346e: f1c3 0307 rsb r3, r3, #7
8003472: 2b04 cmp r3, #4
8003474: bf28 it cs
8003476: 2304 movcs r3, #4
8003478: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800347a: 69fb ldr r3, [r7, #28]
800347c: 3304 adds r3, #4
800347e: 2b06 cmp r3, #6
8003480: d902 bls.n 8003488 <NVIC_EncodePriority+0x30>
8003482: 69fb ldr r3, [r7, #28]
8003484: 3b03 subs r3, #3
8003486: e000 b.n 800348a <NVIC_EncodePriority+0x32>
8003488: 2300 movs r3, #0
800348a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800348c: f04f 32ff mov.w r2, #4294967295
8003490: 69bb ldr r3, [r7, #24]
8003492: fa02 f303 lsl.w r3, r2, r3
8003496: 43da mvns r2, r3
8003498: 68bb ldr r3, [r7, #8]
800349a: 401a ands r2, r3
800349c: 697b ldr r3, [r7, #20]
800349e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80034a0: f04f 31ff mov.w r1, #4294967295
80034a4: 697b ldr r3, [r7, #20]
80034a6: fa01 f303 lsl.w r3, r1, r3
80034aa: 43d9 mvns r1, r3
80034ac: 687b ldr r3, [r7, #4]
80034ae: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80034b0: 4313 orrs r3, r2
);
}
80034b2: 4618 mov r0, r3
80034b4: 3724 adds r7, #36 @ 0x24
80034b6: 46bd mov sp, r7
80034b8: bc80 pop {r7}
80034ba: 4770 bx lr
080034bc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80034bc: b580 push {r7, lr}
80034be: b082 sub sp, #8
80034c0: af00 add r7, sp, #0
80034c2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80034c4: 687b ldr r3, [r7, #4]
80034c6: 3b01 subs r3, #1
80034c8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80034cc: d301 bcc.n 80034d2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80034ce: 2301 movs r3, #1
80034d0: e00f b.n 80034f2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80034d2: 4a0a ldr r2, [pc, #40] @ (80034fc <SysTick_Config+0x40>)
80034d4: 687b ldr r3, [r7, #4]
80034d6: 3b01 subs r3, #1
80034d8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80034da: 210f movs r1, #15
80034dc: f04f 30ff mov.w r0, #4294967295
80034e0: f7ff ff90 bl 8003404 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80034e4: 4b05 ldr r3, [pc, #20] @ (80034fc <SysTick_Config+0x40>)
80034e6: 2200 movs r2, #0
80034e8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80034ea: 4b04 ldr r3, [pc, #16] @ (80034fc <SysTick_Config+0x40>)
80034ec: 2207 movs r2, #7
80034ee: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80034f0: 2300 movs r3, #0
}
80034f2: 4618 mov r0, r3
80034f4: 3708 adds r7, #8
80034f6: 46bd mov sp, r7
80034f8: bd80 pop {r7, pc}
80034fa: bf00 nop
80034fc: e000e010 .word 0xe000e010
08003500 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003500: b580 push {r7, lr}
8003502: b082 sub sp, #8
8003504: af00 add r7, sp, #0
8003506: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003508: 6878 ldr r0, [r7, #4]
800350a: f7ff ff2d bl 8003368 <__NVIC_SetPriorityGrouping>
}
800350e: bf00 nop
8003510: 3708 adds r7, #8
8003512: 46bd mov sp, r7
8003514: bd80 pop {r7, pc}
08003516 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003516: b580 push {r7, lr}
8003518: b086 sub sp, #24
800351a: af00 add r7, sp, #0
800351c: 4603 mov r3, r0
800351e: 60b9 str r1, [r7, #8]
8003520: 607a str r2, [r7, #4]
8003522: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8003524: 2300 movs r3, #0
8003526: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003528: f7ff ff42 bl 80033b0 <__NVIC_GetPriorityGrouping>
800352c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800352e: 687a ldr r2, [r7, #4]
8003530: 68b9 ldr r1, [r7, #8]
8003532: 6978 ldr r0, [r7, #20]
8003534: f7ff ff90 bl 8003458 <NVIC_EncodePriority>
8003538: 4602 mov r2, r0
800353a: f997 300f ldrsb.w r3, [r7, #15]
800353e: 4611 mov r1, r2
8003540: 4618 mov r0, r3
8003542: f7ff ff5f bl 8003404 <__NVIC_SetPriority>
}
8003546: bf00 nop
8003548: 3718 adds r7, #24
800354a: 46bd mov sp, r7
800354c: bd80 pop {r7, pc}
0800354e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800354e: b580 push {r7, lr}
8003550: b082 sub sp, #8
8003552: af00 add r7, sp, #0
8003554: 4603 mov r3, r0
8003556: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003558: f997 3007 ldrsb.w r3, [r7, #7]
800355c: 4618 mov r0, r3
800355e: f7ff ff35 bl 80033cc <__NVIC_EnableIRQ>
}
8003562: bf00 nop
8003564: 3708 adds r7, #8
8003566: 46bd mov sp, r7
8003568: bd80 pop {r7, pc}
0800356a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800356a: b580 push {r7, lr}
800356c: b082 sub sp, #8
800356e: af00 add r7, sp, #0
8003570: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003572: 6878 ldr r0, [r7, #4]
8003574: f7ff ffa2 bl 80034bc <SysTick_Config>
8003578: 4603 mov r3, r0
}
800357a: 4618 mov r0, r3
800357c: 3708 adds r7, #8
800357e: 46bd mov sp, r7
8003580: bd80 pop {r7, pc}
08003582 <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003582: b480 push {r7}
8003584: b085 sub sp, #20
8003586: af00 add r7, sp, #0
8003588: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800358a: 2300 movs r3, #0
800358c: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
800358e: 687b ldr r3, [r7, #4]
8003590: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003594: b2db uxtb r3, r3
8003596: 2b02 cmp r3, #2
8003598: d008 beq.n 80035ac <HAL_DMA_Abort+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800359a: 687b ldr r3, [r7, #4]
800359c: 2204 movs r2, #4
800359e: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80035a0: 687b ldr r3, [r7, #4]
80035a2: 2200 movs r2, #0
80035a4: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
80035a8: 2301 movs r3, #1
80035aa: e020 b.n 80035ee <HAL_DMA_Abort+0x6c>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80035ac: 687b ldr r3, [r7, #4]
80035ae: 681b ldr r3, [r3, #0]
80035b0: 681a ldr r2, [r3, #0]
80035b2: 687b ldr r3, [r7, #4]
80035b4: 681b ldr r3, [r3, #0]
80035b6: f022 020e bic.w r2, r2, #14
80035ba: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80035bc: 687b ldr r3, [r7, #4]
80035be: 681b ldr r3, [r3, #0]
80035c0: 681a ldr r2, [r3, #0]
80035c2: 687b ldr r3, [r7, #4]
80035c4: 681b ldr r3, [r3, #0]
80035c6: f022 0201 bic.w r2, r2, #1
80035ca: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
80035cc: 687b ldr r3, [r7, #4]
80035ce: 6c1a ldr r2, [r3, #64] @ 0x40
80035d0: 687b ldr r3, [r7, #4]
80035d2: 6bdb ldr r3, [r3, #60] @ 0x3c
80035d4: 2101 movs r1, #1
80035d6: fa01 f202 lsl.w r2, r1, r2
80035da: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80035dc: 687b ldr r3, [r7, #4]
80035de: 2201 movs r2, #1
80035e0: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80035e4: 687b ldr r3, [r7, #4]
80035e6: 2200 movs r2, #0
80035e8: f883 2020 strb.w r2, [r3, #32]
return status;
80035ec: 7bfb ldrb r3, [r7, #15]
}
80035ee: 4618 mov r0, r3
80035f0: 3714 adds r7, #20
80035f2: 46bd mov sp, r7
80035f4: bc80 pop {r7}
80035f6: 4770 bx lr
080035f8 <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
80035f8: b580 push {r7, lr}
80035fa: b084 sub sp, #16
80035fc: af00 add r7, sp, #0
80035fe: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003600: 2300 movs r3, #0
8003602: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8003604: 687b ldr r3, [r7, #4]
8003606: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
800360a: b2db uxtb r3, r3
800360c: 2b02 cmp r3, #2
800360e: d005 beq.n 800361c <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003610: 687b ldr r3, [r7, #4]
8003612: 2204 movs r2, #4
8003614: 639a str r2, [r3, #56] @ 0x38
status = HAL_ERROR;
8003616: 2301 movs r3, #1
8003618: 73fb strb r3, [r7, #15]
800361a: e051 b.n 80036c0 <HAL_DMA_Abort_IT+0xc8>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800361c: 687b ldr r3, [r7, #4]
800361e: 681b ldr r3, [r3, #0]
8003620: 681a ldr r2, [r3, #0]
8003622: 687b ldr r3, [r7, #4]
8003624: 681b ldr r3, [r3, #0]
8003626: f022 020e bic.w r2, r2, #14
800362a: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800362c: 687b ldr r3, [r7, #4]
800362e: 681b ldr r3, [r3, #0]
8003630: 681a ldr r2, [r3, #0]
8003632: 687b ldr r3, [r7, #4]
8003634: 681b ldr r3, [r3, #0]
8003636: f022 0201 bic.w r2, r2, #1
800363a: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
800363c: 687b ldr r3, [r7, #4]
800363e: 681b ldr r3, [r3, #0]
8003640: 4a22 ldr r2, [pc, #136] @ (80036cc <HAL_DMA_Abort_IT+0xd4>)
8003642: 4293 cmp r3, r2
8003644: d029 beq.n 800369a <HAL_DMA_Abort_IT+0xa2>
8003646: 687b ldr r3, [r7, #4]
8003648: 681b ldr r3, [r3, #0]
800364a: 4a21 ldr r2, [pc, #132] @ (80036d0 <HAL_DMA_Abort_IT+0xd8>)
800364c: 4293 cmp r3, r2
800364e: d022 beq.n 8003696 <HAL_DMA_Abort_IT+0x9e>
8003650: 687b ldr r3, [r7, #4]
8003652: 681b ldr r3, [r3, #0]
8003654: 4a1f ldr r2, [pc, #124] @ (80036d4 <HAL_DMA_Abort_IT+0xdc>)
8003656: 4293 cmp r3, r2
8003658: d01a beq.n 8003690 <HAL_DMA_Abort_IT+0x98>
800365a: 687b ldr r3, [r7, #4]
800365c: 681b ldr r3, [r3, #0]
800365e: 4a1e ldr r2, [pc, #120] @ (80036d8 <HAL_DMA_Abort_IT+0xe0>)
8003660: 4293 cmp r3, r2
8003662: d012 beq.n 800368a <HAL_DMA_Abort_IT+0x92>
8003664: 687b ldr r3, [r7, #4]
8003666: 681b ldr r3, [r3, #0]
8003668: 4a1c ldr r2, [pc, #112] @ (80036dc <HAL_DMA_Abort_IT+0xe4>)
800366a: 4293 cmp r3, r2
800366c: d00a beq.n 8003684 <HAL_DMA_Abort_IT+0x8c>
800366e: 687b ldr r3, [r7, #4]
8003670: 681b ldr r3, [r3, #0]
8003672: 4a1b ldr r2, [pc, #108] @ (80036e0 <HAL_DMA_Abort_IT+0xe8>)
8003674: 4293 cmp r3, r2
8003676: d102 bne.n 800367e <HAL_DMA_Abort_IT+0x86>
8003678: f44f 1380 mov.w r3, #1048576 @ 0x100000
800367c: e00e b.n 800369c <HAL_DMA_Abort_IT+0xa4>
800367e: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8003682: e00b b.n 800369c <HAL_DMA_Abort_IT+0xa4>
8003684: f44f 3380 mov.w r3, #65536 @ 0x10000
8003688: e008 b.n 800369c <HAL_DMA_Abort_IT+0xa4>
800368a: f44f 5380 mov.w r3, #4096 @ 0x1000
800368e: e005 b.n 800369c <HAL_DMA_Abort_IT+0xa4>
8003690: f44f 7380 mov.w r3, #256 @ 0x100
8003694: e002 b.n 800369c <HAL_DMA_Abort_IT+0xa4>
8003696: 2310 movs r3, #16
8003698: e000 b.n 800369c <HAL_DMA_Abort_IT+0xa4>
800369a: 2301 movs r3, #1
800369c: 4a11 ldr r2, [pc, #68] @ (80036e4 <HAL_DMA_Abort_IT+0xec>)
800369e: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80036a0: 687b ldr r3, [r7, #4]
80036a2: 2201 movs r2, #1
80036a4: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80036a8: 687b ldr r3, [r7, #4]
80036aa: 2200 movs r2, #0
80036ac: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
80036b0: 687b ldr r3, [r7, #4]
80036b2: 6b5b ldr r3, [r3, #52] @ 0x34
80036b4: 2b00 cmp r3, #0
80036b6: d003 beq.n 80036c0 <HAL_DMA_Abort_IT+0xc8>
{
hdma->XferAbortCallback(hdma);
80036b8: 687b ldr r3, [r7, #4]
80036ba: 6b5b ldr r3, [r3, #52] @ 0x34
80036bc: 6878 ldr r0, [r7, #4]
80036be: 4798 blx r3
}
}
return status;
80036c0: 7bfb ldrb r3, [r7, #15]
}
80036c2: 4618 mov r0, r3
80036c4: 3710 adds r7, #16
80036c6: 46bd mov sp, r7
80036c8: bd80 pop {r7, pc}
80036ca: bf00 nop
80036cc: 40020008 .word 0x40020008
80036d0: 4002001c .word 0x4002001c
80036d4: 40020030 .word 0x40020030
80036d8: 40020044 .word 0x40020044
80036dc: 40020058 .word 0x40020058
80036e0: 4002006c .word 0x4002006c
80036e4: 40020000 .word 0x40020000
080036e8 <HAL_FLASH_Program>:
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
80036e8: b5f0 push {r4, r5, r6, r7, lr}
80036ea: b087 sub sp, #28
80036ec: af00 add r7, sp, #0
80036ee: 60f8 str r0, [r7, #12]
80036f0: 60b9 str r1, [r7, #8]
80036f2: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
80036f6: 2301 movs r3, #1
80036f8: 75fb strb r3, [r7, #23]
uint8_t index = 0;
80036fa: 2300 movs r3, #0
80036fc: 75bb strb r3, [r7, #22]
uint8_t nbiterations = 0;
80036fe: 2300 movs r3, #0
8003700: 757b strb r3, [r7, #21]
/* Process Locked */
__HAL_LOCK(&pFlash);
8003702: 4b2f ldr r3, [pc, #188] @ (80037c0 <HAL_FLASH_Program+0xd8>)
8003704: 7e1b ldrb r3, [r3, #24]
8003706: 2b01 cmp r3, #1
8003708: d101 bne.n 800370e <HAL_FLASH_Program+0x26>
800370a: 2302 movs r3, #2
800370c: e054 b.n 80037b8 <HAL_FLASH_Program+0xd0>
800370e: 4b2c ldr r3, [pc, #176] @ (80037c0 <HAL_FLASH_Program+0xd8>)
8003710: 2201 movs r2, #1
8003712: 761a strb r2, [r3, #24]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8003714: f24c 3050 movw r0, #50000 @ 0xc350
8003718: f000 f8a8 bl 800386c <FLASH_WaitForLastOperation>
800371c: 4603 mov r3, r0
800371e: 75fb strb r3, [r7, #23]
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
8003720: 7dfb ldrb r3, [r7, #23]
8003722: 2b00 cmp r3, #0
8003724: d144 bne.n 80037b0 <HAL_FLASH_Program+0xc8>
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
8003726: 68fb ldr r3, [r7, #12]
8003728: 2b01 cmp r3, #1
800372a: d102 bne.n 8003732 <HAL_FLASH_Program+0x4a>
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
800372c: 2301 movs r3, #1
800372e: 757b strb r3, [r7, #21]
8003730: e007 b.n 8003742 <HAL_FLASH_Program+0x5a>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
8003732: 68fb ldr r3, [r7, #12]
8003734: 2b02 cmp r3, #2
8003736: d102 bne.n 800373e <HAL_FLASH_Program+0x56>
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
8003738: 2302 movs r3, #2
800373a: 757b strb r3, [r7, #21]
800373c: e001 b.n 8003742 <HAL_FLASH_Program+0x5a>
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
800373e: 2304 movs r3, #4
8003740: 757b strb r3, [r7, #21]
}
for (index = 0U; index < nbiterations; index++)
8003742: 2300 movs r3, #0
8003744: 75bb strb r3, [r7, #22]
8003746: e02d b.n 80037a4 <HAL_FLASH_Program+0xbc>
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
8003748: 7dbb ldrb r3, [r7, #22]
800374a: 005a lsls r2, r3, #1
800374c: 68bb ldr r3, [r7, #8]
800374e: eb02 0c03 add.w ip, r2, r3
8003752: 7dbb ldrb r3, [r7, #22]
8003754: 0119 lsls r1, r3, #4
8003756: e9d7 2300 ldrd r2, r3, [r7]
800375a: f1c1 0620 rsb r6, r1, #32
800375e: f1a1 0020 sub.w r0, r1, #32
8003762: fa22 f401 lsr.w r4, r2, r1
8003766: fa03 f606 lsl.w r6, r3, r6
800376a: 4334 orrs r4, r6
800376c: fa23 f000 lsr.w r0, r3, r0
8003770: 4304 orrs r4, r0
8003772: fa23 f501 lsr.w r5, r3, r1
8003776: b2a3 uxth r3, r4
8003778: 4619 mov r1, r3
800377a: 4660 mov r0, ip
800377c: f000 f85a bl 8003834 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8003780: f24c 3050 movw r0, #50000 @ 0xc350
8003784: f000 f872 bl 800386c <FLASH_WaitForLastOperation>
8003788: 4603 mov r3, r0
800378a: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
800378c: 4b0d ldr r3, [pc, #52] @ (80037c4 <HAL_FLASH_Program+0xdc>)
800378e: 691b ldr r3, [r3, #16]
8003790: 4a0c ldr r2, [pc, #48] @ (80037c4 <HAL_FLASH_Program+0xdc>)
8003792: f023 0301 bic.w r3, r3, #1
8003796: 6113 str r3, [r2, #16]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
8003798: 7dfb ldrb r3, [r7, #23]
800379a: 2b00 cmp r3, #0
800379c: d107 bne.n 80037ae <HAL_FLASH_Program+0xc6>
for (index = 0U; index < nbiterations; index++)
800379e: 7dbb ldrb r3, [r7, #22]
80037a0: 3301 adds r3, #1
80037a2: 75bb strb r3, [r7, #22]
80037a4: 7dba ldrb r2, [r7, #22]
80037a6: 7d7b ldrb r3, [r7, #21]
80037a8: 429a cmp r2, r3
80037aa: d3cd bcc.n 8003748 <HAL_FLASH_Program+0x60>
80037ac: e000 b.n 80037b0 <HAL_FLASH_Program+0xc8>
{
break;
80037ae: bf00 nop
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
80037b0: 4b03 ldr r3, [pc, #12] @ (80037c0 <HAL_FLASH_Program+0xd8>)
80037b2: 2200 movs r2, #0
80037b4: 761a strb r2, [r3, #24]
return status;
80037b6: 7dfb ldrb r3, [r7, #23]
}
80037b8: 4618 mov r0, r3
80037ba: 371c adds r7, #28
80037bc: 46bd mov sp, r7
80037be: bdf0 pop {r4, r5, r6, r7, pc}
80037c0: 20000768 .word 0x20000768
80037c4: 40022000 .word 0x40022000
080037c8 <HAL_FLASH_Unlock>:
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
80037c8: b480 push {r7}
80037ca: b083 sub sp, #12
80037cc: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
80037ce: 2300 movs r3, #0
80037d0: 71fb strb r3, [r7, #7]
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
80037d2: 4b0d ldr r3, [pc, #52] @ (8003808 <HAL_FLASH_Unlock+0x40>)
80037d4: 691b ldr r3, [r3, #16]
80037d6: f003 0380 and.w r3, r3, #128 @ 0x80
80037da: 2b00 cmp r3, #0
80037dc: d00d beq.n 80037fa <HAL_FLASH_Unlock+0x32>
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
80037de: 4b0a ldr r3, [pc, #40] @ (8003808 <HAL_FLASH_Unlock+0x40>)
80037e0: 4a0a ldr r2, [pc, #40] @ (800380c <HAL_FLASH_Unlock+0x44>)
80037e2: 605a str r2, [r3, #4]
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
80037e4: 4b08 ldr r3, [pc, #32] @ (8003808 <HAL_FLASH_Unlock+0x40>)
80037e6: 4a0a ldr r2, [pc, #40] @ (8003810 <HAL_FLASH_Unlock+0x48>)
80037e8: 605a str r2, [r3, #4]
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
80037ea: 4b07 ldr r3, [pc, #28] @ (8003808 <HAL_FLASH_Unlock+0x40>)
80037ec: 691b ldr r3, [r3, #16]
80037ee: f003 0380 and.w r3, r3, #128 @ 0x80
80037f2: 2b00 cmp r3, #0
80037f4: d001 beq.n 80037fa <HAL_FLASH_Unlock+0x32>
{
status = HAL_ERROR;
80037f6: 2301 movs r3, #1
80037f8: 71fb strb r3, [r7, #7]
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
80037fa: 79fb ldrb r3, [r7, #7]
}
80037fc: 4618 mov r0, r3
80037fe: 370c adds r7, #12
8003800: 46bd mov sp, r7
8003802: bc80 pop {r7}
8003804: 4770 bx lr
8003806: bf00 nop
8003808: 40022000 .word 0x40022000
800380c: 45670123 .word 0x45670123
8003810: cdef89ab .word 0xcdef89ab
08003814 <HAL_FLASH_Lock>:
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
8003814: b480 push {r7}
8003816: af00 add r7, sp, #0
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
8003818: 4b05 ldr r3, [pc, #20] @ (8003830 <HAL_FLASH_Lock+0x1c>)
800381a: 691b ldr r3, [r3, #16]
800381c: 4a04 ldr r2, [pc, #16] @ (8003830 <HAL_FLASH_Lock+0x1c>)
800381e: f043 0380 orr.w r3, r3, #128 @ 0x80
8003822: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
8003824: 2300 movs r3, #0
}
8003826: 4618 mov r0, r3
8003828: 46bd mov sp, r7
800382a: bc80 pop {r7}
800382c: 4770 bx lr
800382e: bf00 nop
8003830: 40022000 .word 0x40022000
08003834 <FLASH_Program_HalfWord>:
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
8003834: b480 push {r7}
8003836: b083 sub sp, #12
8003838: af00 add r7, sp, #0
800383a: 6078 str r0, [r7, #4]
800383c: 460b mov r3, r1
800383e: 807b strh r3, [r7, #2]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003840: 4b08 ldr r3, [pc, #32] @ (8003864 <FLASH_Program_HalfWord+0x30>)
8003842: 2200 movs r2, #0
8003844: 61da str r2, [r3, #28]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
8003846: 4b08 ldr r3, [pc, #32] @ (8003868 <FLASH_Program_HalfWord+0x34>)
8003848: 691b ldr r3, [r3, #16]
800384a: 4a07 ldr r2, [pc, #28] @ (8003868 <FLASH_Program_HalfWord+0x34>)
800384c: f043 0301 orr.w r3, r3, #1
8003850: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
8003852: 687b ldr r3, [r7, #4]
8003854: 887a ldrh r2, [r7, #2]
8003856: 801a strh r2, [r3, #0]
}
8003858: bf00 nop
800385a: 370c adds r7, #12
800385c: 46bd mov sp, r7
800385e: bc80 pop {r7}
8003860: 4770 bx lr
8003862: bf00 nop
8003864: 20000768 .word 0x20000768
8003868: 40022000 .word 0x40022000
0800386c <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
800386c: b580 push {r7, lr}
800386e: b084 sub sp, #16
8003870: af00 add r7, sp, #0
8003872: 6078 str r0, [r7, #4]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
8003874: f7ff fb38 bl 8002ee8 <HAL_GetTick>
8003878: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
800387a: e010 b.n 800389e <FLASH_WaitForLastOperation+0x32>
{
if (Timeout != HAL_MAX_DELAY)
800387c: 687b ldr r3, [r7, #4]
800387e: f1b3 3fff cmp.w r3, #4294967295
8003882: d00c beq.n 800389e <FLASH_WaitForLastOperation+0x32>
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
8003884: 687b ldr r3, [r7, #4]
8003886: 2b00 cmp r3, #0
8003888: d007 beq.n 800389a <FLASH_WaitForLastOperation+0x2e>
800388a: f7ff fb2d bl 8002ee8 <HAL_GetTick>
800388e: 4602 mov r2, r0
8003890: 68fb ldr r3, [r7, #12]
8003892: 1ad3 subs r3, r2, r3
8003894: 687a ldr r2, [r7, #4]
8003896: 429a cmp r2, r3
8003898: d201 bcs.n 800389e <FLASH_WaitForLastOperation+0x32>
{
return HAL_TIMEOUT;
800389a: 2303 movs r3, #3
800389c: e025 b.n 80038ea <FLASH_WaitForLastOperation+0x7e>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
800389e: 4b15 ldr r3, [pc, #84] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038a0: 68db ldr r3, [r3, #12]
80038a2: f003 0301 and.w r3, r3, #1
80038a6: 2b00 cmp r3, #0
80038a8: d1e8 bne.n 800387c <FLASH_WaitForLastOperation+0x10>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
80038aa: 4b12 ldr r3, [pc, #72] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038ac: 68db ldr r3, [r3, #12]
80038ae: f003 0320 and.w r3, r3, #32
80038b2: 2b00 cmp r3, #0
80038b4: d002 beq.n 80038bc <FLASH_WaitForLastOperation+0x50>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
80038b6: 4b0f ldr r3, [pc, #60] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038b8: 2220 movs r2, #32
80038ba: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
80038bc: 4b0d ldr r3, [pc, #52] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038be: 68db ldr r3, [r3, #12]
80038c0: f003 0310 and.w r3, r3, #16
80038c4: 2b00 cmp r3, #0
80038c6: d10b bne.n 80038e0 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
80038c8: 4b0a ldr r3, [pc, #40] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038ca: 69db ldr r3, [r3, #28]
80038cc: f003 0301 and.w r3, r3, #1
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
80038d0: 2b00 cmp r3, #0
80038d2: d105 bne.n 80038e0 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
80038d4: 4b07 ldr r3, [pc, #28] @ (80038f4 <FLASH_WaitForLastOperation+0x88>)
80038d6: 68db ldr r3, [r3, #12]
80038d8: f003 0304 and.w r3, r3, #4
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
80038dc: 2b00 cmp r3, #0
80038de: d003 beq.n 80038e8 <FLASH_WaitForLastOperation+0x7c>
{
/*Save the error code*/
FLASH_SetErrorCode();
80038e0: f000 f80a bl 80038f8 <FLASH_SetErrorCode>
return HAL_ERROR;
80038e4: 2301 movs r3, #1
80038e6: e000 b.n 80038ea <FLASH_WaitForLastOperation+0x7e>
}
/* There is no error flag set */
return HAL_OK;
80038e8: 2300 movs r3, #0
}
80038ea: 4618 mov r0, r3
80038ec: 3710 adds r7, #16
80038ee: 46bd mov sp, r7
80038f0: bd80 pop {r7, pc}
80038f2: bf00 nop
80038f4: 40022000 .word 0x40022000
080038f8 <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
80038f8: b480 push {r7}
80038fa: b083 sub sp, #12
80038fc: af00 add r7, sp, #0
uint32_t flags = 0U;
80038fe: 2300 movs r3, #0
8003900: 607b str r3, [r7, #4]
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
8003902: 4b23 ldr r3, [pc, #140] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003904: 68db ldr r3, [r3, #12]
8003906: f003 0310 and.w r3, r3, #16
800390a: 2b00 cmp r3, #0
800390c: d009 beq.n 8003922 <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
800390e: 4b21 ldr r3, [pc, #132] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003910: 69db ldr r3, [r3, #28]
8003912: f043 0302 orr.w r3, r3, #2
8003916: 4a1f ldr r2, [pc, #124] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003918: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
800391a: 687b ldr r3, [r7, #4]
800391c: f043 0310 orr.w r3, r3, #16
8003920: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8003922: 4b1b ldr r3, [pc, #108] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003924: 68db ldr r3, [r3, #12]
8003926: f003 0304 and.w r3, r3, #4
800392a: 2b00 cmp r3, #0
800392c: d009 beq.n 8003942 <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
800392e: 4b19 ldr r3, [pc, #100] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003930: 69db ldr r3, [r3, #28]
8003932: f043 0301 orr.w r3, r3, #1
8003936: 4a17 ldr r2, [pc, #92] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003938: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
800393a: 687b ldr r3, [r7, #4]
800393c: f043 0304 orr.w r3, r3, #4
8003940: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
8003942: 4b13 ldr r3, [pc, #76] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003944: 69db ldr r3, [r3, #28]
8003946: f003 0301 and.w r3, r3, #1
800394a: 2b00 cmp r3, #0
800394c: d00b beq.n 8003966 <FLASH_SetErrorCode+0x6e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
800394e: 4b11 ldr r3, [pc, #68] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003950: 69db ldr r3, [r3, #28]
8003952: f043 0304 orr.w r3, r3, #4
8003956: 4a0f ldr r2, [pc, #60] @ (8003994 <FLASH_SetErrorCode+0x9c>)
8003958: 61d3 str r3, [r2, #28]
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
800395a: 4b0d ldr r3, [pc, #52] @ (8003990 <FLASH_SetErrorCode+0x98>)
800395c: 69db ldr r3, [r3, #28]
800395e: 4a0c ldr r2, [pc, #48] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003960: f023 0301 bic.w r3, r3, #1
8003964: 61d3 str r3, [r2, #28]
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
8003966: 687b ldr r3, [r7, #4]
8003968: f240 1201 movw r2, #257 @ 0x101
800396c: 4293 cmp r3, r2
800396e: d106 bne.n 800397e <FLASH_SetErrorCode+0x86>
8003970: 4b07 ldr r3, [pc, #28] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003972: 69db ldr r3, [r3, #28]
8003974: 4a06 ldr r2, [pc, #24] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003976: f023 0301 bic.w r3, r3, #1
800397a: 61d3 str r3, [r2, #28]
}
800397c: e002 b.n 8003984 <FLASH_SetErrorCode+0x8c>
__HAL_FLASH_CLEAR_FLAG(flags);
800397e: 4a04 ldr r2, [pc, #16] @ (8003990 <FLASH_SetErrorCode+0x98>)
8003980: 687b ldr r3, [r7, #4]
8003982: 60d3 str r3, [r2, #12]
}
8003984: bf00 nop
8003986: 370c adds r7, #12
8003988: 46bd mov sp, r7
800398a: bc80 pop {r7}
800398c: 4770 bx lr
800398e: bf00 nop
8003990: 40022000 .word 0x40022000
8003994: 20000768 .word 0x20000768
08003998 <HAL_FLASHEx_Erase>:
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
8003998: b580 push {r7, lr}
800399a: b084 sub sp, #16
800399c: af00 add r7, sp, #0
800399e: 6078 str r0, [r7, #4]
80039a0: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
80039a2: 2301 movs r3, #1
80039a4: 73fb strb r3, [r7, #15]
uint32_t address = 0U;
80039a6: 2300 movs r3, #0
80039a8: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
80039aa: 4b2f ldr r3, [pc, #188] @ (8003a68 <HAL_FLASHEx_Erase+0xd0>)
80039ac: 7e1b ldrb r3, [r3, #24]
80039ae: 2b01 cmp r3, #1
80039b0: d101 bne.n 80039b6 <HAL_FLASHEx_Erase+0x1e>
80039b2: 2302 movs r3, #2
80039b4: e053 b.n 8003a5e <HAL_FLASHEx_Erase+0xc6>
80039b6: 4b2c ldr r3, [pc, #176] @ (8003a68 <HAL_FLASHEx_Erase+0xd0>)
80039b8: 2201 movs r2, #1
80039ba: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
80039bc: 687b ldr r3, [r7, #4]
80039be: 681b ldr r3, [r3, #0]
80039c0: 2b02 cmp r3, #2
80039c2: d116 bne.n 80039f2 <HAL_FLASHEx_Erase+0x5a>
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
80039c4: f24c 3050 movw r0, #50000 @ 0xc350
80039c8: f7ff ff50 bl 800386c <FLASH_WaitForLastOperation>
80039cc: 4603 mov r3, r0
80039ce: 2b00 cmp r3, #0
80039d0: d141 bne.n 8003a56 <HAL_FLASHEx_Erase+0xbe>
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
80039d2: 2001 movs r0, #1
80039d4: f000 f84c bl 8003a70 <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
80039d8: f24c 3050 movw r0, #50000 @ 0xc350
80039dc: f7ff ff46 bl 800386c <FLASH_WaitForLastOperation>
80039e0: 4603 mov r3, r0
80039e2: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
80039e4: 4b21 ldr r3, [pc, #132] @ (8003a6c <HAL_FLASHEx_Erase+0xd4>)
80039e6: 691b ldr r3, [r3, #16]
80039e8: 4a20 ldr r2, [pc, #128] @ (8003a6c <HAL_FLASHEx_Erase+0xd4>)
80039ea: f023 0304 bic.w r3, r3, #4
80039ee: 6113 str r3, [r2, #16]
80039f0: e031 b.n 8003a56 <HAL_FLASHEx_Erase+0xbe>
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
80039f2: f24c 3050 movw r0, #50000 @ 0xc350
80039f6: f7ff ff39 bl 800386c <FLASH_WaitForLastOperation>
80039fa: 4603 mov r3, r0
80039fc: 2b00 cmp r3, #0
80039fe: d12a bne.n 8003a56 <HAL_FLASHEx_Erase+0xbe>
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
8003a00: 683b ldr r3, [r7, #0]
8003a02: f04f 32ff mov.w r2, #4294967295
8003a06: 601a str r2, [r3, #0]
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
8003a08: 687b ldr r3, [r7, #4]
8003a0a: 689b ldr r3, [r3, #8]
8003a0c: 60bb str r3, [r7, #8]
8003a0e: e019 b.n 8003a44 <HAL_FLASHEx_Erase+0xac>
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
8003a10: 68b8 ldr r0, [r7, #8]
8003a12: f000 f849 bl 8003aa8 <FLASH_PageErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8003a16: f24c 3050 movw r0, #50000 @ 0xc350
8003a1a: f7ff ff27 bl 800386c <FLASH_WaitForLastOperation>
8003a1e: 4603 mov r3, r0
8003a20: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
8003a22: 4b12 ldr r3, [pc, #72] @ (8003a6c <HAL_FLASHEx_Erase+0xd4>)
8003a24: 691b ldr r3, [r3, #16]
8003a26: 4a11 ldr r2, [pc, #68] @ (8003a6c <HAL_FLASHEx_Erase+0xd4>)
8003a28: f023 0302 bic.w r3, r3, #2
8003a2c: 6113 str r3, [r2, #16]
if (status != HAL_OK)
8003a2e: 7bfb ldrb r3, [r7, #15]
8003a30: 2b00 cmp r3, #0
8003a32: d003 beq.n 8003a3c <HAL_FLASHEx_Erase+0xa4>
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
8003a34: 683b ldr r3, [r7, #0]
8003a36: 68ba ldr r2, [r7, #8]
8003a38: 601a str r2, [r3, #0]
break;
8003a3a: e00c b.n 8003a56 <HAL_FLASHEx_Erase+0xbe>
address += FLASH_PAGE_SIZE)
8003a3c: 68bb ldr r3, [r7, #8]
8003a3e: f503 6380 add.w r3, r3, #1024 @ 0x400
8003a42: 60bb str r3, [r7, #8]
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
8003a44: 687b ldr r3, [r7, #4]
8003a46: 68db ldr r3, [r3, #12]
8003a48: 029a lsls r2, r3, #10
8003a4a: 687b ldr r3, [r7, #4]
8003a4c: 689b ldr r3, [r3, #8]
8003a4e: 4413 add r3, r2
8003a50: 68ba ldr r2, [r7, #8]
8003a52: 429a cmp r2, r3
8003a54: d3dc bcc.n 8003a10 <HAL_FLASHEx_Erase+0x78>
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8003a56: 4b04 ldr r3, [pc, #16] @ (8003a68 <HAL_FLASHEx_Erase+0xd0>)
8003a58: 2200 movs r2, #0
8003a5a: 761a strb r2, [r3, #24]
return status;
8003a5c: 7bfb ldrb r3, [r7, #15]
}
8003a5e: 4618 mov r0, r3
8003a60: 3710 adds r7, #16
8003a62: 46bd mov sp, r7
8003a64: bd80 pop {r7, pc}
8003a66: bf00 nop
8003a68: 20000768 .word 0x20000768
8003a6c: 40022000 .word 0x40022000
08003a70 <FLASH_MassErase>:
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
8003a70: b480 push {r7}
8003a72: b083 sub sp, #12
8003a74: af00 add r7, sp, #0
8003a76: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003a78: 4b09 ldr r3, [pc, #36] @ (8003aa0 <FLASH_MassErase+0x30>)
8003a7a: 2200 movs r2, #0
8003a7c: 61da str r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
8003a7e: 4b09 ldr r3, [pc, #36] @ (8003aa4 <FLASH_MassErase+0x34>)
8003a80: 691b ldr r3, [r3, #16]
8003a82: 4a08 ldr r2, [pc, #32] @ (8003aa4 <FLASH_MassErase+0x34>)
8003a84: f043 0304 orr.w r3, r3, #4
8003a88: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
8003a8a: 4b06 ldr r3, [pc, #24] @ (8003aa4 <FLASH_MassErase+0x34>)
8003a8c: 691b ldr r3, [r3, #16]
8003a8e: 4a05 ldr r2, [pc, #20] @ (8003aa4 <FLASH_MassErase+0x34>)
8003a90: f043 0340 orr.w r3, r3, #64 @ 0x40
8003a94: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8003a96: bf00 nop
8003a98: 370c adds r7, #12
8003a9a: 46bd mov sp, r7
8003a9c: bc80 pop {r7}
8003a9e: 4770 bx lr
8003aa0: 20000768 .word 0x20000768
8003aa4: 40022000 .word 0x40022000
08003aa8 <FLASH_PageErase>:
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
8003aa8: b480 push {r7}
8003aaa: b083 sub sp, #12
8003aac: af00 add r7, sp, #0
8003aae: 6078 str r0, [r7, #4]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003ab0: 4b0b ldr r3, [pc, #44] @ (8003ae0 <FLASH_PageErase+0x38>)
8003ab2: 2200 movs r2, #0
8003ab4: 61da str r2, [r3, #28]
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
8003ab6: 4b0b ldr r3, [pc, #44] @ (8003ae4 <FLASH_PageErase+0x3c>)
8003ab8: 691b ldr r3, [r3, #16]
8003aba: 4a0a ldr r2, [pc, #40] @ (8003ae4 <FLASH_PageErase+0x3c>)
8003abc: f043 0302 orr.w r3, r3, #2
8003ac0: 6113 str r3, [r2, #16]
WRITE_REG(FLASH->AR, PageAddress);
8003ac2: 4a08 ldr r2, [pc, #32] @ (8003ae4 <FLASH_PageErase+0x3c>)
8003ac4: 687b ldr r3, [r7, #4]
8003ac6: 6153 str r3, [r2, #20]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
8003ac8: 4b06 ldr r3, [pc, #24] @ (8003ae4 <FLASH_PageErase+0x3c>)
8003aca: 691b ldr r3, [r3, #16]
8003acc: 4a05 ldr r2, [pc, #20] @ (8003ae4 <FLASH_PageErase+0x3c>)
8003ace: f043 0340 orr.w r3, r3, #64 @ 0x40
8003ad2: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8003ad4: bf00 nop
8003ad6: 370c adds r7, #12
8003ad8: 46bd mov sp, r7
8003ada: bc80 pop {r7}
8003adc: 4770 bx lr
8003ade: bf00 nop
8003ae0: 20000768 .word 0x20000768
8003ae4: 40022000 .word 0x40022000
08003ae8 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003ae8: b480 push {r7}
8003aea: b08b sub sp, #44 @ 0x2c
8003aec: af00 add r7, sp, #0
8003aee: 6078 str r0, [r7, #4]
8003af0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003af2: 2300 movs r3, #0
8003af4: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8003af6: 2300 movs r3, #0
8003af8: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003afa: e169 b.n 8003dd0 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8003afc: 2201 movs r2, #1
8003afe: 6a7b ldr r3, [r7, #36] @ 0x24
8003b00: fa02 f303 lsl.w r3, r2, r3
8003b04: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8003b06: 683b ldr r3, [r7, #0]
8003b08: 681b ldr r3, [r3, #0]
8003b0a: 69fa ldr r2, [r7, #28]
8003b0c: 4013 ands r3, r2
8003b0e: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8003b10: 69ba ldr r2, [r7, #24]
8003b12: 69fb ldr r3, [r7, #28]
8003b14: 429a cmp r2, r3
8003b16: f040 8158 bne.w 8003dca <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8003b1a: 683b ldr r3, [r7, #0]
8003b1c: 685b ldr r3, [r3, #4]
8003b1e: 4a9a ldr r2, [pc, #616] @ (8003d88 <HAL_GPIO_Init+0x2a0>)
8003b20: 4293 cmp r3, r2
8003b22: d05e beq.n 8003be2 <HAL_GPIO_Init+0xfa>
8003b24: 4a98 ldr r2, [pc, #608] @ (8003d88 <HAL_GPIO_Init+0x2a0>)
8003b26: 4293 cmp r3, r2
8003b28: d875 bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b2a: 4a98 ldr r2, [pc, #608] @ (8003d8c <HAL_GPIO_Init+0x2a4>)
8003b2c: 4293 cmp r3, r2
8003b2e: d058 beq.n 8003be2 <HAL_GPIO_Init+0xfa>
8003b30: 4a96 ldr r2, [pc, #600] @ (8003d8c <HAL_GPIO_Init+0x2a4>)
8003b32: 4293 cmp r3, r2
8003b34: d86f bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b36: 4a96 ldr r2, [pc, #600] @ (8003d90 <HAL_GPIO_Init+0x2a8>)
8003b38: 4293 cmp r3, r2
8003b3a: d052 beq.n 8003be2 <HAL_GPIO_Init+0xfa>
8003b3c: 4a94 ldr r2, [pc, #592] @ (8003d90 <HAL_GPIO_Init+0x2a8>)
8003b3e: 4293 cmp r3, r2
8003b40: d869 bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b42: 4a94 ldr r2, [pc, #592] @ (8003d94 <HAL_GPIO_Init+0x2ac>)
8003b44: 4293 cmp r3, r2
8003b46: d04c beq.n 8003be2 <HAL_GPIO_Init+0xfa>
8003b48: 4a92 ldr r2, [pc, #584] @ (8003d94 <HAL_GPIO_Init+0x2ac>)
8003b4a: 4293 cmp r3, r2
8003b4c: d863 bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b4e: 4a92 ldr r2, [pc, #584] @ (8003d98 <HAL_GPIO_Init+0x2b0>)
8003b50: 4293 cmp r3, r2
8003b52: d046 beq.n 8003be2 <HAL_GPIO_Init+0xfa>
8003b54: 4a90 ldr r2, [pc, #576] @ (8003d98 <HAL_GPIO_Init+0x2b0>)
8003b56: 4293 cmp r3, r2
8003b58: d85d bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b5a: 2b12 cmp r3, #18
8003b5c: d82a bhi.n 8003bb4 <HAL_GPIO_Init+0xcc>
8003b5e: 2b12 cmp r3, #18
8003b60: d859 bhi.n 8003c16 <HAL_GPIO_Init+0x12e>
8003b62: a201 add r2, pc, #4 @ (adr r2, 8003b68 <HAL_GPIO_Init+0x80>)
8003b64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003b68: 08003be3 .word 0x08003be3
8003b6c: 08003bbd .word 0x08003bbd
8003b70: 08003bcf .word 0x08003bcf
8003b74: 08003c11 .word 0x08003c11
8003b78: 08003c17 .word 0x08003c17
8003b7c: 08003c17 .word 0x08003c17
8003b80: 08003c17 .word 0x08003c17
8003b84: 08003c17 .word 0x08003c17
8003b88: 08003c17 .word 0x08003c17
8003b8c: 08003c17 .word 0x08003c17
8003b90: 08003c17 .word 0x08003c17
8003b94: 08003c17 .word 0x08003c17
8003b98: 08003c17 .word 0x08003c17
8003b9c: 08003c17 .word 0x08003c17
8003ba0: 08003c17 .word 0x08003c17
8003ba4: 08003c17 .word 0x08003c17
8003ba8: 08003c17 .word 0x08003c17
8003bac: 08003bc5 .word 0x08003bc5
8003bb0: 08003bd9 .word 0x08003bd9
8003bb4: 4a79 ldr r2, [pc, #484] @ (8003d9c <HAL_GPIO_Init+0x2b4>)
8003bb6: 4293 cmp r3, r2
8003bb8: d013 beq.n 8003be2 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8003bba: e02c b.n 8003c16 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8003bbc: 683b ldr r3, [r7, #0]
8003bbe: 68db ldr r3, [r3, #12]
8003bc0: 623b str r3, [r7, #32]
break;
8003bc2: e029 b.n 8003c18 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003bc4: 683b ldr r3, [r7, #0]
8003bc6: 68db ldr r3, [r3, #12]
8003bc8: 3304 adds r3, #4
8003bca: 623b str r3, [r7, #32]
break;
8003bcc: e024 b.n 8003c18 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8003bce: 683b ldr r3, [r7, #0]
8003bd0: 68db ldr r3, [r3, #12]
8003bd2: 3308 adds r3, #8
8003bd4: 623b str r3, [r7, #32]
break;
8003bd6: e01f b.n 8003c18 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8003bd8: 683b ldr r3, [r7, #0]
8003bda: 68db ldr r3, [r3, #12]
8003bdc: 330c adds r3, #12
8003bde: 623b str r3, [r7, #32]
break;
8003be0: e01a b.n 8003c18 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8003be2: 683b ldr r3, [r7, #0]
8003be4: 689b ldr r3, [r3, #8]
8003be6: 2b00 cmp r3, #0
8003be8: d102 bne.n 8003bf0 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8003bea: 2304 movs r3, #4
8003bec: 623b str r3, [r7, #32]
break;
8003bee: e013 b.n 8003c18 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8003bf0: 683b ldr r3, [r7, #0]
8003bf2: 689b ldr r3, [r3, #8]
8003bf4: 2b01 cmp r3, #1
8003bf6: d105 bne.n 8003c04 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003bf8: 2308 movs r3, #8
8003bfa: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8003bfc: 687b ldr r3, [r7, #4]
8003bfe: 69fa ldr r2, [r7, #28]
8003c00: 611a str r2, [r3, #16]
break;
8003c02: e009 b.n 8003c18 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003c04: 2308 movs r3, #8
8003c06: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8003c08: 687b ldr r3, [r7, #4]
8003c0a: 69fa ldr r2, [r7, #28]
8003c0c: 615a str r2, [r3, #20]
break;
8003c0e: e003 b.n 8003c18 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8003c10: 2300 movs r3, #0
8003c12: 623b str r3, [r7, #32]
break;
8003c14: e000 b.n 8003c18 <HAL_GPIO_Init+0x130>
break;
8003c16: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8003c18: 69bb ldr r3, [r7, #24]
8003c1a: 2bff cmp r3, #255 @ 0xff
8003c1c: d801 bhi.n 8003c22 <HAL_GPIO_Init+0x13a>
8003c1e: 687b ldr r3, [r7, #4]
8003c20: e001 b.n 8003c26 <HAL_GPIO_Init+0x13e>
8003c22: 687b ldr r3, [r7, #4]
8003c24: 3304 adds r3, #4
8003c26: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8003c28: 69bb ldr r3, [r7, #24]
8003c2a: 2bff cmp r3, #255 @ 0xff
8003c2c: d802 bhi.n 8003c34 <HAL_GPIO_Init+0x14c>
8003c2e: 6a7b ldr r3, [r7, #36] @ 0x24
8003c30: 009b lsls r3, r3, #2
8003c32: e002 b.n 8003c3a <HAL_GPIO_Init+0x152>
8003c34: 6a7b ldr r3, [r7, #36] @ 0x24
8003c36: 3b08 subs r3, #8
8003c38: 009b lsls r3, r3, #2
8003c3a: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8003c3c: 697b ldr r3, [r7, #20]
8003c3e: 681a ldr r2, [r3, #0]
8003c40: 210f movs r1, #15
8003c42: 693b ldr r3, [r7, #16]
8003c44: fa01 f303 lsl.w r3, r1, r3
8003c48: 43db mvns r3, r3
8003c4a: 401a ands r2, r3
8003c4c: 6a39 ldr r1, [r7, #32]
8003c4e: 693b ldr r3, [r7, #16]
8003c50: fa01 f303 lsl.w r3, r1, r3
8003c54: 431a orrs r2, r3
8003c56: 697b ldr r3, [r7, #20]
8003c58: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8003c5a: 683b ldr r3, [r7, #0]
8003c5c: 685b ldr r3, [r3, #4]
8003c5e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003c62: 2b00 cmp r3, #0
8003c64: f000 80b1 beq.w 8003dca <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8003c68: 4b4d ldr r3, [pc, #308] @ (8003da0 <HAL_GPIO_Init+0x2b8>)
8003c6a: 699b ldr r3, [r3, #24]
8003c6c: 4a4c ldr r2, [pc, #304] @ (8003da0 <HAL_GPIO_Init+0x2b8>)
8003c6e: f043 0301 orr.w r3, r3, #1
8003c72: 6193 str r3, [r2, #24]
8003c74: 4b4a ldr r3, [pc, #296] @ (8003da0 <HAL_GPIO_Init+0x2b8>)
8003c76: 699b ldr r3, [r3, #24]
8003c78: f003 0301 and.w r3, r3, #1
8003c7c: 60bb str r3, [r7, #8]
8003c7e: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8003c80: 4a48 ldr r2, [pc, #288] @ (8003da4 <HAL_GPIO_Init+0x2bc>)
8003c82: 6a7b ldr r3, [r7, #36] @ 0x24
8003c84: 089b lsrs r3, r3, #2
8003c86: 3302 adds r3, #2
8003c88: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c8c: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8003c8e: 6a7b ldr r3, [r7, #36] @ 0x24
8003c90: f003 0303 and.w r3, r3, #3
8003c94: 009b lsls r3, r3, #2
8003c96: 220f movs r2, #15
8003c98: fa02 f303 lsl.w r3, r2, r3
8003c9c: 43db mvns r3, r3
8003c9e: 68fa ldr r2, [r7, #12]
8003ca0: 4013 ands r3, r2
8003ca2: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003ca4: 687b ldr r3, [r7, #4]
8003ca6: 4a40 ldr r2, [pc, #256] @ (8003da8 <HAL_GPIO_Init+0x2c0>)
8003ca8: 4293 cmp r3, r2
8003caa: d013 beq.n 8003cd4 <HAL_GPIO_Init+0x1ec>
8003cac: 687b ldr r3, [r7, #4]
8003cae: 4a3f ldr r2, [pc, #252] @ (8003dac <HAL_GPIO_Init+0x2c4>)
8003cb0: 4293 cmp r3, r2
8003cb2: d00d beq.n 8003cd0 <HAL_GPIO_Init+0x1e8>
8003cb4: 687b ldr r3, [r7, #4]
8003cb6: 4a3e ldr r2, [pc, #248] @ (8003db0 <HAL_GPIO_Init+0x2c8>)
8003cb8: 4293 cmp r3, r2
8003cba: d007 beq.n 8003ccc <HAL_GPIO_Init+0x1e4>
8003cbc: 687b ldr r3, [r7, #4]
8003cbe: 4a3d ldr r2, [pc, #244] @ (8003db4 <HAL_GPIO_Init+0x2cc>)
8003cc0: 4293 cmp r3, r2
8003cc2: d101 bne.n 8003cc8 <HAL_GPIO_Init+0x1e0>
8003cc4: 2303 movs r3, #3
8003cc6: e006 b.n 8003cd6 <HAL_GPIO_Init+0x1ee>
8003cc8: 2304 movs r3, #4
8003cca: e004 b.n 8003cd6 <HAL_GPIO_Init+0x1ee>
8003ccc: 2302 movs r3, #2
8003cce: e002 b.n 8003cd6 <HAL_GPIO_Init+0x1ee>
8003cd0: 2301 movs r3, #1
8003cd2: e000 b.n 8003cd6 <HAL_GPIO_Init+0x1ee>
8003cd4: 2300 movs r3, #0
8003cd6: 6a7a ldr r2, [r7, #36] @ 0x24
8003cd8: f002 0203 and.w r2, r2, #3
8003cdc: 0092 lsls r2, r2, #2
8003cde: 4093 lsls r3, r2
8003ce0: 68fa ldr r2, [r7, #12]
8003ce2: 4313 orrs r3, r2
8003ce4: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8003ce6: 492f ldr r1, [pc, #188] @ (8003da4 <HAL_GPIO_Init+0x2bc>)
8003ce8: 6a7b ldr r3, [r7, #36] @ 0x24
8003cea: 089b lsrs r3, r3, #2
8003cec: 3302 adds r3, #2
8003cee: 68fa ldr r2, [r7, #12]
8003cf0: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003cf4: 683b ldr r3, [r7, #0]
8003cf6: 685b ldr r3, [r3, #4]
8003cf8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003cfc: 2b00 cmp r3, #0
8003cfe: d006 beq.n 8003d0e <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8003d00: 4b2d ldr r3, [pc, #180] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d02: 689a ldr r2, [r3, #8]
8003d04: 492c ldr r1, [pc, #176] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d06: 69bb ldr r3, [r7, #24]
8003d08: 4313 orrs r3, r2
8003d0a: 608b str r3, [r1, #8]
8003d0c: e006 b.n 8003d1c <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8003d0e: 4b2a ldr r3, [pc, #168] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d10: 689a ldr r2, [r3, #8]
8003d12: 69bb ldr r3, [r7, #24]
8003d14: 43db mvns r3, r3
8003d16: 4928 ldr r1, [pc, #160] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d18: 4013 ands r3, r2
8003d1a: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8003d1c: 683b ldr r3, [r7, #0]
8003d1e: 685b ldr r3, [r3, #4]
8003d20: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003d24: 2b00 cmp r3, #0
8003d26: d006 beq.n 8003d36 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
8003d28: 4b23 ldr r3, [pc, #140] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d2a: 68da ldr r2, [r3, #12]
8003d2c: 4922 ldr r1, [pc, #136] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d2e: 69bb ldr r3, [r7, #24]
8003d30: 4313 orrs r3, r2
8003d32: 60cb str r3, [r1, #12]
8003d34: e006 b.n 8003d44 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8003d36: 4b20 ldr r3, [pc, #128] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d38: 68da ldr r2, [r3, #12]
8003d3a: 69bb ldr r3, [r7, #24]
8003d3c: 43db mvns r3, r3
8003d3e: 491e ldr r1, [pc, #120] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d40: 4013 ands r3, r2
8003d42: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8003d44: 683b ldr r3, [r7, #0]
8003d46: 685b ldr r3, [r3, #4]
8003d48: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003d4c: 2b00 cmp r3, #0
8003d4e: d006 beq.n 8003d5e <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8003d50: 4b19 ldr r3, [pc, #100] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d52: 685a ldr r2, [r3, #4]
8003d54: 4918 ldr r1, [pc, #96] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d56: 69bb ldr r3, [r7, #24]
8003d58: 4313 orrs r3, r2
8003d5a: 604b str r3, [r1, #4]
8003d5c: e006 b.n 8003d6c <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8003d5e: 4b16 ldr r3, [pc, #88] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d60: 685a ldr r2, [r3, #4]
8003d62: 69bb ldr r3, [r7, #24]
8003d64: 43db mvns r3, r3
8003d66: 4914 ldr r1, [pc, #80] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d68: 4013 ands r3, r2
8003d6a: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8003d6c: 683b ldr r3, [r7, #0]
8003d6e: 685b ldr r3, [r3, #4]
8003d70: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003d74: 2b00 cmp r3, #0
8003d76: d021 beq.n 8003dbc <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8003d78: 4b0f ldr r3, [pc, #60] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d7a: 681a ldr r2, [r3, #0]
8003d7c: 490e ldr r1, [pc, #56] @ (8003db8 <HAL_GPIO_Init+0x2d0>)
8003d7e: 69bb ldr r3, [r7, #24]
8003d80: 4313 orrs r3, r2
8003d82: 600b str r3, [r1, #0]
8003d84: e021 b.n 8003dca <HAL_GPIO_Init+0x2e2>
8003d86: bf00 nop
8003d88: 10320000 .word 0x10320000
8003d8c: 10310000 .word 0x10310000
8003d90: 10220000 .word 0x10220000
8003d94: 10210000 .word 0x10210000
8003d98: 10120000 .word 0x10120000
8003d9c: 10110000 .word 0x10110000
8003da0: 40021000 .word 0x40021000
8003da4: 40010000 .word 0x40010000
8003da8: 40010800 .word 0x40010800
8003dac: 40010c00 .word 0x40010c00
8003db0: 40011000 .word 0x40011000
8003db4: 40011400 .word 0x40011400
8003db8: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8003dbc: 4b0b ldr r3, [pc, #44] @ (8003dec <HAL_GPIO_Init+0x304>)
8003dbe: 681a ldr r2, [r3, #0]
8003dc0: 69bb ldr r3, [r7, #24]
8003dc2: 43db mvns r3, r3
8003dc4: 4909 ldr r1, [pc, #36] @ (8003dec <HAL_GPIO_Init+0x304>)
8003dc6: 4013 ands r3, r2
8003dc8: 600b str r3, [r1, #0]
}
}
}
position++;
8003dca: 6a7b ldr r3, [r7, #36] @ 0x24
8003dcc: 3301 adds r3, #1
8003dce: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003dd0: 683b ldr r3, [r7, #0]
8003dd2: 681a ldr r2, [r3, #0]
8003dd4: 6a7b ldr r3, [r7, #36] @ 0x24
8003dd6: fa22 f303 lsr.w r3, r2, r3
8003dda: 2b00 cmp r3, #0
8003ddc: f47f ae8e bne.w 8003afc <HAL_GPIO_Init+0x14>
}
}
8003de0: bf00 nop
8003de2: bf00 nop
8003de4: 372c adds r7, #44 @ 0x2c
8003de6: 46bd mov sp, r7
8003de8: bc80 pop {r7}
8003dea: 4770 bx lr
8003dec: 40010400 .word 0x40010400
08003df0 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003df0: b480 push {r7}
8003df2: b085 sub sp, #20
8003df4: af00 add r7, sp, #0
8003df6: 6078 str r0, [r7, #4]
8003df8: 460b mov r3, r1
8003dfa: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8003dfc: 687b ldr r3, [r7, #4]
8003dfe: 689a ldr r2, [r3, #8]
8003e00: 887b ldrh r3, [r7, #2]
8003e02: 4013 ands r3, r2
8003e04: 2b00 cmp r3, #0
8003e06: d002 beq.n 8003e0e <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8003e08: 2301 movs r3, #1
8003e0a: 73fb strb r3, [r7, #15]
8003e0c: e001 b.n 8003e12 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8003e0e: 2300 movs r3, #0
8003e10: 73fb strb r3, [r7, #15]
}
return bitstatus;
8003e12: 7bfb ldrb r3, [r7, #15]
}
8003e14: 4618 mov r0, r3
8003e16: 3714 adds r7, #20
8003e18: 46bd mov sp, r7
8003e1a: bc80 pop {r7}
8003e1c: 4770 bx lr
08003e1e <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003e1e: b480 push {r7}
8003e20: b083 sub sp, #12
8003e22: af00 add r7, sp, #0
8003e24: 6078 str r0, [r7, #4]
8003e26: 460b mov r3, r1
8003e28: 807b strh r3, [r7, #2]
8003e2a: 4613 mov r3, r2
8003e2c: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003e2e: 787b ldrb r3, [r7, #1]
8003e30: 2b00 cmp r3, #0
8003e32: d003 beq.n 8003e3c <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8003e34: 887a ldrh r2, [r7, #2]
8003e36: 687b ldr r3, [r7, #4]
8003e38: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8003e3a: e003 b.n 8003e44 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8003e3c: 887b ldrh r3, [r7, #2]
8003e3e: 041a lsls r2, r3, #16
8003e40: 687b ldr r3, [r7, #4]
8003e42: 611a str r2, [r3, #16]
}
8003e44: bf00 nop
8003e46: 370c adds r7, #12
8003e48: 46bd mov sp, r7
8003e4a: bc80 pop {r7}
8003e4c: 4770 bx lr
08003e4e <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003e4e: b480 push {r7}
8003e50: b085 sub sp, #20
8003e52: af00 add r7, sp, #0
8003e54: 6078 str r0, [r7, #4]
8003e56: 460b mov r3, r1
8003e58: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8003e5a: 687b ldr r3, [r7, #4]
8003e5c: 68db ldr r3, [r3, #12]
8003e5e: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8003e60: 887a ldrh r2, [r7, #2]
8003e62: 68fb ldr r3, [r7, #12]
8003e64: 4013 ands r3, r2
8003e66: 041a lsls r2, r3, #16
8003e68: 68fb ldr r3, [r7, #12]
8003e6a: 43d9 mvns r1, r3
8003e6c: 887b ldrh r3, [r7, #2]
8003e6e: 400b ands r3, r1
8003e70: 431a orrs r2, r3
8003e72: 687b ldr r3, [r7, #4]
8003e74: 611a str r2, [r3, #16]
}
8003e76: bf00 nop
8003e78: 3714 adds r7, #20
8003e7a: 46bd mov sp, r7
8003e7c: bc80 pop {r7}
8003e7e: 4770 bx lr
08003e80 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003e80: b580 push {r7, lr}
8003e82: b084 sub sp, #16
8003e84: af00 add r7, sp, #0
8003e86: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003e88: 687b ldr r3, [r7, #4]
8003e8a: 2b00 cmp r3, #0
8003e8c: d101 bne.n 8003e92 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8003e8e: 2301 movs r3, #1
8003e90: e12b b.n 80040ea <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003e92: 687b ldr r3, [r7, #4]
8003e94: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003e98: b2db uxtb r3, r3
8003e9a: 2b00 cmp r3, #0
8003e9c: d106 bne.n 8003eac <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8003e9e: 687b ldr r3, [r7, #4]
8003ea0: 2200 movs r2, #0
8003ea2: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003ea6: 6878 ldr r0, [r7, #4]
8003ea8: f7fe f99a bl 80021e0 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8003eac: 687b ldr r3, [r7, #4]
8003eae: 2224 movs r2, #36 @ 0x24
8003eb0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003eb4: 687b ldr r3, [r7, #4]
8003eb6: 681b ldr r3, [r3, #0]
8003eb8: 681a ldr r2, [r3, #0]
8003eba: 687b ldr r3, [r7, #4]
8003ebc: 681b ldr r3, [r3, #0]
8003ebe: f022 0201 bic.w r2, r2, #1
8003ec2: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003ec4: 687b ldr r3, [r7, #4]
8003ec6: 681b ldr r3, [r3, #0]
8003ec8: 681a ldr r2, [r3, #0]
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 681b ldr r3, [r3, #0]
8003ece: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003ed2: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 681b ldr r3, [r3, #0]
8003ed8: 681a ldr r2, [r3, #0]
8003eda: 687b ldr r3, [r7, #4]
8003edc: 681b ldr r3, [r3, #0]
8003ede: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003ee2: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003ee4: f001 fbcc bl 8005680 <HAL_RCC_GetPCLK1Freq>
8003ee8: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
8003eea: 687b ldr r3, [r7, #4]
8003eec: 685b ldr r3, [r3, #4]
8003eee: 4a81 ldr r2, [pc, #516] @ (80040f4 <HAL_I2C_Init+0x274>)
8003ef0: 4293 cmp r3, r2
8003ef2: d807 bhi.n 8003f04 <HAL_I2C_Init+0x84>
8003ef4: 68fb ldr r3, [r7, #12]
8003ef6: 4a80 ldr r2, [pc, #512] @ (80040f8 <HAL_I2C_Init+0x278>)
8003ef8: 4293 cmp r3, r2
8003efa: bf94 ite ls
8003efc: 2301 movls r3, #1
8003efe: 2300 movhi r3, #0
8003f00: b2db uxtb r3, r3
8003f02: e006 b.n 8003f12 <HAL_I2C_Init+0x92>
8003f04: 68fb ldr r3, [r7, #12]
8003f06: 4a7d ldr r2, [pc, #500] @ (80040fc <HAL_I2C_Init+0x27c>)
8003f08: 4293 cmp r3, r2
8003f0a: bf94 ite ls
8003f0c: 2301 movls r3, #1
8003f0e: 2300 movhi r3, #0
8003f10: b2db uxtb r3, r3
8003f12: 2b00 cmp r3, #0
8003f14: d001 beq.n 8003f1a <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003f16: 2301 movs r3, #1
8003f18: e0e7 b.n 80040ea <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
8003f1a: 68fb ldr r3, [r7, #12]
8003f1c: 4a78 ldr r2, [pc, #480] @ (8004100 <HAL_I2C_Init+0x280>)
8003f1e: fba2 2303 umull r2, r3, r2, r3
8003f22: 0c9b lsrs r3, r3, #18
8003f24: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
8003f26: 687b ldr r3, [r7, #4]
8003f28: 681b ldr r3, [r3, #0]
8003f2a: 685b ldr r3, [r3, #4]
8003f2c: f023 013f bic.w r1, r3, #63 @ 0x3f
8003f30: 687b ldr r3, [r7, #4]
8003f32: 681b ldr r3, [r3, #0]
8003f34: 68ba ldr r2, [r7, #8]
8003f36: 430a orrs r2, r1
8003f38: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 681b ldr r3, [r3, #0]
8003f3e: 6a1b ldr r3, [r3, #32]
8003f40: f023 013f bic.w r1, r3, #63 @ 0x3f
8003f44: 687b ldr r3, [r7, #4]
8003f46: 685b ldr r3, [r3, #4]
8003f48: 4a6a ldr r2, [pc, #424] @ (80040f4 <HAL_I2C_Init+0x274>)
8003f4a: 4293 cmp r3, r2
8003f4c: d802 bhi.n 8003f54 <HAL_I2C_Init+0xd4>
8003f4e: 68bb ldr r3, [r7, #8]
8003f50: 3301 adds r3, #1
8003f52: e009 b.n 8003f68 <HAL_I2C_Init+0xe8>
8003f54: 68bb ldr r3, [r7, #8]
8003f56: f44f 7296 mov.w r2, #300 @ 0x12c
8003f5a: fb02 f303 mul.w r3, r2, r3
8003f5e: 4a69 ldr r2, [pc, #420] @ (8004104 <HAL_I2C_Init+0x284>)
8003f60: fba2 2303 umull r2, r3, r2, r3
8003f64: 099b lsrs r3, r3, #6
8003f66: 3301 adds r3, #1
8003f68: 687a ldr r2, [r7, #4]
8003f6a: 6812 ldr r2, [r2, #0]
8003f6c: 430b orrs r3, r1
8003f6e: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8003f70: 687b ldr r3, [r7, #4]
8003f72: 681b ldr r3, [r3, #0]
8003f74: 69db ldr r3, [r3, #28]
8003f76: f423 424f bic.w r2, r3, #52992 @ 0xcf00
8003f7a: f022 02ff bic.w r2, r2, #255 @ 0xff
8003f7e: 687b ldr r3, [r7, #4]
8003f80: 685b ldr r3, [r3, #4]
8003f82: 495c ldr r1, [pc, #368] @ (80040f4 <HAL_I2C_Init+0x274>)
8003f84: 428b cmp r3, r1
8003f86: d819 bhi.n 8003fbc <HAL_I2C_Init+0x13c>
8003f88: 68fb ldr r3, [r7, #12]
8003f8a: 1e59 subs r1, r3, #1
8003f8c: 687b ldr r3, [r7, #4]
8003f8e: 685b ldr r3, [r3, #4]
8003f90: 005b lsls r3, r3, #1
8003f92: fbb1 f3f3 udiv r3, r1, r3
8003f96: 1c59 adds r1, r3, #1
8003f98: f640 73fc movw r3, #4092 @ 0xffc
8003f9c: 400b ands r3, r1
8003f9e: 2b00 cmp r3, #0
8003fa0: d00a beq.n 8003fb8 <HAL_I2C_Init+0x138>
8003fa2: 68fb ldr r3, [r7, #12]
8003fa4: 1e59 subs r1, r3, #1
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 685b ldr r3, [r3, #4]
8003faa: 005b lsls r3, r3, #1
8003fac: fbb1 f3f3 udiv r3, r1, r3
8003fb0: 3301 adds r3, #1
8003fb2: f3c3 030b ubfx r3, r3, #0, #12
8003fb6: e051 b.n 800405c <HAL_I2C_Init+0x1dc>
8003fb8: 2304 movs r3, #4
8003fba: e04f b.n 800405c <HAL_I2C_Init+0x1dc>
8003fbc: 687b ldr r3, [r7, #4]
8003fbe: 689b ldr r3, [r3, #8]
8003fc0: 2b00 cmp r3, #0
8003fc2: d111 bne.n 8003fe8 <HAL_I2C_Init+0x168>
8003fc4: 68fb ldr r3, [r7, #12]
8003fc6: 1e58 subs r0, r3, #1
8003fc8: 687b ldr r3, [r7, #4]
8003fca: 6859 ldr r1, [r3, #4]
8003fcc: 460b mov r3, r1
8003fce: 005b lsls r3, r3, #1
8003fd0: 440b add r3, r1
8003fd2: fbb0 f3f3 udiv r3, r0, r3
8003fd6: 3301 adds r3, #1
8003fd8: f3c3 030b ubfx r3, r3, #0, #12
8003fdc: 2b00 cmp r3, #0
8003fde: bf0c ite eq
8003fe0: 2301 moveq r3, #1
8003fe2: 2300 movne r3, #0
8003fe4: b2db uxtb r3, r3
8003fe6: e012 b.n 800400e <HAL_I2C_Init+0x18e>
8003fe8: 68fb ldr r3, [r7, #12]
8003fea: 1e58 subs r0, r3, #1
8003fec: 687b ldr r3, [r7, #4]
8003fee: 6859 ldr r1, [r3, #4]
8003ff0: 460b mov r3, r1
8003ff2: 009b lsls r3, r3, #2
8003ff4: 440b add r3, r1
8003ff6: 0099 lsls r1, r3, #2
8003ff8: 440b add r3, r1
8003ffa: fbb0 f3f3 udiv r3, r0, r3
8003ffe: 3301 adds r3, #1
8004000: f3c3 030b ubfx r3, r3, #0, #12
8004004: 2b00 cmp r3, #0
8004006: bf0c ite eq
8004008: 2301 moveq r3, #1
800400a: 2300 movne r3, #0
800400c: b2db uxtb r3, r3
800400e: 2b00 cmp r3, #0
8004010: d001 beq.n 8004016 <HAL_I2C_Init+0x196>
8004012: 2301 movs r3, #1
8004014: e022 b.n 800405c <HAL_I2C_Init+0x1dc>
8004016: 687b ldr r3, [r7, #4]
8004018: 689b ldr r3, [r3, #8]
800401a: 2b00 cmp r3, #0
800401c: d10e bne.n 800403c <HAL_I2C_Init+0x1bc>
800401e: 68fb ldr r3, [r7, #12]
8004020: 1e58 subs r0, r3, #1
8004022: 687b ldr r3, [r7, #4]
8004024: 6859 ldr r1, [r3, #4]
8004026: 460b mov r3, r1
8004028: 005b lsls r3, r3, #1
800402a: 440b add r3, r1
800402c: fbb0 f3f3 udiv r3, r0, r3
8004030: 3301 adds r3, #1
8004032: f3c3 030b ubfx r3, r3, #0, #12
8004036: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800403a: e00f b.n 800405c <HAL_I2C_Init+0x1dc>
800403c: 68fb ldr r3, [r7, #12]
800403e: 1e58 subs r0, r3, #1
8004040: 687b ldr r3, [r7, #4]
8004042: 6859 ldr r1, [r3, #4]
8004044: 460b mov r3, r1
8004046: 009b lsls r3, r3, #2
8004048: 440b add r3, r1
800404a: 0099 lsls r1, r3, #2
800404c: 440b add r3, r1
800404e: fbb0 f3f3 udiv r3, r0, r3
8004052: 3301 adds r3, #1
8004054: f3c3 030b ubfx r3, r3, #0, #12
8004058: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800405c: 6879 ldr r1, [r7, #4]
800405e: 6809 ldr r1, [r1, #0]
8004060: 4313 orrs r3, r2
8004062: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8004064: 687b ldr r3, [r7, #4]
8004066: 681b ldr r3, [r3, #0]
8004068: 681b ldr r3, [r3, #0]
800406a: f023 01c0 bic.w r1, r3, #192 @ 0xc0
800406e: 687b ldr r3, [r7, #4]
8004070: 69da ldr r2, [r3, #28]
8004072: 687b ldr r3, [r7, #4]
8004074: 6a1b ldr r3, [r3, #32]
8004076: 431a orrs r2, r3
8004078: 687b ldr r3, [r7, #4]
800407a: 681b ldr r3, [r3, #0]
800407c: 430a orrs r2, r1
800407e: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8004080: 687b ldr r3, [r7, #4]
8004082: 681b ldr r3, [r3, #0]
8004084: 689b ldr r3, [r3, #8]
8004086: f423 4303 bic.w r3, r3, #33536 @ 0x8300
800408a: f023 03ff bic.w r3, r3, #255 @ 0xff
800408e: 687a ldr r2, [r7, #4]
8004090: 6911 ldr r1, [r2, #16]
8004092: 687a ldr r2, [r7, #4]
8004094: 68d2 ldr r2, [r2, #12]
8004096: 4311 orrs r1, r2
8004098: 687a ldr r2, [r7, #4]
800409a: 6812 ldr r2, [r2, #0]
800409c: 430b orrs r3, r1
800409e: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
80040a0: 687b ldr r3, [r7, #4]
80040a2: 681b ldr r3, [r3, #0]
80040a4: 68db ldr r3, [r3, #12]
80040a6: f023 01ff bic.w r1, r3, #255 @ 0xff
80040aa: 687b ldr r3, [r7, #4]
80040ac: 695a ldr r2, [r3, #20]
80040ae: 687b ldr r3, [r7, #4]
80040b0: 699b ldr r3, [r3, #24]
80040b2: 431a orrs r2, r3
80040b4: 687b ldr r3, [r7, #4]
80040b6: 681b ldr r3, [r3, #0]
80040b8: 430a orrs r2, r1
80040ba: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80040bc: 687b ldr r3, [r7, #4]
80040be: 681b ldr r3, [r3, #0]
80040c0: 681a ldr r2, [r3, #0]
80040c2: 687b ldr r3, [r7, #4]
80040c4: 681b ldr r3, [r3, #0]
80040c6: f042 0201 orr.w r2, r2, #1
80040ca: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80040cc: 687b ldr r3, [r7, #4]
80040ce: 2200 movs r2, #0
80040d0: 641a str r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_READY;
80040d2: 687b ldr r3, [r7, #4]
80040d4: 2220 movs r2, #32
80040d6: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
80040da: 687b ldr r3, [r7, #4]
80040dc: 2200 movs r2, #0
80040de: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80040e0: 687b ldr r3, [r7, #4]
80040e2: 2200 movs r2, #0
80040e4: f883 203e strb.w r2, [r3, #62] @ 0x3e
return HAL_OK;
80040e8: 2300 movs r3, #0
}
80040ea: 4618 mov r0, r3
80040ec: 3710 adds r7, #16
80040ee: 46bd mov sp, r7
80040f0: bd80 pop {r7, pc}
80040f2: bf00 nop
80040f4: 000186a0 .word 0x000186a0
80040f8: 001e847f .word 0x001e847f
80040fc: 003d08ff .word 0x003d08ff
8004100: 431bde83 .word 0x431bde83
8004104: 10624dd3 .word 0x10624dd3
08004108 <HAL_I2C_Master_Transmit>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8004108: b580 push {r7, lr}
800410a: b088 sub sp, #32
800410c: af02 add r7, sp, #8
800410e: 60f8 str r0, [r7, #12]
8004110: 607a str r2, [r7, #4]
8004112: 461a mov r2, r3
8004114: 460b mov r3, r1
8004116: 817b strh r3, [r7, #10]
8004118: 4613 mov r3, r2
800411a: 813b strh r3, [r7, #8]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
800411c: f7fe fee4 bl 8002ee8 <HAL_GetTick>
8004120: 6178 str r0, [r7, #20]
if (hi2c->State == HAL_I2C_STATE_READY)
8004122: 68fb ldr r3, [r7, #12]
8004124: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004128: b2db uxtb r3, r3
800412a: 2b20 cmp r3, #32
800412c: f040 80e0 bne.w 80042f0 <HAL_I2C_Master_Transmit+0x1e8>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
8004130: 697b ldr r3, [r7, #20]
8004132: 9300 str r3, [sp, #0]
8004134: 2319 movs r3, #25
8004136: 2201 movs r2, #1
8004138: 4970 ldr r1, [pc, #448] @ (80042fc <HAL_I2C_Master_Transmit+0x1f4>)
800413a: 68f8 ldr r0, [r7, #12]
800413c: f000 fc9e bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
8004140: 4603 mov r3, r0
8004142: 2b00 cmp r3, #0
8004144: d001 beq.n 800414a <HAL_I2C_Master_Transmit+0x42>
{
return HAL_BUSY;
8004146: 2302 movs r3, #2
8004148: e0d3 b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800414a: 68fb ldr r3, [r7, #12]
800414c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004150: 2b01 cmp r3, #1
8004152: d101 bne.n 8004158 <HAL_I2C_Master_Transmit+0x50>
8004154: 2302 movs r3, #2
8004156: e0cc b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
8004158: 68fb ldr r3, [r7, #12]
800415a: 2201 movs r2, #1
800415c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
8004160: 68fb ldr r3, [r7, #12]
8004162: 681b ldr r3, [r3, #0]
8004164: 681b ldr r3, [r3, #0]
8004166: f003 0301 and.w r3, r3, #1
800416a: 2b01 cmp r3, #1
800416c: d007 beq.n 800417e <HAL_I2C_Master_Transmit+0x76>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800416e: 68fb ldr r3, [r7, #12]
8004170: 681b ldr r3, [r3, #0]
8004172: 681a ldr r2, [r3, #0]
8004174: 68fb ldr r3, [r7, #12]
8004176: 681b ldr r3, [r3, #0]
8004178: f042 0201 orr.w r2, r2, #1
800417c: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
800417e: 68fb ldr r3, [r7, #12]
8004180: 681b ldr r3, [r3, #0]
8004182: 681a ldr r2, [r3, #0]
8004184: 68fb ldr r3, [r7, #12]
8004186: 681b ldr r3, [r3, #0]
8004188: f422 6200 bic.w r2, r2, #2048 @ 0x800
800418c: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_TX;
800418e: 68fb ldr r3, [r7, #12]
8004190: 2221 movs r2, #33 @ 0x21
8004192: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8004196: 68fb ldr r3, [r7, #12]
8004198: 2210 movs r2, #16
800419a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800419e: 68fb ldr r3, [r7, #12]
80041a0: 2200 movs r2, #0
80041a2: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80041a4: 68fb ldr r3, [r7, #12]
80041a6: 687a ldr r2, [r7, #4]
80041a8: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
80041aa: 68fb ldr r3, [r7, #12]
80041ac: 893a ldrh r2, [r7, #8]
80041ae: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
80041b0: 68fb ldr r3, [r7, #12]
80041b2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80041b4: b29a uxth r2, r3
80041b6: 68fb ldr r3, [r7, #12]
80041b8: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
80041ba: 68fb ldr r3, [r7, #12]
80041bc: 4a50 ldr r2, [pc, #320] @ (8004300 <HAL_I2C_Master_Transmit+0x1f8>)
80041be: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
80041c0: 8979 ldrh r1, [r7, #10]
80041c2: 697b ldr r3, [r7, #20]
80041c4: 6a3a ldr r2, [r7, #32]
80041c6: 68f8 ldr r0, [r7, #12]
80041c8: f000 fb08 bl 80047dc <I2C_MasterRequestWrite>
80041cc: 4603 mov r3, r0
80041ce: 2b00 cmp r3, #0
80041d0: d001 beq.n 80041d6 <HAL_I2C_Master_Transmit+0xce>
{
return HAL_ERROR;
80041d2: 2301 movs r3, #1
80041d4: e08d b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80041d6: 2300 movs r3, #0
80041d8: 613b str r3, [r7, #16]
80041da: 68fb ldr r3, [r7, #12]
80041dc: 681b ldr r3, [r3, #0]
80041de: 695b ldr r3, [r3, #20]
80041e0: 613b str r3, [r7, #16]
80041e2: 68fb ldr r3, [r7, #12]
80041e4: 681b ldr r3, [r3, #0]
80041e6: 699b ldr r3, [r3, #24]
80041e8: 613b str r3, [r7, #16]
80041ea: 693b ldr r3, [r7, #16]
while (hi2c->XferSize > 0U)
80041ec: e066 b.n 80042bc <HAL_I2C_Master_Transmit+0x1b4>
{
/* Wait until TXE flag is set */
if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
80041ee: 697a ldr r2, [r7, #20]
80041f0: 6a39 ldr r1, [r7, #32]
80041f2: 68f8 ldr r0, [r7, #12]
80041f4: f000 fd5c bl 8004cb0 <I2C_WaitOnTXEFlagUntilTimeout>
80041f8: 4603 mov r3, r0
80041fa: 2b00 cmp r3, #0
80041fc: d00d beq.n 800421a <HAL_I2C_Master_Transmit+0x112>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
80041fe: 68fb ldr r3, [r7, #12]
8004200: 6c1b ldr r3, [r3, #64] @ 0x40
8004202: 2b04 cmp r3, #4
8004204: d107 bne.n 8004216 <HAL_I2C_Master_Transmit+0x10e>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004206: 68fb ldr r3, [r7, #12]
8004208: 681b ldr r3, [r3, #0]
800420a: 681a ldr r2, [r3, #0]
800420c: 68fb ldr r3, [r7, #12]
800420e: 681b ldr r3, [r3, #0]
8004210: f442 7200 orr.w r2, r2, #512 @ 0x200
8004214: 601a str r2, [r3, #0]
}
return HAL_ERROR;
8004216: 2301 movs r3, #1
8004218: e06b b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
}
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
800421a: 68fb ldr r3, [r7, #12]
800421c: 6a5b ldr r3, [r3, #36] @ 0x24
800421e: 781a ldrb r2, [r3, #0]
8004220: 68fb ldr r3, [r7, #12]
8004222: 681b ldr r3, [r3, #0]
8004224: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004226: 68fb ldr r3, [r7, #12]
8004228: 6a5b ldr r3, [r3, #36] @ 0x24
800422a: 1c5a adds r2, r3, #1
800422c: 68fb ldr r3, [r7, #12]
800422e: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8004230: 68fb ldr r3, [r7, #12]
8004232: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004234: b29b uxth r3, r3
8004236: 3b01 subs r3, #1
8004238: b29a uxth r2, r3
800423a: 68fb ldr r3, [r7, #12]
800423c: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
800423e: 68fb ldr r3, [r7, #12]
8004240: 8d1b ldrh r3, [r3, #40] @ 0x28
8004242: 3b01 subs r3, #1
8004244: b29a uxth r2, r3
8004246: 68fb ldr r3, [r7, #12]
8004248: 851a strh r2, [r3, #40] @ 0x28
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
800424a: 68fb ldr r3, [r7, #12]
800424c: 681b ldr r3, [r3, #0]
800424e: 695b ldr r3, [r3, #20]
8004250: f003 0304 and.w r3, r3, #4
8004254: 2b04 cmp r3, #4
8004256: d11b bne.n 8004290 <HAL_I2C_Master_Transmit+0x188>
8004258: 68fb ldr r3, [r7, #12]
800425a: 8d1b ldrh r3, [r3, #40] @ 0x28
800425c: 2b00 cmp r3, #0
800425e: d017 beq.n 8004290 <HAL_I2C_Master_Transmit+0x188>
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
8004260: 68fb ldr r3, [r7, #12]
8004262: 6a5b ldr r3, [r3, #36] @ 0x24
8004264: 781a ldrb r2, [r3, #0]
8004266: 68fb ldr r3, [r7, #12]
8004268: 681b ldr r3, [r3, #0]
800426a: 611a str r2, [r3, #16]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800426c: 68fb ldr r3, [r7, #12]
800426e: 6a5b ldr r3, [r3, #36] @ 0x24
8004270: 1c5a adds r2, r3, #1
8004272: 68fb ldr r3, [r7, #12]
8004274: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferCount--;
8004276: 68fb ldr r3, [r7, #12]
8004278: 8d5b ldrh r3, [r3, #42] @ 0x2a
800427a: b29b uxth r3, r3
800427c: 3b01 subs r3, #1
800427e: b29a uxth r2, r3
8004280: 68fb ldr r3, [r7, #12]
8004282: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8004284: 68fb ldr r3, [r7, #12]
8004286: 8d1b ldrh r3, [r3, #40] @ 0x28
8004288: 3b01 subs r3, #1
800428a: b29a uxth r2, r3
800428c: 68fb ldr r3, [r7, #12]
800428e: 851a strh r2, [r3, #40] @ 0x28
}
/* Wait until BTF flag is set */
if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004290: 697a ldr r2, [r7, #20]
8004292: 6a39 ldr r1, [r7, #32]
8004294: 68f8 ldr r0, [r7, #12]
8004296: f000 fd53 bl 8004d40 <I2C_WaitOnBTFFlagUntilTimeout>
800429a: 4603 mov r3, r0
800429c: 2b00 cmp r3, #0
800429e: d00d beq.n 80042bc <HAL_I2C_Master_Transmit+0x1b4>
{
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
80042a0: 68fb ldr r3, [r7, #12]
80042a2: 6c1b ldr r3, [r3, #64] @ 0x40
80042a4: 2b04 cmp r3, #4
80042a6: d107 bne.n 80042b8 <HAL_I2C_Master_Transmit+0x1b0>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80042a8: 68fb ldr r3, [r7, #12]
80042aa: 681b ldr r3, [r3, #0]
80042ac: 681a ldr r2, [r3, #0]
80042ae: 68fb ldr r3, [r7, #12]
80042b0: 681b ldr r3, [r3, #0]
80042b2: f442 7200 orr.w r2, r2, #512 @ 0x200
80042b6: 601a str r2, [r3, #0]
}
return HAL_ERROR;
80042b8: 2301 movs r3, #1
80042ba: e01a b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
while (hi2c->XferSize > 0U)
80042bc: 68fb ldr r3, [r7, #12]
80042be: 8d1b ldrh r3, [r3, #40] @ 0x28
80042c0: 2b00 cmp r3, #0
80042c2: d194 bne.n 80041ee <HAL_I2C_Master_Transmit+0xe6>
}
}
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80042c4: 68fb ldr r3, [r7, #12]
80042c6: 681b ldr r3, [r3, #0]
80042c8: 681a ldr r2, [r3, #0]
80042ca: 68fb ldr r3, [r7, #12]
80042cc: 681b ldr r3, [r3, #0]
80042ce: f442 7200 orr.w r2, r2, #512 @ 0x200
80042d2: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80042d4: 68fb ldr r3, [r7, #12]
80042d6: 2220 movs r2, #32
80042d8: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80042dc: 68fb ldr r3, [r7, #12]
80042de: 2200 movs r2, #0
80042e0: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80042e4: 68fb ldr r3, [r7, #12]
80042e6: 2200 movs r2, #0
80042e8: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80042ec: 2300 movs r3, #0
80042ee: e000 b.n 80042f2 <HAL_I2C_Master_Transmit+0x1ea>
}
else
{
return HAL_BUSY;
80042f0: 2302 movs r3, #2
}
}
80042f2: 4618 mov r0, r3
80042f4: 3718 adds r7, #24
80042f6: 46bd mov sp, r7
80042f8: bd80 pop {r7, pc}
80042fa: bf00 nop
80042fc: 00100002 .word 0x00100002
8004300: ffff0000 .word 0xffff0000
08004304 <HAL_I2C_Master_Receive>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8004304: b580 push {r7, lr}
8004306: b08c sub sp, #48 @ 0x30
8004308: af02 add r7, sp, #8
800430a: 60f8 str r0, [r7, #12]
800430c: 607a str r2, [r7, #4]
800430e: 461a mov r2, r3
8004310: 460b mov r3, r1
8004312: 817b strh r3, [r7, #10]
8004314: 4613 mov r3, r2
8004316: 813b strh r3, [r7, #8]
__IO uint32_t count = 0U;
8004318: 2300 movs r3, #0
800431a: 623b str r3, [r7, #32]
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
800431c: f7fe fde4 bl 8002ee8 <HAL_GetTick>
8004320: 6278 str r0, [r7, #36] @ 0x24
if (hi2c->State == HAL_I2C_STATE_READY)
8004322: 68fb ldr r3, [r7, #12]
8004324: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004328: b2db uxtb r3, r3
800432a: 2b20 cmp r3, #32
800432c: f040 824b bne.w 80047c6 <HAL_I2C_Master_Receive+0x4c2>
{
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
8004330: 6a7b ldr r3, [r7, #36] @ 0x24
8004332: 9300 str r3, [sp, #0]
8004334: 2319 movs r3, #25
8004336: 2201 movs r2, #1
8004338: 497f ldr r1, [pc, #508] @ (8004538 <HAL_I2C_Master_Receive+0x234>)
800433a: 68f8 ldr r0, [r7, #12]
800433c: f000 fb9e bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
8004340: 4603 mov r3, r0
8004342: 2b00 cmp r3, #0
8004344: d001 beq.n 800434a <HAL_I2C_Master_Receive+0x46>
{
return HAL_BUSY;
8004346: 2302 movs r3, #2
8004348: e23e b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800434a: 68fb ldr r3, [r7, #12]
800434c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004350: 2b01 cmp r3, #1
8004352: d101 bne.n 8004358 <HAL_I2C_Master_Receive+0x54>
8004354: 2302 movs r3, #2
8004356: e237 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
8004358: 68fb ldr r3, [r7, #12]
800435a: 2201 movs r2, #1
800435c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Check if the I2C is already enabled */
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
8004360: 68fb ldr r3, [r7, #12]
8004362: 681b ldr r3, [r3, #0]
8004364: 681b ldr r3, [r3, #0]
8004366: f003 0301 and.w r3, r3, #1
800436a: 2b01 cmp r3, #1
800436c: d007 beq.n 800437e <HAL_I2C_Master_Receive+0x7a>
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800436e: 68fb ldr r3, [r7, #12]
8004370: 681b ldr r3, [r3, #0]
8004372: 681a ldr r2, [r3, #0]
8004374: 68fb ldr r3, [r7, #12]
8004376: 681b ldr r3, [r3, #0]
8004378: f042 0201 orr.w r2, r2, #1
800437c: 601a str r2, [r3, #0]
}
/* Disable Pos */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
800437e: 68fb ldr r3, [r7, #12]
8004380: 681b ldr r3, [r3, #0]
8004382: 681a ldr r2, [r3, #0]
8004384: 68fb ldr r3, [r7, #12]
8004386: 681b ldr r3, [r3, #0]
8004388: f422 6200 bic.w r2, r2, #2048 @ 0x800
800438c: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_BUSY_RX;
800438e: 68fb ldr r3, [r7, #12]
8004390: 2222 movs r2, #34 @ 0x22
8004392: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_MASTER;
8004396: 68fb ldr r3, [r7, #12]
8004398: 2210 movs r2, #16
800439a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800439e: 68fb ldr r3, [r7, #12]
80043a0: 2200 movs r2, #0
80043a2: 641a str r2, [r3, #64] @ 0x40
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80043a4: 68fb ldr r3, [r7, #12]
80043a6: 687a ldr r2, [r7, #4]
80043a8: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
80043aa: 68fb ldr r3, [r7, #12]
80043ac: 893a ldrh r2, [r7, #8]
80043ae: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
80043b0: 68fb ldr r3, [r7, #12]
80043b2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80043b4: b29a uxth r2, r3
80043b6: 68fb ldr r3, [r7, #12]
80043b8: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
80043ba: 68fb ldr r3, [r7, #12]
80043bc: 4a5f ldr r2, [pc, #380] @ (800453c <HAL_I2C_Master_Receive+0x238>)
80043be: 62da str r2, [r3, #44] @ 0x2c
/* Send Slave Address */
if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
80043c0: 8979 ldrh r1, [r7, #10]
80043c2: 6a7b ldr r3, [r7, #36] @ 0x24
80043c4: 6b3a ldr r2, [r7, #48] @ 0x30
80043c6: 68f8 ldr r0, [r7, #12]
80043c8: f000 fa8a bl 80048e0 <I2C_MasterRequestRead>
80043cc: 4603 mov r3, r0
80043ce: 2b00 cmp r3, #0
80043d0: d001 beq.n 80043d6 <HAL_I2C_Master_Receive+0xd2>
{
return HAL_ERROR;
80043d2: 2301 movs r3, #1
80043d4: e1f8 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
if (hi2c->XferSize == 0U)
80043d6: 68fb ldr r3, [r7, #12]
80043d8: 8d1b ldrh r3, [r3, #40] @ 0x28
80043da: 2b00 cmp r3, #0
80043dc: d113 bne.n 8004406 <HAL_I2C_Master_Receive+0x102>
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80043de: 2300 movs r3, #0
80043e0: 61fb str r3, [r7, #28]
80043e2: 68fb ldr r3, [r7, #12]
80043e4: 681b ldr r3, [r3, #0]
80043e6: 695b ldr r3, [r3, #20]
80043e8: 61fb str r3, [r7, #28]
80043ea: 68fb ldr r3, [r7, #12]
80043ec: 681b ldr r3, [r3, #0]
80043ee: 699b ldr r3, [r3, #24]
80043f0: 61fb str r3, [r7, #28]
80043f2: 69fb ldr r3, [r7, #28]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
80043f4: 68fb ldr r3, [r7, #12]
80043f6: 681b ldr r3, [r3, #0]
80043f8: 681a ldr r2, [r3, #0]
80043fa: 68fb ldr r3, [r7, #12]
80043fc: 681b ldr r3, [r3, #0]
80043fe: f442 7200 orr.w r2, r2, #512 @ 0x200
8004402: 601a str r2, [r3, #0]
8004404: e1cc b.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
}
else if (hi2c->XferSize == 1U)
8004406: 68fb ldr r3, [r7, #12]
8004408: 8d1b ldrh r3, [r3, #40] @ 0x28
800440a: 2b01 cmp r3, #1
800440c: d11e bne.n 800444c <HAL_I2C_Master_Receive+0x148>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
800440e: 68fb ldr r3, [r7, #12]
8004410: 681b ldr r3, [r3, #0]
8004412: 681a ldr r2, [r3, #0]
8004414: 68fb ldr r3, [r7, #12]
8004416: 681b ldr r3, [r3, #0]
8004418: f422 6280 bic.w r2, r2, #1024 @ 0x400
800441c: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
800441e: b672 cpsid i
}
8004420: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004422: 2300 movs r3, #0
8004424: 61bb str r3, [r7, #24]
8004426: 68fb ldr r3, [r7, #12]
8004428: 681b ldr r3, [r3, #0]
800442a: 695b ldr r3, [r3, #20]
800442c: 61bb str r3, [r7, #24]
800442e: 68fb ldr r3, [r7, #12]
8004430: 681b ldr r3, [r3, #0]
8004432: 699b ldr r3, [r3, #24]
8004434: 61bb str r3, [r7, #24]
8004436: 69bb ldr r3, [r7, #24]
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004438: 68fb ldr r3, [r7, #12]
800443a: 681b ldr r3, [r3, #0]
800443c: 681a ldr r2, [r3, #0]
800443e: 68fb ldr r3, [r7, #12]
8004440: 681b ldr r3, [r3, #0]
8004442: f442 7200 orr.w r2, r2, #512 @ 0x200
8004446: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
8004448: b662 cpsie i
}
800444a: e035 b.n 80044b8 <HAL_I2C_Master_Receive+0x1b4>
/* Re-enable IRQs */
__enable_irq();
}
else if (hi2c->XferSize == 2U)
800444c: 68fb ldr r3, [r7, #12]
800444e: 8d1b ldrh r3, [r3, #40] @ 0x28
8004450: 2b02 cmp r3, #2
8004452: d11e bne.n 8004492 <HAL_I2C_Master_Receive+0x18e>
{
/* Enable Pos */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
8004454: 68fb ldr r3, [r7, #12]
8004456: 681b ldr r3, [r3, #0]
8004458: 681a ldr r2, [r3, #0]
800445a: 68fb ldr r3, [r7, #12]
800445c: 681b ldr r3, [r3, #0]
800445e: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004462: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
8004464: b672 cpsid i
}
8004466: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
8004468: 2300 movs r3, #0
800446a: 617b str r3, [r7, #20]
800446c: 68fb ldr r3, [r7, #12]
800446e: 681b ldr r3, [r3, #0]
8004470: 695b ldr r3, [r3, #20]
8004472: 617b str r3, [r7, #20]
8004474: 68fb ldr r3, [r7, #12]
8004476: 681b ldr r3, [r3, #0]
8004478: 699b ldr r3, [r3, #24]
800447a: 617b str r3, [r7, #20]
800447c: 697b ldr r3, [r7, #20]
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
800447e: 68fb ldr r3, [r7, #12]
8004480: 681b ldr r3, [r3, #0]
8004482: 681a ldr r2, [r3, #0]
8004484: 68fb ldr r3, [r7, #12]
8004486: 681b ldr r3, [r3, #0]
8004488: f422 6280 bic.w r2, r2, #1024 @ 0x400
800448c: 601a str r2, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
800448e: b662 cpsie i
}
8004490: e012 b.n 80044b8 <HAL_I2C_Master_Receive+0x1b4>
__enable_irq();
}
else
{
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
8004492: 68fb ldr r3, [r7, #12]
8004494: 681b ldr r3, [r3, #0]
8004496: 681a ldr r2, [r3, #0]
8004498: 68fb ldr r3, [r7, #12]
800449a: 681b ldr r3, [r3, #0]
800449c: f442 6280 orr.w r2, r2, #1024 @ 0x400
80044a0: 601a str r2, [r3, #0]
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80044a2: 2300 movs r3, #0
80044a4: 613b str r3, [r7, #16]
80044a6: 68fb ldr r3, [r7, #12]
80044a8: 681b ldr r3, [r3, #0]
80044aa: 695b ldr r3, [r3, #20]
80044ac: 613b str r3, [r7, #16]
80044ae: 68fb ldr r3, [r7, #12]
80044b0: 681b ldr r3, [r3, #0]
80044b2: 699b ldr r3, [r3, #24]
80044b4: 613b str r3, [r7, #16]
80044b6: 693b ldr r3, [r7, #16]
}
while (hi2c->XferSize > 0U)
80044b8: e172 b.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize <= 3U)
80044ba: 68fb ldr r3, [r7, #12]
80044bc: 8d1b ldrh r3, [r3, #40] @ 0x28
80044be: 2b03 cmp r3, #3
80044c0: f200 811f bhi.w 8004702 <HAL_I2C_Master_Receive+0x3fe>
{
/* One byte */
if (hi2c->XferSize == 1U)
80044c4: 68fb ldr r3, [r7, #12]
80044c6: 8d1b ldrh r3, [r3, #40] @ 0x28
80044c8: 2b01 cmp r3, #1
80044ca: d123 bne.n 8004514 <HAL_I2C_Master_Receive+0x210>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
80044cc: 6a7a ldr r2, [r7, #36] @ 0x24
80044ce: 6b39 ldr r1, [r7, #48] @ 0x30
80044d0: 68f8 ldr r0, [r7, #12]
80044d2: f000 fc7d bl 8004dd0 <I2C_WaitOnRXNEFlagUntilTimeout>
80044d6: 4603 mov r3, r0
80044d8: 2b00 cmp r3, #0
80044da: d001 beq.n 80044e0 <HAL_I2C_Master_Receive+0x1dc>
{
return HAL_ERROR;
80044dc: 2301 movs r3, #1
80044de: e173 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80044e0: 68fb ldr r3, [r7, #12]
80044e2: 681b ldr r3, [r3, #0]
80044e4: 691a ldr r2, [r3, #16]
80044e6: 68fb ldr r3, [r7, #12]
80044e8: 6a5b ldr r3, [r3, #36] @ 0x24
80044ea: b2d2 uxtb r2, r2
80044ec: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 6a5b ldr r3, [r3, #36] @ 0x24
80044f2: 1c5a adds r2, r3, #1
80044f4: 68fb ldr r3, [r7, #12]
80044f6: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80044f8: 68fb ldr r3, [r7, #12]
80044fa: 8d1b ldrh r3, [r3, #40] @ 0x28
80044fc: 3b01 subs r3, #1
80044fe: b29a uxth r2, r3
8004500: 68fb ldr r3, [r7, #12]
8004502: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004504: 68fb ldr r3, [r7, #12]
8004506: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004508: b29b uxth r3, r3
800450a: 3b01 subs r3, #1
800450c: b29a uxth r2, r3
800450e: 68fb ldr r3, [r7, #12]
8004510: 855a strh r2, [r3, #42] @ 0x2a
8004512: e145 b.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
}
/* Two bytes */
else if (hi2c->XferSize == 2U)
8004514: 68fb ldr r3, [r7, #12]
8004516: 8d1b ldrh r3, [r3, #40] @ 0x28
8004518: 2b02 cmp r3, #2
800451a: d152 bne.n 80045c2 <HAL_I2C_Master_Receive+0x2be>
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
800451c: 6a7b ldr r3, [r7, #36] @ 0x24
800451e: 9300 str r3, [sp, #0]
8004520: 6b3b ldr r3, [r7, #48] @ 0x30
8004522: 2200 movs r2, #0
8004524: 4906 ldr r1, [pc, #24] @ (8004540 <HAL_I2C_Master_Receive+0x23c>)
8004526: 68f8 ldr r0, [r7, #12]
8004528: f000 faa8 bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
800452c: 4603 mov r3, r0
800452e: 2b00 cmp r3, #0
8004530: d008 beq.n 8004544 <HAL_I2C_Master_Receive+0x240>
{
return HAL_ERROR;
8004532: 2301 movs r3, #1
8004534: e148 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
8004536: bf00 nop
8004538: 00100002 .word 0x00100002
800453c: ffff0000 .word 0xffff0000
8004540: 00010004 .word 0x00010004
__ASM volatile ("cpsid i" : : : "memory");
8004544: b672 cpsid i
}
8004546: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004548: 68fb ldr r3, [r7, #12]
800454a: 681b ldr r3, [r3, #0]
800454c: 681a ldr r2, [r3, #0]
800454e: 68fb ldr r3, [r7, #12]
8004550: 681b ldr r3, [r3, #0]
8004552: f442 7200 orr.w r2, r2, #512 @ 0x200
8004556: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004558: 68fb ldr r3, [r7, #12]
800455a: 681b ldr r3, [r3, #0]
800455c: 691a ldr r2, [r3, #16]
800455e: 68fb ldr r3, [r7, #12]
8004560: 6a5b ldr r3, [r3, #36] @ 0x24
8004562: b2d2 uxtb r2, r2
8004564: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004566: 68fb ldr r3, [r7, #12]
8004568: 6a5b ldr r3, [r3, #36] @ 0x24
800456a: 1c5a adds r2, r3, #1
800456c: 68fb ldr r3, [r7, #12]
800456e: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004570: 68fb ldr r3, [r7, #12]
8004572: 8d1b ldrh r3, [r3, #40] @ 0x28
8004574: 3b01 subs r3, #1
8004576: b29a uxth r2, r3
8004578: 68fb ldr r3, [r7, #12]
800457a: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
800457c: 68fb ldr r3, [r7, #12]
800457e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004580: b29b uxth r3, r3
8004582: 3b01 subs r3, #1
8004584: b29a uxth r2, r3
8004586: 68fb ldr r3, [r7, #12]
8004588: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
800458a: b662 cpsie i
}
800458c: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800458e: 68fb ldr r3, [r7, #12]
8004590: 681b ldr r3, [r3, #0]
8004592: 691a ldr r2, [r3, #16]
8004594: 68fb ldr r3, [r7, #12]
8004596: 6a5b ldr r3, [r3, #36] @ 0x24
8004598: b2d2 uxtb r2, r2
800459a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800459c: 68fb ldr r3, [r7, #12]
800459e: 6a5b ldr r3, [r3, #36] @ 0x24
80045a0: 1c5a adds r2, r3, #1
80045a2: 68fb ldr r3, [r7, #12]
80045a4: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80045a6: 68fb ldr r3, [r7, #12]
80045a8: 8d1b ldrh r3, [r3, #40] @ 0x28
80045aa: 3b01 subs r3, #1
80045ac: b29a uxth r2, r3
80045ae: 68fb ldr r3, [r7, #12]
80045b0: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80045b2: 68fb ldr r3, [r7, #12]
80045b4: 8d5b ldrh r3, [r3, #42] @ 0x2a
80045b6: b29b uxth r3, r3
80045b8: 3b01 subs r3, #1
80045ba: b29a uxth r2, r3
80045bc: 68fb ldr r3, [r7, #12]
80045be: 855a strh r2, [r3, #42] @ 0x2a
80045c0: e0ee b.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
80045c2: 6a7b ldr r3, [r7, #36] @ 0x24
80045c4: 9300 str r3, [sp, #0]
80045c6: 6b3b ldr r3, [r7, #48] @ 0x30
80045c8: 2200 movs r2, #0
80045ca: 4981 ldr r1, [pc, #516] @ (80047d0 <HAL_I2C_Master_Receive+0x4cc>)
80045cc: 68f8 ldr r0, [r7, #12]
80045ce: f000 fa55 bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
80045d2: 4603 mov r3, r0
80045d4: 2b00 cmp r3, #0
80045d6: d001 beq.n 80045dc <HAL_I2C_Master_Receive+0x2d8>
{
return HAL_ERROR;
80045d8: 2301 movs r3, #1
80045da: e0f5 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80045dc: 68fb ldr r3, [r7, #12]
80045de: 681b ldr r3, [r3, #0]
80045e0: 681a ldr r2, [r3, #0]
80045e2: 68fb ldr r3, [r7, #12]
80045e4: 681b ldr r3, [r3, #0]
80045e6: f422 6280 bic.w r2, r2, #1024 @ 0x400
80045ea: 601a str r2, [r3, #0]
__ASM volatile ("cpsid i" : : : "memory");
80045ec: b672 cpsid i
}
80045ee: bf00 nop
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80045f0: 68fb ldr r3, [r7, #12]
80045f2: 681b ldr r3, [r3, #0]
80045f4: 691a ldr r2, [r3, #16]
80045f6: 68fb ldr r3, [r7, #12]
80045f8: 6a5b ldr r3, [r3, #36] @ 0x24
80045fa: b2d2 uxtb r2, r2
80045fc: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80045fe: 68fb ldr r3, [r7, #12]
8004600: 6a5b ldr r3, [r3, #36] @ 0x24
8004602: 1c5a adds r2, r3, #1
8004604: 68fb ldr r3, [r7, #12]
8004606: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004608: 68fb ldr r3, [r7, #12]
800460a: 8d1b ldrh r3, [r3, #40] @ 0x28
800460c: 3b01 subs r3, #1
800460e: b29a uxth r2, r3
8004610: 68fb ldr r3, [r7, #12]
8004612: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004614: 68fb ldr r3, [r7, #12]
8004616: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004618: b29b uxth r3, r3
800461a: 3b01 subs r3, #1
800461c: b29a uxth r2, r3
800461e: 68fb ldr r3, [r7, #12]
8004620: 855a strh r2, [r3, #42] @ 0x2a
/* Wait until BTF flag is set */
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
8004622: 4b6c ldr r3, [pc, #432] @ (80047d4 <HAL_I2C_Master_Receive+0x4d0>)
8004624: 681b ldr r3, [r3, #0]
8004626: 08db lsrs r3, r3, #3
8004628: 4a6b ldr r2, [pc, #428] @ (80047d8 <HAL_I2C_Master_Receive+0x4d4>)
800462a: fba2 2303 umull r2, r3, r2, r3
800462e: 0a1a lsrs r2, r3, #8
8004630: 4613 mov r3, r2
8004632: 009b lsls r3, r3, #2
8004634: 4413 add r3, r2
8004636: 00da lsls r2, r3, #3
8004638: 1ad3 subs r3, r2, r3
800463a: 623b str r3, [r7, #32]
do
{
count--;
800463c: 6a3b ldr r3, [r7, #32]
800463e: 3b01 subs r3, #1
8004640: 623b str r3, [r7, #32]
if (count == 0U)
8004642: 6a3b ldr r3, [r7, #32]
8004644: 2b00 cmp r3, #0
8004646: d118 bne.n 800467a <HAL_I2C_Master_Receive+0x376>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004648: 68fb ldr r3, [r7, #12]
800464a: 2200 movs r2, #0
800464c: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
800464e: 68fb ldr r3, [r7, #12]
8004650: 2220 movs r2, #32
8004652: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004656: 68fb ldr r3, [r7, #12]
8004658: 2200 movs r2, #0
800465a: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
800465e: 68fb ldr r3, [r7, #12]
8004660: 6c1b ldr r3, [r3, #64] @ 0x40
8004662: f043 0220 orr.w r2, r3, #32
8004666: 68fb ldr r3, [r7, #12]
8004668: 641a str r2, [r3, #64] @ 0x40
__ASM volatile ("cpsie i" : : : "memory");
800466a: b662 cpsie i
}
800466c: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800466e: 68fb ldr r3, [r7, #12]
8004670: 2200 movs r2, #0
8004672: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004676: 2301 movs r3, #1
8004678: e0a6 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
800467a: 68fb ldr r3, [r7, #12]
800467c: 681b ldr r3, [r3, #0]
800467e: 695b ldr r3, [r3, #20]
8004680: f003 0304 and.w r3, r3, #4
8004684: 2b04 cmp r3, #4
8004686: d1d9 bne.n 800463c <HAL_I2C_Master_Receive+0x338>
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004688: 68fb ldr r3, [r7, #12]
800468a: 681b ldr r3, [r3, #0]
800468c: 681a ldr r2, [r3, #0]
800468e: 68fb ldr r3, [r7, #12]
8004690: 681b ldr r3, [r3, #0]
8004692: f442 7200 orr.w r2, r2, #512 @ 0x200
8004696: 601a str r2, [r3, #0]
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004698: 68fb ldr r3, [r7, #12]
800469a: 681b ldr r3, [r3, #0]
800469c: 691a ldr r2, [r3, #16]
800469e: 68fb ldr r3, [r7, #12]
80046a0: 6a5b ldr r3, [r3, #36] @ 0x24
80046a2: b2d2 uxtb r2, r2
80046a4: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80046a6: 68fb ldr r3, [r7, #12]
80046a8: 6a5b ldr r3, [r3, #36] @ 0x24
80046aa: 1c5a adds r2, r3, #1
80046ac: 68fb ldr r3, [r7, #12]
80046ae: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80046b0: 68fb ldr r3, [r7, #12]
80046b2: 8d1b ldrh r3, [r3, #40] @ 0x28
80046b4: 3b01 subs r3, #1
80046b6: b29a uxth r2, r3
80046b8: 68fb ldr r3, [r7, #12]
80046ba: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80046bc: 68fb ldr r3, [r7, #12]
80046be: 8d5b ldrh r3, [r3, #42] @ 0x2a
80046c0: b29b uxth r3, r3
80046c2: 3b01 subs r3, #1
80046c4: b29a uxth r2, r3
80046c6: 68fb ldr r3, [r7, #12]
80046c8: 855a strh r2, [r3, #42] @ 0x2a
__ASM volatile ("cpsie i" : : : "memory");
80046ca: b662 cpsie i
}
80046cc: bf00 nop
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
80046ce: 68fb ldr r3, [r7, #12]
80046d0: 681b ldr r3, [r3, #0]
80046d2: 691a ldr r2, [r3, #16]
80046d4: 68fb ldr r3, [r7, #12]
80046d6: 6a5b ldr r3, [r3, #36] @ 0x24
80046d8: b2d2 uxtb r2, r2
80046da: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80046dc: 68fb ldr r3, [r7, #12]
80046de: 6a5b ldr r3, [r3, #36] @ 0x24
80046e0: 1c5a adds r2, r3, #1
80046e2: 68fb ldr r3, [r7, #12]
80046e4: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
80046e6: 68fb ldr r3, [r7, #12]
80046e8: 8d1b ldrh r3, [r3, #40] @ 0x28
80046ea: 3b01 subs r3, #1
80046ec: b29a uxth r2, r3
80046ee: 68fb ldr r3, [r7, #12]
80046f0: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80046f2: 68fb ldr r3, [r7, #12]
80046f4: 8d5b ldrh r3, [r3, #42] @ 0x2a
80046f6: b29b uxth r3, r3
80046f8: 3b01 subs r3, #1
80046fa: b29a uxth r2, r3
80046fc: 68fb ldr r3, [r7, #12]
80046fe: 855a strh r2, [r3, #42] @ 0x2a
8004700: e04e b.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
}
}
else
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004702: 6a7a ldr r2, [r7, #36] @ 0x24
8004704: 6b39 ldr r1, [r7, #48] @ 0x30
8004706: 68f8 ldr r0, [r7, #12]
8004708: f000 fb62 bl 8004dd0 <I2C_WaitOnRXNEFlagUntilTimeout>
800470c: 4603 mov r3, r0
800470e: 2b00 cmp r3, #0
8004710: d001 beq.n 8004716 <HAL_I2C_Master_Receive+0x412>
{
return HAL_ERROR;
8004712: 2301 movs r3, #1
8004714: e058 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
8004716: 68fb ldr r3, [r7, #12]
8004718: 681b ldr r3, [r3, #0]
800471a: 691a ldr r2, [r3, #16]
800471c: 68fb ldr r3, [r7, #12]
800471e: 6a5b ldr r3, [r3, #36] @ 0x24
8004720: b2d2 uxtb r2, r2
8004722: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004724: 68fb ldr r3, [r7, #12]
8004726: 6a5b ldr r3, [r3, #36] @ 0x24
8004728: 1c5a adds r2, r3, #1
800472a: 68fb ldr r3, [r7, #12]
800472c: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
800472e: 68fb ldr r3, [r7, #12]
8004730: 8d1b ldrh r3, [r3, #40] @ 0x28
8004732: 3b01 subs r3, #1
8004734: b29a uxth r2, r3
8004736: 68fb ldr r3, [r7, #12]
8004738: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
800473a: 68fb ldr r3, [r7, #12]
800473c: 8d5b ldrh r3, [r3, #42] @ 0x2a
800473e: b29b uxth r3, r3
8004740: 3b01 subs r3, #1
8004742: b29a uxth r2, r3
8004744: 68fb ldr r3, [r7, #12]
8004746: 855a strh r2, [r3, #42] @ 0x2a
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
8004748: 68fb ldr r3, [r7, #12]
800474a: 681b ldr r3, [r3, #0]
800474c: 695b ldr r3, [r3, #20]
800474e: f003 0304 and.w r3, r3, #4
8004752: 2b04 cmp r3, #4
8004754: d124 bne.n 80047a0 <HAL_I2C_Master_Receive+0x49c>
{
if (hi2c->XferSize == 3U)
8004756: 68fb ldr r3, [r7, #12]
8004758: 8d1b ldrh r3, [r3, #40] @ 0x28
800475a: 2b03 cmp r3, #3
800475c: d107 bne.n 800476e <HAL_I2C_Master_Receive+0x46a>
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
800475e: 68fb ldr r3, [r7, #12]
8004760: 681b ldr r3, [r3, #0]
8004762: 681a ldr r2, [r3, #0]
8004764: 68fb ldr r3, [r7, #12]
8004766: 681b ldr r3, [r3, #0]
8004768: f422 6280 bic.w r2, r2, #1024 @ 0x400
800476c: 601a str r2, [r3, #0]
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
800476e: 68fb ldr r3, [r7, #12]
8004770: 681b ldr r3, [r3, #0]
8004772: 691a ldr r2, [r3, #16]
8004774: 68fb ldr r3, [r7, #12]
8004776: 6a5b ldr r3, [r3, #36] @ 0x24
8004778: b2d2 uxtb r2, r2
800477a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800477c: 68fb ldr r3, [r7, #12]
800477e: 6a5b ldr r3, [r3, #36] @ 0x24
8004780: 1c5a adds r2, r3, #1
8004782: 68fb ldr r3, [r7, #12]
8004784: 625a str r2, [r3, #36] @ 0x24
/* Update counter */
hi2c->XferSize--;
8004786: 68fb ldr r3, [r7, #12]
8004788: 8d1b ldrh r3, [r3, #40] @ 0x28
800478a: 3b01 subs r3, #1
800478c: b29a uxth r2, r3
800478e: 68fb ldr r3, [r7, #12]
8004790: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8004792: 68fb ldr r3, [r7, #12]
8004794: 8d5b ldrh r3, [r3, #42] @ 0x2a
8004796: b29b uxth r3, r3
8004798: 3b01 subs r3, #1
800479a: b29a uxth r2, r3
800479c: 68fb ldr r3, [r7, #12]
800479e: 855a strh r2, [r3, #42] @ 0x2a
while (hi2c->XferSize > 0U)
80047a0: 68fb ldr r3, [r7, #12]
80047a2: 8d1b ldrh r3, [r3, #40] @ 0x28
80047a4: 2b00 cmp r3, #0
80047a6: f47f ae88 bne.w 80044ba <HAL_I2C_Master_Receive+0x1b6>
}
}
}
hi2c->State = HAL_I2C_STATE_READY;
80047aa: 68fb ldr r3, [r7, #12]
80047ac: 2220 movs r2, #32
80047ae: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
80047b2: 68fb ldr r3, [r7, #12]
80047b4: 2200 movs r2, #0
80047b6: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80047ba: 68fb ldr r3, [r7, #12]
80047bc: 2200 movs r2, #0
80047be: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80047c2: 2300 movs r3, #0
80047c4: e000 b.n 80047c8 <HAL_I2C_Master_Receive+0x4c4>
}
else
{
return HAL_BUSY;
80047c6: 2302 movs r3, #2
}
}
80047c8: 4618 mov r0, r3
80047ca: 3728 adds r7, #40 @ 0x28
80047cc: 46bd mov sp, r7
80047ce: bd80 pop {r7, pc}
80047d0: 00010004 .word 0x00010004
80047d4: 20000034 .word 0x20000034
80047d8: 14f8b589 .word 0x14f8b589
080047dc <I2C_MasterRequestWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
80047dc: b580 push {r7, lr}
80047de: b088 sub sp, #32
80047e0: af02 add r7, sp, #8
80047e2: 60f8 str r0, [r7, #12]
80047e4: 607a str r2, [r7, #4]
80047e6: 603b str r3, [r7, #0]
80047e8: 460b mov r3, r1
80047ea: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
80047ec: 68fb ldr r3, [r7, #12]
80047ee: 6adb ldr r3, [r3, #44] @ 0x2c
80047f0: 617b str r3, [r7, #20]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
80047f2: 697b ldr r3, [r7, #20]
80047f4: 2b08 cmp r3, #8
80047f6: d006 beq.n 8004806 <I2C_MasterRequestWrite+0x2a>
80047f8: 697b ldr r3, [r7, #20]
80047fa: 2b01 cmp r3, #1
80047fc: d003 beq.n 8004806 <I2C_MasterRequestWrite+0x2a>
80047fe: 697b ldr r3, [r7, #20]
8004800: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004804: d108 bne.n 8004818 <I2C_MasterRequestWrite+0x3c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004806: 68fb ldr r3, [r7, #12]
8004808: 681b ldr r3, [r3, #0]
800480a: 681a ldr r2, [r3, #0]
800480c: 68fb ldr r3, [r7, #12]
800480e: 681b ldr r3, [r3, #0]
8004810: f442 7280 orr.w r2, r2, #256 @ 0x100
8004814: 601a str r2, [r3, #0]
8004816: e00b b.n 8004830 <I2C_MasterRequestWrite+0x54>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
8004818: 68fb ldr r3, [r7, #12]
800481a: 6b1b ldr r3, [r3, #48] @ 0x30
800481c: 2b12 cmp r3, #18
800481e: d107 bne.n 8004830 <I2C_MasterRequestWrite+0x54>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004820: 68fb ldr r3, [r7, #12]
8004822: 681b ldr r3, [r3, #0]
8004824: 681a ldr r2, [r3, #0]
8004826: 68fb ldr r3, [r7, #12]
8004828: 681b ldr r3, [r3, #0]
800482a: f442 7280 orr.w r2, r2, #256 @ 0x100
800482e: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
8004830: 683b ldr r3, [r7, #0]
8004832: 9300 str r3, [sp, #0]
8004834: 687b ldr r3, [r7, #4]
8004836: 2200 movs r2, #0
8004838: f04f 1101 mov.w r1, #65537 @ 0x10001
800483c: 68f8 ldr r0, [r7, #12]
800483e: f000 f91d bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
8004842: 4603 mov r3, r0
8004844: 2b00 cmp r3, #0
8004846: d00d beq.n 8004864 <I2C_MasterRequestWrite+0x88>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
8004848: 68fb ldr r3, [r7, #12]
800484a: 681b ldr r3, [r3, #0]
800484c: 681b ldr r3, [r3, #0]
800484e: f403 7380 and.w r3, r3, #256 @ 0x100
8004852: f5b3 7f80 cmp.w r3, #256 @ 0x100
8004856: d103 bne.n 8004860 <I2C_MasterRequestWrite+0x84>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
8004858: 68fb ldr r3, [r7, #12]
800485a: f44f 7200 mov.w r2, #512 @ 0x200
800485e: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
8004860: 2303 movs r3, #3
8004862: e035 b.n 80048d0 <I2C_MasterRequestWrite+0xf4>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8004864: 68fb ldr r3, [r7, #12]
8004866: 691b ldr r3, [r3, #16]
8004868: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
800486c: d108 bne.n 8004880 <I2C_MasterRequestWrite+0xa4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
800486e: 897b ldrh r3, [r7, #10]
8004870: b2db uxtb r3, r3
8004872: 461a mov r2, r3
8004874: 68fb ldr r3, [r7, #12]
8004876: 681b ldr r3, [r3, #0]
8004878: f002 02fe and.w r2, r2, #254 @ 0xfe
800487c: 611a str r2, [r3, #16]
800487e: e01b b.n 80048b8 <I2C_MasterRequestWrite+0xdc>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004880: 897b ldrh r3, [r7, #10]
8004882: 11db asrs r3, r3, #7
8004884: b2db uxtb r3, r3
8004886: f003 0306 and.w r3, r3, #6
800488a: b2db uxtb r3, r3
800488c: f063 030f orn r3, r3, #15
8004890: b2da uxtb r2, r3
8004892: 68fb ldr r3, [r7, #12]
8004894: 681b ldr r3, [r3, #0]
8004896: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
8004898: 683b ldr r3, [r7, #0]
800489a: 687a ldr r2, [r7, #4]
800489c: 490e ldr r1, [pc, #56] @ (80048d8 <I2C_MasterRequestWrite+0xfc>)
800489e: 68f8 ldr r0, [r7, #12]
80048a0: f000 f966 bl 8004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80048a4: 4603 mov r3, r0
80048a6: 2b00 cmp r3, #0
80048a8: d001 beq.n 80048ae <I2C_MasterRequestWrite+0xd2>
{
return HAL_ERROR;
80048aa: 2301 movs r3, #1
80048ac: e010 b.n 80048d0 <I2C_MasterRequestWrite+0xf4>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
80048ae: 897b ldrh r3, [r7, #10]
80048b0: b2da uxtb r2, r3
80048b2: 68fb ldr r3, [r7, #12]
80048b4: 681b ldr r3, [r3, #0]
80048b6: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
80048b8: 683b ldr r3, [r7, #0]
80048ba: 687a ldr r2, [r7, #4]
80048bc: 4907 ldr r1, [pc, #28] @ (80048dc <I2C_MasterRequestWrite+0x100>)
80048be: 68f8 ldr r0, [r7, #12]
80048c0: f000 f956 bl 8004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80048c4: 4603 mov r3, r0
80048c6: 2b00 cmp r3, #0
80048c8: d001 beq.n 80048ce <I2C_MasterRequestWrite+0xf2>
{
return HAL_ERROR;
80048ca: 2301 movs r3, #1
80048cc: e000 b.n 80048d0 <I2C_MasterRequestWrite+0xf4>
}
return HAL_OK;
80048ce: 2300 movs r3, #0
}
80048d0: 4618 mov r0, r3
80048d2: 3718 adds r7, #24
80048d4: 46bd mov sp, r7
80048d6: bd80 pop {r7, pc}
80048d8: 00010008 .word 0x00010008
80048dc: 00010002 .word 0x00010002
080048e0 <I2C_MasterRequestRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
80048e0: b580 push {r7, lr}
80048e2: b088 sub sp, #32
80048e4: af02 add r7, sp, #8
80048e6: 60f8 str r0, [r7, #12]
80048e8: 607a str r2, [r7, #4]
80048ea: 603b str r3, [r7, #0]
80048ec: 460b mov r3, r1
80048ee: 817b strh r3, [r7, #10]
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
80048f0: 68fb ldr r3, [r7, #12]
80048f2: 6adb ldr r3, [r3, #44] @ 0x2c
80048f4: 617b str r3, [r7, #20]
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
80048f6: 68fb ldr r3, [r7, #12]
80048f8: 681b ldr r3, [r3, #0]
80048fa: 681a ldr r2, [r3, #0]
80048fc: 68fb ldr r3, [r7, #12]
80048fe: 681b ldr r3, [r3, #0]
8004900: f442 6280 orr.w r2, r2, #1024 @ 0x400
8004904: 601a str r2, [r3, #0]
/* Generate Start condition if first transfer */
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
8004906: 697b ldr r3, [r7, #20]
8004908: 2b08 cmp r3, #8
800490a: d006 beq.n 800491a <I2C_MasterRequestRead+0x3a>
800490c: 697b ldr r3, [r7, #20]
800490e: 2b01 cmp r3, #1
8004910: d003 beq.n 800491a <I2C_MasterRequestRead+0x3a>
8004912: 697b ldr r3, [r7, #20]
8004914: f513 3f80 cmn.w r3, #65536 @ 0x10000
8004918: d108 bne.n 800492c <I2C_MasterRequestRead+0x4c>
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
800491a: 68fb ldr r3, [r7, #12]
800491c: 681b ldr r3, [r3, #0]
800491e: 681a ldr r2, [r3, #0]
8004920: 68fb ldr r3, [r7, #12]
8004922: 681b ldr r3, [r3, #0]
8004924: f442 7280 orr.w r2, r2, #256 @ 0x100
8004928: 601a str r2, [r3, #0]
800492a: e00b b.n 8004944 <I2C_MasterRequestRead+0x64>
}
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
800492c: 68fb ldr r3, [r7, #12]
800492e: 6b1b ldr r3, [r3, #48] @ 0x30
8004930: 2b11 cmp r3, #17
8004932: d107 bne.n 8004944 <I2C_MasterRequestRead+0x64>
{
/* Generate ReStart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
8004934: 68fb ldr r3, [r7, #12]
8004936: 681b ldr r3, [r3, #0]
8004938: 681a ldr r2, [r3, #0]
800493a: 68fb ldr r3, [r7, #12]
800493c: 681b ldr r3, [r3, #0]
800493e: f442 7280 orr.w r2, r2, #256 @ 0x100
8004942: 601a str r2, [r3, #0]
{
/* Do nothing */
}
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
8004944: 683b ldr r3, [r7, #0]
8004946: 9300 str r3, [sp, #0]
8004948: 687b ldr r3, [r7, #4]
800494a: 2200 movs r2, #0
800494c: f04f 1101 mov.w r1, #65537 @ 0x10001
8004950: 68f8 ldr r0, [r7, #12]
8004952: f000 f893 bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
8004956: 4603 mov r3, r0
8004958: 2b00 cmp r3, #0
800495a: d00d beq.n 8004978 <I2C_MasterRequestRead+0x98>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
800495c: 68fb ldr r3, [r7, #12]
800495e: 681b ldr r3, [r3, #0]
8004960: 681b ldr r3, [r3, #0]
8004962: f403 7380 and.w r3, r3, #256 @ 0x100
8004966: f5b3 7f80 cmp.w r3, #256 @ 0x100
800496a: d103 bne.n 8004974 <I2C_MasterRequestRead+0x94>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
800496c: 68fb ldr r3, [r7, #12]
800496e: f44f 7200 mov.w r2, #512 @ 0x200
8004972: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
8004974: 2303 movs r3, #3
8004976: e079 b.n 8004a6c <I2C_MasterRequestRead+0x18c>
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8004978: 68fb ldr r3, [r7, #12]
800497a: 691b ldr r3, [r3, #16]
800497c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8004980: d108 bne.n 8004994 <I2C_MasterRequestRead+0xb4>
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
8004982: 897b ldrh r3, [r7, #10]
8004984: b2db uxtb r3, r3
8004986: f043 0301 orr.w r3, r3, #1
800498a: b2da uxtb r2, r3
800498c: 68fb ldr r3, [r7, #12]
800498e: 681b ldr r3, [r3, #0]
8004990: 611a str r2, [r3, #16]
8004992: e05f b.n 8004a54 <I2C_MasterRequestRead+0x174>
}
else
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
8004994: 897b ldrh r3, [r7, #10]
8004996: 11db asrs r3, r3, #7
8004998: b2db uxtb r3, r3
800499a: f003 0306 and.w r3, r3, #6
800499e: b2db uxtb r3, r3
80049a0: f063 030f orn r3, r3, #15
80049a4: b2da uxtb r2, r3
80049a6: 68fb ldr r3, [r7, #12]
80049a8: 681b ldr r3, [r3, #0]
80049aa: 611a str r2, [r3, #16]
/* Wait until ADD10 flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
80049ac: 683b ldr r3, [r7, #0]
80049ae: 687a ldr r2, [r7, #4]
80049b0: 4930 ldr r1, [pc, #192] @ (8004a74 <I2C_MasterRequestRead+0x194>)
80049b2: 68f8 ldr r0, [r7, #12]
80049b4: f000 f8dc bl 8004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80049b8: 4603 mov r3, r0
80049ba: 2b00 cmp r3, #0
80049bc: d001 beq.n 80049c2 <I2C_MasterRequestRead+0xe2>
{
return HAL_ERROR;
80049be: 2301 movs r3, #1
80049c0: e054 b.n 8004a6c <I2C_MasterRequestRead+0x18c>
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
80049c2: 897b ldrh r3, [r7, #10]
80049c4: b2da uxtb r2, r3
80049c6: 68fb ldr r3, [r7, #12]
80049c8: 681b ldr r3, [r3, #0]
80049ca: 611a str r2, [r3, #16]
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
80049cc: 683b ldr r3, [r7, #0]
80049ce: 687a ldr r2, [r7, #4]
80049d0: 4929 ldr r1, [pc, #164] @ (8004a78 <I2C_MasterRequestRead+0x198>)
80049d2: 68f8 ldr r0, [r7, #12]
80049d4: f000 f8cc bl 8004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>
80049d8: 4603 mov r3, r0
80049da: 2b00 cmp r3, #0
80049dc: d001 beq.n 80049e2 <I2C_MasterRequestRead+0x102>
{
return HAL_ERROR;
80049de: 2301 movs r3, #1
80049e0: e044 b.n 8004a6c <I2C_MasterRequestRead+0x18c>
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
80049e2: 2300 movs r3, #0
80049e4: 613b str r3, [r7, #16]
80049e6: 68fb ldr r3, [r7, #12]
80049e8: 681b ldr r3, [r3, #0]
80049ea: 695b ldr r3, [r3, #20]
80049ec: 613b str r3, [r7, #16]
80049ee: 68fb ldr r3, [r7, #12]
80049f0: 681b ldr r3, [r3, #0]
80049f2: 699b ldr r3, [r3, #24]
80049f4: 613b str r3, [r7, #16]
80049f6: 693b ldr r3, [r7, #16]
/* Generate Restart */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
80049f8: 68fb ldr r3, [r7, #12]
80049fa: 681b ldr r3, [r3, #0]
80049fc: 681a ldr r2, [r3, #0]
80049fe: 68fb ldr r3, [r7, #12]
8004a00: 681b ldr r3, [r3, #0]
8004a02: f442 7280 orr.w r2, r2, #256 @ 0x100
8004a06: 601a str r2, [r3, #0]
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
8004a08: 683b ldr r3, [r7, #0]
8004a0a: 9300 str r3, [sp, #0]
8004a0c: 687b ldr r3, [r7, #4]
8004a0e: 2200 movs r2, #0
8004a10: f04f 1101 mov.w r1, #65537 @ 0x10001
8004a14: 68f8 ldr r0, [r7, #12]
8004a16: f000 f831 bl 8004a7c <I2C_WaitOnFlagUntilTimeout>
8004a1a: 4603 mov r3, r0
8004a1c: 2b00 cmp r3, #0
8004a1e: d00d beq.n 8004a3c <I2C_MasterRequestRead+0x15c>
{
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
8004a20: 68fb ldr r3, [r7, #12]
8004a22: 681b ldr r3, [r3, #0]
8004a24: 681b ldr r3, [r3, #0]
8004a26: f403 7380 and.w r3, r3, #256 @ 0x100
8004a2a: f5b3 7f80 cmp.w r3, #256 @ 0x100
8004a2e: d103 bne.n 8004a38 <I2C_MasterRequestRead+0x158>
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
8004a30: 68fb ldr r3, [r7, #12]
8004a32: f44f 7200 mov.w r2, #512 @ 0x200
8004a36: 641a str r2, [r3, #64] @ 0x40
}
return HAL_TIMEOUT;
8004a38: 2303 movs r3, #3
8004a3a: e017 b.n 8004a6c <I2C_MasterRequestRead+0x18c>
}
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
8004a3c: 897b ldrh r3, [r7, #10]
8004a3e: 11db asrs r3, r3, #7
8004a40: b2db uxtb r3, r3
8004a42: f003 0306 and.w r3, r3, #6
8004a46: b2db uxtb r3, r3
8004a48: f063 030e orn r3, r3, #14
8004a4c: b2da uxtb r2, r3
8004a4e: 68fb ldr r3, [r7, #12]
8004a50: 681b ldr r3, [r3, #0]
8004a52: 611a str r2, [r3, #16]
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
8004a54: 683b ldr r3, [r7, #0]
8004a56: 687a ldr r2, [r7, #4]
8004a58: 4907 ldr r1, [pc, #28] @ (8004a78 <I2C_MasterRequestRead+0x198>)
8004a5a: 68f8 ldr r0, [r7, #12]
8004a5c: f000 f888 bl 8004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>
8004a60: 4603 mov r3, r0
8004a62: 2b00 cmp r3, #0
8004a64: d001 beq.n 8004a6a <I2C_MasterRequestRead+0x18a>
{
return HAL_ERROR;
8004a66: 2301 movs r3, #1
8004a68: e000 b.n 8004a6c <I2C_MasterRequestRead+0x18c>
}
return HAL_OK;
8004a6a: 2300 movs r3, #0
}
8004a6c: 4618 mov r0, r3
8004a6e: 3718 adds r7, #24
8004a70: 46bd mov sp, r7
8004a72: bd80 pop {r7, pc}
8004a74: 00010008 .word 0x00010008
8004a78: 00010002 .word 0x00010002
08004a7c <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
8004a7c: b580 push {r7, lr}
8004a7e: b084 sub sp, #16
8004a80: af00 add r7, sp, #0
8004a82: 60f8 str r0, [r7, #12]
8004a84: 60b9 str r1, [r7, #8]
8004a86: 603b str r3, [r7, #0]
8004a88: 4613 mov r3, r2
8004a8a: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8004a8c: e048 b.n 8004b20 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004a8e: 683b ldr r3, [r7, #0]
8004a90: f1b3 3fff cmp.w r3, #4294967295
8004a94: d044 beq.n 8004b20 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004a96: f7fe fa27 bl 8002ee8 <HAL_GetTick>
8004a9a: 4602 mov r2, r0
8004a9c: 69bb ldr r3, [r7, #24]
8004a9e: 1ad3 subs r3, r2, r3
8004aa0: 683a ldr r2, [r7, #0]
8004aa2: 429a cmp r2, r3
8004aa4: d302 bcc.n 8004aac <I2C_WaitOnFlagUntilTimeout+0x30>
8004aa6: 683b ldr r3, [r7, #0]
8004aa8: 2b00 cmp r3, #0
8004aaa: d139 bne.n 8004b20 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
8004aac: 68bb ldr r3, [r7, #8]
8004aae: 0c1b lsrs r3, r3, #16
8004ab0: b2db uxtb r3, r3
8004ab2: 2b01 cmp r3, #1
8004ab4: d10d bne.n 8004ad2 <I2C_WaitOnFlagUntilTimeout+0x56>
8004ab6: 68fb ldr r3, [r7, #12]
8004ab8: 681b ldr r3, [r3, #0]
8004aba: 695b ldr r3, [r3, #20]
8004abc: 43da mvns r2, r3
8004abe: 68bb ldr r3, [r7, #8]
8004ac0: 4013 ands r3, r2
8004ac2: b29b uxth r3, r3
8004ac4: 2b00 cmp r3, #0
8004ac6: bf0c ite eq
8004ac8: 2301 moveq r3, #1
8004aca: 2300 movne r3, #0
8004acc: b2db uxtb r3, r3
8004ace: 461a mov r2, r3
8004ad0: e00c b.n 8004aec <I2C_WaitOnFlagUntilTimeout+0x70>
8004ad2: 68fb ldr r3, [r7, #12]
8004ad4: 681b ldr r3, [r3, #0]
8004ad6: 699b ldr r3, [r3, #24]
8004ad8: 43da mvns r2, r3
8004ada: 68bb ldr r3, [r7, #8]
8004adc: 4013 ands r3, r2
8004ade: b29b uxth r3, r3
8004ae0: 2b00 cmp r3, #0
8004ae2: bf0c ite eq
8004ae4: 2301 moveq r3, #1
8004ae6: 2300 movne r3, #0
8004ae8: b2db uxtb r3, r3
8004aea: 461a mov r2, r3
8004aec: 79fb ldrb r3, [r7, #7]
8004aee: 429a cmp r2, r3
8004af0: d116 bne.n 8004b20 <I2C_WaitOnFlagUntilTimeout+0xa4>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004af2: 68fb ldr r3, [r7, #12]
8004af4: 2200 movs r2, #0
8004af6: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004af8: 68fb ldr r3, [r7, #12]
8004afa: 2220 movs r2, #32
8004afc: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004b00: 68fb ldr r3, [r7, #12]
8004b02: 2200 movs r2, #0
8004b04: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004b08: 68fb ldr r3, [r7, #12]
8004b0a: 6c1b ldr r3, [r3, #64] @ 0x40
8004b0c: f043 0220 orr.w r2, r3, #32
8004b10: 68fb ldr r3, [r7, #12]
8004b12: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004b14: 68fb ldr r3, [r7, #12]
8004b16: 2200 movs r2, #0
8004b18: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004b1c: 2301 movs r3, #1
8004b1e: e023 b.n 8004b68 <I2C_WaitOnFlagUntilTimeout+0xec>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8004b20: 68bb ldr r3, [r7, #8]
8004b22: 0c1b lsrs r3, r3, #16
8004b24: b2db uxtb r3, r3
8004b26: 2b01 cmp r3, #1
8004b28: d10d bne.n 8004b46 <I2C_WaitOnFlagUntilTimeout+0xca>
8004b2a: 68fb ldr r3, [r7, #12]
8004b2c: 681b ldr r3, [r3, #0]
8004b2e: 695b ldr r3, [r3, #20]
8004b30: 43da mvns r2, r3
8004b32: 68bb ldr r3, [r7, #8]
8004b34: 4013 ands r3, r2
8004b36: b29b uxth r3, r3
8004b38: 2b00 cmp r3, #0
8004b3a: bf0c ite eq
8004b3c: 2301 moveq r3, #1
8004b3e: 2300 movne r3, #0
8004b40: b2db uxtb r3, r3
8004b42: 461a mov r2, r3
8004b44: e00c b.n 8004b60 <I2C_WaitOnFlagUntilTimeout+0xe4>
8004b46: 68fb ldr r3, [r7, #12]
8004b48: 681b ldr r3, [r3, #0]
8004b4a: 699b ldr r3, [r3, #24]
8004b4c: 43da mvns r2, r3
8004b4e: 68bb ldr r3, [r7, #8]
8004b50: 4013 ands r3, r2
8004b52: b29b uxth r3, r3
8004b54: 2b00 cmp r3, #0
8004b56: bf0c ite eq
8004b58: 2301 moveq r3, #1
8004b5a: 2300 movne r3, #0
8004b5c: b2db uxtb r3, r3
8004b5e: 461a mov r2, r3
8004b60: 79fb ldrb r3, [r7, #7]
8004b62: 429a cmp r2, r3
8004b64: d093 beq.n 8004a8e <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8004b66: 2300 movs r3, #0
}
8004b68: 4618 mov r0, r3
8004b6a: 3710 adds r7, #16
8004b6c: 46bd mov sp, r7
8004b6e: bd80 pop {r7, pc}
08004b70 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
8004b70: b580 push {r7, lr}
8004b72: b084 sub sp, #16
8004b74: af00 add r7, sp, #0
8004b76: 60f8 str r0, [r7, #12]
8004b78: 60b9 str r1, [r7, #8]
8004b7a: 607a str r2, [r7, #4]
8004b7c: 603b str r3, [r7, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
8004b7e: e071 b.n 8004c64 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 681b ldr r3, [r3, #0]
8004b84: 695b ldr r3, [r3, #20]
8004b86: f403 6380 and.w r3, r3, #1024 @ 0x400
8004b8a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004b8e: d123 bne.n 8004bd8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
8004b90: 68fb ldr r3, [r7, #12]
8004b92: 681b ldr r3, [r3, #0]
8004b94: 681a ldr r2, [r3, #0]
8004b96: 68fb ldr r3, [r7, #12]
8004b98: 681b ldr r3, [r3, #0]
8004b9a: f442 7200 orr.w r2, r2, #512 @ 0x200
8004b9e: 601a str r2, [r3, #0]
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004ba0: 68fb ldr r3, [r7, #12]
8004ba2: 681b ldr r3, [r3, #0]
8004ba4: f46f 6280 mvn.w r2, #1024 @ 0x400
8004ba8: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004baa: 68fb ldr r3, [r7, #12]
8004bac: 2200 movs r2, #0
8004bae: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004bb0: 68fb ldr r3, [r7, #12]
8004bb2: 2220 movs r2, #32
8004bb4: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004bb8: 68fb ldr r3, [r7, #12]
8004bba: 2200 movs r2, #0
8004bbc: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004bc0: 68fb ldr r3, [r7, #12]
8004bc2: 6c1b ldr r3, [r3, #64] @ 0x40
8004bc4: f043 0204 orr.w r2, r3, #4
8004bc8: 68fb ldr r3, [r7, #12]
8004bca: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004bcc: 68fb ldr r3, [r7, #12]
8004bce: 2200 movs r2, #0
8004bd0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004bd4: 2301 movs r3, #1
8004bd6: e067 b.n 8004ca8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004bd8: 687b ldr r3, [r7, #4]
8004bda: f1b3 3fff cmp.w r3, #4294967295
8004bde: d041 beq.n 8004c64 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004be0: f7fe f982 bl 8002ee8 <HAL_GetTick>
8004be4: 4602 mov r2, r0
8004be6: 683b ldr r3, [r7, #0]
8004be8: 1ad3 subs r3, r2, r3
8004bea: 687a ldr r2, [r7, #4]
8004bec: 429a cmp r2, r3
8004bee: d302 bcc.n 8004bf6 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
8004bf0: 687b ldr r3, [r7, #4]
8004bf2: 2b00 cmp r3, #0
8004bf4: d136 bne.n 8004c64 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
8004bf6: 68bb ldr r3, [r7, #8]
8004bf8: 0c1b lsrs r3, r3, #16
8004bfa: b2db uxtb r3, r3
8004bfc: 2b01 cmp r3, #1
8004bfe: d10c bne.n 8004c1a <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
8004c00: 68fb ldr r3, [r7, #12]
8004c02: 681b ldr r3, [r3, #0]
8004c04: 695b ldr r3, [r3, #20]
8004c06: 43da mvns r2, r3
8004c08: 68bb ldr r3, [r7, #8]
8004c0a: 4013 ands r3, r2
8004c0c: b29b uxth r3, r3
8004c0e: 2b00 cmp r3, #0
8004c10: bf14 ite ne
8004c12: 2301 movne r3, #1
8004c14: 2300 moveq r3, #0
8004c16: b2db uxtb r3, r3
8004c18: e00b b.n 8004c32 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
8004c1a: 68fb ldr r3, [r7, #12]
8004c1c: 681b ldr r3, [r3, #0]
8004c1e: 699b ldr r3, [r3, #24]
8004c20: 43da mvns r2, r3
8004c22: 68bb ldr r3, [r7, #8]
8004c24: 4013 ands r3, r2
8004c26: b29b uxth r3, r3
8004c28: 2b00 cmp r3, #0
8004c2a: bf14 ite ne
8004c2c: 2301 movne r3, #1
8004c2e: 2300 moveq r3, #0
8004c30: b2db uxtb r3, r3
8004c32: 2b00 cmp r3, #0
8004c34: d016 beq.n 8004c64 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004c36: 68fb ldr r3, [r7, #12]
8004c38: 2200 movs r2, #0
8004c3a: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004c3c: 68fb ldr r3, [r7, #12]
8004c3e: 2220 movs r2, #32
8004c40: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004c44: 68fb ldr r3, [r7, #12]
8004c46: 2200 movs r2, #0
8004c48: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004c4c: 68fb ldr r3, [r7, #12]
8004c4e: 6c1b ldr r3, [r3, #64] @ 0x40
8004c50: f043 0220 orr.w r2, r3, #32
8004c54: 68fb ldr r3, [r7, #12]
8004c56: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004c58: 68fb ldr r3, [r7, #12]
8004c5a: 2200 movs r2, #0
8004c5c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004c60: 2301 movs r3, #1
8004c62: e021 b.n 8004ca8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
8004c64: 68bb ldr r3, [r7, #8]
8004c66: 0c1b lsrs r3, r3, #16
8004c68: b2db uxtb r3, r3
8004c6a: 2b01 cmp r3, #1
8004c6c: d10c bne.n 8004c88 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
8004c6e: 68fb ldr r3, [r7, #12]
8004c70: 681b ldr r3, [r3, #0]
8004c72: 695b ldr r3, [r3, #20]
8004c74: 43da mvns r2, r3
8004c76: 68bb ldr r3, [r7, #8]
8004c78: 4013 ands r3, r2
8004c7a: b29b uxth r3, r3
8004c7c: 2b00 cmp r3, #0
8004c7e: bf14 ite ne
8004c80: 2301 movne r3, #1
8004c82: 2300 moveq r3, #0
8004c84: b2db uxtb r3, r3
8004c86: e00b b.n 8004ca0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
8004c88: 68fb ldr r3, [r7, #12]
8004c8a: 681b ldr r3, [r3, #0]
8004c8c: 699b ldr r3, [r3, #24]
8004c8e: 43da mvns r2, r3
8004c90: 68bb ldr r3, [r7, #8]
8004c92: 4013 ands r3, r2
8004c94: b29b uxth r3, r3
8004c96: 2b00 cmp r3, #0
8004c98: bf14 ite ne
8004c9a: 2301 movne r3, #1
8004c9c: 2300 moveq r3, #0
8004c9e: b2db uxtb r3, r3
8004ca0: 2b00 cmp r3, #0
8004ca2: f47f af6d bne.w 8004b80 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
}
}
}
}
return HAL_OK;
8004ca6: 2300 movs r3, #0
}
8004ca8: 4618 mov r0, r3
8004caa: 3710 adds r7, #16
8004cac: 46bd mov sp, r7
8004cae: bd80 pop {r7, pc}
08004cb0 <I2C_WaitOnTXEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004cb0: b580 push {r7, lr}
8004cb2: b084 sub sp, #16
8004cb4: af00 add r7, sp, #0
8004cb6: 60f8 str r0, [r7, #12]
8004cb8: 60b9 str r1, [r7, #8]
8004cba: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004cbc: e034 b.n 8004d28 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004cbe: 68f8 ldr r0, [r7, #12]
8004cc0: f000 f8e3 bl 8004e8a <I2C_IsAcknowledgeFailed>
8004cc4: 4603 mov r3, r0
8004cc6: 2b00 cmp r3, #0
8004cc8: d001 beq.n 8004cce <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004cca: 2301 movs r3, #1
8004ccc: e034 b.n 8004d38 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004cce: 68bb ldr r3, [r7, #8]
8004cd0: f1b3 3fff cmp.w r3, #4294967295
8004cd4: d028 beq.n 8004d28 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004cd6: f7fe f907 bl 8002ee8 <HAL_GetTick>
8004cda: 4602 mov r2, r0
8004cdc: 687b ldr r3, [r7, #4]
8004cde: 1ad3 subs r3, r2, r3
8004ce0: 68ba ldr r2, [r7, #8]
8004ce2: 429a cmp r2, r3
8004ce4: d302 bcc.n 8004cec <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
8004ce6: 68bb ldr r3, [r7, #8]
8004ce8: 2b00 cmp r3, #0
8004cea: d11d bne.n 8004d28 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
8004cec: 68fb ldr r3, [r7, #12]
8004cee: 681b ldr r3, [r3, #0]
8004cf0: 695b ldr r3, [r3, #20]
8004cf2: f003 0380 and.w r3, r3, #128 @ 0x80
8004cf6: 2b80 cmp r3, #128 @ 0x80
8004cf8: d016 beq.n 8004d28 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004cfa: 68fb ldr r3, [r7, #12]
8004cfc: 2200 movs r2, #0
8004cfe: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004d00: 68fb ldr r3, [r7, #12]
8004d02: 2220 movs r2, #32
8004d04: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004d08: 68fb ldr r3, [r7, #12]
8004d0a: 2200 movs r2, #0
8004d0c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004d10: 68fb ldr r3, [r7, #12]
8004d12: 6c1b ldr r3, [r3, #64] @ 0x40
8004d14: f043 0220 orr.w r2, r3, #32
8004d18: 68fb ldr r3, [r7, #12]
8004d1a: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004d1c: 68fb ldr r3, [r7, #12]
8004d1e: 2200 movs r2, #0
8004d20: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004d24: 2301 movs r3, #1
8004d26: e007 b.n 8004d38 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8004d28: 68fb ldr r3, [r7, #12]
8004d2a: 681b ldr r3, [r3, #0]
8004d2c: 695b ldr r3, [r3, #20]
8004d2e: f003 0380 and.w r3, r3, #128 @ 0x80
8004d32: 2b80 cmp r3, #128 @ 0x80
8004d34: d1c3 bne.n 8004cbe <I2C_WaitOnTXEFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004d36: 2300 movs r3, #0
}
8004d38: 4618 mov r0, r3
8004d3a: 3710 adds r7, #16
8004d3c: 46bd mov sp, r7
8004d3e: bd80 pop {r7, pc}
08004d40 <I2C_WaitOnBTFFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004d40: b580 push {r7, lr}
8004d42: b084 sub sp, #16
8004d44: af00 add r7, sp, #0
8004d46: 60f8 str r0, [r7, #12]
8004d48: 60b9 str r1, [r7, #8]
8004d4a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004d4c: e034 b.n 8004db8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
8004d4e: 68f8 ldr r0, [r7, #12]
8004d50: f000 f89b bl 8004e8a <I2C_IsAcknowledgeFailed>
8004d54: 4603 mov r3, r0
8004d56: 2b00 cmp r3, #0
8004d58: d001 beq.n 8004d5e <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
{
return HAL_ERROR;
8004d5a: 2301 movs r3, #1
8004d5c: e034 b.n 8004dc8 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004d5e: 68bb ldr r3, [r7, #8]
8004d60: f1b3 3fff cmp.w r3, #4294967295
8004d64: d028 beq.n 8004db8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004d66: f7fe f8bf bl 8002ee8 <HAL_GetTick>
8004d6a: 4602 mov r2, r0
8004d6c: 687b ldr r3, [r7, #4]
8004d6e: 1ad3 subs r3, r2, r3
8004d70: 68ba ldr r2, [r7, #8]
8004d72: 429a cmp r2, r3
8004d74: d302 bcc.n 8004d7c <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
8004d76: 68bb ldr r3, [r7, #8]
8004d78: 2b00 cmp r3, #0
8004d7a: d11d bne.n 8004db8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
8004d7c: 68fb ldr r3, [r7, #12]
8004d7e: 681b ldr r3, [r3, #0]
8004d80: 695b ldr r3, [r3, #20]
8004d82: f003 0304 and.w r3, r3, #4
8004d86: 2b04 cmp r3, #4
8004d88: d016 beq.n 8004db8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004d8a: 68fb ldr r3, [r7, #12]
8004d8c: 2200 movs r2, #0
8004d8e: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004d90: 68fb ldr r3, [r7, #12]
8004d92: 2220 movs r2, #32
8004d94: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004d98: 68fb ldr r3, [r7, #12]
8004d9a: 2200 movs r2, #0
8004d9c: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004da0: 68fb ldr r3, [r7, #12]
8004da2: 6c1b ldr r3, [r3, #64] @ 0x40
8004da4: f043 0220 orr.w r2, r3, #32
8004da8: 68fb ldr r3, [r7, #12]
8004daa: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004dac: 68fb ldr r3, [r7, #12]
8004dae: 2200 movs r2, #0
8004db0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004db4: 2301 movs r3, #1
8004db6: e007 b.n 8004dc8 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
8004db8: 68fb ldr r3, [r7, #12]
8004dba: 681b ldr r3, [r3, #0]
8004dbc: 695b ldr r3, [r3, #20]
8004dbe: f003 0304 and.w r3, r3, #4
8004dc2: 2b04 cmp r3, #4
8004dc4: d1c3 bne.n 8004d4e <I2C_WaitOnBTFFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8004dc6: 2300 movs r3, #0
}
8004dc8: 4618 mov r0, r3
8004dca: 3710 adds r7, #16
8004dcc: 46bd mov sp, r7
8004dce: bd80 pop {r7, pc}
08004dd0 <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8004dd0: b580 push {r7, lr}
8004dd2: b084 sub sp, #16
8004dd4: af00 add r7, sp, #0
8004dd6: 60f8 str r0, [r7, #12]
8004dd8: 60b9 str r1, [r7, #8]
8004dda: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004ddc: e049 b.n 8004e72 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
8004dde: 68fb ldr r3, [r7, #12]
8004de0: 681b ldr r3, [r3, #0]
8004de2: 695b ldr r3, [r3, #20]
8004de4: f003 0310 and.w r3, r3, #16
8004de8: 2b10 cmp r3, #16
8004dea: d119 bne.n 8004e20 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8004dec: 68fb ldr r3, [r7, #12]
8004dee: 681b ldr r3, [r3, #0]
8004df0: f06f 0210 mvn.w r2, #16
8004df4: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004df6: 68fb ldr r3, [r7, #12]
8004df8: 2200 movs r2, #0
8004dfa: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004dfc: 68fb ldr r3, [r7, #12]
8004dfe: 2220 movs r2, #32
8004e00: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004e04: 68fb ldr r3, [r7, #12]
8004e06: 2200 movs r2, #0
8004e08: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
8004e0c: 68fb ldr r3, [r7, #12]
8004e0e: 6c1a ldr r2, [r3, #64] @ 0x40
8004e10: 68fb ldr r3, [r7, #12]
8004e12: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004e14: 68fb ldr r3, [r7, #12]
8004e16: 2200 movs r2, #0
8004e18: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004e1c: 2301 movs r3, #1
8004e1e: e030 b.n 8004e82 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004e20: f7fe f862 bl 8002ee8 <HAL_GetTick>
8004e24: 4602 mov r2, r0
8004e26: 687b ldr r3, [r7, #4]
8004e28: 1ad3 subs r3, r2, r3
8004e2a: 68ba ldr r2, [r7, #8]
8004e2c: 429a cmp r2, r3
8004e2e: d302 bcc.n 8004e36 <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
8004e30: 68bb ldr r3, [r7, #8]
8004e32: 2b00 cmp r3, #0
8004e34: d11d bne.n 8004e72 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
8004e36: 68fb ldr r3, [r7, #12]
8004e38: 681b ldr r3, [r3, #0]
8004e3a: 695b ldr r3, [r3, #20]
8004e3c: f003 0340 and.w r3, r3, #64 @ 0x40
8004e40: 2b40 cmp r3, #64 @ 0x40
8004e42: d016 beq.n 8004e72 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
hi2c->PreviousState = I2C_STATE_NONE;
8004e44: 68fb ldr r3, [r7, #12]
8004e46: 2200 movs r2, #0
8004e48: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004e4a: 68fb ldr r3, [r7, #12]
8004e4c: 2220 movs r2, #32
8004e4e: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004e52: 68fb ldr r3, [r7, #12]
8004e54: 2200 movs r2, #0
8004e56: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8004e5a: 68fb ldr r3, [r7, #12]
8004e5c: 6c1b ldr r3, [r3, #64] @ 0x40
8004e5e: f043 0220 orr.w r2, r3, #32
8004e62: 68fb ldr r3, [r7, #12]
8004e64: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004e66: 68fb ldr r3, [r7, #12]
8004e68: 2200 movs r2, #0
8004e6a: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004e6e: 2301 movs r3, #1
8004e70: e007 b.n 8004e82 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8004e72: 68fb ldr r3, [r7, #12]
8004e74: 681b ldr r3, [r3, #0]
8004e76: 695b ldr r3, [r3, #20]
8004e78: f003 0340 and.w r3, r3, #64 @ 0x40
8004e7c: 2b40 cmp r3, #64 @ 0x40
8004e7e: d1ae bne.n 8004dde <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8004e80: 2300 movs r3, #0
}
8004e82: 4618 mov r0, r3
8004e84: 3710 adds r7, #16
8004e86: 46bd mov sp, r7
8004e88: bd80 pop {r7, pc}
08004e8a <I2C_IsAcknowledgeFailed>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
8004e8a: b480 push {r7}
8004e8c: b083 sub sp, #12
8004e8e: af00 add r7, sp, #0
8004e90: 6078 str r0, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8004e92: 687b ldr r3, [r7, #4]
8004e94: 681b ldr r3, [r3, #0]
8004e96: 695b ldr r3, [r3, #20]
8004e98: f403 6380 and.w r3, r3, #1024 @ 0x400
8004e9c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004ea0: d11b bne.n 8004eda <I2C_IsAcknowledgeFailed+0x50>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8004ea2: 687b ldr r3, [r7, #4]
8004ea4: 681b ldr r3, [r3, #0]
8004ea6: f46f 6280 mvn.w r2, #1024 @ 0x400
8004eaa: 615a str r2, [r3, #20]
hi2c->PreviousState = I2C_STATE_NONE;
8004eac: 687b ldr r3, [r7, #4]
8004eae: 2200 movs r2, #0
8004eb0: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8004eb2: 687b ldr r3, [r7, #4]
8004eb4: 2220 movs r2, #32
8004eb6: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->Mode = HAL_I2C_MODE_NONE;
8004eba: 687b ldr r3, [r7, #4]
8004ebc: 2200 movs r2, #0
8004ebe: f883 203e strb.w r2, [r3, #62] @ 0x3e
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8004ec2: 687b ldr r3, [r7, #4]
8004ec4: 6c1b ldr r3, [r3, #64] @ 0x40
8004ec6: f043 0204 orr.w r2, r3, #4
8004eca: 687b ldr r3, [r7, #4]
8004ecc: 641a str r2, [r3, #64] @ 0x40
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8004ece: 687b ldr r3, [r7, #4]
8004ed0: 2200 movs r2, #0
8004ed2: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8004ed6: 2301 movs r3, #1
8004ed8: e000 b.n 8004edc <I2C_IsAcknowledgeFailed+0x52>
}
return HAL_OK;
8004eda: 2300 movs r3, #0
}
8004edc: 4618 mov r0, r3
8004ede: 370c adds r7, #12
8004ee0: 46bd mov sp, r7
8004ee2: bc80 pop {r7}
8004ee4: 4770 bx lr
...
08004ee8 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004ee8: b580 push {r7, lr}
8004eea: b086 sub sp, #24
8004eec: af00 add r7, sp, #0
8004eee: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004ef0: 687b ldr r3, [r7, #4]
8004ef2: 2b00 cmp r3, #0
8004ef4: d101 bne.n 8004efa <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8004ef6: 2301 movs r3, #1
8004ef8: e272 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8004efa: 687b ldr r3, [r7, #4]
8004efc: 681b ldr r3, [r3, #0]
8004efe: f003 0301 and.w r3, r3, #1
8004f02: 2b00 cmp r3, #0
8004f04: f000 8087 beq.w 8005016 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8004f08: 4b92 ldr r3, [pc, #584] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f0a: 685b ldr r3, [r3, #4]
8004f0c: f003 030c and.w r3, r3, #12
8004f10: 2b04 cmp r3, #4
8004f12: d00c beq.n 8004f2e <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8004f14: 4b8f ldr r3, [pc, #572] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f16: 685b ldr r3, [r3, #4]
8004f18: f003 030c and.w r3, r3, #12
8004f1c: 2b08 cmp r3, #8
8004f1e: d112 bne.n 8004f46 <HAL_RCC_OscConfig+0x5e>
8004f20: 4b8c ldr r3, [pc, #560] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f22: 685b ldr r3, [r3, #4]
8004f24: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004f28: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004f2c: d10b bne.n 8004f46 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004f2e: 4b89 ldr r3, [pc, #548] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f30: 681b ldr r3, [r3, #0]
8004f32: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004f36: 2b00 cmp r3, #0
8004f38: d06c beq.n 8005014 <HAL_RCC_OscConfig+0x12c>
8004f3a: 687b ldr r3, [r7, #4]
8004f3c: 685b ldr r3, [r3, #4]
8004f3e: 2b00 cmp r3, #0
8004f40: d168 bne.n 8005014 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8004f42: 2301 movs r3, #1
8004f44: e24c b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8004f46: 687b ldr r3, [r7, #4]
8004f48: 685b ldr r3, [r3, #4]
8004f4a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004f4e: d106 bne.n 8004f5e <HAL_RCC_OscConfig+0x76>
8004f50: 4b80 ldr r3, [pc, #512] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f52: 681b ldr r3, [r3, #0]
8004f54: 4a7f ldr r2, [pc, #508] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f56: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004f5a: 6013 str r3, [r2, #0]
8004f5c: e02e b.n 8004fbc <HAL_RCC_OscConfig+0xd4>
8004f5e: 687b ldr r3, [r7, #4]
8004f60: 685b ldr r3, [r3, #4]
8004f62: 2b00 cmp r3, #0
8004f64: d10c bne.n 8004f80 <HAL_RCC_OscConfig+0x98>
8004f66: 4b7b ldr r3, [pc, #492] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f68: 681b ldr r3, [r3, #0]
8004f6a: 4a7a ldr r2, [pc, #488] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f6c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004f70: 6013 str r3, [r2, #0]
8004f72: 4b78 ldr r3, [pc, #480] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f74: 681b ldr r3, [r3, #0]
8004f76: 4a77 ldr r2, [pc, #476] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f78: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004f7c: 6013 str r3, [r2, #0]
8004f7e: e01d b.n 8004fbc <HAL_RCC_OscConfig+0xd4>
8004f80: 687b ldr r3, [r7, #4]
8004f82: 685b ldr r3, [r3, #4]
8004f84: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004f88: d10c bne.n 8004fa4 <HAL_RCC_OscConfig+0xbc>
8004f8a: 4b72 ldr r3, [pc, #456] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f8c: 681b ldr r3, [r3, #0]
8004f8e: 4a71 ldr r2, [pc, #452] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f90: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8004f94: 6013 str r3, [r2, #0]
8004f96: 4b6f ldr r3, [pc, #444] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f98: 681b ldr r3, [r3, #0]
8004f9a: 4a6e ldr r2, [pc, #440] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004f9c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004fa0: 6013 str r3, [r2, #0]
8004fa2: e00b b.n 8004fbc <HAL_RCC_OscConfig+0xd4>
8004fa4: 4b6b ldr r3, [pc, #428] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004fa6: 681b ldr r3, [r3, #0]
8004fa8: 4a6a ldr r2, [pc, #424] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004faa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004fae: 6013 str r3, [r2, #0]
8004fb0: 4b68 ldr r3, [pc, #416] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004fb2: 681b ldr r3, [r3, #0]
8004fb4: 4a67 ldr r2, [pc, #412] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004fb6: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004fba: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8004fbc: 687b ldr r3, [r7, #4]
8004fbe: 685b ldr r3, [r3, #4]
8004fc0: 2b00 cmp r3, #0
8004fc2: d013 beq.n 8004fec <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004fc4: f7fd ff90 bl 8002ee8 <HAL_GetTick>
8004fc8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004fca: e008 b.n 8004fde <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004fcc: f7fd ff8c bl 8002ee8 <HAL_GetTick>
8004fd0: 4602 mov r2, r0
8004fd2: 693b ldr r3, [r7, #16]
8004fd4: 1ad3 subs r3, r2, r3
8004fd6: 2b64 cmp r3, #100 @ 0x64
8004fd8: d901 bls.n 8004fde <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8004fda: 2303 movs r3, #3
8004fdc: e200 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004fde: 4b5d ldr r3, [pc, #372] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8004fe0: 681b ldr r3, [r3, #0]
8004fe2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004fe6: 2b00 cmp r3, #0
8004fe8: d0f0 beq.n 8004fcc <HAL_RCC_OscConfig+0xe4>
8004fea: e014 b.n 8005016 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004fec: f7fd ff7c bl 8002ee8 <HAL_GetTick>
8004ff0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004ff2: e008 b.n 8005006 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004ff4: f7fd ff78 bl 8002ee8 <HAL_GetTick>
8004ff8: 4602 mov r2, r0
8004ffa: 693b ldr r3, [r7, #16]
8004ffc: 1ad3 subs r3, r2, r3
8004ffe: 2b64 cmp r3, #100 @ 0x64
8005000: d901 bls.n 8005006 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8005002: 2303 movs r3, #3
8005004: e1ec b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8005006: 4b53 ldr r3, [pc, #332] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005008: 681b ldr r3, [r3, #0]
800500a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800500e: 2b00 cmp r3, #0
8005010: d1f0 bne.n 8004ff4 <HAL_RCC_OscConfig+0x10c>
8005012: e000 b.n 8005016 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8005014: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8005016: 687b ldr r3, [r7, #4]
8005018: 681b ldr r3, [r3, #0]
800501a: f003 0302 and.w r3, r3, #2
800501e: 2b00 cmp r3, #0
8005020: d063 beq.n 80050ea <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8005022: 4b4c ldr r3, [pc, #304] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005024: 685b ldr r3, [r3, #4]
8005026: f003 030c and.w r3, r3, #12
800502a: 2b00 cmp r3, #0
800502c: d00b beq.n 8005046 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
800502e: 4b49 ldr r3, [pc, #292] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005030: 685b ldr r3, [r3, #4]
8005032: f003 030c and.w r3, r3, #12
8005036: 2b08 cmp r3, #8
8005038: d11c bne.n 8005074 <HAL_RCC_OscConfig+0x18c>
800503a: 4b46 ldr r3, [pc, #280] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
800503c: 685b ldr r3, [r3, #4]
800503e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8005042: 2b00 cmp r3, #0
8005044: d116 bne.n 8005074 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8005046: 4b43 ldr r3, [pc, #268] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005048: 681b ldr r3, [r3, #0]
800504a: f003 0302 and.w r3, r3, #2
800504e: 2b00 cmp r3, #0
8005050: d005 beq.n 800505e <HAL_RCC_OscConfig+0x176>
8005052: 687b ldr r3, [r7, #4]
8005054: 691b ldr r3, [r3, #16]
8005056: 2b01 cmp r3, #1
8005058: d001 beq.n 800505e <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
800505a: 2301 movs r3, #1
800505c: e1c0 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800505e: 4b3d ldr r3, [pc, #244] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005060: 681b ldr r3, [r3, #0]
8005062: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8005066: 687b ldr r3, [r7, #4]
8005068: 695b ldr r3, [r3, #20]
800506a: 00db lsls r3, r3, #3
800506c: 4939 ldr r1, [pc, #228] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
800506e: 4313 orrs r3, r2
8005070: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8005072: e03a b.n 80050ea <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8005074: 687b ldr r3, [r7, #4]
8005076: 691b ldr r3, [r3, #16]
8005078: 2b00 cmp r3, #0
800507a: d020 beq.n 80050be <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800507c: 4b36 ldr r3, [pc, #216] @ (8005158 <HAL_RCC_OscConfig+0x270>)
800507e: 2201 movs r2, #1
8005080: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005082: f7fd ff31 bl 8002ee8 <HAL_GetTick>
8005086: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005088: e008 b.n 800509c <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800508a: f7fd ff2d bl 8002ee8 <HAL_GetTick>
800508e: 4602 mov r2, r0
8005090: 693b ldr r3, [r7, #16]
8005092: 1ad3 subs r3, r2, r3
8005094: 2b02 cmp r3, #2
8005096: d901 bls.n 800509c <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8005098: 2303 movs r3, #3
800509a: e1a1 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800509c: 4b2d ldr r3, [pc, #180] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
800509e: 681b ldr r3, [r3, #0]
80050a0: f003 0302 and.w r3, r3, #2
80050a4: 2b00 cmp r3, #0
80050a6: d0f0 beq.n 800508a <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80050a8: 4b2a ldr r3, [pc, #168] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
80050aa: 681b ldr r3, [r3, #0]
80050ac: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80050b0: 687b ldr r3, [r7, #4]
80050b2: 695b ldr r3, [r3, #20]
80050b4: 00db lsls r3, r3, #3
80050b6: 4927 ldr r1, [pc, #156] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
80050b8: 4313 orrs r3, r2
80050ba: 600b str r3, [r1, #0]
80050bc: e015 b.n 80050ea <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80050be: 4b26 ldr r3, [pc, #152] @ (8005158 <HAL_RCC_OscConfig+0x270>)
80050c0: 2200 movs r2, #0
80050c2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80050c4: f7fd ff10 bl 8002ee8 <HAL_GetTick>
80050c8: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80050ca: e008 b.n 80050de <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80050cc: f7fd ff0c bl 8002ee8 <HAL_GetTick>
80050d0: 4602 mov r2, r0
80050d2: 693b ldr r3, [r7, #16]
80050d4: 1ad3 subs r3, r2, r3
80050d6: 2b02 cmp r3, #2
80050d8: d901 bls.n 80050de <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
80050da: 2303 movs r3, #3
80050dc: e180 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80050de: 4b1d ldr r3, [pc, #116] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
80050e0: 681b ldr r3, [r3, #0]
80050e2: f003 0302 and.w r3, r3, #2
80050e6: 2b00 cmp r3, #0
80050e8: d1f0 bne.n 80050cc <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80050ea: 687b ldr r3, [r7, #4]
80050ec: 681b ldr r3, [r3, #0]
80050ee: f003 0308 and.w r3, r3, #8
80050f2: 2b00 cmp r3, #0
80050f4: d03a beq.n 800516c <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80050f6: 687b ldr r3, [r7, #4]
80050f8: 699b ldr r3, [r3, #24]
80050fa: 2b00 cmp r3, #0
80050fc: d019 beq.n 8005132 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80050fe: 4b17 ldr r3, [pc, #92] @ (800515c <HAL_RCC_OscConfig+0x274>)
8005100: 2201 movs r2, #1
8005102: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005104: f7fd fef0 bl 8002ee8 <HAL_GetTick>
8005108: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800510a: e008 b.n 800511e <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800510c: f7fd feec bl 8002ee8 <HAL_GetTick>
8005110: 4602 mov r2, r0
8005112: 693b ldr r3, [r7, #16]
8005114: 1ad3 subs r3, r2, r3
8005116: 2b02 cmp r3, #2
8005118: d901 bls.n 800511e <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
800511a: 2303 movs r3, #3
800511c: e160 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800511e: 4b0d ldr r3, [pc, #52] @ (8005154 <HAL_RCC_OscConfig+0x26c>)
8005120: 6a5b ldr r3, [r3, #36] @ 0x24
8005122: f003 0302 and.w r3, r3, #2
8005126: 2b00 cmp r3, #0
8005128: d0f0 beq.n 800510c <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
800512a: 2001 movs r0, #1
800512c: f000 fad0 bl 80056d0 <RCC_Delay>
8005130: e01c b.n 800516c <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8005132: 4b0a ldr r3, [pc, #40] @ (800515c <HAL_RCC_OscConfig+0x274>)
8005134: 2200 movs r2, #0
8005136: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005138: f7fd fed6 bl 8002ee8 <HAL_GetTick>
800513c: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800513e: e00f b.n 8005160 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8005140: f7fd fed2 bl 8002ee8 <HAL_GetTick>
8005144: 4602 mov r2, r0
8005146: 693b ldr r3, [r7, #16]
8005148: 1ad3 subs r3, r2, r3
800514a: 2b02 cmp r3, #2
800514c: d908 bls.n 8005160 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800514e: 2303 movs r3, #3
8005150: e146 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
8005152: bf00 nop
8005154: 40021000 .word 0x40021000
8005158: 42420000 .word 0x42420000
800515c: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8005160: 4b92 ldr r3, [pc, #584] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005162: 6a5b ldr r3, [r3, #36] @ 0x24
8005164: f003 0302 and.w r3, r3, #2
8005168: 2b00 cmp r3, #0
800516a: d1e9 bne.n 8005140 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800516c: 687b ldr r3, [r7, #4]
800516e: 681b ldr r3, [r3, #0]
8005170: f003 0304 and.w r3, r3, #4
8005174: 2b00 cmp r3, #0
8005176: f000 80a6 beq.w 80052c6 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800517a: 2300 movs r3, #0
800517c: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800517e: 4b8b ldr r3, [pc, #556] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005180: 69db ldr r3, [r3, #28]
8005182: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005186: 2b00 cmp r3, #0
8005188: d10d bne.n 80051a6 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800518a: 4b88 ldr r3, [pc, #544] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800518c: 69db ldr r3, [r3, #28]
800518e: 4a87 ldr r2, [pc, #540] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005190: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005194: 61d3 str r3, [r2, #28]
8005196: 4b85 ldr r3, [pc, #532] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005198: 69db ldr r3, [r3, #28]
800519a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800519e: 60bb str r3, [r7, #8]
80051a0: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80051a2: 2301 movs r3, #1
80051a4: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80051a6: 4b82 ldr r3, [pc, #520] @ (80053b0 <HAL_RCC_OscConfig+0x4c8>)
80051a8: 681b ldr r3, [r3, #0]
80051aa: f403 7380 and.w r3, r3, #256 @ 0x100
80051ae: 2b00 cmp r3, #0
80051b0: d118 bne.n 80051e4 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80051b2: 4b7f ldr r3, [pc, #508] @ (80053b0 <HAL_RCC_OscConfig+0x4c8>)
80051b4: 681b ldr r3, [r3, #0]
80051b6: 4a7e ldr r2, [pc, #504] @ (80053b0 <HAL_RCC_OscConfig+0x4c8>)
80051b8: f443 7380 orr.w r3, r3, #256 @ 0x100
80051bc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80051be: f7fd fe93 bl 8002ee8 <HAL_GetTick>
80051c2: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80051c4: e008 b.n 80051d8 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80051c6: f7fd fe8f bl 8002ee8 <HAL_GetTick>
80051ca: 4602 mov r2, r0
80051cc: 693b ldr r3, [r7, #16]
80051ce: 1ad3 subs r3, r2, r3
80051d0: 2b64 cmp r3, #100 @ 0x64
80051d2: d901 bls.n 80051d8 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80051d4: 2303 movs r3, #3
80051d6: e103 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80051d8: 4b75 ldr r3, [pc, #468] @ (80053b0 <HAL_RCC_OscConfig+0x4c8>)
80051da: 681b ldr r3, [r3, #0]
80051dc: f403 7380 and.w r3, r3, #256 @ 0x100
80051e0: 2b00 cmp r3, #0
80051e2: d0f0 beq.n 80051c6 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80051e4: 687b ldr r3, [r7, #4]
80051e6: 68db ldr r3, [r3, #12]
80051e8: 2b01 cmp r3, #1
80051ea: d106 bne.n 80051fa <HAL_RCC_OscConfig+0x312>
80051ec: 4b6f ldr r3, [pc, #444] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80051ee: 6a1b ldr r3, [r3, #32]
80051f0: 4a6e ldr r2, [pc, #440] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80051f2: f043 0301 orr.w r3, r3, #1
80051f6: 6213 str r3, [r2, #32]
80051f8: e02d b.n 8005256 <HAL_RCC_OscConfig+0x36e>
80051fa: 687b ldr r3, [r7, #4]
80051fc: 68db ldr r3, [r3, #12]
80051fe: 2b00 cmp r3, #0
8005200: d10c bne.n 800521c <HAL_RCC_OscConfig+0x334>
8005202: 4b6a ldr r3, [pc, #424] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005204: 6a1b ldr r3, [r3, #32]
8005206: 4a69 ldr r2, [pc, #420] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005208: f023 0301 bic.w r3, r3, #1
800520c: 6213 str r3, [r2, #32]
800520e: 4b67 ldr r3, [pc, #412] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005210: 6a1b ldr r3, [r3, #32]
8005212: 4a66 ldr r2, [pc, #408] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005214: f023 0304 bic.w r3, r3, #4
8005218: 6213 str r3, [r2, #32]
800521a: e01c b.n 8005256 <HAL_RCC_OscConfig+0x36e>
800521c: 687b ldr r3, [r7, #4]
800521e: 68db ldr r3, [r3, #12]
8005220: 2b05 cmp r3, #5
8005222: d10c bne.n 800523e <HAL_RCC_OscConfig+0x356>
8005224: 4b61 ldr r3, [pc, #388] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005226: 6a1b ldr r3, [r3, #32]
8005228: 4a60 ldr r2, [pc, #384] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800522a: f043 0304 orr.w r3, r3, #4
800522e: 6213 str r3, [r2, #32]
8005230: 4b5e ldr r3, [pc, #376] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005232: 6a1b ldr r3, [r3, #32]
8005234: 4a5d ldr r2, [pc, #372] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005236: f043 0301 orr.w r3, r3, #1
800523a: 6213 str r3, [r2, #32]
800523c: e00b b.n 8005256 <HAL_RCC_OscConfig+0x36e>
800523e: 4b5b ldr r3, [pc, #364] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005240: 6a1b ldr r3, [r3, #32]
8005242: 4a5a ldr r2, [pc, #360] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005244: f023 0301 bic.w r3, r3, #1
8005248: 6213 str r3, [r2, #32]
800524a: 4b58 ldr r3, [pc, #352] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800524c: 6a1b ldr r3, [r3, #32]
800524e: 4a57 ldr r2, [pc, #348] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005250: f023 0304 bic.w r3, r3, #4
8005254: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8005256: 687b ldr r3, [r7, #4]
8005258: 68db ldr r3, [r3, #12]
800525a: 2b00 cmp r3, #0
800525c: d015 beq.n 800528a <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800525e: f7fd fe43 bl 8002ee8 <HAL_GetTick>
8005262: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005264: e00a b.n 800527c <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005266: f7fd fe3f bl 8002ee8 <HAL_GetTick>
800526a: 4602 mov r2, r0
800526c: 693b ldr r3, [r7, #16]
800526e: 1ad3 subs r3, r2, r3
8005270: f241 3288 movw r2, #5000 @ 0x1388
8005274: 4293 cmp r3, r2
8005276: d901 bls.n 800527c <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8005278: 2303 movs r3, #3
800527a: e0b1 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800527c: 4b4b ldr r3, [pc, #300] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800527e: 6a1b ldr r3, [r3, #32]
8005280: f003 0302 and.w r3, r3, #2
8005284: 2b00 cmp r3, #0
8005286: d0ee beq.n 8005266 <HAL_RCC_OscConfig+0x37e>
8005288: e014 b.n 80052b4 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800528a: f7fd fe2d bl 8002ee8 <HAL_GetTick>
800528e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8005290: e00a b.n 80052a8 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005292: f7fd fe29 bl 8002ee8 <HAL_GetTick>
8005296: 4602 mov r2, r0
8005298: 693b ldr r3, [r7, #16]
800529a: 1ad3 subs r3, r2, r3
800529c: f241 3288 movw r2, #5000 @ 0x1388
80052a0: 4293 cmp r3, r2
80052a2: d901 bls.n 80052a8 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
80052a4: 2303 movs r3, #3
80052a6: e09b b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80052a8: 4b40 ldr r3, [pc, #256] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80052aa: 6a1b ldr r3, [r3, #32]
80052ac: f003 0302 and.w r3, r3, #2
80052b0: 2b00 cmp r3, #0
80052b2: d1ee bne.n 8005292 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
80052b4: 7dfb ldrb r3, [r7, #23]
80052b6: 2b01 cmp r3, #1
80052b8: d105 bne.n 80052c6 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
80052ba: 4b3c ldr r3, [pc, #240] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80052bc: 69db ldr r3, [r3, #28]
80052be: 4a3b ldr r2, [pc, #236] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80052c0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80052c4: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80052c6: 687b ldr r3, [r7, #4]
80052c8: 69db ldr r3, [r3, #28]
80052ca: 2b00 cmp r3, #0
80052cc: f000 8087 beq.w 80053de <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80052d0: 4b36 ldr r3, [pc, #216] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
80052d2: 685b ldr r3, [r3, #4]
80052d4: f003 030c and.w r3, r3, #12
80052d8: 2b08 cmp r3, #8
80052da: d061 beq.n 80053a0 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80052dc: 687b ldr r3, [r7, #4]
80052de: 69db ldr r3, [r3, #28]
80052e0: 2b02 cmp r3, #2
80052e2: d146 bne.n 8005372 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80052e4: 4b33 ldr r3, [pc, #204] @ (80053b4 <HAL_RCC_OscConfig+0x4cc>)
80052e6: 2200 movs r2, #0
80052e8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80052ea: f7fd fdfd bl 8002ee8 <HAL_GetTick>
80052ee: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80052f0: e008 b.n 8005304 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80052f2: f7fd fdf9 bl 8002ee8 <HAL_GetTick>
80052f6: 4602 mov r2, r0
80052f8: 693b ldr r3, [r7, #16]
80052fa: 1ad3 subs r3, r2, r3
80052fc: 2b02 cmp r3, #2
80052fe: d901 bls.n 8005304 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8005300: 2303 movs r3, #3
8005302: e06d b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005304: 4b29 ldr r3, [pc, #164] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005306: 681b ldr r3, [r3, #0]
8005308: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800530c: 2b00 cmp r3, #0
800530e: d1f0 bne.n 80052f2 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8005310: 687b ldr r3, [r7, #4]
8005312: 6a1b ldr r3, [r3, #32]
8005314: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8005318: d108 bne.n 800532c <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
800531a: 4b24 ldr r3, [pc, #144] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800531c: 685b ldr r3, [r3, #4]
800531e: f423 3200 bic.w r2, r3, #131072 @ 0x20000
8005322: 687b ldr r3, [r7, #4]
8005324: 689b ldr r3, [r3, #8]
8005326: 4921 ldr r1, [pc, #132] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005328: 4313 orrs r3, r2
800532a: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800532c: 4b1f ldr r3, [pc, #124] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
800532e: 685b ldr r3, [r3, #4]
8005330: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8005334: 687b ldr r3, [r7, #4]
8005336: 6a19 ldr r1, [r3, #32]
8005338: 687b ldr r3, [r7, #4]
800533a: 6a5b ldr r3, [r3, #36] @ 0x24
800533c: 430b orrs r3, r1
800533e: 491b ldr r1, [pc, #108] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005340: 4313 orrs r3, r2
8005342: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8005344: 4b1b ldr r3, [pc, #108] @ (80053b4 <HAL_RCC_OscConfig+0x4cc>)
8005346: 2201 movs r2, #1
8005348: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800534a: f7fd fdcd bl 8002ee8 <HAL_GetTick>
800534e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005350: e008 b.n 8005364 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005352: f7fd fdc9 bl 8002ee8 <HAL_GetTick>
8005356: 4602 mov r2, r0
8005358: 693b ldr r3, [r7, #16]
800535a: 1ad3 subs r3, r2, r3
800535c: 2b02 cmp r3, #2
800535e: d901 bls.n 8005364 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8005360: 2303 movs r3, #3
8005362: e03d b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005364: 4b11 ldr r3, [pc, #68] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005366: 681b ldr r3, [r3, #0]
8005368: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800536c: 2b00 cmp r3, #0
800536e: d0f0 beq.n 8005352 <HAL_RCC_OscConfig+0x46a>
8005370: e035 b.n 80053de <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8005372: 4b10 ldr r3, [pc, #64] @ (80053b4 <HAL_RCC_OscConfig+0x4cc>)
8005374: 2200 movs r2, #0
8005376: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005378: f7fd fdb6 bl 8002ee8 <HAL_GetTick>
800537c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800537e: e008 b.n 8005392 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005380: f7fd fdb2 bl 8002ee8 <HAL_GetTick>
8005384: 4602 mov r2, r0
8005386: 693b ldr r3, [r7, #16]
8005388: 1ad3 subs r3, r2, r3
800538a: 2b02 cmp r3, #2
800538c: d901 bls.n 8005392 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
800538e: 2303 movs r3, #3
8005390: e026 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005392: 4b06 ldr r3, [pc, #24] @ (80053ac <HAL_RCC_OscConfig+0x4c4>)
8005394: 681b ldr r3, [r3, #0]
8005396: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800539a: 2b00 cmp r3, #0
800539c: d1f0 bne.n 8005380 <HAL_RCC_OscConfig+0x498>
800539e: e01e b.n 80053de <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80053a0: 687b ldr r3, [r7, #4]
80053a2: 69db ldr r3, [r3, #28]
80053a4: 2b01 cmp r3, #1
80053a6: d107 bne.n 80053b8 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
80053a8: 2301 movs r3, #1
80053aa: e019 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
80053ac: 40021000 .word 0x40021000
80053b0: 40007000 .word 0x40007000
80053b4: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80053b8: 4b0b ldr r3, [pc, #44] @ (80053e8 <HAL_RCC_OscConfig+0x500>)
80053ba: 685b ldr r3, [r3, #4]
80053bc: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80053be: 68fb ldr r3, [r7, #12]
80053c0: f403 3280 and.w r2, r3, #65536 @ 0x10000
80053c4: 687b ldr r3, [r7, #4]
80053c6: 6a1b ldr r3, [r3, #32]
80053c8: 429a cmp r2, r3
80053ca: d106 bne.n 80053da <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80053cc: 68fb ldr r3, [r7, #12]
80053ce: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80053d2: 687b ldr r3, [r7, #4]
80053d4: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80053d6: 429a cmp r2, r3
80053d8: d001 beq.n 80053de <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80053da: 2301 movs r3, #1
80053dc: e000 b.n 80053e0 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80053de: 2300 movs r3, #0
}
80053e0: 4618 mov r0, r3
80053e2: 3718 adds r7, #24
80053e4: 46bd mov sp, r7
80053e6: bd80 pop {r7, pc}
80053e8: 40021000 .word 0x40021000
080053ec <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80053ec: b580 push {r7, lr}
80053ee: b084 sub sp, #16
80053f0: af00 add r7, sp, #0
80053f2: 6078 str r0, [r7, #4]
80053f4: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80053f6: 687b ldr r3, [r7, #4]
80053f8: 2b00 cmp r3, #0
80053fa: d101 bne.n 8005400 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80053fc: 2301 movs r3, #1
80053fe: e0d0 b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8005400: 4b6a ldr r3, [pc, #424] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
8005402: 681b ldr r3, [r3, #0]
8005404: f003 0307 and.w r3, r3, #7
8005408: 683a ldr r2, [r7, #0]
800540a: 429a cmp r2, r3
800540c: d910 bls.n 8005430 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800540e: 4b67 ldr r3, [pc, #412] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
8005410: 681b ldr r3, [r3, #0]
8005412: f023 0207 bic.w r2, r3, #7
8005416: 4965 ldr r1, [pc, #404] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
8005418: 683b ldr r3, [r7, #0]
800541a: 4313 orrs r3, r2
800541c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800541e: 4b63 ldr r3, [pc, #396] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
8005420: 681b ldr r3, [r3, #0]
8005422: f003 0307 and.w r3, r3, #7
8005426: 683a ldr r2, [r7, #0]
8005428: 429a cmp r2, r3
800542a: d001 beq.n 8005430 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
800542c: 2301 movs r3, #1
800542e: e0b8 b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8005430: 687b ldr r3, [r7, #4]
8005432: 681b ldr r3, [r3, #0]
8005434: f003 0302 and.w r3, r3, #2
8005438: 2b00 cmp r3, #0
800543a: d020 beq.n 800547e <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800543c: 687b ldr r3, [r7, #4]
800543e: 681b ldr r3, [r3, #0]
8005440: f003 0304 and.w r3, r3, #4
8005444: 2b00 cmp r3, #0
8005446: d005 beq.n 8005454 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8005448: 4b59 ldr r3, [pc, #356] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
800544a: 685b ldr r3, [r3, #4]
800544c: 4a58 ldr r2, [pc, #352] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
800544e: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8005452: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005454: 687b ldr r3, [r7, #4]
8005456: 681b ldr r3, [r3, #0]
8005458: f003 0308 and.w r3, r3, #8
800545c: 2b00 cmp r3, #0
800545e: d005 beq.n 800546c <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8005460: 4b53 ldr r3, [pc, #332] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005462: 685b ldr r3, [r3, #4]
8005464: 4a52 ldr r2, [pc, #328] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005466: f443 5360 orr.w r3, r3, #14336 @ 0x3800
800546a: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800546c: 4b50 ldr r3, [pc, #320] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
800546e: 685b ldr r3, [r3, #4]
8005470: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8005474: 687b ldr r3, [r7, #4]
8005476: 689b ldr r3, [r3, #8]
8005478: 494d ldr r1, [pc, #308] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
800547a: 4313 orrs r3, r2
800547c: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800547e: 687b ldr r3, [r7, #4]
8005480: 681b ldr r3, [r3, #0]
8005482: f003 0301 and.w r3, r3, #1
8005486: 2b00 cmp r3, #0
8005488: d040 beq.n 800550c <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800548a: 687b ldr r3, [r7, #4]
800548c: 685b ldr r3, [r3, #4]
800548e: 2b01 cmp r3, #1
8005490: d107 bne.n 80054a2 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8005492: 4b47 ldr r3, [pc, #284] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005494: 681b ldr r3, [r3, #0]
8005496: f403 3300 and.w r3, r3, #131072 @ 0x20000
800549a: 2b00 cmp r3, #0
800549c: d115 bne.n 80054ca <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800549e: 2301 movs r3, #1
80054a0: e07f b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80054a2: 687b ldr r3, [r7, #4]
80054a4: 685b ldr r3, [r3, #4]
80054a6: 2b02 cmp r3, #2
80054a8: d107 bne.n 80054ba <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80054aa: 4b41 ldr r3, [pc, #260] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
80054ac: 681b ldr r3, [r3, #0]
80054ae: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80054b2: 2b00 cmp r3, #0
80054b4: d109 bne.n 80054ca <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80054b6: 2301 movs r3, #1
80054b8: e073 b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80054ba: 4b3d ldr r3, [pc, #244] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
80054bc: 681b ldr r3, [r3, #0]
80054be: f003 0302 and.w r3, r3, #2
80054c2: 2b00 cmp r3, #0
80054c4: d101 bne.n 80054ca <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80054c6: 2301 movs r3, #1
80054c8: e06b b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80054ca: 4b39 ldr r3, [pc, #228] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
80054cc: 685b ldr r3, [r3, #4]
80054ce: f023 0203 bic.w r2, r3, #3
80054d2: 687b ldr r3, [r7, #4]
80054d4: 685b ldr r3, [r3, #4]
80054d6: 4936 ldr r1, [pc, #216] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
80054d8: 4313 orrs r3, r2
80054da: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80054dc: f7fd fd04 bl 8002ee8 <HAL_GetTick>
80054e0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80054e2: e00a b.n 80054fa <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80054e4: f7fd fd00 bl 8002ee8 <HAL_GetTick>
80054e8: 4602 mov r2, r0
80054ea: 68fb ldr r3, [r7, #12]
80054ec: 1ad3 subs r3, r2, r3
80054ee: f241 3288 movw r2, #5000 @ 0x1388
80054f2: 4293 cmp r3, r2
80054f4: d901 bls.n 80054fa <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80054f6: 2303 movs r3, #3
80054f8: e053 b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80054fa: 4b2d ldr r3, [pc, #180] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
80054fc: 685b ldr r3, [r3, #4]
80054fe: f003 020c and.w r2, r3, #12
8005502: 687b ldr r3, [r7, #4]
8005504: 685b ldr r3, [r3, #4]
8005506: 009b lsls r3, r3, #2
8005508: 429a cmp r2, r3
800550a: d1eb bne.n 80054e4 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
800550c: 4b27 ldr r3, [pc, #156] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
800550e: 681b ldr r3, [r3, #0]
8005510: f003 0307 and.w r3, r3, #7
8005514: 683a ldr r2, [r7, #0]
8005516: 429a cmp r2, r3
8005518: d210 bcs.n 800553c <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800551a: 4b24 ldr r3, [pc, #144] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
800551c: 681b ldr r3, [r3, #0]
800551e: f023 0207 bic.w r2, r3, #7
8005522: 4922 ldr r1, [pc, #136] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
8005524: 683b ldr r3, [r7, #0]
8005526: 4313 orrs r3, r2
8005528: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800552a: 4b20 ldr r3, [pc, #128] @ (80055ac <HAL_RCC_ClockConfig+0x1c0>)
800552c: 681b ldr r3, [r3, #0]
800552e: f003 0307 and.w r3, r3, #7
8005532: 683a ldr r2, [r7, #0]
8005534: 429a cmp r2, r3
8005536: d001 beq.n 800553c <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8005538: 2301 movs r3, #1
800553a: e032 b.n 80055a2 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800553c: 687b ldr r3, [r7, #4]
800553e: 681b ldr r3, [r3, #0]
8005540: f003 0304 and.w r3, r3, #4
8005544: 2b00 cmp r3, #0
8005546: d008 beq.n 800555a <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8005548: 4b19 ldr r3, [pc, #100] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
800554a: 685b ldr r3, [r3, #4]
800554c: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8005550: 687b ldr r3, [r7, #4]
8005552: 68db ldr r3, [r3, #12]
8005554: 4916 ldr r1, [pc, #88] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005556: 4313 orrs r3, r2
8005558: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800555a: 687b ldr r3, [r7, #4]
800555c: 681b ldr r3, [r3, #0]
800555e: f003 0308 and.w r3, r3, #8
8005562: 2b00 cmp r3, #0
8005564: d009 beq.n 800557a <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8005566: 4b12 ldr r3, [pc, #72] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005568: 685b ldr r3, [r3, #4]
800556a: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800556e: 687b ldr r3, [r7, #4]
8005570: 691b ldr r3, [r3, #16]
8005572: 00db lsls r3, r3, #3
8005574: 490e ldr r1, [pc, #56] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005576: 4313 orrs r3, r2
8005578: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
800557a: f000 f821 bl 80055c0 <HAL_RCC_GetSysClockFreq>
800557e: 4602 mov r2, r0
8005580: 4b0b ldr r3, [pc, #44] @ (80055b0 <HAL_RCC_ClockConfig+0x1c4>)
8005582: 685b ldr r3, [r3, #4]
8005584: 091b lsrs r3, r3, #4
8005586: f003 030f and.w r3, r3, #15
800558a: 490a ldr r1, [pc, #40] @ (80055b4 <HAL_RCC_ClockConfig+0x1c8>)
800558c: 5ccb ldrb r3, [r1, r3]
800558e: fa22 f303 lsr.w r3, r2, r3
8005592: 4a09 ldr r2, [pc, #36] @ (80055b8 <HAL_RCC_ClockConfig+0x1cc>)
8005594: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8005596: 4b09 ldr r3, [pc, #36] @ (80055bc <HAL_RCC_ClockConfig+0x1d0>)
8005598: 681b ldr r3, [r3, #0]
800559a: 4618 mov r0, r3
800559c: f7fd fc62 bl 8002e64 <HAL_InitTick>
return HAL_OK;
80055a0: 2300 movs r3, #0
}
80055a2: 4618 mov r0, r3
80055a4: 3710 adds r7, #16
80055a6: 46bd mov sp, r7
80055a8: bd80 pop {r7, pc}
80055aa: bf00 nop
80055ac: 40022000 .word 0x40022000
80055b0: 40021000 .word 0x40021000
80055b4: 080067e4 .word 0x080067e4
80055b8: 20000034 .word 0x20000034
80055bc: 20000038 .word 0x20000038
080055c0 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80055c0: b480 push {r7}
80055c2: b087 sub sp, #28
80055c4: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80055c6: 2300 movs r3, #0
80055c8: 60fb str r3, [r7, #12]
80055ca: 2300 movs r3, #0
80055cc: 60bb str r3, [r7, #8]
80055ce: 2300 movs r3, #0
80055d0: 617b str r3, [r7, #20]
80055d2: 2300 movs r3, #0
80055d4: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80055d6: 2300 movs r3, #0
80055d8: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80055da: 4b1e ldr r3, [pc, #120] @ (8005654 <HAL_RCC_GetSysClockFreq+0x94>)
80055dc: 685b ldr r3, [r3, #4]
80055de: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80055e0: 68fb ldr r3, [r7, #12]
80055e2: f003 030c and.w r3, r3, #12
80055e6: 2b04 cmp r3, #4
80055e8: d002 beq.n 80055f0 <HAL_RCC_GetSysClockFreq+0x30>
80055ea: 2b08 cmp r3, #8
80055ec: d003 beq.n 80055f6 <HAL_RCC_GetSysClockFreq+0x36>
80055ee: e027 b.n 8005640 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80055f0: 4b19 ldr r3, [pc, #100] @ (8005658 <HAL_RCC_GetSysClockFreq+0x98>)
80055f2: 613b str r3, [r7, #16]
break;
80055f4: e027 b.n 8005646 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80055f6: 68fb ldr r3, [r7, #12]
80055f8: 0c9b lsrs r3, r3, #18
80055fa: f003 030f and.w r3, r3, #15
80055fe: 4a17 ldr r2, [pc, #92] @ (800565c <HAL_RCC_GetSysClockFreq+0x9c>)
8005600: 5cd3 ldrb r3, [r2, r3]
8005602: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8005604: 68fb ldr r3, [r7, #12]
8005606: f403 3380 and.w r3, r3, #65536 @ 0x10000
800560a: 2b00 cmp r3, #0
800560c: d010 beq.n 8005630 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
800560e: 4b11 ldr r3, [pc, #68] @ (8005654 <HAL_RCC_GetSysClockFreq+0x94>)
8005610: 685b ldr r3, [r3, #4]
8005612: 0c5b lsrs r3, r3, #17
8005614: f003 0301 and.w r3, r3, #1
8005618: 4a11 ldr r2, [pc, #68] @ (8005660 <HAL_RCC_GetSysClockFreq+0xa0>)
800561a: 5cd3 ldrb r3, [r2, r3]
800561c: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
800561e: 687b ldr r3, [r7, #4]
8005620: 4a0d ldr r2, [pc, #52] @ (8005658 <HAL_RCC_GetSysClockFreq+0x98>)
8005622: fb03 f202 mul.w r2, r3, r2
8005626: 68bb ldr r3, [r7, #8]
8005628: fbb2 f3f3 udiv r3, r2, r3
800562c: 617b str r3, [r7, #20]
800562e: e004 b.n 800563a <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8005630: 687b ldr r3, [r7, #4]
8005632: 4a0c ldr r2, [pc, #48] @ (8005664 <HAL_RCC_GetSysClockFreq+0xa4>)
8005634: fb02 f303 mul.w r3, r2, r3
8005638: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
800563a: 697b ldr r3, [r7, #20]
800563c: 613b str r3, [r7, #16]
break;
800563e: e002 b.n 8005646 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8005640: 4b09 ldr r3, [pc, #36] @ (8005668 <HAL_RCC_GetSysClockFreq+0xa8>)
8005642: 613b str r3, [r7, #16]
break;
8005644: bf00 nop
}
}
return sysclockfreq;
8005646: 693b ldr r3, [r7, #16]
}
8005648: 4618 mov r0, r3
800564a: 371c adds r7, #28
800564c: 46bd mov sp, r7
800564e: bc80 pop {r7}
8005650: 4770 bx lr
8005652: bf00 nop
8005654: 40021000 .word 0x40021000
8005658: 00b71b00 .word 0x00b71b00
800565c: 080067fc .word 0x080067fc
8005660: 0800680c .word 0x0800680c
8005664: 003d0900 .word 0x003d0900
8005668: 007a1200 .word 0x007a1200
0800566c <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800566c: b480 push {r7}
800566e: af00 add r7, sp, #0
return SystemCoreClock;
8005670: 4b02 ldr r3, [pc, #8] @ (800567c <HAL_RCC_GetHCLKFreq+0x10>)
8005672: 681b ldr r3, [r3, #0]
}
8005674: 4618 mov r0, r3
8005676: 46bd mov sp, r7
8005678: bc80 pop {r7}
800567a: 4770 bx lr
800567c: 20000034 .word 0x20000034
08005680 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8005680: b580 push {r7, lr}
8005682: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8005684: f7ff fff2 bl 800566c <HAL_RCC_GetHCLKFreq>
8005688: 4602 mov r2, r0
800568a: 4b05 ldr r3, [pc, #20] @ (80056a0 <HAL_RCC_GetPCLK1Freq+0x20>)
800568c: 685b ldr r3, [r3, #4]
800568e: 0a1b lsrs r3, r3, #8
8005690: f003 0307 and.w r3, r3, #7
8005694: 4903 ldr r1, [pc, #12] @ (80056a4 <HAL_RCC_GetPCLK1Freq+0x24>)
8005696: 5ccb ldrb r3, [r1, r3]
8005698: fa22 f303 lsr.w r3, r2, r3
}
800569c: 4618 mov r0, r3
800569e: bd80 pop {r7, pc}
80056a0: 40021000 .word 0x40021000
80056a4: 080067f4 .word 0x080067f4
080056a8 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80056a8: b580 push {r7, lr}
80056aa: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
80056ac: f7ff ffde bl 800566c <HAL_RCC_GetHCLKFreq>
80056b0: 4602 mov r2, r0
80056b2: 4b05 ldr r3, [pc, #20] @ (80056c8 <HAL_RCC_GetPCLK2Freq+0x20>)
80056b4: 685b ldr r3, [r3, #4]
80056b6: 0adb lsrs r3, r3, #11
80056b8: f003 0307 and.w r3, r3, #7
80056bc: 4903 ldr r1, [pc, #12] @ (80056cc <HAL_RCC_GetPCLK2Freq+0x24>)
80056be: 5ccb ldrb r3, [r1, r3]
80056c0: fa22 f303 lsr.w r3, r2, r3
}
80056c4: 4618 mov r0, r3
80056c6: bd80 pop {r7, pc}
80056c8: 40021000 .word 0x40021000
80056cc: 080067f4 .word 0x080067f4
080056d0 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
80056d0: b480 push {r7}
80056d2: b085 sub sp, #20
80056d4: af00 add r7, sp, #0
80056d6: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
80056d8: 4b0a ldr r3, [pc, #40] @ (8005704 <RCC_Delay+0x34>)
80056da: 681b ldr r3, [r3, #0]
80056dc: 4a0a ldr r2, [pc, #40] @ (8005708 <RCC_Delay+0x38>)
80056de: fba2 2303 umull r2, r3, r2, r3
80056e2: 0a5b lsrs r3, r3, #9
80056e4: 687a ldr r2, [r7, #4]
80056e6: fb02 f303 mul.w r3, r2, r3
80056ea: 60fb str r3, [r7, #12]
do
{
__NOP();
80056ec: bf00 nop
}
while (Delay --);
80056ee: 68fb ldr r3, [r7, #12]
80056f0: 1e5a subs r2, r3, #1
80056f2: 60fa str r2, [r7, #12]
80056f4: 2b00 cmp r3, #0
80056f6: d1f9 bne.n 80056ec <RCC_Delay+0x1c>
}
80056f8: bf00 nop
80056fa: bf00 nop
80056fc: 3714 adds r7, #20
80056fe: 46bd mov sp, r7
8005700: bc80 pop {r7}
8005702: 4770 bx lr
8005704: 20000034 .word 0x20000034
8005708: 10624dd3 .word 0x10624dd3
0800570c <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
800570c: b580 push {r7, lr}
800570e: b086 sub sp, #24
8005710: af00 add r7, sp, #0
8005712: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8005714: 2300 movs r3, #0
8005716: 613b str r3, [r7, #16]
8005718: 2300 movs r3, #0
800571a: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
800571c: 687b ldr r3, [r7, #4]
800571e: 681b ldr r3, [r3, #0]
8005720: f003 0301 and.w r3, r3, #1
8005724: 2b00 cmp r3, #0
8005726: d07d beq.n 8005824 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8005728: 2300 movs r3, #0
800572a: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800572c: 4b4f ldr r3, [pc, #316] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800572e: 69db ldr r3, [r3, #28]
8005730: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005734: 2b00 cmp r3, #0
8005736: d10d bne.n 8005754 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005738: 4b4c ldr r3, [pc, #304] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800573a: 69db ldr r3, [r3, #28]
800573c: 4a4b ldr r2, [pc, #300] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800573e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005742: 61d3 str r3, [r2, #28]
8005744: 4b49 ldr r3, [pc, #292] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005746: 69db ldr r3, [r3, #28]
8005748: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800574c: 60bb str r3, [r7, #8]
800574e: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8005750: 2301 movs r3, #1
8005752: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005754: 4b46 ldr r3, [pc, #280] @ (8005870 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005756: 681b ldr r3, [r3, #0]
8005758: f403 7380 and.w r3, r3, #256 @ 0x100
800575c: 2b00 cmp r3, #0
800575e: d118 bne.n 8005792 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8005760: 4b43 ldr r3, [pc, #268] @ (8005870 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005762: 681b ldr r3, [r3, #0]
8005764: 4a42 ldr r2, [pc, #264] @ (8005870 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005766: f443 7380 orr.w r3, r3, #256 @ 0x100
800576a: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800576c: f7fd fbbc bl 8002ee8 <HAL_GetTick>
8005770: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005772: e008 b.n 8005786 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005774: f7fd fbb8 bl 8002ee8 <HAL_GetTick>
8005778: 4602 mov r2, r0
800577a: 693b ldr r3, [r7, #16]
800577c: 1ad3 subs r3, r2, r3
800577e: 2b64 cmp r3, #100 @ 0x64
8005780: d901 bls.n 8005786 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8005782: 2303 movs r3, #3
8005784: e06d b.n 8005862 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005786: 4b3a ldr r3, [pc, #232] @ (8005870 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005788: 681b ldr r3, [r3, #0]
800578a: f403 7380 and.w r3, r3, #256 @ 0x100
800578e: 2b00 cmp r3, #0
8005790: d0f0 beq.n 8005774 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8005792: 4b36 ldr r3, [pc, #216] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005794: 6a1b ldr r3, [r3, #32]
8005796: f403 7340 and.w r3, r3, #768 @ 0x300
800579a: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
800579c: 68fb ldr r3, [r7, #12]
800579e: 2b00 cmp r3, #0
80057a0: d02e beq.n 8005800 <HAL_RCCEx_PeriphCLKConfig+0xf4>
80057a2: 687b ldr r3, [r7, #4]
80057a4: 685b ldr r3, [r3, #4]
80057a6: f403 7340 and.w r3, r3, #768 @ 0x300
80057aa: 68fa ldr r2, [r7, #12]
80057ac: 429a cmp r2, r3
80057ae: d027 beq.n 8005800 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80057b0: 4b2e ldr r3, [pc, #184] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
80057b2: 6a1b ldr r3, [r3, #32]
80057b4: f423 7340 bic.w r3, r3, #768 @ 0x300
80057b8: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80057ba: 4b2e ldr r3, [pc, #184] @ (8005874 <HAL_RCCEx_PeriphCLKConfig+0x168>)
80057bc: 2201 movs r2, #1
80057be: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
80057c0: 4b2c ldr r3, [pc, #176] @ (8005874 <HAL_RCCEx_PeriphCLKConfig+0x168>)
80057c2: 2200 movs r2, #0
80057c4: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
80057c6: 4a29 ldr r2, [pc, #164] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
80057c8: 68fb ldr r3, [r7, #12]
80057ca: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
80057cc: 68fb ldr r3, [r7, #12]
80057ce: f003 0301 and.w r3, r3, #1
80057d2: 2b00 cmp r3, #0
80057d4: d014 beq.n 8005800 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80057d6: f7fd fb87 bl 8002ee8 <HAL_GetTick>
80057da: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80057dc: e00a b.n 80057f4 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80057de: f7fd fb83 bl 8002ee8 <HAL_GetTick>
80057e2: 4602 mov r2, r0
80057e4: 693b ldr r3, [r7, #16]
80057e6: 1ad3 subs r3, r2, r3
80057e8: f241 3288 movw r2, #5000 @ 0x1388
80057ec: 4293 cmp r3, r2
80057ee: d901 bls.n 80057f4 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
80057f0: 2303 movs r3, #3
80057f2: e036 b.n 8005862 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80057f4: 4b1d ldr r3, [pc, #116] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
80057f6: 6a1b ldr r3, [r3, #32]
80057f8: f003 0302 and.w r3, r3, #2
80057fc: 2b00 cmp r3, #0
80057fe: d0ee beq.n 80057de <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005800: 4b1a ldr r3, [pc, #104] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005802: 6a1b ldr r3, [r3, #32]
8005804: f423 7240 bic.w r2, r3, #768 @ 0x300
8005808: 687b ldr r3, [r7, #4]
800580a: 685b ldr r3, [r3, #4]
800580c: 4917 ldr r1, [pc, #92] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800580e: 4313 orrs r3, r2
8005810: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005812: 7dfb ldrb r3, [r7, #23]
8005814: 2b01 cmp r3, #1
8005816: d105 bne.n 8005824 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005818: 4b14 ldr r3, [pc, #80] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800581a: 69db ldr r3, [r3, #28]
800581c: 4a13 ldr r2, [pc, #76] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800581e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005822: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8005824: 687b ldr r3, [r7, #4]
8005826: 681b ldr r3, [r3, #0]
8005828: f003 0302 and.w r3, r3, #2
800582c: 2b00 cmp r3, #0
800582e: d008 beq.n 8005842 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8005830: 4b0e ldr r3, [pc, #56] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005832: 685b ldr r3, [r3, #4]
8005834: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8005838: 687b ldr r3, [r7, #4]
800583a: 689b ldr r3, [r3, #8]
800583c: 490b ldr r1, [pc, #44] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800583e: 4313 orrs r3, r2
8005840: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8005842: 687b ldr r3, [r7, #4]
8005844: 681b ldr r3, [r3, #0]
8005846: f003 0310 and.w r3, r3, #16
800584a: 2b00 cmp r3, #0
800584c: d008 beq.n 8005860 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
800584e: 4b07 ldr r3, [pc, #28] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005850: 685b ldr r3, [r3, #4]
8005852: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8005856: 687b ldr r3, [r7, #4]
8005858: 68db ldr r3, [r3, #12]
800585a: 4904 ldr r1, [pc, #16] @ (800586c <HAL_RCCEx_PeriphCLKConfig+0x160>)
800585c: 4313 orrs r3, r2
800585e: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8005860: 2300 movs r3, #0
}
8005862: 4618 mov r0, r3
8005864: 3718 adds r7, #24
8005866: 46bd mov sp, r7
8005868: bd80 pop {r7, pc}
800586a: bf00 nop
800586c: 40021000 .word 0x40021000
8005870: 40007000 .word 0x40007000
8005874: 42420440 .word 0x42420440
08005878 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005878: b580 push {r7, lr}
800587a: b082 sub sp, #8
800587c: af00 add r7, sp, #0
800587e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005880: 687b ldr r3, [r7, #4]
8005882: 2b00 cmp r3, #0
8005884: d101 bne.n 800588a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8005886: 2301 movs r3, #1
8005888: e042 b.n 8005910 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
800588a: 687b ldr r3, [r7, #4]
800588c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005890: b2db uxtb r3, r3
8005892: 2b00 cmp r3, #0
8005894: d106 bne.n 80058a4 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8005896: 687b ldr r3, [r7, #4]
8005898: 2200 movs r2, #0
800589a: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800589e: 6878 ldr r0, [r7, #4]
80058a0: f7fd fa50 bl 8002d44 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80058a4: 687b ldr r3, [r7, #4]
80058a6: 2224 movs r2, #36 @ 0x24
80058a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80058ac: 687b ldr r3, [r7, #4]
80058ae: 681b ldr r3, [r3, #0]
80058b0: 68da ldr r2, [r3, #12]
80058b2: 687b ldr r3, [r7, #4]
80058b4: 681b ldr r3, [r3, #0]
80058b6: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80058ba: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80058bc: 6878 ldr r0, [r7, #4]
80058be: f000 fd63 bl 8006388 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80058c2: 687b ldr r3, [r7, #4]
80058c4: 681b ldr r3, [r3, #0]
80058c6: 691a ldr r2, [r3, #16]
80058c8: 687b ldr r3, [r7, #4]
80058ca: 681b ldr r3, [r3, #0]
80058cc: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80058d0: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80058d2: 687b ldr r3, [r7, #4]
80058d4: 681b ldr r3, [r3, #0]
80058d6: 695a ldr r2, [r3, #20]
80058d8: 687b ldr r3, [r7, #4]
80058da: 681b ldr r3, [r3, #0]
80058dc: f022 022a bic.w r2, r2, #42 @ 0x2a
80058e0: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80058e2: 687b ldr r3, [r7, #4]
80058e4: 681b ldr r3, [r3, #0]
80058e6: 68da ldr r2, [r3, #12]
80058e8: 687b ldr r3, [r7, #4]
80058ea: 681b ldr r3, [r3, #0]
80058ec: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80058f0: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80058f2: 687b ldr r3, [r7, #4]
80058f4: 2200 movs r2, #0
80058f6: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
80058f8: 687b ldr r3, [r7, #4]
80058fa: 2220 movs r2, #32
80058fc: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8005900: 687b ldr r3, [r7, #4]
8005902: 2220 movs r2, #32
8005904: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005908: 687b ldr r3, [r7, #4]
800590a: 2200 movs r2, #0
800590c: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
800590e: 2300 movs r3, #0
}
8005910: 4618 mov r0, r3
8005912: 3708 adds r7, #8
8005914: 46bd mov sp, r7
8005916: bd80 pop {r7, pc}
08005918 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8005918: b580 push {r7, lr}
800591a: b08a sub sp, #40 @ 0x28
800591c: af02 add r7, sp, #8
800591e: 60f8 str r0, [r7, #12]
8005920: 60b9 str r1, [r7, #8]
8005922: 603b str r3, [r7, #0]
8005924: 4613 mov r3, r2
8005926: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8005928: 2300 movs r3, #0
800592a: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800592c: 68fb ldr r3, [r7, #12]
800592e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005932: b2db uxtb r3, r3
8005934: 2b20 cmp r3, #32
8005936: d175 bne.n 8005a24 <HAL_UART_Transmit+0x10c>
{
if ((pData == NULL) || (Size == 0U))
8005938: 68bb ldr r3, [r7, #8]
800593a: 2b00 cmp r3, #0
800593c: d002 beq.n 8005944 <HAL_UART_Transmit+0x2c>
800593e: 88fb ldrh r3, [r7, #6]
8005940: 2b00 cmp r3, #0
8005942: d101 bne.n 8005948 <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
8005944: 2301 movs r3, #1
8005946: e06e b.n 8005a26 <HAL_UART_Transmit+0x10e>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005948: 68fb ldr r3, [r7, #12]
800594a: 2200 movs r2, #0
800594c: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_BUSY_TX;
800594e: 68fb ldr r3, [r7, #12]
8005950: 2221 movs r2, #33 @ 0x21
8005952: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8005956: f7fd fac7 bl 8002ee8 <HAL_GetTick>
800595a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
800595c: 68fb ldr r3, [r7, #12]
800595e: 88fa ldrh r2, [r7, #6]
8005960: 849a strh r2, [r3, #36] @ 0x24
huart->TxXferCount = Size;
8005962: 68fb ldr r3, [r7, #12]
8005964: 88fa ldrh r2, [r7, #6]
8005966: 84da strh r2, [r3, #38] @ 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005968: 68fb ldr r3, [r7, #12]
800596a: 689b ldr r3, [r3, #8]
800596c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005970: d108 bne.n 8005984 <HAL_UART_Transmit+0x6c>
8005972: 68fb ldr r3, [r7, #12]
8005974: 691b ldr r3, [r3, #16]
8005976: 2b00 cmp r3, #0
8005978: d104 bne.n 8005984 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
800597a: 2300 movs r3, #0
800597c: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
800597e: 68bb ldr r3, [r7, #8]
8005980: 61bb str r3, [r7, #24]
8005982: e003 b.n 800598c <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8005984: 68bb ldr r3, [r7, #8]
8005986: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8005988: 2300 movs r3, #0
800598a: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
800598c: e02e b.n 80059ec <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
800598e: 683b ldr r3, [r7, #0]
8005990: 9300 str r3, [sp, #0]
8005992: 697b ldr r3, [r7, #20]
8005994: 2200 movs r2, #0
8005996: 2180 movs r1, #128 @ 0x80
8005998: 68f8 ldr r0, [r7, #12]
800599a: f000 fb01 bl 8005fa0 <UART_WaitOnFlagUntilTimeout>
800599e: 4603 mov r3, r0
80059a0: 2b00 cmp r3, #0
80059a2: d005 beq.n 80059b0 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
80059a4: 68fb ldr r3, [r7, #12]
80059a6: 2220 movs r2, #32
80059a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
80059ac: 2303 movs r3, #3
80059ae: e03a b.n 8005a26 <HAL_UART_Transmit+0x10e>
}
if (pdata8bits == NULL)
80059b0: 69fb ldr r3, [r7, #28]
80059b2: 2b00 cmp r3, #0
80059b4: d10b bne.n 80059ce <HAL_UART_Transmit+0xb6>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
80059b6: 69bb ldr r3, [r7, #24]
80059b8: 881b ldrh r3, [r3, #0]
80059ba: 461a mov r2, r3
80059bc: 68fb ldr r3, [r7, #12]
80059be: 681b ldr r3, [r3, #0]
80059c0: f3c2 0208 ubfx r2, r2, #0, #9
80059c4: 605a str r2, [r3, #4]
pdata16bits++;
80059c6: 69bb ldr r3, [r7, #24]
80059c8: 3302 adds r3, #2
80059ca: 61bb str r3, [r7, #24]
80059cc: e007 b.n 80059de <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
80059ce: 69fb ldr r3, [r7, #28]
80059d0: 781a ldrb r2, [r3, #0]
80059d2: 68fb ldr r3, [r7, #12]
80059d4: 681b ldr r3, [r3, #0]
80059d6: 605a str r2, [r3, #4]
pdata8bits++;
80059d8: 69fb ldr r3, [r7, #28]
80059da: 3301 adds r3, #1
80059dc: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
80059de: 68fb ldr r3, [r7, #12]
80059e0: 8cdb ldrh r3, [r3, #38] @ 0x26
80059e2: b29b uxth r3, r3
80059e4: 3b01 subs r3, #1
80059e6: b29a uxth r2, r3
80059e8: 68fb ldr r3, [r7, #12]
80059ea: 84da strh r2, [r3, #38] @ 0x26
while (huart->TxXferCount > 0U)
80059ec: 68fb ldr r3, [r7, #12]
80059ee: 8cdb ldrh r3, [r3, #38] @ 0x26
80059f0: b29b uxth r3, r3
80059f2: 2b00 cmp r3, #0
80059f4: d1cb bne.n 800598e <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80059f6: 683b ldr r3, [r7, #0]
80059f8: 9300 str r3, [sp, #0]
80059fa: 697b ldr r3, [r7, #20]
80059fc: 2200 movs r2, #0
80059fe: 2140 movs r1, #64 @ 0x40
8005a00: 68f8 ldr r0, [r7, #12]
8005a02: f000 facd bl 8005fa0 <UART_WaitOnFlagUntilTimeout>
8005a06: 4603 mov r3, r0
8005a08: 2b00 cmp r3, #0
8005a0a: d005 beq.n 8005a18 <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8005a0c: 68fb ldr r3, [r7, #12]
8005a0e: 2220 movs r2, #32
8005a10: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_TIMEOUT;
8005a14: 2303 movs r3, #3
8005a16: e006 b.n 8005a26 <HAL_UART_Transmit+0x10e>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8005a18: 68fb ldr r3, [r7, #12]
8005a1a: 2220 movs r2, #32
8005a1c: f883 2041 strb.w r2, [r3, #65] @ 0x41
return HAL_OK;
8005a20: 2300 movs r3, #0
8005a22: e000 b.n 8005a26 <HAL_UART_Transmit+0x10e>
}
else
{
return HAL_BUSY;
8005a24: 2302 movs r3, #2
}
}
8005a26: 4618 mov r0, r3
8005a28: 3720 adds r7, #32
8005a2a: 46bd mov sp, r7
8005a2c: bd80 pop {r7, pc}
...
08005a30 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8005a30: b580 push {r7, lr}
8005a32: b0ba sub sp, #232 @ 0xe8
8005a34: af00 add r7, sp, #0
8005a36: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
8005a38: 687b ldr r3, [r7, #4]
8005a3a: 681b ldr r3, [r3, #0]
8005a3c: 681b ldr r3, [r3, #0]
8005a3e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8005a42: 687b ldr r3, [r7, #4]
8005a44: 681b ldr r3, [r3, #0]
8005a46: 68db ldr r3, [r3, #12]
8005a48: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8005a4c: 687b ldr r3, [r7, #4]
8005a4e: 681b ldr r3, [r3, #0]
8005a50: 695b ldr r3, [r3, #20]
8005a52: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags = 0x00U;
8005a56: 2300 movs r3, #0
8005a58: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
uint32_t dmarequest = 0x00U;
8005a5c: 2300 movs r3, #0
8005a5e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
8005a62: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005a66: f003 030f and.w r3, r3, #15
8005a6a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == RESET)
8005a6e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005a72: 2b00 cmp r3, #0
8005a74: d10f bne.n 8005a96 <HAL_UART_IRQHandler+0x66>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8005a76: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005a7a: f003 0320 and.w r3, r3, #32
8005a7e: 2b00 cmp r3, #0
8005a80: d009 beq.n 8005a96 <HAL_UART_IRQHandler+0x66>
8005a82: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005a86: f003 0320 and.w r3, r3, #32
8005a8a: 2b00 cmp r3, #0
8005a8c: d003 beq.n 8005a96 <HAL_UART_IRQHandler+0x66>
{
UART_Receive_IT(huart);
8005a8e: 6878 ldr r0, [r7, #4]
8005a90: f000 fbbc bl 800620c <UART_Receive_IT>
return;
8005a94: e25b b.n 8005f4e <HAL_UART_IRQHandler+0x51e>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
8005a96: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8005a9a: 2b00 cmp r3, #0
8005a9c: f000 80de beq.w 8005c5c <HAL_UART_IRQHandler+0x22c>
8005aa0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005aa4: f003 0301 and.w r3, r3, #1
8005aa8: 2b00 cmp r3, #0
8005aaa: d106 bne.n 8005aba <HAL_UART_IRQHandler+0x8a>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8005aac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005ab0: f403 7390 and.w r3, r3, #288 @ 0x120
8005ab4: 2b00 cmp r3, #0
8005ab6: f000 80d1 beq.w 8005c5c <HAL_UART_IRQHandler+0x22c>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
8005aba: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005abe: f003 0301 and.w r3, r3, #1
8005ac2: 2b00 cmp r3, #0
8005ac4: d00b beq.n 8005ade <HAL_UART_IRQHandler+0xae>
8005ac6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005aca: f403 7380 and.w r3, r3, #256 @ 0x100
8005ace: 2b00 cmp r3, #0
8005ad0: d005 beq.n 8005ade <HAL_UART_IRQHandler+0xae>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
8005ad2: 687b ldr r3, [r7, #4]
8005ad4: 6c5b ldr r3, [r3, #68] @ 0x44
8005ad6: f043 0201 orr.w r2, r3, #1
8005ada: 687b ldr r3, [r7, #4]
8005adc: 645a str r2, [r3, #68] @ 0x44
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005ade: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005ae2: f003 0304 and.w r3, r3, #4
8005ae6: 2b00 cmp r3, #0
8005ae8: d00b beq.n 8005b02 <HAL_UART_IRQHandler+0xd2>
8005aea: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005aee: f003 0301 and.w r3, r3, #1
8005af2: 2b00 cmp r3, #0
8005af4: d005 beq.n 8005b02 <HAL_UART_IRQHandler+0xd2>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
8005af6: 687b ldr r3, [r7, #4]
8005af8: 6c5b ldr r3, [r3, #68] @ 0x44
8005afa: f043 0202 orr.w r2, r3, #2
8005afe: 687b ldr r3, [r7, #4]
8005b00: 645a str r2, [r3, #68] @ 0x44
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8005b02: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b06: f003 0302 and.w r3, r3, #2
8005b0a: 2b00 cmp r3, #0
8005b0c: d00b beq.n 8005b26 <HAL_UART_IRQHandler+0xf6>
8005b0e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005b12: f003 0301 and.w r3, r3, #1
8005b16: 2b00 cmp r3, #0
8005b18: d005 beq.n 8005b26 <HAL_UART_IRQHandler+0xf6>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
8005b1a: 687b ldr r3, [r7, #4]
8005b1c: 6c5b ldr r3, [r3, #68] @ 0x44
8005b1e: f043 0204 orr.w r2, r3, #4
8005b22: 687b ldr r3, [r7, #4]
8005b24: 645a str r2, [r3, #68] @ 0x44
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
8005b26: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b2a: f003 0308 and.w r3, r3, #8
8005b2e: 2b00 cmp r3, #0
8005b30: d011 beq.n 8005b56 <HAL_UART_IRQHandler+0x126>
8005b32: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005b36: f003 0320 and.w r3, r3, #32
8005b3a: 2b00 cmp r3, #0
8005b3c: d105 bne.n 8005b4a <HAL_UART_IRQHandler+0x11a>
|| ((cr3its & USART_CR3_EIE) != RESET)))
8005b3e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8005b42: f003 0301 and.w r3, r3, #1
8005b46: 2b00 cmp r3, #0
8005b48: d005 beq.n 8005b56 <HAL_UART_IRQHandler+0x126>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8005b4a: 687b ldr r3, [r7, #4]
8005b4c: 6c5b ldr r3, [r3, #68] @ 0x44
8005b4e: f043 0208 orr.w r2, r3, #8
8005b52: 687b ldr r3, [r7, #4]
8005b54: 645a str r2, [r3, #68] @ 0x44
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8005b56: 687b ldr r3, [r7, #4]
8005b58: 6c5b ldr r3, [r3, #68] @ 0x44
8005b5a: 2b00 cmp r3, #0
8005b5c: f000 81f2 beq.w 8005f44 <HAL_UART_IRQHandler+0x514>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8005b60: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005b64: f003 0320 and.w r3, r3, #32
8005b68: 2b00 cmp r3, #0
8005b6a: d008 beq.n 8005b7e <HAL_UART_IRQHandler+0x14e>
8005b6c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005b70: f003 0320 and.w r3, r3, #32
8005b74: 2b00 cmp r3, #0
8005b76: d002 beq.n 8005b7e <HAL_UART_IRQHandler+0x14e>
{
UART_Receive_IT(huart);
8005b78: 6878 ldr r0, [r7, #4]
8005b7a: f000 fb47 bl 800620c <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 681b ldr r3, [r3, #0]
8005b82: 695b ldr r3, [r3, #20]
8005b84: f003 0340 and.w r3, r3, #64 @ 0x40
8005b88: 2b00 cmp r3, #0
8005b8a: bf14 ite ne
8005b8c: 2301 movne r3, #1
8005b8e: 2300 moveq r3, #0
8005b90: b2db uxtb r3, r3
8005b92: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
8005b96: 687b ldr r3, [r7, #4]
8005b98: 6c5b ldr r3, [r3, #68] @ 0x44
8005b9a: f003 0308 and.w r3, r3, #8
8005b9e: 2b00 cmp r3, #0
8005ba0: d103 bne.n 8005baa <HAL_UART_IRQHandler+0x17a>
8005ba2: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8005ba6: 2b00 cmp r3, #0
8005ba8: d04f beq.n 8005c4a <HAL_UART_IRQHandler+0x21a>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8005baa: 6878 ldr r0, [r7, #4]
8005bac: f000 fa51 bl 8006052 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005bb0: 687b ldr r3, [r7, #4]
8005bb2: 681b ldr r3, [r3, #0]
8005bb4: 695b ldr r3, [r3, #20]
8005bb6: f003 0340 and.w r3, r3, #64 @ 0x40
8005bba: 2b00 cmp r3, #0
8005bbc: d041 beq.n 8005c42 <HAL_UART_IRQHandler+0x212>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 681b ldr r3, [r3, #0]
8005bc2: 3314 adds r3, #20
8005bc4: f8c7 309c str.w r3, [r7, #156] @ 0x9c
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005bc8: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8005bcc: e853 3f00 ldrex r3, [r3]
8005bd0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8005bd4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8005bd8: f023 0340 bic.w r3, r3, #64 @ 0x40
8005bdc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8005be0: 687b ldr r3, [r7, #4]
8005be2: 681b ldr r3, [r3, #0]
8005be4: 3314 adds r3, #20
8005be6: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
8005bea: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
8005bee: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005bf2: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
8005bf6: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
8005bfa: e841 2300 strex r3, r2, [r1]
8005bfe: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8005c02: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8005c06: 2b00 cmp r3, #0
8005c08: d1d9 bne.n 8005bbe <HAL_UART_IRQHandler+0x18e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8005c0a: 687b ldr r3, [r7, #4]
8005c0c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c0e: 2b00 cmp r3, #0
8005c10: d013 beq.n 8005c3a <HAL_UART_IRQHandler+0x20a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8005c12: 687b ldr r3, [r7, #4]
8005c14: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c16: 4a7e ldr r2, [pc, #504] @ (8005e10 <HAL_UART_IRQHandler+0x3e0>)
8005c18: 635a str r2, [r3, #52] @ 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8005c1a: 687b ldr r3, [r7, #4]
8005c1c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c1e: 4618 mov r0, r3
8005c20: f7fd fcea bl 80035f8 <HAL_DMA_Abort_IT>
8005c24: 4603 mov r3, r0
8005c26: 2b00 cmp r3, #0
8005c28: d016 beq.n 8005c58 <HAL_UART_IRQHandler+0x228>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8005c2a: 687b ldr r3, [r7, #4]
8005c2c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005c2e: 6b5b ldr r3, [r3, #52] @ 0x34
8005c30: 687a ldr r2, [r7, #4]
8005c32: 6bd2 ldr r2, [r2, #60] @ 0x3c
8005c34: 4610 mov r0, r2
8005c36: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c38: e00e b.n 8005c58 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005c3a: 6878 ldr r0, [r7, #4]
8005c3c: f000 f99c bl 8005f78 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c40: e00a b.n 8005c58 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005c42: 6878 ldr r0, [r7, #4]
8005c44: f000 f998 bl 8005f78 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c48: e006 b.n 8005c58 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005c4a: 6878 ldr r0, [r7, #4]
8005c4c: f000 f994 bl 8005f78 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005c50: 687b ldr r3, [r7, #4]
8005c52: 2200 movs r2, #0
8005c54: 645a str r2, [r3, #68] @ 0x44
}
}
return;
8005c56: e175 b.n 8005f44 <HAL_UART_IRQHandler+0x514>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c58: bf00 nop
return;
8005c5a: e173 b.n 8005f44 <HAL_UART_IRQHandler+0x514>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005c5c: 687b ldr r3, [r7, #4]
8005c5e: 6b1b ldr r3, [r3, #48] @ 0x30
8005c60: 2b01 cmp r3, #1
8005c62: f040 814f bne.w 8005f04 <HAL_UART_IRQHandler+0x4d4>
&& ((isrflags & USART_SR_IDLE) != 0U)
8005c66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005c6a: f003 0310 and.w r3, r3, #16
8005c6e: 2b00 cmp r3, #0
8005c70: f000 8148 beq.w 8005f04 <HAL_UART_IRQHandler+0x4d4>
&& ((cr1its & USART_SR_IDLE) != 0U))
8005c74: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005c78: f003 0310 and.w r3, r3, #16
8005c7c: 2b00 cmp r3, #0
8005c7e: f000 8141 beq.w 8005f04 <HAL_UART_IRQHandler+0x4d4>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
8005c82: 2300 movs r3, #0
8005c84: 60bb str r3, [r7, #8]
8005c86: 687b ldr r3, [r7, #4]
8005c88: 681b ldr r3, [r3, #0]
8005c8a: 681b ldr r3, [r3, #0]
8005c8c: 60bb str r3, [r7, #8]
8005c8e: 687b ldr r3, [r7, #4]
8005c90: 681b ldr r3, [r3, #0]
8005c92: 685b ldr r3, [r3, #4]
8005c94: 60bb str r3, [r7, #8]
8005c96: 68bb ldr r3, [r7, #8]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005c98: 687b ldr r3, [r7, #4]
8005c9a: 681b ldr r3, [r3, #0]
8005c9c: 695b ldr r3, [r3, #20]
8005c9e: f003 0340 and.w r3, r3, #64 @ 0x40
8005ca2: 2b00 cmp r3, #0
8005ca4: f000 80b6 beq.w 8005e14 <HAL_UART_IRQHandler+0x3e4>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8005ca8: 687b ldr r3, [r7, #4]
8005caa: 6bdb ldr r3, [r3, #60] @ 0x3c
8005cac: 681b ldr r3, [r3, #0]
8005cae: 685b ldr r3, [r3, #4]
8005cb0: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
8005cb4: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8005cb8: 2b00 cmp r3, #0
8005cba: f000 8145 beq.w 8005f48 <HAL_UART_IRQHandler+0x518>
&& (nb_remaining_rx_data < huart->RxXferSize))
8005cbe: 687b ldr r3, [r7, #4]
8005cc0: 8d9b ldrh r3, [r3, #44] @ 0x2c
8005cc2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005cc6: 429a cmp r2, r3
8005cc8: f080 813e bcs.w 8005f48 <HAL_UART_IRQHandler+0x518>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8005ccc: 687b ldr r3, [r7, #4]
8005cce: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8005cd2: 85da strh r2, [r3, #46] @ 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8005cd4: 687b ldr r3, [r7, #4]
8005cd6: 6bdb ldr r3, [r3, #60] @ 0x3c
8005cd8: 699b ldr r3, [r3, #24]
8005cda: 2b20 cmp r3, #32
8005cdc: f000 8088 beq.w 8005df0 <HAL_UART_IRQHandler+0x3c0>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8005ce0: 687b ldr r3, [r7, #4]
8005ce2: 681b ldr r3, [r3, #0]
8005ce4: 330c adds r3, #12
8005ce6: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005cea: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8005cee: e853 3f00 ldrex r3, [r3]
8005cf2: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8005cf6: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8005cfa: f423 7380 bic.w r3, r3, #256 @ 0x100
8005cfe: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8005d02: 687b ldr r3, [r7, #4]
8005d04: 681b ldr r3, [r3, #0]
8005d06: 330c adds r3, #12
8005d08: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
8005d0c: f8c7 2094 str.w r2, [r7, #148] @ 0x94
8005d10: f8c7 3090 str.w r3, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d14: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8005d18: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8005d1c: e841 2300 strex r3, r2, [r1]
8005d20: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
8005d24: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005d28: 2b00 cmp r3, #0
8005d2a: d1d9 bne.n 8005ce0 <HAL_UART_IRQHandler+0x2b0>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005d2c: 687b ldr r3, [r7, #4]
8005d2e: 681b ldr r3, [r3, #0]
8005d30: 3314 adds r3, #20
8005d32: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d34: 6f7b ldr r3, [r7, #116] @ 0x74
8005d36: e853 3f00 ldrex r3, [r3]
8005d3a: 673b str r3, [r7, #112] @ 0x70
return(result);
8005d3c: 6f3b ldr r3, [r7, #112] @ 0x70
8005d3e: f023 0301 bic.w r3, r3, #1
8005d42: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8005d46: 687b ldr r3, [r7, #4]
8005d48: 681b ldr r3, [r3, #0]
8005d4a: 3314 adds r3, #20
8005d4c: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8005d50: f8c7 2080 str.w r2, [r7, #128] @ 0x80
8005d54: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d56: 6ff9 ldr r1, [r7, #124] @ 0x7c
8005d58: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
8005d5c: e841 2300 strex r3, r2, [r1]
8005d60: 67bb str r3, [r7, #120] @ 0x78
return(result);
8005d62: 6fbb ldr r3, [r7, #120] @ 0x78
8005d64: 2b00 cmp r3, #0
8005d66: d1e1 bne.n 8005d2c <HAL_UART_IRQHandler+0x2fc>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005d68: 687b ldr r3, [r7, #4]
8005d6a: 681b ldr r3, [r3, #0]
8005d6c: 3314 adds r3, #20
8005d6e: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d70: 6e3b ldr r3, [r7, #96] @ 0x60
8005d72: e853 3f00 ldrex r3, [r3]
8005d76: 65fb str r3, [r7, #92] @ 0x5c
return(result);
8005d78: 6dfb ldr r3, [r7, #92] @ 0x5c
8005d7a: f023 0340 bic.w r3, r3, #64 @ 0x40
8005d7e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8005d82: 687b ldr r3, [r7, #4]
8005d84: 681b ldr r3, [r3, #0]
8005d86: 3314 adds r3, #20
8005d88: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
8005d8c: 66fa str r2, [r7, #108] @ 0x6c
8005d8e: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d90: 6eb9 ldr r1, [r7, #104] @ 0x68
8005d92: 6efa ldr r2, [r7, #108] @ 0x6c
8005d94: e841 2300 strex r3, r2, [r1]
8005d98: 667b str r3, [r7, #100] @ 0x64
return(result);
8005d9a: 6e7b ldr r3, [r7, #100] @ 0x64
8005d9c: 2b00 cmp r3, #0
8005d9e: d1e3 bne.n 8005d68 <HAL_UART_IRQHandler+0x338>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005da0: 687b ldr r3, [r7, #4]
8005da2: 2220 movs r2, #32
8005da4: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005da8: 687b ldr r3, [r7, #4]
8005daa: 2200 movs r2, #0
8005dac: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005dae: 687b ldr r3, [r7, #4]
8005db0: 681b ldr r3, [r3, #0]
8005db2: 330c adds r3, #12
8005db4: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005db6: 6cfb ldr r3, [r7, #76] @ 0x4c
8005db8: e853 3f00 ldrex r3, [r3]
8005dbc: 64bb str r3, [r7, #72] @ 0x48
return(result);
8005dbe: 6cbb ldr r3, [r7, #72] @ 0x48
8005dc0: f023 0310 bic.w r3, r3, #16
8005dc4: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8005dc8: 687b ldr r3, [r7, #4]
8005dca: 681b ldr r3, [r3, #0]
8005dcc: 330c adds r3, #12
8005dce: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
8005dd2: 65ba str r2, [r7, #88] @ 0x58
8005dd4: 657b str r3, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005dd6: 6d79 ldr r1, [r7, #84] @ 0x54
8005dd8: 6dba ldr r2, [r7, #88] @ 0x58
8005dda: e841 2300 strex r3, r2, [r1]
8005dde: 653b str r3, [r7, #80] @ 0x50
return(result);
8005de0: 6d3b ldr r3, [r7, #80] @ 0x50
8005de2: 2b00 cmp r3, #0
8005de4: d1e3 bne.n 8005dae <HAL_UART_IRQHandler+0x37e>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8005de6: 687b ldr r3, [r7, #4]
8005de8: 6bdb ldr r3, [r3, #60] @ 0x3c
8005dea: 4618 mov r0, r3
8005dec: f7fd fbc9 bl 8003582 <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005df0: 687b ldr r3, [r7, #4]
8005df2: 2202 movs r2, #2
8005df4: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8005df6: 687b ldr r3, [r7, #4]
8005df8: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005dfa: 687b ldr r3, [r7, #4]
8005dfc: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005dfe: b29b uxth r3, r3
8005e00: 1ad3 subs r3, r2, r3
8005e02: b29b uxth r3, r3
8005e04: 4619 mov r1, r3
8005e06: 6878 ldr r0, [r7, #4]
8005e08: f000 f8bf bl 8005f8a <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005e0c: e09c b.n 8005f48 <HAL_UART_IRQHandler+0x518>
8005e0e: bf00 nop
8005e10: 08006117 .word 0x08006117
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8005e14: 687b ldr r3, [r7, #4]
8005e16: 8d9a ldrh r2, [r3, #44] @ 0x2c
8005e18: 687b ldr r3, [r7, #4]
8005e1a: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005e1c: b29b uxth r3, r3
8005e1e: 1ad3 subs r3, r2, r3
8005e20: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8005e24: 687b ldr r3, [r7, #4]
8005e26: 8ddb ldrh r3, [r3, #46] @ 0x2e
8005e28: b29b uxth r3, r3
8005e2a: 2b00 cmp r3, #0
8005e2c: f000 808e beq.w 8005f4c <HAL_UART_IRQHandler+0x51c>
&& (nb_rx_data > 0U))
8005e30: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005e34: 2b00 cmp r3, #0
8005e36: f000 8089 beq.w 8005f4c <HAL_UART_IRQHandler+0x51c>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005e3a: 687b ldr r3, [r7, #4]
8005e3c: 681b ldr r3, [r3, #0]
8005e3e: 330c adds r3, #12
8005e40: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005e42: 6bbb ldr r3, [r7, #56] @ 0x38
8005e44: e853 3f00 ldrex r3, [r3]
8005e48: 637b str r3, [r7, #52] @ 0x34
return(result);
8005e4a: 6b7b ldr r3, [r7, #52] @ 0x34
8005e4c: f423 7390 bic.w r3, r3, #288 @ 0x120
8005e50: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8005e54: 687b ldr r3, [r7, #4]
8005e56: 681b ldr r3, [r3, #0]
8005e58: 330c adds r3, #12
8005e5a: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
8005e5e: 647a str r2, [r7, #68] @ 0x44
8005e60: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e62: 6c39 ldr r1, [r7, #64] @ 0x40
8005e64: 6c7a ldr r2, [r7, #68] @ 0x44
8005e66: e841 2300 strex r3, r2, [r1]
8005e6a: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8005e6c: 6bfb ldr r3, [r7, #60] @ 0x3c
8005e6e: 2b00 cmp r3, #0
8005e70: d1e3 bne.n 8005e3a <HAL_UART_IRQHandler+0x40a>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005e72: 687b ldr r3, [r7, #4]
8005e74: 681b ldr r3, [r3, #0]
8005e76: 3314 adds r3, #20
8005e78: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005e7a: 6a7b ldr r3, [r7, #36] @ 0x24
8005e7c: e853 3f00 ldrex r3, [r3]
8005e80: 623b str r3, [r7, #32]
return(result);
8005e82: 6a3b ldr r3, [r7, #32]
8005e84: f023 0301 bic.w r3, r3, #1
8005e88: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8005e8c: 687b ldr r3, [r7, #4]
8005e8e: 681b ldr r3, [r3, #0]
8005e90: 3314 adds r3, #20
8005e92: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8005e96: 633a str r2, [r7, #48] @ 0x30
8005e98: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005e9a: 6af9 ldr r1, [r7, #44] @ 0x2c
8005e9c: 6b3a ldr r2, [r7, #48] @ 0x30
8005e9e: e841 2300 strex r3, r2, [r1]
8005ea2: 62bb str r3, [r7, #40] @ 0x28
return(result);
8005ea4: 6abb ldr r3, [r7, #40] @ 0x28
8005ea6: 2b00 cmp r3, #0
8005ea8: d1e3 bne.n 8005e72 <HAL_UART_IRQHandler+0x442>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005eaa: 687b ldr r3, [r7, #4]
8005eac: 2220 movs r2, #32
8005eae: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005eb2: 687b ldr r3, [r7, #4]
8005eb4: 2200 movs r2, #0
8005eb6: 631a str r2, [r3, #48] @ 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005eb8: 687b ldr r3, [r7, #4]
8005eba: 681b ldr r3, [r3, #0]
8005ebc: 330c adds r3, #12
8005ebe: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005ec0: 693b ldr r3, [r7, #16]
8005ec2: e853 3f00 ldrex r3, [r3]
8005ec6: 60fb str r3, [r7, #12]
return(result);
8005ec8: 68fb ldr r3, [r7, #12]
8005eca: f023 0310 bic.w r3, r3, #16
8005ece: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8005ed2: 687b ldr r3, [r7, #4]
8005ed4: 681b ldr r3, [r3, #0]
8005ed6: 330c adds r3, #12
8005ed8: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
8005edc: 61fa str r2, [r7, #28]
8005ede: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005ee0: 69b9 ldr r1, [r7, #24]
8005ee2: 69fa ldr r2, [r7, #28]
8005ee4: e841 2300 strex r3, r2, [r1]
8005ee8: 617b str r3, [r7, #20]
return(result);
8005eea: 697b ldr r3, [r7, #20]
8005eec: 2b00 cmp r3, #0
8005eee: d1e3 bne.n 8005eb8 <HAL_UART_IRQHandler+0x488>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8005ef0: 687b ldr r3, [r7, #4]
8005ef2: 2202 movs r2, #2
8005ef4: 635a str r2, [r3, #52] @ 0x34
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8005ef6: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8005efa: 4619 mov r1, r3
8005efc: 6878 ldr r0, [r7, #4]
8005efe: f000 f844 bl 8005f8a <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
8005f02: e023 b.n 8005f4c <HAL_UART_IRQHandler+0x51c>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
8005f04: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005f08: f003 0380 and.w r3, r3, #128 @ 0x80
8005f0c: 2b00 cmp r3, #0
8005f0e: d009 beq.n 8005f24 <HAL_UART_IRQHandler+0x4f4>
8005f10: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005f14: f003 0380 and.w r3, r3, #128 @ 0x80
8005f18: 2b00 cmp r3, #0
8005f1a: d003 beq.n 8005f24 <HAL_UART_IRQHandler+0x4f4>
{
UART_Transmit_IT(huart);
8005f1c: 6878 ldr r0, [r7, #4]
8005f1e: f000 f90e bl 800613e <UART_Transmit_IT>
return;
8005f22: e014 b.n 8005f4e <HAL_UART_IRQHandler+0x51e>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
8005f24: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8005f28: f003 0340 and.w r3, r3, #64 @ 0x40
8005f2c: 2b00 cmp r3, #0
8005f2e: d00e beq.n 8005f4e <HAL_UART_IRQHandler+0x51e>
8005f30: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8005f34: f003 0340 and.w r3, r3, #64 @ 0x40
8005f38: 2b00 cmp r3, #0
8005f3a: d008 beq.n 8005f4e <HAL_UART_IRQHandler+0x51e>
{
UART_EndTransmit_IT(huart);
8005f3c: 6878 ldr r0, [r7, #4]
8005f3e: f000 f94d bl 80061dc <UART_EndTransmit_IT>
return;
8005f42: e004 b.n 8005f4e <HAL_UART_IRQHandler+0x51e>
return;
8005f44: bf00 nop
8005f46: e002 b.n 8005f4e <HAL_UART_IRQHandler+0x51e>
return;
8005f48: bf00 nop
8005f4a: e000 b.n 8005f4e <HAL_UART_IRQHandler+0x51e>
return;
8005f4c: bf00 nop
}
}
8005f4e: 37e8 adds r7, #232 @ 0xe8
8005f50: 46bd mov sp, r7
8005f52: bd80 pop {r7, pc}
08005f54 <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8005f54: b480 push {r7}
8005f56: b083 sub sp, #12
8005f58: af00 add r7, sp, #0
8005f5a: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
8005f5c: bf00 nop
8005f5e: 370c adds r7, #12
8005f60: 46bd mov sp, r7
8005f62: bc80 pop {r7}
8005f64: 4770 bx lr
08005f66 <HAL_UART_RxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8005f66: b480 push {r7}
8005f68: b083 sub sp, #12
8005f6a: af00 add r7, sp, #0
8005f6c: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
8005f6e: bf00 nop
8005f70: 370c adds r7, #12
8005f72: 46bd mov sp, r7
8005f74: bc80 pop {r7}
8005f76: 4770 bx lr
08005f78 <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8005f78: b480 push {r7}
8005f7a: b083 sub sp, #12
8005f7c: af00 add r7, sp, #0
8005f7e: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8005f80: bf00 nop
8005f82: 370c adds r7, #12
8005f84: 46bd mov sp, r7
8005f86: bc80 pop {r7}
8005f88: 4770 bx lr
08005f8a <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8005f8a: b480 push {r7}
8005f8c: b083 sub sp, #12
8005f8e: af00 add r7, sp, #0
8005f90: 6078 str r0, [r7, #4]
8005f92: 460b mov r3, r1
8005f94: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8005f96: bf00 nop
8005f98: 370c adds r7, #12
8005f9a: 46bd mov sp, r7
8005f9c: bc80 pop {r7}
8005f9e: 4770 bx lr
08005fa0 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8005fa0: b580 push {r7, lr}
8005fa2: b086 sub sp, #24
8005fa4: af00 add r7, sp, #0
8005fa6: 60f8 str r0, [r7, #12]
8005fa8: 60b9 str r1, [r7, #8]
8005faa: 603b str r3, [r7, #0]
8005fac: 4613 mov r3, r2
8005fae: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005fb0: e03b b.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005fb2: 6a3b ldr r3, [r7, #32]
8005fb4: f1b3 3fff cmp.w r3, #4294967295
8005fb8: d037 beq.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8005fba: f7fc ff95 bl 8002ee8 <HAL_GetTick>
8005fbe: 4602 mov r2, r0
8005fc0: 683b ldr r3, [r7, #0]
8005fc2: 1ad3 subs r3, r2, r3
8005fc4: 6a3a ldr r2, [r7, #32]
8005fc6: 429a cmp r2, r3
8005fc8: d302 bcc.n 8005fd0 <UART_WaitOnFlagUntilTimeout+0x30>
8005fca: 6a3b ldr r3, [r7, #32]
8005fcc: 2b00 cmp r3, #0
8005fce: d101 bne.n 8005fd4 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8005fd0: 2303 movs r3, #3
8005fd2: e03a b.n 800604a <UART_WaitOnFlagUntilTimeout+0xaa>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8005fd4: 68fb ldr r3, [r7, #12]
8005fd6: 681b ldr r3, [r3, #0]
8005fd8: 68db ldr r3, [r3, #12]
8005fda: f003 0304 and.w r3, r3, #4
8005fde: 2b00 cmp r3, #0
8005fe0: d023 beq.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
8005fe2: 68bb ldr r3, [r7, #8]
8005fe4: 2b80 cmp r3, #128 @ 0x80
8005fe6: d020 beq.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
8005fe8: 68bb ldr r3, [r7, #8]
8005fea: 2b40 cmp r3, #64 @ 0x40
8005fec: d01d beq.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8005fee: 68fb ldr r3, [r7, #12]
8005ff0: 681b ldr r3, [r3, #0]
8005ff2: 681b ldr r3, [r3, #0]
8005ff4: f003 0308 and.w r3, r3, #8
8005ff8: 2b08 cmp r3, #8
8005ffa: d116 bne.n 800602a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_OREFLAG(huart);
8005ffc: 2300 movs r3, #0
8005ffe: 617b str r3, [r7, #20]
8006000: 68fb ldr r3, [r7, #12]
8006002: 681b ldr r3, [r3, #0]
8006004: 681b ldr r3, [r3, #0]
8006006: 617b str r3, [r7, #20]
8006008: 68fb ldr r3, [r7, #12]
800600a: 681b ldr r3, [r3, #0]
800600c: 685b ldr r3, [r3, #4]
800600e: 617b str r3, [r7, #20]
8006010: 697b ldr r3, [r7, #20]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8006012: 68f8 ldr r0, [r7, #12]
8006014: f000 f81d bl 8006052 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8006018: 68fb ldr r3, [r7, #12]
800601a: 2208 movs r2, #8
800601c: 645a str r2, [r3, #68] @ 0x44
/* Process Unlocked */
__HAL_UNLOCK(huart);
800601e: 68fb ldr r3, [r7, #12]
8006020: 2200 movs r2, #0
8006022: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8006026: 2301 movs r3, #1
8006028: e00f b.n 800604a <UART_WaitOnFlagUntilTimeout+0xaa>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800602a: 68fb ldr r3, [r7, #12]
800602c: 681b ldr r3, [r3, #0]
800602e: 681a ldr r2, [r3, #0]
8006030: 68bb ldr r3, [r7, #8]
8006032: 4013 ands r3, r2
8006034: 68ba ldr r2, [r7, #8]
8006036: 429a cmp r2, r3
8006038: bf0c ite eq
800603a: 2301 moveq r3, #1
800603c: 2300 movne r3, #0
800603e: b2db uxtb r3, r3
8006040: 461a mov r2, r3
8006042: 79fb ldrb r3, [r7, #7]
8006044: 429a cmp r2, r3
8006046: d0b4 beq.n 8005fb2 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8006048: 2300 movs r3, #0
}
800604a: 4618 mov r0, r3
800604c: 3718 adds r7, #24
800604e: 46bd mov sp, r7
8006050: bd80 pop {r7, pc}
08006052 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8006052: b480 push {r7}
8006054: b095 sub sp, #84 @ 0x54
8006056: af00 add r7, sp, #0
8006058: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800605a: 687b ldr r3, [r7, #4]
800605c: 681b ldr r3, [r3, #0]
800605e: 330c adds r3, #12
8006060: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006062: 6b7b ldr r3, [r7, #52] @ 0x34
8006064: e853 3f00 ldrex r3, [r3]
8006068: 633b str r3, [r7, #48] @ 0x30
return(result);
800606a: 6b3b ldr r3, [r7, #48] @ 0x30
800606c: f423 7390 bic.w r3, r3, #288 @ 0x120
8006070: 64fb str r3, [r7, #76] @ 0x4c
8006072: 687b ldr r3, [r7, #4]
8006074: 681b ldr r3, [r3, #0]
8006076: 330c adds r3, #12
8006078: 6cfa ldr r2, [r7, #76] @ 0x4c
800607a: 643a str r2, [r7, #64] @ 0x40
800607c: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800607e: 6bf9 ldr r1, [r7, #60] @ 0x3c
8006080: 6c3a ldr r2, [r7, #64] @ 0x40
8006082: e841 2300 strex r3, r2, [r1]
8006086: 63bb str r3, [r7, #56] @ 0x38
return(result);
8006088: 6bbb ldr r3, [r7, #56] @ 0x38
800608a: 2b00 cmp r3, #0
800608c: d1e5 bne.n 800605a <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800608e: 687b ldr r3, [r7, #4]
8006090: 681b ldr r3, [r3, #0]
8006092: 3314 adds r3, #20
8006094: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006096: 6a3b ldr r3, [r7, #32]
8006098: e853 3f00 ldrex r3, [r3]
800609c: 61fb str r3, [r7, #28]
return(result);
800609e: 69fb ldr r3, [r7, #28]
80060a0: f023 0301 bic.w r3, r3, #1
80060a4: 64bb str r3, [r7, #72] @ 0x48
80060a6: 687b ldr r3, [r7, #4]
80060a8: 681b ldr r3, [r3, #0]
80060aa: 3314 adds r3, #20
80060ac: 6cba ldr r2, [r7, #72] @ 0x48
80060ae: 62fa str r2, [r7, #44] @ 0x2c
80060b0: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80060b2: 6ab9 ldr r1, [r7, #40] @ 0x28
80060b4: 6afa ldr r2, [r7, #44] @ 0x2c
80060b6: e841 2300 strex r3, r2, [r1]
80060ba: 627b str r3, [r7, #36] @ 0x24
return(result);
80060bc: 6a7b ldr r3, [r7, #36] @ 0x24
80060be: 2b00 cmp r3, #0
80060c0: d1e5 bne.n 800608e <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80060c2: 687b ldr r3, [r7, #4]
80060c4: 6b1b ldr r3, [r3, #48] @ 0x30
80060c6: 2b01 cmp r3, #1
80060c8: d119 bne.n 80060fe <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80060ca: 687b ldr r3, [r7, #4]
80060cc: 681b ldr r3, [r3, #0]
80060ce: 330c adds r3, #12
80060d0: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80060d2: 68fb ldr r3, [r7, #12]
80060d4: e853 3f00 ldrex r3, [r3]
80060d8: 60bb str r3, [r7, #8]
return(result);
80060da: 68bb ldr r3, [r7, #8]
80060dc: f023 0310 bic.w r3, r3, #16
80060e0: 647b str r3, [r7, #68] @ 0x44
80060e2: 687b ldr r3, [r7, #4]
80060e4: 681b ldr r3, [r3, #0]
80060e6: 330c adds r3, #12
80060e8: 6c7a ldr r2, [r7, #68] @ 0x44
80060ea: 61ba str r2, [r7, #24]
80060ec: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80060ee: 6979 ldr r1, [r7, #20]
80060f0: 69ba ldr r2, [r7, #24]
80060f2: e841 2300 strex r3, r2, [r1]
80060f6: 613b str r3, [r7, #16]
return(result);
80060f8: 693b ldr r3, [r7, #16]
80060fa: 2b00 cmp r3, #0
80060fc: d1e5 bne.n 80060ca <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80060fe: 687b ldr r3, [r7, #4]
8006100: 2220 movs r2, #32
8006102: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006106: 687b ldr r3, [r7, #4]
8006108: 2200 movs r2, #0
800610a: 631a str r2, [r3, #48] @ 0x30
}
800610c: bf00 nop
800610e: 3754 adds r7, #84 @ 0x54
8006110: 46bd mov sp, r7
8006112: bc80 pop {r7}
8006114: 4770 bx lr
08006116 <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8006116: b580 push {r7, lr}
8006118: b084 sub sp, #16
800611a: af00 add r7, sp, #0
800611c: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800611e: 687b ldr r3, [r7, #4]
8006120: 6a5b ldr r3, [r3, #36] @ 0x24
8006122: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8006124: 68fb ldr r3, [r7, #12]
8006126: 2200 movs r2, #0
8006128: 85da strh r2, [r3, #46] @ 0x2e
huart->TxXferCount = 0x00U;
800612a: 68fb ldr r3, [r7, #12]
800612c: 2200 movs r2, #0
800612e: 84da strh r2, [r3, #38] @ 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006130: 68f8 ldr r0, [r7, #12]
8006132: f7ff ff21 bl 8005f78 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006136: bf00 nop
8006138: 3710 adds r7, #16
800613a: 46bd mov sp, r7
800613c: bd80 pop {r7, pc}
0800613e <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
800613e: b480 push {r7}
8006140: b085 sub sp, #20
8006142: af00 add r7, sp, #0
8006144: 6078 str r0, [r7, #4]
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8006146: 687b ldr r3, [r7, #4]
8006148: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800614c: b2db uxtb r3, r3
800614e: 2b21 cmp r3, #33 @ 0x21
8006150: d13e bne.n 80061d0 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8006152: 687b ldr r3, [r7, #4]
8006154: 689b ldr r3, [r3, #8]
8006156: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800615a: d114 bne.n 8006186 <UART_Transmit_IT+0x48>
800615c: 687b ldr r3, [r7, #4]
800615e: 691b ldr r3, [r3, #16]
8006160: 2b00 cmp r3, #0
8006162: d110 bne.n 8006186 <UART_Transmit_IT+0x48>
{
tmp = (const uint16_t *) huart->pTxBuffPtr;
8006164: 687b ldr r3, [r7, #4]
8006166: 6a1b ldr r3, [r3, #32]
8006168: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
800616a: 68fb ldr r3, [r7, #12]
800616c: 881b ldrh r3, [r3, #0]
800616e: 461a mov r2, r3
8006170: 687b ldr r3, [r7, #4]
8006172: 681b ldr r3, [r3, #0]
8006174: f3c2 0208 ubfx r2, r2, #0, #9
8006178: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
800617a: 687b ldr r3, [r7, #4]
800617c: 6a1b ldr r3, [r3, #32]
800617e: 1c9a adds r2, r3, #2
8006180: 687b ldr r3, [r7, #4]
8006182: 621a str r2, [r3, #32]
8006184: e008 b.n 8006198 <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
8006186: 687b ldr r3, [r7, #4]
8006188: 6a1b ldr r3, [r3, #32]
800618a: 1c59 adds r1, r3, #1
800618c: 687a ldr r2, [r7, #4]
800618e: 6211 str r1, [r2, #32]
8006190: 781a ldrb r2, [r3, #0]
8006192: 687b ldr r3, [r7, #4]
8006194: 681b ldr r3, [r3, #0]
8006196: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
8006198: 687b ldr r3, [r7, #4]
800619a: 8cdb ldrh r3, [r3, #38] @ 0x26
800619c: b29b uxth r3, r3
800619e: 3b01 subs r3, #1
80061a0: b29b uxth r3, r3
80061a2: 687a ldr r2, [r7, #4]
80061a4: 4619 mov r1, r3
80061a6: 84d1 strh r1, [r2, #38] @ 0x26
80061a8: 2b00 cmp r3, #0
80061aa: d10f bne.n 80061cc <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
80061ac: 687b ldr r3, [r7, #4]
80061ae: 681b ldr r3, [r3, #0]
80061b0: 68da ldr r2, [r3, #12]
80061b2: 687b ldr r3, [r7, #4]
80061b4: 681b ldr r3, [r3, #0]
80061b6: f022 0280 bic.w r2, r2, #128 @ 0x80
80061ba: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
80061bc: 687b ldr r3, [r7, #4]
80061be: 681b ldr r3, [r3, #0]
80061c0: 68da ldr r2, [r3, #12]
80061c2: 687b ldr r3, [r7, #4]
80061c4: 681b ldr r3, [r3, #0]
80061c6: f042 0240 orr.w r2, r2, #64 @ 0x40
80061ca: 60da str r2, [r3, #12]
}
return HAL_OK;
80061cc: 2300 movs r3, #0
80061ce: e000 b.n 80061d2 <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
80061d0: 2302 movs r3, #2
}
}
80061d2: 4618 mov r0, r3
80061d4: 3714 adds r7, #20
80061d6: 46bd mov sp, r7
80061d8: bc80 pop {r7}
80061da: 4770 bx lr
080061dc <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
80061dc: b580 push {r7, lr}
80061de: b082 sub sp, #8
80061e0: af00 add r7, sp, #0
80061e2: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
80061e4: 687b ldr r3, [r7, #4]
80061e6: 681b ldr r3, [r3, #0]
80061e8: 68da ldr r2, [r3, #12]
80061ea: 687b ldr r3, [r7, #4]
80061ec: 681b ldr r3, [r3, #0]
80061ee: f022 0240 bic.w r2, r2, #64 @ 0x40
80061f2: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80061f4: 687b ldr r3, [r7, #4]
80061f6: 2220 movs r2, #32
80061f8: f883 2041 strb.w r2, [r3, #65] @ 0x41
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
80061fc: 6878 ldr r0, [r7, #4]
80061fe: f7ff fea9 bl 8005f54 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8006202: 2300 movs r3, #0
}
8006204: 4618 mov r0, r3
8006206: 3708 adds r7, #8
8006208: 46bd mov sp, r7
800620a: bd80 pop {r7, pc}
0800620c <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
800620c: b580 push {r7, lr}
800620e: b08c sub sp, #48 @ 0x30
8006210: af00 add r7, sp, #0
8006212: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006214: 687b ldr r3, [r7, #4]
8006216: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800621a: b2db uxtb r3, r3
800621c: 2b22 cmp r3, #34 @ 0x22
800621e: f040 80ae bne.w 800637e <UART_Receive_IT+0x172>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8006222: 687b ldr r3, [r7, #4]
8006224: 689b ldr r3, [r3, #8]
8006226: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800622a: d117 bne.n 800625c <UART_Receive_IT+0x50>
800622c: 687b ldr r3, [r7, #4]
800622e: 691b ldr r3, [r3, #16]
8006230: 2b00 cmp r3, #0
8006232: d113 bne.n 800625c <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
8006234: 2300 movs r3, #0
8006236: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
8006238: 687b ldr r3, [r7, #4]
800623a: 6a9b ldr r3, [r3, #40] @ 0x28
800623c: 62bb str r3, [r7, #40] @ 0x28
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
800623e: 687b ldr r3, [r7, #4]
8006240: 681b ldr r3, [r3, #0]
8006242: 685b ldr r3, [r3, #4]
8006244: b29b uxth r3, r3
8006246: f3c3 0308 ubfx r3, r3, #0, #9
800624a: b29a uxth r2, r3
800624c: 6abb ldr r3, [r7, #40] @ 0x28
800624e: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8006250: 687b ldr r3, [r7, #4]
8006252: 6a9b ldr r3, [r3, #40] @ 0x28
8006254: 1c9a adds r2, r3, #2
8006256: 687b ldr r3, [r7, #4]
8006258: 629a str r2, [r3, #40] @ 0x28
800625a: e026 b.n 80062aa <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
800625c: 687b ldr r3, [r7, #4]
800625e: 6a9b ldr r3, [r3, #40] @ 0x28
8006260: 62fb str r3, [r7, #44] @ 0x2c
pdata16bits = NULL;
8006262: 2300 movs r3, #0
8006264: 62bb str r3, [r7, #40] @ 0x28
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8006266: 687b ldr r3, [r7, #4]
8006268: 689b ldr r3, [r3, #8]
800626a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800626e: d007 beq.n 8006280 <UART_Receive_IT+0x74>
8006270: 687b ldr r3, [r7, #4]
8006272: 689b ldr r3, [r3, #8]
8006274: 2b00 cmp r3, #0
8006276: d10a bne.n 800628e <UART_Receive_IT+0x82>
8006278: 687b ldr r3, [r7, #4]
800627a: 691b ldr r3, [r3, #16]
800627c: 2b00 cmp r3, #0
800627e: d106 bne.n 800628e <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8006280: 687b ldr r3, [r7, #4]
8006282: 681b ldr r3, [r3, #0]
8006284: 685b ldr r3, [r3, #4]
8006286: b2da uxtb r2, r3
8006288: 6afb ldr r3, [r7, #44] @ 0x2c
800628a: 701a strb r2, [r3, #0]
800628c: e008 b.n 80062a0 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
800628e: 687b ldr r3, [r7, #4]
8006290: 681b ldr r3, [r3, #0]
8006292: 685b ldr r3, [r3, #4]
8006294: b2db uxtb r3, r3
8006296: f003 037f and.w r3, r3, #127 @ 0x7f
800629a: b2da uxtb r2, r3
800629c: 6afb ldr r3, [r7, #44] @ 0x2c
800629e: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
80062a0: 687b ldr r3, [r7, #4]
80062a2: 6a9b ldr r3, [r3, #40] @ 0x28
80062a4: 1c5a adds r2, r3, #1
80062a6: 687b ldr r3, [r7, #4]
80062a8: 629a str r2, [r3, #40] @ 0x28
}
if (--huart->RxXferCount == 0U)
80062aa: 687b ldr r3, [r7, #4]
80062ac: 8ddb ldrh r3, [r3, #46] @ 0x2e
80062ae: b29b uxth r3, r3
80062b0: 3b01 subs r3, #1
80062b2: b29b uxth r3, r3
80062b4: 687a ldr r2, [r7, #4]
80062b6: 4619 mov r1, r3
80062b8: 85d1 strh r1, [r2, #46] @ 0x2e
80062ba: 2b00 cmp r3, #0
80062bc: d15d bne.n 800637a <UART_Receive_IT+0x16e>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
80062be: 687b ldr r3, [r7, #4]
80062c0: 681b ldr r3, [r3, #0]
80062c2: 68da ldr r2, [r3, #12]
80062c4: 687b ldr r3, [r7, #4]
80062c6: 681b ldr r3, [r3, #0]
80062c8: f022 0220 bic.w r2, r2, #32
80062cc: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
80062ce: 687b ldr r3, [r7, #4]
80062d0: 681b ldr r3, [r3, #0]
80062d2: 68da ldr r2, [r3, #12]
80062d4: 687b ldr r3, [r7, #4]
80062d6: 681b ldr r3, [r3, #0]
80062d8: f422 7280 bic.w r2, r2, #256 @ 0x100
80062dc: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
80062de: 687b ldr r3, [r7, #4]
80062e0: 681b ldr r3, [r3, #0]
80062e2: 695a ldr r2, [r3, #20]
80062e4: 687b ldr r3, [r7, #4]
80062e6: 681b ldr r3, [r3, #0]
80062e8: f022 0201 bic.w r2, r2, #1
80062ec: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80062ee: 687b ldr r3, [r7, #4]
80062f0: 2220 movs r2, #32
80062f2: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
80062f6: 687b ldr r3, [r7, #4]
80062f8: 2200 movs r2, #0
80062fa: 635a str r2, [r3, #52] @ 0x34
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80062fc: 687b ldr r3, [r7, #4]
80062fe: 6b1b ldr r3, [r3, #48] @ 0x30
8006300: 2b01 cmp r3, #1
8006302: d135 bne.n 8006370 <UART_Receive_IT+0x164>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006304: 687b ldr r3, [r7, #4]
8006306: 2200 movs r2, #0
8006308: 631a str r2, [r3, #48] @ 0x30
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800630a: 687b ldr r3, [r7, #4]
800630c: 681b ldr r3, [r3, #0]
800630e: 330c adds r3, #12
8006310: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006312: 697b ldr r3, [r7, #20]
8006314: e853 3f00 ldrex r3, [r3]
8006318: 613b str r3, [r7, #16]
return(result);
800631a: 693b ldr r3, [r7, #16]
800631c: f023 0310 bic.w r3, r3, #16
8006320: 627b str r3, [r7, #36] @ 0x24
8006322: 687b ldr r3, [r7, #4]
8006324: 681b ldr r3, [r3, #0]
8006326: 330c adds r3, #12
8006328: 6a7a ldr r2, [r7, #36] @ 0x24
800632a: 623a str r2, [r7, #32]
800632c: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800632e: 69f9 ldr r1, [r7, #28]
8006330: 6a3a ldr r2, [r7, #32]
8006332: e841 2300 strex r3, r2, [r1]
8006336: 61bb str r3, [r7, #24]
return(result);
8006338: 69bb ldr r3, [r7, #24]
800633a: 2b00 cmp r3, #0
800633c: d1e5 bne.n 800630a <UART_Receive_IT+0xfe>
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
800633e: 687b ldr r3, [r7, #4]
8006340: 681b ldr r3, [r3, #0]
8006342: 681b ldr r3, [r3, #0]
8006344: f003 0310 and.w r3, r3, #16
8006348: 2b10 cmp r3, #16
800634a: d10a bne.n 8006362 <UART_Receive_IT+0x156>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
800634c: 2300 movs r3, #0
800634e: 60fb str r3, [r7, #12]
8006350: 687b ldr r3, [r7, #4]
8006352: 681b ldr r3, [r3, #0]
8006354: 681b ldr r3, [r3, #0]
8006356: 60fb str r3, [r7, #12]
8006358: 687b ldr r3, [r7, #4]
800635a: 681b ldr r3, [r3, #0]
800635c: 685b ldr r3, [r3, #4]
800635e: 60fb str r3, [r7, #12]
8006360: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006362: 687b ldr r3, [r7, #4]
8006364: 8d9b ldrh r3, [r3, #44] @ 0x2c
8006366: 4619 mov r1, r3
8006368: 6878 ldr r0, [r7, #4]
800636a: f7ff fe0e bl 8005f8a <HAL_UARTEx_RxEventCallback>
800636e: e002 b.n 8006376 <UART_Receive_IT+0x16a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8006370: 6878 ldr r0, [r7, #4]
8006372: f7ff fdf8 bl 8005f66 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
8006376: 2300 movs r3, #0
8006378: e002 b.n 8006380 <UART_Receive_IT+0x174>
}
return HAL_OK;
800637a: 2300 movs r3, #0
800637c: e000 b.n 8006380 <UART_Receive_IT+0x174>
}
else
{
return HAL_BUSY;
800637e: 2302 movs r3, #2
}
}
8006380: 4618 mov r0, r3
8006382: 3730 adds r7, #48 @ 0x30
8006384: 46bd mov sp, r7
8006386: bd80 pop {r7, pc}
08006388 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8006388: b580 push {r7, lr}
800638a: b084 sub sp, #16
800638c: af00 add r7, sp, #0
800638e: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8006390: 687b ldr r3, [r7, #4]
8006392: 681b ldr r3, [r3, #0]
8006394: 691b ldr r3, [r3, #16]
8006396: f423 5140 bic.w r1, r3, #12288 @ 0x3000
800639a: 687b ldr r3, [r7, #4]
800639c: 68da ldr r2, [r3, #12]
800639e: 687b ldr r3, [r7, #4]
80063a0: 681b ldr r3, [r3, #0]
80063a2: 430a orrs r2, r1
80063a4: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
80063a6: 687b ldr r3, [r7, #4]
80063a8: 689a ldr r2, [r3, #8]
80063aa: 687b ldr r3, [r7, #4]
80063ac: 691b ldr r3, [r3, #16]
80063ae: 431a orrs r2, r3
80063b0: 687b ldr r3, [r7, #4]
80063b2: 695b ldr r3, [r3, #20]
80063b4: 4313 orrs r3, r2
80063b6: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
80063b8: 687b ldr r3, [r7, #4]
80063ba: 681b ldr r3, [r3, #0]
80063bc: 68db ldr r3, [r3, #12]
80063be: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
80063c2: f023 030c bic.w r3, r3, #12
80063c6: 687a ldr r2, [r7, #4]
80063c8: 6812 ldr r2, [r2, #0]
80063ca: 68b9 ldr r1, [r7, #8]
80063cc: 430b orrs r3, r1
80063ce: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
80063d0: 687b ldr r3, [r7, #4]
80063d2: 681b ldr r3, [r3, #0]
80063d4: 695b ldr r3, [r3, #20]
80063d6: f423 7140 bic.w r1, r3, #768 @ 0x300
80063da: 687b ldr r3, [r7, #4]
80063dc: 699a ldr r2, [r3, #24]
80063de: 687b ldr r3, [r7, #4]
80063e0: 681b ldr r3, [r3, #0]
80063e2: 430a orrs r2, r1
80063e4: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
80063e6: 687b ldr r3, [r7, #4]
80063e8: 681b ldr r3, [r3, #0]
80063ea: 4a2c ldr r2, [pc, #176] @ (800649c <UART_SetConfig+0x114>)
80063ec: 4293 cmp r3, r2
80063ee: d103 bne.n 80063f8 <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
80063f0: f7ff f95a bl 80056a8 <HAL_RCC_GetPCLK2Freq>
80063f4: 60f8 str r0, [r7, #12]
80063f6: e002 b.n 80063fe <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80063f8: f7ff f942 bl 8005680 <HAL_RCC_GetPCLK1Freq>
80063fc: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80063fe: 68fa ldr r2, [r7, #12]
8006400: 4613 mov r3, r2
8006402: 009b lsls r3, r3, #2
8006404: 4413 add r3, r2
8006406: 009a lsls r2, r3, #2
8006408: 441a add r2, r3
800640a: 687b ldr r3, [r7, #4]
800640c: 685b ldr r3, [r3, #4]
800640e: 009b lsls r3, r3, #2
8006410: fbb2 f3f3 udiv r3, r2, r3
8006414: 4a22 ldr r2, [pc, #136] @ (80064a0 <UART_SetConfig+0x118>)
8006416: fba2 2303 umull r2, r3, r2, r3
800641a: 095b lsrs r3, r3, #5
800641c: 0119 lsls r1, r3, #4
800641e: 68fa ldr r2, [r7, #12]
8006420: 4613 mov r3, r2
8006422: 009b lsls r3, r3, #2
8006424: 4413 add r3, r2
8006426: 009a lsls r2, r3, #2
8006428: 441a add r2, r3
800642a: 687b ldr r3, [r7, #4]
800642c: 685b ldr r3, [r3, #4]
800642e: 009b lsls r3, r3, #2
8006430: fbb2 f2f3 udiv r2, r2, r3
8006434: 4b1a ldr r3, [pc, #104] @ (80064a0 <UART_SetConfig+0x118>)
8006436: fba3 0302 umull r0, r3, r3, r2
800643a: 095b lsrs r3, r3, #5
800643c: 2064 movs r0, #100 @ 0x64
800643e: fb00 f303 mul.w r3, r0, r3
8006442: 1ad3 subs r3, r2, r3
8006444: 011b lsls r3, r3, #4
8006446: 3332 adds r3, #50 @ 0x32
8006448: 4a15 ldr r2, [pc, #84] @ (80064a0 <UART_SetConfig+0x118>)
800644a: fba2 2303 umull r2, r3, r2, r3
800644e: 095b lsrs r3, r3, #5
8006450: f003 03f0 and.w r3, r3, #240 @ 0xf0
8006454: 4419 add r1, r3
8006456: 68fa ldr r2, [r7, #12]
8006458: 4613 mov r3, r2
800645a: 009b lsls r3, r3, #2
800645c: 4413 add r3, r2
800645e: 009a lsls r2, r3, #2
8006460: 441a add r2, r3
8006462: 687b ldr r3, [r7, #4]
8006464: 685b ldr r3, [r3, #4]
8006466: 009b lsls r3, r3, #2
8006468: fbb2 f2f3 udiv r2, r2, r3
800646c: 4b0c ldr r3, [pc, #48] @ (80064a0 <UART_SetConfig+0x118>)
800646e: fba3 0302 umull r0, r3, r3, r2
8006472: 095b lsrs r3, r3, #5
8006474: 2064 movs r0, #100 @ 0x64
8006476: fb00 f303 mul.w r3, r0, r3
800647a: 1ad3 subs r3, r2, r3
800647c: 011b lsls r3, r3, #4
800647e: 3332 adds r3, #50 @ 0x32
8006480: 4a07 ldr r2, [pc, #28] @ (80064a0 <UART_SetConfig+0x118>)
8006482: fba2 2303 umull r2, r3, r2, r3
8006486: 095b lsrs r3, r3, #5
8006488: f003 020f and.w r2, r3, #15
800648c: 687b ldr r3, [r7, #4]
800648e: 681b ldr r3, [r3, #0]
8006490: 440a add r2, r1
8006492: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8006494: bf00 nop
8006496: 3710 adds r7, #16
8006498: 46bd mov sp, r7
800649a: bd80 pop {r7, pc}
800649c: 40013800 .word 0x40013800
80064a0: 51eb851f .word 0x51eb851f
080064a4 <memset>:
80064a4: 4603 mov r3, r0
80064a6: 4402 add r2, r0
80064a8: 4293 cmp r3, r2
80064aa: d100 bne.n 80064ae <memset+0xa>
80064ac: 4770 bx lr
80064ae: f803 1b01 strb.w r1, [r3], #1
80064b2: e7f9 b.n 80064a8 <memset+0x4>
080064b4 <__errno>:
80064b4: 4b01 ldr r3, [pc, #4] @ (80064bc <__errno+0x8>)
80064b6: 6818 ldr r0, [r3, #0]
80064b8: 4770 bx lr
80064ba: bf00 nop
80064bc: 20000040 .word 0x20000040
080064c0 <__libc_init_array>:
80064c0: b570 push {r4, r5, r6, lr}
80064c2: 2600 movs r6, #0
80064c4: 4d0c ldr r5, [pc, #48] @ (80064f8 <__libc_init_array+0x38>)
80064c6: 4b0d ldr r3, [pc, #52] @ (80064fc <__libc_init_array+0x3c>)
80064c8: 1b5b subs r3, r3, r5
80064ca: 109c asrs r4, r3, #2
80064cc: 42a6 cmp r6, r4
80064ce: d109 bne.n 80064e4 <__libc_init_array+0x24>
80064d0: 2600 movs r6, #0
80064d2: f000 f8db bl 800668c <_init>
80064d6: 4d0a ldr r5, [pc, #40] @ (8006500 <__libc_init_array+0x40>)
80064d8: 4b0a ldr r3, [pc, #40] @ (8006504 <__libc_init_array+0x44>)
80064da: 1b5b subs r3, r3, r5
80064dc: 109c asrs r4, r3, #2
80064de: 42a6 cmp r6, r4
80064e0: d105 bne.n 80064ee <__libc_init_array+0x2e>
80064e2: bd70 pop {r4, r5, r6, pc}
80064e4: f855 3b04 ldr.w r3, [r5], #4
80064e8: 4798 blx r3
80064ea: 3601 adds r6, #1
80064ec: e7ee b.n 80064cc <__libc_init_array+0xc>
80064ee: f855 3b04 ldr.w r3, [r5], #4
80064f2: 4798 blx r3
80064f4: 3601 adds r6, #1
80064f6: e7f2 b.n 80064de <__libc_init_array+0x1e>
80064f8: 08006820 .word 0x08006820
80064fc: 08006820 .word 0x08006820
8006500: 08006820 .word 0x08006820
8006504: 08006824 .word 0x08006824
08006508 <memcpy>:
8006508: 440a add r2, r1
800650a: 4291 cmp r1, r2
800650c: f100 33ff add.w r3, r0, #4294967295
8006510: d100 bne.n 8006514 <memcpy+0xc>
8006512: 4770 bx lr
8006514: b510 push {r4, lr}
8006516: f811 4b01 ldrb.w r4, [r1], #1
800651a: 4291 cmp r1, r2
800651c: f803 4f01 strb.w r4, [r3, #1]!
8006520: d1f9 bne.n 8006516 <memcpy+0xe>
8006522: bd10 pop {r4, pc}
08006524 <sqrtf>:
8006524: b538 push {r3, r4, r5, lr}
8006526: 4604 mov r4, r0
8006528: f000 f81a bl 8006560 <__ieee754_sqrtf>
800652c: 4621 mov r1, r4
800652e: 4605 mov r5, r0
8006530: 4620 mov r0, r4
8006532: f7fa fc7d bl 8000e30 <__aeabi_fcmpun>
8006536: b920 cbnz r0, 8006542 <sqrtf+0x1e>
8006538: 4620 mov r0, r4
800653a: 2100 movs r1, #0
800653c: f7fa fc50 bl 8000de0 <__aeabi_fcmplt>
8006540: b908 cbnz r0, 8006546 <sqrtf+0x22>
8006542: 4628 mov r0, r5
8006544: bd38 pop {r3, r4, r5, pc}
8006546: f7ff ffb5 bl 80064b4 <__errno>
800654a: 2221 movs r2, #33 @ 0x21
800654c: 4603 mov r3, r0
800654e: 2100 movs r1, #0
8006550: 601a str r2, [r3, #0]
8006552: 4608 mov r0, r1
8006554: f7fa fb5a bl 8000c0c <__aeabi_fdiv>
8006558: 4605 mov r5, r0
800655a: 4628 mov r0, r5
800655c: bd38 pop {r3, r4, r5, pc}
800655e: bf00 nop
08006560 <__ieee754_sqrtf>:
8006560: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000
8006564: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000
8006568: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800656c: 4604 mov r4, r0
800656e: d24f bcs.n 8006610 <__ieee754_sqrtf+0xb0>
8006570: 2a00 cmp r2, #0
8006572: d04b beq.n 800660c <__ieee754_sqrtf+0xac>
8006574: 2800 cmp r0, #0
8006576: 4603 mov r3, r0
8006578: db54 blt.n 8006624 <__ieee754_sqrtf+0xc4>
800657a: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000
800657e: d14f bne.n 8006620 <__ieee754_sqrtf+0xc0>
8006580: 005b lsls r3, r3, #1
8006582: 0218 lsls r0, r3, #8
8006584: 4611 mov r1, r2
8006586: f102 0201 add.w r2, r2, #1
800658a: d5f9 bpl.n 8006580 <__ieee754_sqrtf+0x20>
800658c: 4249 negs r1, r1
800658e: 2400 movs r4, #0
8006590: f3c3 0216 ubfx r2, r3, #0, #23
8006594: f1a1 057f sub.w r5, r1, #127 @ 0x7f
8006598: 07cb lsls r3, r1, #31
800659a: f04f 0e19 mov.w lr, #25
800659e: f04f 7c80 mov.w ip, #16777216 @ 0x1000000
80065a2: 4621 mov r1, r4
80065a4: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
80065a8: bf58 it pl
80065aa: 0052 lslpl r2, r2, #1
80065ac: 106d asrs r5, r5, #1
80065ae: 0052 lsls r2, r2, #1
80065b0: eb01 030c add.w r3, r1, ip
80065b4: 4293 cmp r3, r2
80065b6: bfcf iteee gt
80065b8: 4613 movgt r3, r2
80065ba: eb03 010c addle.w r1, r3, ip
80065be: 4464 addle r4, ip
80065c0: 1ad3 suble r3, r2, r3
80065c2: f1be 0e01 subs.w lr, lr, #1
80065c6: ea4f 0243 mov.w r2, r3, lsl #1
80065ca: ea4f 0c5c mov.w ip, ip, lsr #1
80065ce: d1ef bne.n 80065b0 <__ieee754_sqrtf+0x50>
80065d0: b1bb cbz r3, 8006602 <__ieee754_sqrtf+0xa2>
80065d2: 4e1a ldr r6, [pc, #104] @ (800663c <__ieee754_sqrtf+0xdc>)
80065d4: 4f1a ldr r7, [pc, #104] @ (8006640 <__ieee754_sqrtf+0xe0>)
80065d6: 6830 ldr r0, [r6, #0]
80065d8: 6839 ldr r1, [r7, #0]
80065da: f7fa f959 bl 8000890 <__aeabi_fsub>
80065de: f8d6 8000 ldr.w r8, [r6]
80065e2: 4601 mov r1, r0
80065e4: 4640 mov r0, r8
80065e6: f7fa fc05 bl 8000df4 <__aeabi_fcmple>
80065ea: b150 cbz r0, 8006602 <__ieee754_sqrtf+0xa2>
80065ec: 6830 ldr r0, [r6, #0]
80065ee: 6839 ldr r1, [r7, #0]
80065f0: f7fa f950 bl 8000894 <__addsf3>
80065f4: 6836 ldr r6, [r6, #0]
80065f6: 4601 mov r1, r0
80065f8: 4630 mov r0, r6
80065fa: f7fa fbf1 bl 8000de0 <__aeabi_fcmplt>
80065fe: b1c8 cbz r0, 8006634 <__ieee754_sqrtf+0xd4>
8006600: 3402 adds r4, #2
8006602: 1060 asrs r0, r4, #1
8006604: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000
8006608: eb00 50c5 add.w r0, r0, r5, lsl #23
800660c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006610: 4601 mov r1, r0
8006612: f7fa fa47 bl 8000aa4 <__aeabi_fmul>
8006616: 4621 mov r1, r4
8006618: f7fa f93c bl 8000894 <__addsf3>
800661c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006620: 15c1 asrs r1, r0, #23
8006622: e7b4 b.n 800658e <__ieee754_sqrtf+0x2e>
8006624: 4601 mov r1, r0
8006626: f7fa f933 bl 8000890 <__aeabi_fsub>
800662a: 4601 mov r1, r0
800662c: f7fa faee bl 8000c0c <__aeabi_fdiv>
8006630: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8006634: 3401 adds r4, #1
8006636: f024 0401 bic.w r4, r4, #1
800663a: e7e2 b.n 8006602 <__ieee754_sqrtf+0xa2>
800663c: 08006814 .word 0x08006814
8006640: 08006810 .word 0x08006810
08006644 <roundf>:
8006644: b508 push {r3, lr}
8006646: f3c0 53c7 ubfx r3, r0, #23, #8
800664a: 3b7f subs r3, #127 @ 0x7f
800664c: 2b16 cmp r3, #22
800664e: 4601 mov r1, r0
8006650: dc0e bgt.n 8006670 <roundf+0x2c>
8006652: 2b00 cmp r3, #0
8006654: 4602 mov r2, r0
8006656: db10 blt.n 800667a <roundf+0x36>
8006658: 480b ldr r0, [pc, #44] @ (8006688 <roundf+0x44>)
800665a: 4118 asrs r0, r3
800665c: 4201 tst r1, r0
800665e: d005 beq.n 800666c <roundf+0x28>
8006660: f44f 0180 mov.w r1, #4194304 @ 0x400000
8006664: 4119 asrs r1, r3
8006666: 4411 add r1, r2
8006668: ea21 0100 bic.w r1, r1, r0
800666c: 4608 mov r0, r1
800666e: bd08 pop {r3, pc}
8006670: 2b80 cmp r3, #128 @ 0x80
8006672: d1fb bne.n 800666c <roundf+0x28>
8006674: f7fa f90e bl 8000894 <__addsf3>
8006678: bd08 pop {r3, pc}
800667a: 3301 adds r3, #1
800667c: f000 4100 and.w r1, r0, #2147483648 @ 0x80000000
8006680: d1f4 bne.n 800666c <roundf+0x28>
8006682: f041 517e orr.w r1, r1, #1065353216 @ 0x3f800000
8006686: e7f1 b.n 800666c <roundf+0x28>
8006688: 007fffff .word 0x007fffff
0800668c <_init>:
800668c: b5f8 push {r3, r4, r5, r6, r7, lr}
800668e: bf00 nop
8006690: bcf8 pop {r3, r4, r5, r6, r7}
8006692: bc08 pop {r3}
8006694: 469e mov lr, r3
8006696: 4770 bx lr
08006698 <_fini>:
8006698: b5f8 push {r3, r4, r5, r6, r7, lr}
800669a: bf00 nop
800669c: bcf8 pop {r3, r4, r5, r6, r7}
800669e: bc08 pop {r3}
80066a0: 469e mov lr, r3
80066a2: 4770 bx lr
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