17128 lines
637 KiB
Plaintext
17128 lines
637 KiB
Plaintext
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Fertirrega_v6.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00006854 0800010c 0800010c 0000110c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000013c 08006960 08006960 00007960 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08006a9c 08006a9c 00008064 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 08006a9c 08006a9c 00007a9c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08006aa4 08006aa4 00008064 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08006aa4 08006aa4 00007aa4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08006aa8 08006aa8 00007aa8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000064 20000000 08006aac 00008000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000880 20000064 08006b10 00008064 2**2
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ALLOC
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10 ._user_heap_stack 00000604 200008e4 08006b10 000088e4 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 00008064 2**0
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CONTENTS, READONLY
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12 .debug_info 0001496c 00000000 00000000 0000808d 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00003665 00000000 00000000 0001c9f9 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001320 00000000 00000000 00020060 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00000f0f 00000000 00000000 00021380 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0001a818 00000000 00000000 0002228f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00018d10 00000000 00000000 0003caa7 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 00095d25 00000000 00000000 000557b7 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 000eb4dc 2**0
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CONTENTS, READONLY
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20 .debug_frame 000050f0 00000000 00000000 000eb520 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000052 00000000 00000000 000f0610 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800010c <__do_global_dtors_aux>:
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800010c: b510 push {r4, lr}
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800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
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8000110: 7823 ldrb r3, [r4, #0]
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8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
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8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
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8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
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8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
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800011a: f3af 8000 nop.w
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800011e: 2301 movs r3, #1
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8000120: 7023 strb r3, [r4, #0]
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8000122: bd10 pop {r4, pc}
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8000124: 20000064 .word 0x20000064
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8000128: 00000000 .word 0x00000000
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800012c: 08006948 .word 0x08006948
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08000130 <frame_dummy>:
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8000130: b508 push {r3, lr}
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8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
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8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
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8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
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8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
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800013a: f3af 8000 nop.w
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800013e: bd08 pop {r3, pc}
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8000140: 00000000 .word 0x00000000
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8000144: 20000068 .word 0x20000068
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8000148: 08006948 .word 0x08006948
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0800014c <strlen>:
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800014c: 4603 mov r3, r0
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800014e: f813 2b01 ldrb.w r2, [r3], #1
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8000152: 2a00 cmp r2, #0
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8000154: d1fb bne.n 800014e <strlen+0x2>
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8000156: 1a18 subs r0, r3, r0
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8000158: 3801 subs r0, #1
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800015a: 4770 bx lr
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0800015c <__aeabi_dmul>:
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800015c: b570 push {r4, r5, r6, lr}
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800015e: f04f 0cff mov.w ip, #255 @ 0xff
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8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
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8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20
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800016a: bf1d ittte ne
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800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
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8000170: ea94 0f0c teqne r4, ip
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8000174: ea95 0f0c teqne r5, ip
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8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc>
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800017c: 442c add r4, r5
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800017e: ea81 0603 eor.w r6, r1, r3
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8000182: ea21 514c bic.w r1, r1, ip, lsl #21
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8000186: ea23 534c bic.w r3, r3, ip, lsl #21
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800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12
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800018e: bf18 it ne
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8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12
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8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
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8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
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800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4>
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800019e: fba0 ce02 umull ip, lr, r0, r2
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80001a2: f04f 0500 mov.w r5, #0
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80001a6: fbe1 e502 umlal lr, r5, r1, r2
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80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
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80001ae: fbe0 e503 umlal lr, r5, r0, r3
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80001b2: f04f 0600 mov.w r6, #0
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80001b6: fbe1 5603 umlal r5, r6, r1, r3
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80001ba: f09c 0f00 teq ip, #0
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80001be: bf18 it ne
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80001c0: f04e 0e01 orrne.w lr, lr, #1
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80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff
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80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200
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80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300
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80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80>
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80001d2: ea5f 0e4e movs.w lr, lr, lsl #1
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80001d6: 416d adcs r5, r5
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80001d8: eb46 0606 adc.w r6, r6, r6
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80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11
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80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21
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80001e4: ea4f 20c5 mov.w r0, r5, lsl #11
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80001e8: ea40 505e orr.w r0, r0, lr, lsr #21
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80001ec: ea4f 2ece mov.w lr, lr, lsl #11
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80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
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80001f4: bf88 it hi
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80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
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80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde>
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80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
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8000200: bf08 it eq
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8000202: ea5f 0e50 movseq.w lr, r0, lsr #1
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8000206: f150 0000 adcs.w r0, r0, #0
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800020a: eb41 5104 adc.w r1, r1, r4, lsl #20
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800020e: bd70 pop {r4, r5, r6, pc}
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8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
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8000214: ea46 0101 orr.w r1, r6, r1
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8000218: ea40 0002 orr.w r0, r0, r2
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800021c: ea81 0103 eor.w r1, r1, r3
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8000220: ebb4 045c subs.w r4, r4, ip, lsr #1
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8000224: bfc2 ittt gt
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8000226: ebd4 050c rsbsgt r5, r4, ip
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800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
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800022e: bd70 popgt {r4, r5, r6, pc}
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8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
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8000234: f04f 0e00 mov.w lr, #0
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8000238: 3c01 subs r4, #1
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800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238>
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800023e: f114 0f36 cmn.w r4, #54 @ 0x36
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8000242: bfde ittt le
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8000244: 2000 movle r0, #0
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8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
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800024a: bd70 pople {r4, r5, r6, pc}
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800024c: f1c4 0400 rsb r4, r4, #0
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8000250: 3c20 subs r4, #32
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8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164>
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8000254: 340c adds r4, #12
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8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134>
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8000258: f104 0414 add.w r4, r4, #20
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800025c: f1c4 0520 rsb r5, r4, #32
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8000260: fa00 f305 lsl.w r3, r0, r5
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8000264: fa20 f004 lsr.w r0, r0, r4
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8000268: fa01 f205 lsl.w r2, r1, r5
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800026c: ea40 0002 orr.w r0, r0, r2
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8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
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8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
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8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31
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800027c: fa21 f604 lsr.w r6, r1, r4
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8000280: eb42 0106 adc.w r1, r2, r6
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8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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8000288: bf08 it eq
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800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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800028e: bd70 pop {r4, r5, r6, pc}
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8000290: f1c4 040c rsb r4, r4, #12
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8000294: f1c4 0520 rsb r5, r4, #32
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8000298: fa00 f304 lsl.w r3, r0, r4
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800029c: fa20 f005 lsr.w r0, r0, r5
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80002a0: fa01 f204 lsl.w r2, r1, r4
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80002a4: ea40 0002 orr.w r0, r0, r2
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80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31
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80002b0: f141 0100 adc.w r1, r1, #0
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80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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80002b8: bf08 it eq
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80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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80002be: bd70 pop {r4, r5, r6, pc}
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80002c0: f1c4 0520 rsb r5, r4, #32
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80002c4: fa00 f205 lsl.w r2, r0, r5
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80002c8: ea4e 0e02 orr.w lr, lr, r2
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80002cc: fa20 f304 lsr.w r3, r0, r4
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80002d0: fa01 f205 lsl.w r2, r1, r5
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80002d4: ea43 0302 orr.w r3, r3, r2
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80002d8: fa21 f004 lsr.w r0, r1, r4
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80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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80002e0: fa21 f204 lsr.w r2, r1, r4
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80002e4: ea20 0002 bic.w r0, r0, r2
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80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31
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80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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80002f0: bf08 it eq
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80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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80002f6: bd70 pop {r4, r5, r6, pc}
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80002f8: f094 0f00 teq r4, #0
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80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2>
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80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
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8000302: 0040 lsls r0, r0, #1
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8000304: eb41 0101 adc.w r1, r1, r1
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8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000
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800030c: bf08 it eq
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800030e: 3c01 subeq r4, #1
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8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6>
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8000312: ea41 0106 orr.w r1, r1, r6
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8000316: f095 0f00 teq r5, #0
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800031a: bf18 it ne
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800031c: 4770 bxne lr
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800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
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8000322: 0052 lsls r2, r2, #1
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8000324: eb43 0303 adc.w r3, r3, r3
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8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000
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800032c: bf08 it eq
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800032e: 3d01 subeq r5, #1
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8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6>
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8000332: ea43 0306 orr.w r3, r3, r6
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8000336: 4770 bx lr
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8000338: ea94 0f0c teq r4, ip
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800033c: ea0c 5513 and.w r5, ip, r3, lsr #20
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8000340: bf18 it ne
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8000342: ea95 0f0c teqne r5, ip
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8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206>
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8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1
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800034c: bf18 it ne
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800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c>
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8000354: ea81 0103 eor.w r1, r1, r3
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8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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800035c: f04f 0000 mov.w r0, #0
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8000360: bd70 pop {r4, r5, r6, pc}
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8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1
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8000366: bf06 itte eq
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8000368: 4610 moveq r0, r2
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800036a: 4619 moveq r1, r3
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800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a>
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8000372: ea94 0f0c teq r4, ip
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8000376: d102 bne.n 800037e <__aeabi_dmul+0x222>
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8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12
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800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a>
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800037e: ea95 0f0c teq r5, ip
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8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234>
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8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12
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8000388: bf1c itt ne
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800038a: 4610 movne r0, r2
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800038c: 4619 movne r1, r3
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800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a>
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8000390: ea81 0103 eor.w r1, r1, r3
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8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
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800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
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80003a0: f04f 0000 mov.w r0, #0
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80003a4: bd70 pop {r4, r5, r6, pc}
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80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
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80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
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80003ae: bd70 pop {r4, r5, r6, pc}
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080003b0 <__aeabi_drsub>:
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80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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80003b4: e002 b.n 80003bc <__adddf3>
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80003b6: bf00 nop
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080003b8 <__aeabi_dsub>:
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80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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080003bc <__adddf3>:
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80003bc: b530 push {r4, r5, lr}
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80003be: ea4f 0441 mov.w r4, r1, lsl #1
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80003c2: ea4f 0543 mov.w r5, r3, lsl #1
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80003c6: ea94 0f05 teq r4, r5
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80003ca: bf08 it eq
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80003cc: ea90 0f02 teqeq r0, r2
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80003d0: bf1f itttt ne
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80003d2: ea54 0c00 orrsne.w ip, r4, r0
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80003d6: ea55 0c02 orrsne.w ip, r5, r2
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80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee>
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80003e6: ea4f 5454 mov.w r4, r4, lsr #21
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80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80003ee: bfb8 it lt
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80003f0: 426d neglt r5, r5
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80003f2: dd0c ble.n 800040e <__adddf3+0x52>
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80003f4: 442c add r4, r5
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80003f6: ea80 0202 eor.w r2, r0, r2
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80003fa: ea81 0303 eor.w r3, r1, r3
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80003fe: ea82 0000 eor.w r0, r2, r0
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8000402: ea83 0101 eor.w r1, r3, r1
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8000406: ea80 0202 eor.w r2, r0, r2
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800040a: ea81 0303 eor.w r3, r1, r3
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800040e: 2d36 cmp r5, #54 @ 0x36
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8000410: bf88 it hi
|
|
8000412: bd30 pophi {r4, r5, pc}
|
|
8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000418: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
|
|
8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12
|
|
8000424: d002 beq.n 800042c <__adddf3+0x70>
|
|
8000426: 4240 negs r0, r0
|
|
8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
|
|
8000430: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12
|
|
8000438: d002 beq.n 8000440 <__adddf3+0x84>
|
|
800043a: 4252 negs r2, r2
|
|
800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
8000440: ea94 0f05 teq r4, r5
|
|
8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da>
|
|
8000448: f1a4 0401 sub.w r4, r4, #1
|
|
800044c: f1d5 0e20 rsbs lr, r5, #32
|
|
8000450: db0d blt.n 800046e <__adddf3+0xb2>
|
|
8000452: fa02 fc0e lsl.w ip, r2, lr
|
|
8000456: fa22 f205 lsr.w r2, r2, r5
|
|
800045a: 1880 adds r0, r0, r2
|
|
800045c: f141 0100 adc.w r1, r1, #0
|
|
8000460: fa03 f20e lsl.w r2, r3, lr
|
|
8000464: 1880 adds r0, r0, r2
|
|
8000466: fa43 f305 asr.w r3, r3, r5
|
|
800046a: 4159 adcs r1, r3
|
|
800046c: e00e b.n 800048c <__adddf3+0xd0>
|
|
800046e: f1a5 0520 sub.w r5, r5, #32
|
|
8000472: f10e 0e20 add.w lr, lr, #32
|
|
8000476: 2a01 cmp r2, #1
|
|
8000478: fa03 fc0e lsl.w ip, r3, lr
|
|
800047c: bf28 it cs
|
|
800047e: f04c 0c02 orrcs.w ip, ip, #2
|
|
8000482: fa43 f305 asr.w r3, r3, r5
|
|
8000486: 18c0 adds r0, r0, r3
|
|
8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31
|
|
800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000490: d507 bpl.n 80004a2 <__adddf3+0xe6>
|
|
8000492: f04f 0e00 mov.w lr, #0
|
|
8000496: f1dc 0c00 rsbs ip, ip, #0
|
|
800049a: eb7e 0000 sbcs.w r0, lr, r0
|
|
800049e: eb6e 0101 sbc.w r1, lr, r1
|
|
80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
|
|
80004a6: d31b bcc.n 80004e0 <__adddf3+0x124>
|
|
80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
|
|
80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c>
|
|
80004ae: 0849 lsrs r1, r1, #1
|
|
80004b0: ea5f 0030 movs.w r0, r0, rrx
|
|
80004b4: ea4f 0c3c mov.w ip, ip, rrx
|
|
80004b8: f104 0401 add.w r4, r4, #1
|
|
80004bc: ea4f 5244 mov.w r2, r4, lsl #21
|
|
80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
|
|
80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240>
|
|
80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
|
|
80004cc: bf08 it eq
|
|
80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
80004d2: f150 0000 adcs.w r0, r0, #0
|
|
80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80004da: ea41 0105 orr.w r1, r1, r5
|
|
80004de: bd30 pop {r4, r5, pc}
|
|
80004e0: ea5f 0c4c movs.w ip, ip, lsl #1
|
|
80004e4: 4140 adcs r0, r0
|
|
80004e6: eb41 0101 adc.w r1, r1, r1
|
|
80004ea: 3c01 subs r4, #1
|
|
80004ec: bf28 it cs
|
|
80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
|
|
80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c>
|
|
80004f4: f091 0f00 teq r1, #0
|
|
80004f8: bf04 itt eq
|
|
80004fa: 4601 moveq r1, r0
|
|
80004fc: 2000 moveq r0, #0
|
|
80004fe: fab1 f381 clz r3, r1
|
|
8000502: bf08 it eq
|
|
8000504: 3320 addeq r3, #32
|
|
8000506: f1a3 030b sub.w r3, r3, #11
|
|
800050a: f1b3 0220 subs.w r2, r3, #32
|
|
800050e: da0c bge.n 800052a <__adddf3+0x16e>
|
|
8000510: 320c adds r2, #12
|
|
8000512: dd08 ble.n 8000526 <__adddf3+0x16a>
|
|
8000514: f102 0c14 add.w ip, r2, #20
|
|
8000518: f1c2 020c rsb r2, r2, #12
|
|
800051c: fa01 f00c lsl.w r0, r1, ip
|
|
8000520: fa21 f102 lsr.w r1, r1, r2
|
|
8000524: e00c b.n 8000540 <__adddf3+0x184>
|
|
8000526: f102 0214 add.w r2, r2, #20
|
|
800052a: bfd8 it le
|
|
800052c: f1c2 0c20 rsble ip, r2, #32
|
|
8000530: fa01 f102 lsl.w r1, r1, r2
|
|
8000534: fa20 fc0c lsr.w ip, r0, ip
|
|
8000538: bfdc itt le
|
|
800053a: ea41 010c orrle.w r1, r1, ip
|
|
800053e: 4090 lslle r0, r2
|
|
8000540: 1ae4 subs r4, r4, r3
|
|
8000542: bfa2 ittt ge
|
|
8000544: eb01 5104 addge.w r1, r1, r4, lsl #20
|
|
8000548: 4329 orrge r1, r5
|
|
800054a: bd30 popge {r4, r5, pc}
|
|
800054c: ea6f 0404 mvn.w r4, r4
|
|
8000550: 3c1f subs r4, #31
|
|
8000552: da1c bge.n 800058e <__adddf3+0x1d2>
|
|
8000554: 340c adds r4, #12
|
|
8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba>
|
|
8000558: f104 0414 add.w r4, r4, #20
|
|
800055c: f1c4 0220 rsb r2, r4, #32
|
|
8000560: fa20 f004 lsr.w r0, r0, r4
|
|
8000564: fa01 f302 lsl.w r3, r1, r2
|
|
8000568: ea40 0003 orr.w r0, r0, r3
|
|
800056c: fa21 f304 lsr.w r3, r1, r4
|
|
8000570: ea45 0103 orr.w r1, r5, r3
|
|
8000574: bd30 pop {r4, r5, pc}
|
|
8000576: f1c4 040c rsb r4, r4, #12
|
|
800057a: f1c4 0220 rsb r2, r4, #32
|
|
800057e: fa20 f002 lsr.w r0, r0, r2
|
|
8000582: fa01 f304 lsl.w r3, r1, r4
|
|
8000586: ea40 0003 orr.w r0, r0, r3
|
|
800058a: 4629 mov r1, r5
|
|
800058c: bd30 pop {r4, r5, pc}
|
|
800058e: fa21 f004 lsr.w r0, r1, r4
|
|
8000592: 4629 mov r1, r5
|
|
8000594: bd30 pop {r4, r5, pc}
|
|
8000596: f094 0f00 teq r4, #0
|
|
800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
|
|
800059e: bf06 itte eq
|
|
80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
|
|
80005a4: 3401 addeq r4, #1
|
|
80005a6: 3d01 subne r5, #1
|
|
80005a8: e74e b.n 8000448 <__adddf3+0x8c>
|
|
80005aa: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80005ae: bf18 it ne
|
|
80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21
|
|
80005b4: d029 beq.n 800060a <__adddf3+0x24e>
|
|
80005b6: ea94 0f05 teq r4, r5
|
|
80005ba: bf08 it eq
|
|
80005bc: ea90 0f02 teqeq r0, r2
|
|
80005c0: d005 beq.n 80005ce <__adddf3+0x212>
|
|
80005c2: ea54 0c00 orrs.w ip, r4, r0
|
|
80005c6: bf04 itt eq
|
|
80005c8: 4619 moveq r1, r3
|
|
80005ca: 4610 moveq r0, r2
|
|
80005cc: bd30 pop {r4, r5, pc}
|
|
80005ce: ea91 0f03 teq r1, r3
|
|
80005d2: bf1e ittt ne
|
|
80005d4: 2100 movne r1, #0
|
|
80005d6: 2000 movne r0, #0
|
|
80005d8: bd30 popne {r4, r5, pc}
|
|
80005da: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80005de: d105 bne.n 80005ec <__adddf3+0x230>
|
|
80005e0: 0040 lsls r0, r0, #1
|
|
80005e2: 4149 adcs r1, r1
|
|
80005e4: bf28 it cs
|
|
80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
80005ea: bd30 pop {r4, r5, pc}
|
|
80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
80005f0: bf3c itt cc
|
|
80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
80005f6: bd30 popcc {r4, r5, pc}
|
|
80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
8000604: f04f 0000 mov.w r0, #0
|
|
8000608: bd30 pop {r4, r5, pc}
|
|
800060a: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
800060e: bf1a itte ne
|
|
8000610: 4619 movne r1, r3
|
|
8000612: 4610 movne r0, r2
|
|
8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
8000618: bf1c itt ne
|
|
800061a: 460b movne r3, r1
|
|
800061c: 4602 movne r2, r0
|
|
800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
8000622: bf06 itte eq
|
|
8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
8000628: ea91 0f03 teqeq r1, r3
|
|
800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
8000630: bd30 pop {r4, r5, pc}
|
|
8000632: bf00 nop
|
|
|
|
08000634 <__aeabi_ui2d>:
|
|
8000634: f090 0f00 teq r0, #0
|
|
8000638: bf04 itt eq
|
|
800063a: 2100 moveq r1, #0
|
|
800063c: 4770 bxeq lr
|
|
800063e: b530 push {r4, r5, lr}
|
|
8000640: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000644: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000648: f04f 0500 mov.w r5, #0
|
|
800064c: f04f 0100 mov.w r1, #0
|
|
8000650: e750 b.n 80004f4 <__adddf3+0x138>
|
|
8000652: bf00 nop
|
|
|
|
08000654 <__aeabi_i2d>:
|
|
8000654: f090 0f00 teq r0, #0
|
|
8000658: bf04 itt eq
|
|
800065a: 2100 moveq r1, #0
|
|
800065c: 4770 bxeq lr
|
|
800065e: b530 push {r4, r5, lr}
|
|
8000660: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000664: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
800066c: bf48 it mi
|
|
800066e: 4240 negmi r0, r0
|
|
8000670: f04f 0100 mov.w r1, #0
|
|
8000674: e73e b.n 80004f4 <__adddf3+0x138>
|
|
8000676: bf00 nop
|
|
|
|
08000678 <__aeabi_f2d>:
|
|
8000678: 0042 lsls r2, r0, #1
|
|
800067a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800067e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000682: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000686: bf1f itttt ne
|
|
8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000694: 4770 bxne lr
|
|
8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800069a: bf08 it eq
|
|
800069c: 4770 bxeq lr
|
|
800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
80006a2: bf04 itt eq
|
|
80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
80006a8: 4770 bxeq lr
|
|
80006aa: b530 push {r4, r5, lr}
|
|
80006ac: f44f 7460 mov.w r4, #896 @ 0x380
|
|
80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
80006b8: e71c b.n 80004f4 <__adddf3+0x138>
|
|
80006ba: bf00 nop
|
|
|
|
080006bc <__aeabi_ul2d>:
|
|
80006bc: ea50 0201 orrs.w r2, r0, r1
|
|
80006c0: bf08 it eq
|
|
80006c2: 4770 bxeq lr
|
|
80006c4: b530 push {r4, r5, lr}
|
|
80006c6: f04f 0500 mov.w r5, #0
|
|
80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16>
|
|
|
|
080006cc <__aeabi_l2d>:
|
|
80006cc: ea50 0201 orrs.w r2, r0, r1
|
|
80006d0: bf08 it eq
|
|
80006d2: 4770 bxeq lr
|
|
80006d4: b530 push {r4, r5, lr}
|
|
80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16>
|
|
80006dc: 4240 negs r0, r0
|
|
80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80006e2: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80006e6: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80006ea: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6>
|
|
80006f2: f04f 0203 mov.w r2, #3
|
|
80006f6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80006fa: bf18 it ne
|
|
80006fc: 3203 addne r2, #3
|
|
80006fe: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
8000702: bf18 it ne
|
|
8000704: 3203 addne r2, #3
|
|
8000706: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
800070a: f1c2 0320 rsb r3, r2, #32
|
|
800070e: fa00 fc03 lsl.w ip, r0, r3
|
|
8000712: fa20 f002 lsr.w r0, r0, r2
|
|
8000716: fa01 fe03 lsl.w lr, r1, r3
|
|
800071a: ea40 000e orr.w r0, r0, lr
|
|
800071e: fa21 f102 lsr.w r1, r1, r2
|
|
8000722: 4414 add r4, r2
|
|
8000724: e6bd b.n 80004a2 <__adddf3+0xe6>
|
|
8000726: bf00 nop
|
|
|
|
08000728 <__gedf2>:
|
|
8000728: f04f 3cff mov.w ip, #4294967295
|
|
800072c: e006 b.n 800073c <__cmpdf2+0x4>
|
|
800072e: bf00 nop
|
|
|
|
08000730 <__ledf2>:
|
|
8000730: f04f 0c01 mov.w ip, #1
|
|
8000734: e002 b.n 800073c <__cmpdf2+0x4>
|
|
8000736: bf00 nop
|
|
|
|
08000738 <__cmpdf2>:
|
|
8000738: f04f 0c01 mov.w ip, #1
|
|
800073c: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000740: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000744: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000748: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
800074c: bf18 it ne
|
|
800074e: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000752: d01b beq.n 800078c <__cmpdf2+0x54>
|
|
8000754: b001 add sp, #4
|
|
8000756: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
800075a: bf0c ite eq
|
|
800075c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000760: ea91 0f03 teqne r1, r3
|
|
8000764: bf02 ittt eq
|
|
8000766: ea90 0f02 teqeq r0, r2
|
|
800076a: 2000 moveq r0, #0
|
|
800076c: 4770 bxeq lr
|
|
800076e: f110 0f00 cmn.w r0, #0
|
|
8000772: ea91 0f03 teq r1, r3
|
|
8000776: bf58 it pl
|
|
8000778: 4299 cmppl r1, r3
|
|
800077a: bf08 it eq
|
|
800077c: 4290 cmpeq r0, r2
|
|
800077e: bf2c ite cs
|
|
8000780: 17d8 asrcs r0, r3, #31
|
|
8000782: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000786: f040 0001 orr.w r0, r0, #1
|
|
800078a: 4770 bx lr
|
|
800078c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000790: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000794: d102 bne.n 800079c <__cmpdf2+0x64>
|
|
8000796: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
800079a: d107 bne.n 80007ac <__cmpdf2+0x74>
|
|
800079c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
80007a0: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
80007a4: d1d6 bne.n 8000754 <__cmpdf2+0x1c>
|
|
80007a6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
80007aa: d0d3 beq.n 8000754 <__cmpdf2+0x1c>
|
|
80007ac: f85d 0b04 ldr.w r0, [sp], #4
|
|
80007b0: 4770 bx lr
|
|
80007b2: bf00 nop
|
|
|
|
080007b4 <__aeabi_cdrcmple>:
|
|
80007b4: 4684 mov ip, r0
|
|
80007b6: 4610 mov r0, r2
|
|
80007b8: 4662 mov r2, ip
|
|
80007ba: 468c mov ip, r1
|
|
80007bc: 4619 mov r1, r3
|
|
80007be: 4663 mov r3, ip
|
|
80007c0: e000 b.n 80007c4 <__aeabi_cdcmpeq>
|
|
80007c2: bf00 nop
|
|
|
|
080007c4 <__aeabi_cdcmpeq>:
|
|
80007c4: b501 push {r0, lr}
|
|
80007c6: f7ff ffb7 bl 8000738 <__cmpdf2>
|
|
80007ca: 2800 cmp r0, #0
|
|
80007cc: bf48 it mi
|
|
80007ce: f110 0f00 cmnmi.w r0, #0
|
|
80007d2: bd01 pop {r0, pc}
|
|
|
|
080007d4 <__aeabi_dcmpeq>:
|
|
80007d4: f84d ed08 str.w lr, [sp, #-8]!
|
|
80007d8: f7ff fff4 bl 80007c4 <__aeabi_cdcmpeq>
|
|
80007dc: bf0c ite eq
|
|
80007de: 2001 moveq r0, #1
|
|
80007e0: 2000 movne r0, #0
|
|
80007e2: f85d fb08 ldr.w pc, [sp], #8
|
|
80007e6: bf00 nop
|
|
|
|
080007e8 <__aeabi_dcmplt>:
|
|
80007e8: f84d ed08 str.w lr, [sp, #-8]!
|
|
80007ec: f7ff ffea bl 80007c4 <__aeabi_cdcmpeq>
|
|
80007f0: bf34 ite cc
|
|
80007f2: 2001 movcc r0, #1
|
|
80007f4: 2000 movcs r0, #0
|
|
80007f6: f85d fb08 ldr.w pc, [sp], #8
|
|
80007fa: bf00 nop
|
|
|
|
080007fc <__aeabi_dcmple>:
|
|
80007fc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000800: f7ff ffe0 bl 80007c4 <__aeabi_cdcmpeq>
|
|
8000804: bf94 ite ls
|
|
8000806: 2001 movls r0, #1
|
|
8000808: 2000 movhi r0, #0
|
|
800080a: f85d fb08 ldr.w pc, [sp], #8
|
|
800080e: bf00 nop
|
|
|
|
08000810 <__aeabi_dcmpge>:
|
|
8000810: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000814: f7ff ffce bl 80007b4 <__aeabi_cdrcmple>
|
|
8000818: bf94 ite ls
|
|
800081a: 2001 movls r0, #1
|
|
800081c: 2000 movhi r0, #0
|
|
800081e: f85d fb08 ldr.w pc, [sp], #8
|
|
8000822: bf00 nop
|
|
|
|
08000824 <__aeabi_dcmpgt>:
|
|
8000824: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000828: f7ff ffc4 bl 80007b4 <__aeabi_cdrcmple>
|
|
800082c: bf34 ite cc
|
|
800082e: 2001 movcc r0, #1
|
|
8000830: 2000 movcs r0, #0
|
|
8000832: f85d fb08 ldr.w pc, [sp], #8
|
|
8000836: bf00 nop
|
|
|
|
08000838 <__aeabi_d2iz>:
|
|
8000838: ea4f 0241 mov.w r2, r1, lsl #1
|
|
800083c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000840: d215 bcs.n 800086e <__aeabi_d2iz+0x36>
|
|
8000842: d511 bpl.n 8000868 <__aeabi_d2iz+0x30>
|
|
8000844: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000848: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
800084c: d912 bls.n 8000874 <__aeabi_d2iz+0x3c>
|
|
800084e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000852: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000856: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
800085a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
800085e: fa23 f002 lsr.w r0, r3, r2
|
|
8000862: bf18 it ne
|
|
8000864: 4240 negne r0, r0
|
|
8000866: 4770 bx lr
|
|
8000868: f04f 0000 mov.w r0, #0
|
|
800086c: 4770 bx lr
|
|
800086e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000872: d105 bne.n 8000880 <__aeabi_d2iz+0x48>
|
|
8000874: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000878: bf08 it eq
|
|
800087a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
800087e: 4770 bx lr
|
|
8000880: f04f 0000 mov.w r0, #0
|
|
8000884: 4770 bx lr
|
|
8000886: bf00 nop
|
|
|
|
08000888 <__aeabi_frsub>:
|
|
8000888: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
|
|
800088c: e002 b.n 8000894 <__addsf3>
|
|
800088e: bf00 nop
|
|
|
|
08000890 <__aeabi_fsub>:
|
|
8000890: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
|
|
|
|
08000894 <__addsf3>:
|
|
8000894: 0042 lsls r2, r0, #1
|
|
8000896: bf1f itttt ne
|
|
8000898: ea5f 0341 movsne.w r3, r1, lsl #1
|
|
800089c: ea92 0f03 teqne r2, r3
|
|
80008a0: ea7f 6c22 mvnsne.w ip, r2, asr #24
|
|
80008a4: ea7f 6c23 mvnsne.w ip, r3, asr #24
|
|
80008a8: d06a beq.n 8000980 <__addsf3+0xec>
|
|
80008aa: ea4f 6212 mov.w r2, r2, lsr #24
|
|
80008ae: ebd2 6313 rsbs r3, r2, r3, lsr #24
|
|
80008b2: bfc1 itttt gt
|
|
80008b4: 18d2 addgt r2, r2, r3
|
|
80008b6: 4041 eorgt r1, r0
|
|
80008b8: 4048 eorgt r0, r1
|
|
80008ba: 4041 eorgt r1, r0
|
|
80008bc: bfb8 it lt
|
|
80008be: 425b neglt r3, r3
|
|
80008c0: 2b19 cmp r3, #25
|
|
80008c2: bf88 it hi
|
|
80008c4: 4770 bxhi lr
|
|
80008c6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
|
|
80008ca: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
80008ce: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
|
|
80008d2: bf18 it ne
|
|
80008d4: 4240 negne r0, r0
|
|
80008d6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
80008da: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
|
|
80008de: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
|
|
80008e2: bf18 it ne
|
|
80008e4: 4249 negne r1, r1
|
|
80008e6: ea92 0f03 teq r2, r3
|
|
80008ea: d03f beq.n 800096c <__addsf3+0xd8>
|
|
80008ec: f1a2 0201 sub.w r2, r2, #1
|
|
80008f0: fa41 fc03 asr.w ip, r1, r3
|
|
80008f4: eb10 000c adds.w r0, r0, ip
|
|
80008f8: f1c3 0320 rsb r3, r3, #32
|
|
80008fc: fa01 f103 lsl.w r1, r1, r3
|
|
8000900: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
|
|
8000904: d502 bpl.n 800090c <__addsf3+0x78>
|
|
8000906: 4249 negs r1, r1
|
|
8000908: eb60 0040 sbc.w r0, r0, r0, lsl #1
|
|
800090c: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
|
|
8000910: d313 bcc.n 800093a <__addsf3+0xa6>
|
|
8000912: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
|
|
8000916: d306 bcc.n 8000926 <__addsf3+0x92>
|
|
8000918: 0840 lsrs r0, r0, #1
|
|
800091a: ea4f 0131 mov.w r1, r1, rrx
|
|
800091e: f102 0201 add.w r2, r2, #1
|
|
8000922: 2afe cmp r2, #254 @ 0xfe
|
|
8000924: d251 bcs.n 80009ca <__addsf3+0x136>
|
|
8000926: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
|
|
800092a: eb40 50c2 adc.w r0, r0, r2, lsl #23
|
|
800092e: bf08 it eq
|
|
8000930: f020 0001 biceq.w r0, r0, #1
|
|
8000934: ea40 0003 orr.w r0, r0, r3
|
|
8000938: 4770 bx lr
|
|
800093a: 0049 lsls r1, r1, #1
|
|
800093c: eb40 0000 adc.w r0, r0, r0
|
|
8000940: 3a01 subs r2, #1
|
|
8000942: bf28 it cs
|
|
8000944: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
|
|
8000948: d2ed bcs.n 8000926 <__addsf3+0x92>
|
|
800094a: fab0 fc80 clz ip, r0
|
|
800094e: f1ac 0c08 sub.w ip, ip, #8
|
|
8000952: ebb2 020c subs.w r2, r2, ip
|
|
8000956: fa00 f00c lsl.w r0, r0, ip
|
|
800095a: bfaa itet ge
|
|
800095c: eb00 50c2 addge.w r0, r0, r2, lsl #23
|
|
8000960: 4252 neglt r2, r2
|
|
8000962: 4318 orrge r0, r3
|
|
8000964: bfbc itt lt
|
|
8000966: 40d0 lsrlt r0, r2
|
|
8000968: 4318 orrlt r0, r3
|
|
800096a: 4770 bx lr
|
|
800096c: f092 0f00 teq r2, #0
|
|
8000970: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
|
|
8000974: bf06 itte eq
|
|
8000976: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
|
|
800097a: 3201 addeq r2, #1
|
|
800097c: 3b01 subne r3, #1
|
|
800097e: e7b5 b.n 80008ec <__addsf3+0x58>
|
|
8000980: ea4f 0341 mov.w r3, r1, lsl #1
|
|
8000984: ea7f 6c22 mvns.w ip, r2, asr #24
|
|
8000988: bf18 it ne
|
|
800098a: ea7f 6c23 mvnsne.w ip, r3, asr #24
|
|
800098e: d021 beq.n 80009d4 <__addsf3+0x140>
|
|
8000990: ea92 0f03 teq r2, r3
|
|
8000994: d004 beq.n 80009a0 <__addsf3+0x10c>
|
|
8000996: f092 0f00 teq r2, #0
|
|
800099a: bf08 it eq
|
|
800099c: 4608 moveq r0, r1
|
|
800099e: 4770 bx lr
|
|
80009a0: ea90 0f01 teq r0, r1
|
|
80009a4: bf1c itt ne
|
|
80009a6: 2000 movne r0, #0
|
|
80009a8: 4770 bxne lr
|
|
80009aa: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
|
|
80009ae: d104 bne.n 80009ba <__addsf3+0x126>
|
|
80009b0: 0040 lsls r0, r0, #1
|
|
80009b2: bf28 it cs
|
|
80009b4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
|
|
80009b8: 4770 bx lr
|
|
80009ba: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
|
|
80009be: bf3c itt cc
|
|
80009c0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
|
|
80009c4: 4770 bxcc lr
|
|
80009c6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
|
|
80009ca: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
|
|
80009ce: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
80009d2: 4770 bx lr
|
|
80009d4: ea7f 6222 mvns.w r2, r2, asr #24
|
|
80009d8: bf16 itet ne
|
|
80009da: 4608 movne r0, r1
|
|
80009dc: ea7f 6323 mvnseq.w r3, r3, asr #24
|
|
80009e0: 4601 movne r1, r0
|
|
80009e2: 0242 lsls r2, r0, #9
|
|
80009e4: bf06 itte eq
|
|
80009e6: ea5f 2341 movseq.w r3, r1, lsl #9
|
|
80009ea: ea90 0f01 teqeq r0, r1
|
|
80009ee: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
|
|
80009f2: 4770 bx lr
|
|
|
|
080009f4 <__aeabi_ui2f>:
|
|
80009f4: f04f 0300 mov.w r3, #0
|
|
80009f8: e004 b.n 8000a04 <__aeabi_i2f+0x8>
|
|
80009fa: bf00 nop
|
|
|
|
080009fc <__aeabi_i2f>:
|
|
80009fc: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
|
|
8000a00: bf48 it mi
|
|
8000a02: 4240 negmi r0, r0
|
|
8000a04: ea5f 0c00 movs.w ip, r0
|
|
8000a08: bf08 it eq
|
|
8000a0a: 4770 bxeq lr
|
|
8000a0c: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
|
|
8000a10: 4601 mov r1, r0
|
|
8000a12: f04f 0000 mov.w r0, #0
|
|
8000a16: e01c b.n 8000a52 <__aeabi_l2f+0x2a>
|
|
|
|
08000a18 <__aeabi_ul2f>:
|
|
8000a18: ea50 0201 orrs.w r2, r0, r1
|
|
8000a1c: bf08 it eq
|
|
8000a1e: 4770 bxeq lr
|
|
8000a20: f04f 0300 mov.w r3, #0
|
|
8000a24: e00a b.n 8000a3c <__aeabi_l2f+0x14>
|
|
8000a26: bf00 nop
|
|
|
|
08000a28 <__aeabi_l2f>:
|
|
8000a28: ea50 0201 orrs.w r2, r0, r1
|
|
8000a2c: bf08 it eq
|
|
8000a2e: 4770 bxeq lr
|
|
8000a30: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
|
|
8000a34: d502 bpl.n 8000a3c <__aeabi_l2f+0x14>
|
|
8000a36: 4240 negs r0, r0
|
|
8000a38: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000a3c: ea5f 0c01 movs.w ip, r1
|
|
8000a40: bf02 ittt eq
|
|
8000a42: 4684 moveq ip, r0
|
|
8000a44: 4601 moveq r1, r0
|
|
8000a46: 2000 moveq r0, #0
|
|
8000a48: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
|
|
8000a4c: bf08 it eq
|
|
8000a4e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
|
|
8000a52: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
|
|
8000a56: fabc f28c clz r2, ip
|
|
8000a5a: 3a08 subs r2, #8
|
|
8000a5c: eba3 53c2 sub.w r3, r3, r2, lsl #23
|
|
8000a60: db10 blt.n 8000a84 <__aeabi_l2f+0x5c>
|
|
8000a62: fa01 fc02 lsl.w ip, r1, r2
|
|
8000a66: 4463 add r3, ip
|
|
8000a68: fa00 fc02 lsl.w ip, r0, r2
|
|
8000a6c: f1c2 0220 rsb r2, r2, #32
|
|
8000a70: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
|
|
8000a74: fa20 f202 lsr.w r2, r0, r2
|
|
8000a78: eb43 0002 adc.w r0, r3, r2
|
|
8000a7c: bf08 it eq
|
|
8000a7e: f020 0001 biceq.w r0, r0, #1
|
|
8000a82: 4770 bx lr
|
|
8000a84: f102 0220 add.w r2, r2, #32
|
|
8000a88: fa01 fc02 lsl.w ip, r1, r2
|
|
8000a8c: f1c2 0220 rsb r2, r2, #32
|
|
8000a90: ea50 004c orrs.w r0, r0, ip, lsl #1
|
|
8000a94: fa21 f202 lsr.w r2, r1, r2
|
|
8000a98: eb43 0002 adc.w r0, r3, r2
|
|
8000a9c: bf08 it eq
|
|
8000a9e: ea20 70dc biceq.w r0, r0, ip, lsr #31
|
|
8000aa2: 4770 bx lr
|
|
|
|
08000aa4 <__aeabi_fmul>:
|
|
8000aa4: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000aa8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
|
|
8000aac: bf1e ittt ne
|
|
8000aae: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
|
|
8000ab2: ea92 0f0c teqne r2, ip
|
|
8000ab6: ea93 0f0c teqne r3, ip
|
|
8000aba: d06f beq.n 8000b9c <__aeabi_fmul+0xf8>
|
|
8000abc: 441a add r2, r3
|
|
8000abe: ea80 0c01 eor.w ip, r0, r1
|
|
8000ac2: 0240 lsls r0, r0, #9
|
|
8000ac4: bf18 it ne
|
|
8000ac6: ea5f 2141 movsne.w r1, r1, lsl #9
|
|
8000aca: d01e beq.n 8000b0a <__aeabi_fmul+0x66>
|
|
8000acc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8000ad0: ea43 1050 orr.w r0, r3, r0, lsr #5
|
|
8000ad4: ea43 1151 orr.w r1, r3, r1, lsr #5
|
|
8000ad8: fba0 3101 umull r3, r1, r0, r1
|
|
8000adc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
|
|
8000ae0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
|
|
8000ae4: bf3e ittt cc
|
|
8000ae6: 0049 lslcc r1, r1, #1
|
|
8000ae8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
|
|
8000aec: 005b lslcc r3, r3, #1
|
|
8000aee: ea40 0001 orr.w r0, r0, r1
|
|
8000af2: f162 027f sbc.w r2, r2, #127 @ 0x7f
|
|
8000af6: 2afd cmp r2, #253 @ 0xfd
|
|
8000af8: d81d bhi.n 8000b36 <__aeabi_fmul+0x92>
|
|
8000afa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8000afe: eb40 50c2 adc.w r0, r0, r2, lsl #23
|
|
8000b02: bf08 it eq
|
|
8000b04: f020 0001 biceq.w r0, r0, #1
|
|
8000b08: 4770 bx lr
|
|
8000b0a: f090 0f00 teq r0, #0
|
|
8000b0e: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
|
|
8000b12: bf08 it eq
|
|
8000b14: 0249 lsleq r1, r1, #9
|
|
8000b16: ea4c 2050 orr.w r0, ip, r0, lsr #9
|
|
8000b1a: ea40 2051 orr.w r0, r0, r1, lsr #9
|
|
8000b1e: 3a7f subs r2, #127 @ 0x7f
|
|
8000b20: bfc2 ittt gt
|
|
8000b22: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
|
|
8000b26: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
|
|
8000b2a: 4770 bxgt lr
|
|
8000b2c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000b30: f04f 0300 mov.w r3, #0
|
|
8000b34: 3a01 subs r2, #1
|
|
8000b36: dc5d bgt.n 8000bf4 <__aeabi_fmul+0x150>
|
|
8000b38: f112 0f19 cmn.w r2, #25
|
|
8000b3c: bfdc itt le
|
|
8000b3e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
|
|
8000b42: 4770 bxle lr
|
|
8000b44: f1c2 0200 rsb r2, r2, #0
|
|
8000b48: 0041 lsls r1, r0, #1
|
|
8000b4a: fa21 f102 lsr.w r1, r1, r2
|
|
8000b4e: f1c2 0220 rsb r2, r2, #32
|
|
8000b52: fa00 fc02 lsl.w ip, r0, r2
|
|
8000b56: ea5f 0031 movs.w r0, r1, rrx
|
|
8000b5a: f140 0000 adc.w r0, r0, #0
|
|
8000b5e: ea53 034c orrs.w r3, r3, ip, lsl #1
|
|
8000b62: bf08 it eq
|
|
8000b64: ea20 70dc biceq.w r0, r0, ip, lsr #31
|
|
8000b68: 4770 bx lr
|
|
8000b6a: f092 0f00 teq r2, #0
|
|
8000b6e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
|
|
8000b72: bf02 ittt eq
|
|
8000b74: 0040 lsleq r0, r0, #1
|
|
8000b76: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
|
|
8000b7a: 3a01 subeq r2, #1
|
|
8000b7c: d0f9 beq.n 8000b72 <__aeabi_fmul+0xce>
|
|
8000b7e: ea40 000c orr.w r0, r0, ip
|
|
8000b82: f093 0f00 teq r3, #0
|
|
8000b86: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
|
|
8000b8a: bf02 ittt eq
|
|
8000b8c: 0049 lsleq r1, r1, #1
|
|
8000b8e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
|
|
8000b92: 3b01 subeq r3, #1
|
|
8000b94: d0f9 beq.n 8000b8a <__aeabi_fmul+0xe6>
|
|
8000b96: ea41 010c orr.w r1, r1, ip
|
|
8000b9a: e78f b.n 8000abc <__aeabi_fmul+0x18>
|
|
8000b9c: ea0c 53d1 and.w r3, ip, r1, lsr #23
|
|
8000ba0: ea92 0f0c teq r2, ip
|
|
8000ba4: bf18 it ne
|
|
8000ba6: ea93 0f0c teqne r3, ip
|
|
8000baa: d00a beq.n 8000bc2 <__aeabi_fmul+0x11e>
|
|
8000bac: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
|
|
8000bb0: bf18 it ne
|
|
8000bb2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
|
|
8000bb6: d1d8 bne.n 8000b6a <__aeabi_fmul+0xc6>
|
|
8000bb8: ea80 0001 eor.w r0, r0, r1
|
|
8000bbc: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
|
|
8000bc0: 4770 bx lr
|
|
8000bc2: f090 0f00 teq r0, #0
|
|
8000bc6: bf17 itett ne
|
|
8000bc8: f090 4f00 teqne r0, #2147483648 @ 0x80000000
|
|
8000bcc: 4608 moveq r0, r1
|
|
8000bce: f091 0f00 teqne r1, #0
|
|
8000bd2: f091 4f00 teqne r1, #2147483648 @ 0x80000000
|
|
8000bd6: d014 beq.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000bd8: ea92 0f0c teq r2, ip
|
|
8000bdc: d101 bne.n 8000be2 <__aeabi_fmul+0x13e>
|
|
8000bde: 0242 lsls r2, r0, #9
|
|
8000be0: d10f bne.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000be2: ea93 0f0c teq r3, ip
|
|
8000be6: d103 bne.n 8000bf0 <__aeabi_fmul+0x14c>
|
|
8000be8: 024b lsls r3, r1, #9
|
|
8000bea: bf18 it ne
|
|
8000bec: 4608 movne r0, r1
|
|
8000bee: d108 bne.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000bf0: ea80 0001 eor.w r0, r0, r1
|
|
8000bf4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
|
|
8000bf8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
|
|
8000bfc: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000c00: 4770 bx lr
|
|
8000c02: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
|
|
8000c06: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
|
|
8000c0a: 4770 bx lr
|
|
|
|
08000c0c <__aeabi_fdiv>:
|
|
8000c0c: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000c10: ea1c 52d0 ands.w r2, ip, r0, lsr #23
|
|
8000c14: bf1e ittt ne
|
|
8000c16: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
|
|
8000c1a: ea92 0f0c teqne r2, ip
|
|
8000c1e: ea93 0f0c teqne r3, ip
|
|
8000c22: d069 beq.n 8000cf8 <__aeabi_fdiv+0xec>
|
|
8000c24: eba2 0203 sub.w r2, r2, r3
|
|
8000c28: ea80 0c01 eor.w ip, r0, r1
|
|
8000c2c: 0249 lsls r1, r1, #9
|
|
8000c2e: ea4f 2040 mov.w r0, r0, lsl #9
|
|
8000c32: d037 beq.n 8000ca4 <__aeabi_fdiv+0x98>
|
|
8000c34: f04f 5380 mov.w r3, #268435456 @ 0x10000000
|
|
8000c38: ea43 1111 orr.w r1, r3, r1, lsr #4
|
|
8000c3c: ea43 1310 orr.w r3, r3, r0, lsr #4
|
|
8000c40: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
|
|
8000c44: 428b cmp r3, r1
|
|
8000c46: bf38 it cc
|
|
8000c48: 005b lslcc r3, r3, #1
|
|
8000c4a: f142 027d adc.w r2, r2, #125 @ 0x7d
|
|
8000c4e: f44f 0c00 mov.w ip, #8388608 @ 0x800000
|
|
8000c52: 428b cmp r3, r1
|
|
8000c54: bf24 itt cs
|
|
8000c56: 1a5b subcs r3, r3, r1
|
|
8000c58: ea40 000c orrcs.w r0, r0, ip
|
|
8000c5c: ebb3 0f51 cmp.w r3, r1, lsr #1
|
|
8000c60: bf24 itt cs
|
|
8000c62: eba3 0351 subcs.w r3, r3, r1, lsr #1
|
|
8000c66: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
8000c6a: ebb3 0f91 cmp.w r3, r1, lsr #2
|
|
8000c6e: bf24 itt cs
|
|
8000c70: eba3 0391 subcs.w r3, r3, r1, lsr #2
|
|
8000c74: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000c78: ebb3 0fd1 cmp.w r3, r1, lsr #3
|
|
8000c7c: bf24 itt cs
|
|
8000c7e: eba3 03d1 subcs.w r3, r3, r1, lsr #3
|
|
8000c82: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000c86: 011b lsls r3, r3, #4
|
|
8000c88: bf18 it ne
|
|
8000c8a: ea5f 1c1c movsne.w ip, ip, lsr #4
|
|
8000c8e: d1e0 bne.n 8000c52 <__aeabi_fdiv+0x46>
|
|
8000c90: 2afd cmp r2, #253 @ 0xfd
|
|
8000c92: f63f af50 bhi.w 8000b36 <__aeabi_fmul+0x92>
|
|
8000c96: 428b cmp r3, r1
|
|
8000c98: eb40 50c2 adc.w r0, r0, r2, lsl #23
|
|
8000c9c: bf08 it eq
|
|
8000c9e: f020 0001 biceq.w r0, r0, #1
|
|
8000ca2: 4770 bx lr
|
|
8000ca4: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
|
|
8000ca8: ea4c 2050 orr.w r0, ip, r0, lsr #9
|
|
8000cac: 327f adds r2, #127 @ 0x7f
|
|
8000cae: bfc2 ittt gt
|
|
8000cb0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
|
|
8000cb4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
|
|
8000cb8: 4770 bxgt lr
|
|
8000cba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000cbe: f04f 0300 mov.w r3, #0
|
|
8000cc2: 3a01 subs r2, #1
|
|
8000cc4: e737 b.n 8000b36 <__aeabi_fmul+0x92>
|
|
8000cc6: f092 0f00 teq r2, #0
|
|
8000cca: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
|
|
8000cce: bf02 ittt eq
|
|
8000cd0: 0040 lsleq r0, r0, #1
|
|
8000cd2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
|
|
8000cd6: 3a01 subeq r2, #1
|
|
8000cd8: d0f9 beq.n 8000cce <__aeabi_fdiv+0xc2>
|
|
8000cda: ea40 000c orr.w r0, r0, ip
|
|
8000cde: f093 0f00 teq r3, #0
|
|
8000ce2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
|
|
8000ce6: bf02 ittt eq
|
|
8000ce8: 0049 lsleq r1, r1, #1
|
|
8000cea: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
|
|
8000cee: 3b01 subeq r3, #1
|
|
8000cf0: d0f9 beq.n 8000ce6 <__aeabi_fdiv+0xda>
|
|
8000cf2: ea41 010c orr.w r1, r1, ip
|
|
8000cf6: e795 b.n 8000c24 <__aeabi_fdiv+0x18>
|
|
8000cf8: ea0c 53d1 and.w r3, ip, r1, lsr #23
|
|
8000cfc: ea92 0f0c teq r2, ip
|
|
8000d00: d108 bne.n 8000d14 <__aeabi_fdiv+0x108>
|
|
8000d02: 0242 lsls r2, r0, #9
|
|
8000d04: f47f af7d bne.w 8000c02 <__aeabi_fmul+0x15e>
|
|
8000d08: ea93 0f0c teq r3, ip
|
|
8000d0c: f47f af70 bne.w 8000bf0 <__aeabi_fmul+0x14c>
|
|
8000d10: 4608 mov r0, r1
|
|
8000d12: e776 b.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000d14: ea93 0f0c teq r3, ip
|
|
8000d18: d104 bne.n 8000d24 <__aeabi_fdiv+0x118>
|
|
8000d1a: 024b lsls r3, r1, #9
|
|
8000d1c: f43f af4c beq.w 8000bb8 <__aeabi_fmul+0x114>
|
|
8000d20: 4608 mov r0, r1
|
|
8000d22: e76e b.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000d24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
|
|
8000d28: bf18 it ne
|
|
8000d2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
|
|
8000d2e: d1ca bne.n 8000cc6 <__aeabi_fdiv+0xba>
|
|
8000d30: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
|
|
8000d34: f47f af5c bne.w 8000bf0 <__aeabi_fmul+0x14c>
|
|
8000d38: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
|
|
8000d3c: f47f af3c bne.w 8000bb8 <__aeabi_fmul+0x114>
|
|
8000d40: e75f b.n 8000c02 <__aeabi_fmul+0x15e>
|
|
8000d42: bf00 nop
|
|
|
|
08000d44 <__gesf2>:
|
|
8000d44: f04f 3cff mov.w ip, #4294967295
|
|
8000d48: e006 b.n 8000d58 <__cmpsf2+0x4>
|
|
8000d4a: bf00 nop
|
|
|
|
08000d4c <__lesf2>:
|
|
8000d4c: f04f 0c01 mov.w ip, #1
|
|
8000d50: e002 b.n 8000d58 <__cmpsf2+0x4>
|
|
8000d52: bf00 nop
|
|
|
|
08000d54 <__cmpsf2>:
|
|
8000d54: f04f 0c01 mov.w ip, #1
|
|
8000d58: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000d5c: ea4f 0240 mov.w r2, r0, lsl #1
|
|
8000d60: ea4f 0341 mov.w r3, r1, lsl #1
|
|
8000d64: ea7f 6c22 mvns.w ip, r2, asr #24
|
|
8000d68: bf18 it ne
|
|
8000d6a: ea7f 6c23 mvnsne.w ip, r3, asr #24
|
|
8000d6e: d011 beq.n 8000d94 <__cmpsf2+0x40>
|
|
8000d70: b001 add sp, #4
|
|
8000d72: ea52 0c53 orrs.w ip, r2, r3, lsr #1
|
|
8000d76: bf18 it ne
|
|
8000d78: ea90 0f01 teqne r0, r1
|
|
8000d7c: bf58 it pl
|
|
8000d7e: ebb2 0003 subspl.w r0, r2, r3
|
|
8000d82: bf88 it hi
|
|
8000d84: 17c8 asrhi r0, r1, #31
|
|
8000d86: bf38 it cc
|
|
8000d88: ea6f 70e1 mvncc.w r0, r1, asr #31
|
|
8000d8c: bf18 it ne
|
|
8000d8e: f040 0001 orrne.w r0, r0, #1
|
|
8000d92: 4770 bx lr
|
|
8000d94: ea7f 6c22 mvns.w ip, r2, asr #24
|
|
8000d98: d102 bne.n 8000da0 <__cmpsf2+0x4c>
|
|
8000d9a: ea5f 2c40 movs.w ip, r0, lsl #9
|
|
8000d9e: d105 bne.n 8000dac <__cmpsf2+0x58>
|
|
8000da0: ea7f 6c23 mvns.w ip, r3, asr #24
|
|
8000da4: d1e4 bne.n 8000d70 <__cmpsf2+0x1c>
|
|
8000da6: ea5f 2c41 movs.w ip, r1, lsl #9
|
|
8000daa: d0e1 beq.n 8000d70 <__cmpsf2+0x1c>
|
|
8000dac: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000db0: 4770 bx lr
|
|
8000db2: bf00 nop
|
|
|
|
08000db4 <__aeabi_cfrcmple>:
|
|
8000db4: 4684 mov ip, r0
|
|
8000db6: 4608 mov r0, r1
|
|
8000db8: 4661 mov r1, ip
|
|
8000dba: e7ff b.n 8000dbc <__aeabi_cfcmpeq>
|
|
|
|
08000dbc <__aeabi_cfcmpeq>:
|
|
8000dbc: b50f push {r0, r1, r2, r3, lr}
|
|
8000dbe: f7ff ffc9 bl 8000d54 <__cmpsf2>
|
|
8000dc2: 2800 cmp r0, #0
|
|
8000dc4: bf48 it mi
|
|
8000dc6: f110 0f00 cmnmi.w r0, #0
|
|
8000dca: bd0f pop {r0, r1, r2, r3, pc}
|
|
|
|
08000dcc <__aeabi_fcmpeq>:
|
|
8000dcc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000dd0: f7ff fff4 bl 8000dbc <__aeabi_cfcmpeq>
|
|
8000dd4: bf0c ite eq
|
|
8000dd6: 2001 moveq r0, #1
|
|
8000dd8: 2000 movne r0, #0
|
|
8000dda: f85d fb08 ldr.w pc, [sp], #8
|
|
8000dde: bf00 nop
|
|
|
|
08000de0 <__aeabi_fcmplt>:
|
|
8000de0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000de4: f7ff ffea bl 8000dbc <__aeabi_cfcmpeq>
|
|
8000de8: bf34 ite cc
|
|
8000dea: 2001 movcc r0, #1
|
|
8000dec: 2000 movcs r0, #0
|
|
8000dee: f85d fb08 ldr.w pc, [sp], #8
|
|
8000df2: bf00 nop
|
|
|
|
08000df4 <__aeabi_fcmple>:
|
|
8000df4: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000df8: f7ff ffe0 bl 8000dbc <__aeabi_cfcmpeq>
|
|
8000dfc: bf94 ite ls
|
|
8000dfe: 2001 movls r0, #1
|
|
8000e00: 2000 movhi r0, #0
|
|
8000e02: f85d fb08 ldr.w pc, [sp], #8
|
|
8000e06: bf00 nop
|
|
|
|
08000e08 <__aeabi_fcmpge>:
|
|
8000e08: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000e0c: f7ff ffd2 bl 8000db4 <__aeabi_cfrcmple>
|
|
8000e10: bf94 ite ls
|
|
8000e12: 2001 movls r0, #1
|
|
8000e14: 2000 movhi r0, #0
|
|
8000e16: f85d fb08 ldr.w pc, [sp], #8
|
|
8000e1a: bf00 nop
|
|
|
|
08000e1c <__aeabi_fcmpgt>:
|
|
8000e1c: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000e20: f7ff ffc8 bl 8000db4 <__aeabi_cfrcmple>
|
|
8000e24: bf34 ite cc
|
|
8000e26: 2001 movcc r0, #1
|
|
8000e28: 2000 movcs r0, #0
|
|
8000e2a: f85d fb08 ldr.w pc, [sp], #8
|
|
8000e2e: bf00 nop
|
|
|
|
08000e30 <__aeabi_fcmpun>:
|
|
8000e30: ea4f 0240 mov.w r2, r0, lsl #1
|
|
8000e34: ea4f 0341 mov.w r3, r1, lsl #1
|
|
8000e38: ea7f 6c22 mvns.w ip, r2, asr #24
|
|
8000e3c: d102 bne.n 8000e44 <__aeabi_fcmpun+0x14>
|
|
8000e3e: ea5f 2c40 movs.w ip, r0, lsl #9
|
|
8000e42: d108 bne.n 8000e56 <__aeabi_fcmpun+0x26>
|
|
8000e44: ea7f 6c23 mvns.w ip, r3, asr #24
|
|
8000e48: d102 bne.n 8000e50 <__aeabi_fcmpun+0x20>
|
|
8000e4a: ea5f 2c41 movs.w ip, r1, lsl #9
|
|
8000e4e: d102 bne.n 8000e56 <__aeabi_fcmpun+0x26>
|
|
8000e50: f04f 0000 mov.w r0, #0
|
|
8000e54: 4770 bx lr
|
|
8000e56: f04f 0001 mov.w r0, #1
|
|
8000e5a: 4770 bx lr
|
|
|
|
08000e5c <__aeabi_f2uiz>:
|
|
8000e5c: 0042 lsls r2, r0, #1
|
|
8000e5e: d20e bcs.n 8000e7e <__aeabi_f2uiz+0x22>
|
|
8000e60: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
|
|
8000e64: d30b bcc.n 8000e7e <__aeabi_f2uiz+0x22>
|
|
8000e66: f04f 039e mov.w r3, #158 @ 0x9e
|
|
8000e6a: ebb3 6212 subs.w r2, r3, r2, lsr #24
|
|
8000e6e: d409 bmi.n 8000e84 <__aeabi_f2uiz+0x28>
|
|
8000e70: ea4f 2300 mov.w r3, r0, lsl #8
|
|
8000e74: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000e78: fa23 f002 lsr.w r0, r3, r2
|
|
8000e7c: 4770 bx lr
|
|
8000e7e: f04f 0000 mov.w r0, #0
|
|
8000e82: 4770 bx lr
|
|
8000e84: f112 0f61 cmn.w r2, #97 @ 0x61
|
|
8000e88: d101 bne.n 8000e8e <__aeabi_f2uiz+0x32>
|
|
8000e8a: 0242 lsls r2, r0, #9
|
|
8000e8c: d102 bne.n 8000e94 <__aeabi_f2uiz+0x38>
|
|
8000e8e: f04f 30ff mov.w r0, #4294967295
|
|
8000e92: 4770 bx lr
|
|
8000e94: f04f 0000 mov.w r0, #0
|
|
8000e98: 4770 bx lr
|
|
8000e9a: bf00 nop
|
|
|
|
08000e9c <AD5934_SetRegisterValue>:
|
|
* @param numberOfBytes - Number of bytes to be written in the register
|
|
*
|
|
* @return None.
|
|
******************************************************************************/
|
|
void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
|
|
{
|
|
8000e9c: b580 push {r7, lr}
|
|
8000e9e: b086 sub sp, #24
|
|
8000ea0: af02 add r7, sp, #8
|
|
8000ea2: 4603 mov r3, r0
|
|
8000ea4: 6039 str r1, [r7, #0]
|
|
8000ea6: 71fb strb r3, [r7, #7]
|
|
8000ea8: 4613 mov r3, r2
|
|
8000eaa: 71bb strb r3, [r7, #6]
|
|
uint8_t writeData[2] = {0, 0};
|
|
8000eac: 2300 movs r3, #0
|
|
8000eae: 81bb strh r3, [r7, #12]
|
|
HAL_StatusTypeDef status;
|
|
union Bytes2Long AD5934_reg;
|
|
|
|
AD5934_reg.number = registerValue;
|
|
8000eb0: 683b ldr r3, [r7, #0]
|
|
8000eb2: 60bb str r3, [r7, #8]
|
|
|
|
for (uint8_t i = 0; i < numberOfBytes; i++)
|
|
8000eb4: 2300 movs r3, #0
|
|
8000eb6: 73fb strb r3, [r7, #15]
|
|
8000eb8: e018 b.n 8000eec <AD5934_SetRegisterValue+0x50>
|
|
{
|
|
writeData[0] = registerAddress - i;
|
|
8000eba: 79fa ldrb r2, [r7, #7]
|
|
8000ebc: 7bfb ldrb r3, [r7, #15]
|
|
8000ebe: 1ad3 subs r3, r2, r3
|
|
8000ec0: b2db uxtb r3, r3
|
|
8000ec2: 733b strb r3, [r7, #12]
|
|
writeData[1] = AD5934_reg.bytes[i];
|
|
8000ec4: 7bfb ldrb r3, [r7, #15]
|
|
8000ec6: 3310 adds r3, #16
|
|
8000ec8: 443b add r3, r7
|
|
8000eca: f813 3c08 ldrb.w r3, [r3, #-8]
|
|
8000ece: 737b strb r3, [r7, #13]
|
|
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
|
|
8000ed0: f107 020c add.w r2, r7, #12
|
|
8000ed4: 2305 movs r3, #5
|
|
8000ed6: 9300 str r3, [sp, #0]
|
|
8000ed8: 2302 movs r3, #2
|
|
8000eda: 211a movs r1, #26
|
|
8000edc: 4807 ldr r0, [pc, #28] @ (8000efc <AD5934_SetRegisterValue+0x60>)
|
|
8000ede: f002 fea3 bl 8003c28 <HAL_I2C_Master_Transmit>
|
|
8000ee2: 4603 mov r3, r0
|
|
8000ee4: 73bb strb r3, [r7, #14]
|
|
for (uint8_t i = 0; i < numberOfBytes; i++)
|
|
8000ee6: 7bfb ldrb r3, [r7, #15]
|
|
8000ee8: 3301 adds r3, #1
|
|
8000eea: 73fb strb r3, [r7, #15]
|
|
8000eec: 7bfa ldrb r2, [r7, #15]
|
|
8000eee: 79bb ldrb r3, [r7, #6]
|
|
8000ef0: 429a cmp r2, r3
|
|
8000ef2: d3e2 bcc.n 8000eba <AD5934_SetRegisterValue+0x1e>
|
|
}
|
|
|
|
return;
|
|
8000ef4: bf00 nop
|
|
|
|
}
|
|
8000ef6: 3710 adds r7, #16
|
|
8000ef8: 46bd mov sp, r7
|
|
8000efa: bd80 pop {r7, pc}
|
|
8000efc: 20000678 .word 0x20000678
|
|
|
|
08000f00 <AD5934_GetRegisterValue>:
|
|
* @param numberOfBytes - Number of bytes to be read from the register.
|
|
*
|
|
* @return Register value.
|
|
******************************************************************************/
|
|
uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
|
|
{
|
|
8000f00: b580 push {r7, lr}
|
|
8000f02: b088 sub sp, #32
|
|
8000f04: af02 add r7, sp, #8
|
|
8000f06: 4603 mov r3, r0
|
|
8000f08: 460a mov r2, r1
|
|
8000f0a: 71fb strb r3, [r7, #7]
|
|
8000f0c: 4613 mov r3, r2
|
|
8000f0e: 71bb strb r3, [r7, #6]
|
|
uint8_t readData[1] = {0};
|
|
8000f10: 2300 movs r3, #0
|
|
8000f12: 753b strb r3, [r7, #20]
|
|
uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
|
|
union Bytes2Long AD5934_reg;
|
|
HAL_StatusTypeDef status;
|
|
|
|
if(numberOfBytes > 4)
|
|
8000f14: 79bb ldrb r3, [r7, #6]
|
|
8000f16: 2b04 cmp r3, #4
|
|
8000f18: d902 bls.n 8000f20 <AD5934_GetRegisterValue+0x20>
|
|
return 0xFFFFFFFF; //Overflow
|
|
8000f1a: f04f 33ff mov.w r3, #4294967295
|
|
8000f1e: e031 b.n 8000f84 <AD5934_GetRegisterValue+0x84>
|
|
|
|
AD5934_reg.number = 0;
|
|
8000f20: 2300 movs r3, #0
|
|
8000f22: 60fb str r3, [r7, #12]
|
|
for (uint8_t i = 0; i < numberOfBytes; i++)
|
|
8000f24: 2300 movs r3, #0
|
|
8000f26: 75fb strb r3, [r7, #23]
|
|
8000f28: e027 b.n 8000f7a <AD5934_GetRegisterValue+0x7a>
|
|
{
|
|
writeData[0] = AD5934_ADDR_POINTER;
|
|
8000f2a: 23b0 movs r3, #176 @ 0xb0
|
|
8000f2c: 743b strb r3, [r7, #16]
|
|
writeData[1] = registerAddress - i;
|
|
8000f2e: 79fa ldrb r2, [r7, #7]
|
|
8000f30: 7dfb ldrb r3, [r7, #23]
|
|
8000f32: 1ad3 subs r3, r2, r3
|
|
8000f34: b2db uxtb r3, r3
|
|
8000f36: 747b strb r3, [r7, #17]
|
|
status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
|
|
8000f38: f107 0210 add.w r2, r7, #16
|
|
8000f3c: 2305 movs r3, #5
|
|
8000f3e: 9300 str r3, [sp, #0]
|
|
8000f40: 2302 movs r3, #2
|
|
8000f42: 211a movs r1, #26
|
|
8000f44: 4811 ldr r0, [pc, #68] @ (8000f8c <AD5934_GetRegisterValue+0x8c>)
|
|
8000f46: f002 fe6f bl 8003c28 <HAL_I2C_Master_Transmit>
|
|
8000f4a: 4603 mov r3, r0
|
|
8000f4c: 75bb strb r3, [r7, #22]
|
|
|
|
//HAL_Delay(1);
|
|
readData[0] = 0;
|
|
8000f4e: 2300 movs r3, #0
|
|
8000f50: 753b strb r3, [r7, #20]
|
|
status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
|
|
8000f52: f107 0214 add.w r2, r7, #20
|
|
8000f56: 2305 movs r3, #5
|
|
8000f58: 9300 str r3, [sp, #0]
|
|
8000f5a: 2301 movs r3, #1
|
|
8000f5c: 211a movs r1, #26
|
|
8000f5e: 480b ldr r0, [pc, #44] @ (8000f8c <AD5934_GetRegisterValue+0x8c>)
|
|
8000f60: f002 ff60 bl 8003e24 <HAL_I2C_Master_Receive>
|
|
8000f64: 4603 mov r3, r0
|
|
8000f66: 75bb strb r3, [r7, #22]
|
|
AD5934_reg.bytes[i]=readData[0];
|
|
8000f68: 7dfb ldrb r3, [r7, #23]
|
|
8000f6a: 7d3a ldrb r2, [r7, #20]
|
|
8000f6c: 3318 adds r3, #24
|
|
8000f6e: 443b add r3, r7
|
|
8000f70: f803 2c0c strb.w r2, [r3, #-12]
|
|
for (uint8_t i = 0; i < numberOfBytes; i++)
|
|
8000f74: 7dfb ldrb r3, [r7, #23]
|
|
8000f76: 3301 adds r3, #1
|
|
8000f78: 75fb strb r3, [r7, #23]
|
|
8000f7a: 7dfa ldrb r2, [r7, #23]
|
|
8000f7c: 79bb ldrb r3, [r7, #6]
|
|
8000f7e: 429a cmp r2, r3
|
|
8000f80: d3d3 bcc.n 8000f2a <AD5934_GetRegisterValue+0x2a>
|
|
/*
|
|
AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048;
|
|
AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048;
|
|
*/
|
|
|
|
return AD5934_reg.number;
|
|
8000f82: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000f84: 4618 mov r0, r3
|
|
8000f86: 3718 adds r7, #24
|
|
8000f88: 46bd mov sp, r7
|
|
8000f8a: bd80 pop {r7, pc}
|
|
8000f8c: 20000678 .word 0x20000678
|
|
|
|
08000f90 <AD5934_Init>:
|
|
* @param None.
|
|
*
|
|
* @return None.
|
|
******************************************************************************/
|
|
void AD5934_Init(void)
|
|
{
|
|
8000f90: b580 push {r7, lr}
|
|
8000f92: af00 add r7, sp, #0
|
|
|
|
ADG715_ResetChannels(); // Disconnects Analog Switch on the CE / RTD / Ref Resistor
|
|
8000f94: f000 fbbc bl 8001710 <ADG715_ResetChannels>
|
|
|
|
/************ Config Sweep******************/
|
|
|
|
// Place AD5934 in reset
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
|
|
8000f98: 2201 movs r2, #1
|
|
8000f9a: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000f9e: 2081 movs r0, #129 @ 0x81
|
|
8000fa0: f7ff ff7c bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Configure starting frequency
|
|
AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_2K5HZ, 3);
|
|
8000fa4: 2203 movs r2, #3
|
|
8000fa6: 490a ldr r1, [pc, #40] @ (8000fd0 <AD5934_Init+0x40>)
|
|
8000fa8: 2084 movs r0, #132 @ 0x84
|
|
8000faa: f7ff ff77 bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Configure frequency increment step
|
|
AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
|
|
8000fae: 2203 movs r2, #3
|
|
8000fb0: 2100 movs r1, #0
|
|
8000fb2: 2087 movs r0, #135 @ 0x87
|
|
8000fb4: f7ff ff72 bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Configure number of steps
|
|
AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
|
|
8000fb8: 2202 movs r2, #2
|
|
8000fba: 2100 movs r1, #0
|
|
8000fbc: 2089 movs r0, #137 @ 0x89
|
|
8000fbe: f7ff ff6d bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Set 128 Settling Time
|
|
AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_64, 2);
|
|
8000fc2: 2202 movs r2, #2
|
|
8000fc4: 2140 movs r1, #64 @ 0x40
|
|
8000fc6: 208b movs r0, #139 @ 0x8b
|
|
8000fc8: f7ff ff68 bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
}
|
|
8000fcc: bf00 nop
|
|
8000fce: bd80 pop {r7, pc}
|
|
8000fd0: 0051eb86 .word 0x0051eb86
|
|
|
|
08000fd4 <AD5934_RestartSweep>:
|
|
* @param None.
|
|
*
|
|
* @return None.
|
|
******************************************************************************/
|
|
void AD5934_RestartSweep(void)
|
|
{
|
|
8000fd4: b580 push {r7, lr}
|
|
8000fd6: af00 add r7, sp, #0
|
|
// Place AD5934 in standby
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
8000fd8: 2201 movs r2, #1
|
|
8000fda: 21b5 movs r1, #181 @ 0xb5
|
|
8000fdc: 2080 movs r0, #128 @ 0x80
|
|
8000fde: f7ff ff5d bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Initialize starting frequency, Start frequency sweep, standby
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
8000fe2: 2201 movs r2, #1
|
|
8000fe4: 2115 movs r1, #21
|
|
8000fe6: 2080 movs r0, #128 @ 0x80
|
|
8000fe8: f7ff ff58 bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Disable Internal Reset State
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, AD5934_CONTROL_FUNCTION(AD5934_RESERVED), 1);
|
|
8000fec: 2201 movs r2, #1
|
|
8000fee: 2180 movs r1, #128 @ 0x80
|
|
8000ff0: 2081 movs r0, #129 @ 0x81
|
|
8000ff2: f7ff ff53 bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
// Configure Range Output, PGA gain andPlace AD5934 in sweep
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
8000ff6: 2201 movs r2, #1
|
|
8000ff8: 2125 movs r1, #37 @ 0x25
|
|
8000ffa: 2080 movs r0, #128 @ 0x80
|
|
8000ffc: f7ff ff4e bl 8000e9c <AD5934_SetRegisterValue>
|
|
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
|
|
// Place AD5934 in standby (instead of power down)
|
|
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
|
|
}
|
|
8001000: bf00 nop
|
|
8001002: bd80 pop {r7, pc}
|
|
|
|
08001004 <AD5934_Repeat_Sweep>:
|
|
* @param None.
|
|
*
|
|
* @return none.
|
|
******************************************************************************/
|
|
void AD5934_Repeat_Sweep(void)
|
|
{
|
|
8001004: b580 push {r7, lr}
|
|
8001006: af00 add r7, sp, #0
|
|
// Repeat AD5934 Sweep
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_REPEAT_FREQ) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
8001008: 2201 movs r2, #1
|
|
800100a: 2145 movs r1, #69 @ 0x45
|
|
800100c: 2080 movs r0, #128 @ 0x80
|
|
800100e: f7ff ff45 bl 8000e9c <AD5934_SetRegisterValue>
|
|
}
|
|
8001012: bf00 nop
|
|
8001014: bd80 pop {r7, pc}
|
|
|
|
08001016 <AD5934_StopSweep>:
|
|
* @param None.
|
|
*
|
|
* @return None.
|
|
******************************************************************************/
|
|
void AD5934_StopSweep(void)
|
|
{
|
|
8001016: b580 push {r7, lr}
|
|
8001018: af00 add r7, sp, #0
|
|
// Power Down
|
|
//AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
|
|
// Place AD5934 in standby (instead of power down to save startup time)
|
|
AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X1)), 1);
|
|
800101a: 2201 movs r2, #1
|
|
800101c: 21b5 movs r1, #181 @ 0xb5
|
|
800101e: 2080 movs r0, #128 @ 0x80
|
|
8001020: f7ff ff3c bl 8000e9c <AD5934_SetRegisterValue>
|
|
|
|
}
|
|
8001024: bf00 nop
|
|
8001026: bd80 pop {r7, pc}
|
|
|
|
08001028 <AD5934_GetMagnitude>:
|
|
* @param: none
|
|
*
|
|
* @return Magnitude (float).
|
|
******************************************************************************/
|
|
float AD5934_GetMagnitude(void)
|
|
{
|
|
8001028: b5b0 push {r4, r5, r7, lr}
|
|
800102a: b082 sub sp, #8
|
|
800102c: af00 add r7, sp, #0
|
|
|
|
// Get Real Data register
|
|
int16_t real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2)));
|
|
800102e: 2102 movs r1, #2
|
|
8001030: 2095 movs r0, #149 @ 0x95
|
|
8001032: f7ff ff65 bl 8000f00 <AD5934_GetRegisterValue>
|
|
8001036: 4603 mov r3, r0
|
|
8001038: 80fb strh r3, [r7, #6]
|
|
|
|
// Get Imaginary Data register
|
|
int16_t imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2)));
|
|
800103a: 2102 movs r1, #2
|
|
800103c: 2097 movs r0, #151 @ 0x97
|
|
800103e: f7ff ff5f bl 8000f00 <AD5934_GetRegisterValue>
|
|
8001042: 4603 mov r3, r0
|
|
8001044: 80bb strh r3, [r7, #4]
|
|
|
|
// Calculate Magnitude using float function sqrtf
|
|
float magnitude = sqrtf(((float)real_value * (float)real_value) + ((float)imag_value * (float)imag_value));
|
|
8001046: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800104a: 4618 mov r0, r3
|
|
800104c: f7ff fcd6 bl 80009fc <__aeabi_i2f>
|
|
8001050: 4604 mov r4, r0
|
|
8001052: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
8001056: 4618 mov r0, r3
|
|
8001058: f7ff fcd0 bl 80009fc <__aeabi_i2f>
|
|
800105c: 4603 mov r3, r0
|
|
800105e: 4619 mov r1, r3
|
|
8001060: 4620 mov r0, r4
|
|
8001062: f7ff fd1f bl 8000aa4 <__aeabi_fmul>
|
|
8001066: 4603 mov r3, r0
|
|
8001068: 461d mov r5, r3
|
|
800106a: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
800106e: 4618 mov r0, r3
|
|
8001070: f7ff fcc4 bl 80009fc <__aeabi_i2f>
|
|
8001074: 4604 mov r4, r0
|
|
8001076: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
800107a: 4618 mov r0, r3
|
|
800107c: f7ff fcbe bl 80009fc <__aeabi_i2f>
|
|
8001080: 4603 mov r3, r0
|
|
8001082: 4619 mov r1, r3
|
|
8001084: 4620 mov r0, r4
|
|
8001086: f7ff fd0d bl 8000aa4 <__aeabi_fmul>
|
|
800108a: 4603 mov r3, r0
|
|
800108c: 4619 mov r1, r3
|
|
800108e: 4628 mov r0, r5
|
|
8001090: f7ff fc00 bl 8000894 <__addsf3>
|
|
8001094: 4603 mov r3, r0
|
|
8001096: 4618 mov r0, r3
|
|
8001098: f005 fbc6 bl 8006828 <sqrtf>
|
|
800109c: 6038 str r0, [r7, #0]
|
|
|
|
// Return magnitude value
|
|
return (magnitude);
|
|
800109e: 683b ldr r3, [r7, #0]
|
|
}
|
|
80010a0: 4618 mov r0, r3
|
|
80010a2: 3708 adds r7, #8
|
|
80010a4: 46bd mov sp, r7
|
|
80010a6: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
080010a8 <AD5934_Compress_To_IntScale>:
|
|
* @param scale Escala de Ref Res, EC e RTD
|
|
*
|
|
* @return uint16_t Valor convertido na escala de UINT16_MIN a UINT16_MAX
|
|
*/
|
|
uint16_t AD5934_Compress_To_IntScale(float value, uint8_t scale)
|
|
{
|
|
80010a8: b5b0 push {r4, r5, r7, lr}
|
|
80010aa: b084 sub sp, #16
|
|
80010ac: af00 add r7, sp, #0
|
|
80010ae: 6078 str r0, [r7, #4]
|
|
80010b0: 460b mov r3, r1
|
|
80010b2: 70fb strb r3, [r7, #3]
|
|
// Proteção contra índice inválido para evitar HardFault
|
|
if (scale >= AD5934_CH_MAX)
|
|
80010b4: 78fb ldrb r3, [r7, #3]
|
|
80010b6: 2b0e cmp r3, #14
|
|
80010b8: d901 bls.n 80010be <AD5934_Compress_To_IntScale+0x16>
|
|
return 0;
|
|
80010ba: 2300 movs r3, #0
|
|
80010bc: e076 b.n 80011ac <AD5934_Compress_To_IntScale+0x104>
|
|
|
|
// Verifica limites do valor de entrada
|
|
if (value < AD5934_Scale_Float_Min[scale])
|
|
80010be: 78fb ldrb r3, [r7, #3]
|
|
80010c0: 4a3c ldr r2, [pc, #240] @ (80011b4 <AD5934_Compress_To_IntScale+0x10c>)
|
|
80010c2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80010c6: 4619 mov r1, r3
|
|
80010c8: 6878 ldr r0, [r7, #4]
|
|
80010ca: f7ff fe89 bl 8000de0 <__aeabi_fcmplt>
|
|
80010ce: 4603 mov r3, r0
|
|
80010d0: 2b00 cmp r3, #0
|
|
80010d2: d004 beq.n 80010de <AD5934_Compress_To_IntScale+0x36>
|
|
return AD5934_Scale_Out_Min[scale];
|
|
80010d4: 78fb ldrb r3, [r7, #3]
|
|
80010d6: 4a38 ldr r2, [pc, #224] @ (80011b8 <AD5934_Compress_To_IntScale+0x110>)
|
|
80010d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
80010dc: e066 b.n 80011ac <AD5934_Compress_To_IntScale+0x104>
|
|
else if (value > AD5934_Scale_Float_Max[scale])
|
|
80010de: 78fb ldrb r3, [r7, #3]
|
|
80010e0: 4a36 ldr r2, [pc, #216] @ (80011bc <AD5934_Compress_To_IntScale+0x114>)
|
|
80010e2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80010e6: 4619 mov r1, r3
|
|
80010e8: 6878 ldr r0, [r7, #4]
|
|
80010ea: f7ff fe97 bl 8000e1c <__aeabi_fcmpgt>
|
|
80010ee: 4603 mov r3, r0
|
|
80010f0: 2b00 cmp r3, #0
|
|
80010f2: d004 beq.n 80010fe <AD5934_Compress_To_IntScale+0x56>
|
|
return AD5934_Scale_Out_Max[scale];
|
|
80010f4: 78fb ldrb r3, [r7, #3]
|
|
80010f6: 4a32 ldr r2, [pc, #200] @ (80011c0 <AD5934_Compress_To_IntScale+0x118>)
|
|
80010f8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
80010fc: e056 b.n 80011ac <AD5934_Compress_To_IntScale+0x104>
|
|
|
|
// Converte o valor usando a fórmula: ((value - FLOAT_MIN) / (FLOAT_MAX - FLOAT_MIN)) * (UINT16_MAX - UINT16_MIN) + UINT16_MIN
|
|
uint16_t result = (uint16_t)(((value - AD5934_Scale_Float_Min[scale]) / (AD5934_Scale_Float_Max[scale] - AD5934_Scale_Float_Min[scale])) * ((float)AD5934_Scale_Out_Max[scale] - (float)AD5934_Scale_Out_Min[scale]) + (float)AD5934_Scale_Out_Min[scale]);
|
|
80010fe: 78fb ldrb r3, [r7, #3]
|
|
8001100: 4a2c ldr r2, [pc, #176] @ (80011b4 <AD5934_Compress_To_IntScale+0x10c>)
|
|
8001102: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001106: 4619 mov r1, r3
|
|
8001108: 6878 ldr r0, [r7, #4]
|
|
800110a: f7ff fbc1 bl 8000890 <__aeabi_fsub>
|
|
800110e: 4603 mov r3, r0
|
|
8001110: 461c mov r4, r3
|
|
8001112: 78fb ldrb r3, [r7, #3]
|
|
8001114: 4a29 ldr r2, [pc, #164] @ (80011bc <AD5934_Compress_To_IntScale+0x114>)
|
|
8001116: f852 2023 ldr.w r2, [r2, r3, lsl #2]
|
|
800111a: 78fb ldrb r3, [r7, #3]
|
|
800111c: 4925 ldr r1, [pc, #148] @ (80011b4 <AD5934_Compress_To_IntScale+0x10c>)
|
|
800111e: f851 3023 ldr.w r3, [r1, r3, lsl #2]
|
|
8001122: 4619 mov r1, r3
|
|
8001124: 4610 mov r0, r2
|
|
8001126: f7ff fbb3 bl 8000890 <__aeabi_fsub>
|
|
800112a: 4603 mov r3, r0
|
|
800112c: 4619 mov r1, r3
|
|
800112e: 4620 mov r0, r4
|
|
8001130: f7ff fd6c bl 8000c0c <__aeabi_fdiv>
|
|
8001134: 4603 mov r3, r0
|
|
8001136: 461d mov r5, r3
|
|
8001138: 78fb ldrb r3, [r7, #3]
|
|
800113a: 4a21 ldr r2, [pc, #132] @ (80011c0 <AD5934_Compress_To_IntScale+0x118>)
|
|
800113c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8001140: 4618 mov r0, r3
|
|
8001142: f7ff fc57 bl 80009f4 <__aeabi_ui2f>
|
|
8001146: 4604 mov r4, r0
|
|
8001148: 78fb ldrb r3, [r7, #3]
|
|
800114a: 4a1b ldr r2, [pc, #108] @ (80011b8 <AD5934_Compress_To_IntScale+0x110>)
|
|
800114c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8001150: 4618 mov r0, r3
|
|
8001152: f7ff fc4f bl 80009f4 <__aeabi_ui2f>
|
|
8001156: 4603 mov r3, r0
|
|
8001158: 4619 mov r1, r3
|
|
800115a: 4620 mov r0, r4
|
|
800115c: f7ff fb98 bl 8000890 <__aeabi_fsub>
|
|
8001160: 4603 mov r3, r0
|
|
8001162: 4619 mov r1, r3
|
|
8001164: 4628 mov r0, r5
|
|
8001166: f7ff fc9d bl 8000aa4 <__aeabi_fmul>
|
|
800116a: 4603 mov r3, r0
|
|
800116c: 461c mov r4, r3
|
|
800116e: 78fb ldrb r3, [r7, #3]
|
|
8001170: 4a11 ldr r2, [pc, #68] @ (80011b8 <AD5934_Compress_To_IntScale+0x110>)
|
|
8001172: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8001176: 4618 mov r0, r3
|
|
8001178: f7ff fc3c bl 80009f4 <__aeabi_ui2f>
|
|
800117c: 4603 mov r3, r0
|
|
800117e: 4619 mov r1, r3
|
|
8001180: 4620 mov r0, r4
|
|
8001182: f7ff fb87 bl 8000894 <__addsf3>
|
|
8001186: 4603 mov r3, r0
|
|
8001188: 4618 mov r0, r3
|
|
800118a: f7ff fe67 bl 8000e5c <__aeabi_f2uiz>
|
|
800118e: 4603 mov r3, r0
|
|
8001190: 81fb strh r3, [r7, #14]
|
|
|
|
// Garante que o resultado não exceda o limite superior
|
|
if (result > AD5934_Scale_Out_Max[scale])
|
|
8001192: 78fb ldrb r3, [r7, #3]
|
|
8001194: 4a0a ldr r2, [pc, #40] @ (80011c0 <AD5934_Compress_To_IntScale+0x118>)
|
|
8001196: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
800119a: 89fa ldrh r2, [r7, #14]
|
|
800119c: 429a cmp r2, r3
|
|
800119e: d904 bls.n 80011aa <AD5934_Compress_To_IntScale+0x102>
|
|
return (AD5934_Scale_Out_Max[scale]);
|
|
80011a0: 78fb ldrb r3, [r7, #3]
|
|
80011a2: 4a07 ldr r2, [pc, #28] @ (80011c0 <AD5934_Compress_To_IntScale+0x118>)
|
|
80011a4: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
80011a8: e000 b.n 80011ac <AD5934_Compress_To_IntScale+0x104>
|
|
|
|
return result;
|
|
80011aa: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
80011ac: 4618 mov r0, r3
|
|
80011ae: 3710 adds r7, #16
|
|
80011b0: 46bd mov sp, r7
|
|
80011b2: bdb0 pop {r4, r5, r7, pc}
|
|
80011b4: 08006970 .word 0x08006970
|
|
80011b8: 080069e8 .word 0x080069e8
|
|
80011bc: 080069ac .word 0x080069ac
|
|
80011c0: 08006a08 .word 0x08006a08
|
|
|
|
080011c4 <AD5934_Process_System>:
|
|
return calibration_factor;
|
|
}
|
|
|
|
|
|
void AD5934_Process_System(void)
|
|
{
|
|
80011c4: b580 push {r7, lr}
|
|
80011c6: b082 sub sp, #8
|
|
80011c8: af00 add r7, sp, #0
|
|
static uint32_t state_timer = 0;
|
|
uint8_t status = 0;
|
|
80011ca: 2300 movs r3, #0
|
|
80011cc: 71fb strb r3, [r7, #7]
|
|
|
|
switch (ad5934_state)
|
|
80011ce: 4b79 ldr r3, [pc, #484] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
80011d0: 781b ldrb r3, [r3, #0]
|
|
80011d2: b2db uxtb r3, r3
|
|
80011d4: 2b06 cmp r3, #6
|
|
80011d6: f200 80e9 bhi.w 80013ac <AD5934_Process_System+0x1e8>
|
|
80011da: a201 add r2, pc, #4 @ (adr r2, 80011e0 <AD5934_Process_System+0x1c>)
|
|
80011dc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80011e0: 080011fd .word 0x080011fd
|
|
80011e4: 0800123b .word 0x0800123b
|
|
80011e8: 08001263 .word 0x08001263
|
|
80011ec: 08001283 .word 0x08001283
|
|
80011f0: 080012db .word 0x080012db
|
|
80011f4: 080012f1 .word 0x080012f1
|
|
80011f8: 0800121d .word 0x0800121d
|
|
{
|
|
case AD5934_IDLE:
|
|
ADG715_Update(current_mux_channel); // Starts changing the mux channel
|
|
80011fc: 4b6e ldr r3, [pc, #440] @ (80013b8 <AD5934_Process_System+0x1f4>)
|
|
80011fe: 781b ldrb r3, [r3, #0]
|
|
8001200: 4618 mov r0, r3
|
|
8001202: f000 fa8d bl 8001720 <ADG715_Update>
|
|
is_new_channel = 1; // Forces first channel
|
|
8001206: 4b6d ldr r3, [pc, #436] @ (80013bc <AD5934_Process_System+0x1f8>)
|
|
8001208: 2201 movs r2, #1
|
|
800120a: 701a strb r2, [r3, #0]
|
|
state_timer = g_ms_counter;
|
|
800120c: 4b6c ldr r3, [pc, #432] @ (80013c0 <AD5934_Process_System+0x1fc>)
|
|
800120e: 681b ldr r3, [r3, #0]
|
|
8001210: 4a6c ldr r2, [pc, #432] @ (80013c4 <AD5934_Process_System+0x200>)
|
|
8001212: 6013 str r3, [r2, #0]
|
|
ad5934_state = AD5934_WAIT_MUX;
|
|
8001214: 4b67 ldr r3, [pc, #412] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
8001216: 2206 movs r2, #6
|
|
8001218: 701a strb r2, [r3, #0]
|
|
break;
|
|
800121a: e0c7 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
|
|
case AD5934_WAIT_MUX:
|
|
if ((g_ms_counter - state_timer) >= AD5934_SYNC_MUX_SETTLING) // Wait until AD715 Mux switch stability
|
|
800121c: 4b68 ldr r3, [pc, #416] @ (80013c0 <AD5934_Process_System+0x1fc>)
|
|
800121e: 681a ldr r2, [r3, #0]
|
|
8001220: 4b68 ldr r3, [pc, #416] @ (80013c4 <AD5934_Process_System+0x200>)
|
|
8001222: 681b ldr r3, [r3, #0]
|
|
8001224: 1ad3 subs r3, r2, r3
|
|
8001226: 2b04 cmp r3, #4
|
|
8001228: f240 80bb bls.w 80013a2 <AD5934_Process_System+0x1de>
|
|
{
|
|
sweep_count = 0;
|
|
800122c: 4b66 ldr r3, [pc, #408] @ (80013c8 <AD5934_Process_System+0x204>)
|
|
800122e: 2200 movs r2, #0
|
|
8001230: 701a strb r2, [r3, #0]
|
|
ad5934_state = AD5934_START_CONVERSION;
|
|
8001232: 4b60 ldr r3, [pc, #384] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
8001234: 2201 movs r2, #1
|
|
8001236: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
8001238: e0b3 b.n 80013a2 <AD5934_Process_System+0x1de>
|
|
|
|
case AD5934_START_CONVERSION:
|
|
state_timer = g_ms_counter; // Starts to count the Burst period for the sweeps
|
|
800123a: 4b61 ldr r3, [pc, #388] @ (80013c0 <AD5934_Process_System+0x1fc>)
|
|
800123c: 681b ldr r3, [r3, #0]
|
|
800123e: 4a61 ldr r2, [pc, #388] @ (80013c4 <AD5934_Process_System+0x200>)
|
|
8001240: 6013 str r3, [r2, #0]
|
|
|
|
/* DECISÃO DE COMANDO: Novo canal vs Leituras sucessivas */
|
|
if (is_new_channel) // Decision: Channel Switched or Next Sample in the Burst ?
|
|
8001242: 4b5e ldr r3, [pc, #376] @ (80013bc <AD5934_Process_System+0x1f8>)
|
|
8001244: 781b ldrb r3, [r3, #0]
|
|
8001246: 2b00 cmp r3, #0
|
|
8001248: d005 beq.n 8001256 <AD5934_Process_System+0x92>
|
|
{
|
|
AD5934_RestartSweep(); // Clean some AD5934 internal registers to Re-Start Sweep
|
|
800124a: f7ff fec3 bl 8000fd4 <AD5934_RestartSweep>
|
|
is_new_channel = 0; // Resets the flag to read the next Sample Burst
|
|
800124e: 4b5b ldr r3, [pc, #364] @ (80013bc <AD5934_Process_System+0x1f8>)
|
|
8001250: 2200 movs r2, #0
|
|
8001252: 701a strb r2, [r3, #0]
|
|
8001254: e001 b.n 800125a <AD5934_Process_System+0x96>
|
|
}
|
|
else
|
|
{
|
|
AD5934_Repeat_Sweep(); // Get Sample and just repeat reading
|
|
8001256: f7ff fed5 bl 8001004 <AD5934_Repeat_Sweep>
|
|
}
|
|
|
|
ad5934_state = AD5934_WAIT_CONVERSION; // Next State
|
|
800125a: 4b56 ldr r3, [pc, #344] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
800125c: 2202 movs r2, #2
|
|
800125e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001260: e0a4 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
|
|
case AD5934_WAIT_CONVERSION:
|
|
status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1); // Check if the current converion is ready in the AD5934
|
|
8001262: 2101 movs r1, #1
|
|
8001264: 208f movs r0, #143 @ 0x8f
|
|
8001266: f7ff fe4b bl 8000f00 <AD5934_GetRegisterValue>
|
|
800126a: 4603 mov r3, r0
|
|
800126c: 71fb strb r3, [r7, #7]
|
|
if ((status & AD5934_STATUS_DATA_VALID) != 0)
|
|
800126e: 79fb ldrb r3, [r7, #7]
|
|
8001270: f003 0302 and.w r3, r3, #2
|
|
8001274: 2b00 cmp r3, #0
|
|
8001276: f000 8096 beq.w 80013a6 <AD5934_Process_System+0x1e2>
|
|
{
|
|
ad5934_state = AD5934_READ_DATA;
|
|
800127a: 4b4e ldr r3, [pc, #312] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
800127c: 2203 movs r2, #3
|
|
800127e: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
8001280: e091 b.n 80013a6 <AD5934_Process_System+0x1e2>
|
|
|
|
case AD5934_READ_DATA:
|
|
{
|
|
float magnitude = AD5934_GetMagnitude();
|
|
8001282: f7ff fed1 bl 8001028 <AD5934_GetMagnitude>
|
|
8001286: 6038 str r0, [r7, #0]
|
|
|
|
switch (current_mux_channel)
|
|
8001288: 4b4b ldr r3, [pc, #300] @ (80013b8 <AD5934_Process_System+0x1f4>)
|
|
800128a: 781b ldrb r3, [r3, #0]
|
|
800128c: 2b02 cmp r3, #2
|
|
800128e: d00e beq.n 80012ae <AD5934_Process_System+0xea>
|
|
8001290: 2b02 cmp r3, #2
|
|
8001292: dc10 bgt.n 80012b6 <AD5934_Process_System+0xf2>
|
|
8001294: 2b00 cmp r3, #0
|
|
8001296: d002 beq.n 800129e <AD5934_Process_System+0xda>
|
|
8001298: 2b01 cmp r3, #1
|
|
800129a: d004 beq.n 80012a6 <AD5934_Process_System+0xe2>
|
|
800129c: e00b b.n 80012b6 <AD5934_Process_System+0xf2>
|
|
{
|
|
case AD5934_ID_RTD:
|
|
AD5934_RTD_NewSample(magnitude);
|
|
800129e: 6838 ldr r0, [r7, #0]
|
|
80012a0: f000 f9f4 bl 800168c <AD5934_RTD_NewSample>
|
|
break;
|
|
80012a4: e007 b.n 80012b6 <AD5934_Process_System+0xf2>
|
|
|
|
case AD5934_ID_EC:
|
|
AD5934_EC_NewSample(magnitude);
|
|
80012a6: 6838 ldr r0, [r7, #0]
|
|
80012a8: f000 f9fe bl 80016a8 <AD5934_EC_NewSample>
|
|
break;
|
|
80012ac: e003 b.n 80012b6 <AD5934_Process_System+0xf2>
|
|
|
|
case AD5934_ID_REF:
|
|
AD5934_Reference_NewSample(magnitude);
|
|
80012ae: 6838 ldr r0, [r7, #0]
|
|
80012b0: f000 fa08 bl 80016c4 <AD5934_Reference_NewSample>
|
|
break;
|
|
80012b4: bf00 nop
|
|
}
|
|
|
|
sweep_count++;
|
|
80012b6: 4b44 ldr r3, [pc, #272] @ (80013c8 <AD5934_Process_System+0x204>)
|
|
80012b8: 781b ldrb r3, [r3, #0]
|
|
80012ba: 3301 adds r3, #1
|
|
80012bc: b2da uxtb r2, r3
|
|
80012be: 4b42 ldr r3, [pc, #264] @ (80013c8 <AD5934_Process_System+0x204>)
|
|
80012c0: 701a strb r2, [r3, #0]
|
|
|
|
if (sweep_count >= AD5934_BURST_SIZE) // Check if number of samples for the burst is complete
|
|
80012c2: 4b41 ldr r3, [pc, #260] @ (80013c8 <AD5934_Process_System+0x204>)
|
|
80012c4: 781b ldrb r3, [r3, #0]
|
|
80012c6: 2b04 cmp r3, #4
|
|
80012c8: d903 bls.n 80012d2 <AD5934_Process_System+0x10e>
|
|
{
|
|
ad5934_state = AD5934_SWITCH_MUX; // Next Re-Start Sweep
|
|
80012ca: 4b3a ldr r3, [pc, #232] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
80012cc: 2205 movs r2, #5
|
|
80012ce: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
ad5934_state = AD5934_WAIT_NEXT_SWEEP; // Next Repeat Sweep
|
|
}
|
|
}
|
|
break;
|
|
80012d0: e06c b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
ad5934_state = AD5934_WAIT_NEXT_SWEEP; // Next Repeat Sweep
|
|
80012d2: 4b38 ldr r3, [pc, #224] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
80012d4: 2204 movs r2, #4
|
|
80012d6: 701a strb r2, [r3, #0]
|
|
break;
|
|
80012d8: e068 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
|
|
case AD5934_WAIT_NEXT_SWEEP:
|
|
if ((g_ms_counter - state_timer) >= AD5934_TIME_PER_SWEEP)
|
|
80012da: 4b39 ldr r3, [pc, #228] @ (80013c0 <AD5934_Process_System+0x1fc>)
|
|
80012dc: 681a ldr r2, [r3, #0]
|
|
80012de: 4b39 ldr r3, [pc, #228] @ (80013c4 <AD5934_Process_System+0x200>)
|
|
80012e0: 681b ldr r3, [r3, #0]
|
|
80012e2: 1ad3 subs r3, r2, r3
|
|
80012e4: 2b3b cmp r3, #59 @ 0x3b
|
|
80012e6: d960 bls.n 80013aa <AD5934_Process_System+0x1e6>
|
|
{
|
|
ad5934_state = AD5934_START_CONVERSION;
|
|
80012e8: 4b32 ldr r3, [pc, #200] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
80012ea: 2201 movs r2, #1
|
|
80012ec: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
80012ee: e05c b.n 80013aa <AD5934_Process_System+0x1e6>
|
|
|
|
case AD5934_SWITCH_MUX:
|
|
AD5934_StopSweep(); // Put AD5934 in Standby
|
|
80012f0: f7ff fe91 bl 8001016 <AD5934_StopSweep>
|
|
current_mux_channel = (uint8_t)((current_mux_channel + 1) % 3); // Pointer to the next channel (Circular Buffer 0 to 2)
|
|
80012f4: 4b30 ldr r3, [pc, #192] @ (80013b8 <AD5934_Process_System+0x1f4>)
|
|
80012f6: 781b ldrb r3, [r3, #0]
|
|
80012f8: 1c5a adds r2, r3, #1
|
|
80012fa: 4b34 ldr r3, [pc, #208] @ (80013cc <AD5934_Process_System+0x208>)
|
|
80012fc: fb83 3102 smull r3, r1, r3, r2
|
|
8001300: 17d3 asrs r3, r2, #31
|
|
8001302: 1ac9 subs r1, r1, r3
|
|
8001304: 460b mov r3, r1
|
|
8001306: 005b lsls r3, r3, #1
|
|
8001308: 440b add r3, r1
|
|
800130a: 1ad1 subs r1, r2, r3
|
|
800130c: b2ca uxtb r2, r1
|
|
800130e: 4b2a ldr r3, [pc, #168] @ (80013b8 <AD5934_Process_System+0x1f4>)
|
|
8001310: 701a strb r2, [r3, #0]
|
|
switch (current_mux_channel)
|
|
8001312: 4b29 ldr r3, [pc, #164] @ (80013b8 <AD5934_Process_System+0x1f4>)
|
|
8001314: 781b ldrb r3, [r3, #0]
|
|
8001316: 2b02 cmp r3, #2
|
|
8001318: d024 beq.n 8001364 <AD5934_Process_System+0x1a0>
|
|
800131a: 2b02 cmp r3, #2
|
|
800131c: dc31 bgt.n 8001382 <AD5934_Process_System+0x1be>
|
|
800131e: 2b00 cmp r3, #0
|
|
8001320: d002 beq.n 8001328 <AD5934_Process_System+0x164>
|
|
8001322: 2b01 cmp r3, #1
|
|
8001324: d00f beq.n 8001346 <AD5934_Process_System+0x182>
|
|
8001326: e02c b.n 8001382 <AD5934_Process_System+0x1be>
|
|
{
|
|
case AD5934_ID_RTD:
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
|
|
8001328: 2180 movs r1, #128 @ 0x80
|
|
800132a: 4829 ldr r0, [pc, #164] @ (80013d0 <AD5934_Process_System+0x20c>)
|
|
800132c: f002 faf0 bl 8003910 <HAL_GPIO_ReadPin>
|
|
8001330: 4603 mov r3, r0
|
|
8001332: 2b01 cmp r3, #1
|
|
8001334: d103 bne.n 800133e <AD5934_Process_System+0x17a>
|
|
current_hw_mux_connection = AD5934_CH_RTD_LOW_GAIN; //PT100
|
|
8001336: 4b27 ldr r3, [pc, #156] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
8001338: 2209 movs r2, #9
|
|
800133a: 701a strb r2, [r3, #0]
|
|
else
|
|
current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
|
|
break;
|
|
800133c: e021 b.n 8001382 <AD5934_Process_System+0x1be>
|
|
current_hw_mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
|
|
800133e: 4b25 ldr r3, [pc, #148] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
8001340: 220a movs r2, #10
|
|
8001342: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001344: e01d b.n 8001382 <AD5934_Process_System+0x1be>
|
|
|
|
case AD5934_ID_EC:
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // Hardware Setup: Gain Selection (PA6)
|
|
8001346: 2140 movs r1, #64 @ 0x40
|
|
8001348: 4821 ldr r0, [pc, #132] @ (80013d0 <AD5934_Process_System+0x20c>)
|
|
800134a: f002 fae1 bl 8003910 <HAL_GPIO_ReadPin>
|
|
800134e: 4603 mov r3, r0
|
|
8001350: 2b01 cmp r3, #1
|
|
8001352: d103 bne.n 800135c <AD5934_Process_System+0x198>
|
|
current_hw_mux_connection = AD5934_CH_EC_HIGH_GAIN;
|
|
8001354: 4b1f ldr r3, [pc, #124] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
8001356: 220e movs r2, #14
|
|
8001358: 701a strb r2, [r3, #0]
|
|
else
|
|
current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
|
|
break;
|
|
800135a: e012 b.n 8001382 <AD5934_Process_System+0x1be>
|
|
current_hw_mux_connection = AD5934_CH_EC_MID_GAIN;
|
|
800135c: 4b1d ldr r3, [pc, #116] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
800135e: 220d movs r2, #13
|
|
8001360: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001362: e00e b.n 8001382 <AD5934_Process_System+0x1be>
|
|
|
|
case AD5934_ID_REF:
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
|
|
8001364: 2180 movs r1, #128 @ 0x80
|
|
8001366: 481a ldr r0, [pc, #104] @ (80013d0 <AD5934_Process_System+0x20c>)
|
|
8001368: f002 fad2 bl 8003910 <HAL_GPIO_ReadPin>
|
|
800136c: 4603 mov r3, r0
|
|
800136e: 2b01 cmp r3, #1
|
|
8001370: d103 bne.n 800137a <AD5934_Process_System+0x1b6>
|
|
current_hw_mux_connection = AD5934_CH_REF100R_LOW_GAIN; // 100 Ohms Reference Resistor
|
|
8001372: 4b18 ldr r3, [pc, #96] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
8001374: 2200 movs r2, #0
|
|
8001376: 701a strb r2, [r3, #0]
|
|
else
|
|
current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
|
|
break;
|
|
8001378: e002 b.n 8001380 <AD5934_Process_System+0x1bc>
|
|
current_hw_mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
|
|
800137a: 4b16 ldr r3, [pc, #88] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
800137c: 2204 movs r2, #4
|
|
800137e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001380: bf00 nop
|
|
}
|
|
ADG715_Update(current_hw_mux_connection); // Change the analog mux
|
|
8001382: 4b14 ldr r3, [pc, #80] @ (80013d4 <AD5934_Process_System+0x210>)
|
|
8001384: 781b ldrb r3, [r3, #0]
|
|
8001386: 4618 mov r0, r3
|
|
8001388: f000 f9ca bl 8001720 <ADG715_Update>
|
|
is_new_channel = 1; // Channel Switched
|
|
800138c: 4b0b ldr r3, [pc, #44] @ (80013bc <AD5934_Process_System+0x1f8>)
|
|
800138e: 2201 movs r2, #1
|
|
8001390: 701a strb r2, [r3, #0]
|
|
state_timer = g_ms_counter; // Reload timer to wait for stability
|
|
8001392: 4b0b ldr r3, [pc, #44] @ (80013c0 <AD5934_Process_System+0x1fc>)
|
|
8001394: 681b ldr r3, [r3, #0]
|
|
8001396: 4a0b ldr r2, [pc, #44] @ (80013c4 <AD5934_Process_System+0x200>)
|
|
8001398: 6013 str r3, [r2, #0]
|
|
ad5934_state = AD5934_WAIT_MUX; // Next State
|
|
800139a: 4b06 ldr r3, [pc, #24] @ (80013b4 <AD5934_Process_System+0x1f0>)
|
|
800139c: 2206 movs r2, #6
|
|
800139e: 701a strb r2, [r3, #0]
|
|
break;
|
|
80013a0: e004 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
break;
|
|
80013a2: bf00 nop
|
|
80013a4: e002 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
break;
|
|
80013a6: bf00 nop
|
|
80013a8: e000 b.n 80013ac <AD5934_Process_System+0x1e8>
|
|
break;
|
|
80013aa: bf00 nop
|
|
}
|
|
}
|
|
80013ac: bf00 nop
|
|
80013ae: 3708 adds r7, #8
|
|
80013b0: 46bd mov sp, r7
|
|
80013b2: bd80 pop {r7, pc}
|
|
80013b4: 20000080 .word 0x20000080
|
|
80013b8: 20000088 .word 0x20000088
|
|
80013bc: 20000001 .word 0x20000001
|
|
80013c0: 20000084 .word 0x20000084
|
|
80013c4: 20000158 .word 0x20000158
|
|
80013c8: 20000089 .word 0x20000089
|
|
80013cc: 55555556 .word 0x55555556
|
|
80013d0: 40010800 .word 0x40010800
|
|
80013d4: 20000000 .word 0x20000000
|
|
|
|
080013d8 <AD5934_Sort_Array>:
|
|
/**
|
|
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
|
|
* and it avoids depending on qsort/heap allocation.
|
|
**/
|
|
void AD5934_Sort_Array(float *v, uint8_t n)
|
|
{
|
|
80013d8: b580 push {r7, lr}
|
|
80013da: b084 sub sp, #16
|
|
80013dc: af00 add r7, sp, #0
|
|
80013de: 6078 str r0, [r7, #4]
|
|
80013e0: 460b mov r3, r1
|
|
80013e2: 70fb strb r3, [r7, #3]
|
|
for (uint8_t i = 1; i < n; i++)
|
|
80013e4: 2301 movs r3, #1
|
|
80013e6: 73fb strb r3, [r7, #15]
|
|
80013e8: e039 b.n 800145e <AD5934_Sort_Array+0x86>
|
|
{
|
|
float key = v[i];
|
|
80013ea: 7bfb ldrb r3, [r7, #15]
|
|
80013ec: 009b lsls r3, r3, #2
|
|
80013ee: 687a ldr r2, [r7, #4]
|
|
80013f0: 4413 add r3, r2
|
|
80013f2: 681b ldr r3, [r3, #0]
|
|
80013f4: 60bb str r3, [r7, #8]
|
|
int8_t j = (int8_t)i - 1;
|
|
80013f6: 7bfb ldrb r3, [r7, #15]
|
|
80013f8: 3b01 subs r3, #1
|
|
80013fa: b2db uxtb r3, r3
|
|
80013fc: 73bb strb r3, [r7, #14]
|
|
while (j >= 0 && v[j] > key)
|
|
80013fe: e012 b.n 8001426 <AD5934_Sort_Array+0x4e>
|
|
{
|
|
v[j + 1] = v[j];
|
|
8001400: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001404: 009b lsls r3, r3, #2
|
|
8001406: 687a ldr r2, [r7, #4]
|
|
8001408: 441a add r2, r3
|
|
800140a: f997 300e ldrsb.w r3, [r7, #14]
|
|
800140e: 3301 adds r3, #1
|
|
8001410: 009b lsls r3, r3, #2
|
|
8001412: 6879 ldr r1, [r7, #4]
|
|
8001414: 440b add r3, r1
|
|
8001416: 6812 ldr r2, [r2, #0]
|
|
8001418: 601a str r2, [r3, #0]
|
|
j--;
|
|
800141a: f997 300e ldrsb.w r3, [r7, #14]
|
|
800141e: b2db uxtb r3, r3
|
|
8001420: 3b01 subs r3, #1
|
|
8001422: b2db uxtb r3, r3
|
|
8001424: 73bb strb r3, [r7, #14]
|
|
while (j >= 0 && v[j] > key)
|
|
8001426: f997 300e ldrsb.w r3, [r7, #14]
|
|
800142a: 2b00 cmp r3, #0
|
|
800142c: db0c blt.n 8001448 <AD5934_Sort_Array+0x70>
|
|
800142e: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001432: 009b lsls r3, r3, #2
|
|
8001434: 687a ldr r2, [r7, #4]
|
|
8001436: 4413 add r3, r2
|
|
8001438: 681b ldr r3, [r3, #0]
|
|
800143a: 4619 mov r1, r3
|
|
800143c: 68b8 ldr r0, [r7, #8]
|
|
800143e: f7ff fccf bl 8000de0 <__aeabi_fcmplt>
|
|
8001442: 4603 mov r3, r0
|
|
8001444: 2b00 cmp r3, #0
|
|
8001446: d1db bne.n 8001400 <AD5934_Sort_Array+0x28>
|
|
}
|
|
v[j + 1] = key;
|
|
8001448: f997 300e ldrsb.w r3, [r7, #14]
|
|
800144c: 3301 adds r3, #1
|
|
800144e: 009b lsls r3, r3, #2
|
|
8001450: 687a ldr r2, [r7, #4]
|
|
8001452: 4413 add r3, r2
|
|
8001454: 68ba ldr r2, [r7, #8]
|
|
8001456: 601a str r2, [r3, #0]
|
|
for (uint8_t i = 1; i < n; i++)
|
|
8001458: 7bfb ldrb r3, [r7, #15]
|
|
800145a: 3301 adds r3, #1
|
|
800145c: 73fb strb r3, [r7, #15]
|
|
800145e: 7bfa ldrb r2, [r7, #15]
|
|
8001460: 78fb ldrb r3, [r7, #3]
|
|
8001462: 429a cmp r2, r3
|
|
8001464: d3c1 bcc.n 80013ea <AD5934_Sort_Array+0x12>
|
|
}
|
|
}
|
|
8001466: bf00 nop
|
|
8001468: bf00 nop
|
|
800146a: 3710 adds r7, #16
|
|
800146c: 46bd mov sp, r7
|
|
800146e: bd80 pop {r7, pc}
|
|
|
|
08001470 <AD5934_Trimmed_Mean>:
|
|
* original order is not needed), discards TRIM_COUNT values from each
|
|
* end, and averages the remainder. Sorting in place avoids a temporary
|
|
* array and removes the need for memcpy()/string.h entirely.
|
|
**/
|
|
float AD5934_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
|
|
{
|
|
8001470: b580 push {r7, lr}
|
|
8001472: b086 sub sp, #24
|
|
8001474: af00 add r7, sp, #0
|
|
8001476: 6078 str r0, [r7, #4]
|
|
8001478: 460b mov r3, r1
|
|
800147a: 70fb strb r3, [r7, #3]
|
|
800147c: 4613 mov r3, r2
|
|
800147e: 70bb strb r3, [r7, #2]
|
|
AD5934_Sort_Array(buffer, n);
|
|
8001480: 78fb ldrb r3, [r7, #3]
|
|
8001482: 4619 mov r1, r3
|
|
8001484: 6878 ldr r0, [r7, #4]
|
|
8001486: f7ff ffa7 bl 80013d8 <AD5934_Sort_Array>
|
|
|
|
uint8_t start = trim;
|
|
800148a: 78bb ldrb r3, [r7, #2]
|
|
800148c: 75fb strb r3, [r7, #23]
|
|
uint8_t end = n - trim; /* exclusive */
|
|
800148e: 78fa ldrb r2, [r7, #3]
|
|
8001490: 78bb ldrb r3, [r7, #2]
|
|
8001492: 1ad3 subs r3, r2, r3
|
|
8001494: 75bb strb r3, [r7, #22]
|
|
|
|
if (end <= start) /* guard against a misconfigured trim value */
|
|
8001496: 7dba ldrb r2, [r7, #22]
|
|
8001498: 7dfb ldrb r3, [r7, #23]
|
|
800149a: 429a cmp r2, r3
|
|
800149c: d803 bhi.n 80014a6 <AD5934_Trimmed_Mean+0x36>
|
|
{
|
|
start = 0;
|
|
800149e: 2300 movs r3, #0
|
|
80014a0: 75fb strb r3, [r7, #23]
|
|
end = n;
|
|
80014a2: 78fb ldrb r3, [r7, #3]
|
|
80014a4: 75bb strb r3, [r7, #22]
|
|
}
|
|
|
|
float sum = 0.0f;
|
|
80014a6: f04f 0300 mov.w r3, #0
|
|
80014aa: 613b str r3, [r7, #16]
|
|
uint8_t count = 0;
|
|
80014ac: 2300 movs r3, #0
|
|
80014ae: 73fb strb r3, [r7, #15]
|
|
for (uint8_t i = start; i < end; i++)
|
|
80014b0: 7dfb ldrb r3, [r7, #23]
|
|
80014b2: 73bb strb r3, [r7, #14]
|
|
80014b4: e010 b.n 80014d8 <AD5934_Trimmed_Mean+0x68>
|
|
{
|
|
sum += buffer[i];
|
|
80014b6: 7bbb ldrb r3, [r7, #14]
|
|
80014b8: 009b lsls r3, r3, #2
|
|
80014ba: 687a ldr r2, [r7, #4]
|
|
80014bc: 4413 add r3, r2
|
|
80014be: 681b ldr r3, [r3, #0]
|
|
80014c0: 4619 mov r1, r3
|
|
80014c2: 6938 ldr r0, [r7, #16]
|
|
80014c4: f7ff f9e6 bl 8000894 <__addsf3>
|
|
80014c8: 4603 mov r3, r0
|
|
80014ca: 613b str r3, [r7, #16]
|
|
count++;
|
|
80014cc: 7bfb ldrb r3, [r7, #15]
|
|
80014ce: 3301 adds r3, #1
|
|
80014d0: 73fb strb r3, [r7, #15]
|
|
for (uint8_t i = start; i < end; i++)
|
|
80014d2: 7bbb ldrb r3, [r7, #14]
|
|
80014d4: 3301 adds r3, #1
|
|
80014d6: 73bb strb r3, [r7, #14]
|
|
80014d8: 7bba ldrb r2, [r7, #14]
|
|
80014da: 7dbb ldrb r3, [r7, #22]
|
|
80014dc: 429a cmp r2, r3
|
|
80014de: d3ea bcc.n 80014b6 <AD5934_Trimmed_Mean+0x46>
|
|
}
|
|
return sum / (float)count;
|
|
80014e0: 7bfb ldrb r3, [r7, #15]
|
|
80014e2: 4618 mov r0, r3
|
|
80014e4: f7ff fa86 bl 80009f4 <__aeabi_ui2f>
|
|
80014e8: 4603 mov r3, r0
|
|
80014ea: 4619 mov r1, r3
|
|
80014ec: 6938 ldr r0, [r7, #16]
|
|
80014ee: f7ff fb8d bl 8000c0c <__aeabi_fdiv>
|
|
80014f2: 4603 mov r3, r0
|
|
}
|
|
80014f4: 4618 mov r0, r3
|
|
80014f6: 3718 adds r7, #24
|
|
80014f8: 46bd mov sp, r7
|
|
80014fa: bd80 pop {r7, pc}
|
|
|
|
080014fc <AD5934_History_Average>:
|
|
|
|
/*
|
|
* Simple average of the history buffer (stage-2 sliding window)
|
|
*/
|
|
float AD5934_History_Average(const float *hist, uint8_t n)
|
|
{
|
|
80014fc: b580 push {r7, lr}
|
|
80014fe: b084 sub sp, #16
|
|
8001500: af00 add r7, sp, #0
|
|
8001502: 6078 str r0, [r7, #4]
|
|
8001504: 460b mov r3, r1
|
|
8001506: 70fb strb r3, [r7, #3]
|
|
float sum = 0.0f;
|
|
8001508: f04f 0300 mov.w r3, #0
|
|
800150c: 60fb str r3, [r7, #12]
|
|
for (uint8_t i = 0; i < n; i++)
|
|
800150e: 2300 movs r3, #0
|
|
8001510: 72fb strb r3, [r7, #11]
|
|
8001512: e00d b.n 8001530 <AD5934_History_Average+0x34>
|
|
sum += hist[i];
|
|
8001514: 7afb ldrb r3, [r7, #11]
|
|
8001516: 009b lsls r3, r3, #2
|
|
8001518: 687a ldr r2, [r7, #4]
|
|
800151a: 4413 add r3, r2
|
|
800151c: 681b ldr r3, [r3, #0]
|
|
800151e: 4619 mov r1, r3
|
|
8001520: 68f8 ldr r0, [r7, #12]
|
|
8001522: f7ff f9b7 bl 8000894 <__addsf3>
|
|
8001526: 4603 mov r3, r0
|
|
8001528: 60fb str r3, [r7, #12]
|
|
for (uint8_t i = 0; i < n; i++)
|
|
800152a: 7afb ldrb r3, [r7, #11]
|
|
800152c: 3301 adds r3, #1
|
|
800152e: 72fb strb r3, [r7, #11]
|
|
8001530: 7afa ldrb r2, [r7, #11]
|
|
8001532: 78fb ldrb r3, [r7, #3]
|
|
8001534: 429a cmp r2, r3
|
|
8001536: d3ed bcc.n 8001514 <AD5934_History_Average+0x18>
|
|
return sum / (float)n;
|
|
8001538: 78fb ldrb r3, [r7, #3]
|
|
800153a: 4618 mov r0, r3
|
|
800153c: f7ff fa5a bl 80009f4 <__aeabi_ui2f>
|
|
8001540: 4603 mov r3, r0
|
|
8001542: 4619 mov r1, r3
|
|
8001544: 68f8 ldr r0, [r7, #12]
|
|
8001546: f7ff fb61 bl 8000c0c <__aeabi_fdiv>
|
|
800154a: 4603 mov r3, r0
|
|
}
|
|
800154c: 4618 mov r0, r3
|
|
800154e: 3710 adds r7, #16
|
|
8001550: 46bd mov sp, r7
|
|
8001552: bd80 pop {r7, pc}
|
|
|
|
08001554 <AD5934_Process_Sample>:
|
|
* Common processing core: applied identically to all 3 channels.
|
|
* Receives the current raw reading and the channel's state (global
|
|
* arrays/struct).
|
|
**/
|
|
void AD5934_Process_Sample(AD5934_filter_t *ch, float raw)
|
|
{
|
|
8001554: b590 push {r4, r7, lr}
|
|
8001556: b085 sub sp, #20
|
|
8001558: af00 add r7, sp, #0
|
|
800155a: 6078 str r0, [r7, #4]
|
|
800155c: 6039 str r1, [r7, #0]
|
|
/* --- Stage 1: accumulate into the current burst --- */
|
|
ch->burst[ch->burst_index] = raw;
|
|
800155e: 687b ldr r3, [r7, #4]
|
|
8001560: 7d1b ldrb r3, [r3, #20]
|
|
8001562: 4619 mov r1, r3
|
|
8001564: 687b ldr r3, [r7, #4]
|
|
8001566: 683a ldr r2, [r7, #0]
|
|
8001568: f843 2021 str.w r2, [r3, r1, lsl #2]
|
|
ch->burst_index++;
|
|
800156c: 687b ldr r3, [r7, #4]
|
|
800156e: 7d1b ldrb r3, [r3, #20]
|
|
8001570: 3301 adds r3, #1
|
|
8001572: b2da uxtb r2, r3
|
|
8001574: 687b ldr r3, [r7, #4]
|
|
8001576: 751a strb r2, [r3, #20]
|
|
|
|
if (ch->burst_index < AD5934_BURST_SIZE)
|
|
8001578: 687b ldr r3, [r7, #4]
|
|
800157a: 7d1b ldrb r3, [r3, #20]
|
|
800157c: 2b04 cmp r3, #4
|
|
800157e: d97a bls.n 8001676 <AD5934_Process_Sample+0x122>
|
|
return; /* still collecting the burst, nothing else to do */
|
|
|
|
/* Burst complete: compute the trimmed mean */
|
|
float burst_result = AD5934_Trimmed_Mean(ch->burst, AD5934_BURST_SIZE, AD5934_TRIM_COUNT);
|
|
8001580: 687b ldr r3, [r7, #4]
|
|
8001582: 2201 movs r2, #1
|
|
8001584: 2105 movs r1, #5
|
|
8001586: 4618 mov r0, r3
|
|
8001588: f7ff ff72 bl 8001470 <AD5934_Trimmed_Mean>
|
|
800158c: 60f8 str r0, [r7, #12]
|
|
ch->burst_index = 0; /* reset for the next burst */
|
|
800158e: 687b ldr r3, [r7, #4]
|
|
8001590: 2200 movs r2, #0
|
|
8001592: 751a strb r2, [r3, #20]
|
|
|
|
/* --- Stage 2a: rolling history / sliding window --- */
|
|
ch->history[ch->history_index] = burst_result;
|
|
8001594: 687b ldr r3, [r7, #4]
|
|
8001596: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
800159a: 461a mov r2, r3
|
|
800159c: 687b ldr r3, [r7, #4]
|
|
800159e: 3206 adds r2, #6
|
|
80015a0: 68f9 ldr r1, [r7, #12]
|
|
80015a2: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
ch->history_index = (uint8_t)((ch->history_index + 1) % AD5934_HISTORY_SIZE);
|
|
80015a6: 687b ldr r3, [r7, #4]
|
|
80015a8: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
80015ac: 1c5a adds r2, r3, #1
|
|
80015ae: 4b34 ldr r3, [pc, #208] @ (8001680 <AD5934_Process_Sample+0x12c>)
|
|
80015b0: fb83 3102 smull r3, r1, r3, r2
|
|
80015b4: 17d3 asrs r3, r2, #31
|
|
80015b6: 1ac9 subs r1, r1, r3
|
|
80015b8: 460b mov r3, r1
|
|
80015ba: 005b lsls r3, r3, #1
|
|
80015bc: 440b add r3, r1
|
|
80015be: 005b lsls r3, r3, #1
|
|
80015c0: 1ad1 subs r1, r2, r3
|
|
80015c2: b2ca uxtb r2, r1
|
|
80015c4: 687b ldr r3, [r7, #4]
|
|
80015c6: f883 2030 strb.w r2, [r3, #48] @ 0x30
|
|
if (ch->history_count < AD5934_HISTORY_SIZE)
|
|
80015ca: 687b ldr r3, [r7, #4]
|
|
80015cc: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
80015d0: 2b05 cmp r3, #5
|
|
80015d2: d807 bhi.n 80015e4 <AD5934_Process_Sample+0x90>
|
|
ch->history_count++;
|
|
80015d4: 687b ldr r3, [r7, #4]
|
|
80015d6: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
80015da: 3301 adds r3, #1
|
|
80015dc: b2da uxtb r2, r3
|
|
80015de: 687b ldr r3, [r7, #4]
|
|
80015e0: f883 2031 strb.w r2, [r3, #49] @ 0x31
|
|
|
|
float window_average = AD5934_History_Average(ch->history, ch->history_count);
|
|
80015e4: 687b ldr r3, [r7, #4]
|
|
80015e6: f103 0218 add.w r2, r3, #24
|
|
80015ea: 687b ldr r3, [r7, #4]
|
|
80015ec: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
80015f0: 4619 mov r1, r3
|
|
80015f2: 4610 mov r0, r2
|
|
80015f4: f7ff ff82 bl 80014fc <AD5934_History_Average>
|
|
80015f8: 60b8 str r0, [r7, #8]
|
|
|
|
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
|
|
if (!ch->iir_initialized)
|
|
80015fa: 687b ldr r3, [r7, #4]
|
|
80015fc: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8001600: 2b00 cmp r3, #0
|
|
8001602: d107 bne.n 8001614 <AD5934_Process_Sample+0xc0>
|
|
{
|
|
ch->iir_state = burst_result;
|
|
8001604: 687b ldr r3, [r7, #4]
|
|
8001606: 68fa ldr r2, [r7, #12]
|
|
8001608: 635a str r2, [r3, #52] @ 0x34
|
|
ch->iir_initialized = 1;
|
|
800160a: 687b ldr r3, [r7, #4]
|
|
800160c: 2201 movs r2, #1
|
|
800160e: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
8001612: e014 b.n 800163e <AD5934_Process_Sample+0xea>
|
|
}
|
|
else
|
|
{
|
|
ch->iir_state = AD5934_IIR_ALPHA * burst_result + (1.0f - AD5934_IIR_ALPHA) * ch->iir_state;
|
|
8001614: 491b ldr r1, [pc, #108] @ (8001684 <AD5934_Process_Sample+0x130>)
|
|
8001616: 68f8 ldr r0, [r7, #12]
|
|
8001618: f7ff fa44 bl 8000aa4 <__aeabi_fmul>
|
|
800161c: 4603 mov r3, r0
|
|
800161e: 461c mov r4, r3
|
|
8001620: 687b ldr r3, [r7, #4]
|
|
8001622: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001624: 4918 ldr r1, [pc, #96] @ (8001688 <AD5934_Process_Sample+0x134>)
|
|
8001626: 4618 mov r0, r3
|
|
8001628: f7ff fa3c bl 8000aa4 <__aeabi_fmul>
|
|
800162c: 4603 mov r3, r0
|
|
800162e: 4619 mov r1, r3
|
|
8001630: 4620 mov r0, r4
|
|
8001632: f7ff f92f bl 8000894 <__addsf3>
|
|
8001636: 4603 mov r3, r0
|
|
8001638: 461a mov r2, r3
|
|
800163a: 687b ldr r3, [r7, #4]
|
|
800163c: 635a str r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
/* Final output: combines the IIR state (fast response to real drift)
|
|
* with the window average (more stable, slower response). Adjust
|
|
* the weighting per channel if needed. */
|
|
ch->filtered_value = 0.5f * ch->iir_state + 0.5f * window_average;
|
|
800163e: 687b ldr r3, [r7, #4]
|
|
8001640: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001642: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
|
|
8001646: 4618 mov r0, r3
|
|
8001648: f7ff fa2c bl 8000aa4 <__aeabi_fmul>
|
|
800164c: 4603 mov r3, r0
|
|
800164e: 461c mov r4, r3
|
|
8001650: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
|
|
8001654: 68b8 ldr r0, [r7, #8]
|
|
8001656: f7ff fa25 bl 8000aa4 <__aeabi_fmul>
|
|
800165a: 4603 mov r3, r0
|
|
800165c: 4619 mov r1, r3
|
|
800165e: 4620 mov r0, r4
|
|
8001660: f7ff f918 bl 8000894 <__addsf3>
|
|
8001664: 4603 mov r3, r0
|
|
8001666: 461a mov r2, r3
|
|
8001668: 687b ldr r3, [r7, #4]
|
|
800166a: 63da str r2, [r3, #60] @ 0x3c
|
|
ch->value_valid = 1;
|
|
800166c: 687b ldr r3, [r7, #4]
|
|
800166e: 2201 movs r2, #1
|
|
8001670: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8001674: e000 b.n 8001678 <AD5934_Process_Sample+0x124>
|
|
return; /* still collecting the burst, nothing else to do */
|
|
8001676: bf00 nop
|
|
}
|
|
8001678: 3714 adds r7, #20
|
|
800167a: 46bd mov sp, r7
|
|
800167c: bd90 pop {r4, r7, pc}
|
|
800167e: bf00 nop
|
|
8001680: 2aaaaaab .word 0x2aaaaaab
|
|
8001684: 3ecccccd .word 0x3ecccccd
|
|
8001688: 3f19999a .word 0x3f19999a
|
|
|
|
0800168c <AD5934_RTD_NewSample>:
|
|
/* ---------------------------------------------------------------------- */
|
|
|
|
/* Call this every time a sweep completes with the mux on the RTD
|
|
* (PT100/PT1000) channel */
|
|
void AD5934_RTD_NewSample(float raw)
|
|
{
|
|
800168c: b580 push {r7, lr}
|
|
800168e: b082 sub sp, #8
|
|
8001690: af00 add r7, sp, #0
|
|
8001692: 6078 str r0, [r7, #4]
|
|
AD5934_Process_Sample(&g_rtd_filter, raw);
|
|
8001694: 6879 ldr r1, [r7, #4]
|
|
8001696: 4803 ldr r0, [pc, #12] @ (80016a4 <AD5934_RTD_NewSample+0x18>)
|
|
8001698: f7ff ff5c bl 8001554 <AD5934_Process_Sample>
|
|
}
|
|
800169c: bf00 nop
|
|
800169e: 3708 adds r7, #8
|
|
80016a0: 46bd mov sp, r7
|
|
80016a2: bd80 pop {r7, pc}
|
|
80016a4: 2000008c .word 0x2000008c
|
|
|
|
080016a8 <AD5934_EC_NewSample>:
|
|
|
|
/* Call this every time a sweep completes with the mux on the EC
|
|
* (conductivity probe) channel */
|
|
void AD5934_EC_NewSample(float raw)
|
|
{
|
|
80016a8: b580 push {r7, lr}
|
|
80016aa: b082 sub sp, #8
|
|
80016ac: af00 add r7, sp, #0
|
|
80016ae: 6078 str r0, [r7, #4]
|
|
AD5934_Process_Sample(&g_ec_filter, raw);
|
|
80016b0: 6879 ldr r1, [r7, #4]
|
|
80016b2: 4803 ldr r0, [pc, #12] @ (80016c0 <AD5934_EC_NewSample+0x18>)
|
|
80016b4: f7ff ff4e bl 8001554 <AD5934_Process_Sample>
|
|
}
|
|
80016b8: bf00 nop
|
|
80016ba: 3708 adds r7, #8
|
|
80016bc: 46bd mov sp, r7
|
|
80016be: bd80 pop {r7, pc}
|
|
80016c0: 200000d0 .word 0x200000d0
|
|
|
|
080016c4 <AD5934_Reference_NewSample>:
|
|
|
|
/* Call this every time a sweep completes with the mux on the on-board
|
|
* precision reference resistor channel */
|
|
void AD5934_Reference_NewSample(float raw)
|
|
{
|
|
80016c4: b580 push {r7, lr}
|
|
80016c6: b082 sub sp, #8
|
|
80016c8: af00 add r7, sp, #0
|
|
80016ca: 6078 str r0, [r7, #4]
|
|
AD5934_Process_Sample(&g_ref_filter, raw);
|
|
80016cc: 6879 ldr r1, [r7, #4]
|
|
80016ce: 4803 ldr r0, [pc, #12] @ (80016dc <AD5934_Reference_NewSample+0x18>)
|
|
80016d0: f7ff ff40 bl 8001554 <AD5934_Process_Sample>
|
|
}
|
|
80016d4: bf00 nop
|
|
80016d6: 3708 adds r7, #8
|
|
80016d8: 46bd mov sp, r7
|
|
80016da: bd80 pop {r7, pc}
|
|
80016dc: 20000114 .word 0x20000114
|
|
|
|
080016e0 <ADG715_SetRegisterValue>:
|
|
*
|
|
* @return None.
|
|
*******************************************************************************/
|
|
|
|
void ADG715_SetRegisterValue(char value)
|
|
{
|
|
80016e0: b580 push {r7, lr}
|
|
80016e2: b086 sub sp, #24
|
|
80016e4: af02 add r7, sp, #8
|
|
80016e6: 4603 mov r3, r0
|
|
80016e8: 71fb strb r3, [r7, #7]
|
|
uint8_t writeData[1] = {value};
|
|
80016ea: 79fb ldrb r3, [r7, #7]
|
|
80016ec: 733b strb r3, [r7, #12]
|
|
HAL_StatusTypeDef status;
|
|
|
|
status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
|
|
80016ee: f107 020c add.w r2, r7, #12
|
|
80016f2: 2301 movs r3, #1
|
|
80016f4: 9300 str r3, [sp, #0]
|
|
80016f6: 2301 movs r3, #1
|
|
80016f8: 2190 movs r1, #144 @ 0x90
|
|
80016fa: 4804 ldr r0, [pc, #16] @ (800170c <ADG715_SetRegisterValue+0x2c>)
|
|
80016fc: f002 fa94 bl 8003c28 <HAL_I2C_Master_Transmit>
|
|
8001700: 4603 mov r3, r0
|
|
8001702: 73fb strb r3, [r7, #15]
|
|
|
|
return;
|
|
8001704: bf00 nop
|
|
}
|
|
8001706: 3710 adds r7, #16
|
|
8001708: 46bd mov sp, r7
|
|
800170a: bd80 pop {r7, pc}
|
|
800170c: 20000678 .word 0x20000678
|
|
|
|
08001710 <ADG715_ResetChannels>:
|
|
{
|
|
ADG715_SetRegisterValue(ch1+ch2);
|
|
}
|
|
|
|
void ADG715_ResetChannels(void)
|
|
{
|
|
8001710: b580 push {r7, lr}
|
|
8001712: af00 add r7, sp, #0
|
|
ADG715_SetRegisterValue(0);
|
|
8001714: 2000 movs r0, #0
|
|
8001716: f7ff ffe3 bl 80016e0 <ADG715_SetRegisterValue>
|
|
}
|
|
800171a: bf00 nop
|
|
800171c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001720 <ADG715_Update>:
|
|
* @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000, AD5934_CH_EC, ...
|
|
*
|
|
* @return none.
|
|
******************************************************************************/
|
|
void ADG715_Update(AD5934_Channel_t channel)
|
|
{
|
|
8001720: b580 push {r7, lr}
|
|
8001722: b082 sub sp, #8
|
|
8001724: af00 add r7, sp, #0
|
|
8001726: 4603 mov r3, r0
|
|
8001728: 71fb strb r3, [r7, #7]
|
|
// Garante que o índice recebido não ultrapassa os limites do vetor
|
|
if (channel >= AD5934_CH_MAX)
|
|
800172a: 79fb ldrb r3, [r7, #7]
|
|
800172c: 2b0e cmp r3, #14
|
|
800172e: d806 bhi.n 800173e <ADG715_Update+0x1e>
|
|
return;
|
|
|
|
// Envia o byte combinado via I2C (Make-before-break nativo por barramento)
|
|
ADG715_SetRegisterValue(ADG715_Channel_Map[channel]);
|
|
8001730: 79fb ldrb r3, [r7, #7]
|
|
8001732: 4a05 ldr r2, [pc, #20] @ (8001748 <ADG715_Update+0x28>)
|
|
8001734: 5cd3 ldrb r3, [r2, r3]
|
|
8001736: 4618 mov r0, r3
|
|
8001738: f7ff ffd2 bl 80016e0 <ADG715_SetRegisterValue>
|
|
800173c: e000 b.n 8001740 <ADG715_Update+0x20>
|
|
return;
|
|
800173e: bf00 nop
|
|
/* if (channel >= AD5934_CH_EC_LOW_GAIN)
|
|
HAL_Delay(20); // Canais de Condutividade Elétrica (CE) necessitam de maior estabilização química
|
|
else
|
|
HAL_Delay(10); // Resistores puros e RTD estabilizam mais rapidamente
|
|
*/
|
|
}
|
|
8001740: 3708 adds r7, #8
|
|
8001742: 46bd mov sp, r7
|
|
8001744: bd80 pop {r7, pc}
|
|
8001746: bf00 nop
|
|
8001748: 08006960 .word 0x08006960
|
|
|
|
0800174c <MX_ADC1_Init>:
|
|
ADC_HandleTypeDef hadc1;
|
|
ADC_HandleTypeDef hadc2;
|
|
|
|
/* ADC1 init function */
|
|
void MX_ADC1_Init(void)
|
|
{
|
|
800174c: b580 push {r7, lr}
|
|
800174e: b084 sub sp, #16
|
|
8001750: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8001752: 1d3b adds r3, r7, #4
|
|
8001754: 2200 movs r2, #0
|
|
8001756: 601a str r2, [r3, #0]
|
|
8001758: 605a str r2, [r3, #4]
|
|
800175a: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
800175c: 4b18 ldr r3, [pc, #96] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
800175e: 4a19 ldr r2, [pc, #100] @ (80017c4 <MX_ADC1_Init+0x78>)
|
|
8001760: 601a str r2, [r3, #0]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
8001762: 4b17 ldr r3, [pc, #92] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
8001764: 2200 movs r2, #0
|
|
8001766: 609a str r2, [r3, #8]
|
|
hadc1.Init.ContinuousConvMode = ENABLE;
|
|
8001768: 4b15 ldr r3, [pc, #84] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
800176a: 2201 movs r2, #1
|
|
800176c: 731a strb r2, [r3, #12]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
800176e: 4b14 ldr r3, [pc, #80] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
8001770: 2200 movs r2, #0
|
|
8001772: 751a strb r2, [r3, #20]
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8001774: 4b12 ldr r3, [pc, #72] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
8001776: f44f 2260 mov.w r2, #917504 @ 0xe0000
|
|
800177a: 61da str r2, [r3, #28]
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
800177c: 4b10 ldr r3, [pc, #64] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
800177e: 2200 movs r2, #0
|
|
8001780: 605a str r2, [r3, #4]
|
|
hadc1.Init.NbrOfConversion = 1;
|
|
8001782: 4b0f ldr r3, [pc, #60] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
8001784: 2201 movs r2, #1
|
|
8001786: 611a str r2, [r3, #16]
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
8001788: 480d ldr r0, [pc, #52] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
800178a: f001 fb6b bl 8002e64 <HAL_ADC_Init>
|
|
800178e: 4603 mov r3, r0
|
|
8001790: 2b00 cmp r3, #0
|
|
8001792: d001 beq.n 8001798 <MX_ADC1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001794: f001 f87a bl 800288c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_0;
|
|
8001798: 2300 movs r3, #0
|
|
800179a: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
800179c: 2301 movs r3, #1
|
|
800179e: 60bb str r3, [r7, #8]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
|
80017a0: 2300 movs r3, #0
|
|
80017a2: 60fb str r3, [r7, #12]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80017a4: 1d3b adds r3, r7, #4
|
|
80017a6: 4619 mov r1, r3
|
|
80017a8: 4805 ldr r0, [pc, #20] @ (80017c0 <MX_ADC1_Init+0x74>)
|
|
80017aa: f001 fc33 bl 8003014 <HAL_ADC_ConfigChannel>
|
|
80017ae: 4603 mov r3, r0
|
|
80017b0: 2b00 cmp r3, #0
|
|
80017b2: d001 beq.n 80017b8 <MX_ADC1_Init+0x6c>
|
|
{
|
|
Error_Handler();
|
|
80017b4: f001 f86a bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
80017b8: bf00 nop
|
|
80017ba: 3710 adds r7, #16
|
|
80017bc: 46bd mov sp, r7
|
|
80017be: bd80 pop {r7, pc}
|
|
80017c0: 2000015c .word 0x2000015c
|
|
80017c4: 40012400 .word 0x40012400
|
|
|
|
080017c8 <MX_ADC2_Init>:
|
|
/* ADC2 init function */
|
|
void MX_ADC2_Init(void)
|
|
{
|
|
80017c8: b580 push {r7, lr}
|
|
80017ca: b084 sub sp, #16
|
|
80017cc: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC2_Init 0 */
|
|
|
|
/* USER CODE END ADC2_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
80017ce: 1d3b adds r3, r7, #4
|
|
80017d0: 2200 movs r2, #0
|
|
80017d2: 601a str r2, [r3, #0]
|
|
80017d4: 605a str r2, [r3, #4]
|
|
80017d6: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE END ADC2_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc2.Instance = ADC2;
|
|
80017d8: 4b18 ldr r3, [pc, #96] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017da: 4a19 ldr r2, [pc, #100] @ (8001840 <MX_ADC2_Init+0x78>)
|
|
80017dc: 601a str r2, [r3, #0]
|
|
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
80017de: 4b17 ldr r3, [pc, #92] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017e0: 2200 movs r2, #0
|
|
80017e2: 609a str r2, [r3, #8]
|
|
hadc2.Init.ContinuousConvMode = ENABLE;
|
|
80017e4: 4b15 ldr r3, [pc, #84] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017e6: 2201 movs r2, #1
|
|
80017e8: 731a strb r2, [r3, #12]
|
|
hadc2.Init.DiscontinuousConvMode = DISABLE;
|
|
80017ea: 4b14 ldr r3, [pc, #80] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017ec: 2200 movs r2, #0
|
|
80017ee: 751a strb r2, [r3, #20]
|
|
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
80017f0: 4b12 ldr r3, [pc, #72] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017f2: f44f 2260 mov.w r2, #917504 @ 0xe0000
|
|
80017f6: 61da str r2, [r3, #28]
|
|
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
80017f8: 4b10 ldr r3, [pc, #64] @ (800183c <MX_ADC2_Init+0x74>)
|
|
80017fa: 2200 movs r2, #0
|
|
80017fc: 605a str r2, [r3, #4]
|
|
hadc2.Init.NbrOfConversion = 1;
|
|
80017fe: 4b0f ldr r3, [pc, #60] @ (800183c <MX_ADC2_Init+0x74>)
|
|
8001800: 2201 movs r2, #1
|
|
8001802: 611a str r2, [r3, #16]
|
|
if (HAL_ADC_Init(&hadc2) != HAL_OK)
|
|
8001804: 480d ldr r0, [pc, #52] @ (800183c <MX_ADC2_Init+0x74>)
|
|
8001806: f001 fb2d bl 8002e64 <HAL_ADC_Init>
|
|
800180a: 4603 mov r3, r0
|
|
800180c: 2b00 cmp r3, #0
|
|
800180e: d001 beq.n 8001814 <MX_ADC2_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001810: f001 f83c bl 800288c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_1;
|
|
8001814: 2301 movs r3, #1
|
|
8001816: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
8001818: 2301 movs r3, #1
|
|
800181a: 60bb str r3, [r7, #8]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
|
800181c: 2300 movs r3, #0
|
|
800181e: 60fb str r3, [r7, #12]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
8001820: 1d3b adds r3, r7, #4
|
|
8001822: 4619 mov r1, r3
|
|
8001824: 4805 ldr r0, [pc, #20] @ (800183c <MX_ADC2_Init+0x74>)
|
|
8001826: f001 fbf5 bl 8003014 <HAL_ADC_ConfigChannel>
|
|
800182a: 4603 mov r3, r0
|
|
800182c: 2b00 cmp r3, #0
|
|
800182e: d001 beq.n 8001834 <MX_ADC2_Init+0x6c>
|
|
{
|
|
Error_Handler();
|
|
8001830: f001 f82c bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC2_Init 2 */
|
|
|
|
/* USER CODE END ADC2_Init 2 */
|
|
|
|
}
|
|
8001834: bf00 nop
|
|
8001836: 3710 adds r7, #16
|
|
8001838: 46bd mov sp, r7
|
|
800183a: bd80 pop {r7, pc}
|
|
800183c: 2000018c .word 0x2000018c
|
|
8001840: 40012800 .word 0x40012800
|
|
|
|
08001844 <HAL_ADC_MspInit>:
|
|
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
|
|
{
|
|
8001844: b580 push {r7, lr}
|
|
8001846: b08a sub sp, #40 @ 0x28
|
|
8001848: af00 add r7, sp, #0
|
|
800184a: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800184c: f107 0318 add.w r3, r7, #24
|
|
8001850: 2200 movs r2, #0
|
|
8001852: 601a str r2, [r3, #0]
|
|
8001854: 605a str r2, [r3, #4]
|
|
8001856: 609a str r2, [r3, #8]
|
|
8001858: 60da str r2, [r3, #12]
|
|
if(adcHandle->Instance==ADC1)
|
|
800185a: 687b ldr r3, [r7, #4]
|
|
800185c: 681b ldr r3, [r3, #0]
|
|
800185e: 4a28 ldr r2, [pc, #160] @ (8001900 <HAL_ADC_MspInit+0xbc>)
|
|
8001860: 4293 cmp r3, r2
|
|
8001862: d122 bne.n 80018aa <HAL_ADC_MspInit+0x66>
|
|
{
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/* ADC1 clock enable */
|
|
__HAL_RCC_ADC1_CLK_ENABLE();
|
|
8001864: 4b27 ldr r3, [pc, #156] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
8001866: 699b ldr r3, [r3, #24]
|
|
8001868: 4a26 ldr r2, [pc, #152] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
800186a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800186e: 6193 str r3, [r2, #24]
|
|
8001870: 4b24 ldr r3, [pc, #144] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
8001872: 699b ldr r3, [r3, #24]
|
|
8001874: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001878: 617b str r3, [r7, #20]
|
|
800187a: 697b ldr r3, [r7, #20]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800187c: 4b21 ldr r3, [pc, #132] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
800187e: 699b ldr r3, [r3, #24]
|
|
8001880: 4a20 ldr r2, [pc, #128] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
8001882: f043 0304 orr.w r3, r3, #4
|
|
8001886: 6193 str r3, [r2, #24]
|
|
8001888: 4b1e ldr r3, [pc, #120] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
800188a: 699b ldr r3, [r3, #24]
|
|
800188c: f003 0304 and.w r3, r3, #4
|
|
8001890: 613b str r3, [r7, #16]
|
|
8001892: 693b ldr r3, [r7, #16]
|
|
/**ADC1 GPIO Configuration
|
|
PA0-WKUP ------> ADC1_IN0
|
|
PA1 ------> ADC1_IN1
|
|
*/
|
|
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
|
|
8001894: 2303 movs r3, #3
|
|
8001896: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001898: 2303 movs r3, #3
|
|
800189a: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800189c: f107 0318 add.w r3, r7, #24
|
|
80018a0: 4619 mov r1, r3
|
|
80018a2: 4819 ldr r0, [pc, #100] @ (8001908 <HAL_ADC_MspInit+0xc4>)
|
|
80018a4: f001 feb0 bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN ADC2_MspInit 1 */
|
|
|
|
/* USER CODE END ADC2_MspInit 1 */
|
|
}
|
|
}
|
|
80018a8: e026 b.n 80018f8 <HAL_ADC_MspInit+0xb4>
|
|
else if(adcHandle->Instance==ADC2)
|
|
80018aa: 687b ldr r3, [r7, #4]
|
|
80018ac: 681b ldr r3, [r3, #0]
|
|
80018ae: 4a17 ldr r2, [pc, #92] @ (800190c <HAL_ADC_MspInit+0xc8>)
|
|
80018b0: 4293 cmp r3, r2
|
|
80018b2: d121 bne.n 80018f8 <HAL_ADC_MspInit+0xb4>
|
|
__HAL_RCC_ADC2_CLK_ENABLE();
|
|
80018b4: 4b13 ldr r3, [pc, #76] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018b6: 699b ldr r3, [r3, #24]
|
|
80018b8: 4a12 ldr r2, [pc, #72] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018ba: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
80018be: 6193 str r3, [r2, #24]
|
|
80018c0: 4b10 ldr r3, [pc, #64] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018c2: 699b ldr r3, [r3, #24]
|
|
80018c4: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80018c8: 60fb str r3, [r7, #12]
|
|
80018ca: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80018cc: 4b0d ldr r3, [pc, #52] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018ce: 699b ldr r3, [r3, #24]
|
|
80018d0: 4a0c ldr r2, [pc, #48] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018d2: f043 0304 orr.w r3, r3, #4
|
|
80018d6: 6193 str r3, [r2, #24]
|
|
80018d8: 4b0a ldr r3, [pc, #40] @ (8001904 <HAL_ADC_MspInit+0xc0>)
|
|
80018da: 699b ldr r3, [r3, #24]
|
|
80018dc: f003 0304 and.w r3, r3, #4
|
|
80018e0: 60bb str r3, [r7, #8]
|
|
80018e2: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
|
|
80018e4: 2303 movs r3, #3
|
|
80018e6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80018e8: 2303 movs r3, #3
|
|
80018ea: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80018ec: f107 0318 add.w r3, r7, #24
|
|
80018f0: 4619 mov r1, r3
|
|
80018f2: 4805 ldr r0, [pc, #20] @ (8001908 <HAL_ADC_MspInit+0xc4>)
|
|
80018f4: f001 fe88 bl 8003608 <HAL_GPIO_Init>
|
|
}
|
|
80018f8: bf00 nop
|
|
80018fa: 3728 adds r7, #40 @ 0x28
|
|
80018fc: 46bd mov sp, r7
|
|
80018fe: bd80 pop {r7, pc}
|
|
8001900: 40012400 .word 0x40012400
|
|
8001904: 40021000 .word 0x40021000
|
|
8001908: 40010800 .word 0x40010800
|
|
800190c: 40012800 .word 0x40012800
|
|
|
|
08001910 <writeRegister>:
|
|
ADS1015_filter_t g_ph_filter = {0};
|
|
|
|
volatile ADS1015_State_t ads1015_state = ADS1015_IDLE;
|
|
|
|
// Write the register
|
|
static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
|
|
8001910: b580 push {r7, lr}
|
|
8001912: b086 sub sp, #24
|
|
8001914: af02 add r7, sp, #8
|
|
8001916: 6078 str r0, [r7, #4]
|
|
8001918: 460b mov r3, r1
|
|
800191a: 70fb strb r3, [r7, #3]
|
|
800191c: 4613 mov r3, r2
|
|
800191e: 803b strh r3, [r7, #0]
|
|
uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
|
|
8001920: 78fb ldrb r3, [r7, #3]
|
|
8001922: 733b strb r3, [r7, #12]
|
|
8001924: 883b ldrh r3, [r7, #0]
|
|
8001926: 0a1b lsrs r3, r3, #8
|
|
8001928: b29b uxth r3, r3
|
|
800192a: b2db uxtb r3, r3
|
|
800192c: 737b strb r3, [r7, #13]
|
|
800192e: 883b ldrh r3, [r7, #0]
|
|
8001930: b2db uxtb r3, r3
|
|
8001932: 73bb strb r3, [r7, #14]
|
|
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
|
|
8001934: 687b ldr r3, [r7, #4]
|
|
8001936: 68d8 ldr r0, [r3, #12]
|
|
8001938: 687b ldr r3, [r7, #4]
|
|
800193a: 8819 ldrh r1, [r3, #0]
|
|
800193c: f107 020c add.w r2, r7, #12
|
|
8001940: 230a movs r3, #10
|
|
8001942: 9300 str r3, [sp, #0]
|
|
8001944: 2303 movs r3, #3
|
|
8001946: f002 f96f bl 8003c28 <HAL_I2C_Master_Transmit>
|
|
}
|
|
800194a: bf00 nop
|
|
800194c: 3710 adds r7, #16
|
|
800194e: 46bd mov sp, r7
|
|
8001950: bd80 pop {r7, pc}
|
|
|
|
08001952 <readRegister>:
|
|
|
|
// Read the register
|
|
static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
|
|
8001952: b580 push {r7, lr}
|
|
8001954: b086 sub sp, #24
|
|
8001956: af02 add r7, sp, #8
|
|
8001958: 6078 str r0, [r7, #4]
|
|
800195a: 460b mov r3, r1
|
|
800195c: 70fb strb r3, [r7, #3]
|
|
HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, ®, 1, 10);
|
|
800195e: 687b ldr r3, [r7, #4]
|
|
8001960: 68d8 ldr r0, [r3, #12]
|
|
8001962: 687b ldr r3, [r7, #4]
|
|
8001964: 8819 ldrh r1, [r3, #0]
|
|
8001966: 1cfa adds r2, r7, #3
|
|
8001968: 230a movs r3, #10
|
|
800196a: 9300 str r3, [sp, #0]
|
|
800196c: 2301 movs r3, #1
|
|
800196e: f002 f95b bl 8003c28 <HAL_I2C_Master_Transmit>
|
|
uint8_t pData[2] = { 0, 0 };
|
|
8001972: 2300 movs r3, #0
|
|
8001974: 81bb strh r3, [r7, #12]
|
|
HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
|
|
8001976: 687b ldr r3, [r7, #4]
|
|
8001978: 68d8 ldr r0, [r3, #12]
|
|
800197a: 687b ldr r3, [r7, #4]
|
|
800197c: 8819 ldrh r1, [r3, #0]
|
|
800197e: f107 020c add.w r2, r7, #12
|
|
8001982: 230a movs r3, #10
|
|
8001984: 9300 str r3, [sp, #0]
|
|
8001986: 2302 movs r3, #2
|
|
8001988: f002 fa4c bl 8003e24 <HAL_I2C_Master_Receive>
|
|
return ((pData[0] << 8) | pData[1]);
|
|
800198c: 7b3b ldrb r3, [r7, #12]
|
|
800198e: b21b sxth r3, r3
|
|
8001990: 021b lsls r3, r3, #8
|
|
8001992: b21a sxth r2, r3
|
|
8001994: 7b7b ldrb r3, [r7, #13]
|
|
8001996: b21b sxth r3, r3
|
|
8001998: 4313 orrs r3, r2
|
|
800199a: b21b sxth r3, r3
|
|
800199c: b29b uxth r3, r3
|
|
}
|
|
800199e: 4618 mov r0, r3
|
|
80019a0: 3710 adds r7, #16
|
|
80019a2: 46bd mov sp, r7
|
|
80019a4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080019a8 <ADS1015_Init>:
|
|
|
|
}
|
|
|
|
// Declare an ADS1015 structure
|
|
void ADS1015_Init(void)
|
|
{
|
|
80019a8: b480 push {r7}
|
|
80019aa: af00 add r7, sp, #0
|
|
i2c_ads1015.hi2c = &hi2c1;
|
|
80019ac: 4b09 ldr r3, [pc, #36] @ (80019d4 <ADS1015_Init+0x2c>)
|
|
80019ae: 4a0a ldr r2, [pc, #40] @ (80019d8 <ADS1015_Init+0x30>)
|
|
80019b0: 60da str r2, [r3, #12]
|
|
i2c_ads1015.m_i2cAddress = ADS1015_ADDR_GND; // It's Important to shift the address << 1
|
|
80019b2: 4b08 ldr r3, [pc, #32] @ (80019d4 <ADS1015_Init+0x2c>)
|
|
80019b4: 2290 movs r2, #144 @ 0x90
|
|
80019b6: 801a strh r2, [r3, #0]
|
|
i2c_ads1015.m_conversionDelay = ADS1015_CONVERSIONDELAY;
|
|
80019b8: 4b06 ldr r3, [pc, #24] @ (80019d4 <ADS1015_Init+0x2c>)
|
|
80019ba: 2204 movs r2, #4
|
|
80019bc: 605a str r2, [r3, #4]
|
|
i2c_ads1015.m_bitShift = 4;
|
|
80019be: 4b05 ldr r3, [pc, #20] @ (80019d4 <ADS1015_Init+0x2c>)
|
|
80019c0: 2204 movs r2, #4
|
|
80019c2: 721a strb r2, [r3, #8]
|
|
i2c_ads1015.m_gain = GAIN_SIXTEEN; /* +/- 6.144V range (limited to VDD +0.3V max!) */
|
|
80019c4: 4b03 ldr r3, [pc, #12] @ (80019d4 <ADS1015_Init+0x2c>)
|
|
80019c6: f44f 6220 mov.w r2, #2560 @ 0xa00
|
|
80019ca: 815a strh r2, [r3, #10]
|
|
//ADSbegin(i2c); //Ready is not used
|
|
}
|
|
80019cc: bf00 nop
|
|
80019ce: 46bd mov sp, r7
|
|
80019d0: bc80 pop {r7}
|
|
80019d2: 4770 bx lr
|
|
80019d4: 200001bc .word 0x200001bc
|
|
80019d8: 20000624 .word 0x20000624
|
|
|
|
080019dc <ADS1015_Process_System>:
|
|
|
|
|
|
|
|
|
|
void ADS1015_Process_System(void)
|
|
{
|
|
80019dc: b580 push {r7, lr}
|
|
80019de: b082 sub sp, #8
|
|
80019e0: af00 add r7, sp, #0
|
|
static uint32_t state_timer = 0;
|
|
static uint32_t sample_count = 0;
|
|
uint16_t config_reg = 0;
|
|
80019e2: 2300 movs r3, #0
|
|
80019e4: 80fb strh r3, [r7, #6]
|
|
|
|
switch (ads1015_state)
|
|
80019e6: 4b3d ldr r3, [pc, #244] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
80019e8: 781b ldrb r3, [r3, #0]
|
|
80019ea: b2db uxtb r3, r3
|
|
80019ec: 2b04 cmp r3, #4
|
|
80019ee: d870 bhi.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
80019f0: a201 add r2, pc, #4 @ (adr r2, 80019f8 <ADS1015_Process_System+0x1c>)
|
|
80019f2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80019f6: bf00 nop
|
|
80019f8: 08001a0d .word 0x08001a0d
|
|
80019fc: 08001a1b .word 0x08001a1b
|
|
8001a00: 08001a37 .word 0x08001a37
|
|
8001a04: 08001a61 .word 0x08001a61
|
|
8001a08: 08001ab7 .word 0x08001ab7
|
|
{
|
|
case ADS1015_IDLE:
|
|
sample_count = 0;
|
|
8001a0c: 4b34 ldr r3, [pc, #208] @ (8001ae0 <ADS1015_Process_System+0x104>)
|
|
8001a0e: 2200 movs r2, #0
|
|
8001a10: 601a str r2, [r3, #0]
|
|
ads1015_state = ADS1015_START_CONVERSION;
|
|
8001a12: 4b32 ldr r3, [pc, #200] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001a14: 2201 movs r2, #1
|
|
8001a16: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001a18: e05b b.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
|
|
case ADS1015_START_CONVERSION:
|
|
state_timer = g_ms_counter;
|
|
8001a1a: 4b32 ldr r3, [pc, #200] @ (8001ae4 <ADS1015_Process_System+0x108>)
|
|
8001a1c: 681b ldr r3, [r3, #0]
|
|
8001a1e: 4a32 ldr r2, [pc, #200] @ (8001ae8 <ADS1015_Process_System+0x10c>)
|
|
8001a20: 6013 str r3, [r2, #0]
|
|
|
|
/* Escreve no Config Register (P[1:0]=01b) com OS=1 para
|
|
* iniciar a conversão single-shot. O bit OS só tem efeito
|
|
* quando o dispositivo está em power-down (seção 7.4.2.1) */
|
|
// Write config register to the ADC
|
|
writeRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG, ADS1015_CONFIG_START_SINGLE);
|
|
8001a22: f648 3203 movw r2, #35587 @ 0x8b03
|
|
8001a26: 2101 movs r1, #1
|
|
8001a28: 4830 ldr r0, [pc, #192] @ (8001aec <ADS1015_Process_System+0x110>)
|
|
8001a2a: f7ff ff71 bl 8001910 <writeRegister>
|
|
|
|
ads1015_state = ADS1015_WAIT_CONVERSION;
|
|
8001a2e: 4b2b ldr r3, [pc, #172] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001a30: 2202 movs r2, #2
|
|
8001a32: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001a34: e04d b.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
* 0b = dispositivo ainda convertendo
|
|
* 1b = conversão concluída, dado pronto no Conversion Register
|
|
* (Tabela 8-4, descrição do bit OS)
|
|
*/
|
|
|
|
config_reg = readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONFIG);
|
|
8001a36: 2101 movs r1, #1
|
|
8001a38: 482c ldr r0, [pc, #176] @ (8001aec <ADS1015_Process_System+0x110>)
|
|
8001a3a: f7ff ff8a bl 8001952 <readRegister>
|
|
8001a3e: 4603 mov r3, r0
|
|
8001a40: 80fb strh r3, [r7, #6]
|
|
|
|
if (((config_reg & ADS1015_REG_CONFIG_OS_SINGLE) != 0) && (g_ms_counter - state_timer)>ADS1015_TIME_PER_SAMPLE)
|
|
8001a42: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
8001a46: 2b00 cmp r3, #0
|
|
8001a48: da40 bge.n 8001acc <ADS1015_Process_System+0xf0>
|
|
8001a4a: 4b26 ldr r3, [pc, #152] @ (8001ae4 <ADS1015_Process_System+0x108>)
|
|
8001a4c: 681a ldr r2, [r3, #0]
|
|
8001a4e: 4b26 ldr r3, [pc, #152] @ (8001ae8 <ADS1015_Process_System+0x10c>)
|
|
8001a50: 681b ldr r3, [r3, #0]
|
|
8001a52: 1ad3 subs r3, r2, r3
|
|
8001a54: 2b09 cmp r3, #9
|
|
8001a56: d939 bls.n 8001acc <ADS1015_Process_System+0xf0>
|
|
{
|
|
ads1015_state = ADS1015_READ_DATA;
|
|
8001a58: 4b20 ldr r3, [pc, #128] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001a5a: 2203 movs r2, #3
|
|
8001a5c: 701a strb r2, [r3, #0]
|
|
}
|
|
// (opcional) tratar timeout comparando g_ms_counter - state_timer
|
|
// Datasheet: conversão single-cycle, tempo = 1/DR (ex: 1600SPS ≈ 625µs)
|
|
break;
|
|
8001a5e: e035 b.n 8001acc <ADS1015_Process_System+0xf0>
|
|
case ADS1015_READ_DATA:
|
|
{
|
|
/* Muda o Address Pointer para o Conversion Register (P[1:0]=00b)
|
|
* e lê os 16 bits. Dado é 12 bits em complemento de 2,
|
|
* left-justified em D[15:4]; D[3:0] sempre lê 0h (Tabela 8-3) */
|
|
int16_t raw = (int16_t)readRegister(&i2c_ads1015, ADS1015_REG_POINTER_CONVERT);
|
|
8001a60: 2100 movs r1, #0
|
|
8001a62: 4822 ldr r0, [pc, #136] @ (8001aec <ADS1015_Process_System+0x110>)
|
|
8001a64: f7ff ff75 bl 8001952 <readRegister>
|
|
8001a68: 4603 mov r3, r0
|
|
8001a6a: 80bb strh r3, [r7, #4]
|
|
raw >>= 4; // remove os 4 bits reservados (D[3:0]), resultado = 12 bits signed
|
|
8001a6c: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
8001a70: 111b asrs r3, r3, #4
|
|
8001a72: 80bb strh r3, [r7, #4]
|
|
|
|
float value = (float)(4096 - raw); // ((float)raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX; // usa FSR configurado no PGA
|
|
8001a74: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
8001a78: f5c3 5380 rsb r3, r3, #4096 @ 0x1000
|
|
8001a7c: 4618 mov r0, r3
|
|
8001a7e: f7fe ffbd bl 80009fc <__aeabi_i2f>
|
|
8001a82: 4603 mov r3, r0
|
|
8001a84: 603b str r3, [r7, #0]
|
|
|
|
ADS1015_pH_NewSample(value);
|
|
8001a86: 6838 ldr r0, [r7, #0]
|
|
8001a88: f000 f98c bl 8001da4 <ADS1015_pH_NewSample>
|
|
|
|
sample_count++;
|
|
8001a8c: 4b14 ldr r3, [pc, #80] @ (8001ae0 <ADS1015_Process_System+0x104>)
|
|
8001a8e: 681b ldr r3, [r3, #0]
|
|
8001a90: 3301 adds r3, #1
|
|
8001a92: 4a13 ldr r2, [pc, #76] @ (8001ae0 <ADS1015_Process_System+0x104>)
|
|
8001a94: 6013 str r3, [r2, #0]
|
|
|
|
if (sample_count >= ADS1015_BURST_SIZE)
|
|
8001a96: 4b12 ldr r3, [pc, #72] @ (8001ae0 <ADS1015_Process_System+0x104>)
|
|
8001a98: 681b ldr r3, [r3, #0]
|
|
8001a9a: 2b04 cmp r3, #4
|
|
8001a9c: d903 bls.n 8001aa6 <ADS1015_Process_System+0xca>
|
|
{
|
|
ads1015_state = ADS1015_IDLE;
|
|
8001a9e: 4b0f ldr r3, [pc, #60] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001aa0: 2200 movs r2, #0
|
|
8001aa2: 701a strb r2, [r3, #0]
|
|
{
|
|
state_timer = g_ms_counter;
|
|
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
|
|
}
|
|
}
|
|
break;
|
|
8001aa4: e015 b.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
state_timer = g_ms_counter;
|
|
8001aa6: 4b0f ldr r3, [pc, #60] @ (8001ae4 <ADS1015_Process_System+0x108>)
|
|
8001aa8: 681b ldr r3, [r3, #0]
|
|
8001aaa: 4a0f ldr r2, [pc, #60] @ (8001ae8 <ADS1015_Process_System+0x10c>)
|
|
8001aac: 6013 str r3, [r2, #0]
|
|
ads1015_state = ADS1015_WAIT_NEXT_SAMPLE;
|
|
8001aae: 4b0b ldr r3, [pc, #44] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001ab0: 2204 movs r2, #4
|
|
8001ab2: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001ab4: e00d b.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
|
|
case ADS1015_WAIT_NEXT_SAMPLE:
|
|
if ((g_ms_counter - state_timer) >= ADS1015_TIME_PER_SAMPLE)
|
|
8001ab6: 4b0b ldr r3, [pc, #44] @ (8001ae4 <ADS1015_Process_System+0x108>)
|
|
8001ab8: 681a ldr r2, [r3, #0]
|
|
8001aba: 4b0b ldr r3, [pc, #44] @ (8001ae8 <ADS1015_Process_System+0x10c>)
|
|
8001abc: 681b ldr r3, [r3, #0]
|
|
8001abe: 1ad3 subs r3, r2, r3
|
|
8001ac0: 2b08 cmp r3, #8
|
|
8001ac2: d905 bls.n 8001ad0 <ADS1015_Process_System+0xf4>
|
|
{
|
|
ads1015_state = ADS1015_START_CONVERSION;
|
|
8001ac4: 4b05 ldr r3, [pc, #20] @ (8001adc <ADS1015_Process_System+0x100>)
|
|
8001ac6: 2201 movs r2, #1
|
|
8001ac8: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
8001aca: e001 b.n 8001ad0 <ADS1015_Process_System+0xf4>
|
|
break;
|
|
8001acc: bf00 nop
|
|
8001ace: e000 b.n 8001ad2 <ADS1015_Process_System+0xf6>
|
|
break;
|
|
8001ad0: bf00 nop
|
|
}
|
|
}
|
|
8001ad2: bf00 nop
|
|
8001ad4: 3708 adds r7, #8
|
|
8001ad6: 46bd mov sp, r7
|
|
8001ad8: bd80 pop {r7, pc}
|
|
8001ada: bf00 nop
|
|
8001adc: 20000210 .word 0x20000210
|
|
8001ae0: 20000214 .word 0x20000214
|
|
8001ae4: 20000084 .word 0x20000084
|
|
8001ae8: 20000218 .word 0x20000218
|
|
8001aec: 200001bc .word 0x200001bc
|
|
|
|
08001af0 <ADS1015_Sort_Array>:
|
|
/**
|
|
* Simple insertion sort - BURST_SIZE is small, so the cost is negligible
|
|
* and it avoids depending on qsort/heap allocation.
|
|
**/
|
|
void ADS1015_Sort_Array(float *v, uint8_t n)
|
|
{
|
|
8001af0: b580 push {r7, lr}
|
|
8001af2: b084 sub sp, #16
|
|
8001af4: af00 add r7, sp, #0
|
|
8001af6: 6078 str r0, [r7, #4]
|
|
8001af8: 460b mov r3, r1
|
|
8001afa: 70fb strb r3, [r7, #3]
|
|
for (uint8_t i = 1; i < n; i++)
|
|
8001afc: 2301 movs r3, #1
|
|
8001afe: 73fb strb r3, [r7, #15]
|
|
8001b00: e039 b.n 8001b76 <ADS1015_Sort_Array+0x86>
|
|
{
|
|
float key = v[i];
|
|
8001b02: 7bfb ldrb r3, [r7, #15]
|
|
8001b04: 009b lsls r3, r3, #2
|
|
8001b06: 687a ldr r2, [r7, #4]
|
|
8001b08: 4413 add r3, r2
|
|
8001b0a: 681b ldr r3, [r3, #0]
|
|
8001b0c: 60bb str r3, [r7, #8]
|
|
int8_t j = (int8_t)i - 1;
|
|
8001b0e: 7bfb ldrb r3, [r7, #15]
|
|
8001b10: 3b01 subs r3, #1
|
|
8001b12: b2db uxtb r3, r3
|
|
8001b14: 73bb strb r3, [r7, #14]
|
|
while (j >= 0 && v[j] > key)
|
|
8001b16: e012 b.n 8001b3e <ADS1015_Sort_Array+0x4e>
|
|
{
|
|
v[j + 1] = v[j];
|
|
8001b18: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b1c: 009b lsls r3, r3, #2
|
|
8001b1e: 687a ldr r2, [r7, #4]
|
|
8001b20: 441a add r2, r3
|
|
8001b22: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b26: 3301 adds r3, #1
|
|
8001b28: 009b lsls r3, r3, #2
|
|
8001b2a: 6879 ldr r1, [r7, #4]
|
|
8001b2c: 440b add r3, r1
|
|
8001b2e: 6812 ldr r2, [r2, #0]
|
|
8001b30: 601a str r2, [r3, #0]
|
|
j--;
|
|
8001b32: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b36: b2db uxtb r3, r3
|
|
8001b38: 3b01 subs r3, #1
|
|
8001b3a: b2db uxtb r3, r3
|
|
8001b3c: 73bb strb r3, [r7, #14]
|
|
while (j >= 0 && v[j] > key)
|
|
8001b3e: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b42: 2b00 cmp r3, #0
|
|
8001b44: db0c blt.n 8001b60 <ADS1015_Sort_Array+0x70>
|
|
8001b46: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b4a: 009b lsls r3, r3, #2
|
|
8001b4c: 687a ldr r2, [r7, #4]
|
|
8001b4e: 4413 add r3, r2
|
|
8001b50: 681b ldr r3, [r3, #0]
|
|
8001b52: 4619 mov r1, r3
|
|
8001b54: 68b8 ldr r0, [r7, #8]
|
|
8001b56: f7ff f943 bl 8000de0 <__aeabi_fcmplt>
|
|
8001b5a: 4603 mov r3, r0
|
|
8001b5c: 2b00 cmp r3, #0
|
|
8001b5e: d1db bne.n 8001b18 <ADS1015_Sort_Array+0x28>
|
|
}
|
|
v[j + 1] = key;
|
|
8001b60: f997 300e ldrsb.w r3, [r7, #14]
|
|
8001b64: 3301 adds r3, #1
|
|
8001b66: 009b lsls r3, r3, #2
|
|
8001b68: 687a ldr r2, [r7, #4]
|
|
8001b6a: 4413 add r3, r2
|
|
8001b6c: 68ba ldr r2, [r7, #8]
|
|
8001b6e: 601a str r2, [r3, #0]
|
|
for (uint8_t i = 1; i < n; i++)
|
|
8001b70: 7bfb ldrb r3, [r7, #15]
|
|
8001b72: 3301 adds r3, #1
|
|
8001b74: 73fb strb r3, [r7, #15]
|
|
8001b76: 7bfa ldrb r2, [r7, #15]
|
|
8001b78: 78fb ldrb r3, [r7, #3]
|
|
8001b7a: 429a cmp r2, r3
|
|
8001b7c: d3c1 bcc.n 8001b02 <ADS1015_Sort_Array+0x12>
|
|
}
|
|
}
|
|
8001b7e: bf00 nop
|
|
8001b80: bf00 nop
|
|
8001b82: 3710 adds r7, #16
|
|
8001b84: 46bd mov sp, r7
|
|
8001b86: bd80 pop {r7, pc}
|
|
|
|
08001b88 <ADS1015_Trimmed_Mean>:
|
|
* original order is not needed), discards TRIM_COUNT values from each
|
|
* end, and averages the remainder. Sorting in place avoids a temporary
|
|
* array and removes the need for memcpy()/string.h entirely.
|
|
**/
|
|
float ADS1015_Trimmed_Mean(float *buffer, uint8_t n, uint8_t trim)
|
|
{
|
|
8001b88: b580 push {r7, lr}
|
|
8001b8a: b086 sub sp, #24
|
|
8001b8c: af00 add r7, sp, #0
|
|
8001b8e: 6078 str r0, [r7, #4]
|
|
8001b90: 460b mov r3, r1
|
|
8001b92: 70fb strb r3, [r7, #3]
|
|
8001b94: 4613 mov r3, r2
|
|
8001b96: 70bb strb r3, [r7, #2]
|
|
ADS1015_Sort_Array(buffer, n);
|
|
8001b98: 78fb ldrb r3, [r7, #3]
|
|
8001b9a: 4619 mov r1, r3
|
|
8001b9c: 6878 ldr r0, [r7, #4]
|
|
8001b9e: f7ff ffa7 bl 8001af0 <ADS1015_Sort_Array>
|
|
|
|
uint8_t start = trim;
|
|
8001ba2: 78bb ldrb r3, [r7, #2]
|
|
8001ba4: 75fb strb r3, [r7, #23]
|
|
uint8_t end = n - trim; /* exclusive */
|
|
8001ba6: 78fa ldrb r2, [r7, #3]
|
|
8001ba8: 78bb ldrb r3, [r7, #2]
|
|
8001baa: 1ad3 subs r3, r2, r3
|
|
8001bac: 75bb strb r3, [r7, #22]
|
|
|
|
if (end <= start) /* guard against a misconfigured trim value */
|
|
8001bae: 7dba ldrb r2, [r7, #22]
|
|
8001bb0: 7dfb ldrb r3, [r7, #23]
|
|
8001bb2: 429a cmp r2, r3
|
|
8001bb4: d803 bhi.n 8001bbe <ADS1015_Trimmed_Mean+0x36>
|
|
{
|
|
start = 0;
|
|
8001bb6: 2300 movs r3, #0
|
|
8001bb8: 75fb strb r3, [r7, #23]
|
|
end = n;
|
|
8001bba: 78fb ldrb r3, [r7, #3]
|
|
8001bbc: 75bb strb r3, [r7, #22]
|
|
}
|
|
|
|
float sum = 0.0f;
|
|
8001bbe: f04f 0300 mov.w r3, #0
|
|
8001bc2: 613b str r3, [r7, #16]
|
|
uint8_t count = 0;
|
|
8001bc4: 2300 movs r3, #0
|
|
8001bc6: 73fb strb r3, [r7, #15]
|
|
for (uint8_t i = start; i < end; i++)
|
|
8001bc8: 7dfb ldrb r3, [r7, #23]
|
|
8001bca: 73bb strb r3, [r7, #14]
|
|
8001bcc: e010 b.n 8001bf0 <ADS1015_Trimmed_Mean+0x68>
|
|
{
|
|
sum += buffer[i];
|
|
8001bce: 7bbb ldrb r3, [r7, #14]
|
|
8001bd0: 009b lsls r3, r3, #2
|
|
8001bd2: 687a ldr r2, [r7, #4]
|
|
8001bd4: 4413 add r3, r2
|
|
8001bd6: 681b ldr r3, [r3, #0]
|
|
8001bd8: 4619 mov r1, r3
|
|
8001bda: 6938 ldr r0, [r7, #16]
|
|
8001bdc: f7fe fe5a bl 8000894 <__addsf3>
|
|
8001be0: 4603 mov r3, r0
|
|
8001be2: 613b str r3, [r7, #16]
|
|
count++;
|
|
8001be4: 7bfb ldrb r3, [r7, #15]
|
|
8001be6: 3301 adds r3, #1
|
|
8001be8: 73fb strb r3, [r7, #15]
|
|
for (uint8_t i = start; i < end; i++)
|
|
8001bea: 7bbb ldrb r3, [r7, #14]
|
|
8001bec: 3301 adds r3, #1
|
|
8001bee: 73bb strb r3, [r7, #14]
|
|
8001bf0: 7bba ldrb r2, [r7, #14]
|
|
8001bf2: 7dbb ldrb r3, [r7, #22]
|
|
8001bf4: 429a cmp r2, r3
|
|
8001bf6: d3ea bcc.n 8001bce <ADS1015_Trimmed_Mean+0x46>
|
|
}
|
|
return sum / (float)count;
|
|
8001bf8: 7bfb ldrb r3, [r7, #15]
|
|
8001bfa: 4618 mov r0, r3
|
|
8001bfc: f7fe fefa bl 80009f4 <__aeabi_ui2f>
|
|
8001c00: 4603 mov r3, r0
|
|
8001c02: 4619 mov r1, r3
|
|
8001c04: 6938 ldr r0, [r7, #16]
|
|
8001c06: f7ff f801 bl 8000c0c <__aeabi_fdiv>
|
|
8001c0a: 4603 mov r3, r0
|
|
}
|
|
8001c0c: 4618 mov r0, r3
|
|
8001c0e: 3718 adds r7, #24
|
|
8001c10: 46bd mov sp, r7
|
|
8001c12: bd80 pop {r7, pc}
|
|
|
|
08001c14 <ADS1015_History_Average>:
|
|
|
|
/*
|
|
* Simple average of the history buffer (stage-2 sliding window)
|
|
*/
|
|
float ADS1015_History_Average(const float *hist, uint8_t n)
|
|
{
|
|
8001c14: b580 push {r7, lr}
|
|
8001c16: b084 sub sp, #16
|
|
8001c18: af00 add r7, sp, #0
|
|
8001c1a: 6078 str r0, [r7, #4]
|
|
8001c1c: 460b mov r3, r1
|
|
8001c1e: 70fb strb r3, [r7, #3]
|
|
float sum = 0.0f;
|
|
8001c20: f04f 0300 mov.w r3, #0
|
|
8001c24: 60fb str r3, [r7, #12]
|
|
for (uint8_t i = 0; i < n; i++)
|
|
8001c26: 2300 movs r3, #0
|
|
8001c28: 72fb strb r3, [r7, #11]
|
|
8001c2a: e00d b.n 8001c48 <ADS1015_History_Average+0x34>
|
|
sum += hist[i];
|
|
8001c2c: 7afb ldrb r3, [r7, #11]
|
|
8001c2e: 009b lsls r3, r3, #2
|
|
8001c30: 687a ldr r2, [r7, #4]
|
|
8001c32: 4413 add r3, r2
|
|
8001c34: 681b ldr r3, [r3, #0]
|
|
8001c36: 4619 mov r1, r3
|
|
8001c38: 68f8 ldr r0, [r7, #12]
|
|
8001c3a: f7fe fe2b bl 8000894 <__addsf3>
|
|
8001c3e: 4603 mov r3, r0
|
|
8001c40: 60fb str r3, [r7, #12]
|
|
for (uint8_t i = 0; i < n; i++)
|
|
8001c42: 7afb ldrb r3, [r7, #11]
|
|
8001c44: 3301 adds r3, #1
|
|
8001c46: 72fb strb r3, [r7, #11]
|
|
8001c48: 7afa ldrb r2, [r7, #11]
|
|
8001c4a: 78fb ldrb r3, [r7, #3]
|
|
8001c4c: 429a cmp r2, r3
|
|
8001c4e: d3ed bcc.n 8001c2c <ADS1015_History_Average+0x18>
|
|
return sum / (float)n;
|
|
8001c50: 78fb ldrb r3, [r7, #3]
|
|
8001c52: 4618 mov r0, r3
|
|
8001c54: f7fe fece bl 80009f4 <__aeabi_ui2f>
|
|
8001c58: 4603 mov r3, r0
|
|
8001c5a: 4619 mov r1, r3
|
|
8001c5c: 68f8 ldr r0, [r7, #12]
|
|
8001c5e: f7fe ffd5 bl 8000c0c <__aeabi_fdiv>
|
|
8001c62: 4603 mov r3, r0
|
|
}
|
|
8001c64: 4618 mov r0, r3
|
|
8001c66: 3710 adds r7, #16
|
|
8001c68: 46bd mov sp, r7
|
|
8001c6a: bd80 pop {r7, pc}
|
|
|
|
08001c6c <ADS1015_Process_Sample>:
|
|
* Common processing core: applied identically to all 3 channels.
|
|
* Receives the current raw reading and the channel's state (global
|
|
* arrays/struct).
|
|
**/
|
|
void ADS1015_Process_Sample(ADS1015_filter_t *ch, float raw)
|
|
{
|
|
8001c6c: b590 push {r4, r7, lr}
|
|
8001c6e: b085 sub sp, #20
|
|
8001c70: af00 add r7, sp, #0
|
|
8001c72: 6078 str r0, [r7, #4]
|
|
8001c74: 6039 str r1, [r7, #0]
|
|
/* --- Stage 1: accumulate into the current burst --- */
|
|
ch->burst[ch->burst_index] = raw;
|
|
8001c76: 687b ldr r3, [r7, #4]
|
|
8001c78: 7d1b ldrb r3, [r3, #20]
|
|
8001c7a: 4619 mov r1, r3
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
8001c7e: 683a ldr r2, [r7, #0]
|
|
8001c80: f843 2021 str.w r2, [r3, r1, lsl #2]
|
|
ch->burst_index++;
|
|
8001c84: 687b ldr r3, [r7, #4]
|
|
8001c86: 7d1b ldrb r3, [r3, #20]
|
|
8001c88: 3301 adds r3, #1
|
|
8001c8a: b2da uxtb r2, r3
|
|
8001c8c: 687b ldr r3, [r7, #4]
|
|
8001c8e: 751a strb r2, [r3, #20]
|
|
|
|
if (ch->burst_index < ADS1015_BURST_SIZE)
|
|
8001c90: 687b ldr r3, [r7, #4]
|
|
8001c92: 7d1b ldrb r3, [r3, #20]
|
|
8001c94: 2b04 cmp r3, #4
|
|
8001c96: d97a bls.n 8001d8e <ADS1015_Process_Sample+0x122>
|
|
return; /* still collecting the burst, nothing else to do */
|
|
|
|
/* Burst complete: compute the trimmed mean */
|
|
float burst_result = ADS1015_Trimmed_Mean(ch->burst, ADS1015_BURST_SIZE, ADS1015_TRIM_COUNT);
|
|
8001c98: 687b ldr r3, [r7, #4]
|
|
8001c9a: 2201 movs r2, #1
|
|
8001c9c: 2105 movs r1, #5
|
|
8001c9e: 4618 mov r0, r3
|
|
8001ca0: f7ff ff72 bl 8001b88 <ADS1015_Trimmed_Mean>
|
|
8001ca4: 60f8 str r0, [r7, #12]
|
|
ch->burst_index = 0; /* reset for the next burst */
|
|
8001ca6: 687b ldr r3, [r7, #4]
|
|
8001ca8: 2200 movs r2, #0
|
|
8001caa: 751a strb r2, [r3, #20]
|
|
|
|
/* --- Stage 2a: rolling history / sliding window --- */
|
|
ch->history[ch->history_index] = burst_result;
|
|
8001cac: 687b ldr r3, [r7, #4]
|
|
8001cae: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
8001cb2: 461a mov r2, r3
|
|
8001cb4: 687b ldr r3, [r7, #4]
|
|
8001cb6: 3206 adds r2, #6
|
|
8001cb8: 68f9 ldr r1, [r7, #12]
|
|
8001cba: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
ch->history_index = (uint8_t)((ch->history_index + 1) % ADS1015_HISTORY_SIZE);
|
|
8001cbe: 687b ldr r3, [r7, #4]
|
|
8001cc0: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
8001cc4: 1c5a adds r2, r3, #1
|
|
8001cc6: 4b34 ldr r3, [pc, #208] @ (8001d98 <ADS1015_Process_Sample+0x12c>)
|
|
8001cc8: fb83 3102 smull r3, r1, r3, r2
|
|
8001ccc: 17d3 asrs r3, r2, #31
|
|
8001cce: 1ac9 subs r1, r1, r3
|
|
8001cd0: 460b mov r3, r1
|
|
8001cd2: 005b lsls r3, r3, #1
|
|
8001cd4: 440b add r3, r1
|
|
8001cd6: 005b lsls r3, r3, #1
|
|
8001cd8: 1ad1 subs r1, r2, r3
|
|
8001cda: b2ca uxtb r2, r1
|
|
8001cdc: 687b ldr r3, [r7, #4]
|
|
8001cde: f883 2030 strb.w r2, [r3, #48] @ 0x30
|
|
if (ch->history_count < ADS1015_HISTORY_SIZE)
|
|
8001ce2: 687b ldr r3, [r7, #4]
|
|
8001ce4: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
8001ce8: 2b05 cmp r3, #5
|
|
8001cea: d807 bhi.n 8001cfc <ADS1015_Process_Sample+0x90>
|
|
ch->history_count++;
|
|
8001cec: 687b ldr r3, [r7, #4]
|
|
8001cee: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
8001cf2: 3301 adds r3, #1
|
|
8001cf4: b2da uxtb r2, r3
|
|
8001cf6: 687b ldr r3, [r7, #4]
|
|
8001cf8: f883 2031 strb.w r2, [r3, #49] @ 0x31
|
|
|
|
float window_average = ADS1015_History_Average(ch->history, ch->history_count);
|
|
8001cfc: 687b ldr r3, [r7, #4]
|
|
8001cfe: f103 0218 add.w r2, r3, #24
|
|
8001d02: 687b ldr r3, [r7, #4]
|
|
8001d04: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
8001d08: 4619 mov r1, r3
|
|
8001d0a: 4610 mov r0, r2
|
|
8001d0c: f7ff ff82 bl 8001c14 <ADS1015_History_Average>
|
|
8001d10: 60b8 str r0, [r7, #8]
|
|
|
|
/* --- Stage 2b: first-order IIR low-pass filter on the burst result --- */
|
|
if (!ch->iir_initialized)
|
|
8001d12: 687b ldr r3, [r7, #4]
|
|
8001d14: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8001d18: 2b00 cmp r3, #0
|
|
8001d1a: d107 bne.n 8001d2c <ADS1015_Process_Sample+0xc0>
|
|
{
|
|
ch->iir_state = burst_result;
|
|
8001d1c: 687b ldr r3, [r7, #4]
|
|
8001d1e: 68fa ldr r2, [r7, #12]
|
|
8001d20: 635a str r2, [r3, #52] @ 0x34
|
|
ch->iir_initialized = 1;
|
|
8001d22: 687b ldr r3, [r7, #4]
|
|
8001d24: 2201 movs r2, #1
|
|
8001d26: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
8001d2a: e014 b.n 8001d56 <ADS1015_Process_Sample+0xea>
|
|
}
|
|
else
|
|
{
|
|
ch->iir_state = ADS1015_IIR_ALPHA * burst_result + (1.0f - ADS1015_IIR_ALPHA) * ch->iir_state;
|
|
8001d2c: 491b ldr r1, [pc, #108] @ (8001d9c <ADS1015_Process_Sample+0x130>)
|
|
8001d2e: 68f8 ldr r0, [r7, #12]
|
|
8001d30: f7fe feb8 bl 8000aa4 <__aeabi_fmul>
|
|
8001d34: 4603 mov r3, r0
|
|
8001d36: 461c mov r4, r3
|
|
8001d38: 687b ldr r3, [r7, #4]
|
|
8001d3a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001d3c: 4918 ldr r1, [pc, #96] @ (8001da0 <ADS1015_Process_Sample+0x134>)
|
|
8001d3e: 4618 mov r0, r3
|
|
8001d40: f7fe feb0 bl 8000aa4 <__aeabi_fmul>
|
|
8001d44: 4603 mov r3, r0
|
|
8001d46: 4619 mov r1, r3
|
|
8001d48: 4620 mov r0, r4
|
|
8001d4a: f7fe fda3 bl 8000894 <__addsf3>
|
|
8001d4e: 4603 mov r3, r0
|
|
8001d50: 461a mov r2, r3
|
|
8001d52: 687b ldr r3, [r7, #4]
|
|
8001d54: 635a str r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
/* Final output: combines the IIR state (fast response to real drift)
|
|
* with the window average (more stable, slower response). Adjust
|
|
* the weighting per channel if needed. */
|
|
ch->filtered_value = 0.5f * ch->iir_state + 0.5f * window_average;
|
|
8001d56: 687b ldr r3, [r7, #4]
|
|
8001d58: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001d5a: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
|
|
8001d5e: 4618 mov r0, r3
|
|
8001d60: f7fe fea0 bl 8000aa4 <__aeabi_fmul>
|
|
8001d64: 4603 mov r3, r0
|
|
8001d66: 461c mov r4, r3
|
|
8001d68: f04f 517c mov.w r1, #1056964608 @ 0x3f000000
|
|
8001d6c: 68b8 ldr r0, [r7, #8]
|
|
8001d6e: f7fe fe99 bl 8000aa4 <__aeabi_fmul>
|
|
8001d72: 4603 mov r3, r0
|
|
8001d74: 4619 mov r1, r3
|
|
8001d76: 4620 mov r0, r4
|
|
8001d78: f7fe fd8c bl 8000894 <__addsf3>
|
|
8001d7c: 4603 mov r3, r0
|
|
8001d7e: 461a mov r2, r3
|
|
8001d80: 687b ldr r3, [r7, #4]
|
|
8001d82: 63da str r2, [r3, #60] @ 0x3c
|
|
ch->value_valid = 1;
|
|
8001d84: 687b ldr r3, [r7, #4]
|
|
8001d86: 2201 movs r2, #1
|
|
8001d88: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8001d8c: e000 b.n 8001d90 <ADS1015_Process_Sample+0x124>
|
|
return; /* still collecting the burst, nothing else to do */
|
|
8001d8e: bf00 nop
|
|
}
|
|
8001d90: 3714 adds r7, #20
|
|
8001d92: 46bd mov sp, r7
|
|
8001d94: bd90 pop {r4, r7, pc}
|
|
8001d96: bf00 nop
|
|
8001d98: 2aaaaaab .word 0x2aaaaaab
|
|
8001d9c: 3ecccccd .word 0x3ecccccd
|
|
8001da0: 3f19999a .word 0x3f19999a
|
|
|
|
08001da4 <ADS1015_pH_NewSample>:
|
|
/* PUBLIC FUNCTIONS - ONE PER CHANNEL */
|
|
/* ---------------------------------------------------------------------- */
|
|
|
|
|
|
void ADS1015_pH_NewSample(float raw)
|
|
{
|
|
8001da4: b580 push {r7, lr}
|
|
8001da6: b082 sub sp, #8
|
|
8001da8: af00 add r7, sp, #0
|
|
8001daa: 6078 str r0, [r7, #4]
|
|
ADS1015_Process_Sample(&g_ph_filter, raw);
|
|
8001dac: 6879 ldr r1, [r7, #4]
|
|
8001dae: 4803 ldr r0, [pc, #12] @ (8001dbc <ADS1015_pH_NewSample+0x18>)
|
|
8001db0: f7ff ff5c bl 8001c6c <ADS1015_Process_Sample>
|
|
}
|
|
8001db4: bf00 nop
|
|
8001db6: 3708 adds r7, #8
|
|
8001db8: 46bd mov sp, r7
|
|
8001dba: bd80 pop {r7, pc}
|
|
8001dbc: 200001cc .word 0x200001cc
|
|
|
|
08001dc0 <digital_outputs_init>:
|
|
* @brief Initializes the GPIO hardware and sets initial states.
|
|
* @note This function replaces the handle-based init.
|
|
* @retval None
|
|
*/
|
|
void digital_outputs_init(void)
|
|
{
|
|
8001dc0: b580 push {r7, lr}
|
|
8001dc2: b086 sub sp, #24
|
|
8001dc4: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001dc6: 1d3b adds r3, r7, #4
|
|
8001dc8: 2200 movs r2, #0
|
|
8001dca: 601a str r2, [r3, #0]
|
|
8001dcc: 605a str r2, [r3, #4]
|
|
8001dce: 609a str r2, [r3, #8]
|
|
8001dd0: 60da str r2, [r3, #12]
|
|
|
|
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
|
|
8001dd2: 2300 movs r3, #0
|
|
8001dd4: 617b str r3, [r7, #20]
|
|
8001dd6: e029 b.n 8001e2c <digital_outputs_init+0x6c>
|
|
GPIO_InitStruct.Pin = output_pins[i].pin;
|
|
8001dd8: 4a18 ldr r2, [pc, #96] @ (8001e3c <digital_outputs_init+0x7c>)
|
|
8001dda: 697b ldr r3, [r7, #20]
|
|
8001ddc: 00db lsls r3, r3, #3
|
|
8001dde: 4413 add r3, r2
|
|
8001de0: 889b ldrh r3, [r3, #4]
|
|
8001de2: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain
|
|
8001de4: 2311 movs r3, #17
|
|
8001de6: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001de8: 2300 movs r3, #0
|
|
8001dea: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001dec: 2302 movs r3, #2
|
|
8001dee: 613b str r3, [r7, #16]
|
|
|
|
HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
|
|
8001df0: 4a12 ldr r2, [pc, #72] @ (8001e3c <digital_outputs_init+0x7c>)
|
|
8001df2: 697b ldr r3, [r7, #20]
|
|
8001df4: f852 3033 ldr.w r3, [r2, r3, lsl #3]
|
|
8001df8: 1d3a adds r2, r7, #4
|
|
8001dfa: 4611 mov r1, r2
|
|
8001dfc: 4618 mov r0, r3
|
|
8001dfe: f001 fc03 bl 8003608 <HAL_GPIO_Init>
|
|
|
|
// Force initial state to LOW (Reset)
|
|
HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET);
|
|
8001e02: 4a0e ldr r2, [pc, #56] @ (8001e3c <digital_outputs_init+0x7c>)
|
|
8001e04: 697b ldr r3, [r7, #20]
|
|
8001e06: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8001e0a: 4a0c ldr r2, [pc, #48] @ (8001e3c <digital_outputs_init+0x7c>)
|
|
8001e0c: 697b ldr r3, [r7, #20]
|
|
8001e0e: 00db lsls r3, r3, #3
|
|
8001e10: 4413 add r3, r2
|
|
8001e12: 889b ldrh r3, [r3, #4]
|
|
8001e14: 2200 movs r2, #0
|
|
8001e16: 4619 mov r1, r3
|
|
8001e18: f001 fd91 bl 800393e <HAL_GPIO_WritePin>
|
|
pin_states[i] = 0;
|
|
8001e1c: 4a08 ldr r2, [pc, #32] @ (8001e40 <digital_outputs_init+0x80>)
|
|
8001e1e: 697b ldr r3, [r7, #20]
|
|
8001e20: 4413 add r3, r2
|
|
8001e22: 2200 movs r2, #0
|
|
8001e24: 701a strb r2, [r3, #0]
|
|
for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
|
|
8001e26: 697b ldr r3, [r7, #20]
|
|
8001e28: 3301 adds r3, #1
|
|
8001e2a: 617b str r3, [r7, #20]
|
|
8001e2c: 697b ldr r3, [r7, #20]
|
|
8001e2e: 2b07 cmp r3, #7
|
|
8001e30: ddd2 ble.n 8001dd8 <digital_outputs_init+0x18>
|
|
}
|
|
}
|
|
8001e32: bf00 nop
|
|
8001e34: bf00 nop
|
|
8001e36: 3718 adds r7, #24
|
|
8001e38: 46bd mov sp, r7
|
|
8001e3a: bd80 pop {r7, pc}
|
|
8001e3c: 08006a28 .word 0x08006a28
|
|
8001e40: 2000021c .word 0x2000021c
|
|
|
|
08001e44 <Flash_Load_Page>:
|
|
}
|
|
|
|
/**
|
|
* @brief Lê a página da Flash para a RAM.
|
|
*/
|
|
HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest) {
|
|
8001e44: b580 push {r7, lr}
|
|
8001e46: b082 sub sp, #8
|
|
8001e48: af00 add r7, sp, #0
|
|
8001e4a: 6078 str r0, [r7, #4]
|
|
if (pDest == NULL) return HAL_ERROR;
|
|
8001e4c: 687b ldr r3, [r7, #4]
|
|
8001e4e: 2b00 cmp r3, #0
|
|
8001e50: d101 bne.n 8001e56 <Flash_Load_Page+0x12>
|
|
8001e52: 2301 movs r3, #1
|
|
8001e54: e00d b.n 8001e72 <Flash_Load_Page+0x2e>
|
|
|
|
// Leitura direta por memcpy (A Flash é mapeada no espaço de endereçamento comum)
|
|
memcpy(pDest, (void *)FLASH_PAGE_ADDR, FLASH_PAGE_SIZE);
|
|
8001e56: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001e5a: 4908 ldr r1, [pc, #32] @ (8001e7c <Flash_Load_Page+0x38>)
|
|
8001e5c: 6878 ldr r0, [r7, #4]
|
|
8001e5e: f004 fcd5 bl 800680c <memcpy>
|
|
|
|
// Validação da integridade através do Magic Number
|
|
if (pDest->magic_number != 0xDEADBEEF) {
|
|
8001e62: 687b ldr r3, [r7, #4]
|
|
8001e64: 681b ldr r3, [r3, #0]
|
|
8001e66: 4a06 ldr r2, [pc, #24] @ (8001e80 <Flash_Load_Page+0x3c>)
|
|
8001e68: 4293 cmp r3, r2
|
|
8001e6a: d001 beq.n 8001e70 <Flash_Load_Page+0x2c>
|
|
return HAL_ERROR;
|
|
8001e6c: 2301 movs r3, #1
|
|
8001e6e: e000 b.n 8001e72 <Flash_Load_Page+0x2e>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001e70: 2300 movs r3, #0
|
|
}
|
|
8001e72: 4618 mov r0, r3
|
|
8001e74: 3708 adds r7, #8
|
|
8001e76: 46bd mov sp, r7
|
|
8001e78: bd80 pop {r7, pc}
|
|
8001e7a: bf00 nop
|
|
8001e7c: 0800fc00 .word 0x0800fc00
|
|
8001e80: deadbeef .word 0xdeadbeef
|
|
|
|
08001e84 <MX_GPIO_Init>:
|
|
* EXTI
|
|
* Free pins are configured automatically as Analog (this feature is enabled through
|
|
* the Code Generation settings)
|
|
*/
|
|
void MX_GPIO_Init(void)
|
|
{
|
|
8001e84: b580 push {r7, lr}
|
|
8001e86: b088 sub sp, #32
|
|
8001e88: af00 add r7, sp, #0
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001e8a: f107 0310 add.w r3, r7, #16
|
|
8001e8e: 2200 movs r2, #0
|
|
8001e90: 601a str r2, [r3, #0]
|
|
8001e92: 605a str r2, [r3, #4]
|
|
8001e94: 609a str r2, [r3, #8]
|
|
8001e96: 60da str r2, [r3, #12]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001e98: 4b46 ldr r3, [pc, #280] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001e9a: 699b ldr r3, [r3, #24]
|
|
8001e9c: 4a45 ldr r2, [pc, #276] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001e9e: f043 0310 orr.w r3, r3, #16
|
|
8001ea2: 6193 str r3, [r2, #24]
|
|
8001ea4: 4b43 ldr r3, [pc, #268] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ea6: 699b ldr r3, [r3, #24]
|
|
8001ea8: f003 0310 and.w r3, r3, #16
|
|
8001eac: 60fb str r3, [r7, #12]
|
|
8001eae: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8001eb0: 4b40 ldr r3, [pc, #256] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001eb2: 699b ldr r3, [r3, #24]
|
|
8001eb4: 4a3f ldr r2, [pc, #252] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001eb6: f043 0320 orr.w r3, r3, #32
|
|
8001eba: 6193 str r3, [r2, #24]
|
|
8001ebc: 4b3d ldr r3, [pc, #244] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ebe: 699b ldr r3, [r3, #24]
|
|
8001ec0: f003 0320 and.w r3, r3, #32
|
|
8001ec4: 60bb str r3, [r7, #8]
|
|
8001ec6: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001ec8: 4b3a ldr r3, [pc, #232] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001eca: 699b ldr r3, [r3, #24]
|
|
8001ecc: 4a39 ldr r2, [pc, #228] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ece: f043 0304 orr.w r3, r3, #4
|
|
8001ed2: 6193 str r3, [r2, #24]
|
|
8001ed4: 4b37 ldr r3, [pc, #220] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ed6: 699b ldr r3, [r3, #24]
|
|
8001ed8: f003 0304 and.w r3, r3, #4
|
|
8001edc: 607b str r3, [r7, #4]
|
|
8001ede: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001ee0: 4b34 ldr r3, [pc, #208] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ee2: 699b ldr r3, [r3, #24]
|
|
8001ee4: 4a33 ldr r2, [pc, #204] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001ee6: f043 0308 orr.w r3, r3, #8
|
|
8001eea: 6193 str r3, [r2, #24]
|
|
8001eec: 4b31 ldr r3, [pc, #196] @ (8001fb4 <MX_GPIO_Init+0x130>)
|
|
8001eee: 699b ldr r3, [r3, #24]
|
|
8001ef0: f003 0308 and.w r3, r3, #8
|
|
8001ef4: 603b str r3, [r7, #0]
|
|
8001ef6: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
|
|
8001ef8: 2200 movs r2, #0
|
|
8001efa: f44f 4160 mov.w r1, #57344 @ 0xe000
|
|
8001efe: 482e ldr r0, [pc, #184] @ (8001fb8 <MX_GPIO_Init+0x134>)
|
|
8001f00: f001 fd1d bl 800393e <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
|
|
8001f04: 2200 movs r2, #0
|
|
8001f06: f240 3137 movw r1, #823 @ 0x337
|
|
8001f0a: 482c ldr r0, [pc, #176] @ (8001fbc <MX_GPIO_Init+0x138>)
|
|
8001f0c: f001 fd17 bl 800393e <HAL_GPIO_WritePin>
|
|
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
|
|
8001f10: 2200 movs r2, #0
|
|
8001f12: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8001f16: 482a ldr r0, [pc, #168] @ (8001fc0 <MX_GPIO_Init+0x13c>)
|
|
8001f18: f001 fd11 bl 800393e <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
|
|
GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
|
|
8001f1c: f44f 4360 mov.w r3, #57344 @ 0xe000
|
|
8001f20: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
|
8001f22: 2311 movs r3, #17
|
|
8001f24: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f26: 2300 movs r3, #0
|
|
8001f28: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001f2a: 2302 movs r3, #2
|
|
8001f2c: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001f2e: f107 0310 add.w r3, r7, #16
|
|
8001f32: 4619 mov r1, r3
|
|
8001f34: 4820 ldr r0, [pc, #128] @ (8001fb8 <MX_GPIO_Init+0x134>)
|
|
8001f36: f001 fb67 bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
|
|
SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
|
|
PG_PH_Pin */
|
|
GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
|
|
8001f3a: f648 13fc movw r3, #35324 @ 0x89fc
|
|
8001f3e: 613b str r3, [r7, #16]
|
|
|SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
|
|
|PG_PH_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001f40: 2300 movs r3, #0
|
|
8001f42: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8001f44: 2301 movs r3, #1
|
|
8001f46: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001f48: f107 0310 add.w r3, r7, #16
|
|
8001f4c: 4619 mov r1, r3
|
|
8001f4e: 481c ldr r0, [pc, #112] @ (8001fc0 <MX_GPIO_Init+0x13c>)
|
|
8001f50: f001 fb5a bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
|
|
LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
|
|
GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
|
|
8001f54: f240 3337 movw r3, #823 @ 0x337
|
|
8001f58: 613b str r3, [r7, #16]
|
|
|LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
|
8001f5a: 2311 movs r3, #17
|
|
8001f5c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f5e: 2300 movs r3, #0
|
|
8001f60: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001f62: 2302 movs r3, #2
|
|
8001f64: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001f66: f107 0310 add.w r3, r7, #16
|
|
8001f6a: 4619 mov r1, r3
|
|
8001f6c: 4813 ldr r0, [pc, #76] @ (8001fbc <MX_GPIO_Init+0x138>)
|
|
8001f6e: f001 fb4b bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin
|
|
Calib_PH_Pin */
|
|
GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin
|
|
8001f72: f24f 0308 movw r3, #61448 @ 0xf008
|
|
8001f76: 613b str r3, [r7, #16]
|
|
|Calib_PH_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001f78: 2300 movs r3, #0
|
|
8001f7a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8001f7c: 2301 movs r3, #1
|
|
8001f7e: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001f80: f107 0310 add.w r3, r7, #16
|
|
8001f84: 4619 mov r1, r3
|
|
8001f86: 480d ldr r0, [pc, #52] @ (8001fbc <MX_GPIO_Init+0x138>)
|
|
8001f88: f001 fb3e bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : TX_EN_RS485_Pin */
|
|
GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
|
|
8001f8c: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8001f90: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001f92: 2301 movs r3, #1
|
|
8001f94: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f96: 2300 movs r3, #0
|
|
8001f98: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001f9a: 2302 movs r3, #2
|
|
8001f9c: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
|
|
8001f9e: f107 0310 add.w r3, r7, #16
|
|
8001fa2: 4619 mov r1, r3
|
|
8001fa4: 4806 ldr r0, [pc, #24] @ (8001fc0 <MX_GPIO_Init+0x13c>)
|
|
8001fa6: f001 fb2f bl 8003608 <HAL_GPIO_Init>
|
|
|
|
}
|
|
8001faa: bf00 nop
|
|
8001fac: 3720 adds r7, #32
|
|
8001fae: 46bd mov sp, r7
|
|
8001fb0: bd80 pop {r7, pc}
|
|
8001fb2: bf00 nop
|
|
8001fb4: 40021000 .word 0x40021000
|
|
8001fb8: 40011000 .word 0x40011000
|
|
8001fbc: 40010c00 .word 0x40010c00
|
|
8001fc0: 40010800 .word 0x40010800
|
|
|
|
08001fc4 <MX_I2C1_Init>:
|
|
I2C_HandleTypeDef hi2c1;
|
|
I2C_HandleTypeDef hi2c2;
|
|
|
|
/* I2C1 init function */
|
|
void MX_I2C1_Init(void)
|
|
{
|
|
8001fc4: b580 push {r7, lr}
|
|
8001fc6: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8001fc8: 4b12 ldr r3, [pc, #72] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fca: 4a13 ldr r2, [pc, #76] @ (8002018 <MX_I2C1_Init+0x54>)
|
|
8001fcc: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
8001fce: 4b11 ldr r3, [pc, #68] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fd0: 4a12 ldr r2, [pc, #72] @ (800201c <MX_I2C1_Init+0x58>)
|
|
8001fd2: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
8001fd4: 4b0f ldr r3, [pc, #60] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fd6: 2200 movs r2, #0
|
|
8001fd8: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8001fda: 4b0e ldr r3, [pc, #56] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fdc: 2200 movs r2, #0
|
|
8001fde: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8001fe0: 4b0c ldr r3, [pc, #48] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fe2: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
8001fe6: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8001fe8: 4b0a ldr r3, [pc, #40] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001fea: 2200 movs r2, #0
|
|
8001fec: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8001fee: 4b09 ldr r3, [pc, #36] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001ff0: 2200 movs r2, #0
|
|
8001ff2: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8001ff4: 4b07 ldr r3, [pc, #28] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001ff6: 2200 movs r2, #0
|
|
8001ff8: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8001ffa: 4b06 ldr r3, [pc, #24] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8001ffc: 2200 movs r2, #0
|
|
8001ffe: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
8002000: 4804 ldr r0, [pc, #16] @ (8002014 <MX_I2C1_Init+0x50>)
|
|
8002002: f001 fccd bl 80039a0 <HAL_I2C_Init>
|
|
8002006: 4603 mov r3, r0
|
|
8002008: 2b00 cmp r3, #0
|
|
800200a: d001 beq.n 8002010 <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
800200c: f000 fc3e bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
8002010: bf00 nop
|
|
8002012: bd80 pop {r7, pc}
|
|
8002014: 20000624 .word 0x20000624
|
|
8002018: 40005400 .word 0x40005400
|
|
800201c: 000186a0 .word 0x000186a0
|
|
|
|
08002020 <MX_I2C2_Init>:
|
|
/* I2C2 init function */
|
|
void MX_I2C2_Init(void)
|
|
{
|
|
8002020: b580 push {r7, lr}
|
|
8002022: af00 add r7, sp, #0
|
|
/* USER CODE END I2C2_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C2_Init 1 */
|
|
|
|
/* USER CODE END I2C2_Init 1 */
|
|
hi2c2.Instance = I2C2;
|
|
8002024: 4b12 ldr r3, [pc, #72] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002026: 4a13 ldr r2, [pc, #76] @ (8002074 <MX_I2C2_Init+0x54>)
|
|
8002028: 601a str r2, [r3, #0]
|
|
hi2c2.Init.ClockSpeed = 100000;
|
|
800202a: 4b11 ldr r3, [pc, #68] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
800202c: 4a12 ldr r2, [pc, #72] @ (8002078 <MX_I2C2_Init+0x58>)
|
|
800202e: 605a str r2, [r3, #4]
|
|
hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
8002030: 4b0f ldr r3, [pc, #60] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002032: 2200 movs r2, #0
|
|
8002034: 609a str r2, [r3, #8]
|
|
hi2c2.Init.OwnAddress1 = 0;
|
|
8002036: 4b0e ldr r3, [pc, #56] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002038: 2200 movs r2, #0
|
|
800203a: 60da str r2, [r3, #12]
|
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
800203c: 4b0c ldr r3, [pc, #48] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
800203e: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
8002042: 611a str r2, [r3, #16]
|
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8002044: 4b0a ldr r3, [pc, #40] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002046: 2200 movs r2, #0
|
|
8002048: 615a str r2, [r3, #20]
|
|
hi2c2.Init.OwnAddress2 = 0;
|
|
800204a: 4b09 ldr r3, [pc, #36] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
800204c: 2200 movs r2, #0
|
|
800204e: 619a str r2, [r3, #24]
|
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8002050: 4b07 ldr r3, [pc, #28] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002052: 2200 movs r2, #0
|
|
8002054: 61da str r2, [r3, #28]
|
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8002056: 4b06 ldr r3, [pc, #24] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
8002058: 2200 movs r2, #0
|
|
800205a: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
|
800205c: 4804 ldr r0, [pc, #16] @ (8002070 <MX_I2C2_Init+0x50>)
|
|
800205e: f001 fc9f bl 80039a0 <HAL_I2C_Init>
|
|
8002062: 4603 mov r3, r0
|
|
8002064: 2b00 cmp r3, #0
|
|
8002066: d001 beq.n 800206c <MX_I2C2_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002068: f000 fc10 bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C2_Init 2 */
|
|
|
|
/* USER CODE END I2C2_Init 2 */
|
|
|
|
}
|
|
800206c: bf00 nop
|
|
800206e: bd80 pop {r7, pc}
|
|
8002070: 20000678 .word 0x20000678
|
|
8002074: 40005800 .word 0x40005800
|
|
8002078: 000186a0 .word 0x000186a0
|
|
|
|
0800207c <HAL_I2C_MspInit>:
|
|
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
|
|
{
|
|
800207c: b580 push {r7, lr}
|
|
800207e: b08a sub sp, #40 @ 0x28
|
|
8002080: af00 add r7, sp, #0
|
|
8002082: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002084: f107 0318 add.w r3, r7, #24
|
|
8002088: 2200 movs r2, #0
|
|
800208a: 601a str r2, [r3, #0]
|
|
800208c: 605a str r2, [r3, #4]
|
|
800208e: 609a str r2, [r3, #8]
|
|
8002090: 60da str r2, [r3, #12]
|
|
if(i2cHandle->Instance==I2C1)
|
|
8002092: 687b ldr r3, [r7, #4]
|
|
8002094: 681b ldr r3, [r3, #0]
|
|
8002096: 4a2b ldr r2, [pc, #172] @ (8002144 <HAL_I2C_MspInit+0xc8>)
|
|
8002098: 4293 cmp r3, r2
|
|
800209a: d124 bne.n 80020e6 <HAL_I2C_MspInit+0x6a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800209c: 4b2a ldr r3, [pc, #168] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
800209e: 699b ldr r3, [r3, #24]
|
|
80020a0: 4a29 ldr r2, [pc, #164] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020a2: f043 0308 orr.w r3, r3, #8
|
|
80020a6: 6193 str r3, [r2, #24]
|
|
80020a8: 4b27 ldr r3, [pc, #156] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020aa: 699b ldr r3, [r3, #24]
|
|
80020ac: f003 0308 and.w r3, r3, #8
|
|
80020b0: 617b str r3, [r7, #20]
|
|
80020b2: 697b ldr r3, [r7, #20]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
|
|
80020b4: 23c0 movs r3, #192 @ 0xc0
|
|
80020b6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80020b8: 2312 movs r3, #18
|
|
80020ba: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80020bc: 2302 movs r3, #2
|
|
80020be: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80020c0: f107 0318 add.w r3, r7, #24
|
|
80020c4: 4619 mov r1, r3
|
|
80020c6: 4821 ldr r0, [pc, #132] @ (800214c <HAL_I2C_MspInit+0xd0>)
|
|
80020c8: f001 fa9e bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/* I2C1 clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
80020cc: 4b1e ldr r3, [pc, #120] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020ce: 69db ldr r3, [r3, #28]
|
|
80020d0: 4a1d ldr r2, [pc, #116] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020d2: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
80020d6: 61d3 str r3, [r2, #28]
|
|
80020d8: 4b1b ldr r3, [pc, #108] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020da: 69db ldr r3, [r3, #28]
|
|
80020dc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80020e0: 613b str r3, [r7, #16]
|
|
80020e2: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
/* USER CODE BEGIN I2C2_MspInit 1 */
|
|
|
|
/* USER CODE END I2C2_MspInit 1 */
|
|
}
|
|
}
|
|
80020e4: e029 b.n 800213a <HAL_I2C_MspInit+0xbe>
|
|
else if(i2cHandle->Instance==I2C2)
|
|
80020e6: 687b ldr r3, [r7, #4]
|
|
80020e8: 681b ldr r3, [r3, #0]
|
|
80020ea: 4a19 ldr r2, [pc, #100] @ (8002150 <HAL_I2C_MspInit+0xd4>)
|
|
80020ec: 4293 cmp r3, r2
|
|
80020ee: d124 bne.n 800213a <HAL_I2C_MspInit+0xbe>
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80020f0: 4b15 ldr r3, [pc, #84] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020f2: 699b ldr r3, [r3, #24]
|
|
80020f4: 4a14 ldr r2, [pc, #80] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020f6: f043 0308 orr.w r3, r3, #8
|
|
80020fa: 6193 str r3, [r2, #24]
|
|
80020fc: 4b12 ldr r3, [pc, #72] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
80020fe: 699b ldr r3, [r3, #24]
|
|
8002100: f003 0308 and.w r3, r3, #8
|
|
8002104: 60fb str r3, [r7, #12]
|
|
8002106: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
|
|
8002108: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
800210c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
800210e: 2312 movs r3, #18
|
|
8002110: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002112: 2302 movs r3, #2
|
|
8002114: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002116: f107 0318 add.w r3, r7, #24
|
|
800211a: 4619 mov r1, r3
|
|
800211c: 480b ldr r0, [pc, #44] @ (800214c <HAL_I2C_MspInit+0xd0>)
|
|
800211e: f001 fa73 bl 8003608 <HAL_GPIO_Init>
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
8002122: 4b09 ldr r3, [pc, #36] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
8002124: 69db ldr r3, [r3, #28]
|
|
8002126: 4a08 ldr r2, [pc, #32] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
8002128: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
800212c: 61d3 str r3, [r2, #28]
|
|
800212e: 4b06 ldr r3, [pc, #24] @ (8002148 <HAL_I2C_MspInit+0xcc>)
|
|
8002130: 69db ldr r3, [r3, #28]
|
|
8002132: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8002136: 60bb str r3, [r7, #8]
|
|
8002138: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800213a: bf00 nop
|
|
800213c: 3728 adds r7, #40 @ 0x28
|
|
800213e: 46bd mov sp, r7
|
|
8002140: bd80 pop {r7, pc}
|
|
8002142: bf00 nop
|
|
8002144: 40005400 .word 0x40005400
|
|
8002148: 40021000 .word 0x40021000
|
|
800214c: 40010c00 .word 0x40010c00
|
|
8002150: 40005800 .word 0x40005800
|
|
|
|
08002154 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8002154: b580 push {r7, lr}
|
|
8002156: b08c sub sp, #48 @ 0x30
|
|
8002158: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 1 */
|
|
HAL_StatusTypeDef status0,status1;
|
|
|
|
|
|
// Variables to store previous LED states
|
|
uint8_t previous_green_state = 0;
|
|
800215a: 2300 movs r3, #0
|
|
800215c: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
uint8_t previous_red_state = 0;
|
|
8002160: 2300 movs r3, #0
|
|
8002162: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
|
|
uint8_t mux_connection = 0;
|
|
8002166: 2300 movs r3, #0
|
|
8002168: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
// Variables for timing
|
|
uint32_t previous_millis_green = 0;
|
|
800216c: 2300 movs r3, #0
|
|
800216e: 62bb str r3, [r7, #40] @ 0x28
|
|
uint32_t previous_millis_red = 0;
|
|
8002170: 2300 movs r3, #0
|
|
8002172: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
|
|
|
|
|
|
/*! Temporary variables */
|
|
uint8_t tempString[15] = {0};
|
|
8002174: 463b mov r3, r7
|
|
8002176: 2200 movs r2, #0
|
|
8002178: 601a str r2, [r3, #0]
|
|
800217a: 605a str r2, [r3, #4]
|
|
800217c: 609a str r2, [r3, #8]
|
|
800217e: f8c3 200b str.w r2, [r3, #11]
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8002182: f000 fe0d bl 8002da0 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8002186: f000 f939 bl 80023fc <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800218a: f7ff fe7b bl 8001e84 <MX_GPIO_Init>
|
|
MX_ADC1_Init();
|
|
800218e: f7ff fadd bl 800174c <MX_ADC1_Init>
|
|
MX_ADC2_Init();
|
|
8002192: f7ff fb19 bl 80017c8 <MX_ADC2_Init>
|
|
MX_I2C1_Init();
|
|
8002196: f7ff ff15 bl 8001fc4 <MX_I2C1_Init>
|
|
MX_I2C2_Init();
|
|
800219a: f7ff ff41 bl 8002020 <MX_I2C2_Init>
|
|
MX_USART1_UART_Init();
|
|
800219e: f000 fd5b bl 8002c58 <MX_USART1_UART_Init>
|
|
MX_TIM3_Init();
|
|
80021a2: f000 fce5 bl 8002b70 <MX_TIM3_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
|
|
|
|
Flash_Load_Page(&flash_data);
|
|
80021a6: 488a ldr r0, [pc, #552] @ (80023d0 <main+0x27c>)
|
|
80021a8: f7ff fe4c bl 8001e44 <Flash_Load_Page>
|
|
|
|
|
|
HAL_TIM_Base_Start_IT(&htim3);
|
|
80021ac: 4889 ldr r0, [pc, #548] @ (80023d4 <main+0x280>)
|
|
80021ae: f003 f943 bl 8005438 <HAL_TIM_Base_Start_IT>
|
|
/*
|
|
HAL_ADCEx_Calibration_Start(&hadc1);
|
|
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2); // Internal Temperature conversion
|
|
*/
|
|
|
|
digital_outputs_init();
|
|
80021b2: f7ff fe05 bl 8001dc0 <digital_outputs_init>
|
|
|
|
|
|
rs485_init();
|
|
80021b6: f000 fb7b bl 80028b0 <rs485_init>
|
|
|
|
ADS1015_Init(); // Initializes pH Measurement
|
|
80021ba: f7ff fbf5 bl 80019a8 <ADS1015_Init>
|
|
|
|
|
|
AD5934_Init(); // Initializes CE and RTD Measurement
|
|
80021be: f7fe fee7 bl 8000f90 <AD5934_Init>
|
|
*/
|
|
while (1)
|
|
{
|
|
|
|
|
|
AD5934_Process_System();
|
|
80021c2: f7fe ffff bl 80011c4 <AD5934_Process_System>
|
|
ADS1015_Process_System();
|
|
80021c6: f7ff fc09 bl 80019dc <ADS1015_Process_System>
|
|
|
|
current_millis = g_ms_counter;
|
|
80021ca: 4b83 ldr r3, [pc, #524] @ (80023d8 <main+0x284>)
|
|
80021cc: 681b ldr r3, [r3, #0]
|
|
80021ce: 61fb str r3, [r7, #28]
|
|
|
|
|
|
if((current_millis % 100) == 0) // Send data each 50ms
|
|
80021d0: 69fa ldr r2, [r7, #28]
|
|
80021d2: 4b82 ldr r3, [pc, #520] @ (80023dc <main+0x288>)
|
|
80021d4: fba3 1302 umull r1, r3, r3, r2
|
|
80021d8: 095b lsrs r3, r3, #5
|
|
80021da: 2164 movs r1, #100 @ 0x64
|
|
80021dc: fb01 f303 mul.w r3, r1, r3
|
|
80021e0: 1ad3 subs r3, r2, r3
|
|
80021e2: 2b00 cmp r3, #0
|
|
80021e4: f040 80da bne.w 800239c <main+0x248>
|
|
{
|
|
|
|
|
|
if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms
|
|
80021e8: 4b7d ldr r3, [pc, #500] @ (80023e0 <main+0x28c>)
|
|
80021ea: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80021ee: 2b00 cmp r3, #0
|
|
80021f0: d034 beq.n 800225c <main+0x108>
|
|
{
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
|
|
80021f2: 2180 movs r1, #128 @ 0x80
|
|
80021f4: 487b ldr r0, [pc, #492] @ (80023e4 <main+0x290>)
|
|
80021f6: f001 fb8b bl 8003910 <HAL_GPIO_ReadPin>
|
|
80021fa: 4603 mov r3, r0
|
|
80021fc: 2b01 cmp r3, #1
|
|
80021fe: d103 bne.n 8002208 <main+0xb4>
|
|
mux_connection = AD5934_CH_REF100R_LOW_GAIN; // 100 Ohms Reference Resistor
|
|
8002200: 2300 movs r3, #0
|
|
8002202: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
8002206: e002 b.n 800220e <main+0xba>
|
|
else
|
|
mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor
|
|
8002208: 2304 movs r3, #4
|
|
800220a: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, mux_connection);
|
|
800220e: 4b74 ldr r3, [pc, #464] @ (80023e0 <main+0x28c>)
|
|
8002210: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002212: f897 202f ldrb.w r2, [r7, #47] @ 0x2f
|
|
8002216: 4611 mov r1, r2
|
|
8002218: 4618 mov r0, r3
|
|
800221a: f7fe ff45 bl 80010a8 <AD5934_Compress_To_IntScale>
|
|
800221e: 4603 mov r3, r0
|
|
8002220: f5c3 5380 rsb r3, r3, #4096 @ 0x1000
|
|
8002224: 837b strh r3, [r7, #26]
|
|
intToStr(reference_final, tempString);
|
|
8002226: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
800222a: 463a mov r2, r7
|
|
800222c: 4611 mov r1, r2
|
|
800222e: 4618 mov r0, r3
|
|
8002230: f000 fa48 bl 80026c4 <intToStr>
|
|
// float ref_final = g_ref_filter.filtered_value;
|
|
//FloatToString(tempString, ref_final);
|
|
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
|
|
8002234: 463b mov r3, r7
|
|
8002236: 4618 mov r0, r3
|
|
8002238: f7fd ff88 bl 800014c <strlen>
|
|
800223c: 4603 mov r3, r0
|
|
800223e: b29a uxth r2, r3
|
|
8002240: 463b mov r3, r7
|
|
8002242: 4611 mov r1, r2
|
|
8002244: 4618 mov r0, r3
|
|
8002246: f000 fb5f bl 8002908 <rs485_send_broadcast>
|
|
rs485_send_broadcast(newline, (strlen((uint8_t*)newline)));
|
|
800224a: 4867 ldr r0, [pc, #412] @ (80023e8 <main+0x294>)
|
|
800224c: f7fd ff7e bl 800014c <strlen>
|
|
8002250: 4603 mov r3, r0
|
|
8002252: b29b uxth r3, r3
|
|
8002254: 4619 mov r1, r3
|
|
8002256: 4864 ldr r0, [pc, #400] @ (80023e8 <main+0x294>)
|
|
8002258: f000 fb56 bl 8002908 <rs485_send_broadcast>
|
|
}
|
|
|
|
if (g_ec_filter.value_valid) // EC
|
|
800225c: 4b63 ldr r3, [pc, #396] @ (80023ec <main+0x298>)
|
|
800225e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8002262: 2b00 cmp r3, #0
|
|
8002264: d032 beq.n 80022cc <main+0x178>
|
|
{
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // Hardware Setup: Gain Selection (PA6)
|
|
8002266: 2140 movs r1, #64 @ 0x40
|
|
8002268: 485e ldr r0, [pc, #376] @ (80023e4 <main+0x290>)
|
|
800226a: f001 fb51 bl 8003910 <HAL_GPIO_ReadPin>
|
|
800226e: 4603 mov r3, r0
|
|
8002270: 2b01 cmp r3, #1
|
|
8002272: d103 bne.n 800227c <main+0x128>
|
|
mux_connection = AD5934_CH_EC_HIGH_GAIN;
|
|
8002274: 230e movs r3, #14
|
|
8002276: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
800227a: e002 b.n 8002282 <main+0x12e>
|
|
else
|
|
mux_connection = AD5934_CH_EC_MID_GAIN;
|
|
800227c: 230d movs r3, #13
|
|
800227e: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
uint16_t ec_final = AD5934_Compress_To_IntScale(g_ec_filter.filtered_value, mux_connection);
|
|
8002282: 4b5a ldr r3, [pc, #360] @ (80023ec <main+0x298>)
|
|
8002284: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002286: f897 202f ldrb.w r2, [r7, #47] @ 0x2f
|
|
800228a: 4611 mov r1, r2
|
|
800228c: 4618 mov r0, r3
|
|
800228e: f7fe ff0b bl 80010a8 <AD5934_Compress_To_IntScale>
|
|
8002292: 4603 mov r3, r0
|
|
8002294: 833b strh r3, [r7, #24]
|
|
intToStr(ec_final, tempString);
|
|
8002296: f9b7 3018 ldrsh.w r3, [r7, #24]
|
|
800229a: 463a mov r2, r7
|
|
800229c: 4611 mov r1, r2
|
|
800229e: 4618 mov r0, r3
|
|
80022a0: f000 fa10 bl 80026c4 <intToStr>
|
|
/* float ec_final = g_ec_filter.filtered_value;
|
|
FloatToString(tempString, ec_final);*/
|
|
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
|
|
80022a4: 463b mov r3, r7
|
|
80022a6: 4618 mov r0, r3
|
|
80022a8: f7fd ff50 bl 800014c <strlen>
|
|
80022ac: 4603 mov r3, r0
|
|
80022ae: b29a uxth r2, r3
|
|
80022b0: 463b mov r3, r7
|
|
80022b2: 4611 mov r1, r2
|
|
80022b4: 4618 mov r0, r3
|
|
80022b6: f000 fb27 bl 8002908 <rs485_send_broadcast>
|
|
rs485_send_broadcast(newline, (strlen((uint8_t*)newline)));
|
|
80022ba: 484b ldr r0, [pc, #300] @ (80023e8 <main+0x294>)
|
|
80022bc: f7fd ff46 bl 800014c <strlen>
|
|
80022c0: 4603 mov r3, r0
|
|
80022c2: b29b uxth r3, r3
|
|
80022c4: 4619 mov r1, r3
|
|
80022c6: 4848 ldr r0, [pc, #288] @ (80023e8 <main+0x294>)
|
|
80022c8: f000 fb1e bl 8002908 <rs485_send_broadcast>
|
|
}
|
|
|
|
if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C
|
|
80022cc: 4b48 ldr r3, [pc, #288] @ (80023f0 <main+0x29c>)
|
|
80022ce: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80022d2: 2b00 cmp r3, #0
|
|
80022d4: d034 beq.n 8002340 <main+0x1ec>
|
|
{
|
|
if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
|
|
80022d6: 2180 movs r1, #128 @ 0x80
|
|
80022d8: 4842 ldr r0, [pc, #264] @ (80023e4 <main+0x290>)
|
|
80022da: f001 fb19 bl 8003910 <HAL_GPIO_ReadPin>
|
|
80022de: 4603 mov r3, r0
|
|
80022e0: 2b01 cmp r3, #1
|
|
80022e2: d103 bne.n 80022ec <main+0x198>
|
|
mux_connection = AD5934_CH_RTD_LOW_GAIN; //PT100
|
|
80022e4: 2309 movs r3, #9
|
|
80022e6: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
80022ea: e002 b.n 80022f2 <main+0x19e>
|
|
else
|
|
mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000
|
|
80022ec: 230a movs r3, #10
|
|
80022ee: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, mux_connection);
|
|
80022f2: 4b3f ldr r3, [pc, #252] @ (80023f0 <main+0x29c>)
|
|
80022f4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80022f6: f897 202f ldrb.w r2, [r7, #47] @ 0x2f
|
|
80022fa: 4611 mov r1, r2
|
|
80022fc: 4618 mov r0, r3
|
|
80022fe: f7fe fed3 bl 80010a8 <AD5934_Compress_To_IntScale>
|
|
8002302: 4603 mov r3, r0
|
|
8002304: f5c3 5380 rsb r3, r3, #4096 @ 0x1000
|
|
8002308: 82fb strh r3, [r7, #22]
|
|
intToStr(rtd_final, tempString);
|
|
800230a: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800230e: 463a mov r2, r7
|
|
8002310: 4611 mov r1, r2
|
|
8002312: 4618 mov r0, r3
|
|
8002314: f000 f9d6 bl 80026c4 <intToStr>
|
|
// float rtd_final = g_rtd_filter.filtered_value;
|
|
// FloatToString(tempString, rtd_final);
|
|
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
|
|
8002318: 463b mov r3, r7
|
|
800231a: 4618 mov r0, r3
|
|
800231c: f7fd ff16 bl 800014c <strlen>
|
|
8002320: 4603 mov r3, r0
|
|
8002322: b29a uxth r2, r3
|
|
8002324: 463b mov r3, r7
|
|
8002326: 4611 mov r1, r2
|
|
8002328: 4618 mov r0, r3
|
|
800232a: f000 faed bl 8002908 <rs485_send_broadcast>
|
|
rs485_send_broadcast(newline, (strlen((uint8_t*)newline)));
|
|
800232e: 482e ldr r0, [pc, #184] @ (80023e8 <main+0x294>)
|
|
8002330: f7fd ff0c bl 800014c <strlen>
|
|
8002334: 4603 mov r3, r0
|
|
8002336: b29b uxth r3, r3
|
|
8002338: 4619 mov r1, r3
|
|
800233a: 482b ldr r0, [pc, #172] @ (80023e8 <main+0x294>)
|
|
800233c: f000 fae4 bl 8002908 <rs485_send_broadcast>
|
|
}
|
|
|
|
if (g_ph_filter.value_valid) // pH
|
|
8002340: 4b2c ldr r3, [pc, #176] @ (80023f4 <main+0x2a0>)
|
|
8002342: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8002346: 2b00 cmp r3, #0
|
|
8002348: d01f beq.n 800238a <main+0x236>
|
|
{
|
|
float ph_final = g_ph_filter.filtered_value;
|
|
800234a: 4b2a ldr r3, [pc, #168] @ (80023f4 <main+0x2a0>)
|
|
800234c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800234e: 613b str r3, [r7, #16]
|
|
FloatToString(tempString, ph_final);
|
|
8002350: 6938 ldr r0, [r7, #16]
|
|
8002352: f7fe f991 bl 8000678 <__aeabi_f2d>
|
|
8002356: 4602 mov r2, r0
|
|
8002358: 460b mov r3, r1
|
|
800235a: 4639 mov r1, r7
|
|
800235c: 4608 mov r0, r1
|
|
800235e: f000 f89d bl 800249c <FloatToString>
|
|
rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString)));
|
|
8002362: 463b mov r3, r7
|
|
8002364: 4618 mov r0, r3
|
|
8002366: f7fd fef1 bl 800014c <strlen>
|
|
800236a: 4603 mov r3, r0
|
|
800236c: b29a uxth r2, r3
|
|
800236e: 463b mov r3, r7
|
|
8002370: 4611 mov r1, r2
|
|
8002372: 4618 mov r0, r3
|
|
8002374: f000 fac8 bl 8002908 <rs485_send_broadcast>
|
|
rs485_send_broadcast(newline, (strlen((uint8_t*)newline)));
|
|
8002378: 481b ldr r0, [pc, #108] @ (80023e8 <main+0x294>)
|
|
800237a: f7fd fee7 bl 800014c <strlen>
|
|
800237e: 4603 mov r3, r0
|
|
8002380: b29b uxth r3, r3
|
|
8002382: 4619 mov r1, r3
|
|
8002384: 4818 ldr r0, [pc, #96] @ (80023e8 <main+0x294>)
|
|
8002386: f000 fabf bl 8002908 <rs485_send_broadcast>
|
|
}
|
|
|
|
rs485_send_broadcast(newline, (strlen((uint8_t*)newline)));
|
|
800238a: 4817 ldr r0, [pc, #92] @ (80023e8 <main+0x294>)
|
|
800238c: f7fd fede bl 800014c <strlen>
|
|
8002390: 4603 mov r3, r0
|
|
8002392: b29b uxth r3, r3
|
|
8002394: 4619 mov r1, r3
|
|
8002396: 4814 ldr r0, [pc, #80] @ (80023e8 <main+0x294>)
|
|
8002398: f000 fab6 bl 8002908 <rs485_send_broadcast>
|
|
|
|
}
|
|
|
|
|
|
// Piscar LED verde em PB5 a cada 0,5 segundos
|
|
if ((current_millis - previous_millis_green) >= 500)
|
|
800239c: 69fa ldr r2, [r7, #28]
|
|
800239e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80023a0: 1ad3 subs r3, r2, r3
|
|
80023a2: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
|
|
80023a6: d305 bcc.n 80023b4 <main+0x260>
|
|
{
|
|
previous_millis_green = current_millis;
|
|
80023a8: 69fb ldr r3, [r7, #28]
|
|
80023aa: 62bb str r3, [r7, #40] @ 0x28
|
|
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_5);
|
|
80023ac: 2120 movs r1, #32
|
|
80023ae: 4812 ldr r0, [pc, #72] @ (80023f8 <main+0x2a4>)
|
|
80023b0: f001 fadd bl 800396e <HAL_GPIO_TogglePin>
|
|
|
|
}
|
|
|
|
// Piscar LED vermelho em PB4 a cada 1 segundo
|
|
if ((current_millis - previous_millis_red) >= 1000)
|
|
80023b4: 69fa ldr r2, [r7, #28]
|
|
80023b6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023b8: 1ad3 subs r3, r2, r3
|
|
80023ba: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
80023be: f4ff af00 bcc.w 80021c2 <main+0x6e>
|
|
{
|
|
previous_millis_red = current_millis;
|
|
80023c2: 69fb ldr r3, [r7, #28]
|
|
80023c4: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4);
|
|
80023c6: 2110 movs r1, #16
|
|
80023c8: 480b ldr r0, [pc, #44] @ (80023f8 <main+0x2a4>)
|
|
80023ca: f001 fad0 bl 800396e <HAL_GPIO_TogglePin>
|
|
AD5934_Process_System();
|
|
80023ce: e6f8 b.n 80021c2 <main+0x6e>
|
|
80023d0: 20000224 .word 0x20000224
|
|
80023d4: 20000718 .word 0x20000718
|
|
80023d8: 20000084 .word 0x20000084
|
|
80023dc: 51eb851f .word 0x51eb851f
|
|
80023e0: 20000114 .word 0x20000114
|
|
80023e4: 40010800 .word 0x40010800
|
|
80023e8: 20000004 .word 0x20000004
|
|
80023ec: 200000d0 .word 0x200000d0
|
|
80023f0: 2000008c .word 0x2000008c
|
|
80023f4: 200001cc .word 0x200001cc
|
|
80023f8: 40010c00 .word 0x40010c00
|
|
|
|
080023fc <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
80023fc: b580 push {r7, lr}
|
|
80023fe: b094 sub sp, #80 @ 0x50
|
|
8002400: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8002402: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
8002406: 2228 movs r2, #40 @ 0x28
|
|
8002408: 2100 movs r1, #0
|
|
800240a: 4618 mov r0, r3
|
|
800240c: f004 f9cc bl 80067a8 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8002410: f107 0314 add.w r3, r7, #20
|
|
8002414: 2200 movs r2, #0
|
|
8002416: 601a str r2, [r3, #0]
|
|
8002418: 605a str r2, [r3, #4]
|
|
800241a: 609a str r2, [r3, #8]
|
|
800241c: 60da str r2, [r3, #12]
|
|
800241e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002420: 1d3b adds r3, r7, #4
|
|
8002422: 2200 movs r2, #0
|
|
8002424: 601a str r2, [r3, #0]
|
|
8002426: 605a str r2, [r3, #4]
|
|
8002428: 609a str r2, [r3, #8]
|
|
800242a: 60da str r2, [r3, #12]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
800242c: 2301 movs r3, #1
|
|
800242e: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8002430: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
8002434: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
8002436: 2300 movs r3, #0
|
|
8002438: 647b str r3, [r7, #68] @ 0x44
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
800243a: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
800243e: 4618 mov r0, r3
|
|
8002440: f002 fae2 bl 8004a08 <HAL_RCC_OscConfig>
|
|
8002444: 4603 mov r3, r0
|
|
8002446: 2b00 cmp r3, #0
|
|
8002448: d001 beq.n 800244e <SystemClock_Config+0x52>
|
|
{
|
|
Error_Handler();
|
|
800244a: f000 fa1f bl 800288c <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
800244e: 230f movs r3, #15
|
|
8002450: 617b str r3, [r7, #20]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
|
|
8002452: 2301 movs r3, #1
|
|
8002454: 61bb str r3, [r7, #24]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8002456: 2300 movs r3, #0
|
|
8002458: 61fb str r3, [r7, #28]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
800245a: 2300 movs r3, #0
|
|
800245c: 623b str r3, [r7, #32]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
800245e: 2300 movs r3, #0
|
|
8002460: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
8002462: f107 0314 add.w r3, r7, #20
|
|
8002466: 2100 movs r1, #0
|
|
8002468: 4618 mov r0, r3
|
|
800246a: f002 fd4f bl 8004f0c <HAL_RCC_ClockConfig>
|
|
800246e: 4603 mov r3, r0
|
|
8002470: 2b00 cmp r3, #0
|
|
8002472: d001 beq.n 8002478 <SystemClock_Config+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8002474: f000 fa0a bl 800288c <Error_Handler>
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
|
|
8002478: 2302 movs r3, #2
|
|
800247a: 607b str r3, [r7, #4]
|
|
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
|
|
800247c: f44f 4340 mov.w r3, #49152 @ 0xc000
|
|
8002480: 60fb str r3, [r7, #12]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002482: 1d3b adds r3, r7, #4
|
|
8002484: 4618 mov r0, r3
|
|
8002486: f002 fed1 bl 800522c <HAL_RCCEx_PeriphCLKConfig>
|
|
800248a: 4603 mov r3, r0
|
|
800248c: 2b00 cmp r3, #0
|
|
800248e: d001 beq.n 8002494 <SystemClock_Config+0x98>
|
|
{
|
|
Error_Handler();
|
|
8002490: f000 f9fc bl 800288c <Error_Handler>
|
|
}
|
|
}
|
|
8002494: bf00 nop
|
|
8002496: 3750 adds r7, #80 @ 0x50
|
|
8002498: 46bd mov sp, r7
|
|
800249a: bd80 pop {r7, pc}
|
|
|
|
0800249c <FloatToString>:
|
|
* @param val - value to be converted
|
|
*
|
|
* @return None.
|
|
*******************************************************************************/
|
|
void FloatToString(uint8_t *buf, double val)
|
|
{
|
|
800249c: b5b0 push {r4, r5, r7, lr}
|
|
800249e: b096 sub sp, #88 @ 0x58
|
|
80024a0: af00 add r7, sp, #0
|
|
80024a2: 60f8 str r0, [r7, #12]
|
|
80024a4: e9c7 2300 strd r2, r3, [r7]
|
|
char temp[20]; // Buffer auxiliar para construção segura
|
|
int i = 0;
|
|
80024a8: 2300 movs r3, #0
|
|
80024aa: 657b str r3, [r7, #84] @ 0x54
|
|
|
|
// 1. Tratar sinal negativo
|
|
if (val < 0) {
|
|
80024ac: f04f 0200 mov.w r2, #0
|
|
80024b0: f04f 0300 mov.w r3, #0
|
|
80024b4: e9d7 0100 ldrd r0, r1, [r7]
|
|
80024b8: f7fe f996 bl 80007e8 <__aeabi_dcmplt>
|
|
80024bc: 4603 mov r3, r0
|
|
80024be: 2b00 cmp r3, #0
|
|
80024c0: d00d beq.n 80024de <FloatToString+0x42>
|
|
temp[i++] = '-';
|
|
80024c2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80024c4: 1c5a adds r2, r3, #1
|
|
80024c6: 657a str r2, [r7, #84] @ 0x54
|
|
80024c8: 3358 adds r3, #88 @ 0x58
|
|
80024ca: 443b add r3, r7
|
|
80024cc: 222d movs r2, #45 @ 0x2d
|
|
80024ce: f803 2c30 strb.w r2, [r3, #-48]
|
|
val = -val;
|
|
80024d2: 683c ldr r4, [r7, #0]
|
|
80024d4: 687b ldr r3, [r7, #4]
|
|
80024d6: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000
|
|
80024da: e9c7 4500 strd r4, r5, [r7]
|
|
}
|
|
|
|
// 2. Separar parte inteira e fracionária
|
|
long intPart = (long)val;
|
|
80024de: e9d7 0100 ldrd r0, r1, [r7]
|
|
80024e2: f7fe f9a9 bl 8000838 <__aeabi_d2iz>
|
|
80024e6: 4603 mov r3, r0
|
|
80024e8: 653b str r3, [r7, #80] @ 0x50
|
|
// Multiplicamos por 1000 para obter 3 casas decimais fixas
|
|
int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
|
|
80024ea: 6d38 ldr r0, [r7, #80] @ 0x50
|
|
80024ec: f7fe f8b2 bl 8000654 <__aeabi_i2d>
|
|
80024f0: 4602 mov r2, r0
|
|
80024f2: 460b mov r3, r1
|
|
80024f4: e9d7 0100 ldrd r0, r1, [r7]
|
|
80024f8: f7fd ff5e bl 80003b8 <__aeabi_dsub>
|
|
80024fc: 4602 mov r2, r0
|
|
80024fe: 460b mov r3, r1
|
|
8002500: 4610 mov r0, r2
|
|
8002502: 4619 mov r1, r3
|
|
8002504: f04f 0200 mov.w r2, #0
|
|
8002508: 4b6a ldr r3, [pc, #424] @ (80026b4 <FloatToString+0x218>)
|
|
800250a: f7fd fe27 bl 800015c <__aeabi_dmul>
|
|
800250e: 4602 mov r2, r0
|
|
8002510: 460b mov r3, r1
|
|
8002512: 4610 mov r0, r2
|
|
8002514: 4619 mov r1, r3
|
|
8002516: f04f 0200 mov.w r2, #0
|
|
800251a: 4b67 ldr r3, [pc, #412] @ (80026b8 <FloatToString+0x21c>)
|
|
800251c: f7fd ff4e bl 80003bc <__adddf3>
|
|
8002520: 4602 mov r2, r0
|
|
8002522: 460b mov r3, r1
|
|
8002524: 4610 mov r0, r2
|
|
8002526: 4619 mov r1, r3
|
|
8002528: f7fe f986 bl 8000838 <__aeabi_d2iz>
|
|
800252c: 4603 mov r3, r0
|
|
800252e: 63fb str r3, [r7, #60] @ 0x3c
|
|
|
|
// 3. Converter a parte inteira para o buffer temp
|
|
// Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
|
|
char intRev[12];
|
|
int j = 0;
|
|
8002530: 2300 movs r3, #0
|
|
8002532: 64fb str r3, [r7, #76] @ 0x4c
|
|
|
|
if (intPart == 0) {
|
|
8002534: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8002536: 2b00 cmp r3, #0
|
|
8002538: d126 bne.n 8002588 <FloatToString+0xec>
|
|
intRev[j++] = '0';
|
|
800253a: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800253c: 1c5a adds r2, r3, #1
|
|
800253e: 64fa str r2, [r7, #76] @ 0x4c
|
|
8002540: 3358 adds r3, #88 @ 0x58
|
|
8002542: 443b add r3, r7
|
|
8002544: 2230 movs r2, #48 @ 0x30
|
|
8002546: f803 2c3c strb.w r2, [r3, #-60]
|
|
800254a: e020 b.n 800258e <FloatToString+0xf2>
|
|
} else {
|
|
while (intPart > 0) {
|
|
intRev[j++] = (intPart % 10) + '0';
|
|
800254c: 6d3a ldr r2, [r7, #80] @ 0x50
|
|
800254e: 4b5b ldr r3, [pc, #364] @ (80026bc <FloatToString+0x220>)
|
|
8002550: fb83 1302 smull r1, r3, r3, r2
|
|
8002554: 1099 asrs r1, r3, #2
|
|
8002556: 17d3 asrs r3, r2, #31
|
|
8002558: 1ac9 subs r1, r1, r3
|
|
800255a: 460b mov r3, r1
|
|
800255c: 009b lsls r3, r3, #2
|
|
800255e: 440b add r3, r1
|
|
8002560: 005b lsls r3, r3, #1
|
|
8002562: 1ad1 subs r1, r2, r3
|
|
8002564: b2ca uxtb r2, r1
|
|
8002566: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8002568: 1c59 adds r1, r3, #1
|
|
800256a: 64f9 str r1, [r7, #76] @ 0x4c
|
|
800256c: 3230 adds r2, #48 @ 0x30
|
|
800256e: b2d2 uxtb r2, r2
|
|
8002570: 3358 adds r3, #88 @ 0x58
|
|
8002572: 443b add r3, r7
|
|
8002574: f803 2c3c strb.w r2, [r3, #-60]
|
|
intPart /= 10;
|
|
8002578: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800257a: 4a50 ldr r2, [pc, #320] @ (80026bc <FloatToString+0x220>)
|
|
800257c: fb82 1203 smull r1, r2, r2, r3
|
|
8002580: 1092 asrs r2, r2, #2
|
|
8002582: 17db asrs r3, r3, #31
|
|
8002584: 1ad3 subs r3, r2, r3
|
|
8002586: 653b str r3, [r7, #80] @ 0x50
|
|
while (intPart > 0) {
|
|
8002588: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800258a: 2b00 cmp r3, #0
|
|
800258c: dcde bgt.n 800254c <FloatToString+0xb0>
|
|
}
|
|
}
|
|
|
|
// Inverter a parte inteira de volta para o buffer principal
|
|
for (int k = j - 1; k >= 0; k--) {
|
|
800258e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8002590: 3b01 subs r3, #1
|
|
8002592: 64bb str r3, [r7, #72] @ 0x48
|
|
8002594: e00e b.n 80025b4 <FloatToString+0x118>
|
|
temp[i++] = intRev[k];
|
|
8002596: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002598: 1c5a adds r2, r3, #1
|
|
800259a: 657a str r2, [r7, #84] @ 0x54
|
|
800259c: f107 011c add.w r1, r7, #28
|
|
80025a0: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80025a2: 440a add r2, r1
|
|
80025a4: 7812 ldrb r2, [r2, #0]
|
|
80025a6: 3358 adds r3, #88 @ 0x58
|
|
80025a8: 443b add r3, r7
|
|
80025aa: f803 2c30 strb.w r2, [r3, #-48]
|
|
for (int k = j - 1; k >= 0; k--) {
|
|
80025ae: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80025b0: 3b01 subs r3, #1
|
|
80025b2: 64bb str r3, [r7, #72] @ 0x48
|
|
80025b4: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80025b6: 2b00 cmp r3, #0
|
|
80025b8: daed bge.n 8002596 <FloatToString+0xfa>
|
|
}
|
|
|
|
// 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
|
|
temp[i++] = '.';
|
|
80025ba: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80025bc: 1c5a adds r2, r3, #1
|
|
80025be: 657a str r2, [r7, #84] @ 0x54
|
|
80025c0: 3358 adds r3, #88 @ 0x58
|
|
80025c2: 443b add r3, r7
|
|
80025c4: 222e movs r2, #46 @ 0x2e
|
|
80025c6: f803 2c30 strb.w r2, [r3, #-48]
|
|
|
|
// Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
|
|
int fracBuffer[3];
|
|
fracBuffer[2] = fracPart % 10; // Unidade
|
|
80025ca: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80025cc: 4b3b ldr r3, [pc, #236] @ (80026bc <FloatToString+0x220>)
|
|
80025ce: fb83 2301 smull r2, r3, r3, r1
|
|
80025d2: 109a asrs r2, r3, #2
|
|
80025d4: 17cb asrs r3, r1, #31
|
|
80025d6: 1ad2 subs r2, r2, r3
|
|
80025d8: 4613 mov r3, r2
|
|
80025da: 009b lsls r3, r3, #2
|
|
80025dc: 4413 add r3, r2
|
|
80025de: 005b lsls r3, r3, #1
|
|
80025e0: 1aca subs r2, r1, r3
|
|
80025e2: 61ba str r2, [r7, #24]
|
|
fracBuffer[1] = (fracPart / 10) % 10; // Dezena
|
|
80025e4: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80025e6: 4a35 ldr r2, [pc, #212] @ (80026bc <FloatToString+0x220>)
|
|
80025e8: fb82 1203 smull r1, r2, r2, r3
|
|
80025ec: 1092 asrs r2, r2, #2
|
|
80025ee: 17db asrs r3, r3, #31
|
|
80025f0: 1ad1 subs r1, r2, r3
|
|
80025f2: 4b32 ldr r3, [pc, #200] @ (80026bc <FloatToString+0x220>)
|
|
80025f4: fb83 2301 smull r2, r3, r3, r1
|
|
80025f8: 109a asrs r2, r3, #2
|
|
80025fa: 17cb asrs r3, r1, #31
|
|
80025fc: 1ad2 subs r2, r2, r3
|
|
80025fe: 4613 mov r3, r2
|
|
8002600: 009b lsls r3, r3, #2
|
|
8002602: 4413 add r3, r2
|
|
8002604: 005b lsls r3, r3, #1
|
|
8002606: 1aca subs r2, r1, r3
|
|
8002608: 617a str r2, [r7, #20]
|
|
fracBuffer[0] = (fracPart / 100) % 10; // Centena
|
|
800260a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800260c: 4a2c ldr r2, [pc, #176] @ (80026c0 <FloatToString+0x224>)
|
|
800260e: fb82 1203 smull r1, r2, r2, r3
|
|
8002612: 1152 asrs r2, r2, #5
|
|
8002614: 17db asrs r3, r3, #31
|
|
8002616: 1ad1 subs r1, r2, r3
|
|
8002618: 4b28 ldr r3, [pc, #160] @ (80026bc <FloatToString+0x220>)
|
|
800261a: fb83 2301 smull r2, r3, r3, r1
|
|
800261e: 109a asrs r2, r3, #2
|
|
8002620: 17cb asrs r3, r1, #31
|
|
8002622: 1ad2 subs r2, r2, r3
|
|
8002624: 4613 mov r3, r2
|
|
8002626: 009b lsls r3, r3, #2
|
|
8002628: 4413 add r3, r2
|
|
800262a: 005b lsls r3, r3, #1
|
|
800262c: 1aca subs r2, r1, r3
|
|
800262e: 613a str r2, [r7, #16]
|
|
|
|
for (int k = 2; k >= 0; k--) {
|
|
8002630: 2302 movs r3, #2
|
|
8002632: 647b str r3, [r7, #68] @ 0x44
|
|
8002634: e012 b.n 800265c <FloatToString+0x1c0>
|
|
temp[i++] = fracBuffer[k] + '0';
|
|
8002636: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8002638: 009b lsls r3, r3, #2
|
|
800263a: 3358 adds r3, #88 @ 0x58
|
|
800263c: 443b add r3, r7
|
|
800263e: f853 3c48 ldr.w r3, [r3, #-72]
|
|
8002642: b2da uxtb r2, r3
|
|
8002644: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002646: 1c59 adds r1, r3, #1
|
|
8002648: 6579 str r1, [r7, #84] @ 0x54
|
|
800264a: 3230 adds r2, #48 @ 0x30
|
|
800264c: b2d2 uxtb r2, r2
|
|
800264e: 3358 adds r3, #88 @ 0x58
|
|
8002650: 443b add r3, r7
|
|
8002652: f803 2c30 strb.w r2, [r3, #-48]
|
|
for (int k = 2; k >= 0; k--) {
|
|
8002656: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8002658: 3b01 subs r3, #1
|
|
800265a: 647b str r3, [r7, #68] @ 0x44
|
|
800265c: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800265e: 2b00 cmp r3, #0
|
|
8002660: dae9 bge.n 8002636 <FloatToString+0x19a>
|
|
}
|
|
|
|
// 5. Finalizar a string com o caractere nulo
|
|
temp[i] = '\0';
|
|
8002662: f107 0228 add.w r2, r7, #40 @ 0x28
|
|
8002666: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002668: 4413 add r3, r2
|
|
800266a: 2200 movs r2, #0
|
|
800266c: 701a strb r2, [r3, #0]
|
|
|
|
// 6. Copiar para o buffer de destino final (sem risco de lixo)
|
|
int destIdx = 0;
|
|
800266e: 2300 movs r3, #0
|
|
8002670: 643b str r3, [r7, #64] @ 0x40
|
|
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
|
|
8002672: e00b b.n 800268c <FloatToString+0x1f0>
|
|
buf[destIdx] = temp[destIdx];
|
|
8002674: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8002676: 68fa ldr r2, [r7, #12]
|
|
8002678: 4413 add r3, r2
|
|
800267a: f107 0128 add.w r1, r7, #40 @ 0x28
|
|
800267e: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8002680: 440a add r2, r1
|
|
8002682: 7812 ldrb r2, [r2, #0]
|
|
8002684: 701a strb r2, [r3, #0]
|
|
destIdx++;
|
|
8002686: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8002688: 3301 adds r3, #1
|
|
800268a: 643b str r3, [r7, #64] @ 0x40
|
|
while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
|
|
800268c: f107 0228 add.w r2, r7, #40 @ 0x28
|
|
8002690: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8002692: 4413 add r3, r2
|
|
8002694: 781b ldrb r3, [r3, #0]
|
|
8002696: 2b00 cmp r3, #0
|
|
8002698: d002 beq.n 80026a0 <FloatToString+0x204>
|
|
800269a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800269c: 2b0e cmp r3, #14
|
|
800269e: dde9 ble.n 8002674 <FloatToString+0x1d8>
|
|
}
|
|
buf[destIdx] = '\0';
|
|
80026a0: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80026a2: 68fa ldr r2, [r7, #12]
|
|
80026a4: 4413 add r3, r2
|
|
80026a6: 2200 movs r2, #0
|
|
80026a8: 701a strb r2, [r3, #0]
|
|
}
|
|
80026aa: bf00 nop
|
|
80026ac: 3758 adds r7, #88 @ 0x58
|
|
80026ae: 46bd mov sp, r7
|
|
80026b0: bdb0 pop {r4, r5, r7, pc}
|
|
80026b2: bf00 nop
|
|
80026b4: 408f4000 .word 0x408f4000
|
|
80026b8: 3fe00000 .word 0x3fe00000
|
|
80026bc: 66666667 .word 0x66666667
|
|
80026c0: 51eb851f .word 0x51eb851f
|
|
|
|
080026c4 <intToStr>:
|
|
|
|
|
|
|
|
void intToStr(int16_t N, uint8_t *str)
|
|
{
|
|
80026c4: b480 push {r7}
|
|
80026c6: b087 sub sp, #28
|
|
80026c8: af00 add r7, sp, #0
|
|
80026ca: 4603 mov r3, r0
|
|
80026cc: 6039 str r1, [r7, #0]
|
|
80026ce: 80fb strh r3, [r7, #6]
|
|
int16_t i = 0;
|
|
80026d0: 2300 movs r3, #0
|
|
80026d2: 82fb strh r3, [r7, #22]
|
|
int16_t sign = N;
|
|
80026d4: 88fb ldrh r3, [r7, #6]
|
|
80026d6: 823b strh r3, [r7, #16]
|
|
uint8_t max_len = 15; // Tamanho máximo do buffer
|
|
80026d8: 230f movs r3, #15
|
|
80026da: 73fb strb r3, [r7, #15]
|
|
uint8_t width = 4; // mínimo 4 caracteres
|
|
80026dc: 2304 movs r3, #4
|
|
80026de: 757b strb r3, [r7, #21]
|
|
|
|
// Trata o caso do número zero isoladamente
|
|
if (N == 0)
|
|
80026e0: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
80026e4: 2b00 cmp r3, #0
|
|
80026e6: d127 bne.n 8002738 <intToStr+0x74>
|
|
{
|
|
// Preenche com zeros à esquerda até atingir a largura desejada
|
|
while (width > 1 && i < (max_len - 1))
|
|
80026e8: e00c b.n 8002704 <intToStr+0x40>
|
|
{
|
|
str[i++] = '0';
|
|
80026ea: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80026ee: b293 uxth r3, r2
|
|
80026f0: 3301 adds r3, #1
|
|
80026f2: b29b uxth r3, r3
|
|
80026f4: 82fb strh r3, [r7, #22]
|
|
80026f6: 683b ldr r3, [r7, #0]
|
|
80026f8: 4413 add r3, r2
|
|
80026fa: 2230 movs r2, #48 @ 0x30
|
|
80026fc: 701a strb r2, [r3, #0]
|
|
width--;
|
|
80026fe: 7d7b ldrb r3, [r7, #21]
|
|
8002700: 3b01 subs r3, #1
|
|
8002702: 757b strb r3, [r7, #21]
|
|
while (width > 1 && i < (max_len - 1))
|
|
8002704: 7d7b ldrb r3, [r7, #21]
|
|
8002706: 2b01 cmp r3, #1
|
|
8002708: d905 bls.n 8002716 <intToStr+0x52>
|
|
800270a: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
800270e: 7bfb ldrb r3, [r7, #15]
|
|
8002710: 3b01 subs r3, #1
|
|
8002712: 429a cmp r2, r3
|
|
8002714: dbe9 blt.n 80026ea <intToStr+0x26>
|
|
}
|
|
str[i++] = '0';
|
|
8002716: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
800271a: b293 uxth r3, r2
|
|
800271c: 3301 adds r3, #1
|
|
800271e: b29b uxth r3, r3
|
|
8002720: 82fb strh r3, [r7, #22]
|
|
8002722: 683b ldr r3, [r7, #0]
|
|
8002724: 4413 add r3, r2
|
|
8002726: 2230 movs r2, #48 @ 0x30
|
|
8002728: 701a strb r2, [r3, #0]
|
|
str[i] = '\0';
|
|
800272a: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800272e: 683a ldr r2, [r7, #0]
|
|
8002730: 4413 add r3, r2
|
|
8002732: 2200 movs r2, #0
|
|
8002734: 701a strb r2, [r3, #0]
|
|
return;
|
|
8002736: e08a b.n 800284e <intToStr+0x18a>
|
|
}
|
|
|
|
if (N < 0)
|
|
8002738: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800273c: 2b00 cmp r3, #0
|
|
800273e: da2d bge.n 800279c <intToStr+0xd8>
|
|
N = -N;
|
|
8002740: 88fb ldrh r3, [r7, #6]
|
|
8002742: 425b negs r3, r3
|
|
8002744: b29b uxth r3, r3
|
|
8002746: 80fb strh r3, [r7, #6]
|
|
|
|
// Extração dos dígitos
|
|
while (N > 0)
|
|
8002748: e028 b.n 800279c <intToStr+0xd8>
|
|
{
|
|
if (i >= (max_len - 1))
|
|
800274a: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
800274e: 7bfb ldrb r3, [r7, #15]
|
|
8002750: 3b01 subs r3, #1
|
|
8002752: 429a cmp r2, r3
|
|
8002754: da27 bge.n 80027a6 <intToStr+0xe2>
|
|
break; // Proteção de estouro
|
|
str[i++] = (N % 10) + '0';
|
|
8002756: f9b7 2006 ldrsh.w r2, [r7, #6]
|
|
800275a: 4b3f ldr r3, [pc, #252] @ (8002858 <intToStr+0x194>)
|
|
800275c: fb83 1302 smull r1, r3, r3, r2
|
|
8002760: 1099 asrs r1, r3, #2
|
|
8002762: 17d3 asrs r3, r2, #31
|
|
8002764: 1ac9 subs r1, r1, r3
|
|
8002766: 460b mov r3, r1
|
|
8002768: 009b lsls r3, r3, #2
|
|
800276a: 440b add r3, r1
|
|
800276c: 005b lsls r3, r3, #1
|
|
800276e: 1ad3 subs r3, r2, r3
|
|
8002770: b21b sxth r3, r3
|
|
8002772: b2da uxtb r2, r3
|
|
8002774: f9b7 1016 ldrsh.w r1, [r7, #22]
|
|
8002778: b28b uxth r3, r1
|
|
800277a: 3301 adds r3, #1
|
|
800277c: b29b uxth r3, r3
|
|
800277e: 82fb strh r3, [r7, #22]
|
|
8002780: 683b ldr r3, [r7, #0]
|
|
8002782: 440b add r3, r1
|
|
8002784: 3230 adds r2, #48 @ 0x30
|
|
8002786: b2d2 uxtb r2, r2
|
|
8002788: 701a strb r2, [r3, #0]
|
|
N /= 10;
|
|
800278a: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800278e: 4a32 ldr r2, [pc, #200] @ (8002858 <intToStr+0x194>)
|
|
8002790: fb82 1203 smull r1, r2, r2, r3
|
|
8002794: 1092 asrs r2, r2, #2
|
|
8002796: 17db asrs r3, r3, #31
|
|
8002798: 1ad3 subs r3, r2, r3
|
|
800279a: 80fb strh r3, [r7, #6]
|
|
while (N > 0)
|
|
800279c: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
80027a0: 2b00 cmp r3, #0
|
|
80027a2: dcd2 bgt.n 800274a <intToStr+0x86>
|
|
80027a4: e000 b.n 80027a8 <intToStr+0xe4>
|
|
break; // Proteção de estouro
|
|
80027a6: bf00 nop
|
|
}
|
|
|
|
// Adiciona o sinal de menos se necessário
|
|
if (sign < 0)
|
|
80027a8: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
80027ac: 2b00 cmp r3, #0
|
|
80027ae: da1a bge.n 80027e6 <intToStr+0x122>
|
|
{
|
|
if (i < (max_len - 1))
|
|
80027b0: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80027b4: 7bfb ldrb r3, [r7, #15]
|
|
80027b6: 3b01 subs r3, #1
|
|
80027b8: 429a cmp r2, r3
|
|
80027ba: da14 bge.n 80027e6 <intToStr+0x122>
|
|
str[i++] = '-';
|
|
80027bc: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80027c0: b293 uxth r3, r2
|
|
80027c2: 3301 adds r3, #1
|
|
80027c4: b29b uxth r3, r3
|
|
80027c6: 82fb strh r3, [r7, #22]
|
|
80027c8: 683b ldr r3, [r7, #0]
|
|
80027ca: 4413 add r3, r2
|
|
80027cc: 222d movs r2, #45 @ 0x2d
|
|
80027ce: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
// Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal)
|
|
while (i < width && i < (max_len - 1))
|
|
80027d0: e009 b.n 80027e6 <intToStr+0x122>
|
|
{
|
|
str[i++] = '0';
|
|
80027d2: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80027d6: b293 uxth r3, r2
|
|
80027d8: 3301 adds r3, #1
|
|
80027da: b29b uxth r3, r3
|
|
80027dc: 82fb strh r3, [r7, #22]
|
|
80027de: 683b ldr r3, [r7, #0]
|
|
80027e0: 4413 add r3, r2
|
|
80027e2: 2230 movs r2, #48 @ 0x30
|
|
80027e4: 701a strb r2, [r3, #0]
|
|
while (i < width && i < (max_len - 1))
|
|
80027e6: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80027ea: 7d7b ldrb r3, [r7, #21]
|
|
80027ec: 429a cmp r2, r3
|
|
80027ee: da05 bge.n 80027fc <intToStr+0x138>
|
|
80027f0: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80027f4: 7bfb ldrb r3, [r7, #15]
|
|
80027f6: 3b01 subs r3, #1
|
|
80027f8: 429a cmp r2, r3
|
|
80027fa: dbea blt.n 80027d2 <intToStr+0x10e>
|
|
}
|
|
|
|
str[i] = '\0';
|
|
80027fc: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
8002800: 683a ldr r2, [r7, #0]
|
|
8002802: 4413 add r3, r2
|
|
8002804: 2200 movs r2, #0
|
|
8002806: 701a strb r2, [r3, #0]
|
|
|
|
// Inverte a string para colocar na ordem correta
|
|
for (uint8_t j = 0, k = i - 1; j < k; j++, k--)
|
|
8002808: 2300 movs r3, #0
|
|
800280a: 753b strb r3, [r7, #20]
|
|
800280c: 8afb ldrh r3, [r7, #22]
|
|
800280e: b2db uxtb r3, r3
|
|
8002810: 3b01 subs r3, #1
|
|
8002812: 74fb strb r3, [r7, #19]
|
|
8002814: e017 b.n 8002846 <intToStr+0x182>
|
|
{
|
|
uint8_t temp = str[j];
|
|
8002816: 7d3b ldrb r3, [r7, #20]
|
|
8002818: 683a ldr r2, [r7, #0]
|
|
800281a: 4413 add r3, r2
|
|
800281c: 781b ldrb r3, [r3, #0]
|
|
800281e: 73bb strb r3, [r7, #14]
|
|
str[j] = str[k];
|
|
8002820: 7cfb ldrb r3, [r7, #19]
|
|
8002822: 683a ldr r2, [r7, #0]
|
|
8002824: 441a add r2, r3
|
|
8002826: 7d3b ldrb r3, [r7, #20]
|
|
8002828: 6839 ldr r1, [r7, #0]
|
|
800282a: 440b add r3, r1
|
|
800282c: 7812 ldrb r2, [r2, #0]
|
|
800282e: 701a strb r2, [r3, #0]
|
|
str[k] = temp;
|
|
8002830: 7cfb ldrb r3, [r7, #19]
|
|
8002832: 683a ldr r2, [r7, #0]
|
|
8002834: 4413 add r3, r2
|
|
8002836: 7bba ldrb r2, [r7, #14]
|
|
8002838: 701a strb r2, [r3, #0]
|
|
for (uint8_t j = 0, k = i - 1; j < k; j++, k--)
|
|
800283a: 7d3b ldrb r3, [r7, #20]
|
|
800283c: 3301 adds r3, #1
|
|
800283e: 753b strb r3, [r7, #20]
|
|
8002840: 7cfb ldrb r3, [r7, #19]
|
|
8002842: 3b01 subs r3, #1
|
|
8002844: 74fb strb r3, [r7, #19]
|
|
8002846: 7d3a ldrb r2, [r7, #20]
|
|
8002848: 7cfb ldrb r3, [r7, #19]
|
|
800284a: 429a cmp r2, r3
|
|
800284c: d3e3 bcc.n 8002816 <intToStr+0x152>
|
|
}
|
|
}
|
|
800284e: 371c adds r7, #28
|
|
8002850: 46bd mov sp, r7
|
|
8002852: bc80 pop {r7}
|
|
8002854: 4770 bx lr
|
|
8002856: bf00 nop
|
|
8002858: 66666667 .word 0x66666667
|
|
|
|
0800285c <HAL_TIM_PeriodElapsedCallback>:
|
|
|
|
/* TIM3 Timer Interrupt */
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800285c: b480 push {r7}
|
|
800285e: b083 sub sp, #12
|
|
8002860: af00 add r7, sp, #0
|
|
8002862: 6078 str r0, [r7, #4]
|
|
if (htim->Instance == TIM3)
|
|
8002864: 687b ldr r3, [r7, #4]
|
|
8002866: 681b ldr r3, [r3, #0]
|
|
8002868: 4a06 ldr r2, [pc, #24] @ (8002884 <HAL_TIM_PeriodElapsedCallback+0x28>)
|
|
800286a: 4293 cmp r3, r2
|
|
800286c: d104 bne.n 8002878 <HAL_TIM_PeriodElapsedCallback+0x1c>
|
|
{
|
|
g_ms_counter++; /* Relógio global do sistema */
|
|
800286e: 4b06 ldr r3, [pc, #24] @ (8002888 <HAL_TIM_PeriodElapsedCallback+0x2c>)
|
|
8002870: 681b ldr r3, [r3, #0]
|
|
8002872: 3301 adds r3, #1
|
|
8002874: 4a04 ldr r2, [pc, #16] @ (8002888 <HAL_TIM_PeriodElapsedCallback+0x2c>)
|
|
8002876: 6013 str r3, [r2, #0]
|
|
|
|
}
|
|
}
|
|
8002878: bf00 nop
|
|
800287a: 370c adds r7, #12
|
|
800287c: 46bd mov sp, r7
|
|
800287e: bc80 pop {r7}
|
|
8002880: 4770 bx lr
|
|
8002882: bf00 nop
|
|
8002884: 40000400 .word 0x40000400
|
|
8002888: 20000084 .word 0x20000084
|
|
|
|
0800288c <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
800288c: b480 push {r7}
|
|
800288e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8002890: b672 cpsid i
|
|
}
|
|
8002892: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8002894: bf00 nop
|
|
8002896: e7fd b.n 8002894 <Error_Handler+0x8>
|
|
|
|
08002898 <LL_GPIO_ReadInputPort>:
|
|
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
|
|
* @param GPIOx GPIO Port
|
|
* @retval Input data register value of port
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
|
|
{
|
|
8002898: b480 push {r7}
|
|
800289a: b083 sub sp, #12
|
|
800289c: af00 add r7, sp, #0
|
|
800289e: 6078 str r0, [r7, #4]
|
|
return (READ_REG(GPIOx->IDR));
|
|
80028a0: 687b ldr r3, [r7, #4]
|
|
80028a2: 689b ldr r3, [r3, #8]
|
|
}
|
|
80028a4: 4618 mov r0, r3
|
|
80028a6: 370c adds r7, #12
|
|
80028a8: 46bd mov sp, r7
|
|
80028aa: bc80 pop {r7}
|
|
80028ac: 4770 bx lr
|
|
...
|
|
|
|
080028b0 <rs485_init>:
|
|
/**
|
|
* @brief Initializes the RS-485 driver.
|
|
* @note This function configures GPIOs for address detection and USART1 for communication.
|
|
*/
|
|
void rs485_init(void)
|
|
{
|
|
80028b0: b580 push {r7, lr}
|
|
80028b2: af00 add r7, sp, #0
|
|
/* Configure GPIOs for address detection */
|
|
rs485_configure_gpio_address();
|
|
80028b4: f000 f864 bl 8002980 <rs485_configure_gpio_address>
|
|
|
|
/* Configure USART1 for RS-485 communication */
|
|
rs485_configure_usart1();
|
|
80028b8: f000 f8a8 bl 8002a0c <rs485_configure_usart1>
|
|
|
|
/* Get the current device address from GPIOs */
|
|
device_address.full_address = rs485_get_address();
|
|
80028bc: f000 f808 bl 80028d0 <rs485_get_address>
|
|
80028c0: 4603 mov r3, r0
|
|
80028c2: 461a mov r2, r3
|
|
80028c4: 4b01 ldr r3, [pc, #4] @ (80028cc <rs485_init+0x1c>)
|
|
80028c6: 709a strb r2, [r3, #2]
|
|
}
|
|
80028c8: bf00 nop
|
|
80028ca: bd80 pop {r7, pc}
|
|
80028cc: 200006cc .word 0x200006cc
|
|
|
|
080028d0 <rs485_get_address>:
|
|
/**
|
|
* @brief Gets the current device address from GPIOs.
|
|
* @return The 8-bit device address.
|
|
*/
|
|
uint8_t rs485_get_address(void)
|
|
{
|
|
80028d0: b598 push {r3, r4, r7, lr}
|
|
80028d2: af00 add r7, sp, #0
|
|
return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
|
|
80028d4: 480a ldr r0, [pc, #40] @ (8002900 <rs485_get_address+0x30>)
|
|
80028d6: f7ff ffdf bl 8002898 <LL_GPIO_ReadInputPort>
|
|
80028da: 4603 mov r3, r0
|
|
80028dc: 0a1b lsrs r3, r3, #8
|
|
80028de: b2db uxtb r3, r3
|
|
80028e0: f023 030f bic.w r3, r3, #15
|
|
80028e4: b2dc uxtb r4, r3
|
|
80028e6: 4807 ldr r0, [pc, #28] @ (8002904 <rs485_get_address+0x34>)
|
|
80028e8: f7ff ffd6 bl 8002898 <LL_GPIO_ReadInputPort>
|
|
80028ec: 4603 mov r3, r0
|
|
80028ee: 089b lsrs r3, r3, #2
|
|
80028f0: b2db uxtb r3, r3
|
|
80028f2: f003 030f and.w r3, r3, #15
|
|
80028f6: b2db uxtb r3, r3
|
|
80028f8: 4323 orrs r3, r4
|
|
80028fa: b2db uxtb r3, r3
|
|
}
|
|
80028fc: 4618 mov r0, r3
|
|
80028fe: bd98 pop {r3, r4, r7, pc}
|
|
8002900: 40010c00 .word 0x40010c00
|
|
8002904: 40010800 .word 0x40010800
|
|
|
|
08002908 <rs485_send_broadcast>:
|
|
* @param data Pointer to the data buffer.
|
|
* @param length Number of bytes to send.
|
|
* @retval HAL_OK on success, otherwise error code.
|
|
*/
|
|
HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
|
|
{
|
|
8002908: b580 push {r7, lr}
|
|
800290a: b084 sub sp, #16
|
|
800290c: af00 add r7, sp, #0
|
|
800290e: 6078 str r0, [r7, #4]
|
|
8002910: 460b mov r3, r1
|
|
8002912: 807b strh r3, [r7, #2]
|
|
/* Enable transmission mode */
|
|
rs485_enable_tx();
|
|
8002914: f000 f81c bl 8002950 <rs485_enable_tx>
|
|
|
|
/* Send the broadcast address (0x00) first */
|
|
uint8_t broadcast_address = 0x00;
|
|
8002918: 2300 movs r3, #0
|
|
800291a: 73bb strb r3, [r7, #14]
|
|
HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
|
|
800291c: f107 010e add.w r1, r7, #14
|
|
8002920: f04f 33ff mov.w r3, #4294967295
|
|
8002924: 2201 movs r2, #1
|
|
8002926: 4809 ldr r0, [pc, #36] @ (800294c <rs485_send_broadcast+0x44>)
|
|
8002928: f003 f978 bl 8005c1c <HAL_UART_Transmit>
|
|
|
|
/* Send the data */
|
|
HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
|
|
800292c: 887a ldrh r2, [r7, #2]
|
|
800292e: f04f 33ff mov.w r3, #4294967295
|
|
8002932: 6879 ldr r1, [r7, #4]
|
|
8002934: 4805 ldr r0, [pc, #20] @ (800294c <rs485_send_broadcast+0x44>)
|
|
8002936: f003 f971 bl 8005c1c <HAL_UART_Transmit>
|
|
800293a: 4603 mov r3, r0
|
|
800293c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Disable transmission mode after sending */
|
|
rs485_disable_tx();
|
|
800293e: f000 f813 bl 8002968 <rs485_disable_tx>
|
|
|
|
return status;
|
|
8002942: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002944: 4618 mov r0, r3
|
|
8002946: 3710 adds r7, #16
|
|
8002948: 46bd mov sp, r7
|
|
800294a: bd80 pop {r7, pc}
|
|
800294c: 200006d0 .word 0x200006d0
|
|
|
|
08002950 <rs485_enable_tx>:
|
|
|
|
/**
|
|
* @brief Enables transmission mode on RS-485 transceiver.
|
|
*/
|
|
void rs485_enable_tx(void)
|
|
{
|
|
8002950: b580 push {r7, lr}
|
|
8002952: af00 add r7, sp, #0
|
|
/* Set TX EN pin high to enable transmitter */
|
|
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
|
|
8002954: 2201 movs r2, #1
|
|
8002956: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
800295a: 4802 ldr r0, [pc, #8] @ (8002964 <rs485_enable_tx+0x14>)
|
|
800295c: f000 ffef bl 800393e <HAL_GPIO_WritePin>
|
|
}
|
|
8002960: bf00 nop
|
|
8002962: bd80 pop {r7, pc}
|
|
8002964: 40010800 .word 0x40010800
|
|
|
|
08002968 <rs485_disable_tx>:
|
|
|
|
/**
|
|
* @brief Disables transmission mode on RS-485 transceiver.
|
|
*/
|
|
void rs485_disable_tx(void)
|
|
{
|
|
8002968: b580 push {r7, lr}
|
|
800296a: af00 add r7, sp, #0
|
|
/* Set TX EN pin low to disable transmitter */
|
|
HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
|
|
800296c: 2200 movs r2, #0
|
|
800296e: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8002972: 4802 ldr r0, [pc, #8] @ (800297c <rs485_disable_tx+0x14>)
|
|
8002974: f000 ffe3 bl 800393e <HAL_GPIO_WritePin>
|
|
}
|
|
8002978: bf00 nop
|
|
800297a: bd80 pop {r7, pc}
|
|
800297c: 40010800 .word 0x40010800
|
|
|
|
08002980 <rs485_configure_gpio_address>:
|
|
|
|
/**
|
|
* @brief Configures GPIOs for address detection.
|
|
*/
|
|
static void rs485_configure_gpio_address(void)
|
|
{
|
|
8002980: b580 push {r7, lr}
|
|
8002982: b086 sub sp, #24
|
|
8002984: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002986: f107 0308 add.w r3, r7, #8
|
|
800298a: 2200 movs r2, #0
|
|
800298c: 601a str r2, [r3, #0]
|
|
800298e: 605a str r2, [r3, #4]
|
|
8002990: 609a str r2, [r3, #8]
|
|
8002992: 60da str r2, [r3, #12]
|
|
|
|
/* Enable clock for GPIOA and GPIOB */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002994: 4b1a ldr r3, [pc, #104] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
8002996: 699b ldr r3, [r3, #24]
|
|
8002998: 4a19 ldr r2, [pc, #100] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
800299a: f043 0304 orr.w r3, r3, #4
|
|
800299e: 6193 str r3, [r2, #24]
|
|
80029a0: 4b17 ldr r3, [pc, #92] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
80029a2: 699b ldr r3, [r3, #24]
|
|
80029a4: f003 0304 and.w r3, r3, #4
|
|
80029a8: 607b str r3, [r7, #4]
|
|
80029aa: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80029ac: 4b14 ldr r3, [pc, #80] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
80029ae: 699b ldr r3, [r3, #24]
|
|
80029b0: 4a13 ldr r2, [pc, #76] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
80029b2: f043 0308 orr.w r3, r3, #8
|
|
80029b6: 6193 str r3, [r2, #24]
|
|
80029b8: 4b11 ldr r3, [pc, #68] @ (8002a00 <rs485_configure_gpio_address+0x80>)
|
|
80029ba: 699b ldr r3, [r3, #24]
|
|
80029bc: f003 0308 and.w r3, r3, #8
|
|
80029c0: 603b str r3, [r7, #0]
|
|
80029c2: 683b ldr r3, [r7, #0]
|
|
|
|
/* Configure PA2-PA5 as input with pull-up */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
|
|
80029c4: 233c movs r3, #60 @ 0x3c
|
|
80029c6: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80029c8: 2300 movs r3, #0
|
|
80029ca: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80029cc: 2301 movs r3, #1
|
|
80029ce: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80029d0: f107 0308 add.w r3, r7, #8
|
|
80029d4: 4619 mov r1, r3
|
|
80029d6: 480b ldr r0, [pc, #44] @ (8002a04 <rs485_configure_gpio_address+0x84>)
|
|
80029d8: f000 fe16 bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/* Configure PB12-PB15 as input with pull-up */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
|
|
80029dc: f44f 4370 mov.w r3, #61440 @ 0xf000
|
|
80029e0: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80029e2: 2300 movs r3, #0
|
|
80029e4: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80029e6: 2301 movs r3, #1
|
|
80029e8: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80029ea: f107 0308 add.w r3, r7, #8
|
|
80029ee: 4619 mov r1, r3
|
|
80029f0: 4805 ldr r0, [pc, #20] @ (8002a08 <rs485_configure_gpio_address+0x88>)
|
|
80029f2: f000 fe09 bl 8003608 <HAL_GPIO_Init>
|
|
}
|
|
80029f6: bf00 nop
|
|
80029f8: 3718 adds r7, #24
|
|
80029fa: 46bd mov sp, r7
|
|
80029fc: bd80 pop {r7, pc}
|
|
80029fe: bf00 nop
|
|
8002a00: 40021000 .word 0x40021000
|
|
8002a04: 40010800 .word 0x40010800
|
|
8002a08: 40010c00 .word 0x40010c00
|
|
|
|
08002a0c <rs485_configure_usart1>:
|
|
|
|
/**
|
|
* @brief Configures USART1 for RS-485 communication.
|
|
*/
|
|
static void rs485_configure_usart1(void)
|
|
{
|
|
8002a0c: b580 push {r7, lr}
|
|
8002a0e: b082 sub sp, #8
|
|
8002a10: af00 add r7, sp, #0
|
|
/* Enable clock for USART1 */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8002a12: 4b18 ldr r3, [pc, #96] @ (8002a74 <rs485_configure_usart1+0x68>)
|
|
8002a14: 699b ldr r3, [r3, #24]
|
|
8002a16: 4a17 ldr r2, [pc, #92] @ (8002a74 <rs485_configure_usart1+0x68>)
|
|
8002a18: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8002a1c: 6193 str r3, [r2, #24]
|
|
8002a1e: 4b15 ldr r3, [pc, #84] @ (8002a74 <rs485_configure_usart1+0x68>)
|
|
8002a20: 699b ldr r3, [r3, #24]
|
|
8002a22: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002a26: 607b str r3, [r7, #4]
|
|
8002a28: 687b ldr r3, [r7, #4]
|
|
|
|
huart1.Instance = USART1;
|
|
8002a2a: 4b13 ldr r3, [pc, #76] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a2c: 4a13 ldr r2, [pc, #76] @ (8002a7c <rs485_configure_usart1+0x70>)
|
|
8002a2e: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */
|
|
8002a30: 4b11 ldr r3, [pc, #68] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a32: f44f 5216 mov.w r2, #9600 @ 0x2580
|
|
8002a36: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8002a38: 4b0f ldr r3, [pc, #60] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a3a: 2200 movs r2, #0
|
|
8002a3c: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8002a3e: 4b0e ldr r3, [pc, #56] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a40: 2200 movs r2, #0
|
|
8002a42: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8002a44: 4b0c ldr r3, [pc, #48] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a46: 2200 movs r2, #0
|
|
8002a48: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8002a4a: 4b0b ldr r3, [pc, #44] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a4c: 220c movs r2, #12
|
|
8002a4e: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
|
|
8002a50: 4b09 ldr r3, [pc, #36] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a52: 2200 movs r2, #0
|
|
8002a54: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8002a56: 4b08 ldr r3, [pc, #32] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a58: 2200 movs r2, #0
|
|
8002a5a: 61da str r2, [r3, #28]
|
|
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8002a5c: 4806 ldr r0, [pc, #24] @ (8002a78 <rs485_configure_usart1+0x6c>)
|
|
8002a5e: f003 f88d bl 8005b7c <HAL_UART_Init>
|
|
8002a62: 4603 mov r3, r0
|
|
8002a64: 2b00 cmp r3, #0
|
|
8002a66: d001 beq.n 8002a6c <rs485_configure_usart1+0x60>
|
|
{
|
|
/* Initialization Error */
|
|
while(1);
|
|
8002a68: bf00 nop
|
|
8002a6a: e7fd b.n 8002a68 <rs485_configure_usart1+0x5c>
|
|
}
|
|
}
|
|
8002a6c: bf00 nop
|
|
8002a6e: 3708 adds r7, #8
|
|
8002a70: 46bd mov sp, r7
|
|
8002a72: bd80 pop {r7, pc}
|
|
8002a74: 40021000 .word 0x40021000
|
|
8002a78: 200006d0 .word 0x200006d0
|
|
8002a7c: 40013800 .word 0x40013800
|
|
|
|
08002a80 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8002a80: b480 push {r7}
|
|
8002a82: b085 sub sp, #20
|
|
8002a84: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8002a86: 4b15 ldr r3, [pc, #84] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002a88: 699b ldr r3, [r3, #24]
|
|
8002a8a: 4a14 ldr r2, [pc, #80] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002a8c: f043 0301 orr.w r3, r3, #1
|
|
8002a90: 6193 str r3, [r2, #24]
|
|
8002a92: 4b12 ldr r3, [pc, #72] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002a94: 699b ldr r3, [r3, #24]
|
|
8002a96: f003 0301 and.w r3, r3, #1
|
|
8002a9a: 60bb str r3, [r7, #8]
|
|
8002a9c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002a9e: 4b0f ldr r3, [pc, #60] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002aa0: 69db ldr r3, [r3, #28]
|
|
8002aa2: 4a0e ldr r2, [pc, #56] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002aa4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8002aa8: 61d3 str r3, [r2, #28]
|
|
8002aaa: 4b0c ldr r3, [pc, #48] @ (8002adc <HAL_MspInit+0x5c>)
|
|
8002aac: 69db ldr r3, [r3, #28]
|
|
8002aae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002ab2: 607b str r3, [r7, #4]
|
|
8002ab4: 687b ldr r3, [r7, #4]
|
|
|
|
/* System interrupt init*/
|
|
|
|
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
*/
|
|
__HAL_AFIO_REMAP_SWJ_NOJTAG();
|
|
8002ab6: 4b0a ldr r3, [pc, #40] @ (8002ae0 <HAL_MspInit+0x60>)
|
|
8002ab8: 685b ldr r3, [r3, #4]
|
|
8002aba: 60fb str r3, [r7, #12]
|
|
8002abc: 68fb ldr r3, [r7, #12]
|
|
8002abe: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
|
|
8002ac2: 60fb str r3, [r7, #12]
|
|
8002ac4: 68fb ldr r3, [r7, #12]
|
|
8002ac6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8002aca: 60fb str r3, [r7, #12]
|
|
8002acc: 4a04 ldr r2, [pc, #16] @ (8002ae0 <HAL_MspInit+0x60>)
|
|
8002ace: 68fb ldr r3, [r7, #12]
|
|
8002ad0: 6053 str r3, [r2, #4]
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8002ad2: bf00 nop
|
|
8002ad4: 3714 adds r7, #20
|
|
8002ad6: 46bd mov sp, r7
|
|
8002ad8: bc80 pop {r7}
|
|
8002ada: 4770 bx lr
|
|
8002adc: 40021000 .word 0x40021000
|
|
8002ae0: 40010000 .word 0x40010000
|
|
|
|
08002ae4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8002ae4: b480 push {r7}
|
|
8002ae6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8002ae8: bf00 nop
|
|
8002aea: e7fd b.n 8002ae8 <NMI_Handler+0x4>
|
|
|
|
08002aec <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8002aec: b480 push {r7}
|
|
8002aee: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8002af0: bf00 nop
|
|
8002af2: e7fd b.n 8002af0 <HardFault_Handler+0x4>
|
|
|
|
08002af4 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8002af4: b480 push {r7}
|
|
8002af6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8002af8: bf00 nop
|
|
8002afa: e7fd b.n 8002af8 <MemManage_Handler+0x4>
|
|
|
|
08002afc <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8002afc: b480 push {r7}
|
|
8002afe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8002b00: bf00 nop
|
|
8002b02: e7fd b.n 8002b00 <BusFault_Handler+0x4>
|
|
|
|
08002b04 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8002b04: b480 push {r7}
|
|
8002b06: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8002b08: bf00 nop
|
|
8002b0a: e7fd b.n 8002b08 <UsageFault_Handler+0x4>
|
|
|
|
08002b0c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8002b0c: b480 push {r7}
|
|
8002b0e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8002b10: bf00 nop
|
|
8002b12: 46bd mov sp, r7
|
|
8002b14: bc80 pop {r7}
|
|
8002b16: 4770 bx lr
|
|
|
|
08002b18 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8002b18: b480 push {r7}
|
|
8002b1a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8002b1c: bf00 nop
|
|
8002b1e: 46bd mov sp, r7
|
|
8002b20: bc80 pop {r7}
|
|
8002b22: 4770 bx lr
|
|
|
|
08002b24 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8002b24: b480 push {r7}
|
|
8002b26: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8002b28: bf00 nop
|
|
8002b2a: 46bd mov sp, r7
|
|
8002b2c: bc80 pop {r7}
|
|
8002b2e: 4770 bx lr
|
|
|
|
08002b30 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8002b30: b580 push {r7, lr}
|
|
8002b32: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8002b34: f000 f97a bl 8002e2c <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8002b38: bf00 nop
|
|
8002b3a: bd80 pop {r7, pc}
|
|
|
|
08002b3c <TIM3_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM3 global interrupt.
|
|
*/
|
|
void TIM3_IRQHandler(void)
|
|
{
|
|
8002b3c: b580 push {r7, lr}
|
|
8002b3e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM3_IRQn 0 */
|
|
|
|
/* USER CODE END TIM3_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim3);
|
|
8002b40: 4802 ldr r0, [pc, #8] @ (8002b4c <TIM3_IRQHandler+0x10>)
|
|
8002b42: f002 fccb bl 80054dc <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM3_IRQn 1 */
|
|
|
|
/* USER CODE END TIM3_IRQn 1 */
|
|
}
|
|
8002b46: bf00 nop
|
|
8002b48: bd80 pop {r7, pc}
|
|
8002b4a: bf00 nop
|
|
8002b4c: 20000718 .word 0x20000718
|
|
|
|
08002b50 <USART1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART1 global interrupt.
|
|
*/
|
|
void USART1_IRQHandler(void)
|
|
{
|
|
8002b50: b580 push {r7, lr}
|
|
8002b52: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart1);
|
|
8002b54: 4802 ldr r0, [pc, #8] @ (8002b60 <USART1_IRQHandler+0x10>)
|
|
8002b56: f003 f8ed bl 8005d34 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
}
|
|
8002b5a: bf00 nop
|
|
8002b5c: bd80 pop {r7, pc}
|
|
8002b5e: bf00 nop
|
|
8002b60: 20000760 .word 0x20000760
|
|
|
|
08002b64 <SystemInit>:
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
8002b64: b480 push {r7}
|
|
8002b66: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8002b68: bf00 nop
|
|
8002b6a: 46bd mov sp, r7
|
|
8002b6c: bc80 pop {r7}
|
|
8002b6e: 4770 bx lr
|
|
|
|
08002b70 <MX_TIM3_Init>:
|
|
|
|
TIM_HandleTypeDef htim3;
|
|
|
|
/* TIM3 init function */
|
|
void MX_TIM3_Init(void)
|
|
{
|
|
8002b70: b580 push {r7, lr}
|
|
8002b72: b086 sub sp, #24
|
|
8002b74: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8002b76: f107 0308 add.w r3, r7, #8
|
|
8002b7a: 2200 movs r2, #0
|
|
8002b7c: 601a str r2, [r3, #0]
|
|
8002b7e: 605a str r2, [r3, #4]
|
|
8002b80: 609a str r2, [r3, #8]
|
|
8002b82: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8002b84: 463b mov r3, r7
|
|
8002b86: 2200 movs r2, #0
|
|
8002b88: 601a str r2, [r3, #0]
|
|
8002b8a: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8002b8c: 4b1d ldr r3, [pc, #116] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002b8e: 4a1e ldr r2, [pc, #120] @ (8002c08 <MX_TIM3_Init+0x98>)
|
|
8002b90: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 2;
|
|
8002b92: 4b1c ldr r3, [pc, #112] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002b94: 2202 movs r2, #2
|
|
8002b96: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8002b98: 4b1a ldr r3, [pc, #104] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002b9a: 2200 movs r2, #0
|
|
8002b9c: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 999;
|
|
8002b9e: 4b19 ldr r3, [pc, #100] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002ba0: f240 32e7 movw r2, #999 @ 0x3e7
|
|
8002ba4: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8002ba6: 4b17 ldr r3, [pc, #92] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002ba8: 2200 movs r2, #0
|
|
8002baa: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
|
|
8002bac: 4b15 ldr r3, [pc, #84] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002bae: 2280 movs r2, #128 @ 0x80
|
|
8002bb0: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
|
|
8002bb2: 4814 ldr r0, [pc, #80] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002bb4: f002 fbf0 bl 8005398 <HAL_TIM_Base_Init>
|
|
8002bb8: 4603 mov r3, r0
|
|
8002bba: 2b00 cmp r3, #0
|
|
8002bbc: d001 beq.n 8002bc2 <MX_TIM3_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8002bbe: f7ff fe65 bl 800288c <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8002bc2: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8002bc6: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
|
|
8002bc8: f107 0308 add.w r3, r7, #8
|
|
8002bcc: 4619 mov r1, r3
|
|
8002bce: 480d ldr r0, [pc, #52] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002bd0: f002 fd74 bl 80056bc <HAL_TIM_ConfigClockSource>
|
|
8002bd4: 4603 mov r3, r0
|
|
8002bd6: 2b00 cmp r3, #0
|
|
8002bd8: d001 beq.n 8002bde <MX_TIM3_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8002bda: f7ff fe57 bl 800288c <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8002bde: 2300 movs r3, #0
|
|
8002be0: 603b str r3, [r7, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8002be2: 2300 movs r3, #0
|
|
8002be4: 607b str r3, [r7, #4]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8002be6: 463b mov r3, r7
|
|
8002be8: 4619 mov r1, r3
|
|
8002bea: 4806 ldr r0, [pc, #24] @ (8002c04 <MX_TIM3_Init+0x94>)
|
|
8002bec: f002 ff56 bl 8005a9c <HAL_TIMEx_MasterConfigSynchronization>
|
|
8002bf0: 4603 mov r3, r0
|
|
8002bf2: 2b00 cmp r3, #0
|
|
8002bf4: d001 beq.n 8002bfa <MX_TIM3_Init+0x8a>
|
|
{
|
|
Error_Handler();
|
|
8002bf6: f7ff fe49 bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
8002bfa: bf00 nop
|
|
8002bfc: 3718 adds r7, #24
|
|
8002bfe: 46bd mov sp, r7
|
|
8002c00: bd80 pop {r7, pc}
|
|
8002c02: bf00 nop
|
|
8002c04: 20000718 .word 0x20000718
|
|
8002c08: 40000400 .word 0x40000400
|
|
|
|
08002c0c <HAL_TIM_Base_MspInit>:
|
|
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
|
{
|
|
8002c0c: b580 push {r7, lr}
|
|
8002c0e: b084 sub sp, #16
|
|
8002c10: af00 add r7, sp, #0
|
|
8002c12: 6078 str r0, [r7, #4]
|
|
|
|
if(tim_baseHandle->Instance==TIM3)
|
|
8002c14: 687b ldr r3, [r7, #4]
|
|
8002c16: 681b ldr r3, [r3, #0]
|
|
8002c18: 4a0d ldr r2, [pc, #52] @ (8002c50 <HAL_TIM_Base_MspInit+0x44>)
|
|
8002c1a: 4293 cmp r3, r2
|
|
8002c1c: d113 bne.n 8002c46 <HAL_TIM_Base_MspInit+0x3a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* TIM3 clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8002c1e: 4b0d ldr r3, [pc, #52] @ (8002c54 <HAL_TIM_Base_MspInit+0x48>)
|
|
8002c20: 69db ldr r3, [r3, #28]
|
|
8002c22: 4a0c ldr r2, [pc, #48] @ (8002c54 <HAL_TIM_Base_MspInit+0x48>)
|
|
8002c24: f043 0302 orr.w r3, r3, #2
|
|
8002c28: 61d3 str r3, [r2, #28]
|
|
8002c2a: 4b0a ldr r3, [pc, #40] @ (8002c54 <HAL_TIM_Base_MspInit+0x48>)
|
|
8002c2c: 69db ldr r3, [r3, #28]
|
|
8002c2e: f003 0302 and.w r3, r3, #2
|
|
8002c32: 60fb str r3, [r7, #12]
|
|
8002c34: 68fb ldr r3, [r7, #12]
|
|
|
|
/* TIM3 interrupt Init */
|
|
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
|
|
8002c36: 2200 movs r2, #0
|
|
8002c38: 2100 movs r1, #0
|
|
8002c3a: 201d movs r0, #29
|
|
8002c3c: f000 fbfb bl 8003436 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM3_IRQn);
|
|
8002c40: 201d movs r0, #29
|
|
8002c42: f000 fc14 bl 800346e <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN TIM3_MspInit 1 */
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
}
|
|
}
|
|
8002c46: bf00 nop
|
|
8002c48: 3710 adds r7, #16
|
|
8002c4a: 46bd mov sp, r7
|
|
8002c4c: bd80 pop {r7, pc}
|
|
8002c4e: bf00 nop
|
|
8002c50: 40000400 .word 0x40000400
|
|
8002c54: 40021000 .word 0x40021000
|
|
|
|
08002c58 <MX_USART1_UART_Init>:
|
|
UART_HandleTypeDef huart1;
|
|
|
|
/* USART1 init function */
|
|
|
|
void MX_USART1_UART_Init(void)
|
|
{
|
|
8002c58: b580 push {r7, lr}
|
|
8002c5a: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8002c5c: 4b11 ldr r3, [pc, #68] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c5e: 4a12 ldr r2, [pc, #72] @ (8002ca8 <MX_USART1_UART_Init+0x50>)
|
|
8002c60: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8002c62: 4b10 ldr r3, [pc, #64] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c64: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8002c68: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8002c6a: 4b0e ldr r3, [pc, #56] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c6c: 2200 movs r2, #0
|
|
8002c6e: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8002c70: 4b0c ldr r3, [pc, #48] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c72: 2200 movs r2, #0
|
|
8002c74: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8002c76: 4b0b ldr r3, [pc, #44] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c78: 2200 movs r2, #0
|
|
8002c7a: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8002c7c: 4b09 ldr r3, [pc, #36] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c7e: 220c movs r2, #12
|
|
8002c80: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8002c82: 4b08 ldr r3, [pc, #32] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c84: 2200 movs r2, #0
|
|
8002c86: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8002c88: 4b06 ldr r3, [pc, #24] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c8a: 2200 movs r2, #0
|
|
8002c8c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8002c8e: 4805 ldr r0, [pc, #20] @ (8002ca4 <MX_USART1_UART_Init+0x4c>)
|
|
8002c90: f002 ff74 bl 8005b7c <HAL_UART_Init>
|
|
8002c94: 4603 mov r3, r0
|
|
8002c96: 2b00 cmp r3, #0
|
|
8002c98: d001 beq.n 8002c9e <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8002c9a: f7ff fdf7 bl 800288c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8002c9e: bf00 nop
|
|
8002ca0: bd80 pop {r7, pc}
|
|
8002ca2: bf00 nop
|
|
8002ca4: 20000760 .word 0x20000760
|
|
8002ca8: 40013800 .word 0x40013800
|
|
|
|
08002cac <HAL_UART_MspInit>:
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8002cac: b580 push {r7, lr}
|
|
8002cae: b088 sub sp, #32
|
|
8002cb0: af00 add r7, sp, #0
|
|
8002cb2: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002cb4: f107 0310 add.w r3, r7, #16
|
|
8002cb8: 2200 movs r2, #0
|
|
8002cba: 601a str r2, [r3, #0]
|
|
8002cbc: 605a str r2, [r3, #4]
|
|
8002cbe: 609a str r2, [r3, #8]
|
|
8002cc0: 60da str r2, [r3, #12]
|
|
if(uartHandle->Instance==USART1)
|
|
8002cc2: 687b ldr r3, [r7, #4]
|
|
8002cc4: 681b ldr r3, [r3, #0]
|
|
8002cc6: 4a20 ldr r2, [pc, #128] @ (8002d48 <HAL_UART_MspInit+0x9c>)
|
|
8002cc8: 4293 cmp r3, r2
|
|
8002cca: d139 bne.n 8002d40 <HAL_UART_MspInit+0x94>
|
|
{
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
/* USART1 clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8002ccc: 4b1f ldr r3, [pc, #124] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002cce: 699b ldr r3, [r3, #24]
|
|
8002cd0: 4a1e ldr r2, [pc, #120] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002cd2: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8002cd6: 6193 str r3, [r2, #24]
|
|
8002cd8: 4b1c ldr r3, [pc, #112] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002cda: 699b ldr r3, [r3, #24]
|
|
8002cdc: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002ce0: 60fb str r3, [r7, #12]
|
|
8002ce2: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002ce4: 4b19 ldr r3, [pc, #100] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002ce6: 699b ldr r3, [r3, #24]
|
|
8002ce8: 4a18 ldr r2, [pc, #96] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002cea: f043 0304 orr.w r3, r3, #4
|
|
8002cee: 6193 str r3, [r2, #24]
|
|
8002cf0: 4b16 ldr r3, [pc, #88] @ (8002d4c <HAL_UART_MspInit+0xa0>)
|
|
8002cf2: 699b ldr r3, [r3, #24]
|
|
8002cf4: f003 0304 and.w r3, r3, #4
|
|
8002cf8: 60bb str r3, [r7, #8]
|
|
8002cfa: 68bb ldr r3, [r7, #8]
|
|
/**USART1 GPIO Configuration
|
|
PA9 ------> USART1_TX
|
|
PA10 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = TX_RS485_Pin;
|
|
8002cfc: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8002d00: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002d02: 2302 movs r3, #2
|
|
8002d04: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
|
8002d06: 2301 movs r3, #1
|
|
8002d08: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
|
|
8002d0a: f107 0310 add.w r3, r7, #16
|
|
8002d0e: 4619 mov r1, r3
|
|
8002d10: 480f ldr r0, [pc, #60] @ (8002d50 <HAL_UART_MspInit+0xa4>)
|
|
8002d12: f000 fc79 bl 8003608 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = RX_RS485_Pin;
|
|
8002d16: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8002d1a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8002d1c: 2300 movs r3, #0
|
|
8002d1e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002d20: 2300 movs r3, #0
|
|
8002d22: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
|
|
8002d24: f107 0310 add.w r3, r7, #16
|
|
8002d28: 4619 mov r1, r3
|
|
8002d2a: 4809 ldr r0, [pc, #36] @ (8002d50 <HAL_UART_MspInit+0xa4>)
|
|
8002d2c: f000 fc6c bl 8003608 <HAL_GPIO_Init>
|
|
|
|
/* USART1 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
|
|
8002d30: 2200 movs r2, #0
|
|
8002d32: 2100 movs r1, #0
|
|
8002d34: 2025 movs r0, #37 @ 0x25
|
|
8002d36: f000 fb7e bl 8003436 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
8002d3a: 2025 movs r0, #37 @ 0x25
|
|
8002d3c: f000 fb97 bl 800346e <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USART1_MspInit 1 */
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
}
|
|
}
|
|
8002d40: bf00 nop
|
|
8002d42: 3720 adds r7, #32
|
|
8002d44: 46bd mov sp, r7
|
|
8002d46: bd80 pop {r7, pc}
|
|
8002d48: 40013800 .word 0x40013800
|
|
8002d4c: 40021000 .word 0x40021000
|
|
8002d50: 40010800 .word 0x40010800
|
|
|
|
08002d54 <Reset_Handler>:
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8002d54: f7ff ff06 bl 8002b64 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8002d58: 480b ldr r0, [pc, #44] @ (8002d88 <LoopFillZerobss+0xe>)
|
|
ldr r1, =_edata
|
|
8002d5a: 490c ldr r1, [pc, #48] @ (8002d8c <LoopFillZerobss+0x12>)
|
|
ldr r2, =_sidata
|
|
8002d5c: 4a0c ldr r2, [pc, #48] @ (8002d90 <LoopFillZerobss+0x16>)
|
|
movs r3, #0
|
|
8002d5e: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8002d60: e002 b.n 8002d68 <LoopCopyDataInit>
|
|
|
|
08002d62 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8002d62: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8002d64: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8002d66: 3304 adds r3, #4
|
|
|
|
08002d68 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8002d68: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8002d6a: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8002d6c: d3f9 bcc.n 8002d62 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8002d6e: 4a09 ldr r2, [pc, #36] @ (8002d94 <LoopFillZerobss+0x1a>)
|
|
ldr r4, =_ebss
|
|
8002d70: 4c09 ldr r4, [pc, #36] @ (8002d98 <LoopFillZerobss+0x1e>)
|
|
movs r3, #0
|
|
8002d72: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8002d74: e001 b.n 8002d7a <LoopFillZerobss>
|
|
|
|
08002d76 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8002d76: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8002d78: 3204 adds r2, #4
|
|
|
|
08002d7a <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8002d7a: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8002d7c: d3fb bcc.n 8002d76 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8002d7e: f003 fd21 bl 80067c4 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8002d82: f7ff f9e7 bl 8002154 <main>
|
|
bx lr
|
|
8002d86: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
8002d88: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8002d8c: 20000064 .word 0x20000064
|
|
ldr r2, =_sidata
|
|
8002d90: 08006aac .word 0x08006aac
|
|
ldr r2, =_sbss
|
|
8002d94: 20000064 .word 0x20000064
|
|
ldr r4, =_ebss
|
|
8002d98: 200008e4 .word 0x200008e4
|
|
|
|
08002d9c <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8002d9c: e7fe b.n 8002d9c <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
08002da0 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8002da0: b580 push {r7, lr}
|
|
8002da2: af00 add r7, sp, #0
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8002da4: 4b08 ldr r3, [pc, #32] @ (8002dc8 <HAL_Init+0x28>)
|
|
8002da6: 681b ldr r3, [r3, #0]
|
|
8002da8: 4a07 ldr r2, [pc, #28] @ (8002dc8 <HAL_Init+0x28>)
|
|
8002daa: f043 0310 orr.w r3, r3, #16
|
|
8002dae: 6013 str r3, [r2, #0]
|
|
#endif
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8002db0: 2003 movs r0, #3
|
|
8002db2: f000 fb35 bl 8003420 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8002db6: 200f movs r0, #15
|
|
8002db8: f000 f808 bl 8002dcc <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8002dbc: f7ff fe60 bl 8002a80 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002dc0: 2300 movs r3, #0
|
|
}
|
|
8002dc2: 4618 mov r0, r3
|
|
8002dc4: bd80 pop {r7, pc}
|
|
8002dc6: bf00 nop
|
|
8002dc8: 40022000 .word 0x40022000
|
|
|
|
08002dcc <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8002dcc: b580 push {r7, lr}
|
|
8002dce: b082 sub sp, #8
|
|
8002dd0: af00 add r7, sp, #0
|
|
8002dd2: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8002dd4: 4b12 ldr r3, [pc, #72] @ (8002e20 <HAL_InitTick+0x54>)
|
|
8002dd6: 681a ldr r2, [r3, #0]
|
|
8002dd8: 4b12 ldr r3, [pc, #72] @ (8002e24 <HAL_InitTick+0x58>)
|
|
8002dda: 781b ldrb r3, [r3, #0]
|
|
8002ddc: 4619 mov r1, r3
|
|
8002dde: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8002de2: fbb3 f3f1 udiv r3, r3, r1
|
|
8002de6: fbb2 f3f3 udiv r3, r2, r3
|
|
8002dea: 4618 mov r0, r3
|
|
8002dec: f000 fb4d bl 800348a <HAL_SYSTICK_Config>
|
|
8002df0: 4603 mov r3, r0
|
|
8002df2: 2b00 cmp r3, #0
|
|
8002df4: d001 beq.n 8002dfa <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002df6: 2301 movs r3, #1
|
|
8002df8: e00e b.n 8002e18 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8002dfa: 687b ldr r3, [r7, #4]
|
|
8002dfc: 2b0f cmp r3, #15
|
|
8002dfe: d80a bhi.n 8002e16 <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8002e00: 2200 movs r2, #0
|
|
8002e02: 6879 ldr r1, [r7, #4]
|
|
8002e04: f04f 30ff mov.w r0, #4294967295
|
|
8002e08: f000 fb15 bl 8003436 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8002e0c: 4a06 ldr r2, [pc, #24] @ (8002e28 <HAL_InitTick+0x5c>)
|
|
8002e0e: 687b ldr r3, [r7, #4]
|
|
8002e10: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002e12: 2300 movs r3, #0
|
|
8002e14: e000 b.n 8002e18 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
8002e16: 2301 movs r3, #1
|
|
}
|
|
8002e18: 4618 mov r0, r3
|
|
8002e1a: 3708 adds r7, #8
|
|
8002e1c: 46bd mov sp, r7
|
|
8002e1e: bd80 pop {r7, pc}
|
|
8002e20: 20000008 .word 0x20000008
|
|
8002e24: 20000010 .word 0x20000010
|
|
8002e28: 2000000c .word 0x2000000c
|
|
|
|
08002e2c <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8002e2c: b480 push {r7}
|
|
8002e2e: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8002e30: 4b05 ldr r3, [pc, #20] @ (8002e48 <HAL_IncTick+0x1c>)
|
|
8002e32: 781b ldrb r3, [r3, #0]
|
|
8002e34: 461a mov r2, r3
|
|
8002e36: 4b05 ldr r3, [pc, #20] @ (8002e4c <HAL_IncTick+0x20>)
|
|
8002e38: 681b ldr r3, [r3, #0]
|
|
8002e3a: 4413 add r3, r2
|
|
8002e3c: 4a03 ldr r2, [pc, #12] @ (8002e4c <HAL_IncTick+0x20>)
|
|
8002e3e: 6013 str r3, [r2, #0]
|
|
}
|
|
8002e40: bf00 nop
|
|
8002e42: 46bd mov sp, r7
|
|
8002e44: bc80 pop {r7}
|
|
8002e46: 4770 bx lr
|
|
8002e48: 20000010 .word 0x20000010
|
|
8002e4c: 200007a8 .word 0x200007a8
|
|
|
|
08002e50 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8002e50: b480 push {r7}
|
|
8002e52: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8002e54: 4b02 ldr r3, [pc, #8] @ (8002e60 <HAL_GetTick+0x10>)
|
|
8002e56: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002e58: 4618 mov r0, r3
|
|
8002e5a: 46bd mov sp, r7
|
|
8002e5c: bc80 pop {r7}
|
|
8002e5e: 4770 bx lr
|
|
8002e60: 200007a8 .word 0x200007a8
|
|
|
|
08002e64 <HAL_ADC_Init>:
|
|
* of structure "ADC_InitTypeDef".
|
|
* @param hadc: ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002e64: b580 push {r7, lr}
|
|
8002e66: b086 sub sp, #24
|
|
8002e68: af00 add r7, sp, #0
|
|
8002e6a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002e6c: 2300 movs r3, #0
|
|
8002e6e: 75fb strb r3, [r7, #23]
|
|
uint32_t tmp_cr1 = 0U;
|
|
8002e70: 2300 movs r3, #0
|
|
8002e72: 613b str r3, [r7, #16]
|
|
uint32_t tmp_cr2 = 0U;
|
|
8002e74: 2300 movs r3, #0
|
|
8002e76: 60bb str r3, [r7, #8]
|
|
uint32_t tmp_sqr1 = 0U;
|
|
8002e78: 2300 movs r3, #0
|
|
8002e7a: 60fb str r3, [r7, #12]
|
|
|
|
/* Check ADC handle */
|
|
if(hadc == NULL)
|
|
8002e7c: 687b ldr r3, [r7, #4]
|
|
8002e7e: 2b00 cmp r3, #0
|
|
8002e80: d101 bne.n 8002e86 <HAL_ADC_Init+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e82: 2301 movs r3, #1
|
|
8002e84: e0be b.n 8003004 <HAL_ADC_Init+0x1a0>
|
|
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
|
|
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
|
|
|
|
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
8002e86: 687b ldr r3, [r7, #4]
|
|
8002e88: 689b ldr r3, [r3, #8]
|
|
8002e8a: 2b00 cmp r3, #0
|
|
/* Refer to header of this file for more details on clock enabling */
|
|
/* procedure. */
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
8002e8c: 687b ldr r3, [r7, #4]
|
|
8002e8e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002e90: 2b00 cmp r3, #0
|
|
8002e92: d109 bne.n 8002ea8 <HAL_ADC_Init+0x44>
|
|
{
|
|
/* Initialize ADC error code */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8002e94: 687b ldr r3, [r7, #4]
|
|
8002e96: 2200 movs r2, #0
|
|
8002e98: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
8002e9a: 687b ldr r3, [r7, #4]
|
|
8002e9c: 2200 movs r2, #0
|
|
8002e9e: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
8002ea2: 6878 ldr r0, [r7, #4]
|
|
8002ea4: f7fe fcce bl 8001844 <HAL_ADC_MspInit>
|
|
/* Stop potential conversion on going, on regular and injected groups */
|
|
/* Disable ADC peripheral */
|
|
/* Note: In case of ADC already enabled, precaution to not launch an */
|
|
/* unwanted conversion while modifying register CR2 by writing 1 to */
|
|
/* bit ADON. */
|
|
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
|
|
8002ea8: 6878 ldr r0, [r7, #4]
|
|
8002eaa: f000 f9ab bl 8003204 <ADC_ConversionStop_Disable>
|
|
8002eae: 4603 mov r3, r0
|
|
8002eb0: 75fb strb r3, [r7, #23]
|
|
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed. */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
|
|
8002eb2: 687b ldr r3, [r7, #4]
|
|
8002eb4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002eb6: f003 0310 and.w r3, r3, #16
|
|
8002eba: 2b00 cmp r3, #0
|
|
8002ebc: f040 8099 bne.w 8002ff2 <HAL_ADC_Init+0x18e>
|
|
8002ec0: 7dfb ldrb r3, [r7, #23]
|
|
8002ec2: 2b00 cmp r3, #0
|
|
8002ec4: f040 8095 bne.w 8002ff2 <HAL_ADC_Init+0x18e>
|
|
(tmp_hal_status == HAL_OK) )
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002ec8: 687b ldr r3, [r7, #4]
|
|
8002eca: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002ecc: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
8002ed0: f023 0302 bic.w r3, r3, #2
|
|
8002ed4: f043 0202 orr.w r2, r3, #2
|
|
8002ed8: 687b ldr r3, [r7, #4]
|
|
8002eda: 629a str r2, [r3, #40] @ 0x28
|
|
/* - continuous conversion mode */
|
|
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
|
|
/* HAL_ADC_Start_xxx functions because if set in this function, */
|
|
/* a conversion on injected group would start a conversion also on */
|
|
/* regular group after ADC enabling. */
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
8002edc: 687b ldr r3, [r7, #4]
|
|
8002ede: 685a ldr r2, [r3, #4]
|
|
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
|
|
8002ee0: 687b ldr r3, [r7, #4]
|
|
8002ee2: 69db ldr r3, [r3, #28]
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
8002ee4: 431a orrs r2, r3
|
|
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
|
|
8002ee6: 687b ldr r3, [r7, #4]
|
|
8002ee8: 7b1b ldrb r3, [r3, #12]
|
|
8002eea: 005b lsls r3, r3, #1
|
|
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
|
|
8002eec: 4313 orrs r3, r2
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
8002eee: 68ba ldr r2, [r7, #8]
|
|
8002ef0: 4313 orrs r3, r2
|
|
8002ef2: 60bb str r3, [r7, #8]
|
|
|
|
/* Configuration of ADC: */
|
|
/* - scan mode */
|
|
/* - discontinuous mode disable/enable */
|
|
/* - discontinuous mode number of conversions */
|
|
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
|
|
8002ef4: 687b ldr r3, [r7, #4]
|
|
8002ef6: 689b ldr r3, [r3, #8]
|
|
8002ef8: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8002efc: d003 beq.n 8002f06 <HAL_ADC_Init+0xa2>
|
|
8002efe: 687b ldr r3, [r7, #4]
|
|
8002f00: 689b ldr r3, [r3, #8]
|
|
8002f02: 2b01 cmp r3, #1
|
|
8002f04: d102 bne.n 8002f0c <HAL_ADC_Init+0xa8>
|
|
8002f06: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8002f0a: e000 b.n 8002f0e <HAL_ADC_Init+0xaa>
|
|
8002f0c: 2300 movs r3, #0
|
|
8002f0e: 693a ldr r2, [r7, #16]
|
|
8002f10: 4313 orrs r3, r2
|
|
8002f12: 613b str r3, [r7, #16]
|
|
|
|
/* Enable discontinuous mode only if continuous mode is disabled */
|
|
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
|
|
/* discontinuous is set anyway, but will have no effect on ADC HW. */
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
8002f14: 687b ldr r3, [r7, #4]
|
|
8002f16: 7d1b ldrb r3, [r3, #20]
|
|
8002f18: 2b01 cmp r3, #1
|
|
8002f1a: d119 bne.n 8002f50 <HAL_ADC_Init+0xec>
|
|
{
|
|
if (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8002f1c: 687b ldr r3, [r7, #4]
|
|
8002f1e: 7b1b ldrb r3, [r3, #12]
|
|
8002f20: 2b00 cmp r3, #0
|
|
8002f22: d109 bne.n 8002f38 <HAL_ADC_Init+0xd4>
|
|
{
|
|
/* Enable the selected ADC regular discontinuous mode */
|
|
/* Set the number of channels to be converted in discontinuous mode */
|
|
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
|
|
8002f24: 687b ldr r3, [r7, #4]
|
|
8002f26: 699b ldr r3, [r3, #24]
|
|
8002f28: 3b01 subs r3, #1
|
|
8002f2a: 035a lsls r2, r3, #13
|
|
8002f2c: 693b ldr r3, [r7, #16]
|
|
8002f2e: 4313 orrs r3, r2
|
|
8002f30: f443 6300 orr.w r3, r3, #2048 @ 0x800
|
|
8002f34: 613b str r3, [r7, #16]
|
|
8002f36: e00b b.n 8002f50 <HAL_ADC_Init+0xec>
|
|
{
|
|
/* ADC regular group settings continuous and sequencer discontinuous*/
|
|
/* cannot be enabled simultaneously. */
|
|
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8002f38: 687b ldr r3, [r7, #4]
|
|
8002f3a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002f3c: f043 0220 orr.w r2, r3, #32
|
|
8002f40: 687b ldr r3, [r7, #4]
|
|
8002f42: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002f44: 687b ldr r3, [r7, #4]
|
|
8002f46: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002f48: f043 0201 orr.w r2, r3, #1
|
|
8002f4c: 687b ldr r3, [r7, #4]
|
|
8002f4e: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
}
|
|
|
|
/* Update ADC configuration register CR1 with previous settings */
|
|
MODIFY_REG(hadc->Instance->CR1,
|
|
8002f50: 687b ldr r3, [r7, #4]
|
|
8002f52: 681b ldr r3, [r3, #0]
|
|
8002f54: 685b ldr r3, [r3, #4]
|
|
8002f56: f423 4169 bic.w r1, r3, #59648 @ 0xe900
|
|
8002f5a: 687b ldr r3, [r7, #4]
|
|
8002f5c: 681b ldr r3, [r3, #0]
|
|
8002f5e: 693a ldr r2, [r7, #16]
|
|
8002f60: 430a orrs r2, r1
|
|
8002f62: 605a str r2, [r3, #4]
|
|
ADC_CR1_DISCEN |
|
|
ADC_CR1_DISCNUM ,
|
|
tmp_cr1 );
|
|
|
|
/* Update ADC configuration register CR2 with previous settings */
|
|
MODIFY_REG(hadc->Instance->CR2,
|
|
8002f64: 687b ldr r3, [r7, #4]
|
|
8002f66: 681b ldr r3, [r3, #0]
|
|
8002f68: 689a ldr r2, [r3, #8]
|
|
8002f6a: 4b28 ldr r3, [pc, #160] @ (800300c <HAL_ADC_Init+0x1a8>)
|
|
8002f6c: 4013 ands r3, r2
|
|
8002f6e: 687a ldr r2, [r7, #4]
|
|
8002f70: 6812 ldr r2, [r2, #0]
|
|
8002f72: 68b9 ldr r1, [r7, #8]
|
|
8002f74: 430b orrs r3, r1
|
|
8002f76: 6093 str r3, [r2, #8]
|
|
/* Note: Scan mode is present by hardware on this device and, if */
|
|
/* disabled, discards automatically nb of conversions. Anyway, nb of */
|
|
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion" */
|
|
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
|
|
8002f78: 687b ldr r3, [r7, #4]
|
|
8002f7a: 689b ldr r3, [r3, #8]
|
|
8002f7c: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8002f80: d003 beq.n 8002f8a <HAL_ADC_Init+0x126>
|
|
8002f82: 687b ldr r3, [r7, #4]
|
|
8002f84: 689b ldr r3, [r3, #8]
|
|
8002f86: 2b01 cmp r3, #1
|
|
8002f88: d104 bne.n 8002f94 <HAL_ADC_Init+0x130>
|
|
{
|
|
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
|
|
8002f8a: 687b ldr r3, [r7, #4]
|
|
8002f8c: 691b ldr r3, [r3, #16]
|
|
8002f8e: 3b01 subs r3, #1
|
|
8002f90: 051b lsls r3, r3, #20
|
|
8002f92: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
MODIFY_REG(hadc->Instance->SQR1,
|
|
8002f94: 687b ldr r3, [r7, #4]
|
|
8002f96: 681b ldr r3, [r3, #0]
|
|
8002f98: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002f9a: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
|
|
8002f9e: 687b ldr r3, [r7, #4]
|
|
8002fa0: 681b ldr r3, [r3, #0]
|
|
8002fa2: 68fa ldr r2, [r7, #12]
|
|
8002fa4: 430a orrs r2, r1
|
|
8002fa6: 62da str r2, [r3, #44] @ 0x2c
|
|
/* ensure of no potential problem of ADC core IP clocking. */
|
|
/* Check through register CR2 (excluding bits set in other functions: */
|
|
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
|
|
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
|
|
/* measurement path bit (TSVREFE). */
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
8002fa8: 687b ldr r3, [r7, #4]
|
|
8002faa: 681b ldr r3, [r3, #0]
|
|
8002fac: 689a ldr r2, [r3, #8]
|
|
8002fae: 4b18 ldr r3, [pc, #96] @ (8003010 <HAL_ADC_Init+0x1ac>)
|
|
8002fb0: 4013 ands r3, r2
|
|
8002fb2: 68ba ldr r2, [r7, #8]
|
|
8002fb4: 429a cmp r2, r3
|
|
8002fb6: d10b bne.n 8002fd0 <HAL_ADC_Init+0x16c>
|
|
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
|
|
ADC_CR2_TSVREFE ))
|
|
== tmp_cr2)
|
|
{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8002fb8: 687b ldr r3, [r7, #4]
|
|
8002fba: 2200 movs r2, #0
|
|
8002fbc: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002fbe: 687b ldr r3, [r7, #4]
|
|
8002fc0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002fc2: f023 0303 bic.w r3, r3, #3
|
|
8002fc6: f043 0201 orr.w r2, r3, #1
|
|
8002fca: 687b ldr r3, [r7, #4]
|
|
8002fcc: 629a str r2, [r3, #40] @ 0x28
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
8002fce: e018 b.n 8003002 <HAL_ADC_Init+0x19e>
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002fd0: 687b ldr r3, [r7, #4]
|
|
8002fd2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002fd4: f023 0312 bic.w r3, r3, #18
|
|
8002fd8: f043 0210 orr.w r2, r3, #16
|
|
8002fdc: 687b ldr r3, [r7, #4]
|
|
8002fde: 629a str r2, [r3, #40] @ 0x28
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002fe0: 687b ldr r3, [r7, #4]
|
|
8002fe2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002fe4: f043 0201 orr.w r2, r3, #1
|
|
8002fe8: 687b ldr r3, [r7, #4]
|
|
8002fea: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002fec: 2301 movs r3, #1
|
|
8002fee: 75fb strb r3, [r7, #23]
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
8002ff0: e007 b.n 8003002 <HAL_ADC_Init+0x19e>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002ff2: 687b ldr r3, [r7, #4]
|
|
8002ff4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002ff6: f043 0210 orr.w r2, r3, #16
|
|
8002ffa: 687b ldr r3, [r7, #4]
|
|
8002ffc: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002ffe: 2301 movs r3, #1
|
|
8003000: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8003002: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8003004: 4618 mov r0, r3
|
|
8003006: 3718 adds r7, #24
|
|
8003008: 46bd mov sp, r7
|
|
800300a: bd80 pop {r7, pc}
|
|
800300c: ffe1f7fd .word 0xffe1f7fd
|
|
8003010: ff1f0efe .word 0xff1f0efe
|
|
|
|
08003014 <HAL_ADC_ConfigChannel>:
|
|
* @param hadc: ADC handle
|
|
* @param sConfig: Structure of ADC channel for regular group.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
|
{
|
|
8003014: b480 push {r7}
|
|
8003016: b085 sub sp, #20
|
|
8003018: af00 add r7, sp, #0
|
|
800301a: 6078 str r0, [r7, #4]
|
|
800301c: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
800301e: 2300 movs r3, #0
|
|
8003020: 73fb strb r3, [r7, #15]
|
|
__IO uint32_t wait_loop_index = 0U;
|
|
8003022: 2300 movs r3, #0
|
|
8003024: 60bb str r3, [r7, #8]
|
|
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
|
|
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
|
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8003026: 687b ldr r3, [r7, #4]
|
|
8003028: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
800302c: 2b01 cmp r3, #1
|
|
800302e: d101 bne.n 8003034 <HAL_ADC_ConfigChannel+0x20>
|
|
8003030: 2302 movs r3, #2
|
|
8003032: e0dc b.n 80031ee <HAL_ADC_ConfigChannel+0x1da>
|
|
8003034: 687b ldr r3, [r7, #4]
|
|
8003036: 2201 movs r2, #1
|
|
8003038: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
|
|
/* Regular sequence configuration */
|
|
/* For Rank 1 to 6 */
|
|
if (sConfig->Rank < 7U)
|
|
800303c: 683b ldr r3, [r7, #0]
|
|
800303e: 685b ldr r3, [r3, #4]
|
|
8003040: 2b06 cmp r3, #6
|
|
8003042: d81c bhi.n 800307e <HAL_ADC_ConfigChannel+0x6a>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR3 ,
|
|
8003044: 687b ldr r3, [r7, #4]
|
|
8003046: 681b ldr r3, [r3, #0]
|
|
8003048: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
800304a: 683b ldr r3, [r7, #0]
|
|
800304c: 685a ldr r2, [r3, #4]
|
|
800304e: 4613 mov r3, r2
|
|
8003050: 009b lsls r3, r3, #2
|
|
8003052: 4413 add r3, r2
|
|
8003054: 3b05 subs r3, #5
|
|
8003056: 221f movs r2, #31
|
|
8003058: fa02 f303 lsl.w r3, r2, r3
|
|
800305c: 43db mvns r3, r3
|
|
800305e: 4019 ands r1, r3
|
|
8003060: 683b ldr r3, [r7, #0]
|
|
8003062: 6818 ldr r0, [r3, #0]
|
|
8003064: 683b ldr r3, [r7, #0]
|
|
8003066: 685a ldr r2, [r3, #4]
|
|
8003068: 4613 mov r3, r2
|
|
800306a: 009b lsls r3, r3, #2
|
|
800306c: 4413 add r3, r2
|
|
800306e: 3b05 subs r3, #5
|
|
8003070: fa00 f203 lsl.w r2, r0, r3
|
|
8003074: 687b ldr r3, [r7, #4]
|
|
8003076: 681b ldr r3, [r3, #0]
|
|
8003078: 430a orrs r2, r1
|
|
800307a: 635a str r2, [r3, #52] @ 0x34
|
|
800307c: e03c b.n 80030f8 <HAL_ADC_ConfigChannel+0xe4>
|
|
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
|
|
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 7 to 12 */
|
|
else if (sConfig->Rank < 13U)
|
|
800307e: 683b ldr r3, [r7, #0]
|
|
8003080: 685b ldr r3, [r3, #4]
|
|
8003082: 2b0c cmp r3, #12
|
|
8003084: d81c bhi.n 80030c0 <HAL_ADC_ConfigChannel+0xac>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR2 ,
|
|
8003086: 687b ldr r3, [r7, #4]
|
|
8003088: 681b ldr r3, [r3, #0]
|
|
800308a: 6b19 ldr r1, [r3, #48] @ 0x30
|
|
800308c: 683b ldr r3, [r7, #0]
|
|
800308e: 685a ldr r2, [r3, #4]
|
|
8003090: 4613 mov r3, r2
|
|
8003092: 009b lsls r3, r3, #2
|
|
8003094: 4413 add r3, r2
|
|
8003096: 3b23 subs r3, #35 @ 0x23
|
|
8003098: 221f movs r2, #31
|
|
800309a: fa02 f303 lsl.w r3, r2, r3
|
|
800309e: 43db mvns r3, r3
|
|
80030a0: 4019 ands r1, r3
|
|
80030a2: 683b ldr r3, [r7, #0]
|
|
80030a4: 6818 ldr r0, [r3, #0]
|
|
80030a6: 683b ldr r3, [r7, #0]
|
|
80030a8: 685a ldr r2, [r3, #4]
|
|
80030aa: 4613 mov r3, r2
|
|
80030ac: 009b lsls r3, r3, #2
|
|
80030ae: 4413 add r3, r2
|
|
80030b0: 3b23 subs r3, #35 @ 0x23
|
|
80030b2: fa00 f203 lsl.w r2, r0, r3
|
|
80030b6: 687b ldr r3, [r7, #4]
|
|
80030b8: 681b ldr r3, [r3, #0]
|
|
80030ba: 430a orrs r2, r1
|
|
80030bc: 631a str r2, [r3, #48] @ 0x30
|
|
80030be: e01b b.n 80030f8 <HAL_ADC_ConfigChannel+0xe4>
|
|
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 13 to 16 */
|
|
else
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR1 ,
|
|
80030c0: 687b ldr r3, [r7, #4]
|
|
80030c2: 681b ldr r3, [r3, #0]
|
|
80030c4: 6ad9 ldr r1, [r3, #44] @ 0x2c
|
|
80030c6: 683b ldr r3, [r7, #0]
|
|
80030c8: 685a ldr r2, [r3, #4]
|
|
80030ca: 4613 mov r3, r2
|
|
80030cc: 009b lsls r3, r3, #2
|
|
80030ce: 4413 add r3, r2
|
|
80030d0: 3b41 subs r3, #65 @ 0x41
|
|
80030d2: 221f movs r2, #31
|
|
80030d4: fa02 f303 lsl.w r3, r2, r3
|
|
80030d8: 43db mvns r3, r3
|
|
80030da: 4019 ands r1, r3
|
|
80030dc: 683b ldr r3, [r7, #0]
|
|
80030de: 6818 ldr r0, [r3, #0]
|
|
80030e0: 683b ldr r3, [r7, #0]
|
|
80030e2: 685a ldr r2, [r3, #4]
|
|
80030e4: 4613 mov r3, r2
|
|
80030e6: 009b lsls r3, r3, #2
|
|
80030e8: 4413 add r3, r2
|
|
80030ea: 3b41 subs r3, #65 @ 0x41
|
|
80030ec: fa00 f203 lsl.w r2, r0, r3
|
|
80030f0: 687b ldr r3, [r7, #4]
|
|
80030f2: 681b ldr r3, [r3, #0]
|
|
80030f4: 430a orrs r2, r1
|
|
80030f6: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
|
|
/* Channel sampling time configuration */
|
|
/* For channels 10 to 17 */
|
|
if (sConfig->Channel >= ADC_CHANNEL_10)
|
|
80030f8: 683b ldr r3, [r7, #0]
|
|
80030fa: 681b ldr r3, [r3, #0]
|
|
80030fc: 2b09 cmp r3, #9
|
|
80030fe: d91c bls.n 800313a <HAL_ADC_ConfigChannel+0x126>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR1 ,
|
|
8003100: 687b ldr r3, [r7, #4]
|
|
8003102: 681b ldr r3, [r3, #0]
|
|
8003104: 68d9 ldr r1, [r3, #12]
|
|
8003106: 683b ldr r3, [r7, #0]
|
|
8003108: 681a ldr r2, [r3, #0]
|
|
800310a: 4613 mov r3, r2
|
|
800310c: 005b lsls r3, r3, #1
|
|
800310e: 4413 add r3, r2
|
|
8003110: 3b1e subs r3, #30
|
|
8003112: 2207 movs r2, #7
|
|
8003114: fa02 f303 lsl.w r3, r2, r3
|
|
8003118: 43db mvns r3, r3
|
|
800311a: 4019 ands r1, r3
|
|
800311c: 683b ldr r3, [r7, #0]
|
|
800311e: 6898 ldr r0, [r3, #8]
|
|
8003120: 683b ldr r3, [r7, #0]
|
|
8003122: 681a ldr r2, [r3, #0]
|
|
8003124: 4613 mov r3, r2
|
|
8003126: 005b lsls r3, r3, #1
|
|
8003128: 4413 add r3, r2
|
|
800312a: 3b1e subs r3, #30
|
|
800312c: fa00 f203 lsl.w r2, r0, r3
|
|
8003130: 687b ldr r3, [r7, #4]
|
|
8003132: 681b ldr r3, [r3, #0]
|
|
8003134: 430a orrs r2, r1
|
|
8003136: 60da str r2, [r3, #12]
|
|
8003138: e019 b.n 800316e <HAL_ADC_ConfigChannel+0x15a>
|
|
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
|
|
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
|
|
}
|
|
else /* For channels 0 to 9 */
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR2 ,
|
|
800313a: 687b ldr r3, [r7, #4]
|
|
800313c: 681b ldr r3, [r3, #0]
|
|
800313e: 6919 ldr r1, [r3, #16]
|
|
8003140: 683b ldr r3, [r7, #0]
|
|
8003142: 681a ldr r2, [r3, #0]
|
|
8003144: 4613 mov r3, r2
|
|
8003146: 005b lsls r3, r3, #1
|
|
8003148: 4413 add r3, r2
|
|
800314a: 2207 movs r2, #7
|
|
800314c: fa02 f303 lsl.w r3, r2, r3
|
|
8003150: 43db mvns r3, r3
|
|
8003152: 4019 ands r1, r3
|
|
8003154: 683b ldr r3, [r7, #0]
|
|
8003156: 6898 ldr r0, [r3, #8]
|
|
8003158: 683b ldr r3, [r7, #0]
|
|
800315a: 681a ldr r2, [r3, #0]
|
|
800315c: 4613 mov r3, r2
|
|
800315e: 005b lsls r3, r3, #1
|
|
8003160: 4413 add r3, r2
|
|
8003162: fa00 f203 lsl.w r2, r0, r3
|
|
8003166: 687b ldr r3, [r7, #4]
|
|
8003168: 681b ldr r3, [r3, #0]
|
|
800316a: 430a orrs r2, r1
|
|
800316c: 611a str r2, [r3, #16]
|
|
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
|
|
}
|
|
|
|
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
|
|
/* and VREFINT measurement path. */
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
|
|
800316e: 683b ldr r3, [r7, #0]
|
|
8003170: 681b ldr r3, [r3, #0]
|
|
8003172: 2b10 cmp r3, #16
|
|
8003174: d003 beq.n 800317e <HAL_ADC_ConfigChannel+0x16a>
|
|
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
|
|
8003176: 683b ldr r3, [r7, #0]
|
|
8003178: 681b ldr r3, [r3, #0]
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
|
|
800317a: 2b11 cmp r3, #17
|
|
800317c: d132 bne.n 80031e4 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
|
|
/* measurement channels (VrefInt/TempSensor). If these channels are */
|
|
/* intended to be set on other ADC instances, an error is reported. */
|
|
if (hadc->Instance == ADC1)
|
|
800317e: 687b ldr r3, [r7, #4]
|
|
8003180: 681b ldr r3, [r3, #0]
|
|
8003182: 4a1d ldr r2, [pc, #116] @ (80031f8 <HAL_ADC_ConfigChannel+0x1e4>)
|
|
8003184: 4293 cmp r3, r2
|
|
8003186: d125 bne.n 80031d4 <HAL_ADC_ConfigChannel+0x1c0>
|
|
{
|
|
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
|
|
8003188: 687b ldr r3, [r7, #4]
|
|
800318a: 681b ldr r3, [r3, #0]
|
|
800318c: 689b ldr r3, [r3, #8]
|
|
800318e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8003192: 2b00 cmp r3, #0
|
|
8003194: d126 bne.n 80031e4 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
|
|
8003196: 687b ldr r3, [r7, #4]
|
|
8003198: 681b ldr r3, [r3, #0]
|
|
800319a: 689a ldr r2, [r3, #8]
|
|
800319c: 687b ldr r3, [r7, #4]
|
|
800319e: 681b ldr r3, [r3, #0]
|
|
80031a0: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
|
|
80031a4: 609a str r2, [r3, #8]
|
|
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
80031a6: 683b ldr r3, [r7, #0]
|
|
80031a8: 681b ldr r3, [r3, #0]
|
|
80031aa: 2b10 cmp r3, #16
|
|
80031ac: d11a bne.n 80031e4 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
|
|
80031ae: 4b13 ldr r3, [pc, #76] @ (80031fc <HAL_ADC_ConfigChannel+0x1e8>)
|
|
80031b0: 681b ldr r3, [r3, #0]
|
|
80031b2: 4a13 ldr r2, [pc, #76] @ (8003200 <HAL_ADC_ConfigChannel+0x1ec>)
|
|
80031b4: fba2 2303 umull r2, r3, r2, r3
|
|
80031b8: 0c9a lsrs r2, r3, #18
|
|
80031ba: 4613 mov r3, r2
|
|
80031bc: 009b lsls r3, r3, #2
|
|
80031be: 4413 add r3, r2
|
|
80031c0: 005b lsls r3, r3, #1
|
|
80031c2: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
80031c4: e002 b.n 80031cc <HAL_ADC_ConfigChannel+0x1b8>
|
|
{
|
|
wait_loop_index--;
|
|
80031c6: 68bb ldr r3, [r7, #8]
|
|
80031c8: 3b01 subs r3, #1
|
|
80031ca: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
80031cc: 68bb ldr r3, [r7, #8]
|
|
80031ce: 2b00 cmp r3, #0
|
|
80031d0: d1f9 bne.n 80031c6 <HAL_ADC_ConfigChannel+0x1b2>
|
|
80031d2: e007 b.n 80031e4 <HAL_ADC_ConfigChannel+0x1d0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80031d4: 687b ldr r3, [r7, #4]
|
|
80031d6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80031d8: f043 0220 orr.w r2, r3, #32
|
|
80031dc: 687b ldr r3, [r7, #4]
|
|
80031de: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80031e0: 2301 movs r3, #1
|
|
80031e2: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80031e4: 687b ldr r3, [r7, #4]
|
|
80031e6: 2200 movs r2, #0
|
|
80031e8: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80031ec: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80031ee: 4618 mov r0, r3
|
|
80031f0: 3714 adds r7, #20
|
|
80031f2: 46bd mov sp, r7
|
|
80031f4: bc80 pop {r7}
|
|
80031f6: 4770 bx lr
|
|
80031f8: 40012400 .word 0x40012400
|
|
80031fc: 20000008 .word 0x20000008
|
|
8003200: 431bde83 .word 0x431bde83
|
|
|
|
08003204 <ADC_ConversionStop_Disable>:
|
|
* stopped to disable the ADC.
|
|
* @param hadc: ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8003204: b580 push {r7, lr}
|
|
8003206: b084 sub sp, #16
|
|
8003208: af00 add r7, sp, #0
|
|
800320a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
800320c: 2300 movs r3, #0
|
|
800320e: 60fb str r3, [r7, #12]
|
|
|
|
/* Verification if ADC is not already disabled */
|
|
if (ADC_IS_ENABLE(hadc) != RESET)
|
|
8003210: 687b ldr r3, [r7, #4]
|
|
8003212: 681b ldr r3, [r3, #0]
|
|
8003214: 689b ldr r3, [r3, #8]
|
|
8003216: f003 0301 and.w r3, r3, #1
|
|
800321a: 2b01 cmp r3, #1
|
|
800321c: d12e bne.n 800327c <ADC_ConversionStop_Disable+0x78>
|
|
{
|
|
/* Disable the ADC peripheral */
|
|
__HAL_ADC_DISABLE(hadc);
|
|
800321e: 687b ldr r3, [r7, #4]
|
|
8003220: 681b ldr r3, [r3, #0]
|
|
8003222: 689a ldr r2, [r3, #8]
|
|
8003224: 687b ldr r3, [r7, #4]
|
|
8003226: 681b ldr r3, [r3, #0]
|
|
8003228: f022 0201 bic.w r2, r2, #1
|
|
800322c: 609a str r2, [r3, #8]
|
|
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
800322e: f7ff fe0f bl 8002e50 <HAL_GetTick>
|
|
8003232: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait for ADC effectively disabled */
|
|
while(ADC_IS_ENABLE(hadc) != RESET)
|
|
8003234: e01b b.n 800326e <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
|
8003236: f7ff fe0b bl 8002e50 <HAL_GetTick>
|
|
800323a: 4602 mov r2, r0
|
|
800323c: 68fb ldr r3, [r7, #12]
|
|
800323e: 1ad3 subs r3, r2, r3
|
|
8003240: 2b02 cmp r3, #2
|
|
8003242: d914 bls.n 800326e <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if(ADC_IS_ENABLE(hadc) != RESET)
|
|
8003244: 687b ldr r3, [r7, #4]
|
|
8003246: 681b ldr r3, [r3, #0]
|
|
8003248: 689b ldr r3, [r3, #8]
|
|
800324a: f003 0301 and.w r3, r3, #1
|
|
800324e: 2b01 cmp r3, #1
|
|
8003250: d10d bne.n 800326e <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8003252: 687b ldr r3, [r7, #4]
|
|
8003254: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003256: f043 0210 orr.w r2, r3, #16
|
|
800325a: 687b ldr r3, [r7, #4]
|
|
800325c: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800325e: 687b ldr r3, [r7, #4]
|
|
8003260: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003262: f043 0201 orr.w r2, r3, #1
|
|
8003266: 687b ldr r3, [r7, #4]
|
|
8003268: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_ERROR;
|
|
800326a: 2301 movs r3, #1
|
|
800326c: e007 b.n 800327e <ADC_ConversionStop_Disable+0x7a>
|
|
while(ADC_IS_ENABLE(hadc) != RESET)
|
|
800326e: 687b ldr r3, [r7, #4]
|
|
8003270: 681b ldr r3, [r3, #0]
|
|
8003272: 689b ldr r3, [r3, #8]
|
|
8003274: f003 0301 and.w r3, r3, #1
|
|
8003278: 2b01 cmp r3, #1
|
|
800327a: d0dc beq.n 8003236 <ADC_ConversionStop_Disable+0x32>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
800327c: 2300 movs r3, #0
|
|
}
|
|
800327e: 4618 mov r0, r3
|
|
8003280: 3710 adds r7, #16
|
|
8003282: 46bd mov sp, r7
|
|
8003284: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003288 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8003288: b480 push {r7}
|
|
800328a: b085 sub sp, #20
|
|
800328c: af00 add r7, sp, #0
|
|
800328e: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8003290: 687b ldr r3, [r7, #4]
|
|
8003292: f003 0307 and.w r3, r3, #7
|
|
8003296: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8003298: 4b0c ldr r3, [pc, #48] @ (80032cc <__NVIC_SetPriorityGrouping+0x44>)
|
|
800329a: 68db ldr r3, [r3, #12]
|
|
800329c: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
800329e: 68ba ldr r2, [r7, #8]
|
|
80032a0: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80032a4: 4013 ands r3, r2
|
|
80032a6: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80032a8: 68fb ldr r3, [r7, #12]
|
|
80032aa: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80032ac: 68bb ldr r3, [r7, #8]
|
|
80032ae: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80032b0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80032b4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80032b8: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80032ba: 4a04 ldr r2, [pc, #16] @ (80032cc <__NVIC_SetPriorityGrouping+0x44>)
|
|
80032bc: 68bb ldr r3, [r7, #8]
|
|
80032be: 60d3 str r3, [r2, #12]
|
|
}
|
|
80032c0: bf00 nop
|
|
80032c2: 3714 adds r7, #20
|
|
80032c4: 46bd mov sp, r7
|
|
80032c6: bc80 pop {r7}
|
|
80032c8: 4770 bx lr
|
|
80032ca: bf00 nop
|
|
80032cc: e000ed00 .word 0xe000ed00
|
|
|
|
080032d0 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80032d0: b480 push {r7}
|
|
80032d2: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80032d4: 4b04 ldr r3, [pc, #16] @ (80032e8 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80032d6: 68db ldr r3, [r3, #12]
|
|
80032d8: 0a1b lsrs r3, r3, #8
|
|
80032da: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80032de: 4618 mov r0, r3
|
|
80032e0: 46bd mov sp, r7
|
|
80032e2: bc80 pop {r7}
|
|
80032e4: 4770 bx lr
|
|
80032e6: bf00 nop
|
|
80032e8: e000ed00 .word 0xe000ed00
|
|
|
|
080032ec <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80032ec: b480 push {r7}
|
|
80032ee: b083 sub sp, #12
|
|
80032f0: af00 add r7, sp, #0
|
|
80032f2: 4603 mov r3, r0
|
|
80032f4: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80032f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80032fa: 2b00 cmp r3, #0
|
|
80032fc: db0b blt.n 8003316 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80032fe: 79fb ldrb r3, [r7, #7]
|
|
8003300: f003 021f and.w r2, r3, #31
|
|
8003304: 4906 ldr r1, [pc, #24] @ (8003320 <__NVIC_EnableIRQ+0x34>)
|
|
8003306: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800330a: 095b lsrs r3, r3, #5
|
|
800330c: 2001 movs r0, #1
|
|
800330e: fa00 f202 lsl.w r2, r0, r2
|
|
8003312: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
}
|
|
8003316: bf00 nop
|
|
8003318: 370c adds r7, #12
|
|
800331a: 46bd mov sp, r7
|
|
800331c: bc80 pop {r7}
|
|
800331e: 4770 bx lr
|
|
8003320: e000e100 .word 0xe000e100
|
|
|
|
08003324 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8003324: b480 push {r7}
|
|
8003326: b083 sub sp, #12
|
|
8003328: af00 add r7, sp, #0
|
|
800332a: 4603 mov r3, r0
|
|
800332c: 6039 str r1, [r7, #0]
|
|
800332e: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8003330: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003334: 2b00 cmp r3, #0
|
|
8003336: db0a blt.n 800334e <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8003338: 683b ldr r3, [r7, #0]
|
|
800333a: b2da uxtb r2, r3
|
|
800333c: 490c ldr r1, [pc, #48] @ (8003370 <__NVIC_SetPriority+0x4c>)
|
|
800333e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003342: 0112 lsls r2, r2, #4
|
|
8003344: b2d2 uxtb r2, r2
|
|
8003346: 440b add r3, r1
|
|
8003348: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
800334c: e00a b.n 8003364 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800334e: 683b ldr r3, [r7, #0]
|
|
8003350: b2da uxtb r2, r3
|
|
8003352: 4908 ldr r1, [pc, #32] @ (8003374 <__NVIC_SetPriority+0x50>)
|
|
8003354: 79fb ldrb r3, [r7, #7]
|
|
8003356: f003 030f and.w r3, r3, #15
|
|
800335a: 3b04 subs r3, #4
|
|
800335c: 0112 lsls r2, r2, #4
|
|
800335e: b2d2 uxtb r2, r2
|
|
8003360: 440b add r3, r1
|
|
8003362: 761a strb r2, [r3, #24]
|
|
}
|
|
8003364: bf00 nop
|
|
8003366: 370c adds r7, #12
|
|
8003368: 46bd mov sp, r7
|
|
800336a: bc80 pop {r7}
|
|
800336c: 4770 bx lr
|
|
800336e: bf00 nop
|
|
8003370: e000e100 .word 0xe000e100
|
|
8003374: e000ed00 .word 0xe000ed00
|
|
|
|
08003378 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003378: b480 push {r7}
|
|
800337a: b089 sub sp, #36 @ 0x24
|
|
800337c: af00 add r7, sp, #0
|
|
800337e: 60f8 str r0, [r7, #12]
|
|
8003380: 60b9 str r1, [r7, #8]
|
|
8003382: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8003384: 68fb ldr r3, [r7, #12]
|
|
8003386: f003 0307 and.w r3, r3, #7
|
|
800338a: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
800338c: 69fb ldr r3, [r7, #28]
|
|
800338e: f1c3 0307 rsb r3, r3, #7
|
|
8003392: 2b04 cmp r3, #4
|
|
8003394: bf28 it cs
|
|
8003396: 2304 movcs r3, #4
|
|
8003398: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
800339a: 69fb ldr r3, [r7, #28]
|
|
800339c: 3304 adds r3, #4
|
|
800339e: 2b06 cmp r3, #6
|
|
80033a0: d902 bls.n 80033a8 <NVIC_EncodePriority+0x30>
|
|
80033a2: 69fb ldr r3, [r7, #28]
|
|
80033a4: 3b03 subs r3, #3
|
|
80033a6: e000 b.n 80033aa <NVIC_EncodePriority+0x32>
|
|
80033a8: 2300 movs r3, #0
|
|
80033aa: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80033ac: f04f 32ff mov.w r2, #4294967295
|
|
80033b0: 69bb ldr r3, [r7, #24]
|
|
80033b2: fa02 f303 lsl.w r3, r2, r3
|
|
80033b6: 43da mvns r2, r3
|
|
80033b8: 68bb ldr r3, [r7, #8]
|
|
80033ba: 401a ands r2, r3
|
|
80033bc: 697b ldr r3, [r7, #20]
|
|
80033be: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80033c0: f04f 31ff mov.w r1, #4294967295
|
|
80033c4: 697b ldr r3, [r7, #20]
|
|
80033c6: fa01 f303 lsl.w r3, r1, r3
|
|
80033ca: 43d9 mvns r1, r3
|
|
80033cc: 687b ldr r3, [r7, #4]
|
|
80033ce: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80033d0: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80033d2: 4618 mov r0, r3
|
|
80033d4: 3724 adds r7, #36 @ 0x24
|
|
80033d6: 46bd mov sp, r7
|
|
80033d8: bc80 pop {r7}
|
|
80033da: 4770 bx lr
|
|
|
|
080033dc <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80033dc: b580 push {r7, lr}
|
|
80033de: b082 sub sp, #8
|
|
80033e0: af00 add r7, sp, #0
|
|
80033e2: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80033e4: 687b ldr r3, [r7, #4]
|
|
80033e6: 3b01 subs r3, #1
|
|
80033e8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80033ec: d301 bcc.n 80033f2 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80033ee: 2301 movs r3, #1
|
|
80033f0: e00f b.n 8003412 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80033f2: 4a0a ldr r2, [pc, #40] @ (800341c <SysTick_Config+0x40>)
|
|
80033f4: 687b ldr r3, [r7, #4]
|
|
80033f6: 3b01 subs r3, #1
|
|
80033f8: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
80033fa: 210f movs r1, #15
|
|
80033fc: f04f 30ff mov.w r0, #4294967295
|
|
8003400: f7ff ff90 bl 8003324 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8003404: 4b05 ldr r3, [pc, #20] @ (800341c <SysTick_Config+0x40>)
|
|
8003406: 2200 movs r2, #0
|
|
8003408: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800340a: 4b04 ldr r3, [pc, #16] @ (800341c <SysTick_Config+0x40>)
|
|
800340c: 2207 movs r2, #7
|
|
800340e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8003410: 2300 movs r3, #0
|
|
}
|
|
8003412: 4618 mov r0, r3
|
|
8003414: 3708 adds r7, #8
|
|
8003416: 46bd mov sp, r7
|
|
8003418: bd80 pop {r7, pc}
|
|
800341a: bf00 nop
|
|
800341c: e000e010 .word 0xe000e010
|
|
|
|
08003420 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8003420: b580 push {r7, lr}
|
|
8003422: b082 sub sp, #8
|
|
8003424: af00 add r7, sp, #0
|
|
8003426: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8003428: 6878 ldr r0, [r7, #4]
|
|
800342a: f7ff ff2d bl 8003288 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800342e: bf00 nop
|
|
8003430: 3708 adds r7, #8
|
|
8003432: 46bd mov sp, r7
|
|
8003434: bd80 pop {r7, pc}
|
|
|
|
08003436 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003436: b580 push {r7, lr}
|
|
8003438: b086 sub sp, #24
|
|
800343a: af00 add r7, sp, #0
|
|
800343c: 4603 mov r3, r0
|
|
800343e: 60b9 str r1, [r7, #8]
|
|
8003440: 607a str r2, [r7, #4]
|
|
8003442: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8003444: 2300 movs r3, #0
|
|
8003446: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8003448: f7ff ff42 bl 80032d0 <__NVIC_GetPriorityGrouping>
|
|
800344c: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800344e: 687a ldr r2, [r7, #4]
|
|
8003450: 68b9 ldr r1, [r7, #8]
|
|
8003452: 6978 ldr r0, [r7, #20]
|
|
8003454: f7ff ff90 bl 8003378 <NVIC_EncodePriority>
|
|
8003458: 4602 mov r2, r0
|
|
800345a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800345e: 4611 mov r1, r2
|
|
8003460: 4618 mov r0, r3
|
|
8003462: f7ff ff5f bl 8003324 <__NVIC_SetPriority>
|
|
}
|
|
8003466: bf00 nop
|
|
8003468: 3718 adds r7, #24
|
|
800346a: 46bd mov sp, r7
|
|
800346c: bd80 pop {r7, pc}
|
|
|
|
0800346e <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
800346e: b580 push {r7, lr}
|
|
8003470: b082 sub sp, #8
|
|
8003472: af00 add r7, sp, #0
|
|
8003474: 4603 mov r3, r0
|
|
8003476: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8003478: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800347c: 4618 mov r0, r3
|
|
800347e: f7ff ff35 bl 80032ec <__NVIC_EnableIRQ>
|
|
}
|
|
8003482: bf00 nop
|
|
8003484: 3708 adds r7, #8
|
|
8003486: 46bd mov sp, r7
|
|
8003488: bd80 pop {r7, pc}
|
|
|
|
0800348a <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800348a: b580 push {r7, lr}
|
|
800348c: b082 sub sp, #8
|
|
800348e: af00 add r7, sp, #0
|
|
8003490: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8003492: 6878 ldr r0, [r7, #4]
|
|
8003494: f7ff ffa2 bl 80033dc <SysTick_Config>
|
|
8003498: 4603 mov r3, r0
|
|
}
|
|
800349a: 4618 mov r0, r3
|
|
800349c: 3708 adds r7, #8
|
|
800349e: 46bd mov sp, r7
|
|
80034a0: bd80 pop {r7, pc}
|
|
|
|
080034a2 <HAL_DMA_Abort>:
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80034a2: b480 push {r7}
|
|
80034a4: b085 sub sp, #20
|
|
80034a6: af00 add r7, sp, #0
|
|
80034a8: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80034aa: 2300 movs r3, #0
|
|
80034ac: 73fb strb r3, [r7, #15]
|
|
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
80034ae: 687b ldr r3, [r7, #4]
|
|
80034b0: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
80034b4: b2db uxtb r3, r3
|
|
80034b6: 2b02 cmp r3, #2
|
|
80034b8: d008 beq.n 80034cc <HAL_DMA_Abort+0x2a>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80034ba: 687b ldr r3, [r7, #4]
|
|
80034bc: 2204 movs r2, #4
|
|
80034be: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80034c0: 687b ldr r3, [r7, #4]
|
|
80034c2: 2200 movs r2, #0
|
|
80034c4: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_ERROR;
|
|
80034c8: 2301 movs r3, #1
|
|
80034ca: e020 b.n 800350e <HAL_DMA_Abort+0x6c>
|
|
}
|
|
else
|
|
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
80034cc: 687b ldr r3, [r7, #4]
|
|
80034ce: 681b ldr r3, [r3, #0]
|
|
80034d0: 681a ldr r2, [r3, #0]
|
|
80034d2: 687b ldr r3, [r7, #4]
|
|
80034d4: 681b ldr r3, [r3, #0]
|
|
80034d6: f022 020e bic.w r2, r2, #14
|
|
80034da: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80034dc: 687b ldr r3, [r7, #4]
|
|
80034de: 681b ldr r3, [r3, #0]
|
|
80034e0: 681a ldr r2, [r3, #0]
|
|
80034e2: 687b ldr r3, [r7, #4]
|
|
80034e4: 681b ldr r3, [r3, #0]
|
|
80034e6: f022 0201 bic.w r2, r2, #1
|
|
80034ea: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
|
|
80034ec: 687b ldr r3, [r7, #4]
|
|
80034ee: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80034f0: 687b ldr r3, [r7, #4]
|
|
80034f2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80034f4: 2101 movs r1, #1
|
|
80034f6: fa01 f202 lsl.w r2, r1, r2
|
|
80034fa: 605a str r2, [r3, #4]
|
|
}
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80034fc: 687b ldr r3, [r7, #4]
|
|
80034fe: 2201 movs r2, #1
|
|
8003500: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8003504: 687b ldr r3, [r7, #4]
|
|
8003506: 2200 movs r2, #0
|
|
8003508: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return status;
|
|
800350c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800350e: 4618 mov r0, r3
|
|
8003510: 3714 adds r7, #20
|
|
8003512: 46bd mov sp, r7
|
|
8003514: bc80 pop {r7}
|
|
8003516: 4770 bx lr
|
|
|
|
08003518 <HAL_DMA_Abort_IT>:
|
|
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8003518: b580 push {r7, lr}
|
|
800351a: b084 sub sp, #16
|
|
800351c: af00 add r7, sp, #0
|
|
800351e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003520: 2300 movs r3, #0
|
|
8003522: 73fb strb r3, [r7, #15]
|
|
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
|
8003524: 687b ldr r3, [r7, #4]
|
|
8003526: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
800352a: b2db uxtb r3, r3
|
|
800352c: 2b02 cmp r3, #2
|
|
800352e: d005 beq.n 800353c <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8003530: 687b ldr r3, [r7, #4]
|
|
8003532: 2204 movs r2, #4
|
|
8003534: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
status = HAL_ERROR;
|
|
8003536: 2301 movs r3, #1
|
|
8003538: 73fb strb r3, [r7, #15]
|
|
800353a: e051 b.n 80035e0 <HAL_DMA_Abort_IT+0xc8>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800353c: 687b ldr r3, [r7, #4]
|
|
800353e: 681b ldr r3, [r3, #0]
|
|
8003540: 681a ldr r2, [r3, #0]
|
|
8003542: 687b ldr r3, [r7, #4]
|
|
8003544: 681b ldr r3, [r3, #0]
|
|
8003546: f022 020e bic.w r2, r2, #14
|
|
800354a: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800354c: 687b ldr r3, [r7, #4]
|
|
800354e: 681b ldr r3, [r3, #0]
|
|
8003550: 681a ldr r2, [r3, #0]
|
|
8003552: 687b ldr r3, [r7, #4]
|
|
8003554: 681b ldr r3, [r3, #0]
|
|
8003556: f022 0201 bic.w r2, r2, #1
|
|
800355a: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
|
|
800355c: 687b ldr r3, [r7, #4]
|
|
800355e: 681b ldr r3, [r3, #0]
|
|
8003560: 4a22 ldr r2, [pc, #136] @ (80035ec <HAL_DMA_Abort_IT+0xd4>)
|
|
8003562: 4293 cmp r3, r2
|
|
8003564: d029 beq.n 80035ba <HAL_DMA_Abort_IT+0xa2>
|
|
8003566: 687b ldr r3, [r7, #4]
|
|
8003568: 681b ldr r3, [r3, #0]
|
|
800356a: 4a21 ldr r2, [pc, #132] @ (80035f0 <HAL_DMA_Abort_IT+0xd8>)
|
|
800356c: 4293 cmp r3, r2
|
|
800356e: d022 beq.n 80035b6 <HAL_DMA_Abort_IT+0x9e>
|
|
8003570: 687b ldr r3, [r7, #4]
|
|
8003572: 681b ldr r3, [r3, #0]
|
|
8003574: 4a1f ldr r2, [pc, #124] @ (80035f4 <HAL_DMA_Abort_IT+0xdc>)
|
|
8003576: 4293 cmp r3, r2
|
|
8003578: d01a beq.n 80035b0 <HAL_DMA_Abort_IT+0x98>
|
|
800357a: 687b ldr r3, [r7, #4]
|
|
800357c: 681b ldr r3, [r3, #0]
|
|
800357e: 4a1e ldr r2, [pc, #120] @ (80035f8 <HAL_DMA_Abort_IT+0xe0>)
|
|
8003580: 4293 cmp r3, r2
|
|
8003582: d012 beq.n 80035aa <HAL_DMA_Abort_IT+0x92>
|
|
8003584: 687b ldr r3, [r7, #4]
|
|
8003586: 681b ldr r3, [r3, #0]
|
|
8003588: 4a1c ldr r2, [pc, #112] @ (80035fc <HAL_DMA_Abort_IT+0xe4>)
|
|
800358a: 4293 cmp r3, r2
|
|
800358c: d00a beq.n 80035a4 <HAL_DMA_Abort_IT+0x8c>
|
|
800358e: 687b ldr r3, [r7, #4]
|
|
8003590: 681b ldr r3, [r3, #0]
|
|
8003592: 4a1b ldr r2, [pc, #108] @ (8003600 <HAL_DMA_Abort_IT+0xe8>)
|
|
8003594: 4293 cmp r3, r2
|
|
8003596: d102 bne.n 800359e <HAL_DMA_Abort_IT+0x86>
|
|
8003598: f44f 1380 mov.w r3, #1048576 @ 0x100000
|
|
800359c: e00e b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
800359e: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
80035a2: e00b b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
80035a4: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80035a8: e008 b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
80035aa: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80035ae: e005 b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
80035b0: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80035b4: e002 b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
80035b6: 2310 movs r3, #16
|
|
80035b8: e000 b.n 80035bc <HAL_DMA_Abort_IT+0xa4>
|
|
80035ba: 2301 movs r3, #1
|
|
80035bc: 4a11 ldr r2, [pc, #68] @ (8003604 <HAL_DMA_Abort_IT+0xec>)
|
|
80035be: 6053 str r3, [r2, #4]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80035c0: 687b ldr r3, [r7, #4]
|
|
80035c2: 2201 movs r2, #1
|
|
80035c4: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80035c8: 687b ldr r3, [r7, #4]
|
|
80035ca: 2200 movs r2, #0
|
|
80035cc: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Call User Abort callback */
|
|
if(hdma->XferAbortCallback != NULL)
|
|
80035d0: 687b ldr r3, [r7, #4]
|
|
80035d2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80035d4: 2b00 cmp r3, #0
|
|
80035d6: d003 beq.n 80035e0 <HAL_DMA_Abort_IT+0xc8>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
80035d8: 687b ldr r3, [r7, #4]
|
|
80035da: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80035dc: 6878 ldr r0, [r7, #4]
|
|
80035de: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
80035e0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80035e2: 4618 mov r0, r3
|
|
80035e4: 3710 adds r7, #16
|
|
80035e6: 46bd mov sp, r7
|
|
80035e8: bd80 pop {r7, pc}
|
|
80035ea: bf00 nop
|
|
80035ec: 40020008 .word 0x40020008
|
|
80035f0: 4002001c .word 0x4002001c
|
|
80035f4: 40020030 .word 0x40020030
|
|
80035f8: 40020044 .word 0x40020044
|
|
80035fc: 40020058 .word 0x40020058
|
|
8003600: 4002006c .word 0x4002006c
|
|
8003604: 40020000 .word 0x40020000
|
|
|
|
08003608 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8003608: b480 push {r7}
|
|
800360a: b08b sub sp, #44 @ 0x2c
|
|
800360c: af00 add r7, sp, #0
|
|
800360e: 6078 str r0, [r7, #4]
|
|
8003610: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8003612: 2300 movs r3, #0
|
|
8003614: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t ioposition;
|
|
uint32_t iocurrent;
|
|
uint32_t temp;
|
|
uint32_t config = 0x00u;
|
|
8003616: 2300 movs r3, #0
|
|
8003618: 623b str r3, [r7, #32]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800361a: e169 b.n 80038f0 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = (0x01uL << position);
|
|
800361c: 2201 movs r2, #1
|
|
800361e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003620: fa02 f303 lsl.w r3, r2, r3
|
|
8003624: 61fb str r3, [r7, #28]
|
|
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8003626: 683b ldr r3, [r7, #0]
|
|
8003628: 681b ldr r3, [r3, #0]
|
|
800362a: 69fa ldr r2, [r7, #28]
|
|
800362c: 4013 ands r3, r2
|
|
800362e: 61bb str r3, [r7, #24]
|
|
|
|
if (iocurrent == ioposition)
|
|
8003630: 69ba ldr r2, [r7, #24]
|
|
8003632: 69fb ldr r3, [r7, #28]
|
|
8003634: 429a cmp r2, r3
|
|
8003636: f040 8158 bne.w 80038ea <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
switch (GPIO_Init->Mode)
|
|
800363a: 683b ldr r3, [r7, #0]
|
|
800363c: 685b ldr r3, [r3, #4]
|
|
800363e: 4a9a ldr r2, [pc, #616] @ (80038a8 <HAL_GPIO_Init+0x2a0>)
|
|
8003640: 4293 cmp r3, r2
|
|
8003642: d05e beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
8003644: 4a98 ldr r2, [pc, #608] @ (80038a8 <HAL_GPIO_Init+0x2a0>)
|
|
8003646: 4293 cmp r3, r2
|
|
8003648: d875 bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
800364a: 4a98 ldr r2, [pc, #608] @ (80038ac <HAL_GPIO_Init+0x2a4>)
|
|
800364c: 4293 cmp r3, r2
|
|
800364e: d058 beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
8003650: 4a96 ldr r2, [pc, #600] @ (80038ac <HAL_GPIO_Init+0x2a4>)
|
|
8003652: 4293 cmp r3, r2
|
|
8003654: d86f bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
8003656: 4a96 ldr r2, [pc, #600] @ (80038b0 <HAL_GPIO_Init+0x2a8>)
|
|
8003658: 4293 cmp r3, r2
|
|
800365a: d052 beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
800365c: 4a94 ldr r2, [pc, #592] @ (80038b0 <HAL_GPIO_Init+0x2a8>)
|
|
800365e: 4293 cmp r3, r2
|
|
8003660: d869 bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
8003662: 4a94 ldr r2, [pc, #592] @ (80038b4 <HAL_GPIO_Init+0x2ac>)
|
|
8003664: 4293 cmp r3, r2
|
|
8003666: d04c beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
8003668: 4a92 ldr r2, [pc, #584] @ (80038b4 <HAL_GPIO_Init+0x2ac>)
|
|
800366a: 4293 cmp r3, r2
|
|
800366c: d863 bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
800366e: 4a92 ldr r2, [pc, #584] @ (80038b8 <HAL_GPIO_Init+0x2b0>)
|
|
8003670: 4293 cmp r3, r2
|
|
8003672: d046 beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
8003674: 4a90 ldr r2, [pc, #576] @ (80038b8 <HAL_GPIO_Init+0x2b0>)
|
|
8003676: 4293 cmp r3, r2
|
|
8003678: d85d bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
800367a: 2b12 cmp r3, #18
|
|
800367c: d82a bhi.n 80036d4 <HAL_GPIO_Init+0xcc>
|
|
800367e: 2b12 cmp r3, #18
|
|
8003680: d859 bhi.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
8003682: a201 add r2, pc, #4 @ (adr r2, 8003688 <HAL_GPIO_Init+0x80>)
|
|
8003684: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003688: 08003703 .word 0x08003703
|
|
800368c: 080036dd .word 0x080036dd
|
|
8003690: 080036ef .word 0x080036ef
|
|
8003694: 08003731 .word 0x08003731
|
|
8003698: 08003737 .word 0x08003737
|
|
800369c: 08003737 .word 0x08003737
|
|
80036a0: 08003737 .word 0x08003737
|
|
80036a4: 08003737 .word 0x08003737
|
|
80036a8: 08003737 .word 0x08003737
|
|
80036ac: 08003737 .word 0x08003737
|
|
80036b0: 08003737 .word 0x08003737
|
|
80036b4: 08003737 .word 0x08003737
|
|
80036b8: 08003737 .word 0x08003737
|
|
80036bc: 08003737 .word 0x08003737
|
|
80036c0: 08003737 .word 0x08003737
|
|
80036c4: 08003737 .word 0x08003737
|
|
80036c8: 08003737 .word 0x08003737
|
|
80036cc: 080036e5 .word 0x080036e5
|
|
80036d0: 080036f9 .word 0x080036f9
|
|
80036d4: 4a79 ldr r2, [pc, #484] @ (80038bc <HAL_GPIO_Init+0x2b4>)
|
|
80036d6: 4293 cmp r3, r2
|
|
80036d8: d013 beq.n 8003702 <HAL_GPIO_Init+0xfa>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
break;
|
|
|
|
/* Parameters are checked with assert_param */
|
|
default:
|
|
break;
|
|
80036da: e02c b.n 8003736 <HAL_GPIO_Init+0x12e>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
80036dc: 683b ldr r3, [r7, #0]
|
|
80036de: 68db ldr r3, [r3, #12]
|
|
80036e0: 623b str r3, [r7, #32]
|
|
break;
|
|
80036e2: e029 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
80036e4: 683b ldr r3, [r7, #0]
|
|
80036e6: 68db ldr r3, [r3, #12]
|
|
80036e8: 3304 adds r3, #4
|
|
80036ea: 623b str r3, [r7, #32]
|
|
break;
|
|
80036ec: e024 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
80036ee: 683b ldr r3, [r7, #0]
|
|
80036f0: 68db ldr r3, [r3, #12]
|
|
80036f2: 3308 adds r3, #8
|
|
80036f4: 623b str r3, [r7, #32]
|
|
break;
|
|
80036f6: e01f b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
80036f8: 683b ldr r3, [r7, #0]
|
|
80036fa: 68db ldr r3, [r3, #12]
|
|
80036fc: 330c adds r3, #12
|
|
80036fe: 623b str r3, [r7, #32]
|
|
break;
|
|
8003700: e01a b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
8003702: 683b ldr r3, [r7, #0]
|
|
8003704: 689b ldr r3, [r3, #8]
|
|
8003706: 2b00 cmp r3, #0
|
|
8003708: d102 bne.n 8003710 <HAL_GPIO_Init+0x108>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
800370a: 2304 movs r3, #4
|
|
800370c: 623b str r3, [r7, #32]
|
|
break;
|
|
800370e: e013 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
8003710: 683b ldr r3, [r7, #0]
|
|
8003712: 689b ldr r3, [r3, #8]
|
|
8003714: 2b01 cmp r3, #1
|
|
8003716: d105 bne.n 8003724 <HAL_GPIO_Init+0x11c>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8003718: 2308 movs r3, #8
|
|
800371a: 623b str r3, [r7, #32]
|
|
GPIOx->BSRR = ioposition;
|
|
800371c: 687b ldr r3, [r7, #4]
|
|
800371e: 69fa ldr r2, [r7, #28]
|
|
8003720: 611a str r2, [r3, #16]
|
|
break;
|
|
8003722: e009 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8003724: 2308 movs r3, #8
|
|
8003726: 623b str r3, [r7, #32]
|
|
GPIOx->BRR = ioposition;
|
|
8003728: 687b ldr r3, [r7, #4]
|
|
800372a: 69fa ldr r2, [r7, #28]
|
|
800372c: 615a str r2, [r3, #20]
|
|
break;
|
|
800372e: e003 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
8003730: 2300 movs r3, #0
|
|
8003732: 623b str r3, [r7, #32]
|
|
break;
|
|
8003734: e000 b.n 8003738 <HAL_GPIO_Init+0x130>
|
|
break;
|
|
8003736: bf00 nop
|
|
}
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
in order to address CRH or CRL register*/
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
8003738: 69bb ldr r3, [r7, #24]
|
|
800373a: 2bff cmp r3, #255 @ 0xff
|
|
800373c: d801 bhi.n 8003742 <HAL_GPIO_Init+0x13a>
|
|
800373e: 687b ldr r3, [r7, #4]
|
|
8003740: e001 b.n 8003746 <HAL_GPIO_Init+0x13e>
|
|
8003742: 687b ldr r3, [r7, #4]
|
|
8003744: 3304 adds r3, #4
|
|
8003746: 617b str r3, [r7, #20]
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
8003748: 69bb ldr r3, [r7, #24]
|
|
800374a: 2bff cmp r3, #255 @ 0xff
|
|
800374c: d802 bhi.n 8003754 <HAL_GPIO_Init+0x14c>
|
|
800374e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003750: 009b lsls r3, r3, #2
|
|
8003752: e002 b.n 800375a <HAL_GPIO_Init+0x152>
|
|
8003754: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003756: 3b08 subs r3, #8
|
|
8003758: 009b lsls r3, r3, #2
|
|
800375a: 613b str r3, [r7, #16]
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
800375c: 697b ldr r3, [r7, #20]
|
|
800375e: 681a ldr r2, [r3, #0]
|
|
8003760: 210f movs r1, #15
|
|
8003762: 693b ldr r3, [r7, #16]
|
|
8003764: fa01 f303 lsl.w r3, r1, r3
|
|
8003768: 43db mvns r3, r3
|
|
800376a: 401a ands r2, r3
|
|
800376c: 6a39 ldr r1, [r7, #32]
|
|
800376e: 693b ldr r3, [r7, #16]
|
|
8003770: fa01 f303 lsl.w r3, r1, r3
|
|
8003774: 431a orrs r2, r3
|
|
8003776: 697b ldr r3, [r7, #20]
|
|
8003778: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
800377a: 683b ldr r3, [r7, #0]
|
|
800377c: 685b ldr r3, [r3, #4]
|
|
800377e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003782: 2b00 cmp r3, #0
|
|
8003784: f000 80b1 beq.w 80038ea <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable AFIO Clock */
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8003788: 4b4d ldr r3, [pc, #308] @ (80038c0 <HAL_GPIO_Init+0x2b8>)
|
|
800378a: 699b ldr r3, [r3, #24]
|
|
800378c: 4a4c ldr r2, [pc, #304] @ (80038c0 <HAL_GPIO_Init+0x2b8>)
|
|
800378e: f043 0301 orr.w r3, r3, #1
|
|
8003792: 6193 str r3, [r2, #24]
|
|
8003794: 4b4a ldr r3, [pc, #296] @ (80038c0 <HAL_GPIO_Init+0x2b8>)
|
|
8003796: 699b ldr r3, [r3, #24]
|
|
8003798: f003 0301 and.w r3, r3, #1
|
|
800379c: 60bb str r3, [r7, #8]
|
|
800379e: 68bb ldr r3, [r7, #8]
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
80037a0: 4a48 ldr r2, [pc, #288] @ (80038c4 <HAL_GPIO_Init+0x2bc>)
|
|
80037a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80037a4: 089b lsrs r3, r3, #2
|
|
80037a6: 3302 adds r3, #2
|
|
80037a8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80037ac: 60fb str r3, [r7, #12]
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
80037ae: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80037b0: f003 0303 and.w r3, r3, #3
|
|
80037b4: 009b lsls r3, r3, #2
|
|
80037b6: 220f movs r2, #15
|
|
80037b8: fa02 f303 lsl.w r3, r2, r3
|
|
80037bc: 43db mvns r3, r3
|
|
80037be: 68fa ldr r2, [r7, #12]
|
|
80037c0: 4013 ands r3, r2
|
|
80037c2: 60fb str r3, [r7, #12]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
80037c4: 687b ldr r3, [r7, #4]
|
|
80037c6: 4a40 ldr r2, [pc, #256] @ (80038c8 <HAL_GPIO_Init+0x2c0>)
|
|
80037c8: 4293 cmp r3, r2
|
|
80037ca: d013 beq.n 80037f4 <HAL_GPIO_Init+0x1ec>
|
|
80037cc: 687b ldr r3, [r7, #4]
|
|
80037ce: 4a3f ldr r2, [pc, #252] @ (80038cc <HAL_GPIO_Init+0x2c4>)
|
|
80037d0: 4293 cmp r3, r2
|
|
80037d2: d00d beq.n 80037f0 <HAL_GPIO_Init+0x1e8>
|
|
80037d4: 687b ldr r3, [r7, #4]
|
|
80037d6: 4a3e ldr r2, [pc, #248] @ (80038d0 <HAL_GPIO_Init+0x2c8>)
|
|
80037d8: 4293 cmp r3, r2
|
|
80037da: d007 beq.n 80037ec <HAL_GPIO_Init+0x1e4>
|
|
80037dc: 687b ldr r3, [r7, #4]
|
|
80037de: 4a3d ldr r2, [pc, #244] @ (80038d4 <HAL_GPIO_Init+0x2cc>)
|
|
80037e0: 4293 cmp r3, r2
|
|
80037e2: d101 bne.n 80037e8 <HAL_GPIO_Init+0x1e0>
|
|
80037e4: 2303 movs r3, #3
|
|
80037e6: e006 b.n 80037f6 <HAL_GPIO_Init+0x1ee>
|
|
80037e8: 2304 movs r3, #4
|
|
80037ea: e004 b.n 80037f6 <HAL_GPIO_Init+0x1ee>
|
|
80037ec: 2302 movs r3, #2
|
|
80037ee: e002 b.n 80037f6 <HAL_GPIO_Init+0x1ee>
|
|
80037f0: 2301 movs r3, #1
|
|
80037f2: e000 b.n 80037f6 <HAL_GPIO_Init+0x1ee>
|
|
80037f4: 2300 movs r3, #0
|
|
80037f6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80037f8: f002 0203 and.w r2, r2, #3
|
|
80037fc: 0092 lsls r2, r2, #2
|
|
80037fe: 4093 lsls r3, r2
|
|
8003800: 68fa ldr r2, [r7, #12]
|
|
8003802: 4313 orrs r3, r2
|
|
8003804: 60fb str r3, [r7, #12]
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
8003806: 492f ldr r1, [pc, #188] @ (80038c4 <HAL_GPIO_Init+0x2bc>)
|
|
8003808: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800380a: 089b lsrs r3, r3, #2
|
|
800380c: 3302 adds r3, #2
|
|
800380e: 68fa ldr r2, [r7, #12]
|
|
8003810: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Enable or disable the rising trigger */
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8003814: 683b ldr r3, [r7, #0]
|
|
8003816: 685b ldr r3, [r3, #4]
|
|
8003818: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800381c: 2b00 cmp r3, #0
|
|
800381e: d006 beq.n 800382e <HAL_GPIO_Init+0x226>
|
|
{
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
8003820: 4b2d ldr r3, [pc, #180] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003822: 689a ldr r2, [r3, #8]
|
|
8003824: 492c ldr r1, [pc, #176] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003826: 69bb ldr r3, [r7, #24]
|
|
8003828: 4313 orrs r3, r2
|
|
800382a: 608b str r3, [r1, #8]
|
|
800382c: e006 b.n 800383c <HAL_GPIO_Init+0x234>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
800382e: 4b2a ldr r3, [pc, #168] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003830: 689a ldr r2, [r3, #8]
|
|
8003832: 69bb ldr r3, [r7, #24]
|
|
8003834: 43db mvns r3, r3
|
|
8003836: 4928 ldr r1, [pc, #160] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003838: 4013 ands r3, r2
|
|
800383a: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Enable or disable the falling trigger */
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
800383c: 683b ldr r3, [r7, #0]
|
|
800383e: 685b ldr r3, [r3, #4]
|
|
8003840: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8003844: 2b00 cmp r3, #0
|
|
8003846: d006 beq.n 8003856 <HAL_GPIO_Init+0x24e>
|
|
{
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
8003848: 4b23 ldr r3, [pc, #140] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
800384a: 68da ldr r2, [r3, #12]
|
|
800384c: 4922 ldr r1, [pc, #136] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
800384e: 69bb ldr r3, [r7, #24]
|
|
8003850: 4313 orrs r3, r2
|
|
8003852: 60cb str r3, [r1, #12]
|
|
8003854: e006 b.n 8003864 <HAL_GPIO_Init+0x25c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
8003856: 4b20 ldr r3, [pc, #128] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003858: 68da ldr r2, [r3, #12]
|
|
800385a: 69bb ldr r3, [r7, #24]
|
|
800385c: 43db mvns r3, r3
|
|
800385e: 491e ldr r1, [pc, #120] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003860: 4013 ands r3, r2
|
|
8003862: 60cb str r3, [r1, #12]
|
|
}
|
|
|
|
/* Configure the event mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8003864: 683b ldr r3, [r7, #0]
|
|
8003866: 685b ldr r3, [r3, #4]
|
|
8003868: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800386c: 2b00 cmp r3, #0
|
|
800386e: d006 beq.n 800387e <HAL_GPIO_Init+0x276>
|
|
{
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
8003870: 4b19 ldr r3, [pc, #100] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003872: 685a ldr r2, [r3, #4]
|
|
8003874: 4918 ldr r1, [pc, #96] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003876: 69bb ldr r3, [r7, #24]
|
|
8003878: 4313 orrs r3, r2
|
|
800387a: 604b str r3, [r1, #4]
|
|
800387c: e006 b.n 800388c <HAL_GPIO_Init+0x284>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
800387e: 4b16 ldr r3, [pc, #88] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003880: 685a ldr r2, [r3, #4]
|
|
8003882: 69bb ldr r3, [r7, #24]
|
|
8003884: 43db mvns r3, r3
|
|
8003886: 4914 ldr r1, [pc, #80] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
8003888: 4013 ands r3, r2
|
|
800388a: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the interrupt mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
800388c: 683b ldr r3, [r7, #0]
|
|
800388e: 685b ldr r3, [r3, #4]
|
|
8003890: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003894: 2b00 cmp r3, #0
|
|
8003896: d021 beq.n 80038dc <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
8003898: 4b0f ldr r3, [pc, #60] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
800389a: 681a ldr r2, [r3, #0]
|
|
800389c: 490e ldr r1, [pc, #56] @ (80038d8 <HAL_GPIO_Init+0x2d0>)
|
|
800389e: 69bb ldr r3, [r7, #24]
|
|
80038a0: 4313 orrs r3, r2
|
|
80038a2: 600b str r3, [r1, #0]
|
|
80038a4: e021 b.n 80038ea <HAL_GPIO_Init+0x2e2>
|
|
80038a6: bf00 nop
|
|
80038a8: 10320000 .word 0x10320000
|
|
80038ac: 10310000 .word 0x10310000
|
|
80038b0: 10220000 .word 0x10220000
|
|
80038b4: 10210000 .word 0x10210000
|
|
80038b8: 10120000 .word 0x10120000
|
|
80038bc: 10110000 .word 0x10110000
|
|
80038c0: 40021000 .word 0x40021000
|
|
80038c4: 40010000 .word 0x40010000
|
|
80038c8: 40010800 .word 0x40010800
|
|
80038cc: 40010c00 .word 0x40010c00
|
|
80038d0: 40011000 .word 0x40011000
|
|
80038d4: 40011400 .word 0x40011400
|
|
80038d8: 40010400 .word 0x40010400
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
80038dc: 4b0b ldr r3, [pc, #44] @ (800390c <HAL_GPIO_Init+0x304>)
|
|
80038de: 681a ldr r2, [r3, #0]
|
|
80038e0: 69bb ldr r3, [r7, #24]
|
|
80038e2: 43db mvns r3, r3
|
|
80038e4: 4909 ldr r1, [pc, #36] @ (800390c <HAL_GPIO_Init+0x304>)
|
|
80038e6: 4013 ands r3, r2
|
|
80038e8: 600b str r3, [r1, #0]
|
|
}
|
|
}
|
|
}
|
|
|
|
position++;
|
|
80038ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80038ec: 3301 adds r3, #1
|
|
80038ee: 627b str r3, [r7, #36] @ 0x24
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80038f0: 683b ldr r3, [r7, #0]
|
|
80038f2: 681a ldr r2, [r3, #0]
|
|
80038f4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80038f6: fa22 f303 lsr.w r3, r2, r3
|
|
80038fa: 2b00 cmp r3, #0
|
|
80038fc: f47f ae8e bne.w 800361c <HAL_GPIO_Init+0x14>
|
|
}
|
|
}
|
|
8003900: bf00 nop
|
|
8003902: bf00 nop
|
|
8003904: 372c adds r7, #44 @ 0x2c
|
|
8003906: 46bd mov sp, r7
|
|
8003908: bc80 pop {r7}
|
|
800390a: 4770 bx lr
|
|
800390c: 40010400 .word 0x40010400
|
|
|
|
08003910 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin: specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8003910: b480 push {r7}
|
|
8003912: b085 sub sp, #20
|
|
8003914: af00 add r7, sp, #0
|
|
8003916: 6078 str r0, [r7, #4]
|
|
8003918: 460b mov r3, r1
|
|
800391a: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
800391c: 687b ldr r3, [r7, #4]
|
|
800391e: 689a ldr r2, [r3, #8]
|
|
8003920: 887b ldrh r3, [r7, #2]
|
|
8003922: 4013 ands r3, r2
|
|
8003924: 2b00 cmp r3, #0
|
|
8003926: d002 beq.n 800392e <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8003928: 2301 movs r3, #1
|
|
800392a: 73fb strb r3, [r7, #15]
|
|
800392c: e001 b.n 8003932 <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
800392e: 2300 movs r3, #0
|
|
8003930: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
8003932: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8003934: 4618 mov r0, r3
|
|
8003936: 3714 adds r7, #20
|
|
8003938: 46bd mov sp, r7
|
|
800393a: bc80 pop {r7}
|
|
800393c: 4770 bx lr
|
|
|
|
0800393e <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
800393e: b480 push {r7}
|
|
8003940: b083 sub sp, #12
|
|
8003942: af00 add r7, sp, #0
|
|
8003944: 6078 str r0, [r7, #4]
|
|
8003946: 460b mov r3, r1
|
|
8003948: 807b strh r3, [r7, #2]
|
|
800394a: 4613 mov r3, r2
|
|
800394c: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
800394e: 787b ldrb r3, [r7, #1]
|
|
8003950: 2b00 cmp r3, #0
|
|
8003952: d003 beq.n 800395c <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8003954: 887a ldrh r2, [r7, #2]
|
|
8003956: 687b ldr r3, [r7, #4]
|
|
8003958: 611a str r2, [r3, #16]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
}
|
|
}
|
|
800395a: e003 b.n 8003964 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
800395c: 887b ldrh r3, [r7, #2]
|
|
800395e: 041a lsls r2, r3, #16
|
|
8003960: 687b ldr r3, [r7, #4]
|
|
8003962: 611a str r2, [r3, #16]
|
|
}
|
|
8003964: bf00 nop
|
|
8003966: 370c adds r7, #12
|
|
8003968: 46bd mov sp, r7
|
|
800396a: bc80 pop {r7}
|
|
800396c: 4770 bx lr
|
|
|
|
0800396e <HAL_GPIO_TogglePin>:
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
|
* @param GPIO_Pin: Specifies the pins to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
800396e: b480 push {r7}
|
|
8003970: b085 sub sp, #20
|
|
8003972: af00 add r7, sp, #0
|
|
8003974: 6078 str r0, [r7, #4]
|
|
8003976: 460b mov r3, r1
|
|
8003978: 807b strh r3, [r7, #2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Output Data Register value */
|
|
odr = GPIOx->ODR;
|
|
800397a: 687b ldr r3, [r7, #4]
|
|
800397c: 68db ldr r3, [r3, #12]
|
|
800397e: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
8003980: 887a ldrh r2, [r7, #2]
|
|
8003982: 68fb ldr r3, [r7, #12]
|
|
8003984: 4013 ands r3, r2
|
|
8003986: 041a lsls r2, r3, #16
|
|
8003988: 68fb ldr r3, [r7, #12]
|
|
800398a: 43d9 mvns r1, r3
|
|
800398c: 887b ldrh r3, [r7, #2]
|
|
800398e: 400b ands r3, r1
|
|
8003990: 431a orrs r2, r3
|
|
8003992: 687b ldr r3, [r7, #4]
|
|
8003994: 611a str r2, [r3, #16]
|
|
}
|
|
8003996: bf00 nop
|
|
8003998: 3714 adds r7, #20
|
|
800399a: 46bd mov sp, r7
|
|
800399c: bc80 pop {r7}
|
|
800399e: 4770 bx lr
|
|
|
|
080039a0 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80039a0: b580 push {r7, lr}
|
|
80039a2: b084 sub sp, #16
|
|
80039a4: af00 add r7, sp, #0
|
|
80039a6: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
80039a8: 687b ldr r3, [r7, #4]
|
|
80039aa: 2b00 cmp r3, #0
|
|
80039ac: d101 bne.n 80039b2 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80039ae: 2301 movs r3, #1
|
|
80039b0: e12b b.n 8003c0a <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
80039b2: 687b ldr r3, [r7, #4]
|
|
80039b4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80039b8: b2db uxtb r3, r3
|
|
80039ba: 2b00 cmp r3, #0
|
|
80039bc: d106 bne.n 80039cc <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
80039be: 687b ldr r3, [r7, #4]
|
|
80039c0: 2200 movs r2, #0
|
|
80039c2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
80039c6: 6878 ldr r0, [r7, #4]
|
|
80039c8: f7fe fb58 bl 800207c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80039cc: 687b ldr r3, [r7, #4]
|
|
80039ce: 2224 movs r2, #36 @ 0x24
|
|
80039d0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80039d4: 687b ldr r3, [r7, #4]
|
|
80039d6: 681b ldr r3, [r3, #0]
|
|
80039d8: 681a ldr r2, [r3, #0]
|
|
80039da: 687b ldr r3, [r7, #4]
|
|
80039dc: 681b ldr r3, [r3, #0]
|
|
80039de: f022 0201 bic.w r2, r2, #1
|
|
80039e2: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
80039e4: 687b ldr r3, [r7, #4]
|
|
80039e6: 681b ldr r3, [r3, #0]
|
|
80039e8: 681a ldr r2, [r3, #0]
|
|
80039ea: 687b ldr r3, [r7, #4]
|
|
80039ec: 681b ldr r3, [r3, #0]
|
|
80039ee: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
80039f2: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
80039f4: 687b ldr r3, [r7, #4]
|
|
80039f6: 681b ldr r3, [r3, #0]
|
|
80039f8: 681a ldr r2, [r3, #0]
|
|
80039fa: 687b ldr r3, [r7, #4]
|
|
80039fc: 681b ldr r3, [r3, #0]
|
|
80039fe: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8003a02: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8003a04: f001 fbcc bl 80051a0 <HAL_RCC_GetPCLK1Freq>
|
|
8003a08: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8003a0a: 687b ldr r3, [r7, #4]
|
|
8003a0c: 685b ldr r3, [r3, #4]
|
|
8003a0e: 4a81 ldr r2, [pc, #516] @ (8003c14 <HAL_I2C_Init+0x274>)
|
|
8003a10: 4293 cmp r3, r2
|
|
8003a12: d807 bhi.n 8003a24 <HAL_I2C_Init+0x84>
|
|
8003a14: 68fb ldr r3, [r7, #12]
|
|
8003a16: 4a80 ldr r2, [pc, #512] @ (8003c18 <HAL_I2C_Init+0x278>)
|
|
8003a18: 4293 cmp r3, r2
|
|
8003a1a: bf94 ite ls
|
|
8003a1c: 2301 movls r3, #1
|
|
8003a1e: 2300 movhi r3, #0
|
|
8003a20: b2db uxtb r3, r3
|
|
8003a22: e006 b.n 8003a32 <HAL_I2C_Init+0x92>
|
|
8003a24: 68fb ldr r3, [r7, #12]
|
|
8003a26: 4a7d ldr r2, [pc, #500] @ (8003c1c <HAL_I2C_Init+0x27c>)
|
|
8003a28: 4293 cmp r3, r2
|
|
8003a2a: bf94 ite ls
|
|
8003a2c: 2301 movls r3, #1
|
|
8003a2e: 2300 movhi r3, #0
|
|
8003a30: b2db uxtb r3, r3
|
|
8003a32: 2b00 cmp r3, #0
|
|
8003a34: d001 beq.n 8003a3a <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a36: 2301 movs r3, #1
|
|
8003a38: e0e7 b.n 8003c0a <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
8003a3a: 68fb ldr r3, [r7, #12]
|
|
8003a3c: 4a78 ldr r2, [pc, #480] @ (8003c20 <HAL_I2C_Init+0x280>)
|
|
8003a3e: fba2 2303 umull r2, r3, r2, r3
|
|
8003a42: 0c9b lsrs r3, r3, #18
|
|
8003a44: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8003a46: 687b ldr r3, [r7, #4]
|
|
8003a48: 681b ldr r3, [r3, #0]
|
|
8003a4a: 685b ldr r3, [r3, #4]
|
|
8003a4c: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8003a50: 687b ldr r3, [r7, #4]
|
|
8003a52: 681b ldr r3, [r3, #0]
|
|
8003a54: 68ba ldr r2, [r7, #8]
|
|
8003a56: 430a orrs r2, r1
|
|
8003a58: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
8003a5a: 687b ldr r3, [r7, #4]
|
|
8003a5c: 681b ldr r3, [r3, #0]
|
|
8003a5e: 6a1b ldr r3, [r3, #32]
|
|
8003a60: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8003a64: 687b ldr r3, [r7, #4]
|
|
8003a66: 685b ldr r3, [r3, #4]
|
|
8003a68: 4a6a ldr r2, [pc, #424] @ (8003c14 <HAL_I2C_Init+0x274>)
|
|
8003a6a: 4293 cmp r3, r2
|
|
8003a6c: d802 bhi.n 8003a74 <HAL_I2C_Init+0xd4>
|
|
8003a6e: 68bb ldr r3, [r7, #8]
|
|
8003a70: 3301 adds r3, #1
|
|
8003a72: e009 b.n 8003a88 <HAL_I2C_Init+0xe8>
|
|
8003a74: 68bb ldr r3, [r7, #8]
|
|
8003a76: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8003a7a: fb02 f303 mul.w r3, r2, r3
|
|
8003a7e: 4a69 ldr r2, [pc, #420] @ (8003c24 <HAL_I2C_Init+0x284>)
|
|
8003a80: fba2 2303 umull r2, r3, r2, r3
|
|
8003a84: 099b lsrs r3, r3, #6
|
|
8003a86: 3301 adds r3, #1
|
|
8003a88: 687a ldr r2, [r7, #4]
|
|
8003a8a: 6812 ldr r2, [r2, #0]
|
|
8003a8c: 430b orrs r3, r1
|
|
8003a8e: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8003a90: 687b ldr r3, [r7, #4]
|
|
8003a92: 681b ldr r3, [r3, #0]
|
|
8003a94: 69db ldr r3, [r3, #28]
|
|
8003a96: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8003a9a: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8003a9e: 687b ldr r3, [r7, #4]
|
|
8003aa0: 685b ldr r3, [r3, #4]
|
|
8003aa2: 495c ldr r1, [pc, #368] @ (8003c14 <HAL_I2C_Init+0x274>)
|
|
8003aa4: 428b cmp r3, r1
|
|
8003aa6: d819 bhi.n 8003adc <HAL_I2C_Init+0x13c>
|
|
8003aa8: 68fb ldr r3, [r7, #12]
|
|
8003aaa: 1e59 subs r1, r3, #1
|
|
8003aac: 687b ldr r3, [r7, #4]
|
|
8003aae: 685b ldr r3, [r3, #4]
|
|
8003ab0: 005b lsls r3, r3, #1
|
|
8003ab2: fbb1 f3f3 udiv r3, r1, r3
|
|
8003ab6: 1c59 adds r1, r3, #1
|
|
8003ab8: f640 73fc movw r3, #4092 @ 0xffc
|
|
8003abc: 400b ands r3, r1
|
|
8003abe: 2b00 cmp r3, #0
|
|
8003ac0: d00a beq.n 8003ad8 <HAL_I2C_Init+0x138>
|
|
8003ac2: 68fb ldr r3, [r7, #12]
|
|
8003ac4: 1e59 subs r1, r3, #1
|
|
8003ac6: 687b ldr r3, [r7, #4]
|
|
8003ac8: 685b ldr r3, [r3, #4]
|
|
8003aca: 005b lsls r3, r3, #1
|
|
8003acc: fbb1 f3f3 udiv r3, r1, r3
|
|
8003ad0: 3301 adds r3, #1
|
|
8003ad2: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003ad6: e051 b.n 8003b7c <HAL_I2C_Init+0x1dc>
|
|
8003ad8: 2304 movs r3, #4
|
|
8003ada: e04f b.n 8003b7c <HAL_I2C_Init+0x1dc>
|
|
8003adc: 687b ldr r3, [r7, #4]
|
|
8003ade: 689b ldr r3, [r3, #8]
|
|
8003ae0: 2b00 cmp r3, #0
|
|
8003ae2: d111 bne.n 8003b08 <HAL_I2C_Init+0x168>
|
|
8003ae4: 68fb ldr r3, [r7, #12]
|
|
8003ae6: 1e58 subs r0, r3, #1
|
|
8003ae8: 687b ldr r3, [r7, #4]
|
|
8003aea: 6859 ldr r1, [r3, #4]
|
|
8003aec: 460b mov r3, r1
|
|
8003aee: 005b lsls r3, r3, #1
|
|
8003af0: 440b add r3, r1
|
|
8003af2: fbb0 f3f3 udiv r3, r0, r3
|
|
8003af6: 3301 adds r3, #1
|
|
8003af8: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003afc: 2b00 cmp r3, #0
|
|
8003afe: bf0c ite eq
|
|
8003b00: 2301 moveq r3, #1
|
|
8003b02: 2300 movne r3, #0
|
|
8003b04: b2db uxtb r3, r3
|
|
8003b06: e012 b.n 8003b2e <HAL_I2C_Init+0x18e>
|
|
8003b08: 68fb ldr r3, [r7, #12]
|
|
8003b0a: 1e58 subs r0, r3, #1
|
|
8003b0c: 687b ldr r3, [r7, #4]
|
|
8003b0e: 6859 ldr r1, [r3, #4]
|
|
8003b10: 460b mov r3, r1
|
|
8003b12: 009b lsls r3, r3, #2
|
|
8003b14: 440b add r3, r1
|
|
8003b16: 0099 lsls r1, r3, #2
|
|
8003b18: 440b add r3, r1
|
|
8003b1a: fbb0 f3f3 udiv r3, r0, r3
|
|
8003b1e: 3301 adds r3, #1
|
|
8003b20: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003b24: 2b00 cmp r3, #0
|
|
8003b26: bf0c ite eq
|
|
8003b28: 2301 moveq r3, #1
|
|
8003b2a: 2300 movne r3, #0
|
|
8003b2c: b2db uxtb r3, r3
|
|
8003b2e: 2b00 cmp r3, #0
|
|
8003b30: d001 beq.n 8003b36 <HAL_I2C_Init+0x196>
|
|
8003b32: 2301 movs r3, #1
|
|
8003b34: e022 b.n 8003b7c <HAL_I2C_Init+0x1dc>
|
|
8003b36: 687b ldr r3, [r7, #4]
|
|
8003b38: 689b ldr r3, [r3, #8]
|
|
8003b3a: 2b00 cmp r3, #0
|
|
8003b3c: d10e bne.n 8003b5c <HAL_I2C_Init+0x1bc>
|
|
8003b3e: 68fb ldr r3, [r7, #12]
|
|
8003b40: 1e58 subs r0, r3, #1
|
|
8003b42: 687b ldr r3, [r7, #4]
|
|
8003b44: 6859 ldr r1, [r3, #4]
|
|
8003b46: 460b mov r3, r1
|
|
8003b48: 005b lsls r3, r3, #1
|
|
8003b4a: 440b add r3, r1
|
|
8003b4c: fbb0 f3f3 udiv r3, r0, r3
|
|
8003b50: 3301 adds r3, #1
|
|
8003b52: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003b56: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003b5a: e00f b.n 8003b7c <HAL_I2C_Init+0x1dc>
|
|
8003b5c: 68fb ldr r3, [r7, #12]
|
|
8003b5e: 1e58 subs r0, r3, #1
|
|
8003b60: 687b ldr r3, [r7, #4]
|
|
8003b62: 6859 ldr r1, [r3, #4]
|
|
8003b64: 460b mov r3, r1
|
|
8003b66: 009b lsls r3, r3, #2
|
|
8003b68: 440b add r3, r1
|
|
8003b6a: 0099 lsls r1, r3, #2
|
|
8003b6c: 440b add r3, r1
|
|
8003b6e: fbb0 f3f3 udiv r3, r0, r3
|
|
8003b72: 3301 adds r3, #1
|
|
8003b74: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003b78: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8003b7c: 6879 ldr r1, [r7, #4]
|
|
8003b7e: 6809 ldr r1, [r1, #0]
|
|
8003b80: 4313 orrs r3, r2
|
|
8003b82: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8003b84: 687b ldr r3, [r7, #4]
|
|
8003b86: 681b ldr r3, [r3, #0]
|
|
8003b88: 681b ldr r3, [r3, #0]
|
|
8003b8a: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8003b8e: 687b ldr r3, [r7, #4]
|
|
8003b90: 69da ldr r2, [r3, #28]
|
|
8003b92: 687b ldr r3, [r7, #4]
|
|
8003b94: 6a1b ldr r3, [r3, #32]
|
|
8003b96: 431a orrs r2, r3
|
|
8003b98: 687b ldr r3, [r7, #4]
|
|
8003b9a: 681b ldr r3, [r3, #0]
|
|
8003b9c: 430a orrs r2, r1
|
|
8003b9e: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8003ba0: 687b ldr r3, [r7, #4]
|
|
8003ba2: 681b ldr r3, [r3, #0]
|
|
8003ba4: 689b ldr r3, [r3, #8]
|
|
8003ba6: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8003baa: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8003bae: 687a ldr r2, [r7, #4]
|
|
8003bb0: 6911 ldr r1, [r2, #16]
|
|
8003bb2: 687a ldr r2, [r7, #4]
|
|
8003bb4: 68d2 ldr r2, [r2, #12]
|
|
8003bb6: 4311 orrs r1, r2
|
|
8003bb8: 687a ldr r2, [r7, #4]
|
|
8003bba: 6812 ldr r2, [r2, #0]
|
|
8003bbc: 430b orrs r3, r1
|
|
8003bbe: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8003bc0: 687b ldr r3, [r7, #4]
|
|
8003bc2: 681b ldr r3, [r3, #0]
|
|
8003bc4: 68db ldr r3, [r3, #12]
|
|
8003bc6: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8003bca: 687b ldr r3, [r7, #4]
|
|
8003bcc: 695a ldr r2, [r3, #20]
|
|
8003bce: 687b ldr r3, [r7, #4]
|
|
8003bd0: 699b ldr r3, [r3, #24]
|
|
8003bd2: 431a orrs r2, r3
|
|
8003bd4: 687b ldr r3, [r7, #4]
|
|
8003bd6: 681b ldr r3, [r3, #0]
|
|
8003bd8: 430a orrs r2, r1
|
|
8003bda: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003bdc: 687b ldr r3, [r7, #4]
|
|
8003bde: 681b ldr r3, [r3, #0]
|
|
8003be0: 681a ldr r2, [r3, #0]
|
|
8003be2: 687b ldr r3, [r7, #4]
|
|
8003be4: 681b ldr r3, [r3, #0]
|
|
8003be6: f042 0201 orr.w r2, r2, #1
|
|
8003bea: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003bec: 687b ldr r3, [r7, #4]
|
|
8003bee: 2200 movs r2, #0
|
|
8003bf0: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003bf2: 687b ldr r3, [r7, #4]
|
|
8003bf4: 2220 movs r2, #32
|
|
8003bf6: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8003bfa: 687b ldr r3, [r7, #4]
|
|
8003bfc: 2200 movs r2, #0
|
|
8003bfe: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003c00: 687b ldr r3, [r7, #4]
|
|
8003c02: 2200 movs r2, #0
|
|
8003c04: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8003c08: 2300 movs r3, #0
|
|
}
|
|
8003c0a: 4618 mov r0, r3
|
|
8003c0c: 3710 adds r7, #16
|
|
8003c0e: 46bd mov sp, r7
|
|
8003c10: bd80 pop {r7, pc}
|
|
8003c12: bf00 nop
|
|
8003c14: 000186a0 .word 0x000186a0
|
|
8003c18: 001e847f .word 0x001e847f
|
|
8003c1c: 003d08ff .word 0x003d08ff
|
|
8003c20: 431bde83 .word 0x431bde83
|
|
8003c24: 10624dd3 .word 0x10624dd3
|
|
|
|
08003c28 <HAL_I2C_Master_Transmit>:
|
|
* @param Size Amount of data to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8003c28: b580 push {r7, lr}
|
|
8003c2a: b088 sub sp, #32
|
|
8003c2c: af02 add r7, sp, #8
|
|
8003c2e: 60f8 str r0, [r7, #12]
|
|
8003c30: 607a str r2, [r7, #4]
|
|
8003c32: 461a mov r2, r3
|
|
8003c34: 460b mov r3, r1
|
|
8003c36: 817b strh r3, [r7, #10]
|
|
8003c38: 4613 mov r3, r2
|
|
8003c3a: 813b strh r3, [r7, #8]
|
|
/* Init tickstart for timeout management*/
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8003c3c: f7ff f908 bl 8002e50 <HAL_GetTick>
|
|
8003c40: 6178 str r0, [r7, #20]
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003c42: 68fb ldr r3, [r7, #12]
|
|
8003c44: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8003c48: b2db uxtb r3, r3
|
|
8003c4a: 2b20 cmp r3, #32
|
|
8003c4c: f040 80e0 bne.w 8003e10 <HAL_I2C_Master_Transmit+0x1e8>
|
|
{
|
|
/* Wait until BUSY flag is reset */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
|
|
8003c50: 697b ldr r3, [r7, #20]
|
|
8003c52: 9300 str r3, [sp, #0]
|
|
8003c54: 2319 movs r3, #25
|
|
8003c56: 2201 movs r2, #1
|
|
8003c58: 4970 ldr r1, [pc, #448] @ (8003e1c <HAL_I2C_Master_Transmit+0x1f4>)
|
|
8003c5a: 68f8 ldr r0, [r7, #12]
|
|
8003c5c: f000 fc9e bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
8003c60: 4603 mov r3, r0
|
|
8003c62: 2b00 cmp r3, #0
|
|
8003c64: d001 beq.n 8003c6a <HAL_I2C_Master_Transmit+0x42>
|
|
{
|
|
return HAL_BUSY;
|
|
8003c66: 2302 movs r3, #2
|
|
8003c68: e0d3 b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8003c6a: 68fb ldr r3, [r7, #12]
|
|
8003c6c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8003c70: 2b01 cmp r3, #1
|
|
8003c72: d101 bne.n 8003c78 <HAL_I2C_Master_Transmit+0x50>
|
|
8003c74: 2302 movs r3, #2
|
|
8003c76: e0cc b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
8003c78: 68fb ldr r3, [r7, #12]
|
|
8003c7a: 2201 movs r2, #1
|
|
8003c7c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Check if the I2C is already enabled */
|
|
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
|
|
8003c80: 68fb ldr r3, [r7, #12]
|
|
8003c82: 681b ldr r3, [r3, #0]
|
|
8003c84: 681b ldr r3, [r3, #0]
|
|
8003c86: f003 0301 and.w r3, r3, #1
|
|
8003c8a: 2b01 cmp r3, #1
|
|
8003c8c: d007 beq.n 8003c9e <HAL_I2C_Master_Transmit+0x76>
|
|
{
|
|
/* Enable I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003c8e: 68fb ldr r3, [r7, #12]
|
|
8003c90: 681b ldr r3, [r3, #0]
|
|
8003c92: 681a ldr r2, [r3, #0]
|
|
8003c94: 68fb ldr r3, [r7, #12]
|
|
8003c96: 681b ldr r3, [r3, #0]
|
|
8003c98: f042 0201 orr.w r2, r2, #1
|
|
8003c9c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Disable Pos */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
|
|
8003c9e: 68fb ldr r3, [r7, #12]
|
|
8003ca0: 681b ldr r3, [r3, #0]
|
|
8003ca2: 681a ldr r2, [r3, #0]
|
|
8003ca4: 68fb ldr r3, [r7, #12]
|
|
8003ca6: 681b ldr r3, [r3, #0]
|
|
8003ca8: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8003cac: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8003cae: 68fb ldr r3, [r7, #12]
|
|
8003cb0: 2221 movs r2, #33 @ 0x21
|
|
8003cb2: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_MASTER;
|
|
8003cb6: 68fb ldr r3, [r7, #12]
|
|
8003cb8: 2210 movs r2, #16
|
|
8003cba: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003cbe: 68fb ldr r3, [r7, #12]
|
|
8003cc0: 2200 movs r2, #0
|
|
8003cc2: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8003cc4: 68fb ldr r3, [r7, #12]
|
|
8003cc6: 687a ldr r2, [r7, #4]
|
|
8003cc8: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8003cca: 68fb ldr r3, [r7, #12]
|
|
8003ccc: 893a ldrh r2, [r7, #8]
|
|
8003cce: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8003cd0: 68fb ldr r3, [r7, #12]
|
|
8003cd2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003cd4: b29a uxth r2, r3
|
|
8003cd6: 68fb ldr r3, [r7, #12]
|
|
8003cd8: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8003cda: 68fb ldr r3, [r7, #12]
|
|
8003cdc: 4a50 ldr r2, [pc, #320] @ (8003e20 <HAL_I2C_Master_Transmit+0x1f8>)
|
|
8003cde: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Send Slave Address */
|
|
if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
|
|
8003ce0: 8979 ldrh r1, [r7, #10]
|
|
8003ce2: 697b ldr r3, [r7, #20]
|
|
8003ce4: 6a3a ldr r2, [r7, #32]
|
|
8003ce6: 68f8 ldr r0, [r7, #12]
|
|
8003ce8: f000 fb08 bl 80042fc <I2C_MasterRequestWrite>
|
|
8003cec: 4603 mov r3, r0
|
|
8003cee: 2b00 cmp r3, #0
|
|
8003cf0: d001 beq.n 8003cf6 <HAL_I2C_Master_Transmit+0xce>
|
|
{
|
|
return HAL_ERROR;
|
|
8003cf2: 2301 movs r3, #1
|
|
8003cf4: e08d b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
}
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8003cf6: 2300 movs r3, #0
|
|
8003cf8: 613b str r3, [r7, #16]
|
|
8003cfa: 68fb ldr r3, [r7, #12]
|
|
8003cfc: 681b ldr r3, [r3, #0]
|
|
8003cfe: 695b ldr r3, [r3, #20]
|
|
8003d00: 613b str r3, [r7, #16]
|
|
8003d02: 68fb ldr r3, [r7, #12]
|
|
8003d04: 681b ldr r3, [r3, #0]
|
|
8003d06: 699b ldr r3, [r3, #24]
|
|
8003d08: 613b str r3, [r7, #16]
|
|
8003d0a: 693b ldr r3, [r7, #16]
|
|
|
|
while (hi2c->XferSize > 0U)
|
|
8003d0c: e066 b.n 8003ddc <HAL_I2C_Master_Transmit+0x1b4>
|
|
{
|
|
/* Wait until TXE flag is set */
|
|
if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8003d0e: 697a ldr r2, [r7, #20]
|
|
8003d10: 6a39 ldr r1, [r7, #32]
|
|
8003d12: 68f8 ldr r0, [r7, #12]
|
|
8003d14: f000 fd5c bl 80047d0 <I2C_WaitOnTXEFlagUntilTimeout>
|
|
8003d18: 4603 mov r3, r0
|
|
8003d1a: 2b00 cmp r3, #0
|
|
8003d1c: d00d beq.n 8003d3a <HAL_I2C_Master_Transmit+0x112>
|
|
{
|
|
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
|
|
8003d1e: 68fb ldr r3, [r7, #12]
|
|
8003d20: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003d22: 2b04 cmp r3, #4
|
|
8003d24: d107 bne.n 8003d36 <HAL_I2C_Master_Transmit+0x10e>
|
|
{
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8003d26: 68fb ldr r3, [r7, #12]
|
|
8003d28: 681b ldr r3, [r3, #0]
|
|
8003d2a: 681a ldr r2, [r3, #0]
|
|
8003d2c: 68fb ldr r3, [r7, #12]
|
|
8003d2e: 681b ldr r3, [r3, #0]
|
|
8003d30: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8003d34: 601a str r2, [r3, #0]
|
|
}
|
|
return HAL_ERROR;
|
|
8003d36: 2301 movs r3, #1
|
|
8003d38: e06b b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
}
|
|
|
|
/* Write data to DR */
|
|
hi2c->Instance->DR = *hi2c->pBuffPtr;
|
|
8003d3a: 68fb ldr r3, [r7, #12]
|
|
8003d3c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003d3e: 781a ldrb r2, [r3, #0]
|
|
8003d40: 68fb ldr r3, [r7, #12]
|
|
8003d42: 681b ldr r3, [r3, #0]
|
|
8003d44: 611a str r2, [r3, #16]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8003d46: 68fb ldr r3, [r7, #12]
|
|
8003d48: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003d4a: 1c5a adds r2, r3, #1
|
|
8003d4c: 68fb ldr r3, [r7, #12]
|
|
8003d4e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferCount--;
|
|
8003d50: 68fb ldr r3, [r7, #12]
|
|
8003d52: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003d54: b29b uxth r3, r3
|
|
8003d56: 3b01 subs r3, #1
|
|
8003d58: b29a uxth r2, r3
|
|
8003d5a: 68fb ldr r3, [r7, #12]
|
|
8003d5c: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8003d5e: 68fb ldr r3, [r7, #12]
|
|
8003d60: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003d62: 3b01 subs r3, #1
|
|
8003d64: b29a uxth r2, r3
|
|
8003d66: 68fb ldr r3, [r7, #12]
|
|
8003d68: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
|
|
8003d6a: 68fb ldr r3, [r7, #12]
|
|
8003d6c: 681b ldr r3, [r3, #0]
|
|
8003d6e: 695b ldr r3, [r3, #20]
|
|
8003d70: f003 0304 and.w r3, r3, #4
|
|
8003d74: 2b04 cmp r3, #4
|
|
8003d76: d11b bne.n 8003db0 <HAL_I2C_Master_Transmit+0x188>
|
|
8003d78: 68fb ldr r3, [r7, #12]
|
|
8003d7a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003d7c: 2b00 cmp r3, #0
|
|
8003d7e: d017 beq.n 8003db0 <HAL_I2C_Master_Transmit+0x188>
|
|
{
|
|
/* Write data to DR */
|
|
hi2c->Instance->DR = *hi2c->pBuffPtr;
|
|
8003d80: 68fb ldr r3, [r7, #12]
|
|
8003d82: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003d84: 781a ldrb r2, [r3, #0]
|
|
8003d86: 68fb ldr r3, [r7, #12]
|
|
8003d88: 681b ldr r3, [r3, #0]
|
|
8003d8a: 611a str r2, [r3, #16]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8003d8c: 68fb ldr r3, [r7, #12]
|
|
8003d8e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003d90: 1c5a adds r2, r3, #1
|
|
8003d92: 68fb ldr r3, [r7, #12]
|
|
8003d94: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferCount--;
|
|
8003d96: 68fb ldr r3, [r7, #12]
|
|
8003d98: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003d9a: b29b uxth r3, r3
|
|
8003d9c: 3b01 subs r3, #1
|
|
8003d9e: b29a uxth r2, r3
|
|
8003da0: 68fb ldr r3, [r7, #12]
|
|
8003da2: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8003da4: 68fb ldr r3, [r7, #12]
|
|
8003da6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003da8: 3b01 subs r3, #1
|
|
8003daa: b29a uxth r2, r3
|
|
8003dac: 68fb ldr r3, [r7, #12]
|
|
8003dae: 851a strh r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until BTF flag is set */
|
|
if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8003db0: 697a ldr r2, [r7, #20]
|
|
8003db2: 6a39 ldr r1, [r7, #32]
|
|
8003db4: 68f8 ldr r0, [r7, #12]
|
|
8003db6: f000 fd53 bl 8004860 <I2C_WaitOnBTFFlagUntilTimeout>
|
|
8003dba: 4603 mov r3, r0
|
|
8003dbc: 2b00 cmp r3, #0
|
|
8003dbe: d00d beq.n 8003ddc <HAL_I2C_Master_Transmit+0x1b4>
|
|
{
|
|
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
|
|
8003dc0: 68fb ldr r3, [r7, #12]
|
|
8003dc2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003dc4: 2b04 cmp r3, #4
|
|
8003dc6: d107 bne.n 8003dd8 <HAL_I2C_Master_Transmit+0x1b0>
|
|
{
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8003dc8: 68fb ldr r3, [r7, #12]
|
|
8003dca: 681b ldr r3, [r3, #0]
|
|
8003dcc: 681a ldr r2, [r3, #0]
|
|
8003dce: 68fb ldr r3, [r7, #12]
|
|
8003dd0: 681b ldr r3, [r3, #0]
|
|
8003dd2: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8003dd6: 601a str r2, [r3, #0]
|
|
}
|
|
return HAL_ERROR;
|
|
8003dd8: 2301 movs r3, #1
|
|
8003dda: e01a b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
while (hi2c->XferSize > 0U)
|
|
8003ddc: 68fb ldr r3, [r7, #12]
|
|
8003dde: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003de0: 2b00 cmp r3, #0
|
|
8003de2: d194 bne.n 8003d0e <HAL_I2C_Master_Transmit+0xe6>
|
|
}
|
|
}
|
|
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8003de4: 68fb ldr r3, [r7, #12]
|
|
8003de6: 681b ldr r3, [r3, #0]
|
|
8003de8: 681a ldr r2, [r3, #0]
|
|
8003dea: 68fb ldr r3, [r7, #12]
|
|
8003dec: 681b ldr r3, [r3, #0]
|
|
8003dee: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8003df2: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003df4: 68fb ldr r3, [r7, #12]
|
|
8003df6: 2220 movs r2, #32
|
|
8003df8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003dfc: 68fb ldr r3, [r7, #12]
|
|
8003dfe: 2200 movs r2, #0
|
|
8003e00: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003e04: 68fb ldr r3, [r7, #12]
|
|
8003e06: 2200 movs r2, #0
|
|
8003e08: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8003e0c: 2300 movs r3, #0
|
|
8003e0e: e000 b.n 8003e12 <HAL_I2C_Master_Transmit+0x1ea>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003e10: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8003e12: 4618 mov r0, r3
|
|
8003e14: 3718 adds r7, #24
|
|
8003e16: 46bd mov sp, r7
|
|
8003e18: bd80 pop {r7, pc}
|
|
8003e1a: bf00 nop
|
|
8003e1c: 00100002 .word 0x00100002
|
|
8003e20: ffff0000 .word 0xffff0000
|
|
|
|
08003e24 <HAL_I2C_Master_Receive>:
|
|
* @param Size Amount of data to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8003e24: b580 push {r7, lr}
|
|
8003e26: b08c sub sp, #48 @ 0x30
|
|
8003e28: af02 add r7, sp, #8
|
|
8003e2a: 60f8 str r0, [r7, #12]
|
|
8003e2c: 607a str r2, [r7, #4]
|
|
8003e2e: 461a mov r2, r3
|
|
8003e30: 460b mov r3, r1
|
|
8003e32: 817b strh r3, [r7, #10]
|
|
8003e34: 4613 mov r3, r2
|
|
8003e36: 813b strh r3, [r7, #8]
|
|
__IO uint32_t count = 0U;
|
|
8003e38: 2300 movs r3, #0
|
|
8003e3a: 623b str r3, [r7, #32]
|
|
|
|
/* Init tickstart for timeout management*/
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8003e3c: f7ff f808 bl 8002e50 <HAL_GetTick>
|
|
8003e40: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003e42: 68fb ldr r3, [r7, #12]
|
|
8003e44: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8003e48: b2db uxtb r3, r3
|
|
8003e4a: 2b20 cmp r3, #32
|
|
8003e4c: f040 824b bne.w 80042e6 <HAL_I2C_Master_Receive+0x4c2>
|
|
{
|
|
/* Wait until BUSY flag is reset */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
|
|
8003e50: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003e52: 9300 str r3, [sp, #0]
|
|
8003e54: 2319 movs r3, #25
|
|
8003e56: 2201 movs r2, #1
|
|
8003e58: 497f ldr r1, [pc, #508] @ (8004058 <HAL_I2C_Master_Receive+0x234>)
|
|
8003e5a: 68f8 ldr r0, [r7, #12]
|
|
8003e5c: f000 fb9e bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
8003e60: 4603 mov r3, r0
|
|
8003e62: 2b00 cmp r3, #0
|
|
8003e64: d001 beq.n 8003e6a <HAL_I2C_Master_Receive+0x46>
|
|
{
|
|
return HAL_BUSY;
|
|
8003e66: 2302 movs r3, #2
|
|
8003e68: e23e b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8003e6a: 68fb ldr r3, [r7, #12]
|
|
8003e6c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8003e70: 2b01 cmp r3, #1
|
|
8003e72: d101 bne.n 8003e78 <HAL_I2C_Master_Receive+0x54>
|
|
8003e74: 2302 movs r3, #2
|
|
8003e76: e237 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
8003e78: 68fb ldr r3, [r7, #12]
|
|
8003e7a: 2201 movs r2, #1
|
|
8003e7c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Check if the I2C is already enabled */
|
|
if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
|
|
8003e80: 68fb ldr r3, [r7, #12]
|
|
8003e82: 681b ldr r3, [r3, #0]
|
|
8003e84: 681b ldr r3, [r3, #0]
|
|
8003e86: f003 0301 and.w r3, r3, #1
|
|
8003e8a: 2b01 cmp r3, #1
|
|
8003e8c: d007 beq.n 8003e9e <HAL_I2C_Master_Receive+0x7a>
|
|
{
|
|
/* Enable I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003e8e: 68fb ldr r3, [r7, #12]
|
|
8003e90: 681b ldr r3, [r3, #0]
|
|
8003e92: 681a ldr r2, [r3, #0]
|
|
8003e94: 68fb ldr r3, [r7, #12]
|
|
8003e96: 681b ldr r3, [r3, #0]
|
|
8003e98: f042 0201 orr.w r2, r2, #1
|
|
8003e9c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Disable Pos */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
|
|
8003e9e: 68fb ldr r3, [r7, #12]
|
|
8003ea0: 681b ldr r3, [r3, #0]
|
|
8003ea2: 681a ldr r2, [r3, #0]
|
|
8003ea4: 68fb ldr r3, [r7, #12]
|
|
8003ea6: 681b ldr r3, [r3, #0]
|
|
8003ea8: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8003eac: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
8003eae: 68fb ldr r3, [r7, #12]
|
|
8003eb0: 2222 movs r2, #34 @ 0x22
|
|
8003eb2: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_MASTER;
|
|
8003eb6: 68fb ldr r3, [r7, #12]
|
|
8003eb8: 2210 movs r2, #16
|
|
8003eba: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003ebe: 68fb ldr r3, [r7, #12]
|
|
8003ec0: 2200 movs r2, #0
|
|
8003ec2: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8003ec4: 68fb ldr r3, [r7, #12]
|
|
8003ec6: 687a ldr r2, [r7, #4]
|
|
8003ec8: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8003eca: 68fb ldr r3, [r7, #12]
|
|
8003ecc: 893a ldrh r2, [r7, #8]
|
|
8003ece: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8003ed0: 68fb ldr r3, [r7, #12]
|
|
8003ed2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003ed4: b29a uxth r2, r3
|
|
8003ed6: 68fb ldr r3, [r7, #12]
|
|
8003ed8: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8003eda: 68fb ldr r3, [r7, #12]
|
|
8003edc: 4a5f ldr r2, [pc, #380] @ (800405c <HAL_I2C_Master_Receive+0x238>)
|
|
8003ede: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Send Slave Address */
|
|
if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
|
|
8003ee0: 8979 ldrh r1, [r7, #10]
|
|
8003ee2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003ee4: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8003ee6: 68f8 ldr r0, [r7, #12]
|
|
8003ee8: f000 fa8a bl 8004400 <I2C_MasterRequestRead>
|
|
8003eec: 4603 mov r3, r0
|
|
8003eee: 2b00 cmp r3, #0
|
|
8003ef0: d001 beq.n 8003ef6 <HAL_I2C_Master_Receive+0xd2>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ef2: 2301 movs r3, #1
|
|
8003ef4: e1f8 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
|
|
if (hi2c->XferSize == 0U)
|
|
8003ef6: 68fb ldr r3, [r7, #12]
|
|
8003ef8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003efa: 2b00 cmp r3, #0
|
|
8003efc: d113 bne.n 8003f26 <HAL_I2C_Master_Receive+0x102>
|
|
{
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8003efe: 2300 movs r3, #0
|
|
8003f00: 61fb str r3, [r7, #28]
|
|
8003f02: 68fb ldr r3, [r7, #12]
|
|
8003f04: 681b ldr r3, [r3, #0]
|
|
8003f06: 695b ldr r3, [r3, #20]
|
|
8003f08: 61fb str r3, [r7, #28]
|
|
8003f0a: 68fb ldr r3, [r7, #12]
|
|
8003f0c: 681b ldr r3, [r3, #0]
|
|
8003f0e: 699b ldr r3, [r3, #24]
|
|
8003f10: 61fb str r3, [r7, #28]
|
|
8003f12: 69fb ldr r3, [r7, #28]
|
|
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8003f14: 68fb ldr r3, [r7, #12]
|
|
8003f16: 681b ldr r3, [r3, #0]
|
|
8003f18: 681a ldr r2, [r3, #0]
|
|
8003f1a: 68fb ldr r3, [r7, #12]
|
|
8003f1c: 681b ldr r3, [r3, #0]
|
|
8003f1e: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8003f22: 601a str r2, [r3, #0]
|
|
8003f24: e1cc b.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
}
|
|
else if (hi2c->XferSize == 1U)
|
|
8003f26: 68fb ldr r3, [r7, #12]
|
|
8003f28: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f2a: 2b01 cmp r3, #1
|
|
8003f2c: d11e bne.n 8003f6c <HAL_I2C_Master_Receive+0x148>
|
|
{
|
|
/* Disable Acknowledge */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
8003f2e: 68fb ldr r3, [r7, #12]
|
|
8003f30: 681b ldr r3, [r3, #0]
|
|
8003f32: 681a ldr r2, [r3, #0]
|
|
8003f34: 68fb ldr r3, [r7, #12]
|
|
8003f36: 681b ldr r3, [r3, #0]
|
|
8003f38: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8003f3c: 601a str r2, [r3, #0]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8003f3e: b672 cpsid i
|
|
}
|
|
8003f40: bf00 nop
|
|
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
|
|
software sequence must complete before the current byte end of transfer */
|
|
__disable_irq();
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8003f42: 2300 movs r3, #0
|
|
8003f44: 61bb str r3, [r7, #24]
|
|
8003f46: 68fb ldr r3, [r7, #12]
|
|
8003f48: 681b ldr r3, [r3, #0]
|
|
8003f4a: 695b ldr r3, [r3, #20]
|
|
8003f4c: 61bb str r3, [r7, #24]
|
|
8003f4e: 68fb ldr r3, [r7, #12]
|
|
8003f50: 681b ldr r3, [r3, #0]
|
|
8003f52: 699b ldr r3, [r3, #24]
|
|
8003f54: 61bb str r3, [r7, #24]
|
|
8003f56: 69bb ldr r3, [r7, #24]
|
|
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8003f58: 68fb ldr r3, [r7, #12]
|
|
8003f5a: 681b ldr r3, [r3, #0]
|
|
8003f5c: 681a ldr r2, [r3, #0]
|
|
8003f5e: 68fb ldr r3, [r7, #12]
|
|
8003f60: 681b ldr r3, [r3, #0]
|
|
8003f62: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8003f66: 601a str r2, [r3, #0]
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8003f68: b662 cpsie i
|
|
}
|
|
8003f6a: e035 b.n 8003fd8 <HAL_I2C_Master_Receive+0x1b4>
|
|
|
|
/* Re-enable IRQs */
|
|
__enable_irq();
|
|
}
|
|
else if (hi2c->XferSize == 2U)
|
|
8003f6c: 68fb ldr r3, [r7, #12]
|
|
8003f6e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f70: 2b02 cmp r3, #2
|
|
8003f72: d11e bne.n 8003fb2 <HAL_I2C_Master_Receive+0x18e>
|
|
{
|
|
/* Enable Pos */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
|
|
8003f74: 68fb ldr r3, [r7, #12]
|
|
8003f76: 681b ldr r3, [r3, #0]
|
|
8003f78: 681a ldr r2, [r3, #0]
|
|
8003f7a: 68fb ldr r3, [r7, #12]
|
|
8003f7c: 681b ldr r3, [r3, #0]
|
|
8003f7e: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8003f82: 601a str r2, [r3, #0]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8003f84: b672 cpsid i
|
|
}
|
|
8003f86: bf00 nop
|
|
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
|
|
software sequence must complete before the current byte end of transfer */
|
|
__disable_irq();
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8003f88: 2300 movs r3, #0
|
|
8003f8a: 617b str r3, [r7, #20]
|
|
8003f8c: 68fb ldr r3, [r7, #12]
|
|
8003f8e: 681b ldr r3, [r3, #0]
|
|
8003f90: 695b ldr r3, [r3, #20]
|
|
8003f92: 617b str r3, [r7, #20]
|
|
8003f94: 68fb ldr r3, [r7, #12]
|
|
8003f96: 681b ldr r3, [r3, #0]
|
|
8003f98: 699b ldr r3, [r3, #24]
|
|
8003f9a: 617b str r3, [r7, #20]
|
|
8003f9c: 697b ldr r3, [r7, #20]
|
|
|
|
/* Disable Acknowledge */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
8003f9e: 68fb ldr r3, [r7, #12]
|
|
8003fa0: 681b ldr r3, [r3, #0]
|
|
8003fa2: 681a ldr r2, [r3, #0]
|
|
8003fa4: 68fb ldr r3, [r7, #12]
|
|
8003fa6: 681b ldr r3, [r3, #0]
|
|
8003fa8: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8003fac: 601a str r2, [r3, #0]
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8003fae: b662 cpsie i
|
|
}
|
|
8003fb0: e012 b.n 8003fd8 <HAL_I2C_Master_Receive+0x1b4>
|
|
__enable_irq();
|
|
}
|
|
else
|
|
{
|
|
/* Enable Acknowledge */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
8003fb2: 68fb ldr r3, [r7, #12]
|
|
8003fb4: 681b ldr r3, [r3, #0]
|
|
8003fb6: 681a ldr r2, [r3, #0]
|
|
8003fb8: 68fb ldr r3, [r7, #12]
|
|
8003fba: 681b ldr r3, [r3, #0]
|
|
8003fbc: f442 6280 orr.w r2, r2, #1024 @ 0x400
|
|
8003fc0: 601a str r2, [r3, #0]
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8003fc2: 2300 movs r3, #0
|
|
8003fc4: 613b str r3, [r7, #16]
|
|
8003fc6: 68fb ldr r3, [r7, #12]
|
|
8003fc8: 681b ldr r3, [r3, #0]
|
|
8003fca: 695b ldr r3, [r3, #20]
|
|
8003fcc: 613b str r3, [r7, #16]
|
|
8003fce: 68fb ldr r3, [r7, #12]
|
|
8003fd0: 681b ldr r3, [r3, #0]
|
|
8003fd2: 699b ldr r3, [r3, #24]
|
|
8003fd4: 613b str r3, [r7, #16]
|
|
8003fd6: 693b ldr r3, [r7, #16]
|
|
}
|
|
|
|
while (hi2c->XferSize > 0U)
|
|
8003fd8: e172 b.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
{
|
|
if (hi2c->XferSize <= 3U)
|
|
8003fda: 68fb ldr r3, [r7, #12]
|
|
8003fdc: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003fde: 2b03 cmp r3, #3
|
|
8003fe0: f200 811f bhi.w 8004222 <HAL_I2C_Master_Receive+0x3fe>
|
|
{
|
|
/* One byte */
|
|
if (hi2c->XferSize == 1U)
|
|
8003fe4: 68fb ldr r3, [r7, #12]
|
|
8003fe6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003fe8: 2b01 cmp r3, #1
|
|
8003fea: d123 bne.n 8004034 <HAL_I2C_Master_Receive+0x210>
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8003fec: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003fee: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
8003ff0: 68f8 ldr r0, [r7, #12]
|
|
8003ff2: f000 fc7d bl 80048f0 <I2C_WaitOnRXNEFlagUntilTimeout>
|
|
8003ff6: 4603 mov r3, r0
|
|
8003ff8: 2b00 cmp r3, #0
|
|
8003ffa: d001 beq.n 8004000 <HAL_I2C_Master_Receive+0x1dc>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ffc: 2301 movs r3, #1
|
|
8003ffe: e173 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
8004000: 68fb ldr r3, [r7, #12]
|
|
8004002: 681b ldr r3, [r3, #0]
|
|
8004004: 691a ldr r2, [r3, #16]
|
|
8004006: 68fb ldr r3, [r7, #12]
|
|
8004008: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800400a: b2d2 uxtb r2, r2
|
|
800400c: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
800400e: 68fb ldr r3, [r7, #12]
|
|
8004010: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004012: 1c5a adds r2, r3, #1
|
|
8004014: 68fb ldr r3, [r7, #12]
|
|
8004016: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
8004018: 68fb ldr r3, [r7, #12]
|
|
800401a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800401c: 3b01 subs r3, #1
|
|
800401e: b29a uxth r2, r3
|
|
8004020: 68fb ldr r3, [r7, #12]
|
|
8004022: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8004024: 68fb ldr r3, [r7, #12]
|
|
8004026: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004028: b29b uxth r3, r3
|
|
800402a: 3b01 subs r3, #1
|
|
800402c: b29a uxth r2, r3
|
|
800402e: 68fb ldr r3, [r7, #12]
|
|
8004030: 855a strh r2, [r3, #42] @ 0x2a
|
|
8004032: e145 b.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
}
|
|
/* Two bytes */
|
|
else if (hi2c->XferSize == 2U)
|
|
8004034: 68fb ldr r3, [r7, #12]
|
|
8004036: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004038: 2b02 cmp r3, #2
|
|
800403a: d152 bne.n 80040e2 <HAL_I2C_Master_Receive+0x2be>
|
|
{
|
|
/* Wait until BTF flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
|
|
800403c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800403e: 9300 str r3, [sp, #0]
|
|
8004040: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8004042: 2200 movs r2, #0
|
|
8004044: 4906 ldr r1, [pc, #24] @ (8004060 <HAL_I2C_Master_Receive+0x23c>)
|
|
8004046: 68f8 ldr r0, [r7, #12]
|
|
8004048: f000 faa8 bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
800404c: 4603 mov r3, r0
|
|
800404e: 2b00 cmp r3, #0
|
|
8004050: d008 beq.n 8004064 <HAL_I2C_Master_Receive+0x240>
|
|
{
|
|
return HAL_ERROR;
|
|
8004052: 2301 movs r3, #1
|
|
8004054: e148 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
8004056: bf00 nop
|
|
8004058: 00100002 .word 0x00100002
|
|
800405c: ffff0000 .word 0xffff0000
|
|
8004060: 00010004 .word 0x00010004
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8004064: b672 cpsid i
|
|
}
|
|
8004066: bf00 nop
|
|
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
|
|
software sequence must complete before the current byte end of transfer */
|
|
__disable_irq();
|
|
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
8004068: 68fb ldr r3, [r7, #12]
|
|
800406a: 681b ldr r3, [r3, #0]
|
|
800406c: 681a ldr r2, [r3, #0]
|
|
800406e: 68fb ldr r3, [r7, #12]
|
|
8004070: 681b ldr r3, [r3, #0]
|
|
8004072: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
8004076: 601a str r2, [r3, #0]
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
8004078: 68fb ldr r3, [r7, #12]
|
|
800407a: 681b ldr r3, [r3, #0]
|
|
800407c: 691a ldr r2, [r3, #16]
|
|
800407e: 68fb ldr r3, [r7, #12]
|
|
8004080: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004082: b2d2 uxtb r2, r2
|
|
8004084: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8004086: 68fb ldr r3, [r7, #12]
|
|
8004088: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800408a: 1c5a adds r2, r3, #1
|
|
800408c: 68fb ldr r3, [r7, #12]
|
|
800408e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
8004090: 68fb ldr r3, [r7, #12]
|
|
8004092: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004094: 3b01 subs r3, #1
|
|
8004096: b29a uxth r2, r3
|
|
8004098: 68fb ldr r3, [r7, #12]
|
|
800409a: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
800409c: 68fb ldr r3, [r7, #12]
|
|
800409e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80040a0: b29b uxth r3, r3
|
|
80040a2: 3b01 subs r3, #1
|
|
80040a4: b29a uxth r2, r3
|
|
80040a6: 68fb ldr r3, [r7, #12]
|
|
80040a8: 855a strh r2, [r3, #42] @ 0x2a
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
80040aa: b662 cpsie i
|
|
}
|
|
80040ac: bf00 nop
|
|
|
|
/* Re-enable IRQs */
|
|
__enable_irq();
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
80040ae: 68fb ldr r3, [r7, #12]
|
|
80040b0: 681b ldr r3, [r3, #0]
|
|
80040b2: 691a ldr r2, [r3, #16]
|
|
80040b4: 68fb ldr r3, [r7, #12]
|
|
80040b6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80040b8: b2d2 uxtb r2, r2
|
|
80040ba: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80040bc: 68fb ldr r3, [r7, #12]
|
|
80040be: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80040c0: 1c5a adds r2, r3, #1
|
|
80040c2: 68fb ldr r3, [r7, #12]
|
|
80040c4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
80040c6: 68fb ldr r3, [r7, #12]
|
|
80040c8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80040ca: 3b01 subs r3, #1
|
|
80040cc: b29a uxth r2, r3
|
|
80040ce: 68fb ldr r3, [r7, #12]
|
|
80040d0: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
80040d2: 68fb ldr r3, [r7, #12]
|
|
80040d4: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80040d6: b29b uxth r3, r3
|
|
80040d8: 3b01 subs r3, #1
|
|
80040da: b29a uxth r2, r3
|
|
80040dc: 68fb ldr r3, [r7, #12]
|
|
80040de: 855a strh r2, [r3, #42] @ 0x2a
|
|
80040e0: e0ee b.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
}
|
|
/* 3 Last bytes */
|
|
else
|
|
{
|
|
/* Wait until BTF flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
|
|
80040e2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80040e4: 9300 str r3, [sp, #0]
|
|
80040e6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80040e8: 2200 movs r2, #0
|
|
80040ea: 4981 ldr r1, [pc, #516] @ (80042f0 <HAL_I2C_Master_Receive+0x4cc>)
|
|
80040ec: 68f8 ldr r0, [r7, #12]
|
|
80040ee: f000 fa55 bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
80040f2: 4603 mov r3, r0
|
|
80040f4: 2b00 cmp r3, #0
|
|
80040f6: d001 beq.n 80040fc <HAL_I2C_Master_Receive+0x2d8>
|
|
{
|
|
return HAL_ERROR;
|
|
80040f8: 2301 movs r3, #1
|
|
80040fa: e0f5 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
|
|
/* Disable Acknowledge */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
80040fc: 68fb ldr r3, [r7, #12]
|
|
80040fe: 681b ldr r3, [r3, #0]
|
|
8004100: 681a ldr r2, [r3, #0]
|
|
8004102: 68fb ldr r3, [r7, #12]
|
|
8004104: 681b ldr r3, [r3, #0]
|
|
8004106: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800410a: 601a str r2, [r3, #0]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800410c: b672 cpsid i
|
|
}
|
|
800410e: bf00 nop
|
|
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
|
|
software sequence must complete before the current byte end of transfer */
|
|
__disable_irq();
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
8004110: 68fb ldr r3, [r7, #12]
|
|
8004112: 681b ldr r3, [r3, #0]
|
|
8004114: 691a ldr r2, [r3, #16]
|
|
8004116: 68fb ldr r3, [r7, #12]
|
|
8004118: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800411a: b2d2 uxtb r2, r2
|
|
800411c: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
800411e: 68fb ldr r3, [r7, #12]
|
|
8004120: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004122: 1c5a adds r2, r3, #1
|
|
8004124: 68fb ldr r3, [r7, #12]
|
|
8004126: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
8004128: 68fb ldr r3, [r7, #12]
|
|
800412a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800412c: 3b01 subs r3, #1
|
|
800412e: b29a uxth r2, r3
|
|
8004130: 68fb ldr r3, [r7, #12]
|
|
8004132: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8004134: 68fb ldr r3, [r7, #12]
|
|
8004136: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004138: b29b uxth r3, r3
|
|
800413a: 3b01 subs r3, #1
|
|
800413c: b29a uxth r2, r3
|
|
800413e: 68fb ldr r3, [r7, #12]
|
|
8004140: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Wait until BTF flag is set */
|
|
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
|
|
8004142: 4b6c ldr r3, [pc, #432] @ (80042f4 <HAL_I2C_Master_Receive+0x4d0>)
|
|
8004144: 681b ldr r3, [r3, #0]
|
|
8004146: 08db lsrs r3, r3, #3
|
|
8004148: 4a6b ldr r2, [pc, #428] @ (80042f8 <HAL_I2C_Master_Receive+0x4d4>)
|
|
800414a: fba2 2303 umull r2, r3, r2, r3
|
|
800414e: 0a1a lsrs r2, r3, #8
|
|
8004150: 4613 mov r3, r2
|
|
8004152: 009b lsls r3, r3, #2
|
|
8004154: 4413 add r3, r2
|
|
8004156: 00da lsls r2, r3, #3
|
|
8004158: 1ad3 subs r3, r2, r3
|
|
800415a: 623b str r3, [r7, #32]
|
|
do
|
|
{
|
|
count--;
|
|
800415c: 6a3b ldr r3, [r7, #32]
|
|
800415e: 3b01 subs r3, #1
|
|
8004160: 623b str r3, [r7, #32]
|
|
if (count == 0U)
|
|
8004162: 6a3b ldr r3, [r7, #32]
|
|
8004164: 2b00 cmp r3, #0
|
|
8004166: d118 bne.n 800419a <HAL_I2C_Master_Receive+0x376>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004168: 68fb ldr r3, [r7, #12]
|
|
800416a: 2200 movs r2, #0
|
|
800416c: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800416e: 68fb ldr r3, [r7, #12]
|
|
8004170: 2220 movs r2, #32
|
|
8004172: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004176: 68fb ldr r3, [r7, #12]
|
|
8004178: 2200 movs r2, #0
|
|
800417a: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800417e: 68fb ldr r3, [r7, #12]
|
|
8004180: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004182: f043 0220 orr.w r2, r3, #32
|
|
8004186: 68fb ldr r3, [r7, #12]
|
|
8004188: 641a str r2, [r3, #64] @ 0x40
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
800418a: b662 cpsie i
|
|
}
|
|
800418c: bf00 nop
|
|
|
|
/* Re-enable IRQs */
|
|
__enable_irq();
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800418e: 68fb ldr r3, [r7, #12]
|
|
8004190: 2200 movs r2, #0
|
|
8004192: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8004196: 2301 movs r3, #1
|
|
8004198: e0a6 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
}
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
|
|
800419a: 68fb ldr r3, [r7, #12]
|
|
800419c: 681b ldr r3, [r3, #0]
|
|
800419e: 695b ldr r3, [r3, #20]
|
|
80041a0: f003 0304 and.w r3, r3, #4
|
|
80041a4: 2b04 cmp r3, #4
|
|
80041a6: d1d9 bne.n 800415c <HAL_I2C_Master_Receive+0x338>
|
|
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
80041a8: 68fb ldr r3, [r7, #12]
|
|
80041aa: 681b ldr r3, [r3, #0]
|
|
80041ac: 681a ldr r2, [r3, #0]
|
|
80041ae: 68fb ldr r3, [r7, #12]
|
|
80041b0: 681b ldr r3, [r3, #0]
|
|
80041b2: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
80041b6: 601a str r2, [r3, #0]
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
80041b8: 68fb ldr r3, [r7, #12]
|
|
80041ba: 681b ldr r3, [r3, #0]
|
|
80041bc: 691a ldr r2, [r3, #16]
|
|
80041be: 68fb ldr r3, [r7, #12]
|
|
80041c0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80041c2: b2d2 uxtb r2, r2
|
|
80041c4: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80041c6: 68fb ldr r3, [r7, #12]
|
|
80041c8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80041ca: 1c5a adds r2, r3, #1
|
|
80041cc: 68fb ldr r3, [r7, #12]
|
|
80041ce: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
80041d0: 68fb ldr r3, [r7, #12]
|
|
80041d2: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80041d4: 3b01 subs r3, #1
|
|
80041d6: b29a uxth r2, r3
|
|
80041d8: 68fb ldr r3, [r7, #12]
|
|
80041da: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
80041dc: 68fb ldr r3, [r7, #12]
|
|
80041de: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80041e0: b29b uxth r3, r3
|
|
80041e2: 3b01 subs r3, #1
|
|
80041e4: b29a uxth r2, r3
|
|
80041e6: 68fb ldr r3, [r7, #12]
|
|
80041e8: 855a strh r2, [r3, #42] @ 0x2a
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
80041ea: b662 cpsie i
|
|
}
|
|
80041ec: bf00 nop
|
|
|
|
/* Re-enable IRQs */
|
|
__enable_irq();
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
80041ee: 68fb ldr r3, [r7, #12]
|
|
80041f0: 681b ldr r3, [r3, #0]
|
|
80041f2: 691a ldr r2, [r3, #16]
|
|
80041f4: 68fb ldr r3, [r7, #12]
|
|
80041f6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80041f8: b2d2 uxtb r2, r2
|
|
80041fa: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80041fc: 68fb ldr r3, [r7, #12]
|
|
80041fe: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004200: 1c5a adds r2, r3, #1
|
|
8004202: 68fb ldr r3, [r7, #12]
|
|
8004204: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
8004206: 68fb ldr r3, [r7, #12]
|
|
8004208: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800420a: 3b01 subs r3, #1
|
|
800420c: b29a uxth r2, r3
|
|
800420e: 68fb ldr r3, [r7, #12]
|
|
8004210: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8004212: 68fb ldr r3, [r7, #12]
|
|
8004214: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004216: b29b uxth r3, r3
|
|
8004218: 3b01 subs r3, #1
|
|
800421a: b29a uxth r2, r3
|
|
800421c: 68fb ldr r3, [r7, #12]
|
|
800421e: 855a strh r2, [r3, #42] @ 0x2a
|
|
8004220: e04e b.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8004222: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8004224: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
8004226: 68f8 ldr r0, [r7, #12]
|
|
8004228: f000 fb62 bl 80048f0 <I2C_WaitOnRXNEFlagUntilTimeout>
|
|
800422c: 4603 mov r3, r0
|
|
800422e: 2b00 cmp r3, #0
|
|
8004230: d001 beq.n 8004236 <HAL_I2C_Master_Receive+0x412>
|
|
{
|
|
return HAL_ERROR;
|
|
8004232: 2301 movs r3, #1
|
|
8004234: e058 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
8004236: 68fb ldr r3, [r7, #12]
|
|
8004238: 681b ldr r3, [r3, #0]
|
|
800423a: 691a ldr r2, [r3, #16]
|
|
800423c: 68fb ldr r3, [r7, #12]
|
|
800423e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004240: b2d2 uxtb r2, r2
|
|
8004242: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8004244: 68fb ldr r3, [r7, #12]
|
|
8004246: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004248: 1c5a adds r2, r3, #1
|
|
800424a: 68fb ldr r3, [r7, #12]
|
|
800424c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
800424e: 68fb ldr r3, [r7, #12]
|
|
8004250: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004252: 3b01 subs r3, #1
|
|
8004254: b29a uxth r2, r3
|
|
8004256: 68fb ldr r3, [r7, #12]
|
|
8004258: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
800425a: 68fb ldr r3, [r7, #12]
|
|
800425c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800425e: b29b uxth r3, r3
|
|
8004260: 3b01 subs r3, #1
|
|
8004262: b29a uxth r2, r3
|
|
8004264: 68fb ldr r3, [r7, #12]
|
|
8004266: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
|
|
8004268: 68fb ldr r3, [r7, #12]
|
|
800426a: 681b ldr r3, [r3, #0]
|
|
800426c: 695b ldr r3, [r3, #20]
|
|
800426e: f003 0304 and.w r3, r3, #4
|
|
8004272: 2b04 cmp r3, #4
|
|
8004274: d124 bne.n 80042c0 <HAL_I2C_Master_Receive+0x49c>
|
|
{
|
|
|
|
if (hi2c->XferSize == 3U)
|
|
8004276: 68fb ldr r3, [r7, #12]
|
|
8004278: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800427a: 2b03 cmp r3, #3
|
|
800427c: d107 bne.n 800428e <HAL_I2C_Master_Receive+0x46a>
|
|
{
|
|
/* Disable Acknowledge */
|
|
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
800427e: 68fb ldr r3, [r7, #12]
|
|
8004280: 681b ldr r3, [r3, #0]
|
|
8004282: 681a ldr r2, [r3, #0]
|
|
8004284: 68fb ldr r3, [r7, #12]
|
|
8004286: 681b ldr r3, [r3, #0]
|
|
8004288: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800428c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Read data from DR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
|
800428e: 68fb ldr r3, [r7, #12]
|
|
8004290: 681b ldr r3, [r3, #0]
|
|
8004292: 691a ldr r2, [r3, #16]
|
|
8004294: 68fb ldr r3, [r7, #12]
|
|
8004296: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004298: b2d2 uxtb r2, r2
|
|
800429a: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
800429c: 68fb ldr r3, [r7, #12]
|
|
800429e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80042a0: 1c5a adds r2, r3, #1
|
|
80042a2: 68fb ldr r3, [r7, #12]
|
|
80042a4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Update counter */
|
|
hi2c->XferSize--;
|
|
80042a6: 68fb ldr r3, [r7, #12]
|
|
80042a8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80042aa: 3b01 subs r3, #1
|
|
80042ac: b29a uxth r2, r3
|
|
80042ae: 68fb ldr r3, [r7, #12]
|
|
80042b0: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
80042b2: 68fb ldr r3, [r7, #12]
|
|
80042b4: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80042b6: b29b uxth r3, r3
|
|
80042b8: 3b01 subs r3, #1
|
|
80042ba: b29a uxth r2, r3
|
|
80042bc: 68fb ldr r3, [r7, #12]
|
|
80042be: 855a strh r2, [r3, #42] @ 0x2a
|
|
while (hi2c->XferSize > 0U)
|
|
80042c0: 68fb ldr r3, [r7, #12]
|
|
80042c2: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80042c4: 2b00 cmp r3, #0
|
|
80042c6: f47f ae88 bne.w 8003fda <HAL_I2C_Master_Receive+0x1b6>
|
|
}
|
|
}
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80042ca: 68fb ldr r3, [r7, #12]
|
|
80042cc: 2220 movs r2, #32
|
|
80042ce: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80042d2: 68fb ldr r3, [r7, #12]
|
|
80042d4: 2200 movs r2, #0
|
|
80042d6: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80042da: 68fb ldr r3, [r7, #12]
|
|
80042dc: 2200 movs r2, #0
|
|
80042de: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
80042e2: 2300 movs r3, #0
|
|
80042e4: e000 b.n 80042e8 <HAL_I2C_Master_Receive+0x4c4>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80042e6: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80042e8: 4618 mov r0, r3
|
|
80042ea: 3728 adds r7, #40 @ 0x28
|
|
80042ec: 46bd mov sp, r7
|
|
80042ee: bd80 pop {r7, pc}
|
|
80042f0: 00010004 .word 0x00010004
|
|
80042f4: 20000008 .word 0x20000008
|
|
80042f8: 14f8b589 .word 0x14f8b589
|
|
|
|
080042fc <I2C_MasterRequestWrite>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80042fc: b580 push {r7, lr}
|
|
80042fe: b088 sub sp, #32
|
|
8004300: af02 add r7, sp, #8
|
|
8004302: 60f8 str r0, [r7, #12]
|
|
8004304: 607a str r2, [r7, #4]
|
|
8004306: 603b str r3, [r7, #0]
|
|
8004308: 460b mov r3, r1
|
|
800430a: 817b strh r3, [r7, #10]
|
|
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
|
|
uint32_t CurrentXferOptions = hi2c->XferOptions;
|
|
800430c: 68fb ldr r3, [r7, #12]
|
|
800430e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004310: 617b str r3, [r7, #20]
|
|
|
|
/* Generate Start condition if first transfer */
|
|
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
|
|
8004312: 697b ldr r3, [r7, #20]
|
|
8004314: 2b08 cmp r3, #8
|
|
8004316: d006 beq.n 8004326 <I2C_MasterRequestWrite+0x2a>
|
|
8004318: 697b ldr r3, [r7, #20]
|
|
800431a: 2b01 cmp r3, #1
|
|
800431c: d003 beq.n 8004326 <I2C_MasterRequestWrite+0x2a>
|
|
800431e: 697b ldr r3, [r7, #20]
|
|
8004320: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8004324: d108 bne.n 8004338 <I2C_MasterRequestWrite+0x3c>
|
|
{
|
|
/* Generate Start */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
|
|
8004326: 68fb ldr r3, [r7, #12]
|
|
8004328: 681b ldr r3, [r3, #0]
|
|
800432a: 681a ldr r2, [r3, #0]
|
|
800432c: 68fb ldr r3, [r7, #12]
|
|
800432e: 681b ldr r3, [r3, #0]
|
|
8004330: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8004334: 601a str r2, [r3, #0]
|
|
8004336: e00b b.n 8004350 <I2C_MasterRequestWrite+0x54>
|
|
}
|
|
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
|
|
8004338: 68fb ldr r3, [r7, #12]
|
|
800433a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800433c: 2b12 cmp r3, #18
|
|
800433e: d107 bne.n 8004350 <I2C_MasterRequestWrite+0x54>
|
|
{
|
|
/* Generate ReStart */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
|
|
8004340: 68fb ldr r3, [r7, #12]
|
|
8004342: 681b ldr r3, [r3, #0]
|
|
8004344: 681a ldr r2, [r3, #0]
|
|
8004346: 68fb ldr r3, [r7, #12]
|
|
8004348: 681b ldr r3, [r3, #0]
|
|
800434a: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
800434e: 601a str r2, [r3, #0]
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
/* Wait until SB flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004350: 683b ldr r3, [r7, #0]
|
|
8004352: 9300 str r3, [sp, #0]
|
|
8004354: 687b ldr r3, [r7, #4]
|
|
8004356: 2200 movs r2, #0
|
|
8004358: f04f 1101 mov.w r1, #65537 @ 0x10001
|
|
800435c: 68f8 ldr r0, [r7, #12]
|
|
800435e: f000 f91d bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
8004362: 4603 mov r3, r0
|
|
8004364: 2b00 cmp r3, #0
|
|
8004366: d00d beq.n 8004384 <I2C_MasterRequestWrite+0x88>
|
|
{
|
|
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
|
8004368: 68fb ldr r3, [r7, #12]
|
|
800436a: 681b ldr r3, [r3, #0]
|
|
800436c: 681b ldr r3, [r3, #0]
|
|
800436e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004372: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8004376: d103 bne.n 8004380 <I2C_MasterRequestWrite+0x84>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
|
8004378: 68fb ldr r3, [r7, #12]
|
|
800437a: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800437e: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
return HAL_TIMEOUT;
|
|
8004380: 2303 movs r3, #3
|
|
8004382: e035 b.n 80043f0 <I2C_MasterRequestWrite+0xf4>
|
|
}
|
|
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8004384: 68fb ldr r3, [r7, #12]
|
|
8004386: 691b ldr r3, [r3, #16]
|
|
8004388: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
800438c: d108 bne.n 80043a0 <I2C_MasterRequestWrite+0xa4>
|
|
{
|
|
/* Send slave address */
|
|
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
|
|
800438e: 897b ldrh r3, [r7, #10]
|
|
8004390: b2db uxtb r3, r3
|
|
8004392: 461a mov r2, r3
|
|
8004394: 68fb ldr r3, [r7, #12]
|
|
8004396: 681b ldr r3, [r3, #0]
|
|
8004398: f002 02fe and.w r2, r2, #254 @ 0xfe
|
|
800439c: 611a str r2, [r3, #16]
|
|
800439e: e01b b.n 80043d8 <I2C_MasterRequestWrite+0xdc>
|
|
}
|
|
else
|
|
{
|
|
/* Send header of slave address */
|
|
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
|
|
80043a0: 897b ldrh r3, [r7, #10]
|
|
80043a2: 11db asrs r3, r3, #7
|
|
80043a4: b2db uxtb r3, r3
|
|
80043a6: f003 0306 and.w r3, r3, #6
|
|
80043aa: b2db uxtb r3, r3
|
|
80043ac: f063 030f orn r3, r3, #15
|
|
80043b0: b2da uxtb r2, r3
|
|
80043b2: 68fb ldr r3, [r7, #12]
|
|
80043b4: 681b ldr r3, [r3, #0]
|
|
80043b6: 611a str r2, [r3, #16]
|
|
|
|
/* Wait until ADD10 flag is set */
|
|
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
|
|
80043b8: 683b ldr r3, [r7, #0]
|
|
80043ba: 687a ldr r2, [r7, #4]
|
|
80043bc: 490e ldr r1, [pc, #56] @ (80043f8 <I2C_MasterRequestWrite+0xfc>)
|
|
80043be: 68f8 ldr r0, [r7, #12]
|
|
80043c0: f000 f966 bl 8004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>
|
|
80043c4: 4603 mov r3, r0
|
|
80043c6: 2b00 cmp r3, #0
|
|
80043c8: d001 beq.n 80043ce <I2C_MasterRequestWrite+0xd2>
|
|
{
|
|
return HAL_ERROR;
|
|
80043ca: 2301 movs r3, #1
|
|
80043cc: e010 b.n 80043f0 <I2C_MasterRequestWrite+0xf4>
|
|
}
|
|
|
|
/* Send slave address */
|
|
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
|
|
80043ce: 897b ldrh r3, [r7, #10]
|
|
80043d0: b2da uxtb r2, r3
|
|
80043d2: 68fb ldr r3, [r7, #12]
|
|
80043d4: 681b ldr r3, [r3, #0]
|
|
80043d6: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Wait until ADDR flag is set */
|
|
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
|
|
80043d8: 683b ldr r3, [r7, #0]
|
|
80043da: 687a ldr r2, [r7, #4]
|
|
80043dc: 4907 ldr r1, [pc, #28] @ (80043fc <I2C_MasterRequestWrite+0x100>)
|
|
80043de: 68f8 ldr r0, [r7, #12]
|
|
80043e0: f000 f956 bl 8004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>
|
|
80043e4: 4603 mov r3, r0
|
|
80043e6: 2b00 cmp r3, #0
|
|
80043e8: d001 beq.n 80043ee <I2C_MasterRequestWrite+0xf2>
|
|
{
|
|
return HAL_ERROR;
|
|
80043ea: 2301 movs r3, #1
|
|
80043ec: e000 b.n 80043f0 <I2C_MasterRequestWrite+0xf4>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80043ee: 2300 movs r3, #0
|
|
}
|
|
80043f0: 4618 mov r0, r3
|
|
80043f2: 3718 adds r7, #24
|
|
80043f4: 46bd mov sp, r7
|
|
80043f6: bd80 pop {r7, pc}
|
|
80043f8: 00010008 .word 0x00010008
|
|
80043fc: 00010002 .word 0x00010002
|
|
|
|
08004400 <I2C_MasterRequestRead>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8004400: b580 push {r7, lr}
|
|
8004402: b088 sub sp, #32
|
|
8004404: af02 add r7, sp, #8
|
|
8004406: 60f8 str r0, [r7, #12]
|
|
8004408: 607a str r2, [r7, #4]
|
|
800440a: 603b str r3, [r7, #0]
|
|
800440c: 460b mov r3, r1
|
|
800440e: 817b strh r3, [r7, #10]
|
|
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
|
|
uint32_t CurrentXferOptions = hi2c->XferOptions;
|
|
8004410: 68fb ldr r3, [r7, #12]
|
|
8004412: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004414: 617b str r3, [r7, #20]
|
|
|
|
/* Enable Acknowledge */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
|
8004416: 68fb ldr r3, [r7, #12]
|
|
8004418: 681b ldr r3, [r3, #0]
|
|
800441a: 681a ldr r2, [r3, #0]
|
|
800441c: 68fb ldr r3, [r7, #12]
|
|
800441e: 681b ldr r3, [r3, #0]
|
|
8004420: f442 6280 orr.w r2, r2, #1024 @ 0x400
|
|
8004424: 601a str r2, [r3, #0]
|
|
|
|
/* Generate Start condition if first transfer */
|
|
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
|
|
8004426: 697b ldr r3, [r7, #20]
|
|
8004428: 2b08 cmp r3, #8
|
|
800442a: d006 beq.n 800443a <I2C_MasterRequestRead+0x3a>
|
|
800442c: 697b ldr r3, [r7, #20]
|
|
800442e: 2b01 cmp r3, #1
|
|
8004430: d003 beq.n 800443a <I2C_MasterRequestRead+0x3a>
|
|
8004432: 697b ldr r3, [r7, #20]
|
|
8004434: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8004438: d108 bne.n 800444c <I2C_MasterRequestRead+0x4c>
|
|
{
|
|
/* Generate Start */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
|
|
800443a: 68fb ldr r3, [r7, #12]
|
|
800443c: 681b ldr r3, [r3, #0]
|
|
800443e: 681a ldr r2, [r3, #0]
|
|
8004440: 68fb ldr r3, [r7, #12]
|
|
8004442: 681b ldr r3, [r3, #0]
|
|
8004444: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8004448: 601a str r2, [r3, #0]
|
|
800444a: e00b b.n 8004464 <I2C_MasterRequestRead+0x64>
|
|
}
|
|
else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
|
|
800444c: 68fb ldr r3, [r7, #12]
|
|
800444e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004450: 2b11 cmp r3, #17
|
|
8004452: d107 bne.n 8004464 <I2C_MasterRequestRead+0x64>
|
|
{
|
|
/* Generate ReStart */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
|
|
8004454: 68fb ldr r3, [r7, #12]
|
|
8004456: 681b ldr r3, [r3, #0]
|
|
8004458: 681a ldr r2, [r3, #0]
|
|
800445a: 68fb ldr r3, [r7, #12]
|
|
800445c: 681b ldr r3, [r3, #0]
|
|
800445e: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8004462: 601a str r2, [r3, #0]
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
/* Wait until SB flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004464: 683b ldr r3, [r7, #0]
|
|
8004466: 9300 str r3, [sp, #0]
|
|
8004468: 687b ldr r3, [r7, #4]
|
|
800446a: 2200 movs r2, #0
|
|
800446c: f04f 1101 mov.w r1, #65537 @ 0x10001
|
|
8004470: 68f8 ldr r0, [r7, #12]
|
|
8004472: f000 f893 bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
8004476: 4603 mov r3, r0
|
|
8004478: 2b00 cmp r3, #0
|
|
800447a: d00d beq.n 8004498 <I2C_MasterRequestRead+0x98>
|
|
{
|
|
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
|
800447c: 68fb ldr r3, [r7, #12]
|
|
800447e: 681b ldr r3, [r3, #0]
|
|
8004480: 681b ldr r3, [r3, #0]
|
|
8004482: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004486: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
800448a: d103 bne.n 8004494 <I2C_MasterRequestRead+0x94>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
|
800448c: 68fb ldr r3, [r7, #12]
|
|
800448e: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004492: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
return HAL_TIMEOUT;
|
|
8004494: 2303 movs r3, #3
|
|
8004496: e079 b.n 800458c <I2C_MasterRequestRead+0x18c>
|
|
}
|
|
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8004498: 68fb ldr r3, [r7, #12]
|
|
800449a: 691b ldr r3, [r3, #16]
|
|
800449c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
80044a0: d108 bne.n 80044b4 <I2C_MasterRequestRead+0xb4>
|
|
{
|
|
/* Send slave address */
|
|
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
|
|
80044a2: 897b ldrh r3, [r7, #10]
|
|
80044a4: b2db uxtb r3, r3
|
|
80044a6: f043 0301 orr.w r3, r3, #1
|
|
80044aa: b2da uxtb r2, r3
|
|
80044ac: 68fb ldr r3, [r7, #12]
|
|
80044ae: 681b ldr r3, [r3, #0]
|
|
80044b0: 611a str r2, [r3, #16]
|
|
80044b2: e05f b.n 8004574 <I2C_MasterRequestRead+0x174>
|
|
}
|
|
else
|
|
{
|
|
/* Send header of slave address */
|
|
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
|
|
80044b4: 897b ldrh r3, [r7, #10]
|
|
80044b6: 11db asrs r3, r3, #7
|
|
80044b8: b2db uxtb r3, r3
|
|
80044ba: f003 0306 and.w r3, r3, #6
|
|
80044be: b2db uxtb r3, r3
|
|
80044c0: f063 030f orn r3, r3, #15
|
|
80044c4: b2da uxtb r2, r3
|
|
80044c6: 68fb ldr r3, [r7, #12]
|
|
80044c8: 681b ldr r3, [r3, #0]
|
|
80044ca: 611a str r2, [r3, #16]
|
|
|
|
/* Wait until ADD10 flag is set */
|
|
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
|
|
80044cc: 683b ldr r3, [r7, #0]
|
|
80044ce: 687a ldr r2, [r7, #4]
|
|
80044d0: 4930 ldr r1, [pc, #192] @ (8004594 <I2C_MasterRequestRead+0x194>)
|
|
80044d2: 68f8 ldr r0, [r7, #12]
|
|
80044d4: f000 f8dc bl 8004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>
|
|
80044d8: 4603 mov r3, r0
|
|
80044da: 2b00 cmp r3, #0
|
|
80044dc: d001 beq.n 80044e2 <I2C_MasterRequestRead+0xe2>
|
|
{
|
|
return HAL_ERROR;
|
|
80044de: 2301 movs r3, #1
|
|
80044e0: e054 b.n 800458c <I2C_MasterRequestRead+0x18c>
|
|
}
|
|
|
|
/* Send slave address */
|
|
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
|
|
80044e2: 897b ldrh r3, [r7, #10]
|
|
80044e4: b2da uxtb r2, r3
|
|
80044e6: 68fb ldr r3, [r7, #12]
|
|
80044e8: 681b ldr r3, [r3, #0]
|
|
80044ea: 611a str r2, [r3, #16]
|
|
|
|
/* Wait until ADDR flag is set */
|
|
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
|
|
80044ec: 683b ldr r3, [r7, #0]
|
|
80044ee: 687a ldr r2, [r7, #4]
|
|
80044f0: 4929 ldr r1, [pc, #164] @ (8004598 <I2C_MasterRequestRead+0x198>)
|
|
80044f2: 68f8 ldr r0, [r7, #12]
|
|
80044f4: f000 f8cc bl 8004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>
|
|
80044f8: 4603 mov r3, r0
|
|
80044fa: 2b00 cmp r3, #0
|
|
80044fc: d001 beq.n 8004502 <I2C_MasterRequestRead+0x102>
|
|
{
|
|
return HAL_ERROR;
|
|
80044fe: 2301 movs r3, #1
|
|
8004500: e044 b.n 800458c <I2C_MasterRequestRead+0x18c>
|
|
}
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
|
|
8004502: 2300 movs r3, #0
|
|
8004504: 613b str r3, [r7, #16]
|
|
8004506: 68fb ldr r3, [r7, #12]
|
|
8004508: 681b ldr r3, [r3, #0]
|
|
800450a: 695b ldr r3, [r3, #20]
|
|
800450c: 613b str r3, [r7, #16]
|
|
800450e: 68fb ldr r3, [r7, #12]
|
|
8004510: 681b ldr r3, [r3, #0]
|
|
8004512: 699b ldr r3, [r3, #24]
|
|
8004514: 613b str r3, [r7, #16]
|
|
8004516: 693b ldr r3, [r7, #16]
|
|
|
|
/* Generate Restart */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
|
|
8004518: 68fb ldr r3, [r7, #12]
|
|
800451a: 681b ldr r3, [r3, #0]
|
|
800451c: 681a ldr r2, [r3, #0]
|
|
800451e: 68fb ldr r3, [r7, #12]
|
|
8004520: 681b ldr r3, [r3, #0]
|
|
8004522: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8004526: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until SB flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004528: 683b ldr r3, [r7, #0]
|
|
800452a: 9300 str r3, [sp, #0]
|
|
800452c: 687b ldr r3, [r7, #4]
|
|
800452e: 2200 movs r2, #0
|
|
8004530: f04f 1101 mov.w r1, #65537 @ 0x10001
|
|
8004534: 68f8 ldr r0, [r7, #12]
|
|
8004536: f000 f831 bl 800459c <I2C_WaitOnFlagUntilTimeout>
|
|
800453a: 4603 mov r3, r0
|
|
800453c: 2b00 cmp r3, #0
|
|
800453e: d00d beq.n 800455c <I2C_MasterRequestRead+0x15c>
|
|
{
|
|
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
|
8004540: 68fb ldr r3, [r7, #12]
|
|
8004542: 681b ldr r3, [r3, #0]
|
|
8004544: 681b ldr r3, [r3, #0]
|
|
8004546: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800454a: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
800454e: d103 bne.n 8004558 <I2C_MasterRequestRead+0x158>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
|
8004550: 68fb ldr r3, [r7, #12]
|
|
8004552: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004556: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
return HAL_TIMEOUT;
|
|
8004558: 2303 movs r3, #3
|
|
800455a: e017 b.n 800458c <I2C_MasterRequestRead+0x18c>
|
|
}
|
|
|
|
/* Send header of slave address */
|
|
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
|
|
800455c: 897b ldrh r3, [r7, #10]
|
|
800455e: 11db asrs r3, r3, #7
|
|
8004560: b2db uxtb r3, r3
|
|
8004562: f003 0306 and.w r3, r3, #6
|
|
8004566: b2db uxtb r3, r3
|
|
8004568: f063 030e orn r3, r3, #14
|
|
800456c: b2da uxtb r2, r3
|
|
800456e: 68fb ldr r3, [r7, #12]
|
|
8004570: 681b ldr r3, [r3, #0]
|
|
8004572: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Wait until ADDR flag is set */
|
|
if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
|
|
8004574: 683b ldr r3, [r7, #0]
|
|
8004576: 687a ldr r2, [r7, #4]
|
|
8004578: 4907 ldr r1, [pc, #28] @ (8004598 <I2C_MasterRequestRead+0x198>)
|
|
800457a: 68f8 ldr r0, [r7, #12]
|
|
800457c: f000 f888 bl 8004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>
|
|
8004580: 4603 mov r3, r0
|
|
8004582: 2b00 cmp r3, #0
|
|
8004584: d001 beq.n 800458a <I2C_MasterRequestRead+0x18a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004586: 2301 movs r3, #1
|
|
8004588: e000 b.n 800458c <I2C_MasterRequestRead+0x18c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800458a: 2300 movs r3, #0
|
|
}
|
|
800458c: 4618 mov r0, r3
|
|
800458e: 3718 adds r7, #24
|
|
8004590: 46bd mov sp, r7
|
|
8004592: bd80 pop {r7, pc}
|
|
8004594: 00010008 .word 0x00010008
|
|
8004598: 00010002 .word 0x00010002
|
|
|
|
0800459c <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800459c: b580 push {r7, lr}
|
|
800459e: b084 sub sp, #16
|
|
80045a0: af00 add r7, sp, #0
|
|
80045a2: 60f8 str r0, [r7, #12]
|
|
80045a4: 60b9 str r1, [r7, #8]
|
|
80045a6: 603b str r3, [r7, #0]
|
|
80045a8: 4613 mov r3, r2
|
|
80045aa: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
80045ac: e048 b.n 8004640 <I2C_WaitOnFlagUntilTimeout+0xa4>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80045ae: 683b ldr r3, [r7, #0]
|
|
80045b0: f1b3 3fff cmp.w r3, #4294967295
|
|
80045b4: d044 beq.n 8004640 <I2C_WaitOnFlagUntilTimeout+0xa4>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80045b6: f7fe fc4b bl 8002e50 <HAL_GetTick>
|
|
80045ba: 4602 mov r2, r0
|
|
80045bc: 69bb ldr r3, [r7, #24]
|
|
80045be: 1ad3 subs r3, r2, r3
|
|
80045c0: 683a ldr r2, [r7, #0]
|
|
80045c2: 429a cmp r2, r3
|
|
80045c4: d302 bcc.n 80045cc <I2C_WaitOnFlagUntilTimeout+0x30>
|
|
80045c6: 683b ldr r3, [r7, #0]
|
|
80045c8: 2b00 cmp r3, #0
|
|
80045ca: d139 bne.n 8004640 <I2C_WaitOnFlagUntilTimeout+0xa4>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
|
|
80045cc: 68bb ldr r3, [r7, #8]
|
|
80045ce: 0c1b lsrs r3, r3, #16
|
|
80045d0: b2db uxtb r3, r3
|
|
80045d2: 2b01 cmp r3, #1
|
|
80045d4: d10d bne.n 80045f2 <I2C_WaitOnFlagUntilTimeout+0x56>
|
|
80045d6: 68fb ldr r3, [r7, #12]
|
|
80045d8: 681b ldr r3, [r3, #0]
|
|
80045da: 695b ldr r3, [r3, #20]
|
|
80045dc: 43da mvns r2, r3
|
|
80045de: 68bb ldr r3, [r7, #8]
|
|
80045e0: 4013 ands r3, r2
|
|
80045e2: b29b uxth r3, r3
|
|
80045e4: 2b00 cmp r3, #0
|
|
80045e6: bf0c ite eq
|
|
80045e8: 2301 moveq r3, #1
|
|
80045ea: 2300 movne r3, #0
|
|
80045ec: b2db uxtb r3, r3
|
|
80045ee: 461a mov r2, r3
|
|
80045f0: e00c b.n 800460c <I2C_WaitOnFlagUntilTimeout+0x70>
|
|
80045f2: 68fb ldr r3, [r7, #12]
|
|
80045f4: 681b ldr r3, [r3, #0]
|
|
80045f6: 699b ldr r3, [r3, #24]
|
|
80045f8: 43da mvns r2, r3
|
|
80045fa: 68bb ldr r3, [r7, #8]
|
|
80045fc: 4013 ands r3, r2
|
|
80045fe: b29b uxth r3, r3
|
|
8004600: 2b00 cmp r3, #0
|
|
8004602: bf0c ite eq
|
|
8004604: 2301 moveq r3, #1
|
|
8004606: 2300 movne r3, #0
|
|
8004608: b2db uxtb r3, r3
|
|
800460a: 461a mov r2, r3
|
|
800460c: 79fb ldrb r3, [r7, #7]
|
|
800460e: 429a cmp r2, r3
|
|
8004610: d116 bne.n 8004640 <I2C_WaitOnFlagUntilTimeout+0xa4>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004612: 68fb ldr r3, [r7, #12]
|
|
8004614: 2200 movs r2, #0
|
|
8004616: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004618: 68fb ldr r3, [r7, #12]
|
|
800461a: 2220 movs r2, #32
|
|
800461c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004620: 68fb ldr r3, [r7, #12]
|
|
8004622: 2200 movs r2, #0
|
|
8004624: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8004628: 68fb ldr r3, [r7, #12]
|
|
800462a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800462c: f043 0220 orr.w r2, r3, #32
|
|
8004630: 68fb ldr r3, [r7, #12]
|
|
8004632: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004634: 68fb ldr r3, [r7, #12]
|
|
8004636: 2200 movs r2, #0
|
|
8004638: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
800463c: 2301 movs r3, #1
|
|
800463e: e023 b.n 8004688 <I2C_WaitOnFlagUntilTimeout+0xec>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8004640: 68bb ldr r3, [r7, #8]
|
|
8004642: 0c1b lsrs r3, r3, #16
|
|
8004644: b2db uxtb r3, r3
|
|
8004646: 2b01 cmp r3, #1
|
|
8004648: d10d bne.n 8004666 <I2C_WaitOnFlagUntilTimeout+0xca>
|
|
800464a: 68fb ldr r3, [r7, #12]
|
|
800464c: 681b ldr r3, [r3, #0]
|
|
800464e: 695b ldr r3, [r3, #20]
|
|
8004650: 43da mvns r2, r3
|
|
8004652: 68bb ldr r3, [r7, #8]
|
|
8004654: 4013 ands r3, r2
|
|
8004656: b29b uxth r3, r3
|
|
8004658: 2b00 cmp r3, #0
|
|
800465a: bf0c ite eq
|
|
800465c: 2301 moveq r3, #1
|
|
800465e: 2300 movne r3, #0
|
|
8004660: b2db uxtb r3, r3
|
|
8004662: 461a mov r2, r3
|
|
8004664: e00c b.n 8004680 <I2C_WaitOnFlagUntilTimeout+0xe4>
|
|
8004666: 68fb ldr r3, [r7, #12]
|
|
8004668: 681b ldr r3, [r3, #0]
|
|
800466a: 699b ldr r3, [r3, #24]
|
|
800466c: 43da mvns r2, r3
|
|
800466e: 68bb ldr r3, [r7, #8]
|
|
8004670: 4013 ands r3, r2
|
|
8004672: b29b uxth r3, r3
|
|
8004674: 2b00 cmp r3, #0
|
|
8004676: bf0c ite eq
|
|
8004678: 2301 moveq r3, #1
|
|
800467a: 2300 movne r3, #0
|
|
800467c: b2db uxtb r3, r3
|
|
800467e: 461a mov r2, r3
|
|
8004680: 79fb ldrb r3, [r7, #7]
|
|
8004682: 429a cmp r2, r3
|
|
8004684: d093 beq.n 80045ae <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004686: 2300 movs r3, #0
|
|
}
|
|
8004688: 4618 mov r0, r3
|
|
800468a: 3710 adds r7, #16
|
|
800468c: 46bd mov sp, r7
|
|
800468e: bd80 pop {r7, pc}
|
|
|
|
08004690 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8004690: b580 push {r7, lr}
|
|
8004692: b084 sub sp, #16
|
|
8004694: af00 add r7, sp, #0
|
|
8004696: 60f8 str r0, [r7, #12]
|
|
8004698: 60b9 str r1, [r7, #8]
|
|
800469a: 607a str r2, [r7, #4]
|
|
800469c: 603b str r3, [r7, #0]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
|
|
800469e: e071 b.n 8004784 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
|
|
{
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
|
80046a0: 68fb ldr r3, [r7, #12]
|
|
80046a2: 681b ldr r3, [r3, #0]
|
|
80046a4: 695b ldr r3, [r3, #20]
|
|
80046a6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80046aa: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80046ae: d123 bne.n 80046f8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
|
|
{
|
|
/* Generate Stop */
|
|
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
|
80046b0: 68fb ldr r3, [r7, #12]
|
|
80046b2: 681b ldr r3, [r3, #0]
|
|
80046b4: 681a ldr r2, [r3, #0]
|
|
80046b6: 68fb ldr r3, [r7, #12]
|
|
80046b8: 681b ldr r3, [r3, #0]
|
|
80046ba: f442 7200 orr.w r2, r2, #512 @ 0x200
|
|
80046be: 601a str r2, [r3, #0]
|
|
|
|
/* Clear AF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
80046c0: 68fb ldr r3, [r7, #12]
|
|
80046c2: 681b ldr r3, [r3, #0]
|
|
80046c4: f46f 6280 mvn.w r2, #1024 @ 0x400
|
|
80046c8: 615a str r2, [r3, #20]
|
|
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
80046ca: 68fb ldr r3, [r7, #12]
|
|
80046cc: 2200 movs r2, #0
|
|
80046ce: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80046d0: 68fb ldr r3, [r7, #12]
|
|
80046d2: 2220 movs r2, #32
|
|
80046d4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80046d8: 68fb ldr r3, [r7, #12]
|
|
80046da: 2200 movs r2, #0
|
|
80046dc: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
80046e0: 68fb ldr r3, [r7, #12]
|
|
80046e2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80046e4: f043 0204 orr.w r2, r3, #4
|
|
80046e8: 68fb ldr r3, [r7, #12]
|
|
80046ea: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80046ec: 68fb ldr r3, [r7, #12]
|
|
80046ee: 2200 movs r2, #0
|
|
80046f0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
80046f4: 2301 movs r3, #1
|
|
80046f6: e067 b.n 80047c8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80046f8: 687b ldr r3, [r7, #4]
|
|
80046fa: f1b3 3fff cmp.w r3, #4294967295
|
|
80046fe: d041 beq.n 8004784 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004700: f7fe fba6 bl 8002e50 <HAL_GetTick>
|
|
8004704: 4602 mov r2, r0
|
|
8004706: 683b ldr r3, [r7, #0]
|
|
8004708: 1ad3 subs r3, r2, r3
|
|
800470a: 687a ldr r2, [r7, #4]
|
|
800470c: 429a cmp r2, r3
|
|
800470e: d302 bcc.n 8004716 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
|
|
8004710: 687b ldr r3, [r7, #4]
|
|
8004712: 2b00 cmp r3, #0
|
|
8004714: d136 bne.n 8004784 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
|
|
8004716: 68bb ldr r3, [r7, #8]
|
|
8004718: 0c1b lsrs r3, r3, #16
|
|
800471a: b2db uxtb r3, r3
|
|
800471c: 2b01 cmp r3, #1
|
|
800471e: d10c bne.n 800473a <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
|
|
8004720: 68fb ldr r3, [r7, #12]
|
|
8004722: 681b ldr r3, [r3, #0]
|
|
8004724: 695b ldr r3, [r3, #20]
|
|
8004726: 43da mvns r2, r3
|
|
8004728: 68bb ldr r3, [r7, #8]
|
|
800472a: 4013 ands r3, r2
|
|
800472c: b29b uxth r3, r3
|
|
800472e: 2b00 cmp r3, #0
|
|
8004730: bf14 ite ne
|
|
8004732: 2301 movne r3, #1
|
|
8004734: 2300 moveq r3, #0
|
|
8004736: b2db uxtb r3, r3
|
|
8004738: e00b b.n 8004752 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
|
|
800473a: 68fb ldr r3, [r7, #12]
|
|
800473c: 681b ldr r3, [r3, #0]
|
|
800473e: 699b ldr r3, [r3, #24]
|
|
8004740: 43da mvns r2, r3
|
|
8004742: 68bb ldr r3, [r7, #8]
|
|
8004744: 4013 ands r3, r2
|
|
8004746: b29b uxth r3, r3
|
|
8004748: 2b00 cmp r3, #0
|
|
800474a: bf14 ite ne
|
|
800474c: 2301 movne r3, #1
|
|
800474e: 2300 moveq r3, #0
|
|
8004750: b2db uxtb r3, r3
|
|
8004752: 2b00 cmp r3, #0
|
|
8004754: d016 beq.n 8004784 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004756: 68fb ldr r3, [r7, #12]
|
|
8004758: 2200 movs r2, #0
|
|
800475a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800475c: 68fb ldr r3, [r7, #12]
|
|
800475e: 2220 movs r2, #32
|
|
8004760: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004764: 68fb ldr r3, [r7, #12]
|
|
8004766: 2200 movs r2, #0
|
|
8004768: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800476c: 68fb ldr r3, [r7, #12]
|
|
800476e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004770: f043 0220 orr.w r2, r3, #32
|
|
8004774: 68fb ldr r3, [r7, #12]
|
|
8004776: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004778: 68fb ldr r3, [r7, #12]
|
|
800477a: 2200 movs r2, #0
|
|
800477c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8004780: 2301 movs r3, #1
|
|
8004782: e021 b.n 80047c8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
|
|
8004784: 68bb ldr r3, [r7, #8]
|
|
8004786: 0c1b lsrs r3, r3, #16
|
|
8004788: b2db uxtb r3, r3
|
|
800478a: 2b01 cmp r3, #1
|
|
800478c: d10c bne.n 80047a8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
|
|
800478e: 68fb ldr r3, [r7, #12]
|
|
8004790: 681b ldr r3, [r3, #0]
|
|
8004792: 695b ldr r3, [r3, #20]
|
|
8004794: 43da mvns r2, r3
|
|
8004796: 68bb ldr r3, [r7, #8]
|
|
8004798: 4013 ands r3, r2
|
|
800479a: b29b uxth r3, r3
|
|
800479c: 2b00 cmp r3, #0
|
|
800479e: bf14 ite ne
|
|
80047a0: 2301 movne r3, #1
|
|
80047a2: 2300 moveq r3, #0
|
|
80047a4: b2db uxtb r3, r3
|
|
80047a6: e00b b.n 80047c0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
|
|
80047a8: 68fb ldr r3, [r7, #12]
|
|
80047aa: 681b ldr r3, [r3, #0]
|
|
80047ac: 699b ldr r3, [r3, #24]
|
|
80047ae: 43da mvns r2, r3
|
|
80047b0: 68bb ldr r3, [r7, #8]
|
|
80047b2: 4013 ands r3, r2
|
|
80047b4: b29b uxth r3, r3
|
|
80047b6: 2b00 cmp r3, #0
|
|
80047b8: bf14 ite ne
|
|
80047ba: 2301 movne r3, #1
|
|
80047bc: 2300 moveq r3, #0
|
|
80047be: b2db uxtb r3, r3
|
|
80047c0: 2b00 cmp r3, #0
|
|
80047c2: f47f af6d bne.w 80046a0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80047c6: 2300 movs r3, #0
|
|
}
|
|
80047c8: 4618 mov r0, r3
|
|
80047ca: 3710 adds r7, #16
|
|
80047cc: 46bd mov sp, r7
|
|
80047ce: bd80 pop {r7, pc}
|
|
|
|
080047d0 <I2C_WaitOnTXEFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80047d0: b580 push {r7, lr}
|
|
80047d2: b084 sub sp, #16
|
|
80047d4: af00 add r7, sp, #0
|
|
80047d6: 60f8 str r0, [r7, #12]
|
|
80047d8: 60b9 str r1, [r7, #8]
|
|
80047da: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
80047dc: e034 b.n 8004848 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
|
|
80047de: 68f8 ldr r0, [r7, #12]
|
|
80047e0: f000 f8e3 bl 80049aa <I2C_IsAcknowledgeFailed>
|
|
80047e4: 4603 mov r3, r0
|
|
80047e6: 2b00 cmp r3, #0
|
|
80047e8: d001 beq.n 80047ee <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
80047ea: 2301 movs r3, #1
|
|
80047ec: e034 b.n 8004858 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80047ee: 68bb ldr r3, [r7, #8]
|
|
80047f0: f1b3 3fff cmp.w r3, #4294967295
|
|
80047f4: d028 beq.n 8004848 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80047f6: f7fe fb2b bl 8002e50 <HAL_GetTick>
|
|
80047fa: 4602 mov r2, r0
|
|
80047fc: 687b ldr r3, [r7, #4]
|
|
80047fe: 1ad3 subs r3, r2, r3
|
|
8004800: 68ba ldr r2, [r7, #8]
|
|
8004802: 429a cmp r2, r3
|
|
8004804: d302 bcc.n 800480c <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
|
|
8004806: 68bb ldr r3, [r7, #8]
|
|
8004808: 2b00 cmp r3, #0
|
|
800480a: d11d bne.n 8004848 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
|
|
800480c: 68fb ldr r3, [r7, #12]
|
|
800480e: 681b ldr r3, [r3, #0]
|
|
8004810: 695b ldr r3, [r3, #20]
|
|
8004812: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004816: 2b80 cmp r3, #128 @ 0x80
|
|
8004818: d016 beq.n 8004848 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800481a: 68fb ldr r3, [r7, #12]
|
|
800481c: 2200 movs r2, #0
|
|
800481e: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004820: 68fb ldr r3, [r7, #12]
|
|
8004822: 2220 movs r2, #32
|
|
8004824: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004828: 68fb ldr r3, [r7, #12]
|
|
800482a: 2200 movs r2, #0
|
|
800482c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8004830: 68fb ldr r3, [r7, #12]
|
|
8004832: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004834: f043 0220 orr.w r2, r3, #32
|
|
8004838: 68fb ldr r3, [r7, #12]
|
|
800483a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800483c: 68fb ldr r3, [r7, #12]
|
|
800483e: 2200 movs r2, #0
|
|
8004840: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8004844: 2301 movs r3, #1
|
|
8004846: e007 b.n 8004858 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
8004848: 68fb ldr r3, [r7, #12]
|
|
800484a: 681b ldr r3, [r3, #0]
|
|
800484c: 695b ldr r3, [r3, #20]
|
|
800484e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004852: 2b80 cmp r3, #128 @ 0x80
|
|
8004854: d1c3 bne.n 80047de <I2C_WaitOnTXEFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004856: 2300 movs r3, #0
|
|
}
|
|
8004858: 4618 mov r0, r3
|
|
800485a: 3710 adds r7, #16
|
|
800485c: 46bd mov sp, r7
|
|
800485e: bd80 pop {r7, pc}
|
|
|
|
08004860 <I2C_WaitOnBTFFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8004860: b580 push {r7, lr}
|
|
8004862: b084 sub sp, #16
|
|
8004864: af00 add r7, sp, #0
|
|
8004866: 60f8 str r0, [r7, #12]
|
|
8004868: 60b9 str r1, [r7, #8]
|
|
800486a: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
|
|
800486c: e034 b.n 80048d8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
|
|
800486e: 68f8 ldr r0, [r7, #12]
|
|
8004870: f000 f89b bl 80049aa <I2C_IsAcknowledgeFailed>
|
|
8004874: 4603 mov r3, r0
|
|
8004876: 2b00 cmp r3, #0
|
|
8004878: d001 beq.n 800487e <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
800487a: 2301 movs r3, #1
|
|
800487c: e034 b.n 80048e8 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800487e: 68bb ldr r3, [r7, #8]
|
|
8004880: f1b3 3fff cmp.w r3, #4294967295
|
|
8004884: d028 beq.n 80048d8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004886: f7fe fae3 bl 8002e50 <HAL_GetTick>
|
|
800488a: 4602 mov r2, r0
|
|
800488c: 687b ldr r3, [r7, #4]
|
|
800488e: 1ad3 subs r3, r2, r3
|
|
8004890: 68ba ldr r2, [r7, #8]
|
|
8004892: 429a cmp r2, r3
|
|
8004894: d302 bcc.n 800489c <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
|
|
8004896: 68bb ldr r3, [r7, #8]
|
|
8004898: 2b00 cmp r3, #0
|
|
800489a: d11d bne.n 80048d8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
|
|
800489c: 68fb ldr r3, [r7, #12]
|
|
800489e: 681b ldr r3, [r3, #0]
|
|
80048a0: 695b ldr r3, [r3, #20]
|
|
80048a2: f003 0304 and.w r3, r3, #4
|
|
80048a6: 2b04 cmp r3, #4
|
|
80048a8: d016 beq.n 80048d8 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
80048aa: 68fb ldr r3, [r7, #12]
|
|
80048ac: 2200 movs r2, #0
|
|
80048ae: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80048b0: 68fb ldr r3, [r7, #12]
|
|
80048b2: 2220 movs r2, #32
|
|
80048b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80048b8: 68fb ldr r3, [r7, #12]
|
|
80048ba: 2200 movs r2, #0
|
|
80048bc: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80048c0: 68fb ldr r3, [r7, #12]
|
|
80048c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80048c4: f043 0220 orr.w r2, r3, #32
|
|
80048c8: 68fb ldr r3, [r7, #12]
|
|
80048ca: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80048cc: 68fb ldr r3, [r7, #12]
|
|
80048ce: 2200 movs r2, #0
|
|
80048d0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
80048d4: 2301 movs r3, #1
|
|
80048d6: e007 b.n 80048e8 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
|
|
80048d8: 68fb ldr r3, [r7, #12]
|
|
80048da: 681b ldr r3, [r3, #0]
|
|
80048dc: 695b ldr r3, [r3, #20]
|
|
80048de: f003 0304 and.w r3, r3, #4
|
|
80048e2: 2b04 cmp r3, #4
|
|
80048e4: d1c3 bne.n 800486e <I2C_WaitOnBTFFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80048e6: 2300 movs r3, #0
|
|
}
|
|
80048e8: 4618 mov r0, r3
|
|
80048ea: 3710 adds r7, #16
|
|
80048ec: 46bd mov sp, r7
|
|
80048ee: bd80 pop {r7, pc}
|
|
|
|
080048f0 <I2C_WaitOnRXNEFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80048f0: b580 push {r7, lr}
|
|
80048f2: b084 sub sp, #16
|
|
80048f4: af00 add r7, sp, #0
|
|
80048f6: 60f8 str r0, [r7, #12]
|
|
80048f8: 60b9 str r1, [r7, #8]
|
|
80048fa: 607a str r2, [r7, #4]
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
|
80048fc: e049 b.n 8004992 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
|
|
{
|
|
/* Check if a STOPF is detected */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
|
80048fe: 68fb ldr r3, [r7, #12]
|
|
8004900: 681b ldr r3, [r3, #0]
|
|
8004902: 695b ldr r3, [r3, #20]
|
|
8004904: f003 0310 and.w r3, r3, #16
|
|
8004908: 2b10 cmp r3, #16
|
|
800490a: d119 bne.n 8004940 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
800490c: 68fb ldr r3, [r7, #12]
|
|
800490e: 681b ldr r3, [r3, #0]
|
|
8004910: f06f 0210 mvn.w r2, #16
|
|
8004914: 615a str r2, [r3, #20]
|
|
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004916: 68fb ldr r3, [r7, #12]
|
|
8004918: 2200 movs r2, #0
|
|
800491a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800491c: 68fb ldr r3, [r7, #12]
|
|
800491e: 2220 movs r2, #32
|
|
8004920: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004924: 68fb ldr r3, [r7, #12]
|
|
8004926: 2200 movs r2, #0
|
|
8004928: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
|
|
800492c: 68fb ldr r3, [r7, #12]
|
|
800492e: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8004930: 68fb ldr r3, [r7, #12]
|
|
8004932: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004934: 68fb ldr r3, [r7, #12]
|
|
8004936: 2200 movs r2, #0
|
|
8004938: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
800493c: 2301 movs r3, #1
|
|
800493e: e030 b.n 80049a2 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004940: f7fe fa86 bl 8002e50 <HAL_GetTick>
|
|
8004944: 4602 mov r2, r0
|
|
8004946: 687b ldr r3, [r7, #4]
|
|
8004948: 1ad3 subs r3, r2, r3
|
|
800494a: 68ba ldr r2, [r7, #8]
|
|
800494c: 429a cmp r2, r3
|
|
800494e: d302 bcc.n 8004956 <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
|
|
8004950: 68bb ldr r3, [r7, #8]
|
|
8004952: 2b00 cmp r3, #0
|
|
8004954: d11d bne.n 8004992 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
|
|
8004956: 68fb ldr r3, [r7, #12]
|
|
8004958: 681b ldr r3, [r3, #0]
|
|
800495a: 695b ldr r3, [r3, #20]
|
|
800495c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004960: 2b40 cmp r3, #64 @ 0x40
|
|
8004962: d016 beq.n 8004992 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004964: 68fb ldr r3, [r7, #12]
|
|
8004966: 2200 movs r2, #0
|
|
8004968: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800496a: 68fb ldr r3, [r7, #12]
|
|
800496c: 2220 movs r2, #32
|
|
800496e: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004972: 68fb ldr r3, [r7, #12]
|
|
8004974: 2200 movs r2, #0
|
|
8004976: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800497a: 68fb ldr r3, [r7, #12]
|
|
800497c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800497e: f043 0220 orr.w r2, r3, #32
|
|
8004982: 68fb ldr r3, [r7, #12]
|
|
8004984: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004986: 68fb ldr r3, [r7, #12]
|
|
8004988: 2200 movs r2, #0
|
|
800498a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
800498e: 2301 movs r3, #1
|
|
8004990: e007 b.n 80049a2 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
|
8004992: 68fb ldr r3, [r7, #12]
|
|
8004994: 681b ldr r3, [r3, #0]
|
|
8004996: 695b ldr r3, [r3, #20]
|
|
8004998: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800499c: 2b40 cmp r3, #64 @ 0x40
|
|
800499e: d1ae bne.n 80048fe <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80049a0: 2300 movs r3, #0
|
|
}
|
|
80049a2: 4618 mov r0, r3
|
|
80049a4: 3710 adds r7, #16
|
|
80049a6: 46bd mov sp, r7
|
|
80049a8: bd80 pop {r7, pc}
|
|
|
|
080049aa <I2C_IsAcknowledgeFailed>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80049aa: b480 push {r7}
|
|
80049ac: b083 sub sp, #12
|
|
80049ae: af00 add r7, sp, #0
|
|
80049b0: 6078 str r0, [r7, #4]
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
|
80049b2: 687b ldr r3, [r7, #4]
|
|
80049b4: 681b ldr r3, [r3, #0]
|
|
80049b6: 695b ldr r3, [r3, #20]
|
|
80049b8: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80049bc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80049c0: d11b bne.n 80049fa <I2C_IsAcknowledgeFailed+0x50>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
80049c2: 687b ldr r3, [r7, #4]
|
|
80049c4: 681b ldr r3, [r3, #0]
|
|
80049c6: f46f 6280 mvn.w r2, #1024 @ 0x400
|
|
80049ca: 615a str r2, [r3, #20]
|
|
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
80049cc: 687b ldr r3, [r7, #4]
|
|
80049ce: 2200 movs r2, #0
|
|
80049d0: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80049d2: 687b ldr r3, [r7, #4]
|
|
80049d4: 2220 movs r2, #32
|
|
80049d6: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80049da: 687b ldr r3, [r7, #4]
|
|
80049dc: 2200 movs r2, #0
|
|
80049de: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
80049e2: 687b ldr r3, [r7, #4]
|
|
80049e4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80049e6: f043 0204 orr.w r2, r3, #4
|
|
80049ea: 687b ldr r3, [r7, #4]
|
|
80049ec: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80049ee: 687b ldr r3, [r7, #4]
|
|
80049f0: 2200 movs r2, #0
|
|
80049f2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
80049f6: 2301 movs r3, #1
|
|
80049f8: e000 b.n 80049fc <I2C_IsAcknowledgeFailed+0x52>
|
|
}
|
|
return HAL_OK;
|
|
80049fa: 2300 movs r3, #0
|
|
}
|
|
80049fc: 4618 mov r0, r3
|
|
80049fe: 370c adds r7, #12
|
|
8004a00: 46bd mov sp, r7
|
|
8004a02: bc80 pop {r7}
|
|
8004a04: 4770 bx lr
|
|
...
|
|
|
|
08004a08 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8004a08: b580 push {r7, lr}
|
|
8004a0a: b086 sub sp, #24
|
|
8004a0c: af00 add r7, sp, #0
|
|
8004a0e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8004a10: 687b ldr r3, [r7, #4]
|
|
8004a12: 2b00 cmp r3, #0
|
|
8004a14: d101 bne.n 8004a1a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a16: 2301 movs r3, #1
|
|
8004a18: e272 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8004a1a: 687b ldr r3, [r7, #4]
|
|
8004a1c: 681b ldr r3, [r3, #0]
|
|
8004a1e: f003 0301 and.w r3, r3, #1
|
|
8004a22: 2b00 cmp r3, #0
|
|
8004a24: f000 8087 beq.w 8004b36 <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8004a28: 4b92 ldr r3, [pc, #584] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a2a: 685b ldr r3, [r3, #4]
|
|
8004a2c: f003 030c and.w r3, r3, #12
|
|
8004a30: 2b04 cmp r3, #4
|
|
8004a32: d00c beq.n 8004a4e <HAL_RCC_OscConfig+0x46>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8004a34: 4b8f ldr r3, [pc, #572] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a36: 685b ldr r3, [r3, #4]
|
|
8004a38: f003 030c and.w r3, r3, #12
|
|
8004a3c: 2b08 cmp r3, #8
|
|
8004a3e: d112 bne.n 8004a66 <HAL_RCC_OscConfig+0x5e>
|
|
8004a40: 4b8c ldr r3, [pc, #560] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a42: 685b ldr r3, [r3, #4]
|
|
8004a44: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004a48: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004a4c: d10b bne.n 8004a66 <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004a4e: 4b89 ldr r3, [pc, #548] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a50: 681b ldr r3, [r3, #0]
|
|
8004a52: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004a56: 2b00 cmp r3, #0
|
|
8004a58: d06c beq.n 8004b34 <HAL_RCC_OscConfig+0x12c>
|
|
8004a5a: 687b ldr r3, [r7, #4]
|
|
8004a5c: 685b ldr r3, [r3, #4]
|
|
8004a5e: 2b00 cmp r3, #0
|
|
8004a60: d168 bne.n 8004b34 <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a62: 2301 movs r3, #1
|
|
8004a64: e24c b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004a66: 687b ldr r3, [r7, #4]
|
|
8004a68: 685b ldr r3, [r3, #4]
|
|
8004a6a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004a6e: d106 bne.n 8004a7e <HAL_RCC_OscConfig+0x76>
|
|
8004a70: 4b80 ldr r3, [pc, #512] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a72: 681b ldr r3, [r3, #0]
|
|
8004a74: 4a7f ldr r2, [pc, #508] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a76: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004a7a: 6013 str r3, [r2, #0]
|
|
8004a7c: e02e b.n 8004adc <HAL_RCC_OscConfig+0xd4>
|
|
8004a7e: 687b ldr r3, [r7, #4]
|
|
8004a80: 685b ldr r3, [r3, #4]
|
|
8004a82: 2b00 cmp r3, #0
|
|
8004a84: d10c bne.n 8004aa0 <HAL_RCC_OscConfig+0x98>
|
|
8004a86: 4b7b ldr r3, [pc, #492] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a88: 681b ldr r3, [r3, #0]
|
|
8004a8a: 4a7a ldr r2, [pc, #488] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a8c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004a90: 6013 str r3, [r2, #0]
|
|
8004a92: 4b78 ldr r3, [pc, #480] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a94: 681b ldr r3, [r3, #0]
|
|
8004a96: 4a77 ldr r2, [pc, #476] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004a98: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004a9c: 6013 str r3, [r2, #0]
|
|
8004a9e: e01d b.n 8004adc <HAL_RCC_OscConfig+0xd4>
|
|
8004aa0: 687b ldr r3, [r7, #4]
|
|
8004aa2: 685b ldr r3, [r3, #4]
|
|
8004aa4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004aa8: d10c bne.n 8004ac4 <HAL_RCC_OscConfig+0xbc>
|
|
8004aaa: 4b72 ldr r3, [pc, #456] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004aac: 681b ldr r3, [r3, #0]
|
|
8004aae: 4a71 ldr r2, [pc, #452] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004ab0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004ab4: 6013 str r3, [r2, #0]
|
|
8004ab6: 4b6f ldr r3, [pc, #444] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004ab8: 681b ldr r3, [r3, #0]
|
|
8004aba: 4a6e ldr r2, [pc, #440] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004abc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004ac0: 6013 str r3, [r2, #0]
|
|
8004ac2: e00b b.n 8004adc <HAL_RCC_OscConfig+0xd4>
|
|
8004ac4: 4b6b ldr r3, [pc, #428] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004ac6: 681b ldr r3, [r3, #0]
|
|
8004ac8: 4a6a ldr r2, [pc, #424] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004aca: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004ace: 6013 str r3, [r2, #0]
|
|
8004ad0: 4b68 ldr r3, [pc, #416] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004ad2: 681b ldr r3, [r3, #0]
|
|
8004ad4: 4a67 ldr r2, [pc, #412] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004ad6: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004ada: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8004adc: 687b ldr r3, [r7, #4]
|
|
8004ade: 685b ldr r3, [r3, #4]
|
|
8004ae0: 2b00 cmp r3, #0
|
|
8004ae2: d013 beq.n 8004b0c <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004ae4: f7fe f9b4 bl 8002e50 <HAL_GetTick>
|
|
8004ae8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004aea: e008 b.n 8004afe <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004aec: f7fe f9b0 bl 8002e50 <HAL_GetTick>
|
|
8004af0: 4602 mov r2, r0
|
|
8004af2: 693b ldr r3, [r7, #16]
|
|
8004af4: 1ad3 subs r3, r2, r3
|
|
8004af6: 2b64 cmp r3, #100 @ 0x64
|
|
8004af8: d901 bls.n 8004afe <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004afa: 2303 movs r3, #3
|
|
8004afc: e200 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004afe: 4b5d ldr r3, [pc, #372] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b00: 681b ldr r3, [r3, #0]
|
|
8004b02: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004b06: 2b00 cmp r3, #0
|
|
8004b08: d0f0 beq.n 8004aec <HAL_RCC_OscConfig+0xe4>
|
|
8004b0a: e014 b.n 8004b36 <HAL_RCC_OscConfig+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004b0c: f7fe f9a0 bl 8002e50 <HAL_GetTick>
|
|
8004b10: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004b12: e008 b.n 8004b26 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004b14: f7fe f99c bl 8002e50 <HAL_GetTick>
|
|
8004b18: 4602 mov r2, r0
|
|
8004b1a: 693b ldr r3, [r7, #16]
|
|
8004b1c: 1ad3 subs r3, r2, r3
|
|
8004b1e: 2b64 cmp r3, #100 @ 0x64
|
|
8004b20: d901 bls.n 8004b26 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004b22: 2303 movs r3, #3
|
|
8004b24: e1ec b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004b26: 4b53 ldr r3, [pc, #332] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b28: 681b ldr r3, [r3, #0]
|
|
8004b2a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004b2e: 2b00 cmp r3, #0
|
|
8004b30: d1f0 bne.n 8004b14 <HAL_RCC_OscConfig+0x10c>
|
|
8004b32: e000 b.n 8004b36 <HAL_RCC_OscConfig+0x12e>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004b34: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8004b36: 687b ldr r3, [r7, #4]
|
|
8004b38: 681b ldr r3, [r3, #0]
|
|
8004b3a: f003 0302 and.w r3, r3, #2
|
|
8004b3e: 2b00 cmp r3, #0
|
|
8004b40: d063 beq.n 8004c0a <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8004b42: 4b4c ldr r3, [pc, #304] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b44: 685b ldr r3, [r3, #4]
|
|
8004b46: f003 030c and.w r3, r3, #12
|
|
8004b4a: 2b00 cmp r3, #0
|
|
8004b4c: d00b beq.n 8004b66 <HAL_RCC_OscConfig+0x15e>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
8004b4e: 4b49 ldr r3, [pc, #292] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b50: 685b ldr r3, [r3, #4]
|
|
8004b52: f003 030c and.w r3, r3, #12
|
|
8004b56: 2b08 cmp r3, #8
|
|
8004b58: d11c bne.n 8004b94 <HAL_RCC_OscConfig+0x18c>
|
|
8004b5a: 4b46 ldr r3, [pc, #280] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b5c: 685b ldr r3, [r3, #4]
|
|
8004b5e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004b62: 2b00 cmp r3, #0
|
|
8004b64: d116 bne.n 8004b94 <HAL_RCC_OscConfig+0x18c>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004b66: 4b43 ldr r3, [pc, #268] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b68: 681b ldr r3, [r3, #0]
|
|
8004b6a: f003 0302 and.w r3, r3, #2
|
|
8004b6e: 2b00 cmp r3, #0
|
|
8004b70: d005 beq.n 8004b7e <HAL_RCC_OscConfig+0x176>
|
|
8004b72: 687b ldr r3, [r7, #4]
|
|
8004b74: 691b ldr r3, [r3, #16]
|
|
8004b76: 2b01 cmp r3, #1
|
|
8004b78: d001 beq.n 8004b7e <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8004b7a: 2301 movs r3, #1
|
|
8004b7c: e1c0 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004b7e: 4b3d ldr r3, [pc, #244] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b80: 681b ldr r3, [r3, #0]
|
|
8004b82: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004b86: 687b ldr r3, [r7, #4]
|
|
8004b88: 695b ldr r3, [r3, #20]
|
|
8004b8a: 00db lsls r3, r3, #3
|
|
8004b8c: 4939 ldr r1, [pc, #228] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004b8e: 4313 orrs r3, r2
|
|
8004b90: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004b92: e03a b.n 8004c0a <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8004b94: 687b ldr r3, [r7, #4]
|
|
8004b96: 691b ldr r3, [r3, #16]
|
|
8004b98: 2b00 cmp r3, #0
|
|
8004b9a: d020 beq.n 8004bde <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004b9c: 4b36 ldr r3, [pc, #216] @ (8004c78 <HAL_RCC_OscConfig+0x270>)
|
|
8004b9e: 2201 movs r2, #1
|
|
8004ba0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004ba2: f7fe f955 bl 8002e50 <HAL_GetTick>
|
|
8004ba6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004ba8: e008 b.n 8004bbc <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004baa: f7fe f951 bl 8002e50 <HAL_GetTick>
|
|
8004bae: 4602 mov r2, r0
|
|
8004bb0: 693b ldr r3, [r7, #16]
|
|
8004bb2: 1ad3 subs r3, r2, r3
|
|
8004bb4: 2b02 cmp r3, #2
|
|
8004bb6: d901 bls.n 8004bbc <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004bb8: 2303 movs r3, #3
|
|
8004bba: e1a1 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004bbc: 4b2d ldr r3, [pc, #180] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004bbe: 681b ldr r3, [r3, #0]
|
|
8004bc0: f003 0302 and.w r3, r3, #2
|
|
8004bc4: 2b00 cmp r3, #0
|
|
8004bc6: d0f0 beq.n 8004baa <HAL_RCC_OscConfig+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004bc8: 4b2a ldr r3, [pc, #168] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004bca: 681b ldr r3, [r3, #0]
|
|
8004bcc: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004bd0: 687b ldr r3, [r7, #4]
|
|
8004bd2: 695b ldr r3, [r3, #20]
|
|
8004bd4: 00db lsls r3, r3, #3
|
|
8004bd6: 4927 ldr r1, [pc, #156] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004bd8: 4313 orrs r3, r2
|
|
8004bda: 600b str r3, [r1, #0]
|
|
8004bdc: e015 b.n 8004c0a <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8004bde: 4b26 ldr r3, [pc, #152] @ (8004c78 <HAL_RCC_OscConfig+0x270>)
|
|
8004be0: 2200 movs r2, #0
|
|
8004be2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004be4: f7fe f934 bl 8002e50 <HAL_GetTick>
|
|
8004be8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004bea: e008 b.n 8004bfe <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004bec: f7fe f930 bl 8002e50 <HAL_GetTick>
|
|
8004bf0: 4602 mov r2, r0
|
|
8004bf2: 693b ldr r3, [r7, #16]
|
|
8004bf4: 1ad3 subs r3, r2, r3
|
|
8004bf6: 2b02 cmp r3, #2
|
|
8004bf8: d901 bls.n 8004bfe <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004bfa: 2303 movs r3, #3
|
|
8004bfc: e180 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004bfe: 4b1d ldr r3, [pc, #116] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004c00: 681b ldr r3, [r3, #0]
|
|
8004c02: f003 0302 and.w r3, r3, #2
|
|
8004c06: 2b00 cmp r3, #0
|
|
8004c08: d1f0 bne.n 8004bec <HAL_RCC_OscConfig+0x1e4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8004c0a: 687b ldr r3, [r7, #4]
|
|
8004c0c: 681b ldr r3, [r3, #0]
|
|
8004c0e: f003 0308 and.w r3, r3, #8
|
|
8004c12: 2b00 cmp r3, #0
|
|
8004c14: d03a beq.n 8004c8c <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8004c16: 687b ldr r3, [r7, #4]
|
|
8004c18: 699b ldr r3, [r3, #24]
|
|
8004c1a: 2b00 cmp r3, #0
|
|
8004c1c: d019 beq.n 8004c52 <HAL_RCC_OscConfig+0x24a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8004c1e: 4b17 ldr r3, [pc, #92] @ (8004c7c <HAL_RCC_OscConfig+0x274>)
|
|
8004c20: 2201 movs r2, #1
|
|
8004c22: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004c24: f7fe f914 bl 8002e50 <HAL_GetTick>
|
|
8004c28: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004c2a: e008 b.n 8004c3e <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004c2c: f7fe f910 bl 8002e50 <HAL_GetTick>
|
|
8004c30: 4602 mov r2, r0
|
|
8004c32: 693b ldr r3, [r7, #16]
|
|
8004c34: 1ad3 subs r3, r2, r3
|
|
8004c36: 2b02 cmp r3, #2
|
|
8004c38: d901 bls.n 8004c3e <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004c3a: 2303 movs r3, #3
|
|
8004c3c: e160 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004c3e: 4b0d ldr r3, [pc, #52] @ (8004c74 <HAL_RCC_OscConfig+0x26c>)
|
|
8004c40: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004c42: f003 0302 and.w r3, r3, #2
|
|
8004c46: 2b00 cmp r3, #0
|
|
8004c48: d0f0 beq.n 8004c2c <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
should be added.*/
|
|
RCC_Delay(1);
|
|
8004c4a: 2001 movs r0, #1
|
|
8004c4c: f000 fad0 bl 80051f0 <RCC_Delay>
|
|
8004c50: e01c b.n 8004c8c <HAL_RCC_OscConfig+0x284>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8004c52: 4b0a ldr r3, [pc, #40] @ (8004c7c <HAL_RCC_OscConfig+0x274>)
|
|
8004c54: 2200 movs r2, #0
|
|
8004c56: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004c58: f7fe f8fa bl 8002e50 <HAL_GetTick>
|
|
8004c5c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004c5e: e00f b.n 8004c80 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004c60: f7fe f8f6 bl 8002e50 <HAL_GetTick>
|
|
8004c64: 4602 mov r2, r0
|
|
8004c66: 693b ldr r3, [r7, #16]
|
|
8004c68: 1ad3 subs r3, r2, r3
|
|
8004c6a: 2b02 cmp r3, #2
|
|
8004c6c: d908 bls.n 8004c80 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004c6e: 2303 movs r3, #3
|
|
8004c70: e146 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
8004c72: bf00 nop
|
|
8004c74: 40021000 .word 0x40021000
|
|
8004c78: 42420000 .word 0x42420000
|
|
8004c7c: 42420480 .word 0x42420480
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004c80: 4b92 ldr r3, [pc, #584] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004c82: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004c84: f003 0302 and.w r3, r3, #2
|
|
8004c88: 2b00 cmp r3, #0
|
|
8004c8a: d1e9 bne.n 8004c60 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8004c8c: 687b ldr r3, [r7, #4]
|
|
8004c8e: 681b ldr r3, [r3, #0]
|
|
8004c90: f003 0304 and.w r3, r3, #4
|
|
8004c94: 2b00 cmp r3, #0
|
|
8004c96: f000 80a6 beq.w 8004de6 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8004c9a: 2300 movs r3, #0
|
|
8004c9c: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004c9e: 4b8b ldr r3, [pc, #556] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004ca0: 69db ldr r3, [r3, #28]
|
|
8004ca2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004ca6: 2b00 cmp r3, #0
|
|
8004ca8: d10d bne.n 8004cc6 <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004caa: 4b88 ldr r3, [pc, #544] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004cac: 69db ldr r3, [r3, #28]
|
|
8004cae: 4a87 ldr r2, [pc, #540] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004cb0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004cb4: 61d3 str r3, [r2, #28]
|
|
8004cb6: 4b85 ldr r3, [pc, #532] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004cb8: 69db ldr r3, [r3, #28]
|
|
8004cba: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004cbe: 60bb str r3, [r7, #8]
|
|
8004cc0: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8004cc2: 2301 movs r3, #1
|
|
8004cc4: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004cc6: 4b82 ldr r3, [pc, #520] @ (8004ed0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8004cc8: 681b ldr r3, [r3, #0]
|
|
8004cca: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004cce: 2b00 cmp r3, #0
|
|
8004cd0: d118 bne.n 8004d04 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8004cd2: 4b7f ldr r3, [pc, #508] @ (8004ed0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8004cd4: 681b ldr r3, [r3, #0]
|
|
8004cd6: 4a7e ldr r2, [pc, #504] @ (8004ed0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8004cd8: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004cdc: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004cde: f7fe f8b7 bl 8002e50 <HAL_GetTick>
|
|
8004ce2: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004ce4: e008 b.n 8004cf8 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004ce6: f7fe f8b3 bl 8002e50 <HAL_GetTick>
|
|
8004cea: 4602 mov r2, r0
|
|
8004cec: 693b ldr r3, [r7, #16]
|
|
8004cee: 1ad3 subs r3, r2, r3
|
|
8004cf0: 2b64 cmp r3, #100 @ 0x64
|
|
8004cf2: d901 bls.n 8004cf8 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004cf4: 2303 movs r3, #3
|
|
8004cf6: e103 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004cf8: 4b75 ldr r3, [pc, #468] @ (8004ed0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8004cfa: 681b ldr r3, [r3, #0]
|
|
8004cfc: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004d00: 2b00 cmp r3, #0
|
|
8004d02: d0f0 beq.n 8004ce6 <HAL_RCC_OscConfig+0x2de>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8004d04: 687b ldr r3, [r7, #4]
|
|
8004d06: 68db ldr r3, [r3, #12]
|
|
8004d08: 2b01 cmp r3, #1
|
|
8004d0a: d106 bne.n 8004d1a <HAL_RCC_OscConfig+0x312>
|
|
8004d0c: 4b6f ldr r3, [pc, #444] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d0e: 6a1b ldr r3, [r3, #32]
|
|
8004d10: 4a6e ldr r2, [pc, #440] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d12: f043 0301 orr.w r3, r3, #1
|
|
8004d16: 6213 str r3, [r2, #32]
|
|
8004d18: e02d b.n 8004d76 <HAL_RCC_OscConfig+0x36e>
|
|
8004d1a: 687b ldr r3, [r7, #4]
|
|
8004d1c: 68db ldr r3, [r3, #12]
|
|
8004d1e: 2b00 cmp r3, #0
|
|
8004d20: d10c bne.n 8004d3c <HAL_RCC_OscConfig+0x334>
|
|
8004d22: 4b6a ldr r3, [pc, #424] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d24: 6a1b ldr r3, [r3, #32]
|
|
8004d26: 4a69 ldr r2, [pc, #420] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d28: f023 0301 bic.w r3, r3, #1
|
|
8004d2c: 6213 str r3, [r2, #32]
|
|
8004d2e: 4b67 ldr r3, [pc, #412] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d30: 6a1b ldr r3, [r3, #32]
|
|
8004d32: 4a66 ldr r2, [pc, #408] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d34: f023 0304 bic.w r3, r3, #4
|
|
8004d38: 6213 str r3, [r2, #32]
|
|
8004d3a: e01c b.n 8004d76 <HAL_RCC_OscConfig+0x36e>
|
|
8004d3c: 687b ldr r3, [r7, #4]
|
|
8004d3e: 68db ldr r3, [r3, #12]
|
|
8004d40: 2b05 cmp r3, #5
|
|
8004d42: d10c bne.n 8004d5e <HAL_RCC_OscConfig+0x356>
|
|
8004d44: 4b61 ldr r3, [pc, #388] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d46: 6a1b ldr r3, [r3, #32]
|
|
8004d48: 4a60 ldr r2, [pc, #384] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d4a: f043 0304 orr.w r3, r3, #4
|
|
8004d4e: 6213 str r3, [r2, #32]
|
|
8004d50: 4b5e ldr r3, [pc, #376] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d52: 6a1b ldr r3, [r3, #32]
|
|
8004d54: 4a5d ldr r2, [pc, #372] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d56: f043 0301 orr.w r3, r3, #1
|
|
8004d5a: 6213 str r3, [r2, #32]
|
|
8004d5c: e00b b.n 8004d76 <HAL_RCC_OscConfig+0x36e>
|
|
8004d5e: 4b5b ldr r3, [pc, #364] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d60: 6a1b ldr r3, [r3, #32]
|
|
8004d62: 4a5a ldr r2, [pc, #360] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d64: f023 0301 bic.w r3, r3, #1
|
|
8004d68: 6213 str r3, [r2, #32]
|
|
8004d6a: 4b58 ldr r3, [pc, #352] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d6c: 6a1b ldr r3, [r3, #32]
|
|
8004d6e: 4a57 ldr r2, [pc, #348] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d70: f023 0304 bic.w r3, r3, #4
|
|
8004d74: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8004d76: 687b ldr r3, [r7, #4]
|
|
8004d78: 68db ldr r3, [r3, #12]
|
|
8004d7a: 2b00 cmp r3, #0
|
|
8004d7c: d015 beq.n 8004daa <HAL_RCC_OscConfig+0x3a2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004d7e: f7fe f867 bl 8002e50 <HAL_GetTick>
|
|
8004d82: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004d84: e00a b.n 8004d9c <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004d86: f7fe f863 bl 8002e50 <HAL_GetTick>
|
|
8004d8a: 4602 mov r2, r0
|
|
8004d8c: 693b ldr r3, [r7, #16]
|
|
8004d8e: 1ad3 subs r3, r2, r3
|
|
8004d90: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004d94: 4293 cmp r3, r2
|
|
8004d96: d901 bls.n 8004d9c <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004d98: 2303 movs r3, #3
|
|
8004d9a: e0b1 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004d9c: 4b4b ldr r3, [pc, #300] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004d9e: 6a1b ldr r3, [r3, #32]
|
|
8004da0: f003 0302 and.w r3, r3, #2
|
|
8004da4: 2b00 cmp r3, #0
|
|
8004da6: d0ee beq.n 8004d86 <HAL_RCC_OscConfig+0x37e>
|
|
8004da8: e014 b.n 8004dd4 <HAL_RCC_OscConfig+0x3cc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004daa: f7fe f851 bl 8002e50 <HAL_GetTick>
|
|
8004dae: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004db0: e00a b.n 8004dc8 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004db2: f7fe f84d bl 8002e50 <HAL_GetTick>
|
|
8004db6: 4602 mov r2, r0
|
|
8004db8: 693b ldr r3, [r7, #16]
|
|
8004dba: 1ad3 subs r3, r2, r3
|
|
8004dbc: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004dc0: 4293 cmp r3, r2
|
|
8004dc2: d901 bls.n 8004dc8 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004dc4: 2303 movs r3, #3
|
|
8004dc6: e09b b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004dc8: 4b40 ldr r3, [pc, #256] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004dca: 6a1b ldr r3, [r3, #32]
|
|
8004dcc: f003 0302 and.w r3, r3, #2
|
|
8004dd0: 2b00 cmp r3, #0
|
|
8004dd2: d1ee bne.n 8004db2 <HAL_RCC_OscConfig+0x3aa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8004dd4: 7dfb ldrb r3, [r7, #23]
|
|
8004dd6: 2b01 cmp r3, #1
|
|
8004dd8: d105 bne.n 8004de6 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8004dda: 4b3c ldr r3, [pc, #240] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004ddc: 69db ldr r3, [r3, #28]
|
|
8004dde: 4a3b ldr r2, [pc, #236] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004de0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8004de4: 61d3 str r3, [r2, #28]
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8004de6: 687b ldr r3, [r7, #4]
|
|
8004de8: 69db ldr r3, [r3, #28]
|
|
8004dea: 2b00 cmp r3, #0
|
|
8004dec: f000 8087 beq.w 8004efe <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8004df0: 4b36 ldr r3, [pc, #216] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004df2: 685b ldr r3, [r3, #4]
|
|
8004df4: f003 030c and.w r3, r3, #12
|
|
8004df8: 2b08 cmp r3, #8
|
|
8004dfa: d061 beq.n 8004ec0 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8004dfc: 687b ldr r3, [r7, #4]
|
|
8004dfe: 69db ldr r3, [r3, #28]
|
|
8004e00: 2b02 cmp r3, #2
|
|
8004e02: d146 bne.n 8004e92 <HAL_RCC_OscConfig+0x48a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004e04: 4b33 ldr r3, [pc, #204] @ (8004ed4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8004e06: 2200 movs r2, #0
|
|
8004e08: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004e0a: f7fe f821 bl 8002e50 <HAL_GetTick>
|
|
8004e0e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004e10: e008 b.n 8004e24 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004e12: f7fe f81d bl 8002e50 <HAL_GetTick>
|
|
8004e16: 4602 mov r2, r0
|
|
8004e18: 693b ldr r3, [r7, #16]
|
|
8004e1a: 1ad3 subs r3, r2, r3
|
|
8004e1c: 2b02 cmp r3, #2
|
|
8004e1e: d901 bls.n 8004e24 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e20: 2303 movs r3, #3
|
|
8004e22: e06d b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004e24: 4b29 ldr r3, [pc, #164] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e26: 681b ldr r3, [r3, #0]
|
|
8004e28: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004e2c: 2b00 cmp r3, #0
|
|
8004e2e: d1f0 bne.n 8004e12 <HAL_RCC_OscConfig+0x40a>
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
8004e30: 687b ldr r3, [r7, #4]
|
|
8004e32: 6a1b ldr r3, [r3, #32]
|
|
8004e34: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004e38: d108 bne.n 8004e4c <HAL_RCC_OscConfig+0x444>
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8004e3a: 4b24 ldr r3, [pc, #144] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e3c: 685b ldr r3, [r3, #4]
|
|
8004e3e: f423 3200 bic.w r2, r3, #131072 @ 0x20000
|
|
8004e42: 687b ldr r3, [r7, #4]
|
|
8004e44: 689b ldr r3, [r3, #8]
|
|
8004e46: 4921 ldr r1, [pc, #132] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e48: 4313 orrs r3, r2
|
|
8004e4a: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8004e4c: 4b1f ldr r3, [pc, #124] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e4e: 685b ldr r3, [r3, #4]
|
|
8004e50: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
|
|
8004e54: 687b ldr r3, [r7, #4]
|
|
8004e56: 6a19 ldr r1, [r3, #32]
|
|
8004e58: 687b ldr r3, [r7, #4]
|
|
8004e5a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004e5c: 430b orrs r3, r1
|
|
8004e5e: 491b ldr r1, [pc, #108] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e60: 4313 orrs r3, r2
|
|
8004e62: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8004e64: 4b1b ldr r3, [pc, #108] @ (8004ed4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8004e66: 2201 movs r2, #1
|
|
8004e68: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004e6a: f7fd fff1 bl 8002e50 <HAL_GetTick>
|
|
8004e6e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004e70: e008 b.n 8004e84 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004e72: f7fd ffed bl 8002e50 <HAL_GetTick>
|
|
8004e76: 4602 mov r2, r0
|
|
8004e78: 693b ldr r3, [r7, #16]
|
|
8004e7a: 1ad3 subs r3, r2, r3
|
|
8004e7c: 2b02 cmp r3, #2
|
|
8004e7e: d901 bls.n 8004e84 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e80: 2303 movs r3, #3
|
|
8004e82: e03d b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004e84: 4b11 ldr r3, [pc, #68] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004e86: 681b ldr r3, [r3, #0]
|
|
8004e88: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004e8c: 2b00 cmp r3, #0
|
|
8004e8e: d0f0 beq.n 8004e72 <HAL_RCC_OscConfig+0x46a>
|
|
8004e90: e035 b.n 8004efe <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004e92: 4b10 ldr r3, [pc, #64] @ (8004ed4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8004e94: 2200 movs r2, #0
|
|
8004e96: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004e98: f7fd ffda bl 8002e50 <HAL_GetTick>
|
|
8004e9c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004e9e: e008 b.n 8004eb2 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004ea0: f7fd ffd6 bl 8002e50 <HAL_GetTick>
|
|
8004ea4: 4602 mov r2, r0
|
|
8004ea6: 693b ldr r3, [r7, #16]
|
|
8004ea8: 1ad3 subs r3, r2, r3
|
|
8004eaa: 2b02 cmp r3, #2
|
|
8004eac: d901 bls.n 8004eb2 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004eae: 2303 movs r3, #3
|
|
8004eb0: e026 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004eb2: 4b06 ldr r3, [pc, #24] @ (8004ecc <HAL_RCC_OscConfig+0x4c4>)
|
|
8004eb4: 681b ldr r3, [r3, #0]
|
|
8004eb6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004eba: 2b00 cmp r3, #0
|
|
8004ebc: d1f0 bne.n 8004ea0 <HAL_RCC_OscConfig+0x498>
|
|
8004ebe: e01e b.n 8004efe <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8004ec0: 687b ldr r3, [r7, #4]
|
|
8004ec2: 69db ldr r3, [r3, #28]
|
|
8004ec4: 2b01 cmp r3, #1
|
|
8004ec6: d107 bne.n 8004ed8 <HAL_RCC_OscConfig+0x4d0>
|
|
{
|
|
return HAL_ERROR;
|
|
8004ec8: 2301 movs r3, #1
|
|
8004eca: e019 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
8004ecc: 40021000 .word 0x40021000
|
|
8004ed0: 40007000 .word 0x40007000
|
|
8004ed4: 42420060 .word 0x42420060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8004ed8: 4b0b ldr r3, [pc, #44] @ (8004f08 <HAL_RCC_OscConfig+0x500>)
|
|
8004eda: 685b ldr r3, [r3, #4]
|
|
8004edc: 60fb str r3, [r7, #12]
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004ede: 68fb ldr r3, [r7, #12]
|
|
8004ee0: f403 3280 and.w r2, r3, #65536 @ 0x10000
|
|
8004ee4: 687b ldr r3, [r7, #4]
|
|
8004ee6: 6a1b ldr r3, [r3, #32]
|
|
8004ee8: 429a cmp r2, r3
|
|
8004eea: d106 bne.n 8004efa <HAL_RCC_OscConfig+0x4f2>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8004eec: 68fb ldr r3, [r7, #12]
|
|
8004eee: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
|
|
8004ef2: 687b ldr r3, [r7, #4]
|
|
8004ef4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004ef6: 429a cmp r2, r3
|
|
8004ef8: d001 beq.n 8004efe <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
return HAL_ERROR;
|
|
8004efa: 2301 movs r3, #1
|
|
8004efc: e000 b.n 8004f00 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8004efe: 2300 movs r3, #0
|
|
}
|
|
8004f00: 4618 mov r0, r3
|
|
8004f02: 3718 adds r7, #24
|
|
8004f04: 46bd mov sp, r7
|
|
8004f06: bd80 pop {r7, pc}
|
|
8004f08: 40021000 .word 0x40021000
|
|
|
|
08004f0c <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8004f0c: b580 push {r7, lr}
|
|
8004f0e: b084 sub sp, #16
|
|
8004f10: af00 add r7, sp, #0
|
|
8004f12: 6078 str r0, [r7, #4]
|
|
8004f14: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8004f16: 687b ldr r3, [r7, #4]
|
|
8004f18: 2b00 cmp r3, #0
|
|
8004f1a: d101 bne.n 8004f20 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f1c: 2301 movs r3, #1
|
|
8004f1e: e0d0 b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8004f20: 4b6a ldr r3, [pc, #424] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004f22: 681b ldr r3, [r3, #0]
|
|
8004f24: f003 0307 and.w r3, r3, #7
|
|
8004f28: 683a ldr r2, [r7, #0]
|
|
8004f2a: 429a cmp r2, r3
|
|
8004f2c: d910 bls.n 8004f50 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8004f2e: 4b67 ldr r3, [pc, #412] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004f30: 681b ldr r3, [r3, #0]
|
|
8004f32: f023 0207 bic.w r2, r3, #7
|
|
8004f36: 4965 ldr r1, [pc, #404] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004f38: 683b ldr r3, [r7, #0]
|
|
8004f3a: 4313 orrs r3, r2
|
|
8004f3c: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8004f3e: 4b63 ldr r3, [pc, #396] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004f40: 681b ldr r3, [r3, #0]
|
|
8004f42: f003 0307 and.w r3, r3, #7
|
|
8004f46: 683a ldr r2, [r7, #0]
|
|
8004f48: 429a cmp r2, r3
|
|
8004f4a: d001 beq.n 8004f50 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f4c: 2301 movs r3, #1
|
|
8004f4e: e0b8 b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
8004f52: 681b ldr r3, [r3, #0]
|
|
8004f54: f003 0302 and.w r3, r3, #2
|
|
8004f58: 2b00 cmp r3, #0
|
|
8004f5a: d020 beq.n 8004f9e <HAL_RCC_ClockConfig+0x92>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8004f5c: 687b ldr r3, [r7, #4]
|
|
8004f5e: 681b ldr r3, [r3, #0]
|
|
8004f60: f003 0304 and.w r3, r3, #4
|
|
8004f64: 2b00 cmp r3, #0
|
|
8004f66: d005 beq.n 8004f74 <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8004f68: 4b59 ldr r3, [pc, #356] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f6a: 685b ldr r3, [r3, #4]
|
|
8004f6c: 4a58 ldr r2, [pc, #352] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f6e: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
8004f72: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004f74: 687b ldr r3, [r7, #4]
|
|
8004f76: 681b ldr r3, [r3, #0]
|
|
8004f78: f003 0308 and.w r3, r3, #8
|
|
8004f7c: 2b00 cmp r3, #0
|
|
8004f7e: d005 beq.n 8004f8c <HAL_RCC_ClockConfig+0x80>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8004f80: 4b53 ldr r3, [pc, #332] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f82: 685b ldr r3, [r3, #4]
|
|
8004f84: 4a52 ldr r2, [pc, #328] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f86: f443 5360 orr.w r3, r3, #14336 @ 0x3800
|
|
8004f8a: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8004f8c: 4b50 ldr r3, [pc, #320] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f8e: 685b ldr r3, [r3, #4]
|
|
8004f90: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004f94: 687b ldr r3, [r7, #4]
|
|
8004f96: 689b ldr r3, [r3, #8]
|
|
8004f98: 494d ldr r1, [pc, #308] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004f9a: 4313 orrs r3, r2
|
|
8004f9c: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8004f9e: 687b ldr r3, [r7, #4]
|
|
8004fa0: 681b ldr r3, [r3, #0]
|
|
8004fa2: f003 0301 and.w r3, r3, #1
|
|
8004fa6: 2b00 cmp r3, #0
|
|
8004fa8: d040 beq.n 800502c <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8004faa: 687b ldr r3, [r7, #4]
|
|
8004fac: 685b ldr r3, [r3, #4]
|
|
8004fae: 2b01 cmp r3, #1
|
|
8004fb0: d107 bne.n 8004fc2 <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004fb2: 4b47 ldr r3, [pc, #284] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004fb4: 681b ldr r3, [r3, #0]
|
|
8004fb6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004fba: 2b00 cmp r3, #0
|
|
8004fbc: d115 bne.n 8004fea <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004fbe: 2301 movs r3, #1
|
|
8004fc0: e07f b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8004fc2: 687b ldr r3, [r7, #4]
|
|
8004fc4: 685b ldr r3, [r3, #4]
|
|
8004fc6: 2b02 cmp r3, #2
|
|
8004fc8: d107 bne.n 8004fda <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004fca: 4b41 ldr r3, [pc, #260] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004fcc: 681b ldr r3, [r3, #0]
|
|
8004fce: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004fd2: 2b00 cmp r3, #0
|
|
8004fd4: d109 bne.n 8004fea <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004fd6: 2301 movs r3, #1
|
|
8004fd8: e073 b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004fda: 4b3d ldr r3, [pc, #244] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004fdc: 681b ldr r3, [r3, #0]
|
|
8004fde: f003 0302 and.w r3, r3, #2
|
|
8004fe2: 2b00 cmp r3, #0
|
|
8004fe4: d101 bne.n 8004fea <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004fe6: 2301 movs r3, #1
|
|
8004fe8: e06b b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8004fea: 4b39 ldr r3, [pc, #228] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004fec: 685b ldr r3, [r3, #4]
|
|
8004fee: f023 0203 bic.w r2, r3, #3
|
|
8004ff2: 687b ldr r3, [r7, #4]
|
|
8004ff4: 685b ldr r3, [r3, #4]
|
|
8004ff6: 4936 ldr r1, [pc, #216] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004ff8: 4313 orrs r3, r2
|
|
8004ffa: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004ffc: f7fd ff28 bl 8002e50 <HAL_GetTick>
|
|
8005000: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8005002: e00a b.n 800501a <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8005004: f7fd ff24 bl 8002e50 <HAL_GetTick>
|
|
8005008: 4602 mov r2, r0
|
|
800500a: 68fb ldr r3, [r7, #12]
|
|
800500c: 1ad3 subs r3, r2, r3
|
|
800500e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005012: 4293 cmp r3, r2
|
|
8005014: d901 bls.n 800501a <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005016: 2303 movs r3, #3
|
|
8005018: e053 b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800501a: 4b2d ldr r3, [pc, #180] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800501c: 685b ldr r3, [r3, #4]
|
|
800501e: f003 020c and.w r2, r3, #12
|
|
8005022: 687b ldr r3, [r7, #4]
|
|
8005024: 685b ldr r3, [r3, #4]
|
|
8005026: 009b lsls r3, r3, #2
|
|
8005028: 429a cmp r2, r3
|
|
800502a: d1eb bne.n 8005004 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800502c: 4b27 ldr r3, [pc, #156] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
800502e: 681b ldr r3, [r3, #0]
|
|
8005030: f003 0307 and.w r3, r3, #7
|
|
8005034: 683a ldr r2, [r7, #0]
|
|
8005036: 429a cmp r2, r3
|
|
8005038: d210 bcs.n 800505c <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800503a: 4b24 ldr r3, [pc, #144] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
800503c: 681b ldr r3, [r3, #0]
|
|
800503e: f023 0207 bic.w r2, r3, #7
|
|
8005042: 4922 ldr r1, [pc, #136] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8005044: 683b ldr r3, [r7, #0]
|
|
8005046: 4313 orrs r3, r2
|
|
8005048: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800504a: 4b20 ldr r3, [pc, #128] @ (80050cc <HAL_RCC_ClockConfig+0x1c0>)
|
|
800504c: 681b ldr r3, [r3, #0]
|
|
800504e: f003 0307 and.w r3, r3, #7
|
|
8005052: 683a ldr r2, [r7, #0]
|
|
8005054: 429a cmp r2, r3
|
|
8005056: d001 beq.n 800505c <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
8005058: 2301 movs r3, #1
|
|
800505a: e032 b.n 80050c2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
800505c: 687b ldr r3, [r7, #4]
|
|
800505e: 681b ldr r3, [r3, #0]
|
|
8005060: f003 0304 and.w r3, r3, #4
|
|
8005064: 2b00 cmp r3, #0
|
|
8005066: d008 beq.n 800507a <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8005068: 4b19 ldr r3, [pc, #100] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800506a: 685b ldr r3, [r3, #4]
|
|
800506c: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
8005070: 687b ldr r3, [r7, #4]
|
|
8005072: 68db ldr r3, [r3, #12]
|
|
8005074: 4916 ldr r1, [pc, #88] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8005076: 4313 orrs r3, r2
|
|
8005078: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800507a: 687b ldr r3, [r7, #4]
|
|
800507c: 681b ldr r3, [r3, #0]
|
|
800507e: f003 0308 and.w r3, r3, #8
|
|
8005082: 2b00 cmp r3, #0
|
|
8005084: d009 beq.n 800509a <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
8005086: 4b12 ldr r3, [pc, #72] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8005088: 685b ldr r3, [r3, #4]
|
|
800508a: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
800508e: 687b ldr r3, [r7, #4]
|
|
8005090: 691b ldr r3, [r3, #16]
|
|
8005092: 00db lsls r3, r3, #3
|
|
8005094: 490e ldr r1, [pc, #56] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8005096: 4313 orrs r3, r2
|
|
8005098: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
800509a: f000 f821 bl 80050e0 <HAL_RCC_GetSysClockFreq>
|
|
800509e: 4602 mov r2, r0
|
|
80050a0: 4b0b ldr r3, [pc, #44] @ (80050d0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80050a2: 685b ldr r3, [r3, #4]
|
|
80050a4: 091b lsrs r3, r3, #4
|
|
80050a6: f003 030f and.w r3, r3, #15
|
|
80050aa: 490a ldr r1, [pc, #40] @ (80050d4 <HAL_RCC_ClockConfig+0x1c8>)
|
|
80050ac: 5ccb ldrb r3, [r1, r3]
|
|
80050ae: fa22 f303 lsr.w r3, r2, r3
|
|
80050b2: 4a09 ldr r2, [pc, #36] @ (80050d8 <HAL_RCC_ClockConfig+0x1cc>)
|
|
80050b4: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
80050b6: 4b09 ldr r3, [pc, #36] @ (80050dc <HAL_RCC_ClockConfig+0x1d0>)
|
|
80050b8: 681b ldr r3, [r3, #0]
|
|
80050ba: 4618 mov r0, r3
|
|
80050bc: f7fd fe86 bl 8002dcc <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
80050c0: 2300 movs r3, #0
|
|
}
|
|
80050c2: 4618 mov r0, r3
|
|
80050c4: 3710 adds r7, #16
|
|
80050c6: 46bd mov sp, r7
|
|
80050c8: bd80 pop {r7, pc}
|
|
80050ca: bf00 nop
|
|
80050cc: 40022000 .word 0x40022000
|
|
80050d0: 40021000 .word 0x40021000
|
|
80050d4: 08006a68 .word 0x08006a68
|
|
80050d8: 20000008 .word 0x20000008
|
|
80050dc: 2000000c .word 0x2000000c
|
|
|
|
080050e0 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80050e0: b480 push {r7}
|
|
80050e2: b087 sub sp, #28
|
|
80050e4: af00 add r7, sp, #0
|
|
#else
|
|
static const uint8_t aPredivFactorTable[2U] = {1, 2};
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
80050e6: 2300 movs r3, #0
|
|
80050e8: 60fb str r3, [r7, #12]
|
|
80050ea: 2300 movs r3, #0
|
|
80050ec: 60bb str r3, [r7, #8]
|
|
80050ee: 2300 movs r3, #0
|
|
80050f0: 617b str r3, [r7, #20]
|
|
80050f2: 2300 movs r3, #0
|
|
80050f4: 607b str r3, [r7, #4]
|
|
uint32_t sysclockfreq = 0U;
|
|
80050f6: 2300 movs r3, #0
|
|
80050f8: 613b str r3, [r7, #16]
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
80050fa: 4b1e ldr r3, [pc, #120] @ (8005174 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
80050fc: 685b ldr r3, [r3, #4]
|
|
80050fe: 60fb str r3, [r7, #12]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8005100: 68fb ldr r3, [r7, #12]
|
|
8005102: f003 030c and.w r3, r3, #12
|
|
8005106: 2b04 cmp r3, #4
|
|
8005108: d002 beq.n 8005110 <HAL_RCC_GetSysClockFreq+0x30>
|
|
800510a: 2b08 cmp r3, #8
|
|
800510c: d003 beq.n 8005116 <HAL_RCC_GetSysClockFreq+0x36>
|
|
800510e: e027 b.n 8005160 <HAL_RCC_GetSysClockFreq+0x80>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8005110: 4b19 ldr r3, [pc, #100] @ (8005178 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8005112: 613b str r3, [r7, #16]
|
|
break;
|
|
8005114: e027 b.n 8005166 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
8005116: 68fb ldr r3, [r7, #12]
|
|
8005118: 0c9b lsrs r3, r3, #18
|
|
800511a: f003 030f and.w r3, r3, #15
|
|
800511e: 4a17 ldr r2, [pc, #92] @ (800517c <HAL_RCC_GetSysClockFreq+0x9c>)
|
|
8005120: 5cd3 ldrb r3, [r2, r3]
|
|
8005122: 607b str r3, [r7, #4]
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
8005124: 68fb ldr r3, [r7, #12]
|
|
8005126: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800512a: 2b00 cmp r3, #0
|
|
800512c: d010 beq.n 8005150 <HAL_RCC_GetSysClockFreq+0x70>
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
800512e: 4b11 ldr r3, [pc, #68] @ (8005174 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8005130: 685b ldr r3, [r3, #4]
|
|
8005132: 0c5b lsrs r3, r3, #17
|
|
8005134: f003 0301 and.w r3, r3, #1
|
|
8005138: 4a11 ldr r2, [pc, #68] @ (8005180 <HAL_RCC_GetSysClockFreq+0xa0>)
|
|
800513a: 5cd3 ldrb r3, [r2, r3]
|
|
800513c: 60bb str r3, [r7, #8]
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
800513e: 687b ldr r3, [r7, #4]
|
|
8005140: 4a0d ldr r2, [pc, #52] @ (8005178 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8005142: fb03 f202 mul.w r2, r3, r2
|
|
8005146: 68bb ldr r3, [r7, #8]
|
|
8005148: fbb2 f3f3 udiv r3, r2, r3
|
|
800514c: 617b str r3, [r7, #20]
|
|
800514e: e004 b.n 800515a <HAL_RCC_GetSysClockFreq+0x7a>
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
8005150: 687b ldr r3, [r7, #4]
|
|
8005152: 4a0c ldr r2, [pc, #48] @ (8005184 <HAL_RCC_GetSysClockFreq+0xa4>)
|
|
8005154: fb02 f303 mul.w r3, r2, r3
|
|
8005158: 617b str r3, [r7, #20]
|
|
}
|
|
sysclockfreq = pllclk;
|
|
800515a: 697b ldr r3, [r7, #20]
|
|
800515c: 613b str r3, [r7, #16]
|
|
break;
|
|
800515e: e002 b.n 8005166 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8005160: 4b09 ldr r3, [pc, #36] @ (8005188 <HAL_RCC_GetSysClockFreq+0xa8>)
|
|
8005162: 613b str r3, [r7, #16]
|
|
break;
|
|
8005164: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8005166: 693b ldr r3, [r7, #16]
|
|
}
|
|
8005168: 4618 mov r0, r3
|
|
800516a: 371c adds r7, #28
|
|
800516c: 46bd mov sp, r7
|
|
800516e: bc80 pop {r7}
|
|
8005170: 4770 bx lr
|
|
8005172: bf00 nop
|
|
8005174: 40021000 .word 0x40021000
|
|
8005178: 00b71b00 .word 0x00b71b00
|
|
800517c: 08006a80 .word 0x08006a80
|
|
8005180: 08006a90 .word 0x08006a90
|
|
8005184: 003d0900 .word 0x003d0900
|
|
8005188: 007a1200 .word 0x007a1200
|
|
|
|
0800518c <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
800518c: b480 push {r7}
|
|
800518e: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8005190: 4b02 ldr r3, [pc, #8] @ (800519c <HAL_RCC_GetHCLKFreq+0x10>)
|
|
8005192: 681b ldr r3, [r3, #0]
|
|
}
|
|
8005194: 4618 mov r0, r3
|
|
8005196: 46bd mov sp, r7
|
|
8005198: bc80 pop {r7}
|
|
800519a: 4770 bx lr
|
|
800519c: 20000008 .word 0x20000008
|
|
|
|
080051a0 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80051a0: b580 push {r7, lr}
|
|
80051a2: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80051a4: f7ff fff2 bl 800518c <HAL_RCC_GetHCLKFreq>
|
|
80051a8: 4602 mov r2, r0
|
|
80051aa: 4b05 ldr r3, [pc, #20] @ (80051c0 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80051ac: 685b ldr r3, [r3, #4]
|
|
80051ae: 0a1b lsrs r3, r3, #8
|
|
80051b0: f003 0307 and.w r3, r3, #7
|
|
80051b4: 4903 ldr r1, [pc, #12] @ (80051c4 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80051b6: 5ccb ldrb r3, [r1, r3]
|
|
80051b8: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80051bc: 4618 mov r0, r3
|
|
80051be: bd80 pop {r7, pc}
|
|
80051c0: 40021000 .word 0x40021000
|
|
80051c4: 08006a78 .word 0x08006a78
|
|
|
|
080051c8 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80051c8: b580 push {r7, lr}
|
|
80051ca: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80051cc: f7ff ffde bl 800518c <HAL_RCC_GetHCLKFreq>
|
|
80051d0: 4602 mov r2, r0
|
|
80051d2: 4b05 ldr r3, [pc, #20] @ (80051e8 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80051d4: 685b ldr r3, [r3, #4]
|
|
80051d6: 0adb lsrs r3, r3, #11
|
|
80051d8: f003 0307 and.w r3, r3, #7
|
|
80051dc: 4903 ldr r1, [pc, #12] @ (80051ec <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80051de: 5ccb ldrb r3, [r1, r3]
|
|
80051e0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80051e4: 4618 mov r0, r3
|
|
80051e6: bd80 pop {r7, pc}
|
|
80051e8: 40021000 .word 0x40021000
|
|
80051ec: 08006a78 .word 0x08006a78
|
|
|
|
080051f0 <RCC_Delay>:
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
80051f0: b480 push {r7}
|
|
80051f2: b085 sub sp, #20
|
|
80051f4: af00 add r7, sp, #0
|
|
80051f6: 6078 str r0, [r7, #4]
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
80051f8: 4b0a ldr r3, [pc, #40] @ (8005224 <RCC_Delay+0x34>)
|
|
80051fa: 681b ldr r3, [r3, #0]
|
|
80051fc: 4a0a ldr r2, [pc, #40] @ (8005228 <RCC_Delay+0x38>)
|
|
80051fe: fba2 2303 umull r2, r3, r2, r3
|
|
8005202: 0a5b lsrs r3, r3, #9
|
|
8005204: 687a ldr r2, [r7, #4]
|
|
8005206: fb02 f303 mul.w r3, r2, r3
|
|
800520a: 60fb str r3, [r7, #12]
|
|
do
|
|
{
|
|
__NOP();
|
|
800520c: bf00 nop
|
|
}
|
|
while (Delay --);
|
|
800520e: 68fb ldr r3, [r7, #12]
|
|
8005210: 1e5a subs r2, r3, #1
|
|
8005212: 60fa str r2, [r7, #12]
|
|
8005214: 2b00 cmp r3, #0
|
|
8005216: d1f9 bne.n 800520c <RCC_Delay+0x1c>
|
|
}
|
|
8005218: bf00 nop
|
|
800521a: bf00 nop
|
|
800521c: 3714 adds r7, #20
|
|
800521e: 46bd mov sp, r7
|
|
8005220: bc80 pop {r7}
|
|
8005222: 4770 bx lr
|
|
8005224: 20000008 .word 0x20000008
|
|
8005228: 10624dd3 .word 0x10624dd3
|
|
|
|
0800522c <HAL_RCCEx_PeriphCLKConfig>:
|
|
* manually disable it.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
800522c: b580 push {r7, lr}
|
|
800522e: b086 sub sp, #24
|
|
8005230: af00 add r7, sp, #0
|
|
8005232: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U, temp_reg = 0U;
|
|
8005234: 2300 movs r3, #0
|
|
8005236: 613b str r3, [r7, #16]
|
|
8005238: 2300 movs r3, #0
|
|
800523a: 60fb str r3, [r7, #12]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
|
800523c: 687b ldr r3, [r7, #4]
|
|
800523e: 681b ldr r3, [r3, #0]
|
|
8005240: f003 0301 and.w r3, r3, #1
|
|
8005244: 2b00 cmp r3, #0
|
|
8005246: d07d beq.n 8005344 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8005248: 2300 movs r3, #0
|
|
800524a: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|
power domain is done. */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800524c: 4b4f ldr r3, [pc, #316] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800524e: 69db ldr r3, [r3, #28]
|
|
8005250: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005254: 2b00 cmp r3, #0
|
|
8005256: d10d bne.n 8005274 <HAL_RCCEx_PeriphCLKConfig+0x48>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005258: 4b4c ldr r3, [pc, #304] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800525a: 69db ldr r3, [r3, #28]
|
|
800525c: 4a4b ldr r2, [pc, #300] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800525e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005262: 61d3 str r3, [r2, #28]
|
|
8005264: 4b49 ldr r3, [pc, #292] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8005266: 69db ldr r3, [r3, #28]
|
|
8005268: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800526c: 60bb str r3, [r7, #8]
|
|
800526e: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8005270: 2301 movs r3, #1
|
|
8005272: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005274: 4b46 ldr r3, [pc, #280] @ (8005390 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8005276: 681b ldr r3, [r3, #0]
|
|
8005278: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800527c: 2b00 cmp r3, #0
|
|
800527e: d118 bne.n 80052b2 <HAL_RCCEx_PeriphCLKConfig+0x86>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8005280: 4b43 ldr r3, [pc, #268] @ (8005390 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8005282: 681b ldr r3, [r3, #0]
|
|
8005284: 4a42 ldr r2, [pc, #264] @ (8005390 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8005286: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800528a: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800528c: f7fd fde0 bl 8002e50 <HAL_GetTick>
|
|
8005290: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005292: e008 b.n 80052a6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8005294: f7fd fddc bl 8002e50 <HAL_GetTick>
|
|
8005298: 4602 mov r2, r0
|
|
800529a: 693b ldr r3, [r7, #16]
|
|
800529c: 1ad3 subs r3, r2, r3
|
|
800529e: 2b64 cmp r3, #100 @ 0x64
|
|
80052a0: d901 bls.n 80052a6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80052a2: 2303 movs r3, #3
|
|
80052a4: e06d b.n 8005382 <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80052a6: 4b3a ldr r3, [pc, #232] @ (8005390 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
80052a8: 681b ldr r3, [r3, #0]
|
|
80052aa: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80052ae: 2b00 cmp r3, #0
|
|
80052b0: d0f0 beq.n 8005294 <HAL_RCCEx_PeriphCLKConfig+0x68>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80052b2: 4b36 ldr r3, [pc, #216] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80052b4: 6a1b ldr r3, [r3, #32]
|
|
80052b6: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80052ba: 60fb str r3, [r7, #12]
|
|
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
80052bc: 68fb ldr r3, [r7, #12]
|
|
80052be: 2b00 cmp r3, #0
|
|
80052c0: d02e beq.n 8005320 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
80052c2: 687b ldr r3, [r7, #4]
|
|
80052c4: 685b ldr r3, [r3, #4]
|
|
80052c6: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80052ca: 68fa ldr r2, [r7, #12]
|
|
80052cc: 429a cmp r2, r3
|
|
80052ce: d027 beq.n 8005320 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
80052d0: 4b2e ldr r3, [pc, #184] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80052d2: 6a1b ldr r3, [r3, #32]
|
|
80052d4: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80052d8: 60fb str r3, [r7, #12]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80052da: 4b2e ldr r3, [pc, #184] @ (8005394 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
80052dc: 2201 movs r2, #1
|
|
80052de: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80052e0: 4b2c ldr r3, [pc, #176] @ (8005394 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
80052e2: 2200 movs r2, #0
|
|
80052e4: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = temp_reg;
|
|
80052e6: 4a29 ldr r2, [pc, #164] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80052e8: 68fb ldr r3, [r7, #12]
|
|
80052ea: 6213 str r3, [r2, #32]
|
|
|
|
/* Wait for LSERDY if LSE was enabled */
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
|
80052ec: 68fb ldr r3, [r7, #12]
|
|
80052ee: f003 0301 and.w r3, r3, #1
|
|
80052f2: 2b00 cmp r3, #0
|
|
80052f4: d014 beq.n 8005320 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80052f6: f7fd fdab bl 8002e50 <HAL_GetTick>
|
|
80052fa: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80052fc: e00a b.n 8005314 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80052fe: f7fd fda7 bl 8002e50 <HAL_GetTick>
|
|
8005302: 4602 mov r2, r0
|
|
8005304: 693b ldr r3, [r7, #16]
|
|
8005306: 1ad3 subs r3, r2, r3
|
|
8005308: f241 3288 movw r2, #5000 @ 0x1388
|
|
800530c: 4293 cmp r3, r2
|
|
800530e: d901 bls.n 8005314 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005310: 2303 movs r3, #3
|
|
8005312: e036 b.n 8005382 <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005314: 4b1d ldr r3, [pc, #116] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8005316: 6a1b ldr r3, [r3, #32]
|
|
8005318: f003 0302 and.w r3, r3, #2
|
|
800531c: 2b00 cmp r3, #0
|
|
800531e: d0ee beq.n 80052fe <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8005320: 4b1a ldr r3, [pc, #104] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8005322: 6a1b ldr r3, [r3, #32]
|
|
8005324: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8005328: 687b ldr r3, [r7, #4]
|
|
800532a: 685b ldr r3, [r3, #4]
|
|
800532c: 4917 ldr r1, [pc, #92] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800532e: 4313 orrs r3, r2
|
|
8005330: 620b str r3, [r1, #32]
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8005332: 7dfb ldrb r3, [r7, #23]
|
|
8005334: 2b01 cmp r3, #1
|
|
8005336: d105 bne.n 8005344 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005338: 4b14 ldr r3, [pc, #80] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800533a: 69db ldr r3, [r3, #28]
|
|
800533c: 4a13 ldr r2, [pc, #76] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800533e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005342: 61d3 str r3, [r2, #28]
|
|
}
|
|
}
|
|
|
|
/*------------------------------ ADC clock Configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8005344: 687b ldr r3, [r7, #4]
|
|
8005346: 681b ldr r3, [r3, #0]
|
|
8005348: f003 0302 and.w r3, r3, #2
|
|
800534c: 2b00 cmp r3, #0
|
|
800534e: d008 beq.n 8005362 <HAL_RCCEx_PeriphCLKConfig+0x136>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8005350: 4b0e ldr r3, [pc, #56] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8005352: 685b ldr r3, [r3, #4]
|
|
8005354: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
8005358: 687b ldr r3, [r7, #4]
|
|
800535a: 689b ldr r3, [r3, #8]
|
|
800535c: 490b ldr r1, [pc, #44] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800535e: 4313 orrs r3, r2
|
|
8005360: 604b str r3, [r1, #4]
|
|
|
|
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
|
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
|| defined(STM32F105xC) || defined(STM32F107xC)
|
|
/*------------------------------ USB clock Configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
|
8005362: 687b ldr r3, [r7, #4]
|
|
8005364: 681b ldr r3, [r3, #0]
|
|
8005366: f003 0310 and.w r3, r3, #16
|
|
800536a: 2b00 cmp r3, #0
|
|
800536c: d008 beq.n 8005380 <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
|
|
|
|
/* Configure the USB clock source */
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
800536e: 4b07 ldr r3, [pc, #28] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8005370: 685b ldr r3, [r3, #4]
|
|
8005372: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
|
|
8005376: 687b ldr r3, [r7, #4]
|
|
8005378: 68db ldr r3, [r3, #12]
|
|
800537a: 4904 ldr r1, [pc, #16] @ (800538c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800537c: 4313 orrs r3, r2
|
|
800537e: 604b str r3, [r1, #4]
|
|
}
|
|
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
|
|
|
return HAL_OK;
|
|
8005380: 2300 movs r3, #0
|
|
}
|
|
8005382: 4618 mov r0, r3
|
|
8005384: 3718 adds r7, #24
|
|
8005386: 46bd mov sp, r7
|
|
8005388: bd80 pop {r7, pc}
|
|
800538a: bf00 nop
|
|
800538c: 40021000 .word 0x40021000
|
|
8005390: 40007000 .word 0x40007000
|
|
8005394: 42420440 .word 0x42420440
|
|
|
|
08005398 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005398: b580 push {r7, lr}
|
|
800539a: b082 sub sp, #8
|
|
800539c: af00 add r7, sp, #0
|
|
800539e: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80053a0: 687b ldr r3, [r7, #4]
|
|
80053a2: 2b00 cmp r3, #0
|
|
80053a4: d101 bne.n 80053aa <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80053a6: 2301 movs r3, #1
|
|
80053a8: e041 b.n 800542e <HAL_TIM_Base_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80053aa: 687b ldr r3, [r7, #4]
|
|
80053ac: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80053b0: b2db uxtb r3, r3
|
|
80053b2: 2b00 cmp r3, #0
|
|
80053b4: d106 bne.n 80053c4 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80053b6: 687b ldr r3, [r7, #4]
|
|
80053b8: 2200 movs r2, #0
|
|
80053ba: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
80053be: 6878 ldr r0, [r7, #4]
|
|
80053c0: f7fd fc24 bl 8002c0c <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80053c4: 687b ldr r3, [r7, #4]
|
|
80053c6: 2202 movs r2, #2
|
|
80053c8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80053cc: 687b ldr r3, [r7, #4]
|
|
80053ce: 681a ldr r2, [r3, #0]
|
|
80053d0: 687b ldr r3, [r7, #4]
|
|
80053d2: 3304 adds r3, #4
|
|
80053d4: 4619 mov r1, r3
|
|
80053d6: 4610 mov r0, r2
|
|
80053d8: f000 fa5c bl 8005894 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80053dc: 687b ldr r3, [r7, #4]
|
|
80053de: 2201 movs r2, #1
|
|
80053e0: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80053e4: 687b ldr r3, [r7, #4]
|
|
80053e6: 2201 movs r2, #1
|
|
80053e8: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80053ec: 687b ldr r3, [r7, #4]
|
|
80053ee: 2201 movs r2, #1
|
|
80053f0: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80053f4: 687b ldr r3, [r7, #4]
|
|
80053f6: 2201 movs r2, #1
|
|
80053f8: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80053fc: 687b ldr r3, [r7, #4]
|
|
80053fe: 2201 movs r2, #1
|
|
8005400: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005404: 687b ldr r3, [r7, #4]
|
|
8005406: 2201 movs r2, #1
|
|
8005408: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
800540c: 687b ldr r3, [r7, #4]
|
|
800540e: 2201 movs r2, #1
|
|
8005410: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8005414: 687b ldr r3, [r7, #4]
|
|
8005416: 2201 movs r2, #1
|
|
8005418: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800541c: 687b ldr r3, [r7, #4]
|
|
800541e: 2201 movs r2, #1
|
|
8005420: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005424: 687b ldr r3, [r7, #4]
|
|
8005426: 2201 movs r2, #1
|
|
8005428: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
800542c: 2300 movs r3, #0
|
|
}
|
|
800542e: 4618 mov r0, r3
|
|
8005430: 3708 adds r7, #8
|
|
8005432: 46bd mov sp, r7
|
|
8005434: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005438 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005438: b480 push {r7}
|
|
800543a: b085 sub sp, #20
|
|
800543c: af00 add r7, sp, #0
|
|
800543e: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
8005440: 687b ldr r3, [r7, #4]
|
|
8005442: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8005446: b2db uxtb r3, r3
|
|
8005448: 2b01 cmp r3, #1
|
|
800544a: d001 beq.n 8005450 <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
800544c: 2301 movs r3, #1
|
|
800544e: e03a b.n 80054c6 <HAL_TIM_Base_Start_IT+0x8e>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005450: 687b ldr r3, [r7, #4]
|
|
8005452: 2202 movs r2, #2
|
|
8005454: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
8005458: 687b ldr r3, [r7, #4]
|
|
800545a: 681b ldr r3, [r3, #0]
|
|
800545c: 68da ldr r2, [r3, #12]
|
|
800545e: 687b ldr r3, [r7, #4]
|
|
8005460: 681b ldr r3, [r3, #0]
|
|
8005462: f042 0201 orr.w r2, r2, #1
|
|
8005466: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005468: 687b ldr r3, [r7, #4]
|
|
800546a: 681b ldr r3, [r3, #0]
|
|
800546c: 4a18 ldr r2, [pc, #96] @ (80054d0 <HAL_TIM_Base_Start_IT+0x98>)
|
|
800546e: 4293 cmp r3, r2
|
|
8005470: d00e beq.n 8005490 <HAL_TIM_Base_Start_IT+0x58>
|
|
8005472: 687b ldr r3, [r7, #4]
|
|
8005474: 681b ldr r3, [r3, #0]
|
|
8005476: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800547a: d009 beq.n 8005490 <HAL_TIM_Base_Start_IT+0x58>
|
|
800547c: 687b ldr r3, [r7, #4]
|
|
800547e: 681b ldr r3, [r3, #0]
|
|
8005480: 4a14 ldr r2, [pc, #80] @ (80054d4 <HAL_TIM_Base_Start_IT+0x9c>)
|
|
8005482: 4293 cmp r3, r2
|
|
8005484: d004 beq.n 8005490 <HAL_TIM_Base_Start_IT+0x58>
|
|
8005486: 687b ldr r3, [r7, #4]
|
|
8005488: 681b ldr r3, [r3, #0]
|
|
800548a: 4a13 ldr r2, [pc, #76] @ (80054d8 <HAL_TIM_Base_Start_IT+0xa0>)
|
|
800548c: 4293 cmp r3, r2
|
|
800548e: d111 bne.n 80054b4 <HAL_TIM_Base_Start_IT+0x7c>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8005490: 687b ldr r3, [r7, #4]
|
|
8005492: 681b ldr r3, [r3, #0]
|
|
8005494: 689b ldr r3, [r3, #8]
|
|
8005496: f003 0307 and.w r3, r3, #7
|
|
800549a: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800549c: 68fb ldr r3, [r7, #12]
|
|
800549e: 2b06 cmp r3, #6
|
|
80054a0: d010 beq.n 80054c4 <HAL_TIM_Base_Start_IT+0x8c>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
80054a2: 687b ldr r3, [r7, #4]
|
|
80054a4: 681b ldr r3, [r3, #0]
|
|
80054a6: 681a ldr r2, [r3, #0]
|
|
80054a8: 687b ldr r3, [r7, #4]
|
|
80054aa: 681b ldr r3, [r3, #0]
|
|
80054ac: f042 0201 orr.w r2, r2, #1
|
|
80054b0: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
80054b2: e007 b.n 80054c4 <HAL_TIM_Base_Start_IT+0x8c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
80054b4: 687b ldr r3, [r7, #4]
|
|
80054b6: 681b ldr r3, [r3, #0]
|
|
80054b8: 681a ldr r2, [r3, #0]
|
|
80054ba: 687b ldr r3, [r7, #4]
|
|
80054bc: 681b ldr r3, [r3, #0]
|
|
80054be: f042 0201 orr.w r2, r2, #1
|
|
80054c2: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80054c4: 2300 movs r3, #0
|
|
}
|
|
80054c6: 4618 mov r0, r3
|
|
80054c8: 3714 adds r7, #20
|
|
80054ca: 46bd mov sp, r7
|
|
80054cc: bc80 pop {r7}
|
|
80054ce: 4770 bx lr
|
|
80054d0: 40012c00 .word 0x40012c00
|
|
80054d4: 40000400 .word 0x40000400
|
|
80054d8: 40000800 .word 0x40000800
|
|
|
|
080054dc <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
80054dc: b580 push {r7, lr}
|
|
80054de: b084 sub sp, #16
|
|
80054e0: af00 add r7, sp, #0
|
|
80054e2: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
80054e4: 687b ldr r3, [r7, #4]
|
|
80054e6: 681b ldr r3, [r3, #0]
|
|
80054e8: 68db ldr r3, [r3, #12]
|
|
80054ea: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
80054ec: 687b ldr r3, [r7, #4]
|
|
80054ee: 681b ldr r3, [r3, #0]
|
|
80054f0: 691b ldr r3, [r3, #16]
|
|
80054f2: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
80054f4: 68bb ldr r3, [r7, #8]
|
|
80054f6: f003 0302 and.w r3, r3, #2
|
|
80054fa: 2b00 cmp r3, #0
|
|
80054fc: d020 beq.n 8005540 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
80054fe: 68fb ldr r3, [r7, #12]
|
|
8005500: f003 0302 and.w r3, r3, #2
|
|
8005504: 2b00 cmp r3, #0
|
|
8005506: d01b beq.n 8005540 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
8005508: 687b ldr r3, [r7, #4]
|
|
800550a: 681b ldr r3, [r3, #0]
|
|
800550c: f06f 0202 mvn.w r2, #2
|
|
8005510: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
8005512: 687b ldr r3, [r7, #4]
|
|
8005514: 2201 movs r2, #1
|
|
8005516: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
8005518: 687b ldr r3, [r7, #4]
|
|
800551a: 681b ldr r3, [r3, #0]
|
|
800551c: 699b ldr r3, [r3, #24]
|
|
800551e: f003 0303 and.w r3, r3, #3
|
|
8005522: 2b00 cmp r3, #0
|
|
8005524: d003 beq.n 800552e <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005526: 6878 ldr r0, [r7, #4]
|
|
8005528: f000 f998 bl 800585c <HAL_TIM_IC_CaptureCallback>
|
|
800552c: e005 b.n 800553a <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800552e: 6878 ldr r0, [r7, #4]
|
|
8005530: f000 f98b bl 800584a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005534: 6878 ldr r0, [r7, #4]
|
|
8005536: f000 f99a bl 800586e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800553a: 687b ldr r3, [r7, #4]
|
|
800553c: 2200 movs r2, #0
|
|
800553e: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
8005540: 68bb ldr r3, [r7, #8]
|
|
8005542: f003 0304 and.w r3, r3, #4
|
|
8005546: 2b00 cmp r3, #0
|
|
8005548: d020 beq.n 800558c <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
800554a: 68fb ldr r3, [r7, #12]
|
|
800554c: f003 0304 and.w r3, r3, #4
|
|
8005550: 2b00 cmp r3, #0
|
|
8005552: d01b beq.n 800558c <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8005554: 687b ldr r3, [r7, #4]
|
|
8005556: 681b ldr r3, [r3, #0]
|
|
8005558: f06f 0204 mvn.w r2, #4
|
|
800555c: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800555e: 687b ldr r3, [r7, #4]
|
|
8005560: 2202 movs r2, #2
|
|
8005562: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8005564: 687b ldr r3, [r7, #4]
|
|
8005566: 681b ldr r3, [r3, #0]
|
|
8005568: 699b ldr r3, [r3, #24]
|
|
800556a: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800556e: 2b00 cmp r3, #0
|
|
8005570: d003 beq.n 800557a <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005572: 6878 ldr r0, [r7, #4]
|
|
8005574: f000 f972 bl 800585c <HAL_TIM_IC_CaptureCallback>
|
|
8005578: e005 b.n 8005586 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800557a: 6878 ldr r0, [r7, #4]
|
|
800557c: f000 f965 bl 800584a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005580: 6878 ldr r0, [r7, #4]
|
|
8005582: f000 f974 bl 800586e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005586: 687b ldr r3, [r7, #4]
|
|
8005588: 2200 movs r2, #0
|
|
800558a: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
800558c: 68bb ldr r3, [r7, #8]
|
|
800558e: f003 0308 and.w r3, r3, #8
|
|
8005592: 2b00 cmp r3, #0
|
|
8005594: d020 beq.n 80055d8 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8005596: 68fb ldr r3, [r7, #12]
|
|
8005598: f003 0308 and.w r3, r3, #8
|
|
800559c: 2b00 cmp r3, #0
|
|
800559e: d01b beq.n 80055d8 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
80055a0: 687b ldr r3, [r7, #4]
|
|
80055a2: 681b ldr r3, [r3, #0]
|
|
80055a4: f06f 0208 mvn.w r2, #8
|
|
80055a8: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
80055aa: 687b ldr r3, [r7, #4]
|
|
80055ac: 2204 movs r2, #4
|
|
80055ae: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
80055b0: 687b ldr r3, [r7, #4]
|
|
80055b2: 681b ldr r3, [r3, #0]
|
|
80055b4: 69db ldr r3, [r3, #28]
|
|
80055b6: f003 0303 and.w r3, r3, #3
|
|
80055ba: 2b00 cmp r3, #0
|
|
80055bc: d003 beq.n 80055c6 <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80055be: 6878 ldr r0, [r7, #4]
|
|
80055c0: f000 f94c bl 800585c <HAL_TIM_IC_CaptureCallback>
|
|
80055c4: e005 b.n 80055d2 <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80055c6: 6878 ldr r0, [r7, #4]
|
|
80055c8: f000 f93f bl 800584a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80055cc: 6878 ldr r0, [r7, #4]
|
|
80055ce: f000 f94e bl 800586e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80055d2: 687b ldr r3, [r7, #4]
|
|
80055d4: 2200 movs r2, #0
|
|
80055d6: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
80055d8: 68bb ldr r3, [r7, #8]
|
|
80055da: f003 0310 and.w r3, r3, #16
|
|
80055de: 2b00 cmp r3, #0
|
|
80055e0: d020 beq.n 8005624 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
80055e2: 68fb ldr r3, [r7, #12]
|
|
80055e4: f003 0310 and.w r3, r3, #16
|
|
80055e8: 2b00 cmp r3, #0
|
|
80055ea: d01b beq.n 8005624 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
80055ec: 687b ldr r3, [r7, #4]
|
|
80055ee: 681b ldr r3, [r3, #0]
|
|
80055f0: f06f 0210 mvn.w r2, #16
|
|
80055f4: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
80055f6: 687b ldr r3, [r7, #4]
|
|
80055f8: 2208 movs r2, #8
|
|
80055fa: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
80055fc: 687b ldr r3, [r7, #4]
|
|
80055fe: 681b ldr r3, [r3, #0]
|
|
8005600: 69db ldr r3, [r3, #28]
|
|
8005602: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005606: 2b00 cmp r3, #0
|
|
8005608: d003 beq.n 8005612 <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800560a: 6878 ldr r0, [r7, #4]
|
|
800560c: f000 f926 bl 800585c <HAL_TIM_IC_CaptureCallback>
|
|
8005610: e005 b.n 800561e <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005612: 6878 ldr r0, [r7, #4]
|
|
8005614: f000 f919 bl 800584a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005618: 6878 ldr r0, [r7, #4]
|
|
800561a: f000 f928 bl 800586e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800561e: 687b ldr r3, [r7, #4]
|
|
8005620: 2200 movs r2, #0
|
|
8005622: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
8005624: 68bb ldr r3, [r7, #8]
|
|
8005626: f003 0301 and.w r3, r3, #1
|
|
800562a: 2b00 cmp r3, #0
|
|
800562c: d00c beq.n 8005648 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
800562e: 68fb ldr r3, [r7, #12]
|
|
8005630: f003 0301 and.w r3, r3, #1
|
|
8005634: 2b00 cmp r3, #0
|
|
8005636: d007 beq.n 8005648 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8005638: 687b ldr r3, [r7, #4]
|
|
800563a: 681b ldr r3, [r3, #0]
|
|
800563c: f06f 0201 mvn.w r2, #1
|
|
8005640: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8005642: 6878 ldr r0, [r7, #4]
|
|
8005644: f7fd f90a bl 800285c <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
|
8005648: 68bb ldr r3, [r7, #8]
|
|
800564a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800564e: 2b00 cmp r3, #0
|
|
8005650: d00c beq.n 800566c <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8005652: 68fb ldr r3, [r7, #12]
|
|
8005654: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005658: 2b00 cmp r3, #0
|
|
800565a: d007 beq.n 800566c <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
|
|
800565c: 687b ldr r3, [r7, #4]
|
|
800565e: 681b ldr r3, [r3, #0]
|
|
8005660: f06f 0280 mvn.w r2, #128 @ 0x80
|
|
8005664: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8005666: 6878 ldr r0, [r7, #4]
|
|
8005668: f000 fa7f bl 8005b6a <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
800566c: 68bb ldr r3, [r7, #8]
|
|
800566e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005672: 2b00 cmp r3, #0
|
|
8005674: d00c beq.n 8005690 <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8005676: 68fb ldr r3, [r7, #12]
|
|
8005678: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800567c: 2b00 cmp r3, #0
|
|
800567e: d007 beq.n 8005690 <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8005680: 687b ldr r3, [r7, #4]
|
|
8005682: 681b ldr r3, [r3, #0]
|
|
8005684: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8005688: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
800568a: 6878 ldr r0, [r7, #4]
|
|
800568c: f000 f8f8 bl 8005880 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8005690: 68bb ldr r3, [r7, #8]
|
|
8005692: f003 0320 and.w r3, r3, #32
|
|
8005696: 2b00 cmp r3, #0
|
|
8005698: d00c beq.n 80056b4 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
800569a: 68fb ldr r3, [r7, #12]
|
|
800569c: f003 0320 and.w r3, r3, #32
|
|
80056a0: 2b00 cmp r3, #0
|
|
80056a2: d007 beq.n 80056b4 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
80056a4: 687b ldr r3, [r7, #4]
|
|
80056a6: 681b ldr r3, [r3, #0]
|
|
80056a8: f06f 0220 mvn.w r2, #32
|
|
80056ac: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
80056ae: 6878 ldr r0, [r7, #4]
|
|
80056b0: f000 fa52 bl 8005b58 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
80056b4: bf00 nop
|
|
80056b6: 3710 adds r7, #16
|
|
80056b8: 46bd mov sp, r7
|
|
80056ba: bd80 pop {r7, pc}
|
|
|
|
080056bc <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
80056bc: b580 push {r7, lr}
|
|
80056be: b084 sub sp, #16
|
|
80056c0: af00 add r7, sp, #0
|
|
80056c2: 6078 str r0, [r7, #4]
|
|
80056c4: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80056c6: 2300 movs r3, #0
|
|
80056c8: 73fb strb r3, [r7, #15]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80056ca: 687b ldr r3, [r7, #4]
|
|
80056cc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80056d0: 2b01 cmp r3, #1
|
|
80056d2: d101 bne.n 80056d8 <HAL_TIM_ConfigClockSource+0x1c>
|
|
80056d4: 2302 movs r3, #2
|
|
80056d6: e0b4 b.n 8005842 <HAL_TIM_ConfigClockSource+0x186>
|
|
80056d8: 687b ldr r3, [r7, #4]
|
|
80056da: 2201 movs r2, #1
|
|
80056dc: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80056e0: 687b ldr r3, [r7, #4]
|
|
80056e2: 2202 movs r2, #2
|
|
80056e4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80056e8: 687b ldr r3, [r7, #4]
|
|
80056ea: 681b ldr r3, [r3, #0]
|
|
80056ec: 689b ldr r3, [r3, #8]
|
|
80056ee: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
80056f0: 68bb ldr r3, [r7, #8]
|
|
80056f2: f023 0377 bic.w r3, r3, #119 @ 0x77
|
|
80056f6: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
80056f8: 68bb ldr r3, [r7, #8]
|
|
80056fa: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
80056fe: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005700: 687b ldr r3, [r7, #4]
|
|
8005702: 681b ldr r3, [r3, #0]
|
|
8005704: 68ba ldr r2, [r7, #8]
|
|
8005706: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
8005708: 683b ldr r3, [r7, #0]
|
|
800570a: 681b ldr r3, [r3, #0]
|
|
800570c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005710: d03e beq.n 8005790 <HAL_TIM_ConfigClockSource+0xd4>
|
|
8005712: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005716: f200 8087 bhi.w 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
800571a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800571e: f000 8086 beq.w 800582e <HAL_TIM_ConfigClockSource+0x172>
|
|
8005722: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005726: d87f bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005728: 2b70 cmp r3, #112 @ 0x70
|
|
800572a: d01a beq.n 8005762 <HAL_TIM_ConfigClockSource+0xa6>
|
|
800572c: 2b70 cmp r3, #112 @ 0x70
|
|
800572e: d87b bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005730: 2b60 cmp r3, #96 @ 0x60
|
|
8005732: d050 beq.n 80057d6 <HAL_TIM_ConfigClockSource+0x11a>
|
|
8005734: 2b60 cmp r3, #96 @ 0x60
|
|
8005736: d877 bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005738: 2b50 cmp r3, #80 @ 0x50
|
|
800573a: d03c beq.n 80057b6 <HAL_TIM_ConfigClockSource+0xfa>
|
|
800573c: 2b50 cmp r3, #80 @ 0x50
|
|
800573e: d873 bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005740: 2b40 cmp r3, #64 @ 0x40
|
|
8005742: d058 beq.n 80057f6 <HAL_TIM_ConfigClockSource+0x13a>
|
|
8005744: 2b40 cmp r3, #64 @ 0x40
|
|
8005746: d86f bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005748: 2b30 cmp r3, #48 @ 0x30
|
|
800574a: d064 beq.n 8005816 <HAL_TIM_ConfigClockSource+0x15a>
|
|
800574c: 2b30 cmp r3, #48 @ 0x30
|
|
800574e: d86b bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005750: 2b20 cmp r3, #32
|
|
8005752: d060 beq.n 8005816 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005754: 2b20 cmp r3, #32
|
|
8005756: d867 bhi.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005758: 2b00 cmp r3, #0
|
|
800575a: d05c beq.n 8005816 <HAL_TIM_ConfigClockSource+0x15a>
|
|
800575c: 2b10 cmp r3, #16
|
|
800575e: d05a beq.n 8005816 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005760: e062 b.n 8005828 <HAL_TIM_ConfigClockSource+0x16c>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005762: 687b ldr r3, [r7, #4]
|
|
8005764: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005766: 683b ldr r3, [r7, #0]
|
|
8005768: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
800576a: 683b ldr r3, [r7, #0]
|
|
800576c: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
800576e: 683b ldr r3, [r7, #0]
|
|
8005770: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005772: f000 f974 bl 8005a5e <TIM_ETR_SetConfig>
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005776: 687b ldr r3, [r7, #4]
|
|
8005778: 681b ldr r3, [r3, #0]
|
|
800577a: 689b ldr r3, [r3, #8]
|
|
800577c: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
800577e: 68bb ldr r3, [r7, #8]
|
|
8005780: f043 0377 orr.w r3, r3, #119 @ 0x77
|
|
8005784: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005786: 687b ldr r3, [r7, #4]
|
|
8005788: 681b ldr r3, [r3, #0]
|
|
800578a: 68ba ldr r2, [r7, #8]
|
|
800578c: 609a str r2, [r3, #8]
|
|
break;
|
|
800578e: e04f b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005790: 687b ldr r3, [r7, #4]
|
|
8005792: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005794: 683b ldr r3, [r7, #0]
|
|
8005796: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005798: 683b ldr r3, [r7, #0]
|
|
800579a: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
800579c: 683b ldr r3, [r7, #0]
|
|
800579e: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80057a0: f000 f95d bl 8005a5e <TIM_ETR_SetConfig>
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
80057a4: 687b ldr r3, [r7, #4]
|
|
80057a6: 681b ldr r3, [r3, #0]
|
|
80057a8: 689a ldr r2, [r3, #8]
|
|
80057aa: 687b ldr r3, [r7, #4]
|
|
80057ac: 681b ldr r3, [r3, #0]
|
|
80057ae: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
80057b2: 609a str r2, [r3, #8]
|
|
break;
|
|
80057b4: e03c b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057b6: 687b ldr r3, [r7, #4]
|
|
80057b8: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057ba: 683b ldr r3, [r7, #0]
|
|
80057bc: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057be: 683b ldr r3, [r7, #0]
|
|
80057c0: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057c2: 461a mov r2, r3
|
|
80057c4: f000 f8d4 bl 8005970 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
80057c8: 687b ldr r3, [r7, #4]
|
|
80057ca: 681b ldr r3, [r3, #0]
|
|
80057cc: 2150 movs r1, #80 @ 0x50
|
|
80057ce: 4618 mov r0, r3
|
|
80057d0: f000 f92b bl 8005a2a <TIM_ITRx_SetConfig>
|
|
break;
|
|
80057d4: e02c b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80057d6: 687b ldr r3, [r7, #4]
|
|
80057d8: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057da: 683b ldr r3, [r7, #0]
|
|
80057dc: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057de: 683b ldr r3, [r7, #0]
|
|
80057e0: 68db ldr r3, [r3, #12]
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80057e2: 461a mov r2, r3
|
|
80057e4: f000 f8f2 bl 80059cc <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
80057e8: 687b ldr r3, [r7, #4]
|
|
80057ea: 681b ldr r3, [r3, #0]
|
|
80057ec: 2160 movs r1, #96 @ 0x60
|
|
80057ee: 4618 mov r0, r3
|
|
80057f0: f000 f91b bl 8005a2a <TIM_ITRx_SetConfig>
|
|
break;
|
|
80057f4: e01c b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057f6: 687b ldr r3, [r7, #4]
|
|
80057f8: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057fa: 683b ldr r3, [r7, #0]
|
|
80057fc: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057fe: 683b ldr r3, [r7, #0]
|
|
8005800: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005802: 461a mov r2, r3
|
|
8005804: f000 f8b4 bl 8005970 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
8005808: 687b ldr r3, [r7, #4]
|
|
800580a: 681b ldr r3, [r3, #0]
|
|
800580c: 2140 movs r1, #64 @ 0x40
|
|
800580e: 4618 mov r0, r3
|
|
8005810: f000 f90b bl 8005a2a <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005814: e00c b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
8005816: 687b ldr r3, [r7, #4]
|
|
8005818: 681a ldr r2, [r3, #0]
|
|
800581a: 683b ldr r3, [r7, #0]
|
|
800581c: 681b ldr r3, [r3, #0]
|
|
800581e: 4619 mov r1, r3
|
|
8005820: 4610 mov r0, r2
|
|
8005822: f000 f902 bl 8005a2a <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005826: e003 b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005828: 2301 movs r3, #1
|
|
800582a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800582c: e000 b.n 8005830 <HAL_TIM_ConfigClockSource+0x174>
|
|
break;
|
|
800582e: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005830: 687b ldr r3, [r7, #4]
|
|
8005832: 2201 movs r2, #1
|
|
8005834: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005838: 687b ldr r3, [r7, #4]
|
|
800583a: 2200 movs r2, #0
|
|
800583c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8005840: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8005842: 4618 mov r0, r3
|
|
8005844: 3710 adds r7, #16
|
|
8005846: 46bd mov sp, r7
|
|
8005848: bd80 pop {r7, pc}
|
|
|
|
0800584a <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800584a: b480 push {r7}
|
|
800584c: b083 sub sp, #12
|
|
800584e: af00 add r7, sp, #0
|
|
8005850: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005852: bf00 nop
|
|
8005854: 370c adds r7, #12
|
|
8005856: 46bd mov sp, r7
|
|
8005858: bc80 pop {r7}
|
|
800585a: 4770 bx lr
|
|
|
|
0800585c <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800585c: b480 push {r7}
|
|
800585e: b083 sub sp, #12
|
|
8005860: af00 add r7, sp, #0
|
|
8005862: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005864: bf00 nop
|
|
8005866: 370c adds r7, #12
|
|
8005868: 46bd mov sp, r7
|
|
800586a: bc80 pop {r7}
|
|
800586c: 4770 bx lr
|
|
|
|
0800586e <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800586e: b480 push {r7}
|
|
8005870: b083 sub sp, #12
|
|
8005872: af00 add r7, sp, #0
|
|
8005874: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005876: bf00 nop
|
|
8005878: 370c adds r7, #12
|
|
800587a: 46bd mov sp, r7
|
|
800587c: bc80 pop {r7}
|
|
800587e: 4770 bx lr
|
|
|
|
08005880 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005880: b480 push {r7}
|
|
8005882: b083 sub sp, #12
|
|
8005884: af00 add r7, sp, #0
|
|
8005886: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005888: bf00 nop
|
|
800588a: 370c adds r7, #12
|
|
800588c: 46bd mov sp, r7
|
|
800588e: bc80 pop {r7}
|
|
8005890: 4770 bx lr
|
|
...
|
|
|
|
08005894 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8005894: b480 push {r7}
|
|
8005896: b085 sub sp, #20
|
|
8005898: af00 add r7, sp, #0
|
|
800589a: 6078 str r0, [r7, #4]
|
|
800589c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800589e: 687b ldr r3, [r7, #4]
|
|
80058a0: 681b ldr r3, [r3, #0]
|
|
80058a2: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
80058a4: 687b ldr r3, [r7, #4]
|
|
80058a6: 4a2f ldr r2, [pc, #188] @ (8005964 <TIM_Base_SetConfig+0xd0>)
|
|
80058a8: 4293 cmp r3, r2
|
|
80058aa: d00b beq.n 80058c4 <TIM_Base_SetConfig+0x30>
|
|
80058ac: 687b ldr r3, [r7, #4]
|
|
80058ae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80058b2: d007 beq.n 80058c4 <TIM_Base_SetConfig+0x30>
|
|
80058b4: 687b ldr r3, [r7, #4]
|
|
80058b6: 4a2c ldr r2, [pc, #176] @ (8005968 <TIM_Base_SetConfig+0xd4>)
|
|
80058b8: 4293 cmp r3, r2
|
|
80058ba: d003 beq.n 80058c4 <TIM_Base_SetConfig+0x30>
|
|
80058bc: 687b ldr r3, [r7, #4]
|
|
80058be: 4a2b ldr r2, [pc, #172] @ (800596c <TIM_Base_SetConfig+0xd8>)
|
|
80058c0: 4293 cmp r3, r2
|
|
80058c2: d108 bne.n 80058d6 <TIM_Base_SetConfig+0x42>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80058c4: 68fb ldr r3, [r7, #12]
|
|
80058c6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80058ca: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80058cc: 683b ldr r3, [r7, #0]
|
|
80058ce: 685b ldr r3, [r3, #4]
|
|
80058d0: 68fa ldr r2, [r7, #12]
|
|
80058d2: 4313 orrs r3, r2
|
|
80058d4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80058d6: 687b ldr r3, [r7, #4]
|
|
80058d8: 4a22 ldr r2, [pc, #136] @ (8005964 <TIM_Base_SetConfig+0xd0>)
|
|
80058da: 4293 cmp r3, r2
|
|
80058dc: d00b beq.n 80058f6 <TIM_Base_SetConfig+0x62>
|
|
80058de: 687b ldr r3, [r7, #4]
|
|
80058e0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80058e4: d007 beq.n 80058f6 <TIM_Base_SetConfig+0x62>
|
|
80058e6: 687b ldr r3, [r7, #4]
|
|
80058e8: 4a1f ldr r2, [pc, #124] @ (8005968 <TIM_Base_SetConfig+0xd4>)
|
|
80058ea: 4293 cmp r3, r2
|
|
80058ec: d003 beq.n 80058f6 <TIM_Base_SetConfig+0x62>
|
|
80058ee: 687b ldr r3, [r7, #4]
|
|
80058f0: 4a1e ldr r2, [pc, #120] @ (800596c <TIM_Base_SetConfig+0xd8>)
|
|
80058f2: 4293 cmp r3, r2
|
|
80058f4: d108 bne.n 8005908 <TIM_Base_SetConfig+0x74>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
80058f6: 68fb ldr r3, [r7, #12]
|
|
80058f8: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80058fc: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80058fe: 683b ldr r3, [r7, #0]
|
|
8005900: 68db ldr r3, [r3, #12]
|
|
8005902: 68fa ldr r2, [r7, #12]
|
|
8005904: 4313 orrs r3, r2
|
|
8005906: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8005908: 68fb ldr r3, [r7, #12]
|
|
800590a: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
800590e: 683b ldr r3, [r7, #0]
|
|
8005910: 695b ldr r3, [r3, #20]
|
|
8005912: 4313 orrs r3, r2
|
|
8005914: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8005916: 687b ldr r3, [r7, #4]
|
|
8005918: 68fa ldr r2, [r7, #12]
|
|
800591a: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800591c: 683b ldr r3, [r7, #0]
|
|
800591e: 689a ldr r2, [r3, #8]
|
|
8005920: 687b ldr r3, [r7, #4]
|
|
8005922: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8005924: 683b ldr r3, [r7, #0]
|
|
8005926: 681a ldr r2, [r3, #0]
|
|
8005928: 687b ldr r3, [r7, #4]
|
|
800592a: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800592c: 687b ldr r3, [r7, #4]
|
|
800592e: 4a0d ldr r2, [pc, #52] @ (8005964 <TIM_Base_SetConfig+0xd0>)
|
|
8005930: 4293 cmp r3, r2
|
|
8005932: d103 bne.n 800593c <TIM_Base_SetConfig+0xa8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8005934: 683b ldr r3, [r7, #0]
|
|
8005936: 691a ldr r2, [r3, #16]
|
|
8005938: 687b ldr r3, [r7, #4]
|
|
800593a: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800593c: 687b ldr r3, [r7, #4]
|
|
800593e: 2201 movs r2, #1
|
|
8005940: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
8005942: 687b ldr r3, [r7, #4]
|
|
8005944: 691b ldr r3, [r3, #16]
|
|
8005946: f003 0301 and.w r3, r3, #1
|
|
800594a: 2b00 cmp r3, #0
|
|
800594c: d005 beq.n 800595a <TIM_Base_SetConfig+0xc6>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
800594e: 687b ldr r3, [r7, #4]
|
|
8005950: 691b ldr r3, [r3, #16]
|
|
8005952: f023 0201 bic.w r2, r3, #1
|
|
8005956: 687b ldr r3, [r7, #4]
|
|
8005958: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
800595a: bf00 nop
|
|
800595c: 3714 adds r7, #20
|
|
800595e: 46bd mov sp, r7
|
|
8005960: bc80 pop {r7}
|
|
8005962: 4770 bx lr
|
|
8005964: 40012c00 .word 0x40012c00
|
|
8005968: 40000400 .word 0x40000400
|
|
800596c: 40000800 .word 0x40000800
|
|
|
|
08005970 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005970: b480 push {r7}
|
|
8005972: b087 sub sp, #28
|
|
8005974: af00 add r7, sp, #0
|
|
8005976: 60f8 str r0, [r7, #12]
|
|
8005978: 60b9 str r1, [r7, #8]
|
|
800597a: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
800597c: 68fb ldr r3, [r7, #12]
|
|
800597e: 6a1b ldr r3, [r3, #32]
|
|
8005980: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8005982: 68fb ldr r3, [r7, #12]
|
|
8005984: 6a1b ldr r3, [r3, #32]
|
|
8005986: f023 0201 bic.w r2, r3, #1
|
|
800598a: 68fb ldr r3, [r7, #12]
|
|
800598c: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
800598e: 68fb ldr r3, [r7, #12]
|
|
8005990: 699b ldr r3, [r3, #24]
|
|
8005992: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
8005994: 693b ldr r3, [r7, #16]
|
|
8005996: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800599a: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
800599c: 687b ldr r3, [r7, #4]
|
|
800599e: 011b lsls r3, r3, #4
|
|
80059a0: 693a ldr r2, [r7, #16]
|
|
80059a2: 4313 orrs r3, r2
|
|
80059a4: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
80059a6: 697b ldr r3, [r7, #20]
|
|
80059a8: f023 030a bic.w r3, r3, #10
|
|
80059ac: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
80059ae: 697a ldr r2, [r7, #20]
|
|
80059b0: 68bb ldr r3, [r7, #8]
|
|
80059b2: 4313 orrs r3, r2
|
|
80059b4: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
80059b6: 68fb ldr r3, [r7, #12]
|
|
80059b8: 693a ldr r2, [r7, #16]
|
|
80059ba: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
80059bc: 68fb ldr r3, [r7, #12]
|
|
80059be: 697a ldr r2, [r7, #20]
|
|
80059c0: 621a str r2, [r3, #32]
|
|
}
|
|
80059c2: bf00 nop
|
|
80059c4: 371c adds r7, #28
|
|
80059c6: 46bd mov sp, r7
|
|
80059c8: bc80 pop {r7}
|
|
80059ca: 4770 bx lr
|
|
|
|
080059cc <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
80059cc: b480 push {r7}
|
|
80059ce: b087 sub sp, #28
|
|
80059d0: af00 add r7, sp, #0
|
|
80059d2: 60f8 str r0, [r7, #12]
|
|
80059d4: 60b9 str r1, [r7, #8]
|
|
80059d6: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
80059d8: 68fb ldr r3, [r7, #12]
|
|
80059da: 6a1b ldr r3, [r3, #32]
|
|
80059dc: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
80059de: 68fb ldr r3, [r7, #12]
|
|
80059e0: 6a1b ldr r3, [r3, #32]
|
|
80059e2: f023 0210 bic.w r2, r3, #16
|
|
80059e6: 68fb ldr r3, [r7, #12]
|
|
80059e8: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
80059ea: 68fb ldr r3, [r7, #12]
|
|
80059ec: 699b ldr r3, [r3, #24]
|
|
80059ee: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
80059f0: 693b ldr r3, [r7, #16]
|
|
80059f2: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
80059f6: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
80059f8: 687b ldr r3, [r7, #4]
|
|
80059fa: 031b lsls r3, r3, #12
|
|
80059fc: 693a ldr r2, [r7, #16]
|
|
80059fe: 4313 orrs r3, r2
|
|
8005a00: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
8005a02: 697b ldr r3, [r7, #20]
|
|
8005a04: f023 03a0 bic.w r3, r3, #160 @ 0xa0
|
|
8005a08: 617b str r3, [r7, #20]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8005a0a: 68bb ldr r3, [r7, #8]
|
|
8005a0c: 011b lsls r3, r3, #4
|
|
8005a0e: 697a ldr r2, [r7, #20]
|
|
8005a10: 4313 orrs r3, r2
|
|
8005a12: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
8005a14: 68fb ldr r3, [r7, #12]
|
|
8005a16: 693a ldr r2, [r7, #16]
|
|
8005a18: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8005a1a: 68fb ldr r3, [r7, #12]
|
|
8005a1c: 697a ldr r2, [r7, #20]
|
|
8005a1e: 621a str r2, [r3, #32]
|
|
}
|
|
8005a20: bf00 nop
|
|
8005a22: 371c adds r7, #28
|
|
8005a24: 46bd mov sp, r7
|
|
8005a26: bc80 pop {r7}
|
|
8005a28: 4770 bx lr
|
|
|
|
08005a2a <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
8005a2a: b480 push {r7}
|
|
8005a2c: b085 sub sp, #20
|
|
8005a2e: af00 add r7, sp, #0
|
|
8005a30: 6078 str r0, [r7, #4]
|
|
8005a32: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005a34: 687b ldr r3, [r7, #4]
|
|
8005a36: 689b ldr r3, [r3, #8]
|
|
8005a38: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8005a3a: 68fb ldr r3, [r7, #12]
|
|
8005a3c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005a40: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8005a42: 683a ldr r2, [r7, #0]
|
|
8005a44: 68fb ldr r3, [r7, #12]
|
|
8005a46: 4313 orrs r3, r2
|
|
8005a48: f043 0307 orr.w r3, r3, #7
|
|
8005a4c: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005a4e: 687b ldr r3, [r7, #4]
|
|
8005a50: 68fa ldr r2, [r7, #12]
|
|
8005a52: 609a str r2, [r3, #8]
|
|
}
|
|
8005a54: bf00 nop
|
|
8005a56: 3714 adds r7, #20
|
|
8005a58: 46bd mov sp, r7
|
|
8005a5a: bc80 pop {r7}
|
|
8005a5c: 4770 bx lr
|
|
|
|
08005a5e <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8005a5e: b480 push {r7}
|
|
8005a60: b087 sub sp, #28
|
|
8005a62: af00 add r7, sp, #0
|
|
8005a64: 60f8 str r0, [r7, #12]
|
|
8005a66: 60b9 str r1, [r7, #8]
|
|
8005a68: 607a str r2, [r7, #4]
|
|
8005a6a: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005a6c: 68fb ldr r3, [r7, #12]
|
|
8005a6e: 689b ldr r3, [r3, #8]
|
|
8005a70: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8005a72: 697b ldr r3, [r7, #20]
|
|
8005a74: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8005a78: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8005a7a: 683b ldr r3, [r7, #0]
|
|
8005a7c: 021a lsls r2, r3, #8
|
|
8005a7e: 687b ldr r3, [r7, #4]
|
|
8005a80: 431a orrs r2, r3
|
|
8005a82: 68bb ldr r3, [r7, #8]
|
|
8005a84: 4313 orrs r3, r2
|
|
8005a86: 697a ldr r2, [r7, #20]
|
|
8005a88: 4313 orrs r3, r2
|
|
8005a8a: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005a8c: 68fb ldr r3, [r7, #12]
|
|
8005a8e: 697a ldr r2, [r7, #20]
|
|
8005a90: 609a str r2, [r3, #8]
|
|
}
|
|
8005a92: bf00 nop
|
|
8005a94: 371c adds r7, #28
|
|
8005a96: 46bd mov sp, r7
|
|
8005a98: bc80 pop {r7}
|
|
8005a9a: 4770 bx lr
|
|
|
|
08005a9c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8005a9c: b480 push {r7}
|
|
8005a9e: b085 sub sp, #20
|
|
8005aa0: af00 add r7, sp, #0
|
|
8005aa2: 6078 str r0, [r7, #4]
|
|
8005aa4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8005aa6: 687b ldr r3, [r7, #4]
|
|
8005aa8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005aac: 2b01 cmp r3, #1
|
|
8005aae: d101 bne.n 8005ab4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8005ab0: 2302 movs r3, #2
|
|
8005ab2: e046 b.n 8005b42 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
8005ab4: 687b ldr r3, [r7, #4]
|
|
8005ab6: 2201 movs r2, #1
|
|
8005ab8: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005abc: 687b ldr r3, [r7, #4]
|
|
8005abe: 2202 movs r2, #2
|
|
8005ac0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8005ac4: 687b ldr r3, [r7, #4]
|
|
8005ac6: 681b ldr r3, [r3, #0]
|
|
8005ac8: 685b ldr r3, [r3, #4]
|
|
8005aca: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005acc: 687b ldr r3, [r7, #4]
|
|
8005ace: 681b ldr r3, [r3, #0]
|
|
8005ad0: 689b ldr r3, [r3, #8]
|
|
8005ad2: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8005ad4: 68fb ldr r3, [r7, #12]
|
|
8005ad6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005ada: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005adc: 683b ldr r3, [r7, #0]
|
|
8005ade: 681b ldr r3, [r3, #0]
|
|
8005ae0: 68fa ldr r2, [r7, #12]
|
|
8005ae2: 4313 orrs r3, r2
|
|
8005ae4: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8005ae6: 687b ldr r3, [r7, #4]
|
|
8005ae8: 681b ldr r3, [r3, #0]
|
|
8005aea: 68fa ldr r2, [r7, #12]
|
|
8005aec: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005aee: 687b ldr r3, [r7, #4]
|
|
8005af0: 681b ldr r3, [r3, #0]
|
|
8005af2: 4a16 ldr r2, [pc, #88] @ (8005b4c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|
8005af4: 4293 cmp r3, r2
|
|
8005af6: d00e beq.n 8005b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8005af8: 687b ldr r3, [r7, #4]
|
|
8005afa: 681b ldr r3, [r3, #0]
|
|
8005afc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005b00: d009 beq.n 8005b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8005b02: 687b ldr r3, [r7, #4]
|
|
8005b04: 681b ldr r3, [r3, #0]
|
|
8005b06: 4a12 ldr r2, [pc, #72] @ (8005b50 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|
8005b08: 4293 cmp r3, r2
|
|
8005b0a: d004 beq.n 8005b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8005b0c: 687b ldr r3, [r7, #4]
|
|
8005b0e: 681b ldr r3, [r3, #0]
|
|
8005b10: 4a10 ldr r2, [pc, #64] @ (8005b54 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8005b12: 4293 cmp r3, r2
|
|
8005b14: d10c bne.n 8005b30 <HAL_TIMEx_MasterConfigSynchronization+0x94>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8005b16: 68bb ldr r3, [r7, #8]
|
|
8005b18: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005b1c: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8005b1e: 683b ldr r3, [r7, #0]
|
|
8005b20: 685b ldr r3, [r3, #4]
|
|
8005b22: 68ba ldr r2, [r7, #8]
|
|
8005b24: 4313 orrs r3, r2
|
|
8005b26: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005b28: 687b ldr r3, [r7, #4]
|
|
8005b2a: 681b ldr r3, [r3, #0]
|
|
8005b2c: 68ba ldr r2, [r7, #8]
|
|
8005b2e: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005b30: 687b ldr r3, [r7, #4]
|
|
8005b32: 2201 movs r2, #1
|
|
8005b34: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005b38: 687b ldr r3, [r7, #4]
|
|
8005b3a: 2200 movs r2, #0
|
|
8005b3c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005b40: 2300 movs r3, #0
|
|
}
|
|
8005b42: 4618 mov r0, r3
|
|
8005b44: 3714 adds r7, #20
|
|
8005b46: 46bd mov sp, r7
|
|
8005b48: bc80 pop {r7}
|
|
8005b4a: 4770 bx lr
|
|
8005b4c: 40012c00 .word 0x40012c00
|
|
8005b50: 40000400 .word 0x40000400
|
|
8005b54: 40000800 .word 0x40000800
|
|
|
|
08005b58 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005b58: b480 push {r7}
|
|
8005b5a: b083 sub sp, #12
|
|
8005b5c: af00 add r7, sp, #0
|
|
8005b5e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005b60: bf00 nop
|
|
8005b62: 370c adds r7, #12
|
|
8005b64: 46bd mov sp, r7
|
|
8005b66: bc80 pop {r7}
|
|
8005b68: 4770 bx lr
|
|
|
|
08005b6a <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005b6a: b480 push {r7}
|
|
8005b6c: b083 sub sp, #12
|
|
8005b6e: af00 add r7, sp, #0
|
|
8005b70: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005b72: bf00 nop
|
|
8005b74: 370c adds r7, #12
|
|
8005b76: 46bd mov sp, r7
|
|
8005b78: bc80 pop {r7}
|
|
8005b7a: 4770 bx lr
|
|
|
|
08005b7c <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8005b7c: b580 push {r7, lr}
|
|
8005b7e: b082 sub sp, #8
|
|
8005b80: af00 add r7, sp, #0
|
|
8005b82: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005b84: 687b ldr r3, [r7, #4]
|
|
8005b86: 2b00 cmp r3, #0
|
|
8005b88: d101 bne.n 8005b8e <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005b8a: 2301 movs r3, #1
|
|
8005b8c: e042 b.n 8005c14 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
#if defined(USART_CR1_OVER8)
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8005b8e: 687b ldr r3, [r7, #4]
|
|
8005b90: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005b94: b2db uxtb r3, r3
|
|
8005b96: 2b00 cmp r3, #0
|
|
8005b98: d106 bne.n 8005ba8 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005b9a: 687b ldr r3, [r7, #4]
|
|
8005b9c: 2200 movs r2, #0
|
|
8005b9e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8005ba2: 6878 ldr r0, [r7, #4]
|
|
8005ba4: f7fd f882 bl 8002cac <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005ba8: 687b ldr r3, [r7, #4]
|
|
8005baa: 2224 movs r2, #36 @ 0x24
|
|
8005bac: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005bb0: 687b ldr r3, [r7, #4]
|
|
8005bb2: 681b ldr r3, [r3, #0]
|
|
8005bb4: 68da ldr r2, [r3, #12]
|
|
8005bb6: 687b ldr r3, [r7, #4]
|
|
8005bb8: 681b ldr r3, [r3, #0]
|
|
8005bba: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8005bbe: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8005bc0: 6878 ldr r0, [r7, #4]
|
|
8005bc2: f000 fd63 bl 800668c <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8005bc6: 687b ldr r3, [r7, #4]
|
|
8005bc8: 681b ldr r3, [r3, #0]
|
|
8005bca: 691a ldr r2, [r3, #16]
|
|
8005bcc: 687b ldr r3, [r7, #4]
|
|
8005bce: 681b ldr r3, [r3, #0]
|
|
8005bd0: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8005bd4: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8005bd6: 687b ldr r3, [r7, #4]
|
|
8005bd8: 681b ldr r3, [r3, #0]
|
|
8005bda: 695a ldr r2, [r3, #20]
|
|
8005bdc: 687b ldr r3, [r7, #4]
|
|
8005bde: 681b ldr r3, [r3, #0]
|
|
8005be0: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8005be4: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8005be6: 687b ldr r3, [r7, #4]
|
|
8005be8: 681b ldr r3, [r3, #0]
|
|
8005bea: 68da ldr r2, [r3, #12]
|
|
8005bec: 687b ldr r3, [r7, #4]
|
|
8005bee: 681b ldr r3, [r3, #0]
|
|
8005bf0: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8005bf4: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005bf6: 687b ldr r3, [r7, #4]
|
|
8005bf8: 2200 movs r2, #0
|
|
8005bfa: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005bfc: 687b ldr r3, [r7, #4]
|
|
8005bfe: 2220 movs r2, #32
|
|
8005c00: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005c04: 687b ldr r3, [r7, #4]
|
|
8005c06: 2220 movs r2, #32
|
|
8005c08: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005c0c: 687b ldr r3, [r7, #4]
|
|
8005c0e: 2200 movs r2, #0
|
|
8005c10: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8005c12: 2300 movs r3, #0
|
|
}
|
|
8005c14: 4618 mov r0, r3
|
|
8005c16: 3708 adds r7, #8
|
|
8005c18: 46bd mov sp, r7
|
|
8005c1a: bd80 pop {r7, pc}
|
|
|
|
08005c1c <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8005c1c: b580 push {r7, lr}
|
|
8005c1e: b08a sub sp, #40 @ 0x28
|
|
8005c20: af02 add r7, sp, #8
|
|
8005c22: 60f8 str r0, [r7, #12]
|
|
8005c24: 60b9 str r1, [r7, #8]
|
|
8005c26: 603b str r3, [r7, #0]
|
|
8005c28: 4613 mov r3, r2
|
|
8005c2a: 80fb strh r3, [r7, #6]
|
|
const uint8_t *pdata8bits;
|
|
const uint16_t *pdata16bits;
|
|
uint32_t tickstart = 0U;
|
|
8005c2c: 2300 movs r3, #0
|
|
8005c2e: 617b str r3, [r7, #20]
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8005c30: 68fb ldr r3, [r7, #12]
|
|
8005c32: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005c36: b2db uxtb r3, r3
|
|
8005c38: 2b20 cmp r3, #32
|
|
8005c3a: d175 bne.n 8005d28 <HAL_UART_Transmit+0x10c>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005c3c: 68bb ldr r3, [r7, #8]
|
|
8005c3e: 2b00 cmp r3, #0
|
|
8005c40: d002 beq.n 8005c48 <HAL_UART_Transmit+0x2c>
|
|
8005c42: 88fb ldrh r3, [r7, #6]
|
|
8005c44: 2b00 cmp r3, #0
|
|
8005c46: d101 bne.n 8005c4c <HAL_UART_Transmit+0x30>
|
|
{
|
|
return HAL_ERROR;
|
|
8005c48: 2301 movs r3, #1
|
|
8005c4a: e06e b.n 8005d2a <HAL_UART_Transmit+0x10e>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005c4c: 68fb ldr r3, [r7, #12]
|
|
8005c4e: 2200 movs r2, #0
|
|
8005c50: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8005c52: 68fb ldr r3, [r7, #12]
|
|
8005c54: 2221 movs r2, #33 @ 0x21
|
|
8005c56: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8005c5a: f7fd f8f9 bl 8002e50 <HAL_GetTick>
|
|
8005c5e: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8005c60: 68fb ldr r3, [r7, #12]
|
|
8005c62: 88fa ldrh r2, [r7, #6]
|
|
8005c64: 849a strh r2, [r3, #36] @ 0x24
|
|
huart->TxXferCount = Size;
|
|
8005c66: 68fb ldr r3, [r7, #12]
|
|
8005c68: 88fa ldrh r2, [r7, #6]
|
|
8005c6a: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8005c6c: 68fb ldr r3, [r7, #12]
|
|
8005c6e: 689b ldr r3, [r3, #8]
|
|
8005c70: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005c74: d108 bne.n 8005c88 <HAL_UART_Transmit+0x6c>
|
|
8005c76: 68fb ldr r3, [r7, #12]
|
|
8005c78: 691b ldr r3, [r3, #16]
|
|
8005c7a: 2b00 cmp r3, #0
|
|
8005c7c: d104 bne.n 8005c88 <HAL_UART_Transmit+0x6c>
|
|
{
|
|
pdata8bits = NULL;
|
|
8005c7e: 2300 movs r3, #0
|
|
8005c80: 61fb str r3, [r7, #28]
|
|
pdata16bits = (const uint16_t *) pData;
|
|
8005c82: 68bb ldr r3, [r7, #8]
|
|
8005c84: 61bb str r3, [r7, #24]
|
|
8005c86: e003 b.n 8005c90 <HAL_UART_Transmit+0x74>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8005c88: 68bb ldr r3, [r7, #8]
|
|
8005c8a: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
8005c8c: 2300 movs r3, #0
|
|
8005c8e: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
8005c90: e02e b.n 8005cf0 <HAL_UART_Transmit+0xd4>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8005c92: 683b ldr r3, [r7, #0]
|
|
8005c94: 9300 str r3, [sp, #0]
|
|
8005c96: 697b ldr r3, [r7, #20]
|
|
8005c98: 2200 movs r2, #0
|
|
8005c9a: 2180 movs r1, #128 @ 0x80
|
|
8005c9c: 68f8 ldr r0, [r7, #12]
|
|
8005c9e: f000 fb01 bl 80062a4 <UART_WaitOnFlagUntilTimeout>
|
|
8005ca2: 4603 mov r3, r0
|
|
8005ca4: 2b00 cmp r3, #0
|
|
8005ca6: d005 beq.n 8005cb4 <HAL_UART_Transmit+0x98>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005ca8: 68fb ldr r3, [r7, #12]
|
|
8005caa: 2220 movs r2, #32
|
|
8005cac: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_TIMEOUT;
|
|
8005cb0: 2303 movs r3, #3
|
|
8005cb2: e03a b.n 8005d2a <HAL_UART_Transmit+0x10e>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8005cb4: 69fb ldr r3, [r7, #28]
|
|
8005cb6: 2b00 cmp r3, #0
|
|
8005cb8: d10b bne.n 8005cd2 <HAL_UART_Transmit+0xb6>
|
|
{
|
|
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8005cba: 69bb ldr r3, [r7, #24]
|
|
8005cbc: 881b ldrh r3, [r3, #0]
|
|
8005cbe: 461a mov r2, r3
|
|
8005cc0: 68fb ldr r3, [r7, #12]
|
|
8005cc2: 681b ldr r3, [r3, #0]
|
|
8005cc4: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8005cc8: 605a str r2, [r3, #4]
|
|
pdata16bits++;
|
|
8005cca: 69bb ldr r3, [r7, #24]
|
|
8005ccc: 3302 adds r3, #2
|
|
8005cce: 61bb str r3, [r7, #24]
|
|
8005cd0: e007 b.n 8005ce2 <HAL_UART_Transmit+0xc6>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8005cd2: 69fb ldr r3, [r7, #28]
|
|
8005cd4: 781a ldrb r2, [r3, #0]
|
|
8005cd6: 68fb ldr r3, [r7, #12]
|
|
8005cd8: 681b ldr r3, [r3, #0]
|
|
8005cda: 605a str r2, [r3, #4]
|
|
pdata8bits++;
|
|
8005cdc: 69fb ldr r3, [r7, #28]
|
|
8005cde: 3301 adds r3, #1
|
|
8005ce0: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
8005ce2: 68fb ldr r3, [r7, #12]
|
|
8005ce4: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8005ce6: b29b uxth r3, r3
|
|
8005ce8: 3b01 subs r3, #1
|
|
8005cea: b29a uxth r2, r3
|
|
8005cec: 68fb ldr r3, [r7, #12]
|
|
8005cee: 84da strh r2, [r3, #38] @ 0x26
|
|
while (huart->TxXferCount > 0U)
|
|
8005cf0: 68fb ldr r3, [r7, #12]
|
|
8005cf2: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8005cf4: b29b uxth r3, r3
|
|
8005cf6: 2b00 cmp r3, #0
|
|
8005cf8: d1cb bne.n 8005c92 <HAL_UART_Transmit+0x76>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8005cfa: 683b ldr r3, [r7, #0]
|
|
8005cfc: 9300 str r3, [sp, #0]
|
|
8005cfe: 697b ldr r3, [r7, #20]
|
|
8005d00: 2200 movs r2, #0
|
|
8005d02: 2140 movs r1, #64 @ 0x40
|
|
8005d04: 68f8 ldr r0, [r7, #12]
|
|
8005d06: f000 facd bl 80062a4 <UART_WaitOnFlagUntilTimeout>
|
|
8005d0a: 4603 mov r3, r0
|
|
8005d0c: 2b00 cmp r3, #0
|
|
8005d0e: d005 beq.n 8005d1c <HAL_UART_Transmit+0x100>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005d10: 68fb ldr r3, [r7, #12]
|
|
8005d12: 2220 movs r2, #32
|
|
8005d14: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_TIMEOUT;
|
|
8005d18: 2303 movs r3, #3
|
|
8005d1a: e006 b.n 8005d2a <HAL_UART_Transmit+0x10e>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005d1c: 68fb ldr r3, [r7, #12]
|
|
8005d1e: 2220 movs r2, #32
|
|
8005d20: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_OK;
|
|
8005d24: 2300 movs r3, #0
|
|
8005d26: e000 b.n 8005d2a <HAL_UART_Transmit+0x10e>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005d28: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005d2a: 4618 mov r0, r3
|
|
8005d2c: 3720 adds r7, #32
|
|
8005d2e: 46bd mov sp, r7
|
|
8005d30: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005d34 <HAL_UART_IRQHandler>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8005d34: b580 push {r7, lr}
|
|
8005d36: b0ba sub sp, #232 @ 0xe8
|
|
8005d38: af00 add r7, sp, #0
|
|
8005d3a: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->SR);
|
|
8005d3c: 687b ldr r3, [r7, #4]
|
|
8005d3e: 681b ldr r3, [r3, #0]
|
|
8005d40: 681b ldr r3, [r3, #0]
|
|
8005d42: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8005d46: 687b ldr r3, [r7, #4]
|
|
8005d48: 681b ldr r3, [r3, #0]
|
|
8005d4a: 68db ldr r3, [r3, #12]
|
|
8005d4c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8005d50: 687b ldr r3, [r7, #4]
|
|
8005d52: 681b ldr r3, [r3, #0]
|
|
8005d54: 695b ldr r3, [r3, #20]
|
|
8005d56: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
uint32_t errorflags = 0x00U;
|
|
8005d5a: 2300 movs r3, #0
|
|
8005d5c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
uint32_t dmarequest = 0x00U;
|
|
8005d60: 2300 movs r3, #0
|
|
8005d62: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
|
|
8005d66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005d6a: f003 030f and.w r3, r3, #15
|
|
8005d6e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == RESET)
|
|
8005d72: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005d76: 2b00 cmp r3, #0
|
|
8005d78: d10f bne.n 8005d9a <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
/* UART in mode Receiver -------------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
8005d7a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005d7e: f003 0320 and.w r3, r3, #32
|
|
8005d82: 2b00 cmp r3, #0
|
|
8005d84: d009 beq.n 8005d9a <HAL_UART_IRQHandler+0x66>
|
|
8005d86: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005d8a: f003 0320 and.w r3, r3, #32
|
|
8005d8e: 2b00 cmp r3, #0
|
|
8005d90: d003 beq.n 8005d9a <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
8005d92: 6878 ldr r0, [r7, #4]
|
|
8005d94: f000 fbbc bl 8006510 <UART_Receive_IT>
|
|
return;
|
|
8005d98: e25b b.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
|
|
8005d9a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005d9e: 2b00 cmp r3, #0
|
|
8005da0: f000 80de beq.w 8005f60 <HAL_UART_IRQHandler+0x22c>
|
|
8005da4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005da8: f003 0301 and.w r3, r3, #1
|
|
8005dac: 2b00 cmp r3, #0
|
|
8005dae: d106 bne.n 8005dbe <HAL_UART_IRQHandler+0x8a>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
|
|
8005db0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005db4: f403 7390 and.w r3, r3, #288 @ 0x120
|
|
8005db8: 2b00 cmp r3, #0
|
|
8005dba: f000 80d1 beq.w 8005f60 <HAL_UART_IRQHandler+0x22c>
|
|
{
|
|
/* UART parity error interrupt occurred ----------------------------------*/
|
|
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
|
|
8005dbe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005dc2: f003 0301 and.w r3, r3, #1
|
|
8005dc6: 2b00 cmp r3, #0
|
|
8005dc8: d00b beq.n 8005de2 <HAL_UART_IRQHandler+0xae>
|
|
8005dca: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005dce: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005dd2: 2b00 cmp r3, #0
|
|
8005dd4: d005 beq.n 8005de2 <HAL_UART_IRQHandler+0xae>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8005dd6: 687b ldr r3, [r7, #4]
|
|
8005dd8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005dda: f043 0201 orr.w r2, r3, #1
|
|
8005dde: 687b ldr r3, [r7, #4]
|
|
8005de0: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART noise error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
8005de2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005de6: f003 0304 and.w r3, r3, #4
|
|
8005dea: 2b00 cmp r3, #0
|
|
8005dec: d00b beq.n 8005e06 <HAL_UART_IRQHandler+0xd2>
|
|
8005dee: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005df2: f003 0301 and.w r3, r3, #1
|
|
8005df6: 2b00 cmp r3, #0
|
|
8005df8: d005 beq.n 8005e06 <HAL_UART_IRQHandler+0xd2>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8005dfa: 687b ldr r3, [r7, #4]
|
|
8005dfc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005dfe: f043 0202 orr.w r2, r3, #2
|
|
8005e02: 687b ldr r3, [r7, #4]
|
|
8005e04: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART frame error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
8005e06: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005e0a: f003 0302 and.w r3, r3, #2
|
|
8005e0e: 2b00 cmp r3, #0
|
|
8005e10: d00b beq.n 8005e2a <HAL_UART_IRQHandler+0xf6>
|
|
8005e12: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005e16: f003 0301 and.w r3, r3, #1
|
|
8005e1a: 2b00 cmp r3, #0
|
|
8005e1c: d005 beq.n 8005e2a <HAL_UART_IRQHandler+0xf6>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8005e1e: 687b ldr r3, [r7, #4]
|
|
8005e20: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005e22: f043 0204 orr.w r2, r3, #4
|
|
8005e26: 687b ldr r3, [r7, #4]
|
|
8005e28: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
|
|
8005e2a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005e2e: f003 0308 and.w r3, r3, #8
|
|
8005e32: 2b00 cmp r3, #0
|
|
8005e34: d011 beq.n 8005e5a <HAL_UART_IRQHandler+0x126>
|
|
8005e36: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005e3a: f003 0320 and.w r3, r3, #32
|
|
8005e3e: 2b00 cmp r3, #0
|
|
8005e40: d105 bne.n 8005e4e <HAL_UART_IRQHandler+0x11a>
|
|
|| ((cr3its & USART_CR3_EIE) != RESET)))
|
|
8005e42: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005e46: f003 0301 and.w r3, r3, #1
|
|
8005e4a: 2b00 cmp r3, #0
|
|
8005e4c: d005 beq.n 8005e5a <HAL_UART_IRQHandler+0x126>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
8005e4e: 687b ldr r3, [r7, #4]
|
|
8005e50: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005e52: f043 0208 orr.w r2, r3, #8
|
|
8005e56: 687b ldr r3, [r7, #4]
|
|
8005e58: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be --------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8005e5a: 687b ldr r3, [r7, #4]
|
|
8005e5c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005e5e: 2b00 cmp r3, #0
|
|
8005e60: f000 81f2 beq.w 8006248 <HAL_UART_IRQHandler+0x514>
|
|
{
|
|
/* UART in mode Receiver -----------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
8005e64: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005e68: f003 0320 and.w r3, r3, #32
|
|
8005e6c: 2b00 cmp r3, #0
|
|
8005e6e: d008 beq.n 8005e82 <HAL_UART_IRQHandler+0x14e>
|
|
8005e70: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005e74: f003 0320 and.w r3, r3, #32
|
|
8005e78: 2b00 cmp r3, #0
|
|
8005e7a: d002 beq.n 8005e82 <HAL_UART_IRQHandler+0x14e>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
8005e7c: 6878 ldr r0, [r7, #4]
|
|
8005e7e: f000 fb47 bl 8006510 <UART_Receive_IT>
|
|
}
|
|
|
|
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
|
|
consider error as blocking */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005e82: 687b ldr r3, [r7, #4]
|
|
8005e84: 681b ldr r3, [r3, #0]
|
|
8005e86: 695b ldr r3, [r3, #20]
|
|
8005e88: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005e8c: 2b00 cmp r3, #0
|
|
8005e8e: bf14 ite ne
|
|
8005e90: 2301 movne r3, #1
|
|
8005e92: 2300 moveq r3, #0
|
|
8005e94: b2db uxtb r3, r3
|
|
8005e96: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
|
|
8005e9a: 687b ldr r3, [r7, #4]
|
|
8005e9c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005e9e: f003 0308 and.w r3, r3, #8
|
|
8005ea2: 2b00 cmp r3, #0
|
|
8005ea4: d103 bne.n 8005eae <HAL_UART_IRQHandler+0x17a>
|
|
8005ea6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
8005eaa: 2b00 cmp r3, #0
|
|
8005eac: d04f beq.n 8005f4e <HAL_UART_IRQHandler+0x21a>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8005eae: 6878 ldr r0, [r7, #4]
|
|
8005eb0: f000 fa51 bl 8006356 <UART_EndRxTransfer>
|
|
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005eb4: 687b ldr r3, [r7, #4]
|
|
8005eb6: 681b ldr r3, [r3, #0]
|
|
8005eb8: 695b ldr r3, [r3, #20]
|
|
8005eba: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005ebe: 2b00 cmp r3, #0
|
|
8005ec0: d041 beq.n 8005f46 <HAL_UART_IRQHandler+0x212>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005ec2: 687b ldr r3, [r7, #4]
|
|
8005ec4: 681b ldr r3, [r3, #0]
|
|
8005ec6: 3314 adds r3, #20
|
|
8005ec8: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005ecc: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8005ed0: e853 3f00 ldrex r3, [r3]
|
|
8005ed4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
8005ed8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8005edc: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005ee0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8005ee4: 687b ldr r3, [r7, #4]
|
|
8005ee6: 681b ldr r3, [r3, #0]
|
|
8005ee8: 3314 adds r3, #20
|
|
8005eea: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
8005eee: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
8005ef2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005ef6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
8005efa: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
8005efe: e841 2300 strex r3, r2, [r1]
|
|
8005f02: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
8005f06: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8005f0a: 2b00 cmp r3, #0
|
|
8005f0c: d1d9 bne.n 8005ec2 <HAL_UART_IRQHandler+0x18e>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
8005f0e: 687b ldr r3, [r7, #4]
|
|
8005f10: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005f12: 2b00 cmp r3, #0
|
|
8005f14: d013 beq.n 8005f3e <HAL_UART_IRQHandler+0x20a>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
8005f16: 687b ldr r3, [r7, #4]
|
|
8005f18: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005f1a: 4a7e ldr r2, [pc, #504] @ (8006114 <HAL_UART_IRQHandler+0x3e0>)
|
|
8005f1c: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
8005f1e: 687b ldr r3, [r7, #4]
|
|
8005f20: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005f22: 4618 mov r0, r3
|
|
8005f24: f7fd faf8 bl 8003518 <HAL_DMA_Abort_IT>
|
|
8005f28: 4603 mov r3, r0
|
|
8005f2a: 2b00 cmp r3, #0
|
|
8005f2c: d016 beq.n 8005f5c <HAL_UART_IRQHandler+0x228>
|
|
{
|
|
/* Call Directly XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8005f2e: 687b ldr r3, [r7, #4]
|
|
8005f30: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005f32: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8005f34: 687a ldr r2, [r7, #4]
|
|
8005f36: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8005f38: 4610 mov r0, r2
|
|
8005f3a: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005f3c: e00e b.n 8005f5c <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005f3e: 6878 ldr r0, [r7, #4]
|
|
8005f40: f000 f99c bl 800627c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005f44: e00a b.n 8005f5c <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005f46: 6878 ldr r0, [r7, #4]
|
|
8005f48: f000 f998 bl 800627c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005f4c: e006 b.n 8005f5c <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005f4e: 6878 ldr r0, [r7, #4]
|
|
8005f50: f000 f994 bl 800627c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005f54: 687b ldr r3, [r7, #4]
|
|
8005f56: 2200 movs r2, #0
|
|
8005f58: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
}
|
|
return;
|
|
8005f5a: e175 b.n 8006248 <HAL_UART_IRQHandler+0x514>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005f5c: bf00 nop
|
|
return;
|
|
8005f5e: e173 b.n 8006248 <HAL_UART_IRQHandler+0x514>
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005f60: 687b ldr r3, [r7, #4]
|
|
8005f62: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005f64: 2b01 cmp r3, #1
|
|
8005f66: f040 814f bne.w 8006208 <HAL_UART_IRQHandler+0x4d4>
|
|
&& ((isrflags & USART_SR_IDLE) != 0U)
|
|
8005f6a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005f6e: f003 0310 and.w r3, r3, #16
|
|
8005f72: 2b00 cmp r3, #0
|
|
8005f74: f000 8148 beq.w 8006208 <HAL_UART_IRQHandler+0x4d4>
|
|
&& ((cr1its & USART_SR_IDLE) != 0U))
|
|
8005f78: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005f7c: f003 0310 and.w r3, r3, #16
|
|
8005f80: 2b00 cmp r3, #0
|
|
8005f82: f000 8141 beq.w 8006208 <HAL_UART_IRQHandler+0x4d4>
|
|
{
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
8005f86: 2300 movs r3, #0
|
|
8005f88: 60bb str r3, [r7, #8]
|
|
8005f8a: 687b ldr r3, [r7, #4]
|
|
8005f8c: 681b ldr r3, [r3, #0]
|
|
8005f8e: 681b ldr r3, [r3, #0]
|
|
8005f90: 60bb str r3, [r7, #8]
|
|
8005f92: 687b ldr r3, [r7, #4]
|
|
8005f94: 681b ldr r3, [r3, #0]
|
|
8005f96: 685b ldr r3, [r3, #4]
|
|
8005f98: 60bb str r3, [r7, #8]
|
|
8005f9a: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005f9c: 687b ldr r3, [r7, #4]
|
|
8005f9e: 681b ldr r3, [r3, #0]
|
|
8005fa0: 695b ldr r3, [r3, #20]
|
|
8005fa2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005fa6: 2b00 cmp r3, #0
|
|
8005fa8: f000 80b6 beq.w 8006118 <HAL_UART_IRQHandler+0x3e4>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8005fac: 687b ldr r3, [r7, #4]
|
|
8005fae: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005fb0: 681b ldr r3, [r3, #0]
|
|
8005fb2: 685b ldr r3, [r3, #4]
|
|
8005fb4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8005fb8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
8005fbc: 2b00 cmp r3, #0
|
|
8005fbe: f000 8145 beq.w 800624c <HAL_UART_IRQHandler+0x518>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
8005fc2: 687b ldr r3, [r7, #4]
|
|
8005fc4: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005fc6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005fca: 429a cmp r2, r3
|
|
8005fcc: f080 813e bcs.w 800624c <HAL_UART_IRQHandler+0x518>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
8005fd0: 687b ldr r3, [r7, #4]
|
|
8005fd2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005fd6: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
|
|
8005fd8: 687b ldr r3, [r7, #4]
|
|
8005fda: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005fdc: 699b ldr r3, [r3, #24]
|
|
8005fde: 2b20 cmp r3, #32
|
|
8005fe0: f000 8088 beq.w 80060f4 <HAL_UART_IRQHandler+0x3c0>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8005fe4: 687b ldr r3, [r7, #4]
|
|
8005fe6: 681b ldr r3, [r3, #0]
|
|
8005fe8: 330c adds r3, #12
|
|
8005fea: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005fee: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
8005ff2: e853 3f00 ldrex r3, [r3]
|
|
8005ff6: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8005ffa: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8005ffe: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8006002: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8006006: 687b ldr r3, [r7, #4]
|
|
8006008: 681b ldr r3, [r3, #0]
|
|
800600a: 330c adds r3, #12
|
|
800600c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
|
|
8006010: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
8006014: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006018: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
800601c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8006020: e841 2300 strex r3, r2, [r1]
|
|
8006024: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8006028: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800602c: 2b00 cmp r3, #0
|
|
800602e: d1d9 bne.n 8005fe4 <HAL_UART_IRQHandler+0x2b0>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006030: 687b ldr r3, [r7, #4]
|
|
8006032: 681b ldr r3, [r3, #0]
|
|
8006034: 3314 adds r3, #20
|
|
8006036: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006038: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800603a: e853 3f00 ldrex r3, [r3]
|
|
800603e: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8006040: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8006042: f023 0301 bic.w r3, r3, #1
|
|
8006046: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
800604a: 687b ldr r3, [r7, #4]
|
|
800604c: 681b ldr r3, [r3, #0]
|
|
800604e: 3314 adds r3, #20
|
|
8006050: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8006054: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
8006058: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800605a: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
800605c: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8006060: e841 2300 strex r3, r2, [r1]
|
|
8006064: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8006066: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006068: 2b00 cmp r3, #0
|
|
800606a: d1e1 bne.n 8006030 <HAL_UART_IRQHandler+0x2fc>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800606c: 687b ldr r3, [r7, #4]
|
|
800606e: 681b ldr r3, [r3, #0]
|
|
8006070: 3314 adds r3, #20
|
|
8006072: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006074: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006076: e853 3f00 ldrex r3, [r3]
|
|
800607a: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
800607c: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
800607e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8006082: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8006086: 687b ldr r3, [r7, #4]
|
|
8006088: 681b ldr r3, [r3, #0]
|
|
800608a: 3314 adds r3, #20
|
|
800608c: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
8006090: 66fa str r2, [r7, #108] @ 0x6c
|
|
8006092: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006094: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8006096: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8006098: e841 2300 strex r3, r2, [r1]
|
|
800609c: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
800609e: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80060a0: 2b00 cmp r3, #0
|
|
80060a2: d1e3 bne.n 800606c <HAL_UART_IRQHandler+0x338>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80060a4: 687b ldr r3, [r7, #4]
|
|
80060a6: 2220 movs r2, #32
|
|
80060a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80060ac: 687b ldr r3, [r7, #4]
|
|
80060ae: 2200 movs r2, #0
|
|
80060b0: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80060b2: 687b ldr r3, [r7, #4]
|
|
80060b4: 681b ldr r3, [r3, #0]
|
|
80060b6: 330c adds r3, #12
|
|
80060b8: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80060ba: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80060bc: e853 3f00 ldrex r3, [r3]
|
|
80060c0: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80060c2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80060c4: f023 0310 bic.w r3, r3, #16
|
|
80060c8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
80060cc: 687b ldr r3, [r7, #4]
|
|
80060ce: 681b ldr r3, [r3, #0]
|
|
80060d0: 330c adds r3, #12
|
|
80060d2: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
|
|
80060d6: 65ba str r2, [r7, #88] @ 0x58
|
|
80060d8: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80060da: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80060dc: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80060de: e841 2300 strex r3, r2, [r1]
|
|
80060e2: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80060e4: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80060e6: 2b00 cmp r3, #0
|
|
80060e8: d1e3 bne.n 80060b2 <HAL_UART_IRQHandler+0x37e>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
80060ea: 687b ldr r3, [r7, #4]
|
|
80060ec: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80060ee: 4618 mov r0, r3
|
|
80060f0: f7fd f9d7 bl 80034a2 <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80060f4: 687b ldr r3, [r7, #4]
|
|
80060f6: 2202 movs r2, #2
|
|
80060f8: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
80060fa: 687b ldr r3, [r7, #4]
|
|
80060fc: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
80060fe: 687b ldr r3, [r7, #4]
|
|
8006100: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006102: b29b uxth r3, r3
|
|
8006104: 1ad3 subs r3, r2, r3
|
|
8006106: b29b uxth r3, r3
|
|
8006108: 4619 mov r1, r3
|
|
800610a: 6878 ldr r0, [r7, #4]
|
|
800610c: f000 f8bf bl 800628e <HAL_UARTEx_RxEventCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
return;
|
|
8006110: e09c b.n 800624c <HAL_UART_IRQHandler+0x518>
|
|
8006112: bf00 nop
|
|
8006114: 0800641b .word 0x0800641b
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
8006118: 687b ldr r3, [r7, #4]
|
|
800611a: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
800611c: 687b ldr r3, [r7, #4]
|
|
800611e: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006120: b29b uxth r3, r3
|
|
8006122: 1ad3 subs r3, r2, r3
|
|
8006124: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
8006128: 687b ldr r3, [r7, #4]
|
|
800612a: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
800612c: b29b uxth r3, r3
|
|
800612e: 2b00 cmp r3, #0
|
|
8006130: f000 808e beq.w 8006250 <HAL_UART_IRQHandler+0x51c>
|
|
&& (nb_rx_data > 0U))
|
|
8006134: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8006138: 2b00 cmp r3, #0
|
|
800613a: f000 8089 beq.w 8006250 <HAL_UART_IRQHandler+0x51c>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800613e: 687b ldr r3, [r7, #4]
|
|
8006140: 681b ldr r3, [r3, #0]
|
|
8006142: 330c adds r3, #12
|
|
8006144: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006146: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006148: e853 3f00 ldrex r3, [r3]
|
|
800614c: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
800614e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006150: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006154: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8006158: 687b ldr r3, [r7, #4]
|
|
800615a: 681b ldr r3, [r3, #0]
|
|
800615c: 330c adds r3, #12
|
|
800615e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
|
|
8006162: 647a str r2, [r7, #68] @ 0x44
|
|
8006164: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006166: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006168: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800616a: e841 2300 strex r3, r2, [r1]
|
|
800616e: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006170: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006172: 2b00 cmp r3, #0
|
|
8006174: d1e3 bne.n 800613e <HAL_UART_IRQHandler+0x40a>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006176: 687b ldr r3, [r7, #4]
|
|
8006178: 681b ldr r3, [r3, #0]
|
|
800617a: 3314 adds r3, #20
|
|
800617c: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800617e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006180: e853 3f00 ldrex r3, [r3]
|
|
8006184: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006186: 6a3b ldr r3, [r7, #32]
|
|
8006188: f023 0301 bic.w r3, r3, #1
|
|
800618c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
8006190: 687b ldr r3, [r7, #4]
|
|
8006192: 681b ldr r3, [r3, #0]
|
|
8006194: 3314 adds r3, #20
|
|
8006196: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
800619a: 633a str r2, [r7, #48] @ 0x30
|
|
800619c: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800619e: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80061a0: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80061a2: e841 2300 strex r3, r2, [r1]
|
|
80061a6: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80061a8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80061aa: 2b00 cmp r3, #0
|
|
80061ac: d1e3 bne.n 8006176 <HAL_UART_IRQHandler+0x442>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80061ae: 687b ldr r3, [r7, #4]
|
|
80061b0: 2220 movs r2, #32
|
|
80061b2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80061b6: 687b ldr r3, [r7, #4]
|
|
80061b8: 2200 movs r2, #0
|
|
80061ba: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80061bc: 687b ldr r3, [r7, #4]
|
|
80061be: 681b ldr r3, [r3, #0]
|
|
80061c0: 330c adds r3, #12
|
|
80061c2: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80061c4: 693b ldr r3, [r7, #16]
|
|
80061c6: e853 3f00 ldrex r3, [r3]
|
|
80061ca: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80061cc: 68fb ldr r3, [r7, #12]
|
|
80061ce: f023 0310 bic.w r3, r3, #16
|
|
80061d2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
80061d6: 687b ldr r3, [r7, #4]
|
|
80061d8: 681b ldr r3, [r3, #0]
|
|
80061da: 330c adds r3, #12
|
|
80061dc: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
|
|
80061e0: 61fa str r2, [r7, #28]
|
|
80061e2: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80061e4: 69b9 ldr r1, [r7, #24]
|
|
80061e6: 69fa ldr r2, [r7, #28]
|
|
80061e8: e841 2300 strex r3, r2, [r1]
|
|
80061ec: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80061ee: 697b ldr r3, [r7, #20]
|
|
80061f0: 2b00 cmp r3, #0
|
|
80061f2: d1e3 bne.n 80061bc <HAL_UART_IRQHandler+0x488>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80061f4: 687b ldr r3, [r7, #4]
|
|
80061f6: 2202 movs r2, #2
|
|
80061f8: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
80061fa: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
80061fe: 4619 mov r1, r3
|
|
8006200: 6878 ldr r0, [r7, #4]
|
|
8006202: f000 f844 bl 800628e <HAL_UARTEx_RxEventCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
return;
|
|
8006206: e023 b.n 8006250 <HAL_UART_IRQHandler+0x51c>
|
|
}
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
|
|
8006208: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800620c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006210: 2b00 cmp r3, #0
|
|
8006212: d009 beq.n 8006228 <HAL_UART_IRQHandler+0x4f4>
|
|
8006214: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006218: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800621c: 2b00 cmp r3, #0
|
|
800621e: d003 beq.n 8006228 <HAL_UART_IRQHandler+0x4f4>
|
|
{
|
|
UART_Transmit_IT(huart);
|
|
8006220: 6878 ldr r0, [r7, #4]
|
|
8006222: f000 f90e bl 8006442 <UART_Transmit_IT>
|
|
return;
|
|
8006226: e014 b.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
}
|
|
|
|
/* UART in mode Transmitter end --------------------------------------------*/
|
|
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
|
|
8006228: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800622c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006230: 2b00 cmp r3, #0
|
|
8006232: d00e beq.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
8006234: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006238: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800623c: 2b00 cmp r3, #0
|
|
800623e: d008 beq.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
8006240: 6878 ldr r0, [r7, #4]
|
|
8006242: f000 f94d bl 80064e0 <UART_EndTransmit_IT>
|
|
return;
|
|
8006246: e004 b.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
return;
|
|
8006248: bf00 nop
|
|
800624a: e002 b.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
return;
|
|
800624c: bf00 nop
|
|
800624e: e000 b.n 8006252 <HAL_UART_IRQHandler+0x51e>
|
|
return;
|
|
8006250: bf00 nop
|
|
}
|
|
}
|
|
8006252: 37e8 adds r7, #232 @ 0xe8
|
|
8006254: 46bd mov sp, r7
|
|
8006256: bd80 pop {r7, pc}
|
|
|
|
08006258 <HAL_UART_TxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8006258: b480 push {r7}
|
|
800625a: b083 sub sp, #12
|
|
800625c: af00 add r7, sp, #0
|
|
800625e: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006260: bf00 nop
|
|
8006262: 370c adds r7, #12
|
|
8006264: 46bd mov sp, r7
|
|
8006266: bc80 pop {r7}
|
|
8006268: 4770 bx lr
|
|
|
|
0800626a <HAL_UART_RxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800626a: b480 push {r7}
|
|
800626c: b083 sub sp, #12
|
|
800626e: af00 add r7, sp, #0
|
|
8006270: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_RxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006272: bf00 nop
|
|
8006274: 370c adds r7, #12
|
|
8006276: 46bd mov sp, r7
|
|
8006278: bc80 pop {r7}
|
|
800627a: 4770 bx lr
|
|
|
|
0800627c <HAL_UART_ErrorCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800627c: b480 push {r7}
|
|
800627e: b083 sub sp, #12
|
|
8006280: af00 add r7, sp, #0
|
|
8006282: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006284: bf00 nop
|
|
8006286: 370c adds r7, #12
|
|
8006288: 46bd mov sp, r7
|
|
800628a: bc80 pop {r7}
|
|
800628c: 4770 bx lr
|
|
|
|
0800628e <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
800628e: b480 push {r7}
|
|
8006290: b083 sub sp, #12
|
|
8006292: af00 add r7, sp, #0
|
|
8006294: 6078 str r0, [r7, #4]
|
|
8006296: 460b mov r3, r1
|
|
8006298: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800629a: bf00 nop
|
|
800629c: 370c adds r7, #12
|
|
800629e: 46bd mov sp, r7
|
|
80062a0: bc80 pop {r7}
|
|
80062a2: 4770 bx lr
|
|
|
|
080062a4 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
80062a4: b580 push {r7, lr}
|
|
80062a6: b086 sub sp, #24
|
|
80062a8: af00 add r7, sp, #0
|
|
80062aa: 60f8 str r0, [r7, #12]
|
|
80062ac: 60b9 str r1, [r7, #8]
|
|
80062ae: 603b str r3, [r7, #0]
|
|
80062b0: 4613 mov r3, r2
|
|
80062b2: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
80062b4: e03b b.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80062b6: 6a3b ldr r3, [r7, #32]
|
|
80062b8: f1b3 3fff cmp.w r3, #4294967295
|
|
80062bc: d037 beq.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80062be: f7fc fdc7 bl 8002e50 <HAL_GetTick>
|
|
80062c2: 4602 mov r2, r0
|
|
80062c4: 683b ldr r3, [r7, #0]
|
|
80062c6: 1ad3 subs r3, r2, r3
|
|
80062c8: 6a3a ldr r2, [r7, #32]
|
|
80062ca: 429a cmp r2, r3
|
|
80062cc: d302 bcc.n 80062d4 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
80062ce: 6a3b ldr r3, [r7, #32]
|
|
80062d0: 2b00 cmp r3, #0
|
|
80062d2: d101 bne.n 80062d8 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
80062d4: 2303 movs r3, #3
|
|
80062d6: e03a b.n 800634e <UART_WaitOnFlagUntilTimeout+0xaa>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
80062d8: 68fb ldr r3, [r7, #12]
|
|
80062da: 681b ldr r3, [r3, #0]
|
|
80062dc: 68db ldr r3, [r3, #12]
|
|
80062de: f003 0304 and.w r3, r3, #4
|
|
80062e2: 2b00 cmp r3, #0
|
|
80062e4: d023 beq.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
80062e6: 68bb ldr r3, [r7, #8]
|
|
80062e8: 2b80 cmp r3, #128 @ 0x80
|
|
80062ea: d020 beq.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
80062ec: 68bb ldr r3, [r7, #8]
|
|
80062ee: 2b40 cmp r3, #64 @ 0x40
|
|
80062f0: d01d beq.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
80062f2: 68fb ldr r3, [r7, #12]
|
|
80062f4: 681b ldr r3, [r3, #0]
|
|
80062f6: 681b ldr r3, [r3, #0]
|
|
80062f8: f003 0308 and.w r3, r3, #8
|
|
80062fc: 2b08 cmp r3, #8
|
|
80062fe: d116 bne.n 800632e <UART_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_OREFLAG(huart);
|
|
8006300: 2300 movs r3, #0
|
|
8006302: 617b str r3, [r7, #20]
|
|
8006304: 68fb ldr r3, [r7, #12]
|
|
8006306: 681b ldr r3, [r3, #0]
|
|
8006308: 681b ldr r3, [r3, #0]
|
|
800630a: 617b str r3, [r7, #20]
|
|
800630c: 68fb ldr r3, [r7, #12]
|
|
800630e: 681b ldr r3, [r3, #0]
|
|
8006310: 685b ldr r3, [r3, #4]
|
|
8006312: 617b str r3, [r7, #20]
|
|
8006314: 697b ldr r3, [r7, #20]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006316: 68f8 ldr r0, [r7, #12]
|
|
8006318: f000 f81d bl 8006356 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
800631c: 68fb ldr r3, [r7, #12]
|
|
800631e: 2208 movs r2, #8
|
|
8006320: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006322: 68fb ldr r3, [r7, #12]
|
|
8006324: 2200 movs r2, #0
|
|
8006326: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
800632a: 2301 movs r3, #1
|
|
800632c: e00f b.n 800634e <UART_WaitOnFlagUntilTimeout+0xaa>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800632e: 68fb ldr r3, [r7, #12]
|
|
8006330: 681b ldr r3, [r3, #0]
|
|
8006332: 681a ldr r2, [r3, #0]
|
|
8006334: 68bb ldr r3, [r7, #8]
|
|
8006336: 4013 ands r3, r2
|
|
8006338: 68ba ldr r2, [r7, #8]
|
|
800633a: 429a cmp r2, r3
|
|
800633c: bf0c ite eq
|
|
800633e: 2301 moveq r3, #1
|
|
8006340: 2300 movne r3, #0
|
|
8006342: b2db uxtb r3, r3
|
|
8006344: 461a mov r2, r3
|
|
8006346: 79fb ldrb r3, [r7, #7]
|
|
8006348: 429a cmp r2, r3
|
|
800634a: d0b4 beq.n 80062b6 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800634c: 2300 movs r3, #0
|
|
}
|
|
800634e: 4618 mov r0, r3
|
|
8006350: 3718 adds r7, #24
|
|
8006352: 46bd mov sp, r7
|
|
8006354: bd80 pop {r7, pc}
|
|
|
|
08006356 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8006356: b480 push {r7}
|
|
8006358: b095 sub sp, #84 @ 0x54
|
|
800635a: af00 add r7, sp, #0
|
|
800635c: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800635e: 687b ldr r3, [r7, #4]
|
|
8006360: 681b ldr r3, [r3, #0]
|
|
8006362: 330c adds r3, #12
|
|
8006364: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006366: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006368: e853 3f00 ldrex r3, [r3]
|
|
800636c: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
800636e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006370: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006374: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006376: 687b ldr r3, [r7, #4]
|
|
8006378: 681b ldr r3, [r3, #0]
|
|
800637a: 330c adds r3, #12
|
|
800637c: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
800637e: 643a str r2, [r7, #64] @ 0x40
|
|
8006380: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006382: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006384: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006386: e841 2300 strex r3, r2, [r1]
|
|
800638a: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
800638c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800638e: 2b00 cmp r3, #0
|
|
8006390: d1e5 bne.n 800635e <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006392: 687b ldr r3, [r7, #4]
|
|
8006394: 681b ldr r3, [r3, #0]
|
|
8006396: 3314 adds r3, #20
|
|
8006398: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800639a: 6a3b ldr r3, [r7, #32]
|
|
800639c: e853 3f00 ldrex r3, [r3]
|
|
80063a0: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80063a2: 69fb ldr r3, [r7, #28]
|
|
80063a4: f023 0301 bic.w r3, r3, #1
|
|
80063a8: 64bb str r3, [r7, #72] @ 0x48
|
|
80063aa: 687b ldr r3, [r7, #4]
|
|
80063ac: 681b ldr r3, [r3, #0]
|
|
80063ae: 3314 adds r3, #20
|
|
80063b0: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80063b2: 62fa str r2, [r7, #44] @ 0x2c
|
|
80063b4: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80063b6: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
80063b8: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80063ba: e841 2300 strex r3, r2, [r1]
|
|
80063be: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
80063c0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80063c2: 2b00 cmp r3, #0
|
|
80063c4: d1e5 bne.n 8006392 <UART_EndRxTransfer+0x3c>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80063c6: 687b ldr r3, [r7, #4]
|
|
80063c8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80063ca: 2b01 cmp r3, #1
|
|
80063cc: d119 bne.n 8006402 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80063ce: 687b ldr r3, [r7, #4]
|
|
80063d0: 681b ldr r3, [r3, #0]
|
|
80063d2: 330c adds r3, #12
|
|
80063d4: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80063d6: 68fb ldr r3, [r7, #12]
|
|
80063d8: e853 3f00 ldrex r3, [r3]
|
|
80063dc: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80063de: 68bb ldr r3, [r7, #8]
|
|
80063e0: f023 0310 bic.w r3, r3, #16
|
|
80063e4: 647b str r3, [r7, #68] @ 0x44
|
|
80063e6: 687b ldr r3, [r7, #4]
|
|
80063e8: 681b ldr r3, [r3, #0]
|
|
80063ea: 330c adds r3, #12
|
|
80063ec: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80063ee: 61ba str r2, [r7, #24]
|
|
80063f0: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80063f2: 6979 ldr r1, [r7, #20]
|
|
80063f4: 69ba ldr r2, [r7, #24]
|
|
80063f6: e841 2300 strex r3, r2, [r1]
|
|
80063fa: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80063fc: 693b ldr r3, [r7, #16]
|
|
80063fe: 2b00 cmp r3, #0
|
|
8006400: d1e5 bne.n 80063ce <UART_EndRxTransfer+0x78>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006402: 687b ldr r3, [r7, #4]
|
|
8006404: 2220 movs r2, #32
|
|
8006406: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800640a: 687b ldr r3, [r7, #4]
|
|
800640c: 2200 movs r2, #0
|
|
800640e: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
8006410: bf00 nop
|
|
8006412: 3754 adds r7, #84 @ 0x54
|
|
8006414: 46bd mov sp, r7
|
|
8006416: bc80 pop {r7}
|
|
8006418: 4770 bx lr
|
|
|
|
0800641a <UART_DMAAbortOnError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800641a: b580 push {r7, lr}
|
|
800641c: b084 sub sp, #16
|
|
800641e: af00 add r7, sp, #0
|
|
8006420: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8006422: 687b ldr r3, [r7, #4]
|
|
8006424: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006426: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0x00U;
|
|
8006428: 68fb ldr r3, [r7, #12]
|
|
800642a: 2200 movs r2, #0
|
|
800642c: 85da strh r2, [r3, #46] @ 0x2e
|
|
huart->TxXferCount = 0x00U;
|
|
800642e: 68fb ldr r3, [r7, #12]
|
|
8006430: 2200 movs r2, #0
|
|
8006432: 84da strh r2, [r3, #38] @ 0x26
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006434: 68f8 ldr r0, [r7, #12]
|
|
8006436: f7ff ff21 bl 800627c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800643a: bf00 nop
|
|
800643c: 3710 adds r7, #16
|
|
800643e: 46bd mov sp, r7
|
|
8006440: bd80 pop {r7, pc}
|
|
|
|
08006442 <UART_Transmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006442: b480 push {r7}
|
|
8006444: b085 sub sp, #20
|
|
8006446: af00 add r7, sp, #0
|
|
8006448: 6078 str r0, [r7, #4]
|
|
const uint16_t *tmp;
|
|
|
|
/* Check that a Tx process is ongoing */
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
800644a: 687b ldr r3, [r7, #4]
|
|
800644c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006450: b2db uxtb r3, r3
|
|
8006452: 2b21 cmp r3, #33 @ 0x21
|
|
8006454: d13e bne.n 80064d4 <UART_Transmit_IT+0x92>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006456: 687b ldr r3, [r7, #4]
|
|
8006458: 689b ldr r3, [r3, #8]
|
|
800645a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800645e: d114 bne.n 800648a <UART_Transmit_IT+0x48>
|
|
8006460: 687b ldr r3, [r7, #4]
|
|
8006462: 691b ldr r3, [r3, #16]
|
|
8006464: 2b00 cmp r3, #0
|
|
8006466: d110 bne.n 800648a <UART_Transmit_IT+0x48>
|
|
{
|
|
tmp = (const uint16_t *) huart->pTxBuffPtr;
|
|
8006468: 687b ldr r3, [r7, #4]
|
|
800646a: 6a1b ldr r3, [r3, #32]
|
|
800646c: 60fb str r3, [r7, #12]
|
|
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
|
800646e: 68fb ldr r3, [r7, #12]
|
|
8006470: 881b ldrh r3, [r3, #0]
|
|
8006472: 461a mov r2, r3
|
|
8006474: 687b ldr r3, [r7, #4]
|
|
8006476: 681b ldr r3, [r3, #0]
|
|
8006478: f3c2 0208 ubfx r2, r2, #0, #9
|
|
800647c: 605a str r2, [r3, #4]
|
|
huart->pTxBuffPtr += 2U;
|
|
800647e: 687b ldr r3, [r7, #4]
|
|
8006480: 6a1b ldr r3, [r3, #32]
|
|
8006482: 1c9a adds r2, r3, #2
|
|
8006484: 687b ldr r3, [r7, #4]
|
|
8006486: 621a str r2, [r3, #32]
|
|
8006488: e008 b.n 800649c <UART_Transmit_IT+0x5a>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
|
|
800648a: 687b ldr r3, [r7, #4]
|
|
800648c: 6a1b ldr r3, [r3, #32]
|
|
800648e: 1c59 adds r1, r3, #1
|
|
8006490: 687a ldr r2, [r7, #4]
|
|
8006492: 6211 str r1, [r2, #32]
|
|
8006494: 781a ldrb r2, [r3, #0]
|
|
8006496: 687b ldr r3, [r7, #4]
|
|
8006498: 681b ldr r3, [r3, #0]
|
|
800649a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if (--huart->TxXferCount == 0U)
|
|
800649c: 687b ldr r3, [r7, #4]
|
|
800649e: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
80064a0: b29b uxth r3, r3
|
|
80064a2: 3b01 subs r3, #1
|
|
80064a4: b29b uxth r3, r3
|
|
80064a6: 687a ldr r2, [r7, #4]
|
|
80064a8: 4619 mov r1, r3
|
|
80064aa: 84d1 strh r1, [r2, #38] @ 0x26
|
|
80064ac: 2b00 cmp r3, #0
|
|
80064ae: d10f bne.n 80064d0 <UART_Transmit_IT+0x8e>
|
|
{
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
|
|
80064b0: 687b ldr r3, [r7, #4]
|
|
80064b2: 681b ldr r3, [r3, #0]
|
|
80064b4: 68da ldr r2, [r3, #12]
|
|
80064b6: 687b ldr r3, [r7, #4]
|
|
80064b8: 681b ldr r3, [r3, #0]
|
|
80064ba: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
80064be: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
|
|
80064c0: 687b ldr r3, [r7, #4]
|
|
80064c2: 681b ldr r3, [r3, #0]
|
|
80064c4: 68da ldr r2, [r3, #12]
|
|
80064c6: 687b ldr r3, [r7, #4]
|
|
80064c8: 681b ldr r3, [r3, #0]
|
|
80064ca: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80064ce: 60da str r2, [r3, #12]
|
|
}
|
|
return HAL_OK;
|
|
80064d0: 2300 movs r3, #0
|
|
80064d2: e000 b.n 80064d6 <UART_Transmit_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80064d4: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80064d6: 4618 mov r0, r3
|
|
80064d8: 3714 adds r7, #20
|
|
80064da: 46bd mov sp, r7
|
|
80064dc: bc80 pop {r7}
|
|
80064de: 4770 bx lr
|
|
|
|
080064e0 <UART_EndTransmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
80064e0: b580 push {r7, lr}
|
|
80064e2: b082 sub sp, #8
|
|
80064e4: af00 add r7, sp, #0
|
|
80064e6: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
|
|
80064e8: 687b ldr r3, [r7, #4]
|
|
80064ea: 681b ldr r3, [r3, #0]
|
|
80064ec: 68da ldr r2, [r3, #12]
|
|
80064ee: 687b ldr r3, [r7, #4]
|
|
80064f0: 681b ldr r3, [r3, #0]
|
|
80064f2: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80064f6: 60da str r2, [r3, #12]
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80064f8: 687b ldr r3, [r7, #4]
|
|
80064fa: 2220 movs r2, #32
|
|
80064fc: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8006500: 6878 ldr r0, [r7, #4]
|
|
8006502: f7ff fea9 bl 8006258 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
return HAL_OK;
|
|
8006506: 2300 movs r3, #0
|
|
}
|
|
8006508: 4618 mov r0, r3
|
|
800650a: 3708 adds r7, #8
|
|
800650c: 46bd mov sp, r7
|
|
800650e: bd80 pop {r7, pc}
|
|
|
|
08006510 <UART_Receive_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006510: b580 push {r7, lr}
|
|
8006512: b08c sub sp, #48 @ 0x30
|
|
8006514: af00 add r7, sp, #0
|
|
8006516: 6078 str r0, [r7, #4]
|
|
uint8_t *pdata8bits;
|
|
uint16_t *pdata16bits;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006518: 687b ldr r3, [r7, #4]
|
|
800651a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
800651e: b2db uxtb r3, r3
|
|
8006520: 2b22 cmp r3, #34 @ 0x22
|
|
8006522: f040 80ae bne.w 8006682 <UART_Receive_IT+0x172>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006526: 687b ldr r3, [r7, #4]
|
|
8006528: 689b ldr r3, [r3, #8]
|
|
800652a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800652e: d117 bne.n 8006560 <UART_Receive_IT+0x50>
|
|
8006530: 687b ldr r3, [r7, #4]
|
|
8006532: 691b ldr r3, [r3, #16]
|
|
8006534: 2b00 cmp r3, #0
|
|
8006536: d113 bne.n 8006560 <UART_Receive_IT+0x50>
|
|
{
|
|
pdata8bits = NULL;
|
|
8006538: 2300 movs r3, #0
|
|
800653a: 62fb str r3, [r7, #44] @ 0x2c
|
|
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
|
|
800653c: 687b ldr r3, [r7, #4]
|
|
800653e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006540: 62bb str r3, [r7, #40] @ 0x28
|
|
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
|
8006542: 687b ldr r3, [r7, #4]
|
|
8006544: 681b ldr r3, [r3, #0]
|
|
8006546: 685b ldr r3, [r3, #4]
|
|
8006548: b29b uxth r3, r3
|
|
800654a: f3c3 0308 ubfx r3, r3, #0, #9
|
|
800654e: b29a uxth r2, r3
|
|
8006550: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006552: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
8006554: 687b ldr r3, [r7, #4]
|
|
8006556: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006558: 1c9a adds r2, r3, #2
|
|
800655a: 687b ldr r3, [r7, #4]
|
|
800655c: 629a str r2, [r3, #40] @ 0x28
|
|
800655e: e026 b.n 80065ae <UART_Receive_IT+0x9e>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
|
|
8006560: 687b ldr r3, [r7, #4]
|
|
8006562: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006564: 62fb str r3, [r7, #44] @ 0x2c
|
|
pdata16bits = NULL;
|
|
8006566: 2300 movs r3, #0
|
|
8006568: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
|
|
800656a: 687b ldr r3, [r7, #4]
|
|
800656c: 689b ldr r3, [r3, #8]
|
|
800656e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006572: d007 beq.n 8006584 <UART_Receive_IT+0x74>
|
|
8006574: 687b ldr r3, [r7, #4]
|
|
8006576: 689b ldr r3, [r3, #8]
|
|
8006578: 2b00 cmp r3, #0
|
|
800657a: d10a bne.n 8006592 <UART_Receive_IT+0x82>
|
|
800657c: 687b ldr r3, [r7, #4]
|
|
800657e: 691b ldr r3, [r3, #16]
|
|
8006580: 2b00 cmp r3, #0
|
|
8006582: d106 bne.n 8006592 <UART_Receive_IT+0x82>
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
|
8006584: 687b ldr r3, [r7, #4]
|
|
8006586: 681b ldr r3, [r3, #0]
|
|
8006588: 685b ldr r3, [r3, #4]
|
|
800658a: b2da uxtb r2, r3
|
|
800658c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800658e: 701a strb r2, [r3, #0]
|
|
8006590: e008 b.n 80065a4 <UART_Receive_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
|
8006592: 687b ldr r3, [r7, #4]
|
|
8006594: 681b ldr r3, [r3, #0]
|
|
8006596: 685b ldr r3, [r3, #4]
|
|
8006598: b2db uxtb r3, r3
|
|
800659a: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
800659e: b2da uxtb r2, r3
|
|
80065a0: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80065a2: 701a strb r2, [r3, #0]
|
|
}
|
|
huart->pRxBuffPtr += 1U;
|
|
80065a4: 687b ldr r3, [r7, #4]
|
|
80065a6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80065a8: 1c5a adds r2, r3, #1
|
|
80065aa: 687b ldr r3, [r7, #4]
|
|
80065ac: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
if (--huart->RxXferCount == 0U)
|
|
80065ae: 687b ldr r3, [r7, #4]
|
|
80065b0: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
80065b2: b29b uxth r3, r3
|
|
80065b4: 3b01 subs r3, #1
|
|
80065b6: b29b uxth r3, r3
|
|
80065b8: 687a ldr r2, [r7, #4]
|
|
80065ba: 4619 mov r1, r3
|
|
80065bc: 85d1 strh r1, [r2, #46] @ 0x2e
|
|
80065be: 2b00 cmp r3, #0
|
|
80065c0: d15d bne.n 800667e <UART_Receive_IT+0x16e>
|
|
{
|
|
/* Disable the UART Data Register not empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
|
|
80065c2: 687b ldr r3, [r7, #4]
|
|
80065c4: 681b ldr r3, [r3, #0]
|
|
80065c6: 68da ldr r2, [r3, #12]
|
|
80065c8: 687b ldr r3, [r7, #4]
|
|
80065ca: 681b ldr r3, [r3, #0]
|
|
80065cc: f022 0220 bic.w r2, r2, #32
|
|
80065d0: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Parity Error Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
|
|
80065d2: 687b ldr r3, [r7, #4]
|
|
80065d4: 681b ldr r3, [r3, #0]
|
|
80065d6: 68da ldr r2, [r3, #12]
|
|
80065d8: 687b ldr r3, [r7, #4]
|
|
80065da: 681b ldr r3, [r3, #0]
|
|
80065dc: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
80065e0: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
|
|
80065e2: 687b ldr r3, [r7, #4]
|
|
80065e4: 681b ldr r3, [r3, #0]
|
|
80065e6: 695a ldr r2, [r3, #20]
|
|
80065e8: 687b ldr r3, [r7, #4]
|
|
80065ea: 681b ldr r3, [r3, #0]
|
|
80065ec: f022 0201 bic.w r2, r2, #1
|
|
80065f0: 615a str r2, [r3, #20]
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80065f2: 687b ldr r3, [r7, #4]
|
|
80065f4: 2220 movs r2, #32
|
|
80065f6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80065fa: 687b ldr r3, [r7, #4]
|
|
80065fc: 2200 movs r2, #0
|
|
80065fe: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006600: 687b ldr r3, [r7, #4]
|
|
8006602: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006604: 2b01 cmp r3, #1
|
|
8006606: d135 bne.n 8006674 <UART_Receive_IT+0x164>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006608: 687b ldr r3, [r7, #4]
|
|
800660a: 2200 movs r2, #0
|
|
800660c: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800660e: 687b ldr r3, [r7, #4]
|
|
8006610: 681b ldr r3, [r3, #0]
|
|
8006612: 330c adds r3, #12
|
|
8006614: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006616: 697b ldr r3, [r7, #20]
|
|
8006618: e853 3f00 ldrex r3, [r3]
|
|
800661c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800661e: 693b ldr r3, [r7, #16]
|
|
8006620: f023 0310 bic.w r3, r3, #16
|
|
8006624: 627b str r3, [r7, #36] @ 0x24
|
|
8006626: 687b ldr r3, [r7, #4]
|
|
8006628: 681b ldr r3, [r3, #0]
|
|
800662a: 330c adds r3, #12
|
|
800662c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800662e: 623a str r2, [r7, #32]
|
|
8006630: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006632: 69f9 ldr r1, [r7, #28]
|
|
8006634: 6a3a ldr r2, [r7, #32]
|
|
8006636: e841 2300 strex r3, r2, [r1]
|
|
800663a: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
800663c: 69bb ldr r3, [r7, #24]
|
|
800663e: 2b00 cmp r3, #0
|
|
8006640: d1e5 bne.n 800660e <UART_Receive_IT+0xfe>
|
|
|
|
/* Check if IDLE flag is set */
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
|
8006642: 687b ldr r3, [r7, #4]
|
|
8006644: 681b ldr r3, [r3, #0]
|
|
8006646: 681b ldr r3, [r3, #0]
|
|
8006648: f003 0310 and.w r3, r3, #16
|
|
800664c: 2b10 cmp r3, #16
|
|
800664e: d10a bne.n 8006666 <UART_Receive_IT+0x156>
|
|
{
|
|
/* Clear IDLE flag in ISR */
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
8006650: 2300 movs r3, #0
|
|
8006652: 60fb str r3, [r7, #12]
|
|
8006654: 687b ldr r3, [r7, #4]
|
|
8006656: 681b ldr r3, [r3, #0]
|
|
8006658: 681b ldr r3, [r3, #0]
|
|
800665a: 60fb str r3, [r7, #12]
|
|
800665c: 687b ldr r3, [r7, #4]
|
|
800665e: 681b ldr r3, [r3, #0]
|
|
8006660: 685b ldr r3, [r3, #4]
|
|
8006662: 60fb str r3, [r7, #12]
|
|
8006664: 68fb ldr r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8006666: 687b ldr r3, [r7, #4]
|
|
8006668: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
800666a: 4619 mov r1, r3
|
|
800666c: 6878 ldr r0, [r7, #4]
|
|
800666e: f7ff fe0e bl 800628e <HAL_UARTEx_RxEventCallback>
|
|
8006672: e002 b.n 800667a <UART_Receive_IT+0x16a>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8006674: 6878 ldr r0, [r7, #4]
|
|
8006676: f7ff fdf8 bl 800626a <HAL_UART_RxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
return HAL_OK;
|
|
800667a: 2300 movs r3, #0
|
|
800667c: e002 b.n 8006684 <UART_Receive_IT+0x174>
|
|
}
|
|
return HAL_OK;
|
|
800667e: 2300 movs r3, #0
|
|
8006680: e000 b.n 8006684 <UART_Receive_IT+0x174>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006682: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006684: 4618 mov r0, r3
|
|
8006686: 3730 adds r7, #48 @ 0x30
|
|
8006688: 46bd mov sp, r7
|
|
800668a: bd80 pop {r7, pc}
|
|
|
|
0800668c <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800668c: b580 push {r7, lr}
|
|
800668e: b084 sub sp, #16
|
|
8006690: af00 add r7, sp, #0
|
|
8006692: 6078 str r0, [r7, #4]
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8006694: 687b ldr r3, [r7, #4]
|
|
8006696: 681b ldr r3, [r3, #0]
|
|
8006698: 691b ldr r3, [r3, #16]
|
|
800669a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
800669e: 687b ldr r3, [r7, #4]
|
|
80066a0: 68da ldr r2, [r3, #12]
|
|
80066a2: 687b ldr r3, [r7, #4]
|
|
80066a4: 681b ldr r3, [r3, #0]
|
|
80066a6: 430a orrs r2, r1
|
|
80066a8: 611a str r2, [r3, #16]
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
#else
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
|
|
80066aa: 687b ldr r3, [r7, #4]
|
|
80066ac: 689a ldr r2, [r3, #8]
|
|
80066ae: 687b ldr r3, [r7, #4]
|
|
80066b0: 691b ldr r3, [r3, #16]
|
|
80066b2: 431a orrs r2, r3
|
|
80066b4: 687b ldr r3, [r7, #4]
|
|
80066b6: 695b ldr r3, [r3, #20]
|
|
80066b8: 4313 orrs r3, r2
|
|
80066ba: 60bb str r3, [r7, #8]
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
80066bc: 687b ldr r3, [r7, #4]
|
|
80066be: 681b ldr r3, [r3, #0]
|
|
80066c0: 68db ldr r3, [r3, #12]
|
|
80066c2: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
|
|
80066c6: f023 030c bic.w r3, r3, #12
|
|
80066ca: 687a ldr r2, [r7, #4]
|
|
80066cc: 6812 ldr r2, [r2, #0]
|
|
80066ce: 68b9 ldr r1, [r7, #8]
|
|
80066d0: 430b orrs r3, r1
|
|
80066d2: 60d3 str r3, [r2, #12]
|
|
tmpreg);
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
80066d4: 687b ldr r3, [r7, #4]
|
|
80066d6: 681b ldr r3, [r3, #0]
|
|
80066d8: 695b ldr r3, [r3, #20]
|
|
80066da: f423 7140 bic.w r1, r3, #768 @ 0x300
|
|
80066de: 687b ldr r3, [r7, #4]
|
|
80066e0: 699a ldr r2, [r3, #24]
|
|
80066e2: 687b ldr r3, [r7, #4]
|
|
80066e4: 681b ldr r3, [r3, #0]
|
|
80066e6: 430a orrs r2, r1
|
|
80066e8: 615a str r2, [r3, #20]
|
|
|
|
|
|
if(huart->Instance == USART1)
|
|
80066ea: 687b ldr r3, [r7, #4]
|
|
80066ec: 681b ldr r3, [r3, #0]
|
|
80066ee: 4a2c ldr r2, [pc, #176] @ (80067a0 <UART_SetConfig+0x114>)
|
|
80066f0: 4293 cmp r3, r2
|
|
80066f2: d103 bne.n 80066fc <UART_SetConfig+0x70>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
80066f4: f7fe fd68 bl 80051c8 <HAL_RCC_GetPCLK2Freq>
|
|
80066f8: 60f8 str r0, [r7, #12]
|
|
80066fa: e002 b.n 8006702 <UART_SetConfig+0x76>
|
|
}
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80066fc: f7fe fd50 bl 80051a0 <HAL_RCC_GetPCLK1Freq>
|
|
8006700: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
#else
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8006702: 68fa ldr r2, [r7, #12]
|
|
8006704: 4613 mov r3, r2
|
|
8006706: 009b lsls r3, r3, #2
|
|
8006708: 4413 add r3, r2
|
|
800670a: 009a lsls r2, r3, #2
|
|
800670c: 441a add r2, r3
|
|
800670e: 687b ldr r3, [r7, #4]
|
|
8006710: 685b ldr r3, [r3, #4]
|
|
8006712: 009b lsls r3, r3, #2
|
|
8006714: fbb2 f3f3 udiv r3, r2, r3
|
|
8006718: 4a22 ldr r2, [pc, #136] @ (80067a4 <UART_SetConfig+0x118>)
|
|
800671a: fba2 2303 umull r2, r3, r2, r3
|
|
800671e: 095b lsrs r3, r3, #5
|
|
8006720: 0119 lsls r1, r3, #4
|
|
8006722: 68fa ldr r2, [r7, #12]
|
|
8006724: 4613 mov r3, r2
|
|
8006726: 009b lsls r3, r3, #2
|
|
8006728: 4413 add r3, r2
|
|
800672a: 009a lsls r2, r3, #2
|
|
800672c: 441a add r2, r3
|
|
800672e: 687b ldr r3, [r7, #4]
|
|
8006730: 685b ldr r3, [r3, #4]
|
|
8006732: 009b lsls r3, r3, #2
|
|
8006734: fbb2 f2f3 udiv r2, r2, r3
|
|
8006738: 4b1a ldr r3, [pc, #104] @ (80067a4 <UART_SetConfig+0x118>)
|
|
800673a: fba3 0302 umull r0, r3, r3, r2
|
|
800673e: 095b lsrs r3, r3, #5
|
|
8006740: 2064 movs r0, #100 @ 0x64
|
|
8006742: fb00 f303 mul.w r3, r0, r3
|
|
8006746: 1ad3 subs r3, r2, r3
|
|
8006748: 011b lsls r3, r3, #4
|
|
800674a: 3332 adds r3, #50 @ 0x32
|
|
800674c: 4a15 ldr r2, [pc, #84] @ (80067a4 <UART_SetConfig+0x118>)
|
|
800674e: fba2 2303 umull r2, r3, r2, r3
|
|
8006752: 095b lsrs r3, r3, #5
|
|
8006754: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8006758: 4419 add r1, r3
|
|
800675a: 68fa ldr r2, [r7, #12]
|
|
800675c: 4613 mov r3, r2
|
|
800675e: 009b lsls r3, r3, #2
|
|
8006760: 4413 add r3, r2
|
|
8006762: 009a lsls r2, r3, #2
|
|
8006764: 441a add r2, r3
|
|
8006766: 687b ldr r3, [r7, #4]
|
|
8006768: 685b ldr r3, [r3, #4]
|
|
800676a: 009b lsls r3, r3, #2
|
|
800676c: fbb2 f2f3 udiv r2, r2, r3
|
|
8006770: 4b0c ldr r3, [pc, #48] @ (80067a4 <UART_SetConfig+0x118>)
|
|
8006772: fba3 0302 umull r0, r3, r3, r2
|
|
8006776: 095b lsrs r3, r3, #5
|
|
8006778: 2064 movs r0, #100 @ 0x64
|
|
800677a: fb00 f303 mul.w r3, r0, r3
|
|
800677e: 1ad3 subs r3, r2, r3
|
|
8006780: 011b lsls r3, r3, #4
|
|
8006782: 3332 adds r3, #50 @ 0x32
|
|
8006784: 4a07 ldr r2, [pc, #28] @ (80067a4 <UART_SetConfig+0x118>)
|
|
8006786: fba2 2303 umull r2, r3, r2, r3
|
|
800678a: 095b lsrs r3, r3, #5
|
|
800678c: f003 020f and.w r2, r3, #15
|
|
8006790: 687b ldr r3, [r7, #4]
|
|
8006792: 681b ldr r3, [r3, #0]
|
|
8006794: 440a add r2, r1
|
|
8006796: 609a str r2, [r3, #8]
|
|
#endif /* USART_CR1_OVER8 */
|
|
}
|
|
8006798: bf00 nop
|
|
800679a: 3710 adds r7, #16
|
|
800679c: 46bd mov sp, r7
|
|
800679e: bd80 pop {r7, pc}
|
|
80067a0: 40013800 .word 0x40013800
|
|
80067a4: 51eb851f .word 0x51eb851f
|
|
|
|
080067a8 <memset>:
|
|
80067a8: 4603 mov r3, r0
|
|
80067aa: 4402 add r2, r0
|
|
80067ac: 4293 cmp r3, r2
|
|
80067ae: d100 bne.n 80067b2 <memset+0xa>
|
|
80067b0: 4770 bx lr
|
|
80067b2: f803 1b01 strb.w r1, [r3], #1
|
|
80067b6: e7f9 b.n 80067ac <memset+0x4>
|
|
|
|
080067b8 <__errno>:
|
|
80067b8: 4b01 ldr r3, [pc, #4] @ (80067c0 <__errno+0x8>)
|
|
80067ba: 6818 ldr r0, [r3, #0]
|
|
80067bc: 4770 bx lr
|
|
80067be: bf00 nop
|
|
80067c0: 20000014 .word 0x20000014
|
|
|
|
080067c4 <__libc_init_array>:
|
|
80067c4: b570 push {r4, r5, r6, lr}
|
|
80067c6: 2600 movs r6, #0
|
|
80067c8: 4d0c ldr r5, [pc, #48] @ (80067fc <__libc_init_array+0x38>)
|
|
80067ca: 4b0d ldr r3, [pc, #52] @ (8006800 <__libc_init_array+0x3c>)
|
|
80067cc: 1b5b subs r3, r3, r5
|
|
80067ce: 109c asrs r4, r3, #2
|
|
80067d0: 42a6 cmp r6, r4
|
|
80067d2: d109 bne.n 80067e8 <__libc_init_array+0x24>
|
|
80067d4: 2600 movs r6, #0
|
|
80067d6: f000 f8b7 bl 8006948 <_init>
|
|
80067da: 4d0a ldr r5, [pc, #40] @ (8006804 <__libc_init_array+0x40>)
|
|
80067dc: 4b0a ldr r3, [pc, #40] @ (8006808 <__libc_init_array+0x44>)
|
|
80067de: 1b5b subs r3, r3, r5
|
|
80067e0: 109c asrs r4, r3, #2
|
|
80067e2: 42a6 cmp r6, r4
|
|
80067e4: d105 bne.n 80067f2 <__libc_init_array+0x2e>
|
|
80067e6: bd70 pop {r4, r5, r6, pc}
|
|
80067e8: f855 3b04 ldr.w r3, [r5], #4
|
|
80067ec: 4798 blx r3
|
|
80067ee: 3601 adds r6, #1
|
|
80067f0: e7ee b.n 80067d0 <__libc_init_array+0xc>
|
|
80067f2: f855 3b04 ldr.w r3, [r5], #4
|
|
80067f6: 4798 blx r3
|
|
80067f8: 3601 adds r6, #1
|
|
80067fa: e7f2 b.n 80067e2 <__libc_init_array+0x1e>
|
|
80067fc: 08006aa4 .word 0x08006aa4
|
|
8006800: 08006aa4 .word 0x08006aa4
|
|
8006804: 08006aa4 .word 0x08006aa4
|
|
8006808: 08006aa8 .word 0x08006aa8
|
|
|
|
0800680c <memcpy>:
|
|
800680c: 440a add r2, r1
|
|
800680e: 4291 cmp r1, r2
|
|
8006810: f100 33ff add.w r3, r0, #4294967295
|
|
8006814: d100 bne.n 8006818 <memcpy+0xc>
|
|
8006816: 4770 bx lr
|
|
8006818: b510 push {r4, lr}
|
|
800681a: f811 4b01 ldrb.w r4, [r1], #1
|
|
800681e: 4291 cmp r1, r2
|
|
8006820: f803 4f01 strb.w r4, [r3, #1]!
|
|
8006824: d1f9 bne.n 800681a <memcpy+0xe>
|
|
8006826: bd10 pop {r4, pc}
|
|
|
|
08006828 <sqrtf>:
|
|
8006828: b538 push {r3, r4, r5, lr}
|
|
800682a: 4604 mov r4, r0
|
|
800682c: f000 f81a bl 8006864 <__ieee754_sqrtf>
|
|
8006830: 4621 mov r1, r4
|
|
8006832: 4605 mov r5, r0
|
|
8006834: 4620 mov r0, r4
|
|
8006836: f7fa fafb bl 8000e30 <__aeabi_fcmpun>
|
|
800683a: b920 cbnz r0, 8006846 <sqrtf+0x1e>
|
|
800683c: 4620 mov r0, r4
|
|
800683e: 2100 movs r1, #0
|
|
8006840: f7fa face bl 8000de0 <__aeabi_fcmplt>
|
|
8006844: b908 cbnz r0, 800684a <sqrtf+0x22>
|
|
8006846: 4628 mov r0, r5
|
|
8006848: bd38 pop {r3, r4, r5, pc}
|
|
800684a: f7ff ffb5 bl 80067b8 <__errno>
|
|
800684e: 2221 movs r2, #33 @ 0x21
|
|
8006850: 4603 mov r3, r0
|
|
8006852: 2100 movs r1, #0
|
|
8006854: 601a str r2, [r3, #0]
|
|
8006856: 4608 mov r0, r1
|
|
8006858: f7fa f9d8 bl 8000c0c <__aeabi_fdiv>
|
|
800685c: 4605 mov r5, r0
|
|
800685e: 4628 mov r0, r5
|
|
8006860: bd38 pop {r3, r4, r5, pc}
|
|
8006862: bf00 nop
|
|
|
|
08006864 <__ieee754_sqrtf>:
|
|
8006864: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000
|
|
8006868: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000
|
|
800686c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8006870: 4604 mov r4, r0
|
|
8006872: d24f bcs.n 8006914 <__ieee754_sqrtf+0xb0>
|
|
8006874: 2a00 cmp r2, #0
|
|
8006876: d04b beq.n 8006910 <__ieee754_sqrtf+0xac>
|
|
8006878: 2800 cmp r0, #0
|
|
800687a: 4603 mov r3, r0
|
|
800687c: db54 blt.n 8006928 <__ieee754_sqrtf+0xc4>
|
|
800687e: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000
|
|
8006882: d14f bne.n 8006924 <__ieee754_sqrtf+0xc0>
|
|
8006884: 005b lsls r3, r3, #1
|
|
8006886: 0218 lsls r0, r3, #8
|
|
8006888: 4611 mov r1, r2
|
|
800688a: f102 0201 add.w r2, r2, #1
|
|
800688e: d5f9 bpl.n 8006884 <__ieee754_sqrtf+0x20>
|
|
8006890: 4249 negs r1, r1
|
|
8006892: 2400 movs r4, #0
|
|
8006894: f3c3 0216 ubfx r2, r3, #0, #23
|
|
8006898: f1a1 057f sub.w r5, r1, #127 @ 0x7f
|
|
800689c: 07cb lsls r3, r1, #31
|
|
800689e: f04f 0e19 mov.w lr, #25
|
|
80068a2: f04f 7c80 mov.w ip, #16777216 @ 0x1000000
|
|
80068a6: 4621 mov r1, r4
|
|
80068a8: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
|
|
80068ac: bf58 it pl
|
|
80068ae: 0052 lslpl r2, r2, #1
|
|
80068b0: 106d asrs r5, r5, #1
|
|
80068b2: 0052 lsls r2, r2, #1
|
|
80068b4: eb01 030c add.w r3, r1, ip
|
|
80068b8: 4293 cmp r3, r2
|
|
80068ba: bfcf iteee gt
|
|
80068bc: 4613 movgt r3, r2
|
|
80068be: eb03 010c addle.w r1, r3, ip
|
|
80068c2: 4464 addle r4, ip
|
|
80068c4: 1ad3 suble r3, r2, r3
|
|
80068c6: f1be 0e01 subs.w lr, lr, #1
|
|
80068ca: ea4f 0243 mov.w r2, r3, lsl #1
|
|
80068ce: ea4f 0c5c mov.w ip, ip, lsr #1
|
|
80068d2: d1ef bne.n 80068b4 <__ieee754_sqrtf+0x50>
|
|
80068d4: b1bb cbz r3, 8006906 <__ieee754_sqrtf+0xa2>
|
|
80068d6: 4e1a ldr r6, [pc, #104] @ (8006940 <__ieee754_sqrtf+0xdc>)
|
|
80068d8: 4f1a ldr r7, [pc, #104] @ (8006944 <__ieee754_sqrtf+0xe0>)
|
|
80068da: 6830 ldr r0, [r6, #0]
|
|
80068dc: 6839 ldr r1, [r7, #0]
|
|
80068de: f7f9 ffd7 bl 8000890 <__aeabi_fsub>
|
|
80068e2: f8d6 8000 ldr.w r8, [r6]
|
|
80068e6: 4601 mov r1, r0
|
|
80068e8: 4640 mov r0, r8
|
|
80068ea: f7fa fa83 bl 8000df4 <__aeabi_fcmple>
|
|
80068ee: b150 cbz r0, 8006906 <__ieee754_sqrtf+0xa2>
|
|
80068f0: 6830 ldr r0, [r6, #0]
|
|
80068f2: 6839 ldr r1, [r7, #0]
|
|
80068f4: f7f9 ffce bl 8000894 <__addsf3>
|
|
80068f8: 6836 ldr r6, [r6, #0]
|
|
80068fa: 4601 mov r1, r0
|
|
80068fc: 4630 mov r0, r6
|
|
80068fe: f7fa fa6f bl 8000de0 <__aeabi_fcmplt>
|
|
8006902: b1c8 cbz r0, 8006938 <__ieee754_sqrtf+0xd4>
|
|
8006904: 3402 adds r4, #2
|
|
8006906: 1060 asrs r0, r4, #1
|
|
8006908: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000
|
|
800690c: eb00 50c5 add.w r0, r0, r5, lsl #23
|
|
8006910: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8006914: 4601 mov r1, r0
|
|
8006916: f7fa f8c5 bl 8000aa4 <__aeabi_fmul>
|
|
800691a: 4621 mov r1, r4
|
|
800691c: f7f9 ffba bl 8000894 <__addsf3>
|
|
8006920: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
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8006924: 15c1 asrs r1, r0, #23
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8006926: e7b4 b.n 8006892 <__ieee754_sqrtf+0x2e>
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8006928: 4601 mov r1, r0
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|
800692a: f7f9 ffb1 bl 8000890 <__aeabi_fsub>
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800692e: 4601 mov r1, r0
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8006930: f7fa f96c bl 8000c0c <__aeabi_fdiv>
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8006934: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
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|
8006938: 3401 adds r4, #1
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|
800693a: f024 0401 bic.w r4, r4, #1
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|
800693e: e7e2 b.n 8006906 <__ieee754_sqrtf+0xa2>
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|
8006940: 08006a98 .word 0x08006a98
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8006944: 08006a94 .word 0x08006a94
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|
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|
08006948 <_init>:
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|
8006948: b5f8 push {r3, r4, r5, r6, r7, lr}
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800694a: bf00 nop
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|
800694c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800694e: bc08 pop {r3}
|
|
8006950: 469e mov lr, r3
|
|
8006952: 4770 bx lr
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|
|
|
08006954 <_fini>:
|
|
8006954: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8006956: bf00 nop
|
|
8006958: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800695a: bc08 pop {r3}
|
|
800695c: 469e mov lr, r3
|
|
800695e: 4770 bx lr
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