: /** * @brief The application entry point. * @retval int */ int main(void) { 8001bb8: b580 push {r7, lr} 8001bba: b08c sub sp, #48 @ 0x30 8001bbc: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ uint8_t tempString[15] = {0}; 8001bbe: 1d3b adds r3, r7, #4 8001bc0: 2200 movs r2, #0 8001bc2: 601a str r2, [r3, #0] 8001bc4: 605a str r2, [r3, #4] 8001bc6: 609a str r2, [r3, #8] 8001bc8: f8c3 200b str.w r2, [r3, #11] uint8_t averages = 0; 8001bcc: 2300 movs r3, #0 8001bce: f887 302f strb.w r3, [r7, #47] @ 0x2f uint8_t newline = '\n'; 8001bd2: 230a movs r3, #10 8001bd4: 70fb strb r3, [r7, #3] // Variables for timing uint32_t previous_millis_green = 0; 8001bd6: 2300 movs r3, #0 8001bd8: 62bb str r3, [r7, #40] @ 0x28 uint32_t previous_millis_red = 0; 8001bda: 2300 movs r3, #0 8001bdc: 627b str r3, [r7, #36] @ 0x24 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001bde: f000 fd09 bl 80025f4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001be2: f000 f949 bl 8001e78 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001be6: f7ff fe7f bl 80018e8 MX_ADC1_Init(); 8001bea: f7ff fabd bl 8001168 MX_ADC2_Init(); 8001bee: f7ff faf9 bl 80011e4 MX_I2C1_Init(); 8001bf2: f7ff ff19 bl 8001a28 MX_I2C2_Init(); 8001bf6: f7ff ff45 bl 8001a84 MX_USART1_UART_Init(); 8001bfa: f000 fc57 bl 80024ac MX_TIM3_Init(); 8001bfe: f000 fbe1 bl 80023c4 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim3); 8001c02: 488e ldr r0, [pc, #568] @ (8001e3c ) 8001c04: f003 f842 bl 8004c8c HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off 8001c08: 2201 movs r2, #1 8001c0a: 2110 movs r1, #16 8001c0c: 488c ldr r0, [pc, #560] @ (8001e40 ) 8001c0e: f001 fac0 bl 8003192 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off 8001c12: 2201 movs r2, #1 8001c14: 2120 movs r1, #32 8001c16: 488a ldr r0, [pc, #552] @ (8001e40 ) 8001c18: f001 fabb bl 8003192 digital_outputs_init(); 8001c1c: f7ff fe22 bl 8001864 rs485_init(); 8001c20: f000 fa70 bl 8002104 ADS1015_Init(); // Initializes pH Measurement 8001c24: f7ff fbce bl 80013c4 AD5934_Init(); // Initializes CE and RTD Measurement 8001c28: f7fe fe1c bl 8000864 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while(averages<15) 8001c2c: e02c b.n 8001c88 { AD5934_Process_System(); 8001c2e: f7fe ffb9 bl 8000ba4 ADS1015_Process_System(); 8001c32: f7ff fc25 bl 8001480 current_millis = g_ms_counter; 8001c36: 4b83 ldr r3, [pc, #524] @ (8001e44 ) 8001c38: 681b ldr r3, [r3, #0] 8001c3a: 623b str r3, [r7, #32] if((current_millis % 20) == 0) // Send data each 20ms 8001c3c: 6a39 ldr r1, [r7, #32] 8001c3e: 4b82 ldr r3, [pc, #520] @ (8001e48 ) 8001c40: fba3 2301 umull r2, r3, r3, r1 8001c44: 091a lsrs r2, r3, #4 8001c46: 4613 mov r3, r2 8001c48: 009b lsls r3, r3, #2 8001c4a: 4413 add r3, r2 8001c4c: 009b lsls r3, r3, #2 8001c4e: 1aca subs r2, r1, r3 8001c50: 2a00 cmp r2, #0 8001c52: d119 bne.n 8001c88 { if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms 8001c54: 4b7d ldr r3, [pc, #500] @ (8001e4c ) 8001c56: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001c5a: 2b00 cmp r3, #0 8001c5c: d014 beq.n 8001c88 { reference_resistor = g_ref_filter.filtered_value; 8001c5e: 4b7b ldr r3, [pc, #492] @ (8001e4c ) 8001c60: 6b9b ldr r3, [r3, #56] @ 0x38 8001c62: 4a7b ldr r2, [pc, #492] @ (8001e50 ) 8001c64: 6013 str r3, [r2, #0] uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, current_ref_mux); 8001c66: 4b79 ldr r3, [pc, #484] @ (8001e4c ) 8001c68: 6b9b ldr r3, [r3, #56] @ 0x38 8001c6a: 4a7a ldr r2, [pc, #488] @ (8001e54 ) 8001c6c: 7812 ldrb r2, [r2, #0] 8001c6e: 4611 mov r1, r2 8001c70: 4618 mov r0, r3 8001c72: f7fe ff09 bl 8000a88 8001c76: 4603 mov r3, r0 8001c78: f5c3 5380 rsb r3, r3, #4096 @ 0x1000 8001c7c: 82fb strh r3, [r7, #22] averages++; 8001c7e: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8001c82: 3301 adds r3, #1 8001c84: f887 302f strb.w r3, [r7, #47] @ 0x2f while(averages<15) 8001c88: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8001c8c: 2b0e cmp r3, #14 8001c8e: d9ce bls.n 8001c2e while (1) { AD5934_Process_System(); 8001c90: f7fe ff88 bl 8000ba4 ADS1015_Process_System(); 8001c94: f7ff fbf4 bl 8001480 current_millis = g_ms_counter; 8001c98: 4b6a ldr r3, [pc, #424] @ (8001e44 ) 8001c9a: 681b ldr r3, [r3, #0] 8001c9c: 623b str r3, [r7, #32] if((current_millis % 100) == 0) // Send data each 100ms 8001c9e: 6a3a ldr r2, [r7, #32] 8001ca0: 4b6d ldr r3, [pc, #436] @ (8001e58 ) 8001ca2: fba3 1302 umull r1, r3, r3, r2 8001ca6: 095b lsrs r3, r3, #5 8001ca8: 2164 movs r1, #100 @ 0x64 8001caa: fb01 f303 mul.w r3, r1, r3 8001cae: 1ad3 subs r3, r2, r3 8001cb0: 2b00 cmp r3, #0 8001cb2: f040 80b4 bne.w 8001e1e { if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms 8001cb6: 4b65 ldr r3, [pc, #404] @ (8001e4c ) 8001cb8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001cbc: 2b00 cmp r3, #0 8001cbe: d022 beq.n 8001d06 { //reference_resistor = g_ref_filter.filtered_value; uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, current_ref_mux); 8001cc0: 4b62 ldr r3, [pc, #392] @ (8001e4c ) 8001cc2: 6b9b ldr r3, [r3, #56] @ 0x38 8001cc4: 4a63 ldr r2, [pc, #396] @ (8001e54 ) 8001cc6: 7812 ldrb r2, [r2, #0] 8001cc8: 4611 mov r1, r2 8001cca: 4618 mov r0, r3 8001ccc: f7fe fedc bl 8000a88 8001cd0: 4603 mov r3, r0 8001cd2: f5c3 5380 rsb r3, r3, #4096 @ 0x1000 8001cd6: 83fb strh r3, [r7, #30] intToStr(reference_final, tempString); 8001cd8: f9b7 301e ldrsh.w r3, [r7, #30] 8001cdc: 1d3a adds r2, r7, #4 8001cde: 4611 mov r1, r2 8001ce0: 4618 mov r0, r3 8001ce2: f000 f919 bl 8001f18 // float ref_final = g_ref_filter.filtered_value; //FloatToString(tempString, ref_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001ce6: 1d3b adds r3, r7, #4 8001ce8: 4618 mov r0, r3 8001cea: f7fe fa2f bl 800014c 8001cee: 4603 mov r3, r0 8001cf0: b29a uxth r2, r3 8001cf2: 1d3b adds r3, r7, #4 8001cf4: 4611 mov r1, r2 8001cf6: 4618 mov r0, r3 8001cf8: f000 fa30 bl 800215c rs485_send_broadcast(&newline, 1); 8001cfc: 1cfb adds r3, r7, #3 8001cfe: 2101 movs r1, #1 8001d00: 4618 mov r0, r3 8001d02: f000 fa2b bl 800215c } if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C 8001d06: 4b55 ldr r3, [pc, #340] @ (8001e5c ) 8001d08: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001d0c: 2b00 cmp r3, #0 8001d0e: d02d beq.n 8001d6c { temperature_RTD = AD5934_Calculate_Temperature(reference_resistor, g_rtd_filter.filtered_value); 8001d10: 4b4f ldr r3, [pc, #316] @ (8001e50 ) 8001d12: 681b ldr r3, [r3, #0] 8001d14: 4a51 ldr r2, [pc, #324] @ (8001e5c ) 8001d16: 6b92 ldr r2, [r2, #56] @ 0x38 8001d18: 4611 mov r1, r2 8001d1a: 4618 mov r0, r3 8001d1c: f7fe fdee bl 80008fc 8001d20: 4603 mov r3, r0 8001d22: 4a4f ldr r2, [pc, #316] @ (8001e60 ) 8001d24: 6013 str r3, [r2, #0] uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, current_rtd_mux); 8001d26: 4b4d ldr r3, [pc, #308] @ (8001e5c ) 8001d28: 6b9b ldr r3, [r3, #56] @ 0x38 8001d2a: 4a4e ldr r2, [pc, #312] @ (8001e64 ) 8001d2c: 7812 ldrb r2, [r2, #0] 8001d2e: 4611 mov r1, r2 8001d30: 4618 mov r0, r3 8001d32: f7fe fea9 bl 8000a88 8001d36: 4603 mov r3, r0 8001d38: f5c3 5380 rsb r3, r3, #4096 @ 0x1000 8001d3c: 83bb strh r3, [r7, #28] intToStr(rtd_final, tempString); 8001d3e: f9b7 301c ldrsh.w r3, [r7, #28] 8001d42: 1d3a adds r2, r7, #4 8001d44: 4611 mov r1, r2 8001d46: 4618 mov r0, r3 8001d48: f000 f8e6 bl 8001f18 //float rtd_final = g_rtd_filter.filtered_value; //FloatToString(tempString, rtd_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001d4c: 1d3b adds r3, r7, #4 8001d4e: 4618 mov r0, r3 8001d50: f7fe f9fc bl 800014c 8001d54: 4603 mov r3, r0 8001d56: b29a uxth r2, r3 8001d58: 1d3b adds r3, r7, #4 8001d5a: 4611 mov r1, r2 8001d5c: 4618 mov r0, r3 8001d5e: f000 f9fd bl 800215c rs485_send_broadcast(&newline, 1); 8001d62: 1cfb adds r3, r7, #3 8001d64: 2101 movs r1, #1 8001d66: 4618 mov r0, r3 8001d68: f000 f9f8 bl 800215c } if (g_ec_filter.value_valid) // EC 8001d6c: 4b3e ldr r3, [pc, #248] @ (8001e68 ) 8001d6e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001d72: 2b00 cmp r3, #0 8001d74: d02b beq.n 8001dce { thermal_compensaded_EC = AD5934_EC_Compensate_Magnitude_To_25C(g_ec_filter.filtered_value, temperature_RTD); 8001d76: 4b3c ldr r3, [pc, #240] @ (8001e68 ) 8001d78: 6b9b ldr r3, [r3, #56] @ 0x38 8001d7a: 4a39 ldr r2, [pc, #228] @ (8001e60 ) 8001d7c: 6812 ldr r2, [r2, #0] 8001d7e: 4611 mov r1, r2 8001d80: 4618 mov r0, r3 8001d82: f7fe fe13 bl 80009ac 8001d86: 4603 mov r3, r0 8001d88: 4a38 ldr r2, [pc, #224] @ (8001e6c ) 8001d8a: 6013 str r3, [r2, #0] uint16_t ec_final = AD5934_Compress_To_IntScale(thermal_compensaded_EC, current_ec_mux); 8001d8c: 4b37 ldr r3, [pc, #220] @ (8001e6c ) 8001d8e: 681b ldr r3, [r3, #0] 8001d90: 4a37 ldr r2, [pc, #220] @ (8001e70 ) 8001d92: 7812 ldrb r2, [r2, #0] 8001d94: 4611 mov r1, r2 8001d96: 4618 mov r0, r3 8001d98: f7fe fe76 bl 8000a88 8001d9c: 4603 mov r3, r0 8001d9e: 837b strh r3, [r7, #26] intToStr(ec_final, tempString); 8001da0: f9b7 301a ldrsh.w r3, [r7, #26] 8001da4: 1d3a adds r2, r7, #4 8001da6: 4611 mov r1, r2 8001da8: 4618 mov r0, r3 8001daa: f000 f8b5 bl 8001f18 // float ec_final = g_ec_filter.filtered_value; // FloatToString(tempString, ec_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001dae: 1d3b adds r3, r7, #4 8001db0: 4618 mov r0, r3 8001db2: f7fe f9cb bl 800014c 8001db6: 4603 mov r3, r0 8001db8: b29a uxth r2, r3 8001dba: 1d3b adds r3, r7, #4 8001dbc: 4611 mov r1, r2 8001dbe: 4618 mov r0, r3 8001dc0: f000 f9cc bl 800215c rs485_send_broadcast(&newline, 1); 8001dc4: 1cfb adds r3, r7, #3 8001dc6: 2101 movs r1, #1 8001dc8: 4618 mov r0, r3 8001dca: f000 f9c7 bl 800215c } if (g_ph_filter.value_valid) // pH 8001dce: 4b29 ldr r3, [pc, #164] @ (8001e74 ) 8001dd0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001dd4: 2b00 cmp r3, #0 8001dd6: d01d beq.n 8001e14 { uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value); 8001dd8: 4b26 ldr r3, [pc, #152] @ (8001e74 ) 8001dda: 6b9b ldr r3, [r3, #56] @ 0x38 8001ddc: 4618 mov r0, r3 8001dde: f7ff fb0b bl 80013f8 8001de2: 4603 mov r3, r0 8001de4: 833b strh r3, [r7, #24] intToStr(ph_final, tempString); 8001de6: f9b7 3018 ldrsh.w r3, [r7, #24] 8001dea: 1d3a adds r2, r7, #4 8001dec: 4611 mov r1, r2 8001dee: 4618 mov r0, r3 8001df0: f000 f892 bl 8001f18 //float ph_final = g_ph_filter.filtered_value; //FloatToString(tempString, ph_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001df4: 1d3b adds r3, r7, #4 8001df6: 4618 mov r0, r3 8001df8: f7fe f9a8 bl 800014c 8001dfc: 4603 mov r3, r0 8001dfe: b29a uxth r2, r3 8001e00: 1d3b adds r3, r7, #4 8001e02: 4611 mov r1, r2 8001e04: 4618 mov r0, r3 8001e06: f000 f9a9 bl 800215c rs485_send_broadcast(&newline, 1); 8001e0a: 1cfb adds r3, r7, #3 8001e0c: 2101 movs r1, #1 8001e0e: 4618 mov r0, r3 8001e10: f000 f9a4 bl 800215c } rs485_send_broadcast(&newline, 1); 8001e14: 1cfb adds r3, r7, #3 8001e16: 2101 movs r1, #1 8001e18: 4618 mov r0, r3 8001e1a: f000 f99f bl 800215c } // Piscar LED verde em PB4 a cada 1 segundo if ((current_millis - previous_millis_green) >= 1000) 8001e1e: 6a3a ldr r2, [r7, #32] 8001e20: 6abb ldr r3, [r7, #40] @ 0x28 8001e22: 1ad3 subs r3, r2, r3 8001e24: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001e28: f4ff af32 bcc.w 8001c90 { previous_millis_green = current_millis; 8001e2c: 6a3b ldr r3, [r7, #32] 8001e2e: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4); 8001e30: 2110 movs r1, #16 8001e32: 4803 ldr r0, [pc, #12] @ (8001e40 ) 8001e34: f001 f9c5 bl 80031c2 AD5934_Process_System(); 8001e38: e72a b.n 8001c90 8001e3a: bf00 nop 8001e3c: 20000310 .word 0x20000310 8001e40: 40010c00 .word 0x40010c00 8001e44: 20000080 .word 0x20000080 8001e48: cccccccd .word 0xcccccccd 8001e4c: 20000114 .word 0x20000114 8001e50: 20000084 .word 0x20000084 8001e54: 20000091 .word 0x20000091 8001e58: 51eb851f .word 0x51eb851f 8001e5c: 20000094 .word 0x20000094 8001e60: 20000088 .word 0x20000088 8001e64: 20000002 .word 0x20000002 8001e68: 200000d4 .word 0x200000d4 8001e6c: 2000008c .word 0x2000008c 8001e70: 20000001 .word 0x20000001 8001e74: 200001c8 .word 0x200001c8 08001e78 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001e78: b580 push {r7, lr} 8001e7a: b094 sub sp, #80 @ 0x50 8001e7c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001e7e: f107 0328 add.w r3, r7, #40 @ 0x28 8001e82: 2228 movs r2, #40 @ 0x28 8001e84: 2100 movs r1, #0 8001e86: 4618 mov r0, r3 8001e88: f004 f8b8 bl 8005ffc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001e8c: f107 0314 add.w r3, r7, #20 8001e90: 2200 movs r2, #0 8001e92: 601a str r2, [r3, #0] 8001e94: 605a str r2, [r3, #4] 8001e96: 609a str r2, [r3, #8] 8001e98: 60da str r2, [r3, #12] 8001e9a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001e9c: 1d3b adds r3, r7, #4 8001e9e: 2200 movs r2, #0 8001ea0: 601a str r2, [r3, #0] 8001ea2: 605a str r2, [r3, #4] 8001ea4: 609a str r2, [r3, #8] 8001ea6: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001ea8: 2301 movs r3, #1 8001eaa: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001eac: f44f 3380 mov.w r3, #65536 @ 0x10000 8001eb0: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8001eb2: 2300 movs r3, #0 8001eb4: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001eb6: f107 0328 add.w r3, r7, #40 @ 0x28 8001eba: 4618 mov r0, r3 8001ebc: f002 f9ce bl 800425c 8001ec0: 4603 mov r3, r0 8001ec2: 2b00 cmp r3, #0 8001ec4: d001 beq.n 8001eca { Error_Handler(); 8001ec6: f000 f90b bl 80020e0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001eca: 230f movs r3, #15 8001ecc: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8001ece: 2301 movs r3, #1 8001ed0: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001ed2: 2300 movs r3, #0 8001ed4: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001ed6: 2300 movs r3, #0 8001ed8: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001eda: 2300 movs r3, #0 8001edc: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8001ede: f107 0314 add.w r3, r7, #20 8001ee2: 2100 movs r1, #0 8001ee4: 4618 mov r0, r3 8001ee6: f002 fc3b bl 8004760 8001eea: 4603 mov r3, r0 8001eec: 2b00 cmp r3, #0 8001eee: d001 beq.n 8001ef4 { Error_Handler(); 8001ef0: f000 f8f6 bl 80020e0 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8001ef4: 2302 movs r3, #2 8001ef6: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 8001ef8: f44f 4340 mov.w r3, #49152 @ 0xc000 8001efc: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001efe: 1d3b adds r3, r7, #4 8001f00: 4618 mov r0, r3 8001f02: f002 fdbd bl 8004a80 8001f06: 4603 mov r3, r0 8001f08: 2b00 cmp r3, #0 8001f0a: d001 beq.n 8001f10 { Error_Handler(); 8001f0c: f000 f8e8 bl 80020e0 } } 8001f10: bf00 nop 8001f12: 3750 adds r7, #80 @ 0x50 8001f14: 46bd mov sp, r7 8001f16: bd80 pop {r7, pc} 08001f18 : } void intToStr(int16_t N, uint8_t *str) { 8001f18: b480 push {r7} 8001f1a: b087 sub sp, #28 8001f1c: af00 add r7, sp, #0 8001f1e: 4603 mov r3, r0 8001f20: 6039 str r1, [r7, #0] 8001f22: 80fb strh r3, [r7, #6] int16_t i = 0; 8001f24: 2300 movs r3, #0 8001f26: 82fb strh r3, [r7, #22] int16_t sign = N; 8001f28: 88fb ldrh r3, [r7, #6] 8001f2a: 823b strh r3, [r7, #16] uint8_t max_len = 15; // Tamanho máximo do buffer 8001f2c: 230f movs r3, #15 8001f2e: 73fb strb r3, [r7, #15] uint8_t width = 4; // mínimo 4 caracteres 8001f30: 2304 movs r3, #4 8001f32: 757b strb r3, [r7, #21] // Trata o caso do número zero isoladamente if (N == 0) 8001f34: f9b7 3006 ldrsh.w r3, [r7, #6] 8001f38: 2b00 cmp r3, #0 8001f3a: d127 bne.n 8001f8c { // Preenche com zeros à esquerda até atingir a largura desejada while (width > 1 && i < (max_len - 1)) 8001f3c: e00c b.n 8001f58 { str[i++] = '0'; 8001f3e: f9b7 2016 ldrsh.w r2, [r7, #22] 8001f42: b293 uxth r3, r2 8001f44: 3301 adds r3, #1 8001f46: b29b uxth r3, r3 8001f48: 82fb strh r3, [r7, #22] 8001f4a: 683b ldr r3, [r7, #0] 8001f4c: 4413 add r3, r2 8001f4e: 2230 movs r2, #48 @ 0x30 8001f50: 701a strb r2, [r3, #0] width--; 8001f52: 7d7b ldrb r3, [r7, #21] 8001f54: 3b01 subs r3, #1 8001f56: 757b strb r3, [r7, #21] while (width > 1 && i < (max_len - 1)) 8001f58: 7d7b ldrb r3, [r7, #21] 8001f5a: 2b01 cmp r3, #1 8001f5c: d905 bls.n 8001f6a 8001f5e: f9b7 2016 ldrsh.w r2, [r7, #22] 8001f62: 7bfb ldrb r3, [r7, #15] 8001f64: 3b01 subs r3, #1 8001f66: 429a cmp r2, r3 8001f68: dbe9 blt.n 8001f3e } str[i++] = '0'; 8001f6a: f9b7 2016 ldrsh.w r2, [r7, #22] 8001f6e: b293 uxth r3, r2 8001f70: 3301 adds r3, #1 8001f72: b29b uxth r3, r3 8001f74: 82fb strh r3, [r7, #22] 8001f76: 683b ldr r3, [r7, #0] 8001f78: 4413 add r3, r2 8001f7a: 2230 movs r2, #48 @ 0x30 8001f7c: 701a strb r2, [r3, #0] str[i] = '\0'; 8001f7e: f9b7 3016 ldrsh.w r3, [r7, #22] 8001f82: 683a ldr r2, [r7, #0] 8001f84: 4413 add r3, r2 8001f86: 2200 movs r2, #0 8001f88: 701a strb r2, [r3, #0] return; 8001f8a: e08a b.n 80020a2 } if (N < 0) 8001f8c: f9b7 3006 ldrsh.w r3, [r7, #6] 8001f90: 2b00 cmp r3, #0 8001f92: da2d bge.n 8001ff0 N = -N; 8001f94: 88fb ldrh r3, [r7, #6] 8001f96: 425b negs r3, r3 8001f98: b29b uxth r3, r3 8001f9a: 80fb strh r3, [r7, #6] // Extração dos dígitos while (N > 0) 8001f9c: e028 b.n 8001ff0 { if (i >= (max_len - 1)) 8001f9e: f9b7 2016 ldrsh.w r2, [r7, #22] 8001fa2: 7bfb ldrb r3, [r7, #15] 8001fa4: 3b01 subs r3, #1 8001fa6: 429a cmp r2, r3 8001fa8: da27 bge.n 8001ffa break; // Proteção de estouro str[i++] = (N % 10) + '0'; 8001faa: f9b7 2006 ldrsh.w r2, [r7, #6] 8001fae: 4b3f ldr r3, [pc, #252] @ (80020ac ) 8001fb0: fb83 1302 smull r1, r3, r3, r2 8001fb4: 1099 asrs r1, r3, #2 8001fb6: 17d3 asrs r3, r2, #31 8001fb8: 1ac9 subs r1, r1, r3 8001fba: 460b mov r3, r1 8001fbc: 009b lsls r3, r3, #2 8001fbe: 440b add r3, r1 8001fc0: 005b lsls r3, r3, #1 8001fc2: 1ad3 subs r3, r2, r3 8001fc4: b21b sxth r3, r3 8001fc6: b2da uxtb r2, r3 8001fc8: f9b7 1016 ldrsh.w r1, [r7, #22] 8001fcc: b28b uxth r3, r1 8001fce: 3301 adds r3, #1 8001fd0: b29b uxth r3, r3 8001fd2: 82fb strh r3, [r7, #22] 8001fd4: 683b ldr r3, [r7, #0] 8001fd6: 440b add r3, r1 8001fd8: 3230 adds r2, #48 @ 0x30 8001fda: b2d2 uxtb r2, r2 8001fdc: 701a strb r2, [r3, #0] N /= 10; 8001fde: f9b7 3006 ldrsh.w r3, [r7, #6] 8001fe2: 4a32 ldr r2, [pc, #200] @ (80020ac ) 8001fe4: fb82 1203 smull r1, r2, r2, r3 8001fe8: 1092 asrs r2, r2, #2 8001fea: 17db asrs r3, r3, #31 8001fec: 1ad3 subs r3, r2, r3 8001fee: 80fb strh r3, [r7, #6] while (N > 0) 8001ff0: f9b7 3006 ldrsh.w r3, [r7, #6] 8001ff4: 2b00 cmp r3, #0 8001ff6: dcd2 bgt.n 8001f9e 8001ff8: e000 b.n 8001ffc break; // Proteção de estouro 8001ffa: bf00 nop } // Adiciona o sinal de menos se necessário if (sign < 0) 8001ffc: f9b7 3010 ldrsh.w r3, [r7, #16] 8002000: 2b00 cmp r3, #0 8002002: da1a bge.n 800203a { if (i < (max_len - 1)) 8002004: f9b7 2016 ldrsh.w r2, [r7, #22] 8002008: 7bfb ldrb r3, [r7, #15] 800200a: 3b01 subs r3, #1 800200c: 429a cmp r2, r3 800200e: da14 bge.n 800203a str[i++] = '-'; 8002010: f9b7 2016 ldrsh.w r2, [r7, #22] 8002014: b293 uxth r3, r2 8002016: 3301 adds r3, #1 8002018: b29b uxth r3, r3 800201a: 82fb strh r3, [r7, #22] 800201c: 683b ldr r3, [r7, #0] 800201e: 4413 add r3, r2 8002020: 222d movs r2, #45 @ 0x2d 8002022: 701a strb r2, [r3, #0] } // Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal) while (i < width && i < (max_len - 1)) 8002024: e009 b.n 800203a { str[i++] = '0'; 8002026: f9b7 2016 ldrsh.w r2, [r7, #22] 800202a: b293 uxth r3, r2 800202c: 3301 adds r3, #1 800202e: b29b uxth r3, r3 8002030: 82fb strh r3, [r7, #22] 8002032: 683b ldr r3, [r7, #0] 8002034: 4413 add r3, r2 8002036: 2230 movs r2, #48 @ 0x30 8002038: 701a strb r2, [r3, #0] while (i < width && i < (max_len - 1)) 800203a: f9b7 2016 ldrsh.w r2, [r7, #22] 800203e: 7d7b ldrb r3, [r7, #21] 8002040: 429a cmp r2, r3 8002042: da05 bge.n 8002050 8002044: f9b7 2016 ldrsh.w r2, [r7, #22] 8002048: 7bfb ldrb r3, [r7, #15] 800204a: 3b01 subs r3, #1 800204c: 429a cmp r2, r3 800204e: dbea blt.n 8002026 } str[i] = '\0'; 8002050: f9b7 3016 ldrsh.w r3, [r7, #22] 8002054: 683a ldr r2, [r7, #0] 8002056: 4413 add r3, r2 8002058: 2200 movs r2, #0 800205a: 701a strb r2, [r3, #0] // Inverte a string para colocar na ordem correta for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 800205c: 2300 movs r3, #0 800205e: 753b strb r3, [r7, #20] 8002060: 8afb ldrh r3, [r7, #22] 8002062: b2db uxtb r3, r3 8002064: 3b01 subs r3, #1 8002066: 74fb strb r3, [r7, #19] 8002068: e017 b.n 800209a { uint8_t temp = str[j]; 800206a: 7d3b ldrb r3, [r7, #20] 800206c: 683a ldr r2, [r7, #0] 800206e: 4413 add r3, r2 8002070: 781b ldrb r3, [r3, #0] 8002072: 73bb strb r3, [r7, #14] str[j] = str[k]; 8002074: 7cfb ldrb r3, [r7, #19] 8002076: 683a ldr r2, [r7, #0] 8002078: 441a add r2, r3 800207a: 7d3b ldrb r3, [r7, #20] 800207c: 6839 ldr r1, [r7, #0] 800207e: 440b add r3, r1 8002080: 7812 ldrb r2, [r2, #0] 8002082: 701a strb r2, [r3, #0] str[k] = temp; 8002084: 7cfb ldrb r3, [r7, #19] 8002086: 683a ldr r2, [r7, #0] 8002088: 4413 add r3, r2 800208a: 7bba ldrb r2, [r7, #14] 800208c: 701a strb r2, [r3, #0] for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 800208e: 7d3b ldrb r3, [r7, #20] 8002090: 3301 adds r3, #1 8002092: 753b strb r3, [r7, #20] 8002094: 7cfb ldrb r3, [r7, #19] 8002096: 3b01 subs r3, #1 8002098: 74fb strb r3, [r7, #19] 800209a: 7d3a ldrb r2, [r7, #20] 800209c: 7cfb ldrb r3, [r7, #19] 800209e: 429a cmp r2, r3 80020a0: d3e3 bcc.n 800206a } } 80020a2: 371c adds r7, #28 80020a4: 46bd mov sp, r7 80020a6: bc80 pop {r7} 80020a8: 4770 bx lr 80020aa: bf00 nop 80020ac: 66666667 .word 0x66666667 080020b0 : /* TIM3 Timer Interrupt */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80020b0: b480 push {r7} 80020b2: b083 sub sp, #12 80020b4: af00 add r7, sp, #0 80020b6: 6078 str r0, [r7, #4] if (htim->Instance == TIM3) 80020b8: 687b ldr r3, [r7, #4] 80020ba: 681b ldr r3, [r3, #0] 80020bc: 4a06 ldr r2, [pc, #24] @ (80020d8 ) 80020be: 4293 cmp r3, r2 80020c0: d104 bne.n 80020cc { g_ms_counter++; /* Relógio global do sistema */ 80020c2: 4b06 ldr r3, [pc, #24] @ (80020dc ) 80020c4: 681b ldr r3, [r3, #0] 80020c6: 3301 adds r3, #1 80020c8: 4a04 ldr r2, [pc, #16] @ (80020dc ) 80020ca: 6013 str r3, [r2, #0] } } 80020cc: bf00 nop 80020ce: 370c adds r7, #12 80020d0: 46bd mov sp, r7 80020d2: bc80 pop {r7} 80020d4: 4770 bx lr 80020d6: bf00 nop 80020d8: 40000400 .word 0x40000400 80020dc: 20000080 .word 0x20000080 080020e0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80020e0: b480 push {r7} 80020e2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80020e4: b672 cpsid i } 80020e6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80020e8: bf00 nop 80020ea: e7fd b.n 80020e8 080020ec : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 80020ec: b480 push {r7} 80020ee: b083 sub sp, #12 80020f0: af00 add r7, sp, #0 80020f2: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 80020f4: 687b ldr r3, [r7, #4] 80020f6: 689b ldr r3, [r3, #8] } 80020f8: 4618 mov r0, r3 80020fa: 370c adds r7, #12 80020fc: 46bd mov sp, r7 80020fe: bc80 pop {r7} 8002100: 4770 bx lr ... 08002104 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 8002104: b580 push {r7, lr} 8002106: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 8002108: f000 f864 bl 80021d4 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 800210c: f000 f8a8 bl 8002260 /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 8002110: f000 f808 bl 8002124 8002114: 4603 mov r3, r0 8002116: 461a mov r2, r3 8002118: 4b01 ldr r3, [pc, #4] @ (8002120 ) 800211a: 709a strb r2, [r3, #2] } 800211c: bf00 nop 800211e: bd80 pop {r7, pc} 8002120: 200002c4 .word 0x200002c4 08002124 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 8002124: b598 push {r3, r4, r7, lr} 8002126: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 8002128: 480a ldr r0, [pc, #40] @ (8002154 ) 800212a: f7ff ffdf bl 80020ec 800212e: 4603 mov r3, r0 8002130: 0a1b lsrs r3, r3, #8 8002132: b2db uxtb r3, r3 8002134: f023 030f bic.w r3, r3, #15 8002138: b2dc uxtb r4, r3 800213a: 4807 ldr r0, [pc, #28] @ (8002158 ) 800213c: f7ff ffd6 bl 80020ec 8002140: 4603 mov r3, r0 8002142: 089b lsrs r3, r3, #2 8002144: b2db uxtb r3, r3 8002146: f003 030f and.w r3, r3, #15 800214a: b2db uxtb r3, r3 800214c: 4323 orrs r3, r4 800214e: b2db uxtb r3, r3 } 8002150: 4618 mov r0, r3 8002152: bd98 pop {r3, r4, r7, pc} 8002154: 40010c00 .word 0x40010c00 8002158: 40010800 .word 0x40010800 0800215c : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 800215c: b580 push {r7, lr} 800215e: b084 sub sp, #16 8002160: af00 add r7, sp, #0 8002162: 6078 str r0, [r7, #4] 8002164: 460b mov r3, r1 8002166: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 8002168: f000 f81c bl 80021a4 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 800216c: 2300 movs r3, #0 800216e: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8002170: f107 010e add.w r1, r7, #14 8002174: f04f 33ff mov.w r3, #4294967295 8002178: 2201 movs r2, #1 800217a: 4809 ldr r0, [pc, #36] @ (80021a0 ) 800217c: f003 f978 bl 8005470 /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 8002180: 887a ldrh r2, [r7, #2] 8002182: f04f 33ff mov.w r3, #4294967295 8002186: 6879 ldr r1, [r7, #4] 8002188: 4805 ldr r0, [pc, #20] @ (80021a0 ) 800218a: f003 f971 bl 8005470 800218e: 4603 mov r3, r0 8002190: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 8002192: f000 f813 bl 80021bc return status; 8002196: 7bfb ldrb r3, [r7, #15] } 8002198: 4618 mov r0, r3 800219a: 3710 adds r7, #16 800219c: 46bd mov sp, r7 800219e: bd80 pop {r7, pc} 80021a0: 200002c8 .word 0x200002c8 080021a4 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 80021a4: b580 push {r7, lr} 80021a6: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 80021a8: 2201 movs r2, #1 80021aa: f44f 5180 mov.w r1, #4096 @ 0x1000 80021ae: 4802 ldr r0, [pc, #8] @ (80021b8 ) 80021b0: f000 ffef bl 8003192 } 80021b4: bf00 nop 80021b6: bd80 pop {r7, pc} 80021b8: 40010800 .word 0x40010800 080021bc : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 80021bc: b580 push {r7, lr} 80021be: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 80021c0: 2200 movs r2, #0 80021c2: f44f 5180 mov.w r1, #4096 @ 0x1000 80021c6: 4802 ldr r0, [pc, #8] @ (80021d0 ) 80021c8: f000 ffe3 bl 8003192 } 80021cc: bf00 nop 80021ce: bd80 pop {r7, pc} 80021d0: 40010800 .word 0x40010800 080021d4 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 80021d4: b580 push {r7, lr} 80021d6: b086 sub sp, #24 80021d8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80021da: f107 0308 add.w r3, r7, #8 80021de: 2200 movs r2, #0 80021e0: 601a str r2, [r3, #0] 80021e2: 605a str r2, [r3, #4] 80021e4: 609a str r2, [r3, #8] 80021e6: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80021e8: 4b1a ldr r3, [pc, #104] @ (8002254 ) 80021ea: 699b ldr r3, [r3, #24] 80021ec: 4a19 ldr r2, [pc, #100] @ (8002254 ) 80021ee: f043 0304 orr.w r3, r3, #4 80021f2: 6193 str r3, [r2, #24] 80021f4: 4b17 ldr r3, [pc, #92] @ (8002254 ) 80021f6: 699b ldr r3, [r3, #24] 80021f8: f003 0304 and.w r3, r3, #4 80021fc: 607b str r3, [r7, #4] 80021fe: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002200: 4b14 ldr r3, [pc, #80] @ (8002254 ) 8002202: 699b ldr r3, [r3, #24] 8002204: 4a13 ldr r2, [pc, #76] @ (8002254 ) 8002206: f043 0308 orr.w r3, r3, #8 800220a: 6193 str r3, [r2, #24] 800220c: 4b11 ldr r3, [pc, #68] @ (8002254 ) 800220e: 699b ldr r3, [r3, #24] 8002210: f003 0308 and.w r3, r3, #8 8002214: 603b str r3, [r7, #0] 8002216: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 8002218: 233c movs r3, #60 @ 0x3c 800221a: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800221c: 2300 movs r3, #0 800221e: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002220: 2301 movs r3, #1 8002222: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002224: f107 0308 add.w r3, r7, #8 8002228: 4619 mov r1, r3 800222a: 480b ldr r0, [pc, #44] @ (8002258 ) 800222c: f000 fe16 bl 8002e5c /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 8002230: f44f 4370 mov.w r3, #61440 @ 0xf000 8002234: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002236: 2300 movs r3, #0 8002238: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 800223a: 2301 movs r3, #1 800223c: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800223e: f107 0308 add.w r3, r7, #8 8002242: 4619 mov r1, r3 8002244: 4805 ldr r0, [pc, #20] @ (800225c ) 8002246: f000 fe09 bl 8002e5c } 800224a: bf00 nop 800224c: 3718 adds r7, #24 800224e: 46bd mov sp, r7 8002250: bd80 pop {r7, pc} 8002252: bf00 nop 8002254: 40021000 .word 0x40021000 8002258: 40010800 .word 0x40010800 800225c: 40010c00 .word 0x40010c00 08002260 : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 8002260: b580 push {r7, lr} 8002262: b082 sub sp, #8 8002264: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 8002266: 4b18 ldr r3, [pc, #96] @ (80022c8 ) 8002268: 699b ldr r3, [r3, #24] 800226a: 4a17 ldr r2, [pc, #92] @ (80022c8 ) 800226c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002270: 6193 str r3, [r2, #24] 8002272: 4b15 ldr r3, [pc, #84] @ (80022c8 ) 8002274: 699b ldr r3, [r3, #24] 8002276: f403 4380 and.w r3, r3, #16384 @ 0x4000 800227a: 607b str r3, [r7, #4] 800227c: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 800227e: 4b13 ldr r3, [pc, #76] @ (80022cc ) 8002280: 4a13 ldr r2, [pc, #76] @ (80022d0 ) 8002282: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002284: 4b11 ldr r3, [pc, #68] @ (80022cc ) 8002286: f44f 5216 mov.w r2, #9600 @ 0x2580 800228a: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800228c: 4b0f ldr r3, [pc, #60] @ (80022cc ) 800228e: 2200 movs r2, #0 8002290: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002292: 4b0e ldr r3, [pc, #56] @ (80022cc ) 8002294: 2200 movs r2, #0 8002296: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002298: 4b0c ldr r3, [pc, #48] @ (80022cc ) 800229a: 2200 movs r2, #0 800229c: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800229e: 4b0b ldr r3, [pc, #44] @ (80022cc ) 80022a0: 220c movs r2, #12 80022a2: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 80022a4: 4b09 ldr r3, [pc, #36] @ (80022cc ) 80022a6: 2200 movs r2, #0 80022a8: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80022aa: 4b08 ldr r3, [pc, #32] @ (80022cc ) 80022ac: 2200 movs r2, #0 80022ae: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80022b0: 4806 ldr r0, [pc, #24] @ (80022cc ) 80022b2: f003 f88d bl 80053d0 80022b6: 4603 mov r3, r0 80022b8: 2b00 cmp r3, #0 80022ba: d001 beq.n 80022c0 { /* Initialization Error */ while(1); 80022bc: bf00 nop 80022be: e7fd b.n 80022bc } } 80022c0: bf00 nop 80022c2: 3708 adds r7, #8 80022c4: 46bd mov sp, r7 80022c6: bd80 pop {r7, pc} 80022c8: 40021000 .word 0x40021000 80022cc: 200002c8 .word 0x200002c8 80022d0: 40013800 .word 0x40013800 080022d4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80022d4: b480 push {r7} 80022d6: b085 sub sp, #20 80022d8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80022da: 4b15 ldr r3, [pc, #84] @ (8002330 ) 80022dc: 699b ldr r3, [r3, #24] 80022de: 4a14 ldr r2, [pc, #80] @ (8002330 ) 80022e0: f043 0301 orr.w r3, r3, #1 80022e4: 6193 str r3, [r2, #24] 80022e6: 4b12 ldr r3, [pc, #72] @ (8002330 ) 80022e8: 699b ldr r3, [r3, #24] 80022ea: f003 0301 and.w r3, r3, #1 80022ee: 60bb str r3, [r7, #8] 80022f0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80022f2: 4b0f ldr r3, [pc, #60] @ (8002330 ) 80022f4: 69db ldr r3, [r3, #28] 80022f6: 4a0e ldr r2, [pc, #56] @ (8002330 ) 80022f8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80022fc: 61d3 str r3, [r2, #28] 80022fe: 4b0c ldr r3, [pc, #48] @ (8002330 ) 8002300: 69db ldr r3, [r3, #28] 8002302: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002306: 607b str r3, [r7, #4] 8002308: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800230a: 4b0a ldr r3, [pc, #40] @ (8002334 ) 800230c: 685b ldr r3, [r3, #4] 800230e: 60fb str r3, [r7, #12] 8002310: 68fb ldr r3, [r7, #12] 8002312: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 8002316: 60fb str r3, [r7, #12] 8002318: 68fb ldr r3, [r7, #12] 800231a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800231e: 60fb str r3, [r7, #12] 8002320: 4a04 ldr r2, [pc, #16] @ (8002334 ) 8002322: 68fb ldr r3, [r7, #12] 8002324: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002326: bf00 nop 8002328: 3714 adds r7, #20 800232a: 46bd mov sp, r7 800232c: bc80 pop {r7} 800232e: 4770 bx lr 8002330: 40021000 .word 0x40021000 8002334: 40010000 .word 0x40010000 08002338 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8002338: b480 push {r7} 800233a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800233c: bf00 nop 800233e: e7fd b.n 800233c 08002340 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002340: b480 push {r7} 8002342: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002344: bf00 nop 8002346: e7fd b.n 8002344 08002348 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002348: b480 push {r7} 800234a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800234c: bf00 nop 800234e: e7fd b.n 800234c 08002350 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8002350: b480 push {r7} 8002352: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002354: bf00 nop 8002356: e7fd b.n 8002354 08002358 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002358: b480 push {r7} 800235a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800235c: bf00 nop 800235e: e7fd b.n 800235c 08002360 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002360: b480 push {r7} 8002362: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002364: bf00 nop 8002366: 46bd mov sp, r7 8002368: bc80 pop {r7} 800236a: 4770 bx lr 0800236c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800236c: b480 push {r7} 800236e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002370: bf00 nop 8002372: 46bd mov sp, r7 8002374: bc80 pop {r7} 8002376: 4770 bx lr 08002378 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002378: b480 push {r7} 800237a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800237c: bf00 nop 800237e: 46bd mov sp, r7 8002380: bc80 pop {r7} 8002382: 4770 bx lr 08002384 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002384: b580 push {r7, lr} 8002386: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002388: f000 f97a bl 8002680 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800238c: bf00 nop 800238e: bd80 pop {r7, pc} 08002390 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8002390: b580 push {r7, lr} 8002392: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002394: 4802 ldr r0, [pc, #8] @ (80023a0 ) 8002396: f002 fccb bl 8004d30 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800239a: bf00 nop 800239c: bd80 pop {r7, pc} 800239e: bf00 nop 80023a0: 20000310 .word 0x20000310 080023a4 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80023a4: b580 push {r7, lr} 80023a6: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80023a8: 4802 ldr r0, [pc, #8] @ (80023b4 ) 80023aa: f003 f8ed bl 8005588 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80023ae: bf00 nop 80023b0: bd80 pop {r7, pc} 80023b2: bf00 nop 80023b4: 20000358 .word 0x20000358 080023b8 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80023b8: b480 push {r7} 80023ba: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80023bc: bf00 nop 80023be: 46bd mov sp, r7 80023c0: bc80 pop {r7} 80023c2: 4770 bx lr 080023c4 : TIM_HandleTypeDef htim3; /* TIM3 init function */ void MX_TIM3_Init(void) { 80023c4: b580 push {r7, lr} 80023c6: b086 sub sp, #24 80023c8: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80023ca: f107 0308 add.w r3, r7, #8 80023ce: 2200 movs r2, #0 80023d0: 601a str r2, [r3, #0] 80023d2: 605a str r2, [r3, #4] 80023d4: 609a str r2, [r3, #8] 80023d6: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80023d8: 463b mov r3, r7 80023da: 2200 movs r2, #0 80023dc: 601a str r2, [r3, #0] 80023de: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80023e0: 4b1d ldr r3, [pc, #116] @ (8002458 ) 80023e2: 4a1e ldr r2, [pc, #120] @ (800245c ) 80023e4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 2; 80023e6: 4b1c ldr r3, [pc, #112] @ (8002458 ) 80023e8: 2202 movs r2, #2 80023ea: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80023ec: 4b1a ldr r3, [pc, #104] @ (8002458 ) 80023ee: 2200 movs r2, #0 80023f0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 80023f2: 4b19 ldr r3, [pc, #100] @ (8002458 ) 80023f4: f240 32e7 movw r2, #999 @ 0x3e7 80023f8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80023fa: 4b17 ldr r3, [pc, #92] @ (8002458 ) 80023fc: 2200 movs r2, #0 80023fe: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8002400: 4b15 ldr r3, [pc, #84] @ (8002458 ) 8002402: 2280 movs r2, #128 @ 0x80 8002404: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8002406: 4814 ldr r0, [pc, #80] @ (8002458 ) 8002408: f002 fbf0 bl 8004bec 800240c: 4603 mov r3, r0 800240e: 2b00 cmp r3, #0 8002410: d001 beq.n 8002416 { Error_Handler(); 8002412: f7ff fe65 bl 80020e0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002416: f44f 5380 mov.w r3, #4096 @ 0x1000 800241a: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800241c: f107 0308 add.w r3, r7, #8 8002420: 4619 mov r1, r3 8002422: 480d ldr r0, [pc, #52] @ (8002458 ) 8002424: f002 fd74 bl 8004f10 8002428: 4603 mov r3, r0 800242a: 2b00 cmp r3, #0 800242c: d001 beq.n 8002432 { Error_Handler(); 800242e: f7ff fe57 bl 80020e0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8002432: 2300 movs r3, #0 8002434: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8002436: 2300 movs r3, #0 8002438: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800243a: 463b mov r3, r7 800243c: 4619 mov r1, r3 800243e: 4806 ldr r0, [pc, #24] @ (8002458 ) 8002440: f002 ff56 bl 80052f0 8002444: 4603 mov r3, r0 8002446: 2b00 cmp r3, #0 8002448: d001 beq.n 800244e { Error_Handler(); 800244a: f7ff fe49 bl 80020e0 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 800244e: bf00 nop 8002450: 3718 adds r7, #24 8002452: 46bd mov sp, r7 8002454: bd80 pop {r7, pc} 8002456: bf00 nop 8002458: 20000310 .word 0x20000310 800245c: 40000400 .word 0x40000400 08002460 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8002460: b580 push {r7, lr} 8002462: b084 sub sp, #16 8002464: af00 add r7, sp, #0 8002466: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 8002468: 687b ldr r3, [r7, #4] 800246a: 681b ldr r3, [r3, #0] 800246c: 4a0d ldr r2, [pc, #52] @ (80024a4 ) 800246e: 4293 cmp r3, r2 8002470: d113 bne.n 800249a { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8002472: 4b0d ldr r3, [pc, #52] @ (80024a8 ) 8002474: 69db ldr r3, [r3, #28] 8002476: 4a0c ldr r2, [pc, #48] @ (80024a8 ) 8002478: f043 0302 orr.w r3, r3, #2 800247c: 61d3 str r3, [r2, #28] 800247e: 4b0a ldr r3, [pc, #40] @ (80024a8 ) 8002480: 69db ldr r3, [r3, #28] 8002482: f003 0302 and.w r3, r3, #2 8002486: 60fb str r3, [r7, #12] 8002488: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800248a: 2200 movs r2, #0 800248c: 2100 movs r1, #0 800248e: 201d movs r0, #29 8002490: f000 fbfb bl 8002c8a HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002494: 201d movs r0, #29 8002496: f000 fc14 bl 8002cc2 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800249a: bf00 nop 800249c: 3710 adds r7, #16 800249e: 46bd mov sp, r7 80024a0: bd80 pop {r7, pc} 80024a2: bf00 nop 80024a4: 40000400 .word 0x40000400 80024a8: 40021000 .word 0x40021000 080024ac : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 80024ac: b580 push {r7, lr} 80024ae: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80024b0: 4b11 ldr r3, [pc, #68] @ (80024f8 ) 80024b2: 4a12 ldr r2, [pc, #72] @ (80024fc ) 80024b4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80024b6: 4b10 ldr r3, [pc, #64] @ (80024f8 ) 80024b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80024bc: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80024be: 4b0e ldr r3, [pc, #56] @ (80024f8 ) 80024c0: 2200 movs r2, #0 80024c2: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80024c4: 4b0c ldr r3, [pc, #48] @ (80024f8 ) 80024c6: 2200 movs r2, #0 80024c8: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80024ca: 4b0b ldr r3, [pc, #44] @ (80024f8 ) 80024cc: 2200 movs r2, #0 80024ce: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80024d0: 4b09 ldr r3, [pc, #36] @ (80024f8 ) 80024d2: 220c movs r2, #12 80024d4: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80024d6: 4b08 ldr r3, [pc, #32] @ (80024f8 ) 80024d8: 2200 movs r2, #0 80024da: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80024dc: 4b06 ldr r3, [pc, #24] @ (80024f8 ) 80024de: 2200 movs r2, #0 80024e0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80024e2: 4805 ldr r0, [pc, #20] @ (80024f8 ) 80024e4: f002 ff74 bl 80053d0 80024e8: 4603 mov r3, r0 80024ea: 2b00 cmp r3, #0 80024ec: d001 beq.n 80024f2 { Error_Handler(); 80024ee: f7ff fdf7 bl 80020e0 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80024f2: bf00 nop 80024f4: bd80 pop {r7, pc} 80024f6: bf00 nop 80024f8: 20000358 .word 0x20000358 80024fc: 40013800 .word 0x40013800 08002500 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8002500: b580 push {r7, lr} 8002502: b088 sub sp, #32 8002504: af00 add r7, sp, #0 8002506: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002508: f107 0310 add.w r3, r7, #16 800250c: 2200 movs r2, #0 800250e: 601a str r2, [r3, #0] 8002510: 605a str r2, [r3, #4] 8002512: 609a str r2, [r3, #8] 8002514: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 8002516: 687b ldr r3, [r7, #4] 8002518: 681b ldr r3, [r3, #0] 800251a: 4a20 ldr r2, [pc, #128] @ (800259c ) 800251c: 4293 cmp r3, r2 800251e: d139 bne.n 8002594 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8002520: 4b1f ldr r3, [pc, #124] @ (80025a0 ) 8002522: 699b ldr r3, [r3, #24] 8002524: 4a1e ldr r2, [pc, #120] @ (80025a0 ) 8002526: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800252a: 6193 str r3, [r2, #24] 800252c: 4b1c ldr r3, [pc, #112] @ (80025a0 ) 800252e: 699b ldr r3, [r3, #24] 8002530: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002534: 60fb str r3, [r7, #12] 8002536: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002538: 4b19 ldr r3, [pc, #100] @ (80025a0 ) 800253a: 699b ldr r3, [r3, #24] 800253c: 4a18 ldr r2, [pc, #96] @ (80025a0 ) 800253e: f043 0304 orr.w r3, r3, #4 8002542: 6193 str r3, [r2, #24] 8002544: 4b16 ldr r3, [pc, #88] @ (80025a0 ) 8002546: 699b ldr r3, [r3, #24] 8002548: f003 0304 and.w r3, r3, #4 800254c: 60bb str r3, [r7, #8] 800254e: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 8002550: f44f 7300 mov.w r3, #512 @ 0x200 8002554: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002556: 2302 movs r3, #2 8002558: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 800255a: 2301 movs r3, #1 800255c: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 800255e: f107 0310 add.w r3, r7, #16 8002562: 4619 mov r1, r3 8002564: 480f ldr r0, [pc, #60] @ (80025a4 ) 8002566: f000 fc79 bl 8002e5c GPIO_InitStruct.Pin = RX_RS485_Pin; 800256a: f44f 6380 mov.w r3, #1024 @ 0x400 800256e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002570: 2300 movs r3, #0 8002572: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002574: 2300 movs r3, #0 8002576: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 8002578: f107 0310 add.w r3, r7, #16 800257c: 4619 mov r1, r3 800257e: 4809 ldr r0, [pc, #36] @ (80025a4 ) 8002580: f000 fc6c bl 8002e5c /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8002584: 2200 movs r2, #0 8002586: 2100 movs r1, #0 8002588: 2025 movs r0, #37 @ 0x25 800258a: f000 fb7e bl 8002c8a HAL_NVIC_EnableIRQ(USART1_IRQn); 800258e: 2025 movs r0, #37 @ 0x25 8002590: f000 fb97 bl 8002cc2 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002594: bf00 nop 8002596: 3720 adds r7, #32 8002598: 46bd mov sp, r7 800259a: bd80 pop {r7, pc} 800259c: 40013800 .word 0x40013800 80025a0: 40021000 .word 0x40021000 80025a4: 40010800 .word 0x40010800 080025a8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 80025a8: f7ff ff06 bl 80023b8 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80025ac: 480b ldr r0, [pc, #44] @ (80025dc ) ldr r1, =_edata 80025ae: 490c ldr r1, [pc, #48] @ (80025e0 ) ldr r2, =_sidata 80025b0: 4a0c ldr r2, [pc, #48] @ (80025e4 ) movs r3, #0 80025b2: 2300 movs r3, #0 b LoopCopyDataInit 80025b4: e002 b.n 80025bc 080025b6 : CopyDataInit: ldr r4, [r2, r3] 80025b6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80025b8: 50c4 str r4, [r0, r3] adds r3, r3, #4 80025ba: 3304 adds r3, #4 080025bc : LoopCopyDataInit: adds r4, r0, r3 80025bc: 18c4 adds r4, r0, r3 cmp r4, r1 80025be: 428c cmp r4, r1 bcc CopyDataInit 80025c0: d3f9 bcc.n 80025b6 /* Zero fill the bss segment. */ ldr r2, =_sbss 80025c2: 4a09 ldr r2, [pc, #36] @ (80025e8 ) ldr r4, =_ebss 80025c4: 4c09 ldr r4, [pc, #36] @ (80025ec ) movs r3, #0 80025c6: 2300 movs r3, #0 b LoopFillZerobss 80025c8: e001 b.n 80025ce 080025ca : FillZerobss: str r3, [r2] 80025ca: 6013 str r3, [r2, #0] adds r2, r2, #4 80025cc: 3204 adds r2, #4 080025ce : LoopFillZerobss: cmp r2, r4 80025ce: 42a2 cmp r2, r4 bcc FillZerobss 80025d0: d3fb bcc.n 80025ca /* Call static constructors */ bl __libc_init_array 80025d2: f003 fd21 bl 8006018 <__libc_init_array> /* Call the application's entry point.*/ bl main 80025d6: f7ff faef bl 8001bb8

bx lr 80025da: 4770 bx lr ldr r0, =_sdata 80025dc: 20000000 .word 0x20000000 ldr r1, =_edata 80025e0: 20000060 .word 0x20000060 ldr r2, =_sidata 80025e4: 080062e4 .word 0x080062e4 ldr r2, =_sbss 80025e8: 20000060 .word 0x20000060 ldr r4, =_ebss 80025ec: 200004dc .word 0x200004dc 080025f0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80025f0: e7fe b.n 80025f0 ... 080025f4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80025f4: b580 push {r7, lr} 80025f6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80025f8: 4b08 ldr r3, [pc, #32] @ (800261c ) 80025fa: 681b ldr r3, [r3, #0] 80025fc: 4a07 ldr r2, [pc, #28] @ (800261c ) 80025fe: f043 0310 orr.w r3, r3, #16 8002602: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002604: 2003 movs r0, #3 8002606: f000 fb35 bl 8002c74 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800260a: 200f movs r0, #15 800260c: f000 f808 bl 8002620 /* Init the low level hardware */ HAL_MspInit(); 8002610: f7ff fe60 bl 80022d4 /* Return function status */ return HAL_OK; 8002614: 2300 movs r3, #0 } 8002616: 4618 mov r0, r3 8002618: bd80 pop {r7, pc} 800261a: bf00 nop 800261c: 40022000 .word 0x40022000 08002620 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8002620: b580 push {r7, lr} 8002622: b082 sub sp, #8 8002624: af00 add r7, sp, #0 8002626: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8002628: 4b12 ldr r3, [pc, #72] @ (8002674 ) 800262a: 681a ldr r2, [r3, #0] 800262c: 4b12 ldr r3, [pc, #72] @ (8002678 ) 800262e: 781b ldrb r3, [r3, #0] 8002630: 4619 mov r1, r3 8002632: f44f 737a mov.w r3, #1000 @ 0x3e8 8002636: fbb3 f3f1 udiv r3, r3, r1 800263a: fbb2 f3f3 udiv r3, r2, r3 800263e: 4618 mov r0, r3 8002640: f000 fb4d bl 8002cde 8002644: 4603 mov r3, r0 8002646: 2b00 cmp r3, #0 8002648: d001 beq.n 800264e { return HAL_ERROR; 800264a: 2301 movs r3, #1 800264c: e00e b.n 800266c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800264e: 687b ldr r3, [r7, #4] 8002650: 2b0f cmp r3, #15 8002652: d80a bhi.n 800266a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8002654: 2200 movs r2, #0 8002656: 6879 ldr r1, [r7, #4] 8002658: f04f 30ff mov.w r0, #4294967295 800265c: f000 fb15 bl 8002c8a uwTickPrio = TickPriority; 8002660: 4a06 ldr r2, [pc, #24] @ (800267c ) 8002662: 687b ldr r3, [r7, #4] 8002664: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8002666: 2300 movs r3, #0 8002668: e000 b.n 800266c return HAL_ERROR; 800266a: 2301 movs r3, #1 } 800266c: 4618 mov r0, r3 800266e: 3708 adds r7, #8 8002670: 46bd mov sp, r7 8002672: bd80 pop {r7, pc} 8002674: 20000004 .word 0x20000004 8002678: 2000000c .word 0x2000000c 800267c: 20000008 .word 0x20000008 08002680 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8002680: b480 push {r7} 8002682: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002684: 4b05 ldr r3, [pc, #20] @ (800269c ) 8002686: 781b ldrb r3, [r3, #0] 8002688: 461a mov r2, r3 800268a: 4b05 ldr r3, [pc, #20] @ (80026a0 ) 800268c: 681b ldr r3, [r3, #0] 800268e: 4413 add r3, r2 8002690: 4a03 ldr r2, [pc, #12] @ (80026a0 ) 8002692: 6013 str r3, [r2, #0] } 8002694: bf00 nop 8002696: 46bd mov sp, r7 8002698: bc80 pop {r7} 800269a: 4770 bx lr 800269c: 2000000c .word 0x2000000c 80026a0: 200003a0 .word 0x200003a0 080026a4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80026a4: b480 push {r7} 80026a6: af00 add r7, sp, #0 return uwTick; 80026a8: 4b02 ldr r3, [pc, #8] @ (80026b4 ) 80026aa: 681b ldr r3, [r3, #0] } 80026ac: 4618 mov r0, r3 80026ae: 46bd mov sp, r7 80026b0: bc80 pop {r7} 80026b2: 4770 bx lr 80026b4: 200003a0 .word 0x200003a0 080026b8 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80026b8: b580 push {r7, lr} 80026ba: b086 sub sp, #24 80026bc: af00 add r7, sp, #0 80026be: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80026c0: 2300 movs r3, #0 80026c2: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 80026c4: 2300 movs r3, #0 80026c6: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 80026c8: 2300 movs r3, #0 80026ca: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 80026cc: 2300 movs r3, #0 80026ce: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 80026d0: 687b ldr r3, [r7, #4] 80026d2: 2b00 cmp r3, #0 80026d4: d101 bne.n 80026da { return HAL_ERROR; 80026d6: 2301 movs r3, #1 80026d8: e0be b.n 8002858 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80026da: 687b ldr r3, [r7, #4] 80026dc: 689b ldr r3, [r3, #8] 80026de: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80026e0: 687b ldr r3, [r7, #4] 80026e2: 6a9b ldr r3, [r3, #40] @ 0x28 80026e4: 2b00 cmp r3, #0 80026e6: d109 bne.n 80026fc { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 80026e8: 687b ldr r3, [r7, #4] 80026ea: 2200 movs r2, #0 80026ec: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 80026ee: 687b ldr r3, [r7, #4] 80026f0: 2200 movs r2, #0 80026f2: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80026f6: 6878 ldr r0, [r7, #4] 80026f8: f7fe fdb2 bl 8001260 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80026fc: 6878 ldr r0, [r7, #4] 80026fe: f000 f9ab bl 8002a58 8002702: 4603 mov r3, r0 8002704: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8002706: 687b ldr r3, [r7, #4] 8002708: 6a9b ldr r3, [r3, #40] @ 0x28 800270a: f003 0310 and.w r3, r3, #16 800270e: 2b00 cmp r3, #0 8002710: f040 8099 bne.w 8002846 8002714: 7dfb ldrb r3, [r7, #23] 8002716: 2b00 cmp r3, #0 8002718: f040 8095 bne.w 8002846 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800271c: 687b ldr r3, [r7, #4] 800271e: 6a9b ldr r3, [r3, #40] @ 0x28 8002720: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8002724: f023 0302 bic.w r3, r3, #2 8002728: f043 0202 orr.w r2, r3, #2 800272c: 687b ldr r3, [r7, #4] 800272e: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8002730: 687b ldr r3, [r7, #4] 8002732: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002734: 687b ldr r3, [r7, #4] 8002736: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8002738: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800273a: 687b ldr r3, [r7, #4] 800273c: 7b1b ldrb r3, [r3, #12] 800273e: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002740: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8002742: 68ba ldr r2, [r7, #8] 8002744: 4313 orrs r3, r2 8002746: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8002748: 687b ldr r3, [r7, #4] 800274a: 689b ldr r3, [r3, #8] 800274c: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002750: d003 beq.n 800275a 8002752: 687b ldr r3, [r7, #4] 8002754: 689b ldr r3, [r3, #8] 8002756: 2b01 cmp r3, #1 8002758: d102 bne.n 8002760 800275a: f44f 7380 mov.w r3, #256 @ 0x100 800275e: e000 b.n 8002762 8002760: 2300 movs r3, #0 8002762: 693a ldr r2, [r7, #16] 8002764: 4313 orrs r3, r2 8002766: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8002768: 687b ldr r3, [r7, #4] 800276a: 7d1b ldrb r3, [r3, #20] 800276c: 2b01 cmp r3, #1 800276e: d119 bne.n 80027a4 { if (hadc->Init.ContinuousConvMode == DISABLE) 8002770: 687b ldr r3, [r7, #4] 8002772: 7b1b ldrb r3, [r3, #12] 8002774: 2b00 cmp r3, #0 8002776: d109 bne.n 800278c { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8002778: 687b ldr r3, [r7, #4] 800277a: 699b ldr r3, [r3, #24] 800277c: 3b01 subs r3, #1 800277e: 035a lsls r2, r3, #13 8002780: 693b ldr r3, [r7, #16] 8002782: 4313 orrs r3, r2 8002784: f443 6300 orr.w r3, r3, #2048 @ 0x800 8002788: 613b str r3, [r7, #16] 800278a: e00b b.n 80027a4 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800278c: 687b ldr r3, [r7, #4] 800278e: 6a9b ldr r3, [r3, #40] @ 0x28 8002790: f043 0220 orr.w r2, r3, #32 8002794: 687b ldr r3, [r7, #4] 8002796: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002798: 687b ldr r3, [r7, #4] 800279a: 6adb ldr r3, [r3, #44] @ 0x2c 800279c: f043 0201 orr.w r2, r3, #1 80027a0: 687b ldr r3, [r7, #4] 80027a2: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80027a4: 687b ldr r3, [r7, #4] 80027a6: 681b ldr r3, [r3, #0] 80027a8: 685b ldr r3, [r3, #4] 80027aa: f423 4169 bic.w r1, r3, #59648 @ 0xe900 80027ae: 687b ldr r3, [r7, #4] 80027b0: 681b ldr r3, [r3, #0] 80027b2: 693a ldr r2, [r7, #16] 80027b4: 430a orrs r2, r1 80027b6: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80027b8: 687b ldr r3, [r7, #4] 80027ba: 681b ldr r3, [r3, #0] 80027bc: 689a ldr r2, [r3, #8] 80027be: 4b28 ldr r3, [pc, #160] @ (8002860 ) 80027c0: 4013 ands r3, r2 80027c2: 687a ldr r2, [r7, #4] 80027c4: 6812 ldr r2, [r2, #0] 80027c6: 68b9 ldr r1, [r7, #8] 80027c8: 430b orrs r3, r1 80027ca: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 80027cc: 687b ldr r3, [r7, #4] 80027ce: 689b ldr r3, [r3, #8] 80027d0: f5b3 7f80 cmp.w r3, #256 @ 0x100 80027d4: d003 beq.n 80027de 80027d6: 687b ldr r3, [r7, #4] 80027d8: 689b ldr r3, [r3, #8] 80027da: 2b01 cmp r3, #1 80027dc: d104 bne.n 80027e8 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 80027de: 687b ldr r3, [r7, #4] 80027e0: 691b ldr r3, [r3, #16] 80027e2: 3b01 subs r3, #1 80027e4: 051b lsls r3, r3, #20 80027e6: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 80027e8: 687b ldr r3, [r7, #4] 80027ea: 681b ldr r3, [r3, #0] 80027ec: 6adb ldr r3, [r3, #44] @ 0x2c 80027ee: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 80027f2: 687b ldr r3, [r7, #4] 80027f4: 681b ldr r3, [r3, #0] 80027f6: 68fa ldr r2, [r7, #12] 80027f8: 430a orrs r2, r1 80027fa: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80027fc: 687b ldr r3, [r7, #4] 80027fe: 681b ldr r3, [r3, #0] 8002800: 689a ldr r2, [r3, #8] 8002802: 4b18 ldr r3, [pc, #96] @ (8002864 ) 8002804: 4013 ands r3, r2 8002806: 68ba ldr r2, [r7, #8] 8002808: 429a cmp r2, r3 800280a: d10b bne.n 8002824 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800280c: 687b ldr r3, [r7, #4] 800280e: 2200 movs r2, #0 8002810: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002812: 687b ldr r3, [r7, #4] 8002814: 6a9b ldr r3, [r3, #40] @ 0x28 8002816: f023 0303 bic.w r3, r3, #3 800281a: f043 0201 orr.w r2, r3, #1 800281e: 687b ldr r3, [r7, #4] 8002820: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002822: e018 b.n 8002856 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002824: 687b ldr r3, [r7, #4] 8002826: 6a9b ldr r3, [r3, #40] @ 0x28 8002828: f023 0312 bic.w r3, r3, #18 800282c: f043 0210 orr.w r2, r3, #16 8002830: 687b ldr r3, [r7, #4] 8002832: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002834: 687b ldr r3, [r7, #4] 8002836: 6adb ldr r3, [r3, #44] @ 0x2c 8002838: f043 0201 orr.w r2, r3, #1 800283c: 687b ldr r3, [r7, #4] 800283e: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8002840: 2301 movs r3, #1 8002842: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002844: e007 b.n 8002856 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002846: 687b ldr r3, [r7, #4] 8002848: 6a9b ldr r3, [r3, #40] @ 0x28 800284a: f043 0210 orr.w r2, r3, #16 800284e: 687b ldr r3, [r7, #4] 8002850: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8002852: 2301 movs r3, #1 8002854: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8002856: 7dfb ldrb r3, [r7, #23] } 8002858: 4618 mov r0, r3 800285a: 3718 adds r7, #24 800285c: 46bd mov sp, r7 800285e: bd80 pop {r7, pc} 8002860: ffe1f7fd .word 0xffe1f7fd 8002864: ff1f0efe .word 0xff1f0efe 08002868 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002868: b480 push {r7} 800286a: b085 sub sp, #20 800286c: af00 add r7, sp, #0 800286e: 6078 str r0, [r7, #4] 8002870: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002872: 2300 movs r3, #0 8002874: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8002876: 2300 movs r3, #0 8002878: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800287a: 687b ldr r3, [r7, #4] 800287c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8002880: 2b01 cmp r3, #1 8002882: d101 bne.n 8002888 8002884: 2302 movs r3, #2 8002886: e0dc b.n 8002a42 8002888: 687b ldr r3, [r7, #4] 800288a: 2201 movs r2, #1 800288c: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8002890: 683b ldr r3, [r7, #0] 8002892: 685b ldr r3, [r3, #4] 8002894: 2b06 cmp r3, #6 8002896: d81c bhi.n 80028d2 { MODIFY_REG(hadc->Instance->SQR3 , 8002898: 687b ldr r3, [r7, #4] 800289a: 681b ldr r3, [r3, #0] 800289c: 6b59 ldr r1, [r3, #52] @ 0x34 800289e: 683b ldr r3, [r7, #0] 80028a0: 685a ldr r2, [r3, #4] 80028a2: 4613 mov r3, r2 80028a4: 009b lsls r3, r3, #2 80028a6: 4413 add r3, r2 80028a8: 3b05 subs r3, #5 80028aa: 221f movs r2, #31 80028ac: fa02 f303 lsl.w r3, r2, r3 80028b0: 43db mvns r3, r3 80028b2: 4019 ands r1, r3 80028b4: 683b ldr r3, [r7, #0] 80028b6: 6818 ldr r0, [r3, #0] 80028b8: 683b ldr r3, [r7, #0] 80028ba: 685a ldr r2, [r3, #4] 80028bc: 4613 mov r3, r2 80028be: 009b lsls r3, r3, #2 80028c0: 4413 add r3, r2 80028c2: 3b05 subs r3, #5 80028c4: fa00 f203 lsl.w r2, r0, r3 80028c8: 687b ldr r3, [r7, #4] 80028ca: 681b ldr r3, [r3, #0] 80028cc: 430a orrs r2, r1 80028ce: 635a str r2, [r3, #52] @ 0x34 80028d0: e03c b.n 800294c ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80028d2: 683b ldr r3, [r7, #0] 80028d4: 685b ldr r3, [r3, #4] 80028d6: 2b0c cmp r3, #12 80028d8: d81c bhi.n 8002914 { MODIFY_REG(hadc->Instance->SQR2 , 80028da: 687b ldr r3, [r7, #4] 80028dc: 681b ldr r3, [r3, #0] 80028de: 6b19 ldr r1, [r3, #48] @ 0x30 80028e0: 683b ldr r3, [r7, #0] 80028e2: 685a ldr r2, [r3, #4] 80028e4: 4613 mov r3, r2 80028e6: 009b lsls r3, r3, #2 80028e8: 4413 add r3, r2 80028ea: 3b23 subs r3, #35 @ 0x23 80028ec: 221f movs r2, #31 80028ee: fa02 f303 lsl.w r3, r2, r3 80028f2: 43db mvns r3, r3 80028f4: 4019 ands r1, r3 80028f6: 683b ldr r3, [r7, #0] 80028f8: 6818 ldr r0, [r3, #0] 80028fa: 683b ldr r3, [r7, #0] 80028fc: 685a ldr r2, [r3, #4] 80028fe: 4613 mov r3, r2 8002900: 009b lsls r3, r3, #2 8002902: 4413 add r3, r2 8002904: 3b23 subs r3, #35 @ 0x23 8002906: fa00 f203 lsl.w r2, r0, r3 800290a: 687b ldr r3, [r7, #4] 800290c: 681b ldr r3, [r3, #0] 800290e: 430a orrs r2, r1 8002910: 631a str r2, [r3, #48] @ 0x30 8002912: e01b b.n 800294c ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8002914: 687b ldr r3, [r7, #4] 8002916: 681b ldr r3, [r3, #0] 8002918: 6ad9 ldr r1, [r3, #44] @ 0x2c 800291a: 683b ldr r3, [r7, #0] 800291c: 685a ldr r2, [r3, #4] 800291e: 4613 mov r3, r2 8002920: 009b lsls r3, r3, #2 8002922: 4413 add r3, r2 8002924: 3b41 subs r3, #65 @ 0x41 8002926: 221f movs r2, #31 8002928: fa02 f303 lsl.w r3, r2, r3 800292c: 43db mvns r3, r3 800292e: 4019 ands r1, r3 8002930: 683b ldr r3, [r7, #0] 8002932: 6818 ldr r0, [r3, #0] 8002934: 683b ldr r3, [r7, #0] 8002936: 685a ldr r2, [r3, #4] 8002938: 4613 mov r3, r2 800293a: 009b lsls r3, r3, #2 800293c: 4413 add r3, r2 800293e: 3b41 subs r3, #65 @ 0x41 8002940: fa00 f203 lsl.w r2, r0, r3 8002944: 687b ldr r3, [r7, #4] 8002946: 681b ldr r3, [r3, #0] 8002948: 430a orrs r2, r1 800294a: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800294c: 683b ldr r3, [r7, #0] 800294e: 681b ldr r3, [r3, #0] 8002950: 2b09 cmp r3, #9 8002952: d91c bls.n 800298e { MODIFY_REG(hadc->Instance->SMPR1 , 8002954: 687b ldr r3, [r7, #4] 8002956: 681b ldr r3, [r3, #0] 8002958: 68d9 ldr r1, [r3, #12] 800295a: 683b ldr r3, [r7, #0] 800295c: 681a ldr r2, [r3, #0] 800295e: 4613 mov r3, r2 8002960: 005b lsls r3, r3, #1 8002962: 4413 add r3, r2 8002964: 3b1e subs r3, #30 8002966: 2207 movs r2, #7 8002968: fa02 f303 lsl.w r3, r2, r3 800296c: 43db mvns r3, r3 800296e: 4019 ands r1, r3 8002970: 683b ldr r3, [r7, #0] 8002972: 6898 ldr r0, [r3, #8] 8002974: 683b ldr r3, [r7, #0] 8002976: 681a ldr r2, [r3, #0] 8002978: 4613 mov r3, r2 800297a: 005b lsls r3, r3, #1 800297c: 4413 add r3, r2 800297e: 3b1e subs r3, #30 8002980: fa00 f203 lsl.w r2, r0, r3 8002984: 687b ldr r3, [r7, #4] 8002986: 681b ldr r3, [r3, #0] 8002988: 430a orrs r2, r1 800298a: 60da str r2, [r3, #12] 800298c: e019 b.n 80029c2 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800298e: 687b ldr r3, [r7, #4] 8002990: 681b ldr r3, [r3, #0] 8002992: 6919 ldr r1, [r3, #16] 8002994: 683b ldr r3, [r7, #0] 8002996: 681a ldr r2, [r3, #0] 8002998: 4613 mov r3, r2 800299a: 005b lsls r3, r3, #1 800299c: 4413 add r3, r2 800299e: 2207 movs r2, #7 80029a0: fa02 f303 lsl.w r3, r2, r3 80029a4: 43db mvns r3, r3 80029a6: 4019 ands r1, r3 80029a8: 683b ldr r3, [r7, #0] 80029aa: 6898 ldr r0, [r3, #8] 80029ac: 683b ldr r3, [r7, #0] 80029ae: 681a ldr r2, [r3, #0] 80029b0: 4613 mov r3, r2 80029b2: 005b lsls r3, r3, #1 80029b4: 4413 add r3, r2 80029b6: fa00 f203 lsl.w r2, r0, r3 80029ba: 687b ldr r3, [r7, #4] 80029bc: 681b ldr r3, [r3, #0] 80029be: 430a orrs r2, r1 80029c0: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80029c2: 683b ldr r3, [r7, #0] 80029c4: 681b ldr r3, [r3, #0] 80029c6: 2b10 cmp r3, #16 80029c8: d003 beq.n 80029d2 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80029ca: 683b ldr r3, [r7, #0] 80029cc: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80029ce: 2b11 cmp r3, #17 80029d0: d132 bne.n 8002a38 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80029d2: 687b ldr r3, [r7, #4] 80029d4: 681b ldr r3, [r3, #0] 80029d6: 4a1d ldr r2, [pc, #116] @ (8002a4c ) 80029d8: 4293 cmp r3, r2 80029da: d125 bne.n 8002a28 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80029dc: 687b ldr r3, [r7, #4] 80029de: 681b ldr r3, [r3, #0] 80029e0: 689b ldr r3, [r3, #8] 80029e2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80029e6: 2b00 cmp r3, #0 80029e8: d126 bne.n 8002a38 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80029ea: 687b ldr r3, [r7, #4] 80029ec: 681b ldr r3, [r3, #0] 80029ee: 689a ldr r2, [r3, #8] 80029f0: 687b ldr r3, [r7, #4] 80029f2: 681b ldr r3, [r3, #0] 80029f4: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 80029f8: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 80029fa: 683b ldr r3, [r7, #0] 80029fc: 681b ldr r3, [r3, #0] 80029fe: 2b10 cmp r3, #16 8002a00: d11a bne.n 8002a38 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8002a02: 4b13 ldr r3, [pc, #76] @ (8002a50 ) 8002a04: 681b ldr r3, [r3, #0] 8002a06: 4a13 ldr r2, [pc, #76] @ (8002a54 ) 8002a08: fba2 2303 umull r2, r3, r2, r3 8002a0c: 0c9a lsrs r2, r3, #18 8002a0e: 4613 mov r3, r2 8002a10: 009b lsls r3, r3, #2 8002a12: 4413 add r3, r2 8002a14: 005b lsls r3, r3, #1 8002a16: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002a18: e002 b.n 8002a20 { wait_loop_index--; 8002a1a: 68bb ldr r3, [r7, #8] 8002a1c: 3b01 subs r3, #1 8002a1e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002a20: 68bb ldr r3, [r7, #8] 8002a22: 2b00 cmp r3, #0 8002a24: d1f9 bne.n 8002a1a 8002a26: e007 b.n 8002a38 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002a28: 687b ldr r3, [r7, #4] 8002a2a: 6a9b ldr r3, [r3, #40] @ 0x28 8002a2c: f043 0220 orr.w r2, r3, #32 8002a30: 687b ldr r3, [r7, #4] 8002a32: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8002a34: 2301 movs r3, #1 8002a36: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002a38: 687b ldr r3, [r7, #4] 8002a3a: 2200 movs r2, #0 8002a3c: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8002a40: 7bfb ldrb r3, [r7, #15] } 8002a42: 4618 mov r0, r3 8002a44: 3714 adds r7, #20 8002a46: 46bd mov sp, r7 8002a48: bc80 pop {r7} 8002a4a: 4770 bx lr 8002a4c: 40012400 .word 0x40012400 8002a50: 20000004 .word 0x20000004 8002a54: 431bde83 .word 0x431bde83 08002a58 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8002a58: b580 push {r7, lr} 8002a5a: b084 sub sp, #16 8002a5c: af00 add r7, sp, #0 8002a5e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002a60: 2300 movs r3, #0 8002a62: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002a64: 687b ldr r3, [r7, #4] 8002a66: 681b ldr r3, [r3, #0] 8002a68: 689b ldr r3, [r3, #8] 8002a6a: f003 0301 and.w r3, r3, #1 8002a6e: 2b01 cmp r3, #1 8002a70: d12e bne.n 8002ad0 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8002a72: 687b ldr r3, [r7, #4] 8002a74: 681b ldr r3, [r3, #0] 8002a76: 689a ldr r2, [r3, #8] 8002a78: 687b ldr r3, [r7, #4] 8002a7a: 681b ldr r3, [r3, #0] 8002a7c: f022 0201 bic.w r2, r2, #1 8002a80: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8002a82: f7ff fe0f bl 80026a4 8002a86: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002a88: e01b b.n 8002ac2 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002a8a: f7ff fe0b bl 80026a4 8002a8e: 4602 mov r2, r0 8002a90: 68fb ldr r3, [r7, #12] 8002a92: 1ad3 subs r3, r2, r3 8002a94: 2b02 cmp r3, #2 8002a96: d914 bls.n 8002ac2 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8002a98: 687b ldr r3, [r7, #4] 8002a9a: 681b ldr r3, [r3, #0] 8002a9c: 689b ldr r3, [r3, #8] 8002a9e: f003 0301 and.w r3, r3, #1 8002aa2: 2b01 cmp r3, #1 8002aa4: d10d bne.n 8002ac2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002aa6: 687b ldr r3, [r7, #4] 8002aa8: 6a9b ldr r3, [r3, #40] @ 0x28 8002aaa: f043 0210 orr.w r2, r3, #16 8002aae: 687b ldr r3, [r7, #4] 8002ab0: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 6adb ldr r3, [r3, #44] @ 0x2c 8002ab6: f043 0201 orr.w r2, r3, #1 8002aba: 687b ldr r3, [r7, #4] 8002abc: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 8002abe: 2301 movs r3, #1 8002ac0: e007 b.n 8002ad2 while(ADC_IS_ENABLE(hadc) != RESET) 8002ac2: 687b ldr r3, [r7, #4] 8002ac4: 681b ldr r3, [r3, #0] 8002ac6: 689b ldr r3, [r3, #8] 8002ac8: f003 0301 and.w r3, r3, #1 8002acc: 2b01 cmp r3, #1 8002ace: d0dc beq.n 8002a8a } } } /* Return HAL status */ return HAL_OK; 8002ad0: 2300 movs r3, #0 } 8002ad2: 4618 mov r0, r3 8002ad4: 3710 adds r7, #16 8002ad6: 46bd mov sp, r7 8002ad8: bd80 pop {r7, pc} ... 08002adc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002adc: b480 push {r7} 8002ade: b085 sub sp, #20 8002ae0: af00 add r7, sp, #0 8002ae2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002ae4: 687b ldr r3, [r7, #4] 8002ae6: f003 0307 and.w r3, r3, #7 8002aea: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002aec: 4b0c ldr r3, [pc, #48] @ (8002b20 <__NVIC_SetPriorityGrouping+0x44>) 8002aee: 68db ldr r3, [r3, #12] 8002af0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002af2: 68ba ldr r2, [r7, #8] 8002af4: f64f 03ff movw r3, #63743 @ 0xf8ff 8002af8: 4013 ands r3, r2 8002afa: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002afc: 68fb ldr r3, [r7, #12] 8002afe: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002b00: 68bb ldr r3, [r7, #8] 8002b02: 4313 orrs r3, r2 reg_value = (reg_value | 8002b04: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002b08: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8002b0c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002b0e: 4a04 ldr r2, [pc, #16] @ (8002b20 <__NVIC_SetPriorityGrouping+0x44>) 8002b10: 68bb ldr r3, [r7, #8] 8002b12: 60d3 str r3, [r2, #12] } 8002b14: bf00 nop 8002b16: 3714 adds r7, #20 8002b18: 46bd mov sp, r7 8002b1a: bc80 pop {r7} 8002b1c: 4770 bx lr 8002b1e: bf00 nop 8002b20: e000ed00 .word 0xe000ed00 08002b24 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8002b24: b480 push {r7} 8002b26: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002b28: 4b04 ldr r3, [pc, #16] @ (8002b3c <__NVIC_GetPriorityGrouping+0x18>) 8002b2a: 68db ldr r3, [r3, #12] 8002b2c: 0a1b lsrs r3, r3, #8 8002b2e: f003 0307 and.w r3, r3, #7 } 8002b32: 4618 mov r0, r3 8002b34: 46bd mov sp, r7 8002b36: bc80 pop {r7} 8002b38: 4770 bx lr 8002b3a: bf00 nop 8002b3c: e000ed00 .word 0xe000ed00 08002b40 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002b40: b480 push {r7} 8002b42: b083 sub sp, #12 8002b44: af00 add r7, sp, #0 8002b46: 4603 mov r3, r0 8002b48: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002b4a: f997 3007 ldrsb.w r3, [r7, #7] 8002b4e: 2b00 cmp r3, #0 8002b50: db0b blt.n 8002b6a <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002b52: 79fb ldrb r3, [r7, #7] 8002b54: f003 021f and.w r2, r3, #31 8002b58: 4906 ldr r1, [pc, #24] @ (8002b74 <__NVIC_EnableIRQ+0x34>) 8002b5a: f997 3007 ldrsb.w r3, [r7, #7] 8002b5e: 095b lsrs r3, r3, #5 8002b60: 2001 movs r0, #1 8002b62: fa00 f202 lsl.w r2, r0, r2 8002b66: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8002b6a: bf00 nop 8002b6c: 370c adds r7, #12 8002b6e: 46bd mov sp, r7 8002b70: bc80 pop {r7} 8002b72: 4770 bx lr 8002b74: e000e100 .word 0xe000e100 08002b78 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002b78: b480 push {r7} 8002b7a: b083 sub sp, #12 8002b7c: af00 add r7, sp, #0 8002b7e: 4603 mov r3, r0 8002b80: 6039 str r1, [r7, #0] 8002b82: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002b84: f997 3007 ldrsb.w r3, [r7, #7] 8002b88: 2b00 cmp r3, #0 8002b8a: db0a blt.n 8002ba2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002b8c: 683b ldr r3, [r7, #0] 8002b8e: b2da uxtb r2, r3 8002b90: 490c ldr r1, [pc, #48] @ (8002bc4 <__NVIC_SetPriority+0x4c>) 8002b92: f997 3007 ldrsb.w r3, [r7, #7] 8002b96: 0112 lsls r2, r2, #4 8002b98: b2d2 uxtb r2, r2 8002b9a: 440b add r3, r1 8002b9c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002ba0: e00a b.n 8002bb8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002ba2: 683b ldr r3, [r7, #0] 8002ba4: b2da uxtb r2, r3 8002ba6: 4908 ldr r1, [pc, #32] @ (8002bc8 <__NVIC_SetPriority+0x50>) 8002ba8: 79fb ldrb r3, [r7, #7] 8002baa: f003 030f and.w r3, r3, #15 8002bae: 3b04 subs r3, #4 8002bb0: 0112 lsls r2, r2, #4 8002bb2: b2d2 uxtb r2, r2 8002bb4: 440b add r3, r1 8002bb6: 761a strb r2, [r3, #24] } 8002bb8: bf00 nop 8002bba: 370c adds r7, #12 8002bbc: 46bd mov sp, r7 8002bbe: bc80 pop {r7} 8002bc0: 4770 bx lr 8002bc2: bf00 nop 8002bc4: e000e100 .word 0xe000e100 8002bc8: e000ed00 .word 0xe000ed00 08002bcc : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002bcc: b480 push {r7} 8002bce: b089 sub sp, #36 @ 0x24 8002bd0: af00 add r7, sp, #0 8002bd2: 60f8 str r0, [r7, #12] 8002bd4: 60b9 str r1, [r7, #8] 8002bd6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002bd8: 68fb ldr r3, [r7, #12] 8002bda: f003 0307 and.w r3, r3, #7 8002bde: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002be0: 69fb ldr r3, [r7, #28] 8002be2: f1c3 0307 rsb r3, r3, #7 8002be6: 2b04 cmp r3, #4 8002be8: bf28 it cs 8002bea: 2304 movcs r3, #4 8002bec: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002bee: 69fb ldr r3, [r7, #28] 8002bf0: 3304 adds r3, #4 8002bf2: 2b06 cmp r3, #6 8002bf4: d902 bls.n 8002bfc 8002bf6: 69fb ldr r3, [r7, #28] 8002bf8: 3b03 subs r3, #3 8002bfa: e000 b.n 8002bfe 8002bfc: 2300 movs r3, #0 8002bfe: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002c00: f04f 32ff mov.w r2, #4294967295 8002c04: 69bb ldr r3, [r7, #24] 8002c06: fa02 f303 lsl.w r3, r2, r3 8002c0a: 43da mvns r2, r3 8002c0c: 68bb ldr r3, [r7, #8] 8002c0e: 401a ands r2, r3 8002c10: 697b ldr r3, [r7, #20] 8002c12: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002c14: f04f 31ff mov.w r1, #4294967295 8002c18: 697b ldr r3, [r7, #20] 8002c1a: fa01 f303 lsl.w r3, r1, r3 8002c1e: 43d9 mvns r1, r3 8002c20: 687b ldr r3, [r7, #4] 8002c22: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002c24: 4313 orrs r3, r2 ); } 8002c26: 4618 mov r0, r3 8002c28: 3724 adds r7, #36 @ 0x24 8002c2a: 46bd mov sp, r7 8002c2c: bc80 pop {r7} 8002c2e: 4770 bx lr 08002c30 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002c30: b580 push {r7, lr} 8002c32: b082 sub sp, #8 8002c34: af00 add r7, sp, #0 8002c36: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002c38: 687b ldr r3, [r7, #4] 8002c3a: 3b01 subs r3, #1 8002c3c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002c40: d301 bcc.n 8002c46 { return (1UL); /* Reload value impossible */ 8002c42: 2301 movs r3, #1 8002c44: e00f b.n 8002c66 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002c46: 4a0a ldr r2, [pc, #40] @ (8002c70 ) 8002c48: 687b ldr r3, [r7, #4] 8002c4a: 3b01 subs r3, #1 8002c4c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002c4e: 210f movs r1, #15 8002c50: f04f 30ff mov.w r0, #4294967295 8002c54: f7ff ff90 bl 8002b78 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002c58: 4b05 ldr r3, [pc, #20] @ (8002c70 ) 8002c5a: 2200 movs r2, #0 8002c5c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002c5e: 4b04 ldr r3, [pc, #16] @ (8002c70 ) 8002c60: 2207 movs r2, #7 8002c62: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002c64: 2300 movs r3, #0 } 8002c66: 4618 mov r0, r3 8002c68: 3708 adds r7, #8 8002c6a: 46bd mov sp, r7 8002c6c: bd80 pop {r7, pc} 8002c6e: bf00 nop 8002c70: e000e010 .word 0xe000e010 08002c74 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002c74: b580 push {r7, lr} 8002c76: b082 sub sp, #8 8002c78: af00 add r7, sp, #0 8002c7a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002c7c: 6878 ldr r0, [r7, #4] 8002c7e: f7ff ff2d bl 8002adc <__NVIC_SetPriorityGrouping> } 8002c82: bf00 nop 8002c84: 3708 adds r7, #8 8002c86: 46bd mov sp, r7 8002c88: bd80 pop {r7, pc} 08002c8a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002c8a: b580 push {r7, lr} 8002c8c: b086 sub sp, #24 8002c8e: af00 add r7, sp, #0 8002c90: 4603 mov r3, r0 8002c92: 60b9 str r1, [r7, #8] 8002c94: 607a str r2, [r7, #4] 8002c96: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8002c98: 2300 movs r3, #0 8002c9a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002c9c: f7ff ff42 bl 8002b24 <__NVIC_GetPriorityGrouping> 8002ca0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002ca2: 687a ldr r2, [r7, #4] 8002ca4: 68b9 ldr r1, [r7, #8] 8002ca6: 6978 ldr r0, [r7, #20] 8002ca8: f7ff ff90 bl 8002bcc 8002cac: 4602 mov r2, r0 8002cae: f997 300f ldrsb.w r3, [r7, #15] 8002cb2: 4611 mov r1, r2 8002cb4: 4618 mov r0, r3 8002cb6: f7ff ff5f bl 8002b78 <__NVIC_SetPriority> } 8002cba: bf00 nop 8002cbc: 3718 adds r7, #24 8002cbe: 46bd mov sp, r7 8002cc0: bd80 pop {r7, pc} 08002cc2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002cc2: b580 push {r7, lr} 8002cc4: b082 sub sp, #8 8002cc6: af00 add r7, sp, #0 8002cc8: 4603 mov r3, r0 8002cca: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002ccc: f997 3007 ldrsb.w r3, [r7, #7] 8002cd0: 4618 mov r0, r3 8002cd2: f7ff ff35 bl 8002b40 <__NVIC_EnableIRQ> } 8002cd6: bf00 nop 8002cd8: 3708 adds r7, #8 8002cda: 46bd mov sp, r7 8002cdc: bd80 pop {r7, pc} 08002cde : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002cde: b580 push {r7, lr} 8002ce0: b082 sub sp, #8 8002ce2: af00 add r7, sp, #0 8002ce4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002ce6: 6878 ldr r0, [r7, #4] 8002ce8: f7ff ffa2 bl 8002c30 8002cec: 4603 mov r3, r0 } 8002cee: 4618 mov r0, r3 8002cf0: 3708 adds r7, #8 8002cf2: 46bd mov sp, r7 8002cf4: bd80 pop {r7, pc} 08002cf6 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002cf6: b480 push {r7} 8002cf8: b085 sub sp, #20 8002cfa: af00 add r7, sp, #0 8002cfc: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002cfe: 2300 movs r3, #0 8002d00: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8002d02: 687b ldr r3, [r7, #4] 8002d04: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002d08: b2db uxtb r3, r3 8002d0a: 2b02 cmp r3, #2 8002d0c: d008 beq.n 8002d20 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 2204 movs r2, #4 8002d12: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d14: 687b ldr r3, [r7, #4] 8002d16: 2200 movs r2, #0 8002d18: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8002d1c: 2301 movs r3, #1 8002d1e: e020 b.n 8002d62 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002d20: 687b ldr r3, [r7, #4] 8002d22: 681b ldr r3, [r3, #0] 8002d24: 681a ldr r2, [r3, #0] 8002d26: 687b ldr r3, [r7, #4] 8002d28: 681b ldr r3, [r3, #0] 8002d2a: f022 020e bic.w r2, r2, #14 8002d2e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002d30: 687b ldr r3, [r7, #4] 8002d32: 681b ldr r3, [r3, #0] 8002d34: 681a ldr r2, [r3, #0] 8002d36: 687b ldr r3, [r7, #4] 8002d38: 681b ldr r3, [r3, #0] 8002d3a: f022 0201 bic.w r2, r2, #1 8002d3e: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002d40: 687b ldr r3, [r7, #4] 8002d42: 6c1a ldr r2, [r3, #64] @ 0x40 8002d44: 687b ldr r3, [r7, #4] 8002d46: 6bdb ldr r3, [r3, #60] @ 0x3c 8002d48: 2101 movs r1, #1 8002d4a: fa01 f202 lsl.w r2, r1, r2 8002d4e: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002d50: 687b ldr r3, [r7, #4] 8002d52: 2201 movs r2, #1 8002d54: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d58: 687b ldr r3, [r7, #4] 8002d5a: 2200 movs r2, #0 8002d5c: f883 2020 strb.w r2, [r3, #32] return status; 8002d60: 7bfb ldrb r3, [r7, #15] } 8002d62: 4618 mov r0, r3 8002d64: 3714 adds r7, #20 8002d66: 46bd mov sp, r7 8002d68: bc80 pop {r7} 8002d6a: 4770 bx lr 08002d6c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002d6c: b580 push {r7, lr} 8002d6e: b084 sub sp, #16 8002d70: af00 add r7, sp, #0 8002d72: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002d74: 2300 movs r3, #0 8002d76: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8002d78: 687b ldr r3, [r7, #4] 8002d7a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002d7e: b2db uxtb r3, r3 8002d80: 2b02 cmp r3, #2 8002d82: d005 beq.n 8002d90 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002d84: 687b ldr r3, [r7, #4] 8002d86: 2204 movs r2, #4 8002d88: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8002d8a: 2301 movs r3, #1 8002d8c: 73fb strb r3, [r7, #15] 8002d8e: e051 b.n 8002e34 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002d90: 687b ldr r3, [r7, #4] 8002d92: 681b ldr r3, [r3, #0] 8002d94: 681a ldr r2, [r3, #0] 8002d96: 687b ldr r3, [r7, #4] 8002d98: 681b ldr r3, [r3, #0] 8002d9a: f022 020e bic.w r2, r2, #14 8002d9e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002da0: 687b ldr r3, [r7, #4] 8002da2: 681b ldr r3, [r3, #0] 8002da4: 681a ldr r2, [r3, #0] 8002da6: 687b ldr r3, [r7, #4] 8002da8: 681b ldr r3, [r3, #0] 8002daa: f022 0201 bic.w r2, r2, #1 8002dae: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8002db0: 687b ldr r3, [r7, #4] 8002db2: 681b ldr r3, [r3, #0] 8002db4: 4a22 ldr r2, [pc, #136] @ (8002e40 ) 8002db6: 4293 cmp r3, r2 8002db8: d029 beq.n 8002e0e 8002dba: 687b ldr r3, [r7, #4] 8002dbc: 681b ldr r3, [r3, #0] 8002dbe: 4a21 ldr r2, [pc, #132] @ (8002e44 ) 8002dc0: 4293 cmp r3, r2 8002dc2: d022 beq.n 8002e0a 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 681b ldr r3, [r3, #0] 8002dc8: 4a1f ldr r2, [pc, #124] @ (8002e48 ) 8002dca: 4293 cmp r3, r2 8002dcc: d01a beq.n 8002e04 8002dce: 687b ldr r3, [r7, #4] 8002dd0: 681b ldr r3, [r3, #0] 8002dd2: 4a1e ldr r2, [pc, #120] @ (8002e4c ) 8002dd4: 4293 cmp r3, r2 8002dd6: d012 beq.n 8002dfe 8002dd8: 687b ldr r3, [r7, #4] 8002dda: 681b ldr r3, [r3, #0] 8002ddc: 4a1c ldr r2, [pc, #112] @ (8002e50 ) 8002dde: 4293 cmp r3, r2 8002de0: d00a beq.n 8002df8 8002de2: 687b ldr r3, [r7, #4] 8002de4: 681b ldr r3, [r3, #0] 8002de6: 4a1b ldr r2, [pc, #108] @ (8002e54 ) 8002de8: 4293 cmp r3, r2 8002dea: d102 bne.n 8002df2 8002dec: f44f 1380 mov.w r3, #1048576 @ 0x100000 8002df0: e00e b.n 8002e10 8002df2: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8002df6: e00b b.n 8002e10 8002df8: f44f 3380 mov.w r3, #65536 @ 0x10000 8002dfc: e008 b.n 8002e10 8002dfe: f44f 5380 mov.w r3, #4096 @ 0x1000 8002e02: e005 b.n 8002e10 8002e04: f44f 7380 mov.w r3, #256 @ 0x100 8002e08: e002 b.n 8002e10 8002e0a: 2310 movs r3, #16 8002e0c: e000 b.n 8002e10 8002e0e: 2301 movs r3, #1 8002e10: 4a11 ldr r2, [pc, #68] @ (8002e58 ) 8002e12: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002e14: 687b ldr r3, [r7, #4] 8002e16: 2201 movs r2, #1 8002e18: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002e1c: 687b ldr r3, [r7, #4] 8002e1e: 2200 movs r2, #0 8002e20: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002e24: 687b ldr r3, [r7, #4] 8002e26: 6b5b ldr r3, [r3, #52] @ 0x34 8002e28: 2b00 cmp r3, #0 8002e2a: d003 beq.n 8002e34 { hdma->XferAbortCallback(hdma); 8002e2c: 687b ldr r3, [r7, #4] 8002e2e: 6b5b ldr r3, [r3, #52] @ 0x34 8002e30: 6878 ldr r0, [r7, #4] 8002e32: 4798 blx r3 } } return status; 8002e34: 7bfb ldrb r3, [r7, #15] } 8002e36: 4618 mov r0, r3 8002e38: 3710 adds r7, #16 8002e3a: 46bd mov sp, r7 8002e3c: bd80 pop {r7, pc} 8002e3e: bf00 nop 8002e40: 40020008 .word 0x40020008 8002e44: 4002001c .word 0x4002001c 8002e48: 40020030 .word 0x40020030 8002e4c: 40020044 .word 0x40020044 8002e50: 40020058 .word 0x40020058 8002e54: 4002006c .word 0x4002006c 8002e58: 40020000 .word 0x40020000 08002e5c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002e5c: b480 push {r7} 8002e5e: b08b sub sp, #44 @ 0x2c 8002e60: af00 add r7, sp, #0 8002e62: 6078 str r0, [r7, #4] 8002e64: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8002e66: 2300 movs r3, #0 8002e68: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8002e6a: 2300 movs r3, #0 8002e6c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8002e6e: e169 b.n 8003144 { /* Get the IO position */ ioposition = (0x01uL << position); 8002e70: 2201 movs r2, #1 8002e72: 6a7b ldr r3, [r7, #36] @ 0x24 8002e74: fa02 f303 lsl.w r3, r2, r3 8002e78: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002e7a: 683b ldr r3, [r7, #0] 8002e7c: 681b ldr r3, [r3, #0] 8002e7e: 69fa ldr r2, [r7, #28] 8002e80: 4013 ands r3, r2 8002e82: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8002e84: 69ba ldr r2, [r7, #24] 8002e86: 69fb ldr r3, [r7, #28] 8002e88: 429a cmp r2, r3 8002e8a: f040 8158 bne.w 800313e { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8002e8e: 683b ldr r3, [r7, #0] 8002e90: 685b ldr r3, [r3, #4] 8002e92: 4a9a ldr r2, [pc, #616] @ (80030fc ) 8002e94: 4293 cmp r3, r2 8002e96: d05e beq.n 8002f56 8002e98: 4a98 ldr r2, [pc, #608] @ (80030fc