: /** * @brief The application entry point. * @retval int */ int main(void) { 80025ac: b590 push {r4, r7, lr} 80025ae: b095 sub sp, #84 @ 0x54 80025b0: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ uint8_t tempString[15] = {0}; 80025b2: 1d3b adds r3, r7, #4 80025b4: 2200 movs r2, #0 80025b6: 601a str r2, [r3, #0] 80025b8: 605a str r2, [r3, #4] 80025ba: 609a str r2, [r3, #8] 80025bc: f8c3 200b str.w r2, [r3, #11] uint8_t averages = 0; 80025c0: 2300 movs r3, #0 80025c2: f887 3047 strb.w r3, [r7, #71] @ 0x47 uint8_t newline = '\n'; 80025c6: 230a movs r3, #10 80025c8: 70fb strb r3, [r7, #3] // Variables for timing uint32_t previous_millis_green = 0; 80025ca: 2300 movs r3, #0 80025cc: 643b str r3, [r7, #64] @ 0x40 uint32_t previous_millis_red = 0; 80025ce: 2300 movs r3, #0 80025d0: 63bb str r3, [r7, #56] @ 0x38 uint32_t current_millis; float reference_resistor_100R = 0, reference_resistor_1K = 0, temperature_RTD = 0, thermal_compensaded_EC = 0; 80025d2: f04f 0300 mov.w r3, #0 80025d6: 637b str r3, [r7, #52] @ 0x34 80025d8: f04f 0300 mov.w r3, #0 80025dc: 633b str r3, [r7, #48] @ 0x30 80025de: f04f 0300 mov.w r3, #0 80025e2: 63fb str r3, [r7, #60] @ 0x3c 80025e4: f04f 0300 mov.w r3, #0 80025e8: 62fb str r3, [r7, #44] @ 0x2c float mag_rtd_reference = 0, mag_ec_reference = 0, mag_rtd = 0, mag_ec = 0; 80025ea: f04f 0300 mov.w r3, #0 80025ee: 62bb str r3, [r7, #40] @ 0x28 80025f0: f04f 0300 mov.w r3, #0 80025f4: 627b str r3, [r7, #36] @ 0x24 80025f6: f04f 0300 mov.w r3, #0 80025fa: 623b str r3, [r7, #32] 80025fc: f04f 0300 mov.w r3, #0 8002600: 61fb str r3, [r7, #28] /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8002602: f000 fde5 bl 80031d0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8002606: f000 f911 bl 800282c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800260a: f7ff fe67 bl 80022dc MX_ADC1_Init(); 800260e: f7ff fa53 bl 8001ab8 MX_ADC2_Init(); 8002612: f7ff fa8f bl 8001b34 MX_I2C1_Init(); 8002616: f7ff ff01 bl 800241c MX_I2C2_Init(); 800261a: f7ff ff2d bl 8002478 MX_USART1_UART_Init(); 800261e: f000 fd33 bl 8003088 MX_TIM3_Init(); 8002622: f000 fcbd bl 8002fa0 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim3); 8002626: 4873 ldr r0, [pc, #460] @ (80027f4 ) 8002628: f003 f942 bl 80058b0 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off 800262c: 2201 movs r2, #1 800262e: 2110 movs r1, #16 8002630: 4871 ldr r0, [pc, #452] @ (80027f8 ) 8002632: f001 fbc0 bl 8003db6 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off 8002636: 2201 movs r2, #1 8002638: 2120 movs r1, #32 800263a: 486f ldr r0, [pc, #444] @ (80027f8 ) 800263c: f001 fbbb bl 8003db6 digital_outputs_init(); 8002640: f7ff fdb4 bl 80021ac rs485_init(); 8002644: f000 fb4c bl 8002ce0 ADG715_ResetChannels(); 8002648: f7ff fa18 bl 8001a7c ADS1015_Init(); // Initializes pH Measurement 800264c: f7ff fb62 bl 8001d14 AD5934_Init(); // Initializes CE and RTD Measurement 8002650: f7fe fc9e bl 8000f90 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while(averages<50) 8002654: e017 b.n 8002686 { AD5934_Process_System(); 8002656: f7fe fee1 bl 800141c ADS1015_Process_System(); 800265a: f7ff fbb9 bl 8001dd0 current_millis = g_ms_counter; 800265e: 4b67 ldr r3, [pc, #412] @ (80027fc ) 8002660: 681b ldr r3, [r3, #0] 8002662: 61bb str r3, [r7, #24] if((current_millis % 20) == 0) // Send data each 40ms 8002664: 69b9 ldr r1, [r7, #24] 8002666: 4b66 ldr r3, [pc, #408] @ (8002800 ) 8002668: fba3 2301 umull r2, r3, r3, r1 800266c: 091a lsrs r2, r3, #4 800266e: 4613 mov r3, r2 8002670: 009b lsls r3, r3, #2 8002672: 4413 add r3, r2 8002674: 009b lsls r3, r3, #2 8002676: 1aca subs r2, r1, r3 8002678: 2a00 cmp r2, #0 800267a: d104 bne.n 8002686 { averages++; 800267c: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8002680: 3301 adds r3, #1 8002682: f887 3047 strb.w r3, [r7, #71] @ 0x47 while(averages<50) 8002686: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800268a: 2b31 cmp r3, #49 @ 0x31 800268c: d9e3 bls.n 8002656 } } digital_outputs_toggle(0); 800268e: 2000 movs r0, #0 8002690: f7ff fe06 bl 80022a0 while (1) { AD5934_Process_System(); 8002694: f7fe fec2 bl 800141c ADS1015_Process_System(); 8002698: f7ff fb9a bl 8001dd0 current_millis = g_ms_counter; 800269c: 4b57 ldr r3, [pc, #348] @ (80027fc ) 800269e: 681b ldr r3, [r3, #0] 80026a0: 61bb str r3, [r7, #24] if((current_millis % 500) == 0) // Send data each 100ms 80026a2: 69ba ldr r2, [r7, #24] 80026a4: 4b57 ldr r3, [pc, #348] @ (8002804 ) 80026a6: fba3 1302 umull r1, r3, r3, r2 80026aa: 095b lsrs r3, r3, #5 80026ac: f44f 71fa mov.w r1, #500 @ 0x1f4 80026b0: fb01 f303 mul.w r3, r1, r3 80026b4: 1ad3 subs r3, r2, r3 80026b6: 2b00 cmp r3, #0 80026b8: f040 808d bne.w 80027d6 { if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C 80026bc: 4b52 ldr r3, [pc, #328] @ (8002808 ) 80026be: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 80026c2: 2b00 cmp r3, #0 80026c4: d022 beq.n 800270c { temperature_RTD = AD5934_Calculate_Temperature(g_ref_100R_LowGain_filter.filtered_value, g_ref_1K_MidGain_filter.filtered_value, g_rtd_filter.filtered_value);// AD5934_GetImpedance(mag_reference,mag_rtd);// 80026c6: 4b51 ldr r3, [pc, #324] @ (800280c ) 80026c8: 6d5b ldr r3, [r3, #84] @ 0x54 80026ca: 4a51 ldr r2, [pc, #324] @ (8002810 ) 80026cc: 6d51 ldr r1, [r2, #84] @ 0x54 80026ce: 4a4e ldr r2, [pc, #312] @ (8002808 ) 80026d0: 6d52 ldr r2, [r2, #84] @ 0x54 80026d2: 4618 mov r0, r3 80026d4: f7fe fca8 bl 8001028 80026d8: 63f8 str r0, [r7, #60] @ 0x3c //uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, current_rtd_mux); //uint16_t rtd_final = AD5934_Compress_To_IntScale(temperature_RTD, current_rtd_mux); //intToStr(rtd_final, tempString); FloatToString(tempString, temperature_RTD); 80026da: 6bf8 ldr r0, [r7, #60] @ 0x3c 80026dc: f7fd ffcc bl 8000678 <__aeabi_f2d> 80026e0: 4602 mov r2, r0 80026e2: 460b mov r3, r1 80026e4: 1d39 adds r1, r7, #4 80026e6: 4608 mov r0, r1 80026e8: f000 f8f0 bl 80028cc rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 80026ec: 1d3b adds r3, r7, #4 80026ee: 4618 mov r0, r3 80026f0: f7fd fd2c bl 800014c 80026f4: 4603 mov r3, r0 80026f6: b29a uxth r2, r3 80026f8: 1d3b adds r3, r7, #4 80026fa: 4611 mov r1, r2 80026fc: 4618 mov r0, r3 80026fe: f000 fb1b bl 8002d38 rs485_send_broadcast(&newline, 1); 8002702: 1cfb adds r3, r7, #3 8002704: 2101 movs r1, #1 8002706: 4618 mov r0, r3 8002708: f000 fb16 bl 8002d38 } if (g_ec_filter.value_valid) // EC 800270c: 4b41 ldr r3, [pc, #260] @ (8002814 ) 800270e: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002712: 2b00 cmp r3, #0 8002714: d032 beq.n 800277c { mag_ec = AD5934_GetAdmittance(g_ref_100R_MidGain_filter.filtered_value, g_ref_1K_MidGain_filter.filtered_value, g_ref_1K_HighGain_filter.filtered_value, g_ref_10K_HighGain_filter.filtered_value, g_ec_filter.filtered_value); 8002716: 4b40 ldr r3, [pc, #256] @ (8002818 ) 8002718: 6d58 ldr r0, [r3, #84] @ 0x54 800271a: 4b3d ldr r3, [pc, #244] @ (8002810 ) 800271c: 6d59 ldr r1, [r3, #84] @ 0x54 800271e: 4b3f ldr r3, [pc, #252] @ (800281c ) 8002720: 6d5a ldr r2, [r3, #84] @ 0x54 8002722: 4b3f ldr r3, [pc, #252] @ (8002820 ) 8002724: 6d5c ldr r4, [r3, #84] @ 0x54 8002726: 4b3b ldr r3, [pc, #236] @ (8002814 ) 8002728: 6d5b ldr r3, [r3, #84] @ 0x54 800272a: 9300 str r3, [sp, #0] 800272c: 4623 mov r3, r4 800272e: f7fe fd39 bl 80011a4 8002732: 61f8 str r0, [r7, #28] thermal_compensaded_EC = AD5934_EC_Compensate_Magnitude_To_25C(mag_ec, temperature_RTD); 8002734: 6bf9 ldr r1, [r7, #60] @ 0x3c 8002736: 69f8 ldr r0, [r7, #28] 8002738: f7fe fd06 bl 8001148 800273c: 62f8 str r0, [r7, #44] @ 0x2c //FloatToString(tempString, thermal_compensaded_EC); //rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); //rs485_send_broadcast(&newline, 1); uint16_t ec_final = AD5934_Compress_To_IntScale(thermal_compensaded_EC, current_ec_mux); 800273e: 4b39 ldr r3, [pc, #228] @ (8002824 ) 8002740: 781b ldrb r3, [r3, #0] 8002742: 4619 mov r1, r3 8002744: 6af8 ldr r0, [r7, #44] @ 0x2c 8002746: f7fe fdad bl 80012a4 800274a: 4603 mov r3, r0 800274c: 82fb strh r3, [r7, #22] intToStr(ec_final, tempString); 800274e: f9b7 3016 ldrsh.w r3, [r7, #22] 8002752: 1d3a adds r2, r7, #4 8002754: 4611 mov r1, r2 8002756: 4618 mov r0, r3 8002758: f000 f9cc bl 8002af4 rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 800275c: 1d3b adds r3, r7, #4 800275e: 4618 mov r0, r3 8002760: f7fd fcf4 bl 800014c 8002764: 4603 mov r3, r0 8002766: b29a uxth r2, r3 8002768: 1d3b adds r3, r7, #4 800276a: 4611 mov r1, r2 800276c: 4618 mov r0, r3 800276e: f000 fae3 bl 8002d38 rs485_send_broadcast(&newline, 1); 8002772: 1cfb adds r3, r7, #3 8002774: 2101 movs r1, #1 8002776: 4618 mov r0, r3 8002778: f000 fade bl 8002d38 } if (g_ph_filter.value_valid) // pH 800277c: 4b2a ldr r3, [pc, #168] @ (8002828 ) 800277e: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002782: 2b00 cmp r3, #0 8002784: d022 beq.n 80027cc { uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value); 8002786: 4b28 ldr r3, [pc, #160] @ (8002828 ) 8002788: 6d5b ldr r3, [r3, #84] @ 0x54 800278a: 4618 mov r0, r3 800278c: f7ff fadc bl 8001d48 8002790: 4603 mov r3, r0 8002792: 82bb strh r3, [r7, #20] intToStr(ph_final, tempString); 8002794: f9b7 3014 ldrsh.w r3, [r7, #20] 8002798: 1d3a adds r2, r7, #4 800279a: 4611 mov r1, r2 800279c: 4618 mov r0, r3 800279e: f000 f9a9 bl 8002af4 //float ph_final = g_ph_filter.filtered_value; //FloatToString(tempString, ph_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 80027a2: 1d3b adds r3, r7, #4 80027a4: 4618 mov r0, r3 80027a6: f7fd fcd1 bl 800014c 80027aa: 4603 mov r3, r0 80027ac: b29a uxth r2, r3 80027ae: 1d3b adds r3, r7, #4 80027b0: 4611 mov r1, r2 80027b2: 4618 mov r0, r3 80027b4: f000 fac0 bl 8002d38 rs485_send_broadcast(&newline, 1); 80027b8: 1cfb adds r3, r7, #3 80027ba: 2101 movs r1, #1 80027bc: 4618 mov r0, r3 80027be: f000 fabb bl 8002d38 rs485_send_broadcast(&newline, 1); 80027c2: 1cfb adds r3, r7, #3 80027c4: 2101 movs r1, #1 80027c6: 4618 mov r0, r3 80027c8: f000 fab6 bl 8002d38 } rs485_send_broadcast(&newline, 1); 80027cc: 1cfb adds r3, r7, #3 80027ce: 2101 movs r1, #1 80027d0: 4618 mov r0, r3 80027d2: f000 fab1 bl 8002d38 } // Piscar LED verde em PB4 a cada 1 segundo if ((current_millis - previous_millis_green) >= 1000) 80027d6: 69ba ldr r2, [r7, #24] 80027d8: 6c3b ldr r3, [r7, #64] @ 0x40 80027da: 1ad3 subs r3, r2, r3 80027dc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80027e0: f4ff af58 bcc.w 8002694 { previous_millis_green = current_millis; 80027e4: 69bb ldr r3, [r7, #24] 80027e6: 643b str r3, [r7, #64] @ 0x40 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4); 80027e8: 2110 movs r1, #16 80027ea: 4803 ldr r0, [pc, #12] @ (80027f8 ) 80027ec: f001 fafb bl 8003de6 AD5934_Process_System(); 80027f0: e750 b.n 8002694 80027f2: bf00 nop 80027f4: 200004e4 .word 0x200004e4 80027f8: 40010c00 .word 0x40010c00 80027fc: 20000084 .word 0x20000084 8002800: cccccccd .word 0xcccccccd 8002804: 10624dd3 .word 0x10624dd3 8002808: 2000008c .word 0x2000008c 800280c: 20000144 .word 0x20000144 8002810: 200001fc .word 0x200001fc 8002814: 200000e8 .word 0x200000e8 8002818: 200001a0 .word 0x200001a0 800281c: 20000258 .word 0x20000258 8002820: 200002b4 .word 0x200002b4 8002824: 20000000 .word 0x20000000 8002828: 20000380 .word 0x20000380 0800282c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800282c: b580 push {r7, lr} 800282e: b094 sub sp, #80 @ 0x50 8002830: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8002832: f107 0328 add.w r3, r7, #40 @ 0x28 8002836: 2228 movs r2, #40 @ 0x28 8002838: 2100 movs r1, #0 800283a: 4618 mov r0, r3 800283c: f004 f9f0 bl 8006c20 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8002840: f107 0314 add.w r3, r7, #20 8002844: 2200 movs r2, #0 8002846: 601a str r2, [r3, #0] 8002848: 605a str r2, [r3, #4] 800284a: 609a str r2, [r3, #8] 800284c: 60da str r2, [r3, #12] 800284e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8002850: 1d3b adds r3, r7, #4 8002852: 2200 movs r2, #0 8002854: 601a str r2, [r3, #0] 8002856: 605a str r2, [r3, #4] 8002858: 609a str r2, [r3, #8] 800285a: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800285c: 2301 movs r3, #1 800285e: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8002860: f44f 3380 mov.w r3, #65536 @ 0x10000 8002864: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8002866: 2300 movs r3, #0 8002868: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800286a: f107 0328 add.w r3, r7, #40 @ 0x28 800286e: 4618 mov r0, r3 8002870: f002 fb06 bl 8004e80 8002874: 4603 mov r3, r0 8002876: 2b00 cmp r3, #0 8002878: d001 beq.n 800287e { Error_Handler(); 800287a: f000 fa1f bl 8002cbc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800287e: 230f movs r3, #15 8002880: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8002882: 2301 movs r3, #1 8002884: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8002886: 2300 movs r3, #0 8002888: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800288a: 2300 movs r3, #0 800288c: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800288e: 2300 movs r3, #0 8002890: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8002892: f107 0314 add.w r3, r7, #20 8002896: 2100 movs r1, #0 8002898: 4618 mov r0, r3 800289a: f002 fd73 bl 8005384 800289e: 4603 mov r3, r0 80028a0: 2b00 cmp r3, #0 80028a2: d001 beq.n 80028a8 { Error_Handler(); 80028a4: f000 fa0a bl 8002cbc } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80028a8: 2302 movs r3, #2 80028aa: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 80028ac: f44f 4340 mov.w r3, #49152 @ 0xc000 80028b0: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80028b2: 1d3b adds r3, r7, #4 80028b4: 4618 mov r0, r3 80028b6: f002 fef5 bl 80056a4 80028ba: 4603 mov r3, r0 80028bc: 2b00 cmp r3, #0 80028be: d001 beq.n 80028c4 { Error_Handler(); 80028c0: f000 f9fc bl 8002cbc } } 80028c4: bf00 nop 80028c6: 3750 adds r7, #80 @ 0x50 80028c8: 46bd mov sp, r7 80028ca: bd80 pop {r7, pc} 080028cc : * @param val - value to be converted * * @return None. *******************************************************************************/ void FloatToString(uint8_t *buf, double val) { 80028cc: b5b0 push {r4, r5, r7, lr} 80028ce: b096 sub sp, #88 @ 0x58 80028d0: af00 add r7, sp, #0 80028d2: 60f8 str r0, [r7, #12] 80028d4: e9c7 2300 strd r2, r3, [r7] char temp[20]; // Buffer auxiliar para construção segura int i = 0; 80028d8: 2300 movs r3, #0 80028da: 657b str r3, [r7, #84] @ 0x54 // 1. Tratar sinal negativo if (val < 0) { 80028dc: f04f 0200 mov.w r2, #0 80028e0: f04f 0300 mov.w r3, #0 80028e4: e9d7 0100 ldrd r0, r1, [r7] 80028e8: f7fd ff7e bl 80007e8 <__aeabi_dcmplt> 80028ec: 4603 mov r3, r0 80028ee: 2b00 cmp r3, #0 80028f0: d00d beq.n 800290e temp[i++] = '-'; 80028f2: 6d7b ldr r3, [r7, #84] @ 0x54 80028f4: 1c5a adds r2, r3, #1 80028f6: 657a str r2, [r7, #84] @ 0x54 80028f8: 3358 adds r3, #88 @ 0x58 80028fa: 443b add r3, r7 80028fc: 222d movs r2, #45 @ 0x2d 80028fe: f803 2c30 strb.w r2, [r3, #-48] val = -val; 8002902: 683c ldr r4, [r7, #0] 8002904: 687b ldr r3, [r7, #4] 8002906: f083 4500 eor.w r5, r3, #2147483648 @ 0x80000000 800290a: e9c7 4500 strd r4, r5, [r7] } // 2. Separar parte inteira e fracionária long intPart = (long)val; 800290e: e9d7 0100 ldrd r0, r1, [r7] 8002912: f7fd ff91 bl 8000838 <__aeabi_d2iz> 8002916: 4603 mov r3, r0 8002918: 653b str r3, [r7, #80] @ 0x50 // Multiplicamos por 1000 para obter 3 casas decimais fixas int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5); 800291a: 6d38 ldr r0, [r7, #80] @ 0x50 800291c: f7fd fe9a bl 8000654 <__aeabi_i2d> 8002920: 4602 mov r2, r0 8002922: 460b mov r3, r1 8002924: e9d7 0100 ldrd r0, r1, [r7] 8002928: f7fd fd46 bl 80003b8 <__aeabi_dsub> 800292c: 4602 mov r2, r0 800292e: 460b mov r3, r1 8002930: 4610 mov r0, r2 8002932: 4619 mov r1, r3 8002934: f04f 0200 mov.w r2, #0 8002938: 4b6a ldr r3, [pc, #424] @ (8002ae4 ) 800293a: f7fd fc0f bl 800015c <__aeabi_dmul> 800293e: 4602 mov r2, r0 8002940: 460b mov r3, r1 8002942: 4610 mov r0, r2 8002944: 4619 mov r1, r3 8002946: f04f 0200 mov.w r2, #0 800294a: 4b67 ldr r3, [pc, #412] @ (8002ae8 ) 800294c: f7fd fd36 bl 80003bc <__adddf3> 8002950: 4602 mov r2, r0 8002952: 460b mov r3, r1 8002954: 4610 mov r0, r2 8002956: 4619 mov r1, r3 8002958: f7fd ff6e bl 8000838 <__aeabi_d2iz> 800295c: 4603 mov r3, r0 800295e: 63fb str r3, [r7, #60] @ 0x3c // 3. Converter a parte inteira para o buffer temp // Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro char intRev[12]; int j = 0; 8002960: 2300 movs r3, #0 8002962: 64fb str r3, [r7, #76] @ 0x4c if (intPart == 0) { 8002964: 6d3b ldr r3, [r7, #80] @ 0x50 8002966: 2b00 cmp r3, #0 8002968: d126 bne.n 80029b8 intRev[j++] = '0'; 800296a: 6cfb ldr r3, [r7, #76] @ 0x4c 800296c: 1c5a adds r2, r3, #1 800296e: 64fa str r2, [r7, #76] @ 0x4c 8002970: 3358 adds r3, #88 @ 0x58 8002972: 443b add r3, r7 8002974: 2230 movs r2, #48 @ 0x30 8002976: f803 2c3c strb.w r2, [r3, #-60] 800297a: e020 b.n 80029be } else { while (intPart > 0) { intRev[j++] = (intPart % 10) + '0'; 800297c: 6d3a ldr r2, [r7, #80] @ 0x50 800297e: 4b5b ldr r3, [pc, #364] @ (8002aec ) 8002980: fb83 1302 smull r1, r3, r3, r2 8002984: 1099 asrs r1, r3, #2 8002986: 17d3 asrs r3, r2, #31 8002988: 1ac9 subs r1, r1, r3 800298a: 460b mov r3, r1 800298c: 009b lsls r3, r3, #2 800298e: 440b add r3, r1 8002990: 005b lsls r3, r3, #1 8002992: 1ad1 subs r1, r2, r3 8002994: b2ca uxtb r2, r1 8002996: 6cfb ldr r3, [r7, #76] @ 0x4c 8002998: 1c59 adds r1, r3, #1 800299a: 64f9 str r1, [r7, #76] @ 0x4c 800299c: 3230 adds r2, #48 @ 0x30 800299e: b2d2 uxtb r2, r2 80029a0: 3358 adds r3, #88 @ 0x58 80029a2: 443b add r3, r7 80029a4: f803 2c3c strb.w r2, [r3, #-60] intPart /= 10; 80029a8: 6d3b ldr r3, [r7, #80] @ 0x50 80029aa: 4a50 ldr r2, [pc, #320] @ (8002aec ) 80029ac: fb82 1203 smull r1, r2, r2, r3 80029b0: 1092 asrs r2, r2, #2 80029b2: 17db asrs r3, r3, #31 80029b4: 1ad3 subs r3, r2, r3 80029b6: 653b str r3, [r7, #80] @ 0x50 while (intPart > 0) { 80029b8: 6d3b ldr r3, [r7, #80] @ 0x50 80029ba: 2b00 cmp r3, #0 80029bc: dcde bgt.n 800297c } } // Inverter a parte inteira de volta para o buffer principal for (int k = j - 1; k >= 0; k--) { 80029be: 6cfb ldr r3, [r7, #76] @ 0x4c 80029c0: 3b01 subs r3, #1 80029c2: 64bb str r3, [r7, #72] @ 0x48 80029c4: e00e b.n 80029e4 temp[i++] = intRev[k]; 80029c6: 6d7b ldr r3, [r7, #84] @ 0x54 80029c8: 1c5a adds r2, r3, #1 80029ca: 657a str r2, [r7, #84] @ 0x54 80029cc: f107 011c add.w r1, r7, #28 80029d0: 6cba ldr r2, [r7, #72] @ 0x48 80029d2: 440a add r2, r1 80029d4: 7812 ldrb r2, [r2, #0] 80029d6: 3358 adds r3, #88 @ 0x58 80029d8: 443b add r3, r7 80029da: f803 2c30 strb.w r2, [r3, #-48] for (int k = j - 1; k >= 0; k--) { 80029de: 6cbb ldr r3, [r7, #72] @ 0x48 80029e0: 3b01 subs r3, #1 80029e2: 64bb str r3, [r7, #72] @ 0x48 80029e4: 6cbb ldr r3, [r7, #72] @ 0x48 80029e6: 2b00 cmp r3, #0 80029e8: daed bge.n 80029c6 } // 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas) temp[i++] = '.'; 80029ea: 6d7b ldr r3, [r7, #84] @ 0x54 80029ec: 1c5a adds r2, r3, #1 80029ee: 657a str r2, [r7, #84] @ 0x54 80029f0: 3358 adds r3, #88 @ 0x58 80029f2: 443b add r3, r7 80029f4: 222e movs r2, #46 @ 0x2e 80029f6: f803 2c30 strb.w r2, [r3, #-48] // Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5) int fracBuffer[3]; fracBuffer[2] = fracPart % 10; // Unidade 80029fa: 6bf9 ldr r1, [r7, #60] @ 0x3c 80029fc: 4b3b ldr r3, [pc, #236] @ (8002aec ) 80029fe: fb83 2301 smull r2, r3, r3, r1 8002a02: 109a asrs r2, r3, #2 8002a04: 17cb asrs r3, r1, #31 8002a06: 1ad2 subs r2, r2, r3 8002a08: 4613 mov r3, r2 8002a0a: 009b lsls r3, r3, #2 8002a0c: 4413 add r3, r2 8002a0e: 005b lsls r3, r3, #1 8002a10: 1aca subs r2, r1, r3 8002a12: 61ba str r2, [r7, #24] fracBuffer[1] = (fracPart / 10) % 10; // Dezena 8002a14: 6bfb ldr r3, [r7, #60] @ 0x3c 8002a16: 4a35 ldr r2, [pc, #212] @ (8002aec ) 8002a18: fb82 1203 smull r1, r2, r2, r3 8002a1c: 1092 asrs r2, r2, #2 8002a1e: 17db asrs r3, r3, #31 8002a20: 1ad1 subs r1, r2, r3 8002a22: 4b32 ldr r3, [pc, #200] @ (8002aec ) 8002a24: fb83 2301 smull r2, r3, r3, r1 8002a28: 109a asrs r2, r3, #2 8002a2a: 17cb asrs r3, r1, #31 8002a2c: 1ad2 subs r2, r2, r3 8002a2e: 4613 mov r3, r2 8002a30: 009b lsls r3, r3, #2 8002a32: 4413 add r3, r2 8002a34: 005b lsls r3, r3, #1 8002a36: 1aca subs r2, r1, r3 8002a38: 617a str r2, [r7, #20] fracBuffer[0] = (fracPart / 100) % 10; // Centena 8002a3a: 6bfb ldr r3, [r7, #60] @ 0x3c 8002a3c: 4a2c ldr r2, [pc, #176] @ (8002af0 ) 8002a3e: fb82 1203 smull r1, r2, r2, r3 8002a42: 1152 asrs r2, r2, #5 8002a44: 17db asrs r3, r3, #31 8002a46: 1ad1 subs r1, r2, r3 8002a48: 4b28 ldr r3, [pc, #160] @ (8002aec ) 8002a4a: fb83 2301 smull r2, r3, r3, r1 8002a4e: 109a asrs r2, r3, #2 8002a50: 17cb asrs r3, r1, #31 8002a52: 1ad2 subs r2, r2, r3 8002a54: 4613 mov r3, r2 8002a56: 009b lsls r3, r3, #2 8002a58: 4413 add r3, r2 8002a5a: 005b lsls r3, r3, #1 8002a5c: 1aca subs r2, r1, r3 8002a5e: 613a str r2, [r7, #16] for (int k = 0; k <= 2; k++) { 8002a60: 2300 movs r3, #0 8002a62: 647b str r3, [r7, #68] @ 0x44 8002a64: e012 b.n 8002a8c temp[i++] = fracBuffer[k] + '0'; 8002a66: 6c7b ldr r3, [r7, #68] @ 0x44 8002a68: 009b lsls r3, r3, #2 8002a6a: 3358 adds r3, #88 @ 0x58 8002a6c: 443b add r3, r7 8002a6e: f853 3c48 ldr.w r3, [r3, #-72] 8002a72: b2da uxtb r2, r3 8002a74: 6d7b ldr r3, [r7, #84] @ 0x54 8002a76: 1c59 adds r1, r3, #1 8002a78: 6579 str r1, [r7, #84] @ 0x54 8002a7a: 3230 adds r2, #48 @ 0x30 8002a7c: b2d2 uxtb r2, r2 8002a7e: 3358 adds r3, #88 @ 0x58 8002a80: 443b add r3, r7 8002a82: f803 2c30 strb.w r2, [r3, #-48] for (int k = 0; k <= 2; k++) { 8002a86: 6c7b ldr r3, [r7, #68] @ 0x44 8002a88: 3301 adds r3, #1 8002a8a: 647b str r3, [r7, #68] @ 0x44 8002a8c: 6c7b ldr r3, [r7, #68] @ 0x44 8002a8e: 2b02 cmp r3, #2 8002a90: dde9 ble.n 8002a66 } // 5. Finalizar a string com o caractere nulo temp[i] = '\0'; 8002a92: f107 0228 add.w r2, r7, #40 @ 0x28 8002a96: 6d7b ldr r3, [r7, #84] @ 0x54 8002a98: 4413 add r3, r2 8002a9a: 2200 movs r2, #0 8002a9c: 701a strb r2, [r3, #0] // 6. Copiar para o buffer de destino final (sem risco de lixo) int destIdx = 0; 8002a9e: 2300 movs r3, #0 8002aa0: 643b str r3, [r7, #64] @ 0x40 while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança 8002aa2: e00b b.n 8002abc buf[destIdx] = temp[destIdx]; 8002aa4: 6c3b ldr r3, [r7, #64] @ 0x40 8002aa6: 68fa ldr r2, [r7, #12] 8002aa8: 4413 add r3, r2 8002aaa: f107 0128 add.w r1, r7, #40 @ 0x28 8002aae: 6c3a ldr r2, [r7, #64] @ 0x40 8002ab0: 440a add r2, r1 8002ab2: 7812 ldrb r2, [r2, #0] 8002ab4: 701a strb r2, [r3, #0] destIdx++; 8002ab6: 6c3b ldr r3, [r7, #64] @ 0x40 8002ab8: 3301 adds r3, #1 8002aba: 643b str r3, [r7, #64] @ 0x40 while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança 8002abc: f107 0228 add.w r2, r7, #40 @ 0x28 8002ac0: 6c3b ldr r3, [r7, #64] @ 0x40 8002ac2: 4413 add r3, r2 8002ac4: 781b ldrb r3, [r3, #0] 8002ac6: 2b00 cmp r3, #0 8002ac8: d002 beq.n 8002ad0 8002aca: 6c3b ldr r3, [r7, #64] @ 0x40 8002acc: 2b0e cmp r3, #14 8002ace: dde9 ble.n 8002aa4 } buf[destIdx] = '\0'; 8002ad0: 6c3b ldr r3, [r7, #64] @ 0x40 8002ad2: 68fa ldr r2, [r7, #12] 8002ad4: 4413 add r3, r2 8002ad6: 2200 movs r2, #0 8002ad8: 701a strb r2, [r3, #0] } 8002ada: bf00 nop 8002adc: 3758 adds r7, #88 @ 0x58 8002ade: 46bd mov sp, r7 8002ae0: bdb0 pop {r4, r5, r7, pc} 8002ae2: bf00 nop 8002ae4: 408f4000 .word 0x408f4000 8002ae8: 3fe00000 .word 0x3fe00000 8002aec: 66666667 .word 0x66666667 8002af0: 51eb851f .word 0x51eb851f 08002af4 : void intToStr(int16_t N, uint8_t *str) { 8002af4: b480 push {r7} 8002af6: b087 sub sp, #28 8002af8: af00 add r7, sp, #0 8002afa: 4603 mov r3, r0 8002afc: 6039 str r1, [r7, #0] 8002afe: 80fb strh r3, [r7, #6] int16_t i = 0; 8002b00: 2300 movs r3, #0 8002b02: 82fb strh r3, [r7, #22] int16_t sign = N; 8002b04: 88fb ldrh r3, [r7, #6] 8002b06: 823b strh r3, [r7, #16] uint8_t max_len = 15; // Tamanho máximo do buffer 8002b08: 230f movs r3, #15 8002b0a: 73fb strb r3, [r7, #15] uint8_t width = 4; // mínimo 4 caracteres 8002b0c: 2304 movs r3, #4 8002b0e: 757b strb r3, [r7, #21] // Trata o caso do número zero isoladamente if (N == 0) 8002b10: f9b7 3006 ldrsh.w r3, [r7, #6] 8002b14: 2b00 cmp r3, #0 8002b16: d127 bne.n 8002b68 { // Preenche com zeros à esquerda até atingir a largura desejada while (width > 1 && i < (max_len - 1)) 8002b18: e00c b.n 8002b34 { str[i++] = '0'; 8002b1a: f9b7 2016 ldrsh.w r2, [r7, #22] 8002b1e: b293 uxth r3, r2 8002b20: 3301 adds r3, #1 8002b22: b29b uxth r3, r3 8002b24: 82fb strh r3, [r7, #22] 8002b26: 683b ldr r3, [r7, #0] 8002b28: 4413 add r3, r2 8002b2a: 2230 movs r2, #48 @ 0x30 8002b2c: 701a strb r2, [r3, #0] width--; 8002b2e: 7d7b ldrb r3, [r7, #21] 8002b30: 3b01 subs r3, #1 8002b32: 757b strb r3, [r7, #21] while (width > 1 && i < (max_len - 1)) 8002b34: 7d7b ldrb r3, [r7, #21] 8002b36: 2b01 cmp r3, #1 8002b38: d905 bls.n 8002b46 8002b3a: f9b7 2016 ldrsh.w r2, [r7, #22] 8002b3e: 7bfb ldrb r3, [r7, #15] 8002b40: 3b01 subs r3, #1 8002b42: 429a cmp r2, r3 8002b44: dbe9 blt.n 8002b1a } str[i++] = '0'; 8002b46: f9b7 2016 ldrsh.w r2, [r7, #22] 8002b4a: b293 uxth r3, r2 8002b4c: 3301 adds r3, #1 8002b4e: b29b uxth r3, r3 8002b50: 82fb strh r3, [r7, #22] 8002b52: 683b ldr r3, [r7, #0] 8002b54: 4413 add r3, r2 8002b56: 2230 movs r2, #48 @ 0x30 8002b58: 701a strb r2, [r3, #0] str[i] = '\0'; 8002b5a: f9b7 3016 ldrsh.w r3, [r7, #22] 8002b5e: 683a ldr r2, [r7, #0] 8002b60: 4413 add r3, r2 8002b62: 2200 movs r2, #0 8002b64: 701a strb r2, [r3, #0] return; 8002b66: e08a b.n 8002c7e } if (N < 0) 8002b68: f9b7 3006 ldrsh.w r3, [r7, #6] 8002b6c: 2b00 cmp r3, #0 8002b6e: da2d bge.n 8002bcc N = -N; 8002b70: 88fb ldrh r3, [r7, #6] 8002b72: 425b negs r3, r3 8002b74: b29b uxth r3, r3 8002b76: 80fb strh r3, [r7, #6] // Extração dos dígitos while (N > 0) 8002b78: e028 b.n 8002bcc { if (i >= (max_len - 1)) 8002b7a: f9b7 2016 ldrsh.w r2, [r7, #22] 8002b7e: 7bfb ldrb r3, [r7, #15] 8002b80: 3b01 subs r3, #1 8002b82: 429a cmp r2, r3 8002b84: da27 bge.n 8002bd6 break; // Proteção de estouro str[i++] = (N % 10) + '0'; 8002b86: f9b7 2006 ldrsh.w r2, [r7, #6] 8002b8a: 4b3f ldr r3, [pc, #252] @ (8002c88 ) 8002b8c: fb83 1302 smull r1, r3, r3, r2 8002b90: 1099 asrs r1, r3, #2 8002b92: 17d3 asrs r3, r2, #31 8002b94: 1ac9 subs r1, r1, r3 8002b96: 460b mov r3, r1 8002b98: 009b lsls r3, r3, #2 8002b9a: 440b add r3, r1 8002b9c: 005b lsls r3, r3, #1 8002b9e: 1ad3 subs r3, r2, r3 8002ba0: b21b sxth r3, r3 8002ba2: b2da uxtb r2, r3 8002ba4: f9b7 1016 ldrsh.w r1, [r7, #22] 8002ba8: b28b uxth r3, r1 8002baa: 3301 adds r3, #1 8002bac: b29b uxth r3, r3 8002bae: 82fb strh r3, [r7, #22] 8002bb0: 683b ldr r3, [r7, #0] 8002bb2: 440b add r3, r1 8002bb4: 3230 adds r2, #48 @ 0x30 8002bb6: b2d2 uxtb r2, r2 8002bb8: 701a strb r2, [r3, #0] N /= 10; 8002bba: f9b7 3006 ldrsh.w r3, [r7, #6] 8002bbe: 4a32 ldr r2, [pc, #200] @ (8002c88 ) 8002bc0: fb82 1203 smull r1, r2, r2, r3 8002bc4: 1092 asrs r2, r2, #2 8002bc6: 17db asrs r3, r3, #31 8002bc8: 1ad3 subs r3, r2, r3 8002bca: 80fb strh r3, [r7, #6] while (N > 0) 8002bcc: f9b7 3006 ldrsh.w r3, [r7, #6] 8002bd0: 2b00 cmp r3, #0 8002bd2: dcd2 bgt.n 8002b7a 8002bd4: e000 b.n 8002bd8 break; // Proteção de estouro 8002bd6: bf00 nop } // Adiciona o sinal de menos se necessário if (sign < 0) 8002bd8: f9b7 3010 ldrsh.w r3, [r7, #16] 8002bdc: 2b00 cmp r3, #0 8002bde: da1a bge.n 8002c16 { if (i < (max_len - 1)) 8002be0: f9b7 2016 ldrsh.w r2, [r7, #22] 8002be4: 7bfb ldrb r3, [r7, #15] 8002be6: 3b01 subs r3, #1 8002be8: 429a cmp r2, r3 8002bea: da14 bge.n 8002c16 str[i++] = '-'; 8002bec: f9b7 2016 ldrsh.w r2, [r7, #22] 8002bf0: b293 uxth r3, r2 8002bf2: 3301 adds r3, #1 8002bf4: b29b uxth r3, r3 8002bf6: 82fb strh r3, [r7, #22] 8002bf8: 683b ldr r3, [r7, #0] 8002bfa: 4413 add r3, r2 8002bfc: 222d movs r2, #45 @ 0x2d 8002bfe: 701a strb r2, [r3, #0] } // Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal) while (i < width && i < (max_len - 1)) 8002c00: e009 b.n 8002c16 { str[i++] = '0'; 8002c02: f9b7 2016 ldrsh.w r2, [r7, #22] 8002c06: b293 uxth r3, r2 8002c08: 3301 adds r3, #1 8002c0a: b29b uxth r3, r3 8002c0c: 82fb strh r3, [r7, #22] 8002c0e: 683b ldr r3, [r7, #0] 8002c10: 4413 add r3, r2 8002c12: 2230 movs r2, #48 @ 0x30 8002c14: 701a strb r2, [r3, #0] while (i < width && i < (max_len - 1)) 8002c16: f9b7 2016 ldrsh.w r2, [r7, #22] 8002c1a: 7d7b ldrb r3, [r7, #21] 8002c1c: 429a cmp r2, r3 8002c1e: da05 bge.n 8002c2c 8002c20: f9b7 2016 ldrsh.w r2, [r7, #22] 8002c24: 7bfb ldrb r3, [r7, #15] 8002c26: 3b01 subs r3, #1 8002c28: 429a cmp r2, r3 8002c2a: dbea blt.n 8002c02 } str[i] = '\0'; 8002c2c: f9b7 3016 ldrsh.w r3, [r7, #22] 8002c30: 683a ldr r2, [r7, #0] 8002c32: 4413 add r3, r2 8002c34: 2200 movs r2, #0 8002c36: 701a strb r2, [r3, #0] // Inverte a string para colocar na ordem correta for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002c38: 2300 movs r3, #0 8002c3a: 753b strb r3, [r7, #20] 8002c3c: 8afb ldrh r3, [r7, #22] 8002c3e: b2db uxtb r3, r3 8002c40: 3b01 subs r3, #1 8002c42: 74fb strb r3, [r7, #19] 8002c44: e017 b.n 8002c76 { uint8_t temp = str[j]; 8002c46: 7d3b ldrb r3, [r7, #20] 8002c48: 683a ldr r2, [r7, #0] 8002c4a: 4413 add r3, r2 8002c4c: 781b ldrb r3, [r3, #0] 8002c4e: 73bb strb r3, [r7, #14] str[j] = str[k]; 8002c50: 7cfb ldrb r3, [r7, #19] 8002c52: 683a ldr r2, [r7, #0] 8002c54: 441a add r2, r3 8002c56: 7d3b ldrb r3, [r7, #20] 8002c58: 6839 ldr r1, [r7, #0] 8002c5a: 440b add r3, r1 8002c5c: 7812 ldrb r2, [r2, #0] 8002c5e: 701a strb r2, [r3, #0] str[k] = temp; 8002c60: 7cfb ldrb r3, [r7, #19] 8002c62: 683a ldr r2, [r7, #0] 8002c64: 4413 add r3, r2 8002c66: 7bba ldrb r2, [r7, #14] 8002c68: 701a strb r2, [r3, #0] for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002c6a: 7d3b ldrb r3, [r7, #20] 8002c6c: 3301 adds r3, #1 8002c6e: 753b strb r3, [r7, #20] 8002c70: 7cfb ldrb r3, [r7, #19] 8002c72: 3b01 subs r3, #1 8002c74: 74fb strb r3, [r7, #19] 8002c76: 7d3a ldrb r2, [r7, #20] 8002c78: 7cfb ldrb r3, [r7, #19] 8002c7a: 429a cmp r2, r3 8002c7c: d3e3 bcc.n 8002c46 } } 8002c7e: 371c adds r7, #28 8002c80: 46bd mov sp, r7 8002c82: bc80 pop {r7} 8002c84: 4770 bx lr 8002c86: bf00 nop 8002c88: 66666667 .word 0x66666667 08002c8c : } /* TIM3 Timer Interrupt */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8002c8c: b480 push {r7} 8002c8e: b083 sub sp, #12 8002c90: af00 add r7, sp, #0 8002c92: 6078 str r0, [r7, #4] if (htim->Instance == TIM3) 8002c94: 687b ldr r3, [r7, #4] 8002c96: 681b ldr r3, [r3, #0] 8002c98: 4a06 ldr r2, [pc, #24] @ (8002cb4 ) 8002c9a: 4293 cmp r3, r2 8002c9c: d104 bne.n 8002ca8 { g_ms_counter++; /* Relógio global do sistema */ 8002c9e: 4b06 ldr r3, [pc, #24] @ (8002cb8 ) 8002ca0: 681b ldr r3, [r3, #0] 8002ca2: 3301 adds r3, #1 8002ca4: 4a04 ldr r2, [pc, #16] @ (8002cb8 ) 8002ca6: 6013 str r3, [r2, #0] } } 8002ca8: bf00 nop 8002caa: 370c adds r7, #12 8002cac: 46bd mov sp, r7 8002cae: bc80 pop {r7} 8002cb0: 4770 bx lr 8002cb2: bf00 nop 8002cb4: 40000400 .word 0x40000400 8002cb8: 20000084 .word 0x20000084 08002cbc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002cbc: b480 push {r7} 8002cbe: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8002cc0: b672 cpsid i } 8002cc2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8002cc4: bf00 nop 8002cc6: e7fd b.n 8002cc4 08002cc8 : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 8002cc8: b480 push {r7} 8002cca: b083 sub sp, #12 8002ccc: af00 add r7, sp, #0 8002cce: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 8002cd0: 687b ldr r3, [r7, #4] 8002cd2: 689b ldr r3, [r3, #8] } 8002cd4: 4618 mov r0, r3 8002cd6: 370c adds r7, #12 8002cd8: 46bd mov sp, r7 8002cda: bc80 pop {r7} 8002cdc: 4770 bx lr ... 08002ce0 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 8002ce0: b580 push {r7, lr} 8002ce2: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 8002ce4: f000 f864 bl 8002db0 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 8002ce8: f000 f8a8 bl 8002e3c /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 8002cec: f000 f808 bl 8002d00 8002cf0: 4603 mov r3, r0 8002cf2: 461a mov r2, r3 8002cf4: 4b01 ldr r3, [pc, #4] @ (8002cfc ) 8002cf6: 709a strb r2, [r3, #2] } 8002cf8: bf00 nop 8002cfa: bd80 pop {r7, pc} 8002cfc: 20000498 .word 0x20000498 08002d00 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 8002d00: b598 push {r3, r4, r7, lr} 8002d02: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 8002d04: 480a ldr r0, [pc, #40] @ (8002d30 ) 8002d06: f7ff ffdf bl 8002cc8 8002d0a: 4603 mov r3, r0 8002d0c: 0a1b lsrs r3, r3, #8 8002d0e: b2db uxtb r3, r3 8002d10: f023 030f bic.w r3, r3, #15 8002d14: b2dc uxtb r4, r3 8002d16: 4807 ldr r0, [pc, #28] @ (8002d34 ) 8002d18: f7ff ffd6 bl 8002cc8 8002d1c: 4603 mov r3, r0 8002d1e: 089b lsrs r3, r3, #2 8002d20: b2db uxtb r3, r3 8002d22: f003 030f and.w r3, r3, #15 8002d26: b2db uxtb r3, r3 8002d28: 4323 orrs r3, r4 8002d2a: b2db uxtb r3, r3 } 8002d2c: 4618 mov r0, r3 8002d2e: bd98 pop {r3, r4, r7, pc} 8002d30: 40010c00 .word 0x40010c00 8002d34: 40010800 .word 0x40010800 08002d38 : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 8002d38: b580 push {r7, lr} 8002d3a: b084 sub sp, #16 8002d3c: af00 add r7, sp, #0 8002d3e: 6078 str r0, [r7, #4] 8002d40: 460b mov r3, r1 8002d42: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 8002d44: f000 f81c bl 8002d80 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 8002d48: 2300 movs r3, #0 8002d4a: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8002d4c: f107 010e add.w r1, r7, #14 8002d50: f04f 33ff mov.w r3, #4294967295 8002d54: 2201 movs r2, #1 8002d56: 4809 ldr r0, [pc, #36] @ (8002d7c ) 8002d58: f003 f99c bl 8006094 /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 8002d5c: 887a ldrh r2, [r7, #2] 8002d5e: f04f 33ff mov.w r3, #4294967295 8002d62: 6879 ldr r1, [r7, #4] 8002d64: 4805 ldr r0, [pc, #20] @ (8002d7c ) 8002d66: f003 f995 bl 8006094 8002d6a: 4603 mov r3, r0 8002d6c: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 8002d6e: f000 f813 bl 8002d98 return status; 8002d72: 7bfb ldrb r3, [r7, #15] } 8002d74: 4618 mov r0, r3 8002d76: 3710 adds r7, #16 8002d78: 46bd mov sp, r7 8002d7a: bd80 pop {r7, pc} 8002d7c: 2000049c .word 0x2000049c 08002d80 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 8002d80: b580 push {r7, lr} 8002d82: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 8002d84: 2201 movs r2, #1 8002d86: f44f 5180 mov.w r1, #4096 @ 0x1000 8002d8a: 4802 ldr r0, [pc, #8] @ (8002d94 ) 8002d8c: f001 f813 bl 8003db6 } 8002d90: bf00 nop 8002d92: bd80 pop {r7, pc} 8002d94: 40010800 .word 0x40010800 08002d98 : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 8002d98: b580 push {r7, lr} 8002d9a: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 8002d9c: 2200 movs r2, #0 8002d9e: f44f 5180 mov.w r1, #4096 @ 0x1000 8002da2: 4802 ldr r0, [pc, #8] @ (8002dac ) 8002da4: f001 f807 bl 8003db6 } 8002da8: bf00 nop 8002daa: bd80 pop {r7, pc} 8002dac: 40010800 .word 0x40010800 08002db0 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 8002db0: b580 push {r7, lr} 8002db2: b086 sub sp, #24 8002db4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002db6: f107 0308 add.w r3, r7, #8 8002dba: 2200 movs r2, #0 8002dbc: 601a str r2, [r3, #0] 8002dbe: 605a str r2, [r3, #4] 8002dc0: 609a str r2, [r3, #8] 8002dc2: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002dc4: 4b1a ldr r3, [pc, #104] @ (8002e30 ) 8002dc6: 699b ldr r3, [r3, #24] 8002dc8: 4a19 ldr r2, [pc, #100] @ (8002e30 ) 8002dca: f043 0304 orr.w r3, r3, #4 8002dce: 6193 str r3, [r2, #24] 8002dd0: 4b17 ldr r3, [pc, #92] @ (8002e30 ) 8002dd2: 699b ldr r3, [r3, #24] 8002dd4: f003 0304 and.w r3, r3, #4 8002dd8: 607b str r3, [r7, #4] 8002dda: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002ddc: 4b14 ldr r3, [pc, #80] @ (8002e30 ) 8002dde: 699b ldr r3, [r3, #24] 8002de0: 4a13 ldr r2, [pc, #76] @ (8002e30 ) 8002de2: f043 0308 orr.w r3, r3, #8 8002de6: 6193 str r3, [r2, #24] 8002de8: 4b11 ldr r3, [pc, #68] @ (8002e30 ) 8002dea: 699b ldr r3, [r3, #24] 8002dec: f003 0308 and.w r3, r3, #8 8002df0: 603b str r3, [r7, #0] 8002df2: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 8002df4: 233c movs r3, #60 @ 0x3c 8002df6: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002df8: 2300 movs r3, #0 8002dfa: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002dfc: 2301 movs r3, #1 8002dfe: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002e00: f107 0308 add.w r3, r7, #8 8002e04: 4619 mov r1, r3 8002e06: 480b ldr r0, [pc, #44] @ (8002e34 ) 8002e08: f000 fe3a bl 8003a80 /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 8002e0c: f44f 4370 mov.w r3, #61440 @ 0xf000 8002e10: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002e12: 2300 movs r3, #0 8002e14: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002e16: 2301 movs r3, #1 8002e18: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002e1a: f107 0308 add.w r3, r7, #8 8002e1e: 4619 mov r1, r3 8002e20: 4805 ldr r0, [pc, #20] @ (8002e38 ) 8002e22: f000 fe2d bl 8003a80 } 8002e26: bf00 nop 8002e28: 3718 adds r7, #24 8002e2a: 46bd mov sp, r7 8002e2c: bd80 pop {r7, pc} 8002e2e: bf00 nop 8002e30: 40021000 .word 0x40021000 8002e34: 40010800 .word 0x40010800 8002e38: 40010c00 .word 0x40010c00 08002e3c : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 8002e3c: b580 push {r7, lr} 8002e3e: b082 sub sp, #8 8002e40: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 8002e42: 4b18 ldr r3, [pc, #96] @ (8002ea4 ) 8002e44: 699b ldr r3, [r3, #24] 8002e46: 4a17 ldr r2, [pc, #92] @ (8002ea4 ) 8002e48: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002e4c: 6193 str r3, [r2, #24] 8002e4e: 4b15 ldr r3, [pc, #84] @ (8002ea4 ) 8002e50: 699b ldr r3, [r3, #24] 8002e52: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002e56: 607b str r3, [r7, #4] 8002e58: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 8002e5a: 4b13 ldr r3, [pc, #76] @ (8002ea8 ) 8002e5c: 4a13 ldr r2, [pc, #76] @ (8002eac ) 8002e5e: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002e60: 4b11 ldr r3, [pc, #68] @ (8002ea8 ) 8002e62: f44f 5216 mov.w r2, #9600 @ 0x2580 8002e66: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002e68: 4b0f ldr r3, [pc, #60] @ (8002ea8 ) 8002e6a: 2200 movs r2, #0 8002e6c: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002e6e: 4b0e ldr r3, [pc, #56] @ (8002ea8 ) 8002e70: 2200 movs r2, #0 8002e72: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002e74: 4b0c ldr r3, [pc, #48] @ (8002ea8 ) 8002e76: 2200 movs r2, #0 8002e78: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002e7a: 4b0b ldr r3, [pc, #44] @ (8002ea8 ) 8002e7c: 220c movs r2, #12 8002e7e: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 8002e80: 4b09 ldr r3, [pc, #36] @ (8002ea8 ) 8002e82: 2200 movs r2, #0 8002e84: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002e86: 4b08 ldr r3, [pc, #32] @ (8002ea8 ) 8002e88: 2200 movs r2, #0 8002e8a: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002e8c: 4806 ldr r0, [pc, #24] @ (8002ea8 ) 8002e8e: f003 f8b1 bl 8005ff4 8002e92: 4603 mov r3, r0 8002e94: 2b00 cmp r3, #0 8002e96: d001 beq.n 8002e9c { /* Initialization Error */ while(1); 8002e98: bf00 nop 8002e9a: e7fd b.n 8002e98 } } 8002e9c: bf00 nop 8002e9e: 3708 adds r7, #8 8002ea0: 46bd mov sp, r7 8002ea2: bd80 pop {r7, pc} 8002ea4: 40021000 .word 0x40021000 8002ea8: 2000049c .word 0x2000049c 8002eac: 40013800 .word 0x40013800 08002eb0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002eb0: b480 push {r7} 8002eb2: b085 sub sp, #20 8002eb4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8002eb6: 4b15 ldr r3, [pc, #84] @ (8002f0c ) 8002eb8: 699b ldr r3, [r3, #24] 8002eba: 4a14 ldr r2, [pc, #80] @ (8002f0c ) 8002ebc: f043 0301 orr.w r3, r3, #1 8002ec0: 6193 str r3, [r2, #24] 8002ec2: 4b12 ldr r3, [pc, #72] @ (8002f0c ) 8002ec4: 699b ldr r3, [r3, #24] 8002ec6: f003 0301 and.w r3, r3, #1 8002eca: 60bb str r3, [r7, #8] 8002ecc: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8002ece: 4b0f ldr r3, [pc, #60] @ (8002f0c ) 8002ed0: 69db ldr r3, [r3, #28] 8002ed2: 4a0e ldr r2, [pc, #56] @ (8002f0c ) 8002ed4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8002ed8: 61d3 str r3, [r2, #28] 8002eda: 4b0c ldr r3, [pc, #48] @ (8002f0c ) 8002edc: 69db ldr r3, [r3, #28] 8002ede: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002ee2: 607b str r3, [r7, #4] 8002ee4: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8002ee6: 4b0a ldr r3, [pc, #40] @ (8002f10 ) 8002ee8: 685b ldr r3, [r3, #4] 8002eea: 60fb str r3, [r7, #12] 8002eec: 68fb ldr r3, [r7, #12] 8002eee: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 8002ef2: 60fb str r3, [r7, #12] 8002ef4: 68fb ldr r3, [r7, #12] 8002ef6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8002efa: 60fb str r3, [r7, #12] 8002efc: 4a04 ldr r2, [pc, #16] @ (8002f10 ) 8002efe: 68fb ldr r3, [r7, #12] 8002f00: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002f02: bf00 nop 8002f04: 3714 adds r7, #20 8002f06: 46bd mov sp, r7 8002f08: bc80 pop {r7} 8002f0a: 4770 bx lr 8002f0c: 40021000 .word 0x40021000 8002f10: 40010000 .word 0x40010000 08002f14 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8002f14: b480 push {r7} 8002f16: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8002f18: bf00 nop 8002f1a: e7fd b.n 8002f18 08002f1c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002f1c: b480 push {r7} 8002f1e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002f20: bf00 nop 8002f22: e7fd b.n 8002f20 08002f24 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002f24: b480 push {r7} 8002f26: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8002f28: bf00 nop 8002f2a: e7fd b.n 8002f28 08002f2c : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8002f2c: b480 push {r7} 8002f2e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002f30: bf00 nop 8002f32: e7fd b.n 8002f30 08002f34 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002f34: b480 push {r7} 8002f36: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002f38: bf00 nop 8002f3a: e7fd b.n 8002f38 08002f3c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002f3c: b480 push {r7} 8002f3e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002f40: bf00 nop 8002f42: 46bd mov sp, r7 8002f44: bc80 pop {r7} 8002f46: 4770 bx lr 08002f48 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002f48: b480 push {r7} 8002f4a: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002f4c: bf00 nop 8002f4e: 46bd mov sp, r7 8002f50: bc80 pop {r7} 8002f52: 4770 bx lr 08002f54 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002f54: b480 push {r7} 8002f56: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002f58: bf00 nop 8002f5a: 46bd mov sp, r7 8002f5c: bc80 pop {r7} 8002f5e: 4770 bx lr 08002f60 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002f60: b580 push {r7, lr} 8002f62: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002f64: f000 f97a bl 800325c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002f68: bf00 nop 8002f6a: bd80 pop {r7, pc} 08002f6c : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8002f6c: b580 push {r7, lr} 8002f6e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002f70: 4802 ldr r0, [pc, #8] @ (8002f7c ) 8002f72: f002 fcef bl 8005954 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 8002f76: bf00 nop 8002f78: bd80 pop {r7, pc} 8002f7a: bf00 nop 8002f7c: 200004e4 .word 0x200004e4 08002f80 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8002f80: b580 push {r7, lr} 8002f82: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8002f84: 4802 ldr r0, [pc, #8] @ (8002f90 ) 8002f86: f003 f911 bl 80061ac /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8002f8a: bf00 nop 8002f8c: bd80 pop {r7, pc} 8002f8e: bf00 nop 8002f90: 2000052c .word 0x2000052c 08002f94 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002f94: b480 push {r7} 8002f96: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002f98: bf00 nop 8002f9a: 46bd mov sp, r7 8002f9c: bc80 pop {r7} 8002f9e: 4770 bx lr 08002fa0 : TIM_HandleTypeDef htim3; /* TIM3 init function */ void MX_TIM3_Init(void) { 8002fa0: b580 push {r7, lr} 8002fa2: b086 sub sp, #24 8002fa4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8002fa6: f107 0308 add.w r3, r7, #8 8002faa: 2200 movs r2, #0 8002fac: 601a str r2, [r3, #0] 8002fae: 605a str r2, [r3, #4] 8002fb0: 609a str r2, [r3, #8] 8002fb2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8002fb4: 463b mov r3, r7 8002fb6: 2200 movs r2, #0 8002fb8: 601a str r2, [r3, #0] 8002fba: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8002fbc: 4b1d ldr r3, [pc, #116] @ (8003034 ) 8002fbe: 4a1e ldr r2, [pc, #120] @ (8003038 ) 8002fc0: 601a str r2, [r3, #0] htim3.Init.Prescaler = 2; 8002fc2: 4b1c ldr r3, [pc, #112] @ (8003034 ) 8002fc4: 2202 movs r2, #2 8002fc6: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8002fc8: 4b1a ldr r3, [pc, #104] @ (8003034 ) 8002fca: 2200 movs r2, #0 8002fcc: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8002fce: 4b19 ldr r3, [pc, #100] @ (8003034 ) 8002fd0: f240 32e7 movw r2, #999 @ 0x3e7 8002fd4: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002fd6: 4b17 ldr r3, [pc, #92] @ (8003034 ) 8002fd8: 2200 movs r2, #0 8002fda: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8002fdc: 4b15 ldr r3, [pc, #84] @ (8003034 ) 8002fde: 2280 movs r2, #128 @ 0x80 8002fe0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8002fe2: 4814 ldr r0, [pc, #80] @ (8003034 ) 8002fe4: f002 fc14 bl 8005810 8002fe8: 4603 mov r3, r0 8002fea: 2b00 cmp r3, #0 8002fec: d001 beq.n 8002ff2 { Error_Handler(); 8002fee: f7ff fe65 bl 8002cbc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002ff2: f44f 5380 mov.w r3, #4096 @ 0x1000 8002ff6: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8002ff8: f107 0308 add.w r3, r7, #8 8002ffc: 4619 mov r1, r3 8002ffe: 480d ldr r0, [pc, #52] @ (8003034 ) 8003000: f002 fd98 bl 8005b34 8003004: 4603 mov r3, r0 8003006: 2b00 cmp r3, #0 8003008: d001 beq.n 800300e { Error_Handler(); 800300a: f7ff fe57 bl 8002cbc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800300e: 2300 movs r3, #0 8003010: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8003012: 2300 movs r3, #0 8003014: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8003016: 463b mov r3, r7 8003018: 4619 mov r1, r3 800301a: 4806 ldr r0, [pc, #24] @ (8003034 ) 800301c: f002 ff7a bl 8005f14 8003020: 4603 mov r3, r0 8003022: 2b00 cmp r3, #0 8003024: d001 beq.n 800302a { Error_Handler(); 8003026: f7ff fe49 bl 8002cbc } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 800302a: bf00 nop 800302c: 3718 adds r7, #24 800302e: 46bd mov sp, r7 8003030: bd80 pop {r7, pc} 8003032: bf00 nop 8003034: 200004e4 .word 0x200004e4 8003038: 40000400 .word 0x40000400 0800303c : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800303c: b580 push {r7, lr} 800303e: b084 sub sp, #16 8003040: af00 add r7, sp, #0 8003042: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 8003044: 687b ldr r3, [r7, #4] 8003046: 681b ldr r3, [r3, #0] 8003048: 4a0d ldr r2, [pc, #52] @ (8003080 ) 800304a: 4293 cmp r3, r2 800304c: d113 bne.n 8003076 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800304e: 4b0d ldr r3, [pc, #52] @ (8003084 ) 8003050: 69db ldr r3, [r3, #28] 8003052: 4a0c ldr r2, [pc, #48] @ (8003084 ) 8003054: f043 0302 orr.w r3, r3, #2 8003058: 61d3 str r3, [r2, #28] 800305a: 4b0a ldr r3, [pc, #40] @ (8003084 ) 800305c: 69db ldr r3, [r3, #28] 800305e: f003 0302 and.w r3, r3, #2 8003062: 60fb str r3, [r7, #12] 8003064: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 8003066: 2200 movs r2, #0 8003068: 2100 movs r1, #0 800306a: 201d movs r0, #29 800306c: f000 fc1f bl 80038ae HAL_NVIC_EnableIRQ(TIM3_IRQn); 8003070: 201d movs r0, #29 8003072: f000 fc38 bl 80038e6 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8003076: bf00 nop 8003078: 3710 adds r7, #16 800307a: 46bd mov sp, r7 800307c: bd80 pop {r7, pc} 800307e: bf00 nop 8003080: 40000400 .word 0x40000400 8003084: 40021000 .word 0x40021000 08003088 : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 8003088: b580 push {r7, lr} 800308a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800308c: 4b11 ldr r3, [pc, #68] @ (80030d4 ) 800308e: 4a12 ldr r2, [pc, #72] @ (80030d8 ) 8003090: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8003092: 4b10 ldr r3, [pc, #64] @ (80030d4 ) 8003094: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8003098: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800309a: 4b0e ldr r3, [pc, #56] @ (80030d4 ) 800309c: 2200 movs r2, #0 800309e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80030a0: 4b0c ldr r3, [pc, #48] @ (80030d4 ) 80030a2: 2200 movs r2, #0 80030a4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80030a6: 4b0b ldr r3, [pc, #44] @ (80030d4 ) 80030a8: 2200 movs r2, #0 80030aa: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80030ac: 4b09 ldr r3, [pc, #36] @ (80030d4 ) 80030ae: 220c movs r2, #12 80030b0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80030b2: 4b08 ldr r3, [pc, #32] @ (80030d4 ) 80030b4: 2200 movs r2, #0 80030b6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80030b8: 4b06 ldr r3, [pc, #24] @ (80030d4 ) 80030ba: 2200 movs r2, #0 80030bc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80030be: 4805 ldr r0, [pc, #20] @ (80030d4 ) 80030c0: f002 ff98 bl 8005ff4 80030c4: 4603 mov r3, r0 80030c6: 2b00 cmp r3, #0 80030c8: d001 beq.n 80030ce { Error_Handler(); 80030ca: f7ff fdf7 bl 8002cbc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80030ce: bf00 nop 80030d0: bd80 pop {r7, pc} 80030d2: bf00 nop 80030d4: 2000052c .word 0x2000052c 80030d8: 40013800 .word 0x40013800 080030dc : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80030dc: b580 push {r7, lr} 80030de: b088 sub sp, #32 80030e0: af00 add r7, sp, #0 80030e2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80030e4: f107 0310 add.w r3, r7, #16 80030e8: 2200 movs r2, #0 80030ea: 601a str r2, [r3, #0] 80030ec: 605a str r2, [r3, #4] 80030ee: 609a str r2, [r3, #8] 80030f0: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 80030f2: 687b ldr r3, [r7, #4] 80030f4: 681b ldr r3, [r3, #0] 80030f6: 4a20 ldr r2, [pc, #128] @ (8003178 ) 80030f8: 4293 cmp r3, r2 80030fa: d139 bne.n 8003170 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80030fc: 4b1f ldr r3, [pc, #124] @ (800317c ) 80030fe: 699b ldr r3, [r3, #24] 8003100: 4a1e ldr r2, [pc, #120] @ (800317c ) 8003102: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8003106: 6193 str r3, [r2, #24] 8003108: 4b1c ldr r3, [pc, #112] @ (800317c ) 800310a: 699b ldr r3, [r3, #24] 800310c: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003110: 60fb str r3, [r7, #12] 8003112: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003114: 4b19 ldr r3, [pc, #100] @ (800317c ) 8003116: 699b ldr r3, [r3, #24] 8003118: 4a18 ldr r2, [pc, #96] @ (800317c ) 800311a: f043 0304 orr.w r3, r3, #4 800311e: 6193 str r3, [r2, #24] 8003120: 4b16 ldr r3, [pc, #88] @ (800317c ) 8003122: 699b ldr r3, [r3, #24] 8003124: f003 0304 and.w r3, r3, #4 8003128: 60bb str r3, [r7, #8] 800312a: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 800312c: f44f 7300 mov.w r3, #512 @ 0x200 8003130: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003132: 2302 movs r3, #2 8003134: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8003136: 2301 movs r3, #1 8003138: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 800313a: f107 0310 add.w r3, r7, #16 800313e: 4619 mov r1, r3 8003140: 480f ldr r0, [pc, #60] @ (8003180 ) 8003142: f000 fc9d bl 8003a80 GPIO_InitStruct.Pin = RX_RS485_Pin; 8003146: f44f 6380 mov.w r3, #1024 @ 0x400 800314a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800314c: 2300 movs r3, #0 800314e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003150: 2300 movs r3, #0 8003152: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 8003154: f107 0310 add.w r3, r7, #16 8003158: 4619 mov r1, r3 800315a: 4809 ldr r0, [pc, #36] @ (8003180 ) 800315c: f000 fc90 bl 8003a80 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8003160: 2200 movs r2, #0 8003162: 2100 movs r1, #0 8003164: 2025 movs r0, #37 @ 0x25 8003166: f000 fba2 bl 80038ae HAL_NVIC_EnableIRQ(USART1_IRQn); 800316a: 2025 movs r0, #37 @ 0x25 800316c: f000 fbbb bl 80038e6 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8003170: bf00 nop 8003172: 3720 adds r7, #32 8003174: 46bd mov sp, r7 8003176: bd80 pop {r7, pc} 8003178: 40013800 .word 0x40013800 800317c: 40021000 .word 0x40021000 8003180: 40010800 .word 0x40010800 08003184 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8003184: f7ff ff06 bl 8002f94 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8003188: 480b ldr r0, [pc, #44] @ (80031b8 ) ldr r1, =_edata 800318a: 490c ldr r1, [pc, #48] @ (80031bc ) ldr r2, =_sidata 800318c: 4a0c ldr r2, [pc, #48] @ (80031c0 ) movs r3, #0 800318e: 2300 movs r3, #0 b LoopCopyDataInit 8003190: e002 b.n 8003198 08003192 : CopyDataInit: ldr r4, [r2, r3] 8003192: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8003194: 50c4 str r4, [r0, r3] adds r3, r3, #4 8003196: 3304 adds r3, #4 08003198 : LoopCopyDataInit: adds r4, r0, r3 8003198: 18c4 adds r4, r0, r3 cmp r4, r1 800319a: 428c cmp r4, r1 bcc CopyDataInit 800319c: d3f9 bcc.n 8003192 /* Zero fill the bss segment. */ ldr r2, =_sbss 800319e: 4a09 ldr r2, [pc, #36] @ (80031c4 ) ldr r4, =_ebss 80031a0: 4c09 ldr r4, [pc, #36] @ (80031c8 ) movs r3, #0 80031a2: 2300 movs r3, #0 b LoopFillZerobss 80031a4: e001 b.n 80031aa 080031a6 : FillZerobss: str r3, [r2] 80031a6: 6013 str r3, [r2, #0] adds r2, r2, #4 80031a8: 3204 adds r2, #4 080031aa : LoopFillZerobss: cmp r2, r4 80031aa: 42a2 cmp r2, r4 bcc FillZerobss 80031ac: d3fb bcc.n 80031a6 /* Call static constructors */ bl __libc_init_array 80031ae: f003 fd45 bl 8006c3c <__libc_init_array> /* Call the application's entry point.*/ bl main 80031b2: f7ff f9fb bl 80025ac

bx lr 80031b6: 4770 bx lr ldr r0, =_sdata 80031b8: 20000000 .word 0x20000000 ldr r1, =_edata 80031bc: 20000060 .word 0x20000060 ldr r2, =_sidata 80031c0: 08006f50 .word 0x08006f50 ldr r2, =_sbss 80031c4: 20000060 .word 0x20000060 ldr r4, =_ebss 80031c8: 200006b0 .word 0x200006b0 080031cc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80031cc: e7fe b.n 80031cc ... 080031d0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80031d0: b580 push {r7, lr} 80031d2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80031d4: 4b08 ldr r3, [pc, #32] @ (80031f8 ) 80031d6: 681b ldr r3, [r3, #0] 80031d8: 4a07 ldr r2, [pc, #28] @ (80031f8 ) 80031da: f043 0310 orr.w r3, r3, #16 80031de: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80031e0: 2003 movs r0, #3 80031e2: f000 fb59 bl 8003898 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80031e6: 200f movs r0, #15 80031e8: f000 f808 bl 80031fc /* Init the low level hardware */ HAL_MspInit(); 80031ec: f7ff fe60 bl 8002eb0 /* Return function status */ return HAL_OK; 80031f0: 2300 movs r3, #0 } 80031f2: 4618 mov r0, r3 80031f4: bd80 pop {r7, pc} 80031f6: bf00 nop 80031f8: 40022000 .word 0x40022000 080031fc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80031fc: b580 push {r7, lr} 80031fe: b082 sub sp, #8 8003200: af00 add r7, sp, #0 8003202: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8003204: 4b12 ldr r3, [pc, #72] @ (8003250 ) 8003206: 681a ldr r2, [r3, #0] 8003208: 4b12 ldr r3, [pc, #72] @ (8003254 ) 800320a: 781b ldrb r3, [r3, #0] 800320c: 4619 mov r1, r3 800320e: f44f 737a mov.w r3, #1000 @ 0x3e8 8003212: fbb3 f3f1 udiv r3, r3, r1 8003216: fbb2 f3f3 udiv r3, r2, r3 800321a: 4618 mov r0, r3 800321c: f000 fb71 bl 8003902 8003220: 4603 mov r3, r0 8003222: 2b00 cmp r3, #0 8003224: d001 beq.n 800322a { return HAL_ERROR; 8003226: 2301 movs r3, #1 8003228: e00e b.n 8003248 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800322a: 687b ldr r3, [r7, #4] 800322c: 2b0f cmp r3, #15 800322e: d80a bhi.n 8003246 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8003230: 2200 movs r2, #0 8003232: 6879 ldr r1, [r7, #4] 8003234: f04f 30ff mov.w r0, #4294967295 8003238: f000 fb39 bl 80038ae uwTickPrio = TickPriority; 800323c: 4a06 ldr r2, [pc, #24] @ (8003258 ) 800323e: 687b ldr r3, [r7, #4] 8003240: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8003242: 2300 movs r3, #0 8003244: e000 b.n 8003248 return HAL_ERROR; 8003246: 2301 movs r3, #1 } 8003248: 4618 mov r0, r3 800324a: 3708 adds r7, #8 800324c: 46bd mov sp, r7 800324e: bd80 pop {r7, pc} 8003250: 20000004 .word 0x20000004 8003254: 2000000c .word 0x2000000c 8003258: 20000008 .word 0x20000008 0800325c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800325c: b480 push {r7} 800325e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8003260: 4b05 ldr r3, [pc, #20] @ (8003278 ) 8003262: 781b ldrb r3, [r3, #0] 8003264: 461a mov r2, r3 8003266: 4b05 ldr r3, [pc, #20] @ (800327c ) 8003268: 681b ldr r3, [r3, #0] 800326a: 4413 add r3, r2 800326c: 4a03 ldr r2, [pc, #12] @ (800327c ) 800326e: 6013 str r3, [r2, #0] } 8003270: bf00 nop 8003272: 46bd mov sp, r7 8003274: bc80 pop {r7} 8003276: 4770 bx lr 8003278: 2000000c .word 0x2000000c 800327c: 20000574 .word 0x20000574 08003280 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8003280: b480 push {r7} 8003282: af00 add r7, sp, #0 return uwTick; 8003284: 4b02 ldr r3, [pc, #8] @ (8003290 ) 8003286: 681b ldr r3, [r3, #0] } 8003288: 4618 mov r0, r3 800328a: 46bd mov sp, r7 800328c: bc80 pop {r7} 800328e: 4770 bx lr 8003290: 20000574 .word 0x20000574 08003294 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8003294: b580 push {r7, lr} 8003296: b084 sub sp, #16 8003298: af00 add r7, sp, #0 800329a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800329c: f7ff fff0 bl 8003280 80032a0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80032a2: 687b ldr r3, [r7, #4] 80032a4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80032a6: 68fb ldr r3, [r7, #12] 80032a8: f1b3 3fff cmp.w r3, #4294967295 80032ac: d005 beq.n 80032ba { wait += (uint32_t)(uwTickFreq); 80032ae: 4b0a ldr r3, [pc, #40] @ (80032d8 ) 80032b0: 781b ldrb r3, [r3, #0] 80032b2: 461a mov r2, r3 80032b4: 68fb ldr r3, [r7, #12] 80032b6: 4413 add r3, r2 80032b8: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80032ba: bf00 nop 80032bc: f7ff ffe0 bl 8003280 80032c0: 4602 mov r2, r0 80032c2: 68bb ldr r3, [r7, #8] 80032c4: 1ad3 subs r3, r2, r3 80032c6: 68fa ldr r2, [r7, #12] 80032c8: 429a cmp r2, r3 80032ca: d8f7 bhi.n 80032bc { } } 80032cc: bf00 nop 80032ce: bf00 nop 80032d0: 3710 adds r7, #16 80032d2: 46bd mov sp, r7 80032d4: bd80 pop {r7, pc} 80032d6: bf00 nop 80032d8: 2000000c .word 0x2000000c 080032dc : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80032dc: b580 push {r7, lr} 80032de: b086 sub sp, #24 80032e0: af00 add r7, sp, #0 80032e2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80032e4: 2300 movs r3, #0 80032e6: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 80032e8: 2300 movs r3, #0 80032ea: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 80032ec: 2300 movs r3, #0 80032ee: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 80032f0: 2300 movs r3, #0 80032f2: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 80032f4: 687b ldr r3, [r7, #4] 80032f6: 2b00 cmp r3, #0 80032f8: d101 bne.n 80032fe { return HAL_ERROR; 80032fa: 2301 movs r3, #1 80032fc: e0be b.n 800347c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80032fe: 687b ldr r3, [r7, #4] 8003300: 689b ldr r3, [r3, #8] 8003302: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8003304: 687b ldr r3, [r7, #4] 8003306: 6a9b ldr r3, [r3, #40] @ 0x28 8003308: 2b00 cmp r3, #0 800330a: d109 bne.n 8003320 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800330c: 687b ldr r3, [r7, #4] 800330e: 2200 movs r2, #0 8003310: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8003312: 687b ldr r3, [r7, #4] 8003314: 2200 movs r2, #0 8003316: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800331a: 6878 ldr r0, [r7, #4] 800331c: f7fe fc48 bl 8001bb0 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8003320: 6878 ldr r0, [r7, #4] 8003322: f000 f9ab bl 800367c 8003326: 4603 mov r3, r0 8003328: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800332a: 687b ldr r3, [r7, #4] 800332c: 6a9b ldr r3, [r3, #40] @ 0x28 800332e: f003 0310 and.w r3, r3, #16 8003332: 2b00 cmp r3, #0 8003334: f040 8099 bne.w 800346a 8003338: 7dfb ldrb r3, [r7, #23] 800333a: 2b00 cmp r3, #0 800333c: f040 8095 bne.w 800346a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003340: 687b ldr r3, [r7, #4] 8003342: 6a9b ldr r3, [r3, #40] @ 0x28 8003344: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8003348: f023 0302 bic.w r3, r3, #2 800334c: f043 0202 orr.w r2, r3, #2 8003350: 687b ldr r3, [r7, #4] 8003352: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8003354: 687b ldr r3, [r7, #4] 8003356: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8003358: 687b ldr r3, [r7, #4] 800335a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800335c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800335e: 687b ldr r3, [r7, #4] 8003360: 7b1b ldrb r3, [r3, #12] 8003362: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8003364: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8003366: 68ba ldr r2, [r7, #8] 8003368: 4313 orrs r3, r2 800336a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800336c: 687b ldr r3, [r7, #4] 800336e: 689b ldr r3, [r3, #8] 8003370: f5b3 7f80 cmp.w r3, #256 @ 0x100 8003374: d003 beq.n 800337e 8003376: 687b ldr r3, [r7, #4] 8003378: 689b ldr r3, [r3, #8] 800337a: 2b01 cmp r3, #1 800337c: d102 bne.n 8003384 800337e: f44f 7380 mov.w r3, #256 @ 0x100 8003382: e000 b.n 8003386 8003384: 2300 movs r3, #0 8003386: 693a ldr r2, [r7, #16] 8003388: 4313 orrs r3, r2 800338a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800338c: 687b ldr r3, [r7, #4] 800338e: 7d1b ldrb r3, [r3, #20] 8003390: 2b01 cmp r3, #1 8003392: d119 bne.n 80033c8 { if (hadc->Init.ContinuousConvMode == DISABLE) 8003394: 687b ldr r3, [r7, #4] 8003396: 7b1b ldrb r3, [r3, #12] 8003398: 2b00 cmp r3, #0 800339a: d109 bne.n 80033b0 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800339c: 687b ldr r3, [r7, #4] 800339e: 699b ldr r3, [r3, #24] 80033a0: 3b01 subs r3, #1 80033a2: 035a lsls r2, r3, #13 80033a4: 693b ldr r3, [r7, #16] 80033a6: 4313 orrs r3, r2 80033a8: f443 6300 orr.w r3, r3, #2048 @ 0x800 80033ac: 613b str r3, [r7, #16] 80033ae: e00b b.n 80033c8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80033b0: 687b ldr r3, [r7, #4] 80033b2: 6a9b ldr r3, [r3, #40] @ 0x28 80033b4: f043 0220 orr.w r2, r3, #32 80033b8: 687b ldr r3, [r7, #4] 80033ba: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80033bc: 687b ldr r3, [r7, #4] 80033be: 6adb ldr r3, [r3, #44] @ 0x2c 80033c0: f043 0201 orr.w r2, r3, #1 80033c4: 687b ldr r3, [r7, #4] 80033c6: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80033c8: 687b ldr r3, [r7, #4] 80033ca: 681b ldr r3, [r3, #0] 80033cc: 685b ldr r3, [r3, #4] 80033ce: f423 4169 bic.w r1, r3, #59648 @ 0xe900 80033d2: 687b ldr r3, [r7, #4] 80033d4: 681b ldr r3, [r3, #0] 80033d6: 693a ldr r2, [r7, #16] 80033d8: 430a orrs r2, r1 80033da: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80033dc: 687b ldr r3, [r7, #4] 80033de: 681b ldr r3, [r3, #0] 80033e0: 689a ldr r2, [r3, #8] 80033e2: 4b28 ldr r3, [pc, #160] @ (8003484 ) 80033e4: 4013 ands r3, r2 80033e6: 687a ldr r2, [r7, #4] 80033e8: 6812 ldr r2, [r2, #0] 80033ea: 68b9 ldr r1, [r7, #8] 80033ec: 430b orrs r3, r1 80033ee: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 80033f0: 687b ldr r3, [r7, #4] 80033f2: 689b ldr r3, [r3, #8] 80033f4: f5b3 7f80 cmp.w r3, #256 @ 0x100 80033f8: d003 beq.n 8003402 80033fa: 687b ldr r3, [r7, #4] 80033fc: 689b ldr r3, [r3, #8] 80033fe: 2b01 cmp r3, #1 8003400: d104 bne.n 800340c { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8003402: 687b ldr r3, [r7, #4] 8003404: 691b ldr r3, [r3, #16] 8003406: 3b01 subs r3, #1 8003408: 051b lsls r3, r3, #20 800340a: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800340c: 687b ldr r3, [r7, #4] 800340e: 681b ldr r3, [r3, #0] 8003410: 6adb ldr r3, [r3, #44] @ 0x2c 8003412: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 8003416: 687b ldr r3, [r7, #4] 8003418: 681b ldr r3, [r3, #0] 800341a: 68fa ldr r2, [r7, #12] 800341c: 430a orrs r2, r1 800341e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003420: 687b ldr r3, [r7, #4] 8003422: 681b ldr r3, [r3, #0] 8003424: 689a ldr r2, [r3, #8] 8003426: 4b18 ldr r3, [pc, #96] @ (8003488 ) 8003428: 4013 ands r3, r2 800342a: 68ba ldr r2, [r7, #8] 800342c: 429a cmp r2, r3 800342e: d10b bne.n 8003448 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8003430: 687b ldr r3, [r7, #4] 8003432: 2200 movs r2, #0 8003434: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003436: 687b ldr r3, [r7, #4] 8003438: 6a9b ldr r3, [r3, #40] @ 0x28 800343a: f023 0303 bic.w r3, r3, #3 800343e: f043 0201 orr.w r2, r3, #1 8003442: 687b ldr r3, [r7, #4] 8003444: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003446: e018 b.n 800347a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8003448: 687b ldr r3, [r7, #4] 800344a: 6a9b ldr r3, [r3, #40] @ 0x28 800344c: f023 0312 bic.w r3, r3, #18 8003450: f043 0210 orr.w r2, r3, #16 8003454: 687b ldr r3, [r7, #4] 8003456: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003458: 687b ldr r3, [r7, #4] 800345a: 6adb ldr r3, [r3, #44] @ 0x2c 800345c: f043 0201 orr.w r2, r3, #1 8003460: 687b ldr r3, [r7, #4] 8003462: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8003464: 2301 movs r3, #1 8003466: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003468: e007 b.n 800347a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800346a: 687b ldr r3, [r7, #4] 800346c: 6a9b ldr r3, [r3, #40] @ 0x28 800346e: f043 0210 orr.w r2, r3, #16 8003472: 687b ldr r3, [r7, #4] 8003474: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8003476: 2301 movs r3, #1 8003478: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800347a: 7dfb ldrb r3, [r7, #23] } 800347c: 4618 mov r0, r3 800347e: 3718 adds r7, #24 8003480: 46bd mov sp, r7 8003482: bd80 pop {r7, pc} 8003484: ffe1f7fd .word 0xffe1f7fd 8003488: ff1f0efe .word 0xff1f0efe 0800348c : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800348c: b480 push {r7} 800348e: b085 sub sp, #20 8003490: af00 add r7, sp, #0 8003492: 6078 str r0, [r7, #4] 8003494: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003496: 2300 movs r3, #0 8003498: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800349a: 2300 movs r3, #0 800349c: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800349e: 687b ldr r3, [r7, #4] 80034a0: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80034a4: 2b01 cmp r3, #1 80034a6: d101 bne.n 80034ac 80034a8: 2302 movs r3, #2 80034aa: e0dc b.n 8003666 80034ac: 687b ldr r3, [r7, #4] 80034ae: 2201 movs r2, #1 80034b0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80034b4: 683b ldr r3, [r7, #0] 80034b6: 685b ldr r3, [r3, #4] 80034b8: 2b06 cmp r3, #6 80034ba: d81c bhi.n 80034f6 { MODIFY_REG(hadc->Instance->SQR3 , 80034bc: 687b ldr r3, [r7, #4] 80034be: 681b ldr r3, [r3, #0] 80034c0: 6b59 ldr r1, [r3, #52] @ 0x34 80034c2: 683b ldr r3, [r7, #0] 80034c4: 685a ldr r2, [r3, #4] 80034c6: 4613 mov r3, r2 80034c8: 009b lsls r3, r3, #2 80034ca: 4413 add r3, r2 80034cc: 3b05 subs r3, #5 80034ce: 221f movs r2, #31 80034d0: fa02 f303 lsl.w r3, r2, r3 80034d4: 43db mvns r3, r3 80034d6: 4019 ands r1, r3 80034d8: 683b ldr r3, [r7, #0] 80034da: 6818 ldr r0, [r3, #0] 80034dc: 683b ldr r3, [r7, #0] 80034de: 685a ldr r2, [r3, #4] 80034e0: 4613 mov r3, r2 80034e2: 009b lsls r3, r3, #2 80034e4: 4413 add r3, r2 80034e6: 3b05 subs r3, #5 80034e8: fa00 f203 lsl.w r2, r0, r3 80034ec: 687b ldr r3, [r7, #4] 80034ee: 681b ldr r3, [r3, #0] 80034f0: 430a orrs r2, r1 80034f2: 635a str r2, [r3, #52] @ 0x34 80034f4: e03c b.n 8003570 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80034f6: 683b ldr r3, [r7, #0] 80034f8: 685b ldr r3, [r3, #4] 80034fa: 2b0c cmp r3, #12 80034fc: d81c bhi.n 8003538 { MODIFY_REG(hadc->Instance->SQR2 , 80034fe: 687b ldr r3, [r7, #4] 8003500: 681b ldr r3, [r3, #0] 8003502: 6b19 ldr r1, [r3, #48] @ 0x30 8003504: 683b ldr r3, [r7, #0] 8003506: 685a ldr r2, [r3, #4] 8003508: 4613 mov r3, r2 800350a: 009b lsls r3, r3, #2 800350c: 4413 add r3, r2 800350e: 3b23 subs r3, #35 @ 0x23 8003510: 221f movs r2, #31 8003512: fa02 f303 lsl.w r3, r2, r3 8003516: 43db mvns r3, r3 8003518: 4019 ands r1, r3 800351a: 683b ldr r3, [r7, #0] 800351c: 6818 ldr r0, [r3, #0] 800351e: 683b ldr r3, [r7, #0] 8003520: 685a ldr r2, [r3, #4] 8003522: 4613 mov r3, r2 8003524: 009b lsls r3, r3, #2 8003526: 4413 add r3, r2 8003528: 3b23 subs r3, #35 @ 0x23 800352a: fa00 f203 lsl.w r2, r0, r3 800352e: 687b ldr r3, [r7, #4] 8003530: 681b ldr r3, [r3, #0] 8003532: 430a orrs r2, r1 8003534: 631a str r2, [r3, #48] @ 0x30 8003536: e01b b.n 8003570 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8003538: 687b ldr r3, [r7, #4] 800353a: 681b ldr r3, [r3, #0] 800353c: 6ad9 ldr r1, [r3, #44] @ 0x2c 800353e: 683b ldr r3, [r7, #0] 8003540: 685a ldr r2, [r3, #4] 8003542: 4613 mov r3, r2 8003544: 009b lsls r3, r3, #2 8003546: 4413 add r3, r2 8003548: 3b41 subs r3, #65 @ 0x41 800354a: 221f movs r2, #31 800354c: fa02 f303 lsl.w r3, r2, r3 8003550: 43db mvns r3, r3 8003552: 4019 ands r1, r3 8003554: 683b ldr r3, [r7, #0] 8003556: 6818 ldr r0, [r3, #0] 8003558: 683b ldr r3, [r7, #0] 800355a: 685a ldr r2, [r3, #4] 800355c: 4613 mov r3, r2 800355e: 009b lsls r3, r3, #2 8003560: 4413 add r3, r2 8003562: 3b41 subs r3, #65 @ 0x41 8003564: fa00 f203 lsl.w r2, r0, r3 8003568: 687b ldr r3, [r7, #4] 800356a: 681b ldr r3, [r3, #0] 800356c: 430a orrs r2, r1 800356e: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8003570: 683b ldr r3, [r7, #0] 8003572: 681b ldr r3, [r3, #0] 8003574: 2b09 cmp r3, #9 8003576: d91c bls.n 80035b2 { MODIFY_REG(hadc->Instance->SMPR1 , 8003578: 687b ldr r3, [r7, #4] 800357a: 681b ldr r3, [r3, #0] 800357c: 68d9 ldr r1, [r3, #12] 800357e: 683b ldr r3, [r7, #0] 8003580: 681a ldr r2, [r3, #0] 8003582: 4613 mov r3, r2 8003584: 005b lsls r3, r3, #1 8003586: 4413 add r3, r2 8003588: 3b1e subs r3, #30 800358a: 2207 movs r2, #7 800358c: fa02 f303 lsl.w r3, r2, r3 8003590: 43db mvns r3, r3 8003592: 4019 ands r1, r3 8003594: 683b ldr r3, [r7, #0] 8003596: 6898 ldr r0, [r3, #8] 8003598: 683b ldr r3, [r7, #0] 800359a: 681a ldr r2, [r3, #0] 800359c: 4613 mov r3, r2 800359e: 005b lsls r3, r3, #1 80035a0: 4413 add r3, r2 80035a2: 3b1e subs r3, #30 80035a4: fa00 f203 lsl.w r2, r0, r3 80035a8: 687b ldr r3, [r7, #4] 80035aa: 681b ldr r3, [r3, #0] 80035ac: 430a orrs r2, r1 80035ae: 60da str r2, [r3, #12] 80035b0: e019 b.n 80035e6 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 80035b2: 687b ldr r3, [r7, #4] 80035b4: 681b ldr r3, [r3, #0] 80035b6: 6919 ldr r1, [r3, #16] 80035b8: 683b ldr r3, [r7, #0] 80035ba: 681a ldr r2, [r3, #0] 80035bc: 4613 mov r3, r2 80035be: 005b lsls r3, r3, #1 80035c0: 4413 add r3, r2 80035c2: 2207 movs r2, #7 80035c4: fa02 f303 lsl.w r3, r2, r3 80035c8: 43db mvns r3, r3 80035ca: 4019 ands r1, r3 80035cc: 683b ldr r3, [r7, #0] 80035ce: 6898 ldr r0, [r3, #8] 80035d0: 683b ldr r3, [r7, #0] 80035d2: 681a ldr r2, [r3, #0] 80035d4: 4613 mov r3, r2 80035d6: 005b lsls r3, r3, #1 80035d8: 4413 add r3, r2 80035da: fa00 f203 lsl.w r2, r0, r3 80035de: 687b ldr r3, [r7, #4] 80035e0: 681b ldr r3, [r3, #0] 80035e2: 430a orrs r2, r1 80035e4: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80035e6: 683b ldr r3, [r7, #0] 80035e8: 681b ldr r3, [r3, #0] 80035ea: 2b10 cmp r3, #16 80035ec: d003 beq.n 80035f6 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80035ee: 683b ldr r3, [r7, #0] 80035f0: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80035f2: 2b11 cmp r3, #17 80035f4: d132 bne.n 800365c { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80035f6: 687b ldr r3, [r7, #4] 80035f8: 681b ldr r3, [r3, #0] 80035fa: 4a1d ldr r2, [pc, #116] @ (8003670 ) 80035fc: 4293 cmp r3, r2 80035fe: d125 bne.n 800364c { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8003600: 687b ldr r3, [r7, #4] 8003602: 681b ldr r3, [r3, #0] 8003604: 689b ldr r3, [r3, #8] 8003606: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800360a: 2b00 cmp r3, #0 800360c: d126 bne.n 800365c { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800360e: 687b ldr r3, [r7, #4] 8003610: 681b ldr r3, [r3, #0] 8003612: 689a ldr r2, [r3, #8] 8003614: 687b ldr r3, [r7, #4] 8003616: 681b ldr r3, [r3, #0] 8003618: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800361c: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800361e: 683b ldr r3, [r7, #0] 8003620: 681b ldr r3, [r3, #0] 8003622: 2b10 cmp r3, #16 8003624: d11a bne.n 800365c { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8003626: 4b13 ldr r3, [pc, #76] @ (8003674 ) 8003628: 681b ldr r3, [r3, #0] 800362a: 4a13 ldr r2, [pc, #76] @ (8003678 ) 800362c: fba2 2303 umull r2, r3, r2, r3 8003630: 0c9a lsrs r2, r3, #18 8003632: 4613 mov r3, r2 8003634: 009b lsls r3, r3, #2 8003636: 4413 add r3, r2 8003638: 005b lsls r3, r3, #1 800363a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800363c: e002 b.n 8003644 { wait_loop_index--; 800363e: 68bb ldr r3, [r7, #8] 8003640: 3b01 subs r3, #1 8003642: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8003644: 68bb ldr r3, [r7, #8] 8003646: 2b00 cmp r3, #0 8003648: d1f9 bne.n 800363e 800364a: e007 b.n 800365c } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800364c: 687b ldr r3, [r7, #4] 800364e: 6a9b ldr r3, [r3, #40] @ 0x28 8003650: f043 0220 orr.w r2, r3, #32 8003654: 687b ldr r3, [r7, #4] 8003656: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8003658: 2301 movs r3, #1 800365a: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800365c: 687b ldr r3, [r7, #4] 800365e: 2200 movs r2, #0 8003660: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8003664: 7bfb ldrb r3, [r7, #15] } 8003666: 4618 mov r0, r3 8003668: 3714 adds r7, #20 800366a: 46bd mov sp, r7 800366c: bc80 pop {r7} 800366e: 4770 bx lr 8003670: 40012400 .word 0x40012400 8003674: 20000004 .word 0x20000004 8003678: 431bde83 .word 0x431bde83 0800367c : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800367c: b580 push {r7, lr} 800367e: b084 sub sp, #16 8003680: af00 add r7, sp, #0 8003682: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003684: 2300 movs r3, #0 8003686: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8003688: 687b ldr r3, [r7, #4] 800368a: 681b ldr r3, [r3, #0] 800368c: 689b ldr r3, [r3, #8] 800368e: f003 0301 and.w r3, r3, #1 8003692: 2b01 cmp r3, #1 8003694: d12e bne.n 80036f4 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8003696: 687b ldr r3, [r7, #4] 8003698: 681b ldr r3, [r3, #0] 800369a: 689a ldr r2, [r3, #8] 800369c: 687b ldr r3, [r7, #4] 800369e: 681b ldr r3, [r3, #0] 80036a0: f022 0201 bic.w r2, r2, #1 80036a4: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 80036a6: f7ff fdeb bl 8003280 80036aa: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 80036ac: e01b b.n 80036e6 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80036ae: f7ff fde7 bl 8003280 80036b2: 4602 mov r2, r0 80036b4: 68fb ldr r3, [r7, #12] 80036b6: 1ad3 subs r3, r2, r3 80036b8: 2b02 cmp r3, #2 80036ba: d914 bls.n 80036e6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 80036bc: 687b ldr r3, [r7, #4] 80036be: 681b ldr r3, [r3, #0] 80036c0: 689b ldr r3, [r3, #8] 80036c2: f003 0301 and.w r3, r3, #1 80036c6: 2b01 cmp r3, #1 80036c8: d10d bne.n 80036e6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80036ca: 687b ldr r3, [r7, #4] 80036cc: 6a9b ldr r3, [r3, #40] @ 0x28 80036ce: f043 0210 orr.w r2, r3, #16 80036d2: 687b ldr r3, [r7, #4] 80036d4: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80036d6: 687b ldr r3, [r7, #4] 80036d8: 6adb ldr r3, [r3, #44] @ 0x2c 80036da: f043 0201 orr.w r2, r3, #1 80036de: 687b ldr r3, [r7, #4] 80036e0: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 80036e2: 2301 movs r3, #1 80036e4: e007 b.n 80036f6 while(ADC_IS_ENABLE(hadc) != RESET) 80036e6: 687b ldr r3, [r7, #4] 80036e8: 681b ldr r3, [r3, #0] 80036ea: 689b ldr r3, [r3, #8] 80036ec: f003 0301 and.w r3, r3, #1 80036f0: 2b01 cmp r3, #1 80036f2: d0dc beq.n 80036ae } } } /* Return HAL status */ return HAL_OK; 80036f4: 2300 movs r3, #0 } 80036f6: 4618 mov r0, r3 80036f8: 3710 adds r7, #16 80036fa: 46bd mov sp, r7 80036fc: bd80 pop {r7, pc} ... 08003700 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003700: b480 push {r7} 8003702: b085 sub sp, #20 8003704: af00 add r7, sp, #0 8003706: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003708: 687b ldr r3, [r7, #4] 800370a: f003 0307 and.w r3, r3, #7 800370e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8003710: 4b0c ldr r3, [pc, #48] @ (8003744 <__NVIC_SetPriorityGrouping+0x44>) 8003712: 68db ldr r3, [r3, #12] 8003714: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8003716: 68ba ldr r2, [r7, #8] 8003718: f64f 03ff movw r3, #63743 @ 0xf8ff 800371c: 4013 ands r3, r2 800371e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8003720: 68fb ldr r3, [r7, #12] 8003722: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8003724: 68bb ldr r3, [r7, #8] 8003726: 4313 orrs r3, r2 reg_value = (reg_value | 8003728: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800372c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003730: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8003732: 4a04 ldr r2, [pc, #16] @ (8003744 <__NVIC_SetPriorityGrouping+0x44>) 8003734: 68bb ldr r3, [r7, #8] 8003736: 60d3 str r3, [r2, #12] } 8003738: bf00 nop 800373a: 3714 adds r7, #20 800373c: 46bd mov sp, r7 800373e: bc80 pop {r7} 8003740: 4770 bx lr 8003742: bf00 nop 8003744: e000ed00 .word 0xe000ed00 08003748 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8003748: b480 push {r7} 800374a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800374c: 4b04 ldr r3, [pc, #16] @ (8003760 <__NVIC_GetPriorityGrouping+0x18>) 800374e: 68db ldr r3, [r3, #12] 8003750: 0a1b lsrs r3, r3, #8 8003752: f003 0307 and.w r3, r3, #7 } 8003756: 4618 mov r0, r3 8003758: 46bd mov sp, r7 800375a: bc80 pop {r7} 800375c: 4770 bx lr 800375e: bf00 nop 8003760: e000ed00 .word 0xe000ed00 08003764 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8003764: b480 push {r7} 8003766: b083 sub sp, #12 8003768: af00 add r7, sp, #0 800376a: 4603 mov r3, r0 800376c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800376e: f997 3007 ldrsb.w r3, [r7, #7] 8003772: 2b00 cmp r3, #0 8003774: db0b blt.n 800378e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8003776: 79fb ldrb r3, [r7, #7] 8003778: f003 021f and.w r2, r3, #31 800377c: 4906 ldr r1, [pc, #24] @ (8003798 <__NVIC_EnableIRQ+0x34>) 800377e: f997 3007 ldrsb.w r3, [r7, #7] 8003782: 095b lsrs r3, r3, #5 8003784: 2001 movs r0, #1 8003786: fa00 f202 lsl.w r2, r0, r2 800378a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 800378e: bf00 nop 8003790: 370c adds r7, #12 8003792: 46bd mov sp, r7 8003794: bc80 pop {r7} 8003796: 4770 bx lr 8003798: e000e100 .word 0xe000e100 0800379c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800379c: b480 push {r7} 800379e: b083 sub sp, #12 80037a0: af00 add r7, sp, #0 80037a2: 4603 mov r3, r0 80037a4: 6039 str r1, [r7, #0] 80037a6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80037a8: f997 3007 ldrsb.w r3, [r7, #7] 80037ac: 2b00 cmp r3, #0 80037ae: db0a blt.n 80037c6 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80037b0: 683b ldr r3, [r7, #0] 80037b2: b2da uxtb r2, r3 80037b4: 490c ldr r1, [pc, #48] @ (80037e8 <__NVIC_SetPriority+0x4c>) 80037b6: f997 3007 ldrsb.w r3, [r7, #7] 80037ba: 0112 lsls r2, r2, #4 80037bc: b2d2 uxtb r2, r2 80037be: 440b add r3, r1 80037c0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80037c4: e00a b.n 80037dc <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80037c6: 683b ldr r3, [r7, #0] 80037c8: b2da uxtb r2, r3 80037ca: 4908 ldr r1, [pc, #32] @ (80037ec <__NVIC_SetPriority+0x50>) 80037cc: 79fb ldrb r3, [r7, #7] 80037ce: f003 030f and.w r3, r3, #15 80037d2: 3b04 subs r3, #4 80037d4: 0112 lsls r2, r2, #4 80037d6: b2d2 uxtb r2, r2 80037d8: 440b add r3, r1 80037da: 761a strb r2, [r3, #24] } 80037dc: bf00 nop 80037de: 370c adds r7, #12 80037e0: 46bd mov sp, r7 80037e2: bc80 pop {r7} 80037e4: 4770 bx lr 80037e6: bf00 nop 80037e8: e000e100 .word 0xe000e100 80037ec: e000ed00 .word 0xe000ed00 080037f0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80037f0: b480 push {r7} 80037f2: b089 sub sp, #36 @ 0x24 80037f4: af00 add r7, sp, #0 80037f6: 60f8 str r0, [r7, #12] 80037f8: 60b9 str r1, [r7, #8] 80037fa: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80037fc: 68fb ldr r3, [r7, #12] 80037fe: f003 0307 and.w r3, r3, #7 8003802: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8003804: 69fb ldr r3, [r7, #28] 8003806: f1c3 0307 rsb r3, r3, #7 800380a: 2b04 cmp r3, #4 800380c: bf28 it cs 800380e: 2304 movcs r3, #4 8003810: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8003812: 69fb ldr r3, [r7, #28] 8003814: 3304 adds r3, #4 8003816: 2b06 cmp r3, #6 8003818: d902 bls.n 8003820 800381a: 69fb ldr r3, [r7, #28] 800381c: 3b03 subs r3, #3 800381e: e000 b.n 8003822 8003820: 2300 movs r3, #0 8003822: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003824: f04f 32ff mov.w r2, #4294967295 8003828: 69bb ldr r3, [r7, #24] 800382a: fa02 f303 lsl.w r3, r2, r3 800382e: 43da mvns r2, r3 8003830: 68bb ldr r3, [r7, #8] 8003832: 401a ands r2, r3 8003834: 697b ldr r3, [r7, #20] 8003836: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8003838: f04f 31ff mov.w r1, #4294967295 800383c: 697b ldr r3, [r7, #20] 800383e: fa01 f303 lsl.w r3, r1, r3 8003842: 43d9 mvns r1, r3 8003844: 687b ldr r3, [r7, #4] 8003846: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003848: 4313 orrs r3, r2 ); } 800384a: 4618 mov r0, r3 800384c: 3724 adds r7, #36 @ 0x24 800384e: 46bd mov sp, r7 8003850: bc80 pop {r7} 8003852: 4770 bx lr 08003854 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8003854: b580 push {r7, lr} 8003856: b082 sub sp, #8 8003858: af00 add r7, sp, #0 800385a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800385c: 687b ldr r3, [r7, #4] 800385e: 3b01 subs r3, #1 8003860: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8003864: d301 bcc.n 800386a { return (1UL); /* Reload value impossible */ 8003866: 2301 movs r3, #1 8003868: e00f b.n 800388a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800386a: 4a0a ldr r2, [pc, #40] @ (8003894 ) 800386c: 687b ldr r3, [r7, #4] 800386e: 3b01 subs r3, #1 8003870: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8003872: 210f movs r1, #15 8003874: f04f 30ff mov.w r0, #4294967295 8003878: f7ff ff90 bl 800379c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800387c: 4b05 ldr r3, [pc, #20] @ (8003894 ) 800387e: 2200 movs r2, #0 8003880: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8003882: 4b04 ldr r3, [pc, #16] @ (8003894 ) 8003884: 2207 movs r2, #7 8003886: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003888: 2300 movs r3, #0 } 800388a: 4618 mov r0, r3 800388c: 3708 adds r7, #8 800388e: 46bd mov sp, r7 8003890: bd80 pop {r7, pc} 8003892: bf00 nop 8003894: e000e010 .word 0xe000e010 08003898 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003898: b580 push {r7, lr} 800389a: b082 sub sp, #8 800389c: af00 add r7, sp, #0 800389e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80038a0: 6878 ldr r0, [r7, #4] 80038a2: f7ff ff2d bl 8003700 <__NVIC_SetPriorityGrouping> } 80038a6: bf00 nop 80038a8: 3708 adds r7, #8 80038aa: 46bd mov sp, r7 80038ac: bd80 pop {r7, pc} 080038ae : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80038ae: b580 push {r7, lr} 80038b0: b086 sub sp, #24 80038b2: af00 add r7, sp, #0 80038b4: 4603 mov r3, r0 80038b6: 60b9 str r1, [r7, #8] 80038b8: 607a str r2, [r7, #4] 80038ba: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80038bc: 2300 movs r3, #0 80038be: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80038c0: f7ff ff42 bl 8003748 <__NVIC_GetPriorityGrouping> 80038c4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80038c6: 687a ldr r2, [r7, #4] 80038c8: 68b9 ldr r1, [r7, #8] 80038ca: 6978 ldr r0, [r7, #20] 80038cc: f7ff ff90 bl 80037f0 80038d0: 4602 mov r2, r0 80038d2: f997 300f ldrsb.w r3, [r7, #15] 80038d6: 4611 mov r1, r2 80038d8: 4618 mov r0, r3 80038da: f7ff ff5f bl 800379c <__NVIC_SetPriority> } 80038de: bf00 nop 80038e0: 3718 adds r7, #24 80038e2: 46bd mov sp, r7 80038e4: bd80 pop {r7, pc} 080038e6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80038e6: b580 push {r7, lr} 80038e8: b082 sub sp, #8 80038ea: af00 add r7, sp, #0 80038ec: 4603 mov r3, r0 80038ee: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80038f0: f997 3007 ldrsb.w r3, [r7, #7] 80038f4: 4618 mov r0, r3 80038f6: f7ff ff35 bl 8003764 <__NVIC_EnableIRQ> } 80038fa: bf00 nop 80038fc: 3708 adds r7, #8 80038fe: 46bd mov sp, r7 8003900: bd80 pop {r7, pc} 08003902 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8003902: b580 push {r7, lr} 8003904: b082 sub sp, #8 8003906: af00 add r7, sp, #0 8003908: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800390a: 6878 ldr r0, [r7, #4] 800390c: f7ff ffa2 bl 8003854 8003910: 4603 mov r3, r0 } 8003912: 4618 mov r0, r3 8003914: 3708 adds r7, #8 8003916: 46bd mov sp, r7 8003918: bd80 pop {r7, pc} 0800391a : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800391a: b480 push {r7} 800391c: b085 sub sp, #20 800391e: af00 add r7, sp, #0 8003920: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003922: 2300 movs r3, #0 8003924: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8003926: 687b ldr r3, [r7, #4] 8003928: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800392c: b2db uxtb r3, r3 800392e: 2b02 cmp r3, #2 8003930: d008 beq.n 8003944 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003932: 687b ldr r3, [r7, #4] 8003934: 2204 movs r2, #4 8003936: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003938: 687b ldr r3, [r7, #4] 800393a: 2200 movs r2, #0 800393c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8003940: 2301 movs r3, #1 8003942: e020 b.n 8003986 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003944: 687b ldr r3, [r7, #4] 8003946: 681b ldr r3, [r3, #0] 8003948: 681a ldr r2, [r3, #0] 800394a: 687b ldr r3, [r7, #4] 800394c: 681b ldr r3, [r3, #0] 800394e: f022 020e bic.w r2, r2, #14 8003952: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8003954: 687b ldr r3, [r7, #4] 8003956: 681b ldr r3, [r3, #0] 8003958: 681a ldr r2, [r3, #0] 800395a: 687b ldr r3, [r7, #4] 800395c: 681b ldr r3, [r3, #0] 800395e: f022 0201 bic.w r2, r2, #1 8003962: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8003964: 687b ldr r3, [r7, #4] 8003966: 6c1a ldr r2, [r3, #64] @ 0x40 8003968: 687b ldr r3, [r7, #4] 800396a: 6bdb ldr r3, [r3, #60] @ 0x3c 800396c: 2101 movs r1, #1 800396e: fa01 f202 lsl.w r2, r1, r2 8003972: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003974: 687b ldr r3, [r7, #4] 8003976: 2201 movs r2, #1 8003978: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800397c: 687b ldr r3, [r7, #4] 800397e: 2200 movs r2, #0 8003980: f883 2020 strb.w r2, [r3, #32] return status; 8003984: 7bfb ldrb r3, [r7, #15] } 8003986: 4618 mov r0, r3 8003988: 3714 adds r7, #20 800398a: 46bd mov sp, r7 800398c: bc80 pop {r7} 800398e: 4770 bx lr 08003990 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003990: b580 push {r7, lr} 8003992: b084 sub sp, #16 8003994: af00 add r7, sp, #0 8003996: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003998: 2300 movs r3, #0 800399a: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800399c: 687b ldr r3, [r7, #4] 800399e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80039a2: b2db uxtb r3, r3 80039a4: 2b02 cmp r3, #2 80039a6: d005 beq.n 80039b4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80039a8: 687b ldr r3, [r7, #4] 80039aa: 2204 movs r2, #4 80039ac: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 80039ae: 2301 movs r3, #1 80039b0: 73fb strb r3, [r7, #15] 80039b2: e051 b.n 8003a58 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80039b4: 687b ldr r3, [r7, #4] 80039b6: 681b ldr r3, [r3, #0] 80039b8: 681a ldr r2, [r3, #0] 80039ba: 687b ldr r3, [r7, #4] 80039bc: 681b ldr r3, [r3, #0] 80039be: f022 020e bic.w r2, r2, #14 80039c2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80039c4: 687b ldr r3, [r7, #4] 80039c6: 681b ldr r3, [r3, #0] 80039c8: 681a ldr r2, [r3, #0] 80039ca: 687b ldr r3, [r7, #4] 80039cc: 681b ldr r3, [r3, #0] 80039ce: f022 0201 bic.w r2, r2, #1 80039d2: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80039d4: 687b ldr r3, [r7, #4] 80039d6: 681b ldr r3, [r3, #0] 80039d8: 4a22 ldr r2, [pc, #136] @ (8003a64 ) 80039da: 4293 cmp r3, r2 80039dc: d029 beq.n 8003a32 80039de: 687b ldr r3, [r7, #4] 80039e0: 681b ldr r3, [r3, #0] 80039e2: 4a21 ldr r2, [pc, #132] @ (8003a68 ) 80039e4: 4293 cmp r3, r2 80039e6: d022 beq.n 8003a2e 80039e8: 687b ldr r3, [r7, #4] 80039ea: 681b ldr r3, [r3, #0] 80039ec: 4a1f ldr r2, [pc, #124] @ (8003a6c ) 80039ee: 4293 cmp r3, r2 80039f0: d01a beq.n 8003a28 80039f2: 687b ldr r3, [r7, #4] 80039f4: 681b ldr r3, [r3, #0] 80039f6: 4a1e ldr r2, [pc, #120] @ (8003a70 ) 80039f8: 4293 cmp r3, r2 80039fa: d012 beq.n 8003a22 80039fc: 687b ldr r3, [r7, #4] 80039fe: 681b ldr r3, [r3, #0] 8003a00: 4a1c ldr r2, [pc, #112] @ (8003a74 ) 8003a02: 4293 cmp r3, r2 8003a04: d00a beq.n 8003a1c 8003a06: 687b ldr r3, [r7, #4] 8003a08: 681b ldr r3, [r3, #0] 8003a0a: 4a1b ldr r2, [pc, #108] @ (8003a78 ) 8003a0c: 4293 cmp r3, r2 8003a0e: d102 bne.n 8003a16 8003a10: f44f 1380 mov.w r3, #1048576 @ 0x100000 8003a14: e00e b.n 8003a34