: /** * @brief The application entry point. * @retval int */ int main(void) { 8001a70: b580 push {r7, lr} 8001a72: b08a sub sp, #40 @ 0x28 8001a74: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ uint8_t tempString[15] = {0}; 8001a76: 463b mov r3, r7 8001a78: 2200 movs r2, #0 8001a7a: 601a str r2, [r3, #0] 8001a7c: 605a str r2, [r3, #4] 8001a7e: 609a str r2, [r3, #8] 8001a80: f8c3 200b str.w r2, [r3, #11] uint8_t i; uint8_t mux_connection = 0; 8001a84: 2300 movs r3, #0 8001a86: f887 3027 strb.w r3, [r7, #39] @ 0x27 // Variables for timing uint32_t previous_millis_green = 0; 8001a8a: 2300 movs r3, #0 8001a8c: 623b str r3, [r7, #32] uint32_t previous_millis_red = 0; 8001a8e: 2300 movs r3, #0 8001a90: 61fb str r3, [r7, #28] /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001a92: f000 fcf5 bl 8002480 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001a96: f000 f935 bl 8001d04 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001a9a: f7ff fe81 bl 80017a0 MX_ADC1_Init(); 8001a9e: f7ff fabf bl 8001020 MX_ADC2_Init(); 8001aa2: f7ff fafb bl 800109c MX_I2C1_Init(); 8001aa6: f7ff ff1b bl 80018e0 MX_I2C2_Init(); 8001aaa: f7ff ff47 bl 800193c MX_USART1_UART_Init(); 8001aae: f000 fc43 bl 8002338 MX_TIM3_Init(); 8001ab2: f000 fbcd bl 8002250 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim3); 8001ab6: 4889 ldr r0, [pc, #548] @ (8001cdc ) 8001ab8: f003 f82e bl 8004b18 TempSensor_Init(&hadc1); HAL_ADCEx_Calibration_Start(&hadc1); HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2); // Internal Temperature conversion */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off 8001abc: 2201 movs r2, #1 8001abe: 2110 movs r1, #16 8001ac0: 4887 ldr r0, [pc, #540] @ (8001ce0 ) 8001ac2: f001 faac bl 800301e HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off 8001ac6: 2201 movs r2, #1 8001ac8: 2120 movs r1, #32 8001aca: 4885 ldr r0, [pc, #532] @ (8001ce0 ) 8001acc: f001 faa7 bl 800301e digital_outputs_init(); 8001ad0: f7ff fe24 bl 800171c rs485_init(); 8001ad4: f000 fa5c bl 8001f90 ADS1015_Init(); // Initializes pH Measurement 8001ad8: f7ff fbd0 bl 800127c AD5934_Init(); // Initializes CE and RTD Measurement 8001adc: f7fe fec2 bl 8000864 */ while (1) { AD5934_Process_System(); 8001ae0: f7fe ffda bl 8000a98 ADS1015_Process_System(); 8001ae4: f7ff fc28 bl 8001338 current_millis = g_ms_counter; 8001ae8: 4b7e ldr r3, [pc, #504] @ (8001ce4 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 61bb str r3, [r7, #24] if((current_millis % 100) == 0) // Send data each 50ms 8001aee: 69ba ldr r2, [r7, #24] 8001af0: 4b7d ldr r3, [pc, #500] @ (8001ce8 ) 8001af2: fba3 1302 umull r1, r3, r3, r2 8001af6: 095b lsrs r3, r3, #5 8001af8: 2164 movs r1, #100 @ 0x64 8001afa: fb01 f303 mul.w r3, r1, r3 8001afe: 1ad3 subs r3, r2, r3 8001b00: 2b00 cmp r3, #0 8001b02: f040 80dc bne.w 8001cbe { if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms 8001b06: 4b79 ldr r3, [pc, #484] @ (8001cec ) 8001b08: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001b0c: 2b00 cmp r3, #0 8001b0e: d034 beq.n 8001b7a { if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND 8001b10: 2180 movs r1, #128 @ 0x80 8001b12: 4877 ldr r0, [pc, #476] @ (8001cf0 ) 8001b14: f001 fa6c bl 8002ff0 8001b18: 4603 mov r3, r0 8001b1a: 2b01 cmp r3, #1 8001b1c: d103 bne.n 8001b26 mux_connection = AD5934_CH_REF100R_LOW_GAIN; // 100 Ohms Reference Resistor 8001b1e: 2300 movs r3, #0 8001b20: f887 3027 strb.w r3, [r7, #39] @ 0x27 8001b24: e002 b.n 8001b2c else mux_connection = AD5934_CH_REF1K_MID_GAIN; // 1K Reference Resistor 8001b26: 2304 movs r3, #4 8001b28: f887 3027 strb.w r3, [r7, #39] @ 0x27 uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, mux_connection); 8001b2c: 4b6f ldr r3, [pc, #444] @ (8001cec ) 8001b2e: 6b9b ldr r3, [r3, #56] @ 0x38 8001b30: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 8001b34: 4611 mov r1, r2 8001b36: 4618 mov r0, r3 8001b38: f7fe ff20 bl 800097c 8001b3c: 4603 mov r3, r0 8001b3e: f5c3 5380 rsb r3, r3, #4096 @ 0x1000 8001b42: 82fb strh r3, [r7, #22] intToStr(reference_final, tempString); 8001b44: f9b7 3016 ldrsh.w r3, [r7, #22] 8001b48: 463a mov r2, r7 8001b4a: 4611 mov r1, r2 8001b4c: 4618 mov r0, r3 8001b4e: f000 f929 bl 8001da4 // float ref_final = g_ref_filter.filtered_value; //FloatToString(tempString, ref_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001b52: 463b mov r3, r7 8001b54: 4618 mov r0, r3 8001b56: f7fe faf9 bl 800014c 8001b5a: 4603 mov r3, r0 8001b5c: b29a uxth r2, r3 8001b5e: 463b mov r3, r7 8001b60: 4611 mov r1, r2 8001b62: 4618 mov r0, r3 8001b64: f000 fa40 bl 8001fe8 rs485_send_broadcast(newline, (strlen((uint8_t*)newline))); 8001b68: 4862 ldr r0, [pc, #392] @ (8001cf4 ) 8001b6a: f7fe faef bl 800014c 8001b6e: 4603 mov r3, r0 8001b70: b29b uxth r3, r3 8001b72: 4619 mov r1, r3 8001b74: 485f ldr r0, [pc, #380] @ (8001cf4 ) 8001b76: f000 fa37 bl 8001fe8 } if (g_ec_filter.value_valid) // EC 8001b7a: 4b5f ldr r3, [pc, #380] @ (8001cf8 ) 8001b7c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001b80: 2b00 cmp r3, #0 8001b82: d032 beq.n 8001bea { if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // Hardware Setup: Gain Selection (PA6) 8001b84: 2140 movs r1, #64 @ 0x40 8001b86: 485a ldr r0, [pc, #360] @ (8001cf0 ) 8001b88: f001 fa32 bl 8002ff0 8001b8c: 4603 mov r3, r0 8001b8e: 2b01 cmp r3, #1 8001b90: d103 bne.n 8001b9a mux_connection = AD5934_CH_EC_HIGH_GAIN; // 5mS 8001b92: 230e movs r3, #14 8001b94: f887 3027 strb.w r3, [r7, #39] @ 0x27 8001b98: e002 b.n 8001ba0 else mux_connection = AD5934_CH_EC_MID_GAIN; // 10mS 8001b9a: 230d movs r3, #13 8001b9c: f887 3027 strb.w r3, [r7, #39] @ 0x27 uint16_t ec_final = AD5934_Compress_To_IntScale(g_ec_filter.filtered_value, mux_connection); 8001ba0: 4b55 ldr r3, [pc, #340] @ (8001cf8 ) 8001ba2: 6b9b ldr r3, [r3, #56] @ 0x38 8001ba4: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 8001ba8: 4611 mov r1, r2 8001baa: 4618 mov r0, r3 8001bac: f7fe fee6 bl 800097c 8001bb0: 4603 mov r3, r0 8001bb2: 82bb strh r3, [r7, #20] intToStr(ec_final, tempString); 8001bb4: f9b7 3014 ldrsh.w r3, [r7, #20] 8001bb8: 463a mov r2, r7 8001bba: 4611 mov r1, r2 8001bbc: 4618 mov r0, r3 8001bbe: f000 f8f1 bl 8001da4 // float ec_final = g_ec_filter.filtered_value; // FloatToString(tempString, ec_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001bc2: 463b mov r3, r7 8001bc4: 4618 mov r0, r3 8001bc6: f7fe fac1 bl 800014c 8001bca: 4603 mov r3, r0 8001bcc: b29a uxth r2, r3 8001bce: 463b mov r3, r7 8001bd0: 4611 mov r1, r2 8001bd2: 4618 mov r0, r3 8001bd4: f000 fa08 bl 8001fe8 rs485_send_broadcast(newline, (strlen((uint8_t*)newline))); 8001bd8: 4846 ldr r0, [pc, #280] @ (8001cf4 ) 8001bda: f7fe fab7 bl 800014c 8001bde: 4603 mov r3, r0 8001be0: b29b uxth r3, r3 8001be2: 4619 mov r1, r3 8001be4: 4843 ldr r0, [pc, #268] @ (8001cf4 ) 8001be6: f000 f9ff bl 8001fe8 } if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C 8001bea: 4b44 ldr r3, [pc, #272] @ (8001cfc ) 8001bec: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001bf0: 2b00 cmp r3, #0 8001bf2: d034 beq.n 8001c5e { if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND 8001bf4: 2180 movs r1, #128 @ 0x80 8001bf6: 483e ldr r0, [pc, #248] @ (8001cf0 ) 8001bf8: f001 f9fa bl 8002ff0 8001bfc: 4603 mov r3, r0 8001bfe: 2b01 cmp r3, #1 8001c00: d103 bne.n 8001c0a mux_connection = AD5934_CH_RTD_LOW_GAIN; //PT100 8001c02: 2309 movs r3, #9 8001c04: f887 3027 strb.w r3, [r7, #39] @ 0x27 8001c08: e002 b.n 8001c10 else mux_connection = AD5934_CH_RTD_MID_GAIN; //PT1000 8001c0a: 230a movs r3, #10 8001c0c: f887 3027 strb.w r3, [r7, #39] @ 0x27 uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_rtd_filter.filtered_value, mux_connection); 8001c10: 4b3a ldr r3, [pc, #232] @ (8001cfc ) 8001c12: 6b9b ldr r3, [r3, #56] @ 0x38 8001c14: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 8001c18: 4611 mov r1, r2 8001c1a: 4618 mov r0, r3 8001c1c: f7fe feae bl 800097c 8001c20: 4603 mov r3, r0 8001c22: f5c3 5380 rsb r3, r3, #4096 @ 0x1000 8001c26: 827b strh r3, [r7, #18] intToStr(rtd_final, tempString); 8001c28: f9b7 3012 ldrsh.w r3, [r7, #18] 8001c2c: 463a mov r2, r7 8001c2e: 4611 mov r1, r2 8001c30: 4618 mov r0, r3 8001c32: f000 f8b7 bl 8001da4 //float rtd_final = g_rtd_filter.filtered_value; //FloatToString(tempString, rtd_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001c36: 463b mov r3, r7 8001c38: 4618 mov r0, r3 8001c3a: f7fe fa87 bl 800014c 8001c3e: 4603 mov r3, r0 8001c40: b29a uxth r2, r3 8001c42: 463b mov r3, r7 8001c44: 4611 mov r1, r2 8001c46: 4618 mov r0, r3 8001c48: f000 f9ce bl 8001fe8 rs485_send_broadcast(newline, (strlen((uint8_t*)newline))); 8001c4c: 4829 ldr r0, [pc, #164] @ (8001cf4 ) 8001c4e: f7fe fa7d bl 800014c 8001c52: 4603 mov r3, r0 8001c54: b29b uxth r3, r3 8001c56: 4619 mov r1, r3 8001c58: 4826 ldr r0, [pc, #152] @ (8001cf4 ) 8001c5a: f000 f9c5 bl 8001fe8 } if (g_ph_filter.value_valid) // pH 8001c5e: 4b28 ldr r3, [pc, #160] @ (8001d00 ) 8001c60: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001c64: 2b00 cmp r3, #0 8001c66: d021 beq.n 8001cac { uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value); 8001c68: 4b25 ldr r3, [pc, #148] @ (8001d00 ) 8001c6a: 6b9b ldr r3, [r3, #56] @ 0x38 8001c6c: 4618 mov r0, r3 8001c6e: f7ff fb1f bl 80012b0 8001c72: 4603 mov r3, r0 8001c74: 823b strh r3, [r7, #16] intToStr(ph_final, tempString); 8001c76: f9b7 3010 ldrsh.w r3, [r7, #16] 8001c7a: 463a mov r2, r7 8001c7c: 4611 mov r1, r2 8001c7e: 4618 mov r0, r3 8001c80: f000 f890 bl 8001da4 //float ph_final = g_ph_filter.filtered_value; //FloatToString(tempString, ph_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001c84: 463b mov r3, r7 8001c86: 4618 mov r0, r3 8001c88: f7fe fa60 bl 800014c 8001c8c: 4603 mov r3, r0 8001c8e: b29a uxth r2, r3 8001c90: 463b mov r3, r7 8001c92: 4611 mov r1, r2 8001c94: 4618 mov r0, r3 8001c96: f000 f9a7 bl 8001fe8 rs485_send_broadcast(newline, (strlen((uint8_t*)newline))); 8001c9a: 4816 ldr r0, [pc, #88] @ (8001cf4 ) 8001c9c: f7fe fa56 bl 800014c 8001ca0: 4603 mov r3, r0 8001ca2: b29b uxth r3, r3 8001ca4: 4619 mov r1, r3 8001ca6: 4813 ldr r0, [pc, #76] @ (8001cf4 ) 8001ca8: f000 f99e bl 8001fe8 } rs485_send_broadcast(newline, (strlen((uint8_t*)newline))); 8001cac: 4811 ldr r0, [pc, #68] @ (8001cf4 ) 8001cae: f7fe fa4d bl 800014c 8001cb2: 4603 mov r3, r0 8001cb4: b29b uxth r3, r3 8001cb6: 4619 mov r1, r3 8001cb8: 480e ldr r0, [pc, #56] @ (8001cf4 ) 8001cba: f000 f995 bl 8001fe8 } // Piscar LED verde em PB4 a cada 1 segundo if ((current_millis - previous_millis_green) >= 1000) 8001cbe: 69ba ldr r2, [r7, #24] 8001cc0: 6a3b ldr r3, [r7, #32] 8001cc2: 1ad3 subs r3, r2, r3 8001cc4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001cc8: f4ff af0a bcc.w 8001ae0 { previous_millis_green = current_millis; 8001ccc: 69bb ldr r3, [r7, #24] 8001cce: 623b str r3, [r7, #32] HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4); 8001cd0: 2110 movs r1, #16 8001cd2: 4803 ldr r0, [pc, #12] @ (8001ce0 ) 8001cd4: f001 f9bb bl 800304e AD5934_Process_System(); 8001cd8: e702 b.n 8001ae0 8001cda: bf00 nop 8001cdc: 20000308 .word 0x20000308 8001ce0: 40010c00 .word 0x40010c00 8001ce4: 20000084 .word 0x20000084 8001ce8: 51eb851f .word 0x51eb851f 8001cec: 2000010c .word 0x2000010c 8001cf0: 40010800 .word 0x40010800 8001cf4: 20000004 .word 0x20000004 8001cf8: 200000cc .word 0x200000cc 8001cfc: 2000008c .word 0x2000008c 8001d00: 200001c0 .word 0x200001c0 08001d04 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001d04: b580 push {r7, lr} 8001d06: b094 sub sp, #80 @ 0x50 8001d08: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001d0a: f107 0328 add.w r3, r7, #40 @ 0x28 8001d0e: 2228 movs r2, #40 @ 0x28 8001d10: 2100 movs r1, #0 8001d12: 4618 mov r0, r3 8001d14: f004 f8b8 bl 8005e88 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001d18: f107 0314 add.w r3, r7, #20 8001d1c: 2200 movs r2, #0 8001d1e: 601a str r2, [r3, #0] 8001d20: 605a str r2, [r3, #4] 8001d22: 609a str r2, [r3, #8] 8001d24: 60da str r2, [r3, #12] 8001d26: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001d28: 1d3b adds r3, r7, #4 8001d2a: 2200 movs r2, #0 8001d2c: 601a str r2, [r3, #0] 8001d2e: 605a str r2, [r3, #4] 8001d30: 609a str r2, [r3, #8] 8001d32: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001d34: 2301 movs r3, #1 8001d36: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001d38: f44f 3380 mov.w r3, #65536 @ 0x10000 8001d3c: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8001d3e: 2300 movs r3, #0 8001d40: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001d42: f107 0328 add.w r3, r7, #40 @ 0x28 8001d46: 4618 mov r0, r3 8001d48: f002 f9ce bl 80040e8 8001d4c: 4603 mov r3, r0 8001d4e: 2b00 cmp r3, #0 8001d50: d001 beq.n 8001d56 { Error_Handler(); 8001d52: f000 f90b bl 8001f6c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001d56: 230f movs r3, #15 8001d58: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8001d5a: 2301 movs r3, #1 8001d5c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001d5e: 2300 movs r3, #0 8001d60: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001d62: 2300 movs r3, #0 8001d64: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001d66: 2300 movs r3, #0 8001d68: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8001d6a: f107 0314 add.w r3, r7, #20 8001d6e: 2100 movs r1, #0 8001d70: 4618 mov r0, r3 8001d72: f002 fc3b bl 80045ec 8001d76: 4603 mov r3, r0 8001d78: 2b00 cmp r3, #0 8001d7a: d001 beq.n 8001d80 { Error_Handler(); 8001d7c: f000 f8f6 bl 8001f6c } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8001d80: 2302 movs r3, #2 8001d82: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 8001d84: f44f 4340 mov.w r3, #49152 @ 0xc000 8001d88: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001d8a: 1d3b adds r3, r7, #4 8001d8c: 4618 mov r0, r3 8001d8e: f002 fdbd bl 800490c 8001d92: 4603 mov r3, r0 8001d94: 2b00 cmp r3, #0 8001d96: d001 beq.n 8001d9c { Error_Handler(); 8001d98: f000 f8e8 bl 8001f6c } } 8001d9c: bf00 nop 8001d9e: 3750 adds r7, #80 @ 0x50 8001da0: 46bd mov sp, r7 8001da2: bd80 pop {r7, pc} 08001da4 : } void intToStr(int16_t N, uint8_t *str) { 8001da4: b480 push {r7} 8001da6: b087 sub sp, #28 8001da8: af00 add r7, sp, #0 8001daa: 4603 mov r3, r0 8001dac: 6039 str r1, [r7, #0] 8001dae: 80fb strh r3, [r7, #6] int16_t i = 0; 8001db0: 2300 movs r3, #0 8001db2: 82fb strh r3, [r7, #22] int16_t sign = N; 8001db4: 88fb ldrh r3, [r7, #6] 8001db6: 823b strh r3, [r7, #16] uint8_t max_len = 15; // Tamanho máximo do buffer 8001db8: 230f movs r3, #15 8001dba: 73fb strb r3, [r7, #15] uint8_t width = 4; // mínimo 4 caracteres 8001dbc: 2304 movs r3, #4 8001dbe: 757b strb r3, [r7, #21] // Trata o caso do número zero isoladamente if (N == 0) 8001dc0: f9b7 3006 ldrsh.w r3, [r7, #6] 8001dc4: 2b00 cmp r3, #0 8001dc6: d127 bne.n 8001e18 { // Preenche com zeros à esquerda até atingir a largura desejada while (width > 1 && i < (max_len - 1)) 8001dc8: e00c b.n 8001de4 { str[i++] = '0'; 8001dca: f9b7 2016 ldrsh.w r2, [r7, #22] 8001dce: b293 uxth r3, r2 8001dd0: 3301 adds r3, #1 8001dd2: b29b uxth r3, r3 8001dd4: 82fb strh r3, [r7, #22] 8001dd6: 683b ldr r3, [r7, #0] 8001dd8: 4413 add r3, r2 8001dda: 2230 movs r2, #48 @ 0x30 8001ddc: 701a strb r2, [r3, #0] width--; 8001dde: 7d7b ldrb r3, [r7, #21] 8001de0: 3b01 subs r3, #1 8001de2: 757b strb r3, [r7, #21] while (width > 1 && i < (max_len - 1)) 8001de4: 7d7b ldrb r3, [r7, #21] 8001de6: 2b01 cmp r3, #1 8001de8: d905 bls.n 8001df6 8001dea: f9b7 2016 ldrsh.w r2, [r7, #22] 8001dee: 7bfb ldrb r3, [r7, #15] 8001df0: 3b01 subs r3, #1 8001df2: 429a cmp r2, r3 8001df4: dbe9 blt.n 8001dca } str[i++] = '0'; 8001df6: f9b7 2016 ldrsh.w r2, [r7, #22] 8001dfa: b293 uxth r3, r2 8001dfc: 3301 adds r3, #1 8001dfe: b29b uxth r3, r3 8001e00: 82fb strh r3, [r7, #22] 8001e02: 683b ldr r3, [r7, #0] 8001e04: 4413 add r3, r2 8001e06: 2230 movs r2, #48 @ 0x30 8001e08: 701a strb r2, [r3, #0] str[i] = '\0'; 8001e0a: f9b7 3016 ldrsh.w r3, [r7, #22] 8001e0e: 683a ldr r2, [r7, #0] 8001e10: 4413 add r3, r2 8001e12: 2200 movs r2, #0 8001e14: 701a strb r2, [r3, #0] return; 8001e16: e08a b.n 8001f2e } if (N < 0) 8001e18: f9b7 3006 ldrsh.w r3, [r7, #6] 8001e1c: 2b00 cmp r3, #0 8001e1e: da2d bge.n 8001e7c N = -N; 8001e20: 88fb ldrh r3, [r7, #6] 8001e22: 425b negs r3, r3 8001e24: b29b uxth r3, r3 8001e26: 80fb strh r3, [r7, #6] // Extração dos dígitos while (N > 0) 8001e28: e028 b.n 8001e7c { if (i >= (max_len - 1)) 8001e2a: f9b7 2016 ldrsh.w r2, [r7, #22] 8001e2e: 7bfb ldrb r3, [r7, #15] 8001e30: 3b01 subs r3, #1 8001e32: 429a cmp r2, r3 8001e34: da27 bge.n 8001e86 break; // Proteção de estouro str[i++] = (N % 10) + '0'; 8001e36: f9b7 2006 ldrsh.w r2, [r7, #6] 8001e3a: 4b3f ldr r3, [pc, #252] @ (8001f38 ) 8001e3c: fb83 1302 smull r1, r3, r3, r2 8001e40: 1099 asrs r1, r3, #2 8001e42: 17d3 asrs r3, r2, #31 8001e44: 1ac9 subs r1, r1, r3 8001e46: 460b mov r3, r1 8001e48: 009b lsls r3, r3, #2 8001e4a: 440b add r3, r1 8001e4c: 005b lsls r3, r3, #1 8001e4e: 1ad3 subs r3, r2, r3 8001e50: b21b sxth r3, r3 8001e52: b2da uxtb r2, r3 8001e54: f9b7 1016 ldrsh.w r1, [r7, #22] 8001e58: b28b uxth r3, r1 8001e5a: 3301 adds r3, #1 8001e5c: b29b uxth r3, r3 8001e5e: 82fb strh r3, [r7, #22] 8001e60: 683b ldr r3, [r7, #0] 8001e62: 440b add r3, r1 8001e64: 3230 adds r2, #48 @ 0x30 8001e66: b2d2 uxtb r2, r2 8001e68: 701a strb r2, [r3, #0] N /= 10; 8001e6a: f9b7 3006 ldrsh.w r3, [r7, #6] 8001e6e: 4a32 ldr r2, [pc, #200] @ (8001f38 ) 8001e70: fb82 1203 smull r1, r2, r2, r3 8001e74: 1092 asrs r2, r2, #2 8001e76: 17db asrs r3, r3, #31 8001e78: 1ad3 subs r3, r2, r3 8001e7a: 80fb strh r3, [r7, #6] while (N > 0) 8001e7c: f9b7 3006 ldrsh.w r3, [r7, #6] 8001e80: 2b00 cmp r3, #0 8001e82: dcd2 bgt.n 8001e2a 8001e84: e000 b.n 8001e88 break; // Proteção de estouro 8001e86: bf00 nop } // Adiciona o sinal de menos se necessário if (sign < 0) 8001e88: f9b7 3010 ldrsh.w r3, [r7, #16] 8001e8c: 2b00 cmp r3, #0 8001e8e: da1a bge.n 8001ec6 { if (i < (max_len - 1)) 8001e90: f9b7 2016 ldrsh.w r2, [r7, #22] 8001e94: 7bfb ldrb r3, [r7, #15] 8001e96: 3b01 subs r3, #1 8001e98: 429a cmp r2, r3 8001e9a: da14 bge.n 8001ec6 str[i++] = '-'; 8001e9c: f9b7 2016 ldrsh.w r2, [r7, #22] 8001ea0: b293 uxth r3, r2 8001ea2: 3301 adds r3, #1 8001ea4: b29b uxth r3, r3 8001ea6: 82fb strh r3, [r7, #22] 8001ea8: 683b ldr r3, [r7, #0] 8001eaa: 4413 add r3, r2 8001eac: 222d movs r2, #45 @ 0x2d 8001eae: 701a strb r2, [r3, #0] } // Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal) while (i < width && i < (max_len - 1)) 8001eb0: e009 b.n 8001ec6 { str[i++] = '0'; 8001eb2: f9b7 2016 ldrsh.w r2, [r7, #22] 8001eb6: b293 uxth r3, r2 8001eb8: 3301 adds r3, #1 8001eba: b29b uxth r3, r3 8001ebc: 82fb strh r3, [r7, #22] 8001ebe: 683b ldr r3, [r7, #0] 8001ec0: 4413 add r3, r2 8001ec2: 2230 movs r2, #48 @ 0x30 8001ec4: 701a strb r2, [r3, #0] while (i < width && i < (max_len - 1)) 8001ec6: f9b7 2016 ldrsh.w r2, [r7, #22] 8001eca: 7d7b ldrb r3, [r7, #21] 8001ecc: 429a cmp r2, r3 8001ece: da05 bge.n 8001edc 8001ed0: f9b7 2016 ldrsh.w r2, [r7, #22] 8001ed4: 7bfb ldrb r3, [r7, #15] 8001ed6: 3b01 subs r3, #1 8001ed8: 429a cmp r2, r3 8001eda: dbea blt.n 8001eb2 } str[i] = '\0'; 8001edc: f9b7 3016 ldrsh.w r3, [r7, #22] 8001ee0: 683a ldr r2, [r7, #0] 8001ee2: 4413 add r3, r2 8001ee4: 2200 movs r2, #0 8001ee6: 701a strb r2, [r3, #0] // Inverte a string para colocar na ordem correta for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8001ee8: 2300 movs r3, #0 8001eea: 753b strb r3, [r7, #20] 8001eec: 8afb ldrh r3, [r7, #22] 8001eee: b2db uxtb r3, r3 8001ef0: 3b01 subs r3, #1 8001ef2: 74fb strb r3, [r7, #19] 8001ef4: e017 b.n 8001f26 { uint8_t temp = str[j]; 8001ef6: 7d3b ldrb r3, [r7, #20] 8001ef8: 683a ldr r2, [r7, #0] 8001efa: 4413 add r3, r2 8001efc: 781b ldrb r3, [r3, #0] 8001efe: 73bb strb r3, [r7, #14] str[j] = str[k]; 8001f00: 7cfb ldrb r3, [r7, #19] 8001f02: 683a ldr r2, [r7, #0] 8001f04: 441a add r2, r3 8001f06: 7d3b ldrb r3, [r7, #20] 8001f08: 6839 ldr r1, [r7, #0] 8001f0a: 440b add r3, r1 8001f0c: 7812 ldrb r2, [r2, #0] 8001f0e: 701a strb r2, [r3, #0] str[k] = temp; 8001f10: 7cfb ldrb r3, [r7, #19] 8001f12: 683a ldr r2, [r7, #0] 8001f14: 4413 add r3, r2 8001f16: 7bba ldrb r2, [r7, #14] 8001f18: 701a strb r2, [r3, #0] for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8001f1a: 7d3b ldrb r3, [r7, #20] 8001f1c: 3301 adds r3, #1 8001f1e: 753b strb r3, [r7, #20] 8001f20: 7cfb ldrb r3, [r7, #19] 8001f22: 3b01 subs r3, #1 8001f24: 74fb strb r3, [r7, #19] 8001f26: 7d3a ldrb r2, [r7, #20] 8001f28: 7cfb ldrb r3, [r7, #19] 8001f2a: 429a cmp r2, r3 8001f2c: d3e3 bcc.n 8001ef6 } } 8001f2e: 371c adds r7, #28 8001f30: 46bd mov sp, r7 8001f32: bc80 pop {r7} 8001f34: 4770 bx lr 8001f36: bf00 nop 8001f38: 66666667 .word 0x66666667 08001f3c : /* TIM3 Timer Interrupt */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001f3c: b480 push {r7} 8001f3e: b083 sub sp, #12 8001f40: af00 add r7, sp, #0 8001f42: 6078 str r0, [r7, #4] if (htim->Instance == TIM3) 8001f44: 687b ldr r3, [r7, #4] 8001f46: 681b ldr r3, [r3, #0] 8001f48: 4a06 ldr r2, [pc, #24] @ (8001f64 ) 8001f4a: 4293 cmp r3, r2 8001f4c: d104 bne.n 8001f58 { g_ms_counter++; /* Relógio global do sistema */ 8001f4e: 4b06 ldr r3, [pc, #24] @ (8001f68 ) 8001f50: 681b ldr r3, [r3, #0] 8001f52: 3301 adds r3, #1 8001f54: 4a04 ldr r2, [pc, #16] @ (8001f68 ) 8001f56: 6013 str r3, [r2, #0] } } 8001f58: bf00 nop 8001f5a: 370c adds r7, #12 8001f5c: 46bd mov sp, r7 8001f5e: bc80 pop {r7} 8001f60: 4770 bx lr 8001f62: bf00 nop 8001f64: 40000400 .word 0x40000400 8001f68: 20000084 .word 0x20000084 08001f6c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001f6c: b480 push {r7} 8001f6e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001f70: b672 cpsid i } 8001f72: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001f74: bf00 nop 8001f76: e7fd b.n 8001f74 08001f78 : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 8001f78: b480 push {r7} 8001f7a: b083 sub sp, #12 8001f7c: af00 add r7, sp, #0 8001f7e: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 8001f80: 687b ldr r3, [r7, #4] 8001f82: 689b ldr r3, [r3, #8] } 8001f84: 4618 mov r0, r3 8001f86: 370c adds r7, #12 8001f88: 46bd mov sp, r7 8001f8a: bc80 pop {r7} 8001f8c: 4770 bx lr ... 08001f90 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 8001f90: b580 push {r7, lr} 8001f92: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 8001f94: f000 f864 bl 8002060 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 8001f98: f000 f8a8 bl 80020ec /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 8001f9c: f000 f808 bl 8001fb0 8001fa0: 4603 mov r3, r0 8001fa2: 461a mov r2, r3 8001fa4: 4b01 ldr r3, [pc, #4] @ (8001fac ) 8001fa6: 709a strb r2, [r3, #2] } 8001fa8: bf00 nop 8001faa: bd80 pop {r7, pc} 8001fac: 200002bc .word 0x200002bc 08001fb0 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 8001fb0: b598 push {r3, r4, r7, lr} 8001fb2: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 8001fb4: 480a ldr r0, [pc, #40] @ (8001fe0 ) 8001fb6: f7ff ffdf bl 8001f78 8001fba: 4603 mov r3, r0 8001fbc: 0a1b lsrs r3, r3, #8 8001fbe: b2db uxtb r3, r3 8001fc0: f023 030f bic.w r3, r3, #15 8001fc4: b2dc uxtb r4, r3 8001fc6: 4807 ldr r0, [pc, #28] @ (8001fe4 ) 8001fc8: f7ff ffd6 bl 8001f78 8001fcc: 4603 mov r3, r0 8001fce: 089b lsrs r3, r3, #2 8001fd0: b2db uxtb r3, r3 8001fd2: f003 030f and.w r3, r3, #15 8001fd6: b2db uxtb r3, r3 8001fd8: 4323 orrs r3, r4 8001fda: b2db uxtb r3, r3 } 8001fdc: 4618 mov r0, r3 8001fde: bd98 pop {r3, r4, r7, pc} 8001fe0: 40010c00 .word 0x40010c00 8001fe4: 40010800 .word 0x40010800 08001fe8 : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 8001fe8: b580 push {r7, lr} 8001fea: b084 sub sp, #16 8001fec: af00 add r7, sp, #0 8001fee: 6078 str r0, [r7, #4] 8001ff0: 460b mov r3, r1 8001ff2: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 8001ff4: f000 f81c bl 8002030 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 8001ff8: 2300 movs r3, #0 8001ffa: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8001ffc: f107 010e add.w r1, r7, #14 8002000: f04f 33ff mov.w r3, #4294967295 8002004: 2201 movs r2, #1 8002006: 4809 ldr r0, [pc, #36] @ (800202c ) 8002008: f003 f978 bl 80052fc /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 800200c: 887a ldrh r2, [r7, #2] 800200e: f04f 33ff mov.w r3, #4294967295 8002012: 6879 ldr r1, [r7, #4] 8002014: 4805 ldr r0, [pc, #20] @ (800202c ) 8002016: f003 f971 bl 80052fc 800201a: 4603 mov r3, r0 800201c: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 800201e: f000 f813 bl 8002048 return status; 8002022: 7bfb ldrb r3, [r7, #15] } 8002024: 4618 mov r0, r3 8002026: 3710 adds r7, #16 8002028: 46bd mov sp, r7 800202a: bd80 pop {r7, pc} 800202c: 200002c0 .word 0x200002c0 08002030 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 8002030: b580 push {r7, lr} 8002032: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 8002034: 2201 movs r2, #1 8002036: f44f 5180 mov.w r1, #4096 @ 0x1000 800203a: 4802 ldr r0, [pc, #8] @ (8002044 ) 800203c: f000 ffef bl 800301e } 8002040: bf00 nop 8002042: bd80 pop {r7, pc} 8002044: 40010800 .word 0x40010800 08002048 : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 8002048: b580 push {r7, lr} 800204a: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 800204c: 2200 movs r2, #0 800204e: f44f 5180 mov.w r1, #4096 @ 0x1000 8002052: 4802 ldr r0, [pc, #8] @ (800205c ) 8002054: f000 ffe3 bl 800301e } 8002058: bf00 nop 800205a: bd80 pop {r7, pc} 800205c: 40010800 .word 0x40010800 08002060 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 8002060: b580 push {r7, lr} 8002062: b086 sub sp, #24 8002064: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002066: f107 0308 add.w r3, r7, #8 800206a: 2200 movs r2, #0 800206c: 601a str r2, [r3, #0] 800206e: 605a str r2, [r3, #4] 8002070: 609a str r2, [r3, #8] 8002072: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002074: 4b1a ldr r3, [pc, #104] @ (80020e0 ) 8002076: 699b ldr r3, [r3, #24] 8002078: 4a19 ldr r2, [pc, #100] @ (80020e0 ) 800207a: f043 0304 orr.w r3, r3, #4 800207e: 6193 str r3, [r2, #24] 8002080: 4b17 ldr r3, [pc, #92] @ (80020e0 ) 8002082: 699b ldr r3, [r3, #24] 8002084: f003 0304 and.w r3, r3, #4 8002088: 607b str r3, [r7, #4] 800208a: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 800208c: 4b14 ldr r3, [pc, #80] @ (80020e0 ) 800208e: 699b ldr r3, [r3, #24] 8002090: 4a13 ldr r2, [pc, #76] @ (80020e0 ) 8002092: f043 0308 orr.w r3, r3, #8 8002096: 6193 str r3, [r2, #24] 8002098: 4b11 ldr r3, [pc, #68] @ (80020e0 ) 800209a: 699b ldr r3, [r3, #24] 800209c: f003 0308 and.w r3, r3, #8 80020a0: 603b str r3, [r7, #0] 80020a2: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 80020a4: 233c movs r3, #60 @ 0x3c 80020a6: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80020a8: 2300 movs r3, #0 80020aa: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80020ac: 2301 movs r3, #1 80020ae: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80020b0: f107 0308 add.w r3, r7, #8 80020b4: 4619 mov r1, r3 80020b6: 480b ldr r0, [pc, #44] @ (80020e4 ) 80020b8: f000 fe16 bl 8002ce8 /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 80020bc: f44f 4370 mov.w r3, #61440 @ 0xf000 80020c0: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80020c2: 2300 movs r3, #0 80020c4: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80020c6: 2301 movs r3, #1 80020c8: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80020ca: f107 0308 add.w r3, r7, #8 80020ce: 4619 mov r1, r3 80020d0: 4805 ldr r0, [pc, #20] @ (80020e8 ) 80020d2: f000 fe09 bl 8002ce8 } 80020d6: bf00 nop 80020d8: 3718 adds r7, #24 80020da: 46bd mov sp, r7 80020dc: bd80 pop {r7, pc} 80020de: bf00 nop 80020e0: 40021000 .word 0x40021000 80020e4: 40010800 .word 0x40010800 80020e8: 40010c00 .word 0x40010c00 080020ec : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 80020ec: b580 push {r7, lr} 80020ee: b082 sub sp, #8 80020f0: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 80020f2: 4b18 ldr r3, [pc, #96] @ (8002154 ) 80020f4: 699b ldr r3, [r3, #24] 80020f6: 4a17 ldr r2, [pc, #92] @ (8002154 ) 80020f8: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80020fc: 6193 str r3, [r2, #24] 80020fe: 4b15 ldr r3, [pc, #84] @ (8002154 ) 8002100: 699b ldr r3, [r3, #24] 8002102: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002106: 607b str r3, [r7, #4] 8002108: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 800210a: 4b13 ldr r3, [pc, #76] @ (8002158 ) 800210c: 4a13 ldr r2, [pc, #76] @ (800215c ) 800210e: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002110: 4b11 ldr r3, [pc, #68] @ (8002158 ) 8002112: f44f 5216 mov.w r2, #9600 @ 0x2580 8002116: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002118: 4b0f ldr r3, [pc, #60] @ (8002158 ) 800211a: 2200 movs r2, #0 800211c: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800211e: 4b0e ldr r3, [pc, #56] @ (8002158 ) 8002120: 2200 movs r2, #0 8002122: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002124: 4b0c ldr r3, [pc, #48] @ (8002158 ) 8002126: 2200 movs r2, #0 8002128: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800212a: 4b0b ldr r3, [pc, #44] @ (8002158 ) 800212c: 220c movs r2, #12 800212e: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 8002130: 4b09 ldr r3, [pc, #36] @ (8002158 ) 8002132: 2200 movs r2, #0 8002134: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002136: 4b08 ldr r3, [pc, #32] @ (8002158 ) 8002138: 2200 movs r2, #0 800213a: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800213c: 4806 ldr r0, [pc, #24] @ (8002158 ) 800213e: f003 f88d bl 800525c 8002142: 4603 mov r3, r0 8002144: 2b00 cmp r3, #0 8002146: d001 beq.n 800214c { /* Initialization Error */ while(1); 8002148: bf00 nop 800214a: e7fd b.n 8002148 } } 800214c: bf00 nop 800214e: 3708 adds r7, #8 8002150: 46bd mov sp, r7 8002152: bd80 pop {r7, pc} 8002154: 40021000 .word 0x40021000 8002158: 200002c0 .word 0x200002c0 800215c: 40013800 .word 0x40013800 08002160 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002160: b480 push {r7} 8002162: b085 sub sp, #20 8002164: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8002166: 4b15 ldr r3, [pc, #84] @ (80021bc ) 8002168: 699b ldr r3, [r3, #24] 800216a: 4a14 ldr r2, [pc, #80] @ (80021bc ) 800216c: f043 0301 orr.w r3, r3, #1 8002170: 6193 str r3, [r2, #24] 8002172: 4b12 ldr r3, [pc, #72] @ (80021bc ) 8002174: 699b ldr r3, [r3, #24] 8002176: f003 0301 and.w r3, r3, #1 800217a: 60bb str r3, [r7, #8] 800217c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800217e: 4b0f ldr r3, [pc, #60] @ (80021bc ) 8002180: 69db ldr r3, [r3, #28] 8002182: 4a0e ldr r2, [pc, #56] @ (80021bc ) 8002184: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8002188: 61d3 str r3, [r2, #28] 800218a: 4b0c ldr r3, [pc, #48] @ (80021bc ) 800218c: 69db ldr r3, [r3, #28] 800218e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002192: 607b str r3, [r7, #4] 8002194: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8002196: 4b0a ldr r3, [pc, #40] @ (80021c0 ) 8002198: 685b ldr r3, [r3, #4] 800219a: 60fb str r3, [r7, #12] 800219c: 68fb ldr r3, [r7, #12] 800219e: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 80021a2: 60fb str r3, [r7, #12] 80021a4: 68fb ldr r3, [r7, #12] 80021a6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80021aa: 60fb str r3, [r7, #12] 80021ac: 4a04 ldr r2, [pc, #16] @ (80021c0 ) 80021ae: 68fb ldr r3, [r7, #12] 80021b0: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80021b2: bf00 nop 80021b4: 3714 adds r7, #20 80021b6: 46bd mov sp, r7 80021b8: bc80 pop {r7} 80021ba: 4770 bx lr 80021bc: 40021000 .word 0x40021000 80021c0: 40010000 .word 0x40010000 080021c4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80021c4: b480 push {r7} 80021c6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80021c8: bf00 nop 80021ca: e7fd b.n 80021c8 080021cc : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80021cc: b480 push {r7} 80021ce: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80021d0: bf00 nop 80021d2: e7fd b.n 80021d0 080021d4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80021d4: b480 push {r7} 80021d6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80021d8: bf00 nop 80021da: e7fd b.n 80021d8 080021dc : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80021dc: b480 push {r7} 80021de: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80021e0: bf00 nop 80021e2: e7fd b.n 80021e0 080021e4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80021e4: b480 push {r7} 80021e6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80021e8: bf00 nop 80021ea: e7fd b.n 80021e8 080021ec : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80021ec: b480 push {r7} 80021ee: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80021f0: bf00 nop 80021f2: 46bd mov sp, r7 80021f4: bc80 pop {r7} 80021f6: 4770 bx lr 080021f8 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80021f8: b480 push {r7} 80021fa: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80021fc: bf00 nop 80021fe: 46bd mov sp, r7 8002200: bc80 pop {r7} 8002202: 4770 bx lr 08002204 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002204: b480 push {r7} 8002206: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002208: bf00 nop 800220a: 46bd mov sp, r7 800220c: bc80 pop {r7} 800220e: 4770 bx lr 08002210 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002210: b580 push {r7, lr} 8002212: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002214: f000 f97a bl 800250c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002218: bf00 nop 800221a: bd80 pop {r7, pc} 0800221c : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800221c: b580 push {r7, lr} 800221e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002220: 4802 ldr r0, [pc, #8] @ (800222c ) 8002222: f002 fccb bl 8004bbc /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 8002226: bf00 nop 8002228: bd80 pop {r7, pc} 800222a: bf00 nop 800222c: 20000308 .word 0x20000308 08002230 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8002230: b580 push {r7, lr} 8002232: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8002234: 4802 ldr r0, [pc, #8] @ (8002240 ) 8002236: f003 f8ed bl 8005414 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800223a: bf00 nop 800223c: bd80 pop {r7, pc} 800223e: bf00 nop 8002240: 20000350 .word 0x20000350 08002244 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002244: b480 push {r7} 8002246: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002248: bf00 nop 800224a: 46bd mov sp, r7 800224c: bc80 pop {r7} 800224e: 4770 bx lr 08002250 : TIM_HandleTypeDef htim3; /* TIM3 init function */ void MX_TIM3_Init(void) { 8002250: b580 push {r7, lr} 8002252: b086 sub sp, #24 8002254: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8002256: f107 0308 add.w r3, r7, #8 800225a: 2200 movs r2, #0 800225c: 601a str r2, [r3, #0] 800225e: 605a str r2, [r3, #4] 8002260: 609a str r2, [r3, #8] 8002262: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8002264: 463b mov r3, r7 8002266: 2200 movs r2, #0 8002268: 601a str r2, [r3, #0] 800226a: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800226c: 4b1d ldr r3, [pc, #116] @ (80022e4 ) 800226e: 4a1e ldr r2, [pc, #120] @ (80022e8 ) 8002270: 601a str r2, [r3, #0] htim3.Init.Prescaler = 2; 8002272: 4b1c ldr r3, [pc, #112] @ (80022e4 ) 8002274: 2202 movs r2, #2 8002276: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8002278: 4b1a ldr r3, [pc, #104] @ (80022e4 ) 800227a: 2200 movs r2, #0 800227c: 609a str r2, [r3, #8] htim3.Init.Period = 999; 800227e: 4b19 ldr r3, [pc, #100] @ (80022e4 ) 8002280: f240 32e7 movw r2, #999 @ 0x3e7 8002284: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002286: 4b17 ldr r3, [pc, #92] @ (80022e4 ) 8002288: 2200 movs r2, #0 800228a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 800228c: 4b15 ldr r3, [pc, #84] @ (80022e4 ) 800228e: 2280 movs r2, #128 @ 0x80 8002290: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8002292: 4814 ldr r0, [pc, #80] @ (80022e4 ) 8002294: f002 fbf0 bl 8004a78 8002298: 4603 mov r3, r0 800229a: 2b00 cmp r3, #0 800229c: d001 beq.n 80022a2 { Error_Handler(); 800229e: f7ff fe65 bl 8001f6c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80022a2: f44f 5380 mov.w r3, #4096 @ 0x1000 80022a6: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 80022a8: f107 0308 add.w r3, r7, #8 80022ac: 4619 mov r1, r3 80022ae: 480d ldr r0, [pc, #52] @ (80022e4 ) 80022b0: f002 fd74 bl 8004d9c 80022b4: 4603 mov r3, r0 80022b6: 2b00 cmp r3, #0 80022b8: d001 beq.n 80022be { Error_Handler(); 80022ba: f7ff fe57 bl 8001f6c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80022be: 2300 movs r3, #0 80022c0: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80022c2: 2300 movs r3, #0 80022c4: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80022c6: 463b mov r3, r7 80022c8: 4619 mov r1, r3 80022ca: 4806 ldr r0, [pc, #24] @ (80022e4 ) 80022cc: f002 ff56 bl 800517c 80022d0: 4603 mov r3, r0 80022d2: 2b00 cmp r3, #0 80022d4: d001 beq.n 80022da { Error_Handler(); 80022d6: f7ff fe49 bl 8001f6c } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80022da: bf00 nop 80022dc: 3718 adds r7, #24 80022de: 46bd mov sp, r7 80022e0: bd80 pop {r7, pc} 80022e2: bf00 nop 80022e4: 20000308 .word 0x20000308 80022e8: 40000400 .word 0x40000400 080022ec : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 80022ec: b580 push {r7, lr} 80022ee: b084 sub sp, #16 80022f0: af00 add r7, sp, #0 80022f2: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: 4a0d ldr r2, [pc, #52] @ (8002330 ) 80022fa: 4293 cmp r3, r2 80022fc: d113 bne.n 8002326 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80022fe: 4b0d ldr r3, [pc, #52] @ (8002334 ) 8002300: 69db ldr r3, [r3, #28] 8002302: 4a0c ldr r2, [pc, #48] @ (8002334 ) 8002304: f043 0302 orr.w r3, r3, #2 8002308: 61d3 str r3, [r2, #28] 800230a: 4b0a ldr r3, [pc, #40] @ (8002334 ) 800230c: 69db ldr r3, [r3, #28] 800230e: f003 0302 and.w r3, r3, #2 8002312: 60fb str r3, [r7, #12] 8002314: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 8002316: 2200 movs r2, #0 8002318: 2100 movs r1, #0 800231a: 201d movs r0, #29 800231c: f000 fbfb bl 8002b16 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002320: 201d movs r0, #29 8002322: f000 fc14 bl 8002b4e /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8002326: bf00 nop 8002328: 3710 adds r7, #16 800232a: 46bd mov sp, r7 800232c: bd80 pop {r7, pc} 800232e: bf00 nop 8002330: 40000400 .word 0x40000400 8002334: 40021000 .word 0x40021000 08002338 : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 8002338: b580 push {r7, lr} 800233a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800233c: 4b11 ldr r3, [pc, #68] @ (8002384 ) 800233e: 4a12 ldr r2, [pc, #72] @ (8002388 ) 8002340: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8002342: 4b10 ldr r3, [pc, #64] @ (8002384 ) 8002344: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8002348: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800234a: 4b0e ldr r3, [pc, #56] @ (8002384 ) 800234c: 2200 movs r2, #0 800234e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002350: 4b0c ldr r3, [pc, #48] @ (8002384 ) 8002352: 2200 movs r2, #0 8002354: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002356: 4b0b ldr r3, [pc, #44] @ (8002384 ) 8002358: 2200 movs r2, #0 800235a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800235c: 4b09 ldr r3, [pc, #36] @ (8002384 ) 800235e: 220c movs r2, #12 8002360: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8002362: 4b08 ldr r3, [pc, #32] @ (8002384 ) 8002364: 2200 movs r2, #0 8002366: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002368: 4b06 ldr r3, [pc, #24] @ (8002384 ) 800236a: 2200 movs r2, #0 800236c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800236e: 4805 ldr r0, [pc, #20] @ (8002384 ) 8002370: f002 ff74 bl 800525c 8002374: 4603 mov r3, r0 8002376: 2b00 cmp r3, #0 8002378: d001 beq.n 800237e { Error_Handler(); 800237a: f7ff fdf7 bl 8001f6c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800237e: bf00 nop 8002380: bd80 pop {r7, pc} 8002382: bf00 nop 8002384: 20000350 .word 0x20000350 8002388: 40013800 .word 0x40013800 0800238c : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800238c: b580 push {r7, lr} 800238e: b088 sub sp, #32 8002390: af00 add r7, sp, #0 8002392: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002394: f107 0310 add.w r3, r7, #16 8002398: 2200 movs r2, #0 800239a: 601a str r2, [r3, #0] 800239c: 605a str r2, [r3, #4] 800239e: 609a str r2, [r3, #8] 80023a0: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 80023a2: 687b ldr r3, [r7, #4] 80023a4: 681b ldr r3, [r3, #0] 80023a6: 4a20 ldr r2, [pc, #128] @ (8002428 ) 80023a8: 4293 cmp r3, r2 80023aa: d139 bne.n 8002420 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80023ac: 4b1f ldr r3, [pc, #124] @ (800242c ) 80023ae: 699b ldr r3, [r3, #24] 80023b0: 4a1e ldr r2, [pc, #120] @ (800242c ) 80023b2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80023b6: 6193 str r3, [r2, #24] 80023b8: 4b1c ldr r3, [pc, #112] @ (800242c ) 80023ba: 699b ldr r3, [r3, #24] 80023bc: f403 4380 and.w r3, r3, #16384 @ 0x4000 80023c0: 60fb str r3, [r7, #12] 80023c2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80023c4: 4b19 ldr r3, [pc, #100] @ (800242c ) 80023c6: 699b ldr r3, [r3, #24] 80023c8: 4a18 ldr r2, [pc, #96] @ (800242c ) 80023ca: f043 0304 orr.w r3, r3, #4 80023ce: 6193 str r3, [r2, #24] 80023d0: 4b16 ldr r3, [pc, #88] @ (800242c ) 80023d2: 699b ldr r3, [r3, #24] 80023d4: f003 0304 and.w r3, r3, #4 80023d8: 60bb str r3, [r7, #8] 80023da: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 80023dc: f44f 7300 mov.w r3, #512 @ 0x200 80023e0: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80023e2: 2302 movs r3, #2 80023e4: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 80023e6: 2301 movs r3, #1 80023e8: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 80023ea: f107 0310 add.w r3, r7, #16 80023ee: 4619 mov r1, r3 80023f0: 480f ldr r0, [pc, #60] @ (8002430 ) 80023f2: f000 fc79 bl 8002ce8 GPIO_InitStruct.Pin = RX_RS485_Pin; 80023f6: f44f 6380 mov.w r3, #1024 @ 0x400 80023fa: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80023fc: 2300 movs r3, #0 80023fe: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002400: 2300 movs r3, #0 8002402: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 8002404: f107 0310 add.w r3, r7, #16 8002408: 4619 mov r1, r3 800240a: 4809 ldr r0, [pc, #36] @ (8002430 ) 800240c: f000 fc6c bl 8002ce8 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8002410: 2200 movs r2, #0 8002412: 2100 movs r1, #0 8002414: 2025 movs r0, #37 @ 0x25 8002416: f000 fb7e bl 8002b16 HAL_NVIC_EnableIRQ(USART1_IRQn); 800241a: 2025 movs r0, #37 @ 0x25 800241c: f000 fb97 bl 8002b4e /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002420: bf00 nop 8002422: 3720 adds r7, #32 8002424: 46bd mov sp, r7 8002426: bd80 pop {r7, pc} 8002428: 40013800 .word 0x40013800 800242c: 40021000 .word 0x40021000 8002430: 40010800 .word 0x40010800 08002434 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8002434: f7ff ff06 bl 8002244 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002438: 480b ldr r0, [pc, #44] @ (8002468 ) ldr r1, =_edata 800243a: 490c ldr r1, [pc, #48] @ (800246c ) ldr r2, =_sidata 800243c: 4a0c ldr r2, [pc, #48] @ (8002470 ) movs r3, #0 800243e: 2300 movs r3, #0 b LoopCopyDataInit 8002440: e002 b.n 8002448 08002442 : CopyDataInit: ldr r4, [r2, r3] 8002442: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002444: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002446: 3304 adds r3, #4 08002448 : LoopCopyDataInit: adds r4, r0, r3 8002448: 18c4 adds r4, r0, r3 cmp r4, r1 800244a: 428c cmp r4, r1 bcc CopyDataInit 800244c: d3f9 bcc.n 8002442 /* Zero fill the bss segment. */ ldr r2, =_sbss 800244e: 4a09 ldr r2, [pc, #36] @ (8002474 ) ldr r4, =_ebss 8002450: 4c09 ldr r4, [pc, #36] @ (8002478 ) movs r3, #0 8002452: 2300 movs r3, #0 b LoopFillZerobss 8002454: e001 b.n 800245a 08002456 : FillZerobss: str r3, [r2] 8002456: 6013 str r3, [r2, #0] adds r2, r2, #4 8002458: 3204 adds r2, #4 0800245a : LoopFillZerobss: cmp r2, r4 800245a: 42a2 cmp r2, r4 bcc FillZerobss 800245c: d3fb bcc.n 8002456 /* Call static constructors */ bl __libc_init_array 800245e: f003 fd21 bl 8005ea4 <__libc_init_array> /* Call the application's entry point.*/ bl main 8002462: f7ff fb05 bl 8001a70

bx lr 8002466: 4770 bx lr ldr r0, =_sdata 8002468: 20000000 .word 0x20000000 ldr r1, =_edata 800246c: 20000064 .word 0x20000064 ldr r2, =_sidata 8002470: 08006170 .word 0x08006170 ldr r2, =_sbss 8002474: 20000064 .word 0x20000064 ldr r4, =_ebss 8002478: 200004d4 .word 0x200004d4 0800247c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800247c: e7fe b.n 800247c ... 08002480 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002480: b580 push {r7, lr} 8002482: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002484: 4b08 ldr r3, [pc, #32] @ (80024a8 ) 8002486: 681b ldr r3, [r3, #0] 8002488: 4a07 ldr r2, [pc, #28] @ (80024a8 ) 800248a: f043 0310 orr.w r3, r3, #16 800248e: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002490: 2003 movs r0, #3 8002492: f000 fb35 bl 8002b00 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002496: 200f movs r0, #15 8002498: f000 f808 bl 80024ac /* Init the low level hardware */ HAL_MspInit(); 800249c: f7ff fe60 bl 8002160 /* Return function status */ return HAL_OK; 80024a0: 2300 movs r3, #0 } 80024a2: 4618 mov r0, r3 80024a4: bd80 pop {r7, pc} 80024a6: bf00 nop 80024a8: 40022000 .word 0x40022000 080024ac : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80024ac: b580 push {r7, lr} 80024ae: b082 sub sp, #8 80024b0: af00 add r7, sp, #0 80024b2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80024b4: 4b12 ldr r3, [pc, #72] @ (8002500 ) 80024b6: 681a ldr r2, [r3, #0] 80024b8: 4b12 ldr r3, [pc, #72] @ (8002504 ) 80024ba: 781b ldrb r3, [r3, #0] 80024bc: 4619 mov r1, r3 80024be: f44f 737a mov.w r3, #1000 @ 0x3e8 80024c2: fbb3 f3f1 udiv r3, r3, r1 80024c6: fbb2 f3f3 udiv r3, r2, r3 80024ca: 4618 mov r0, r3 80024cc: f000 fb4d bl 8002b6a 80024d0: 4603 mov r3, r0 80024d2: 2b00 cmp r3, #0 80024d4: d001 beq.n 80024da { return HAL_ERROR; 80024d6: 2301 movs r3, #1 80024d8: e00e b.n 80024f8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80024da: 687b ldr r3, [r7, #4] 80024dc: 2b0f cmp r3, #15 80024de: d80a bhi.n 80024f6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80024e0: 2200 movs r2, #0 80024e2: 6879 ldr r1, [r7, #4] 80024e4: f04f 30ff mov.w r0, #4294967295 80024e8: f000 fb15 bl 8002b16 uwTickPrio = TickPriority; 80024ec: 4a06 ldr r2, [pc, #24] @ (8002508 ) 80024ee: 687b ldr r3, [r7, #4] 80024f0: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80024f2: 2300 movs r3, #0 80024f4: e000 b.n 80024f8 return HAL_ERROR; 80024f6: 2301 movs r3, #1 } 80024f8: 4618 mov r0, r3 80024fa: 3708 adds r7, #8 80024fc: 46bd mov sp, r7 80024fe: bd80 pop {r7, pc} 8002500: 20000008 .word 0x20000008 8002504: 20000010 .word 0x20000010 8002508: 2000000c .word 0x2000000c 0800250c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800250c: b480 push {r7} 800250e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002510: 4b05 ldr r3, [pc, #20] @ (8002528 ) 8002512: 781b ldrb r3, [r3, #0] 8002514: 461a mov r2, r3 8002516: 4b05 ldr r3, [pc, #20] @ (800252c ) 8002518: 681b ldr r3, [r3, #0] 800251a: 4413 add r3, r2 800251c: 4a03 ldr r2, [pc, #12] @ (800252c ) 800251e: 6013 str r3, [r2, #0] } 8002520: bf00 nop 8002522: 46bd mov sp, r7 8002524: bc80 pop {r7} 8002526: 4770 bx lr 8002528: 20000010 .word 0x20000010 800252c: 20000398 .word 0x20000398 08002530 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002530: b480 push {r7} 8002532: af00 add r7, sp, #0 return uwTick; 8002534: 4b02 ldr r3, [pc, #8] @ (8002540 ) 8002536: 681b ldr r3, [r3, #0] } 8002538: 4618 mov r0, r3 800253a: 46bd mov sp, r7 800253c: bc80 pop {r7} 800253e: 4770 bx lr 8002540: 20000398 .word 0x20000398 08002544 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8002544: b580 push {r7, lr} 8002546: b086 sub sp, #24 8002548: af00 add r7, sp, #0 800254a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800254c: 2300 movs r3, #0 800254e: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8002550: 2300 movs r3, #0 8002552: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8002554: 2300 movs r3, #0 8002556: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8002558: 2300 movs r3, #0 800255a: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800255c: 687b ldr r3, [r7, #4] 800255e: 2b00 cmp r3, #0 8002560: d101 bne.n 8002566 { return HAL_ERROR; 8002562: 2301 movs r3, #1 8002564: e0be b.n 80026e4 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8002566: 687b ldr r3, [r7, #4] 8002568: 689b ldr r3, [r3, #8] 800256a: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800256c: 687b ldr r3, [r7, #4] 800256e: 6a9b ldr r3, [r3, #40] @ 0x28 8002570: 2b00 cmp r3, #0 8002572: d109 bne.n 8002588 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8002574: 687b ldr r3, [r7, #4] 8002576: 2200 movs r2, #0 8002578: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800257a: 687b ldr r3, [r7, #4] 800257c: 2200 movs r2, #0 800257e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8002582: 6878 ldr r0, [r7, #4] 8002584: f7fe fdc8 bl 8001118 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8002588: 6878 ldr r0, [r7, #4] 800258a: f000 f9ab bl 80028e4 800258e: 4603 mov r3, r0 8002590: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8002592: 687b ldr r3, [r7, #4] 8002594: 6a9b ldr r3, [r3, #40] @ 0x28 8002596: f003 0310 and.w r3, r3, #16 800259a: 2b00 cmp r3, #0 800259c: f040 8099 bne.w 80026d2 80025a0: 7dfb ldrb r3, [r7, #23] 80025a2: 2b00 cmp r3, #0 80025a4: f040 8095 bne.w 80026d2 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80025a8: 687b ldr r3, [r7, #4] 80025aa: 6a9b ldr r3, [r3, #40] @ 0x28 80025ac: f423 5388 bic.w r3, r3, #4352 @ 0x1100 80025b0: f023 0302 bic.w r3, r3, #2 80025b4: f043 0202 orr.w r2, r3, #2 80025b8: 687b ldr r3, [r7, #4] 80025ba: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 80025bc: 687b ldr r3, [r7, #4] 80025be: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80025c0: 687b ldr r3, [r7, #4] 80025c2: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 80025c4: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 80025c6: 687b ldr r3, [r7, #4] 80025c8: 7b1b ldrb r3, [r3, #12] 80025ca: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80025cc: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 80025ce: 68ba ldr r2, [r7, #8] 80025d0: 4313 orrs r3, r2 80025d2: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80025d4: 687b ldr r3, [r7, #4] 80025d6: 689b ldr r3, [r3, #8] 80025d8: f5b3 7f80 cmp.w r3, #256 @ 0x100 80025dc: d003 beq.n 80025e6 80025de: 687b ldr r3, [r7, #4] 80025e0: 689b ldr r3, [r3, #8] 80025e2: 2b01 cmp r3, #1 80025e4: d102 bne.n 80025ec 80025e6: f44f 7380 mov.w r3, #256 @ 0x100 80025ea: e000 b.n 80025ee 80025ec: 2300 movs r3, #0 80025ee: 693a ldr r2, [r7, #16] 80025f0: 4313 orrs r3, r2 80025f2: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80025f4: 687b ldr r3, [r7, #4] 80025f6: 7d1b ldrb r3, [r3, #20] 80025f8: 2b01 cmp r3, #1 80025fa: d119 bne.n 8002630 { if (hadc->Init.ContinuousConvMode == DISABLE) 80025fc: 687b ldr r3, [r7, #4] 80025fe: 7b1b ldrb r3, [r3, #12] 8002600: 2b00 cmp r3, #0 8002602: d109 bne.n 8002618 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8002604: 687b ldr r3, [r7, #4] 8002606: 699b ldr r3, [r3, #24] 8002608: 3b01 subs r3, #1 800260a: 035a lsls r2, r3, #13 800260c: 693b ldr r3, [r7, #16] 800260e: 4313 orrs r3, r2 8002610: f443 6300 orr.w r3, r3, #2048 @ 0x800 8002614: 613b str r3, [r7, #16] 8002616: e00b b.n 8002630 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002618: 687b ldr r3, [r7, #4] 800261a: 6a9b ldr r3, [r3, #40] @ 0x28 800261c: f043 0220 orr.w r2, r3, #32 8002620: 687b ldr r3, [r7, #4] 8002622: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002624: 687b ldr r3, [r7, #4] 8002626: 6adb ldr r3, [r3, #44] @ 0x2c 8002628: f043 0201 orr.w r2, r3, #1 800262c: 687b ldr r3, [r7, #4] 800262e: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8002630: 687b ldr r3, [r7, #4] 8002632: 681b ldr r3, [r3, #0] 8002634: 685b ldr r3, [r3, #4] 8002636: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800263a: 687b ldr r3, [r7, #4] 800263c: 681b ldr r3, [r3, #0] 800263e: 693a ldr r2, [r7, #16] 8002640: 430a orrs r2, r1 8002642: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8002644: 687b ldr r3, [r7, #4] 8002646: 681b ldr r3, [r3, #0] 8002648: 689a ldr r2, [r3, #8] 800264a: 4b28 ldr r3, [pc, #160] @ (80026ec ) 800264c: 4013 ands r3, r2 800264e: 687a ldr r2, [r7, #4] 8002650: 6812 ldr r2, [r2, #0] 8002652: 68b9 ldr r1, [r7, #8] 8002654: 430b orrs r3, r1 8002656: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8002658: 687b ldr r3, [r7, #4] 800265a: 689b ldr r3, [r3, #8] 800265c: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002660: d003 beq.n 800266a 8002662: 687b ldr r3, [r7, #4] 8002664: 689b ldr r3, [r3, #8] 8002666: 2b01 cmp r3, #1 8002668: d104 bne.n 8002674 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800266a: 687b ldr r3, [r7, #4] 800266c: 691b ldr r3, [r3, #16] 800266e: 3b01 subs r3, #1 8002670: 051b lsls r3, r3, #20 8002672: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8002674: 687b ldr r3, [r7, #4] 8002676: 681b ldr r3, [r3, #0] 8002678: 6adb ldr r3, [r3, #44] @ 0x2c 800267a: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800267e: 687b ldr r3, [r7, #4] 8002680: 681b ldr r3, [r3, #0] 8002682: 68fa ldr r2, [r7, #12] 8002684: 430a orrs r2, r1 8002686: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002688: 687b ldr r3, [r7, #4] 800268a: 681b ldr r3, [r3, #0] 800268c: 689a ldr r2, [r3, #8] 800268e: 4b18 ldr r3, [pc, #96] @ (80026f0 ) 8002690: 4013 ands r3, r2 8002692: 68ba ldr r2, [r7, #8] 8002694: 429a cmp r2, r3 8002696: d10b bne.n 80026b0 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8002698: 687b ldr r3, [r7, #4] 800269a: 2200 movs r2, #0 800269c: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800269e: 687b ldr r3, [r7, #4] 80026a0: 6a9b ldr r3, [r3, #40] @ 0x28 80026a2: f023 0303 bic.w r3, r3, #3 80026a6: f043 0201 orr.w r2, r3, #1 80026aa: 687b ldr r3, [r7, #4] 80026ac: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80026ae: e018 b.n 80026e2 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80026b0: 687b ldr r3, [r7, #4] 80026b2: 6a9b ldr r3, [r3, #40] @ 0x28 80026b4: f023 0312 bic.w r3, r3, #18 80026b8: f043 0210 orr.w r2, r3, #16 80026bc: 687b ldr r3, [r7, #4] 80026be: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80026c0: 687b ldr r3, [r7, #4] 80026c2: 6adb ldr r3, [r3, #44] @ 0x2c 80026c4: f043 0201 orr.w r2, r3, #1 80026c8: 687b ldr r3, [r7, #4] 80026ca: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 80026cc: 2301 movs r3, #1 80026ce: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80026d0: e007 b.n 80026e2 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80026d2: 687b ldr r3, [r7, #4] 80026d4: 6a9b ldr r3, [r3, #40] @ 0x28 80026d6: f043 0210 orr.w r2, r3, #16 80026da: 687b ldr r3, [r7, #4] 80026dc: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 80026de: 2301 movs r3, #1 80026e0: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80026e2: 7dfb ldrb r3, [r7, #23] } 80026e4: 4618 mov r0, r3 80026e6: 3718 adds r7, #24 80026e8: 46bd mov sp, r7 80026ea: bd80 pop {r7, pc} 80026ec: ffe1f7fd .word 0xffe1f7fd 80026f0: ff1f0efe .word 0xff1f0efe 080026f4 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 80026f4: b480 push {r7} 80026f6: b085 sub sp, #20 80026f8: af00 add r7, sp, #0 80026fa: 6078 str r0, [r7, #4] 80026fc: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80026fe: 2300 movs r3, #0 8002700: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8002702: 2300 movs r3, #0 8002704: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8002706: 687b ldr r3, [r7, #4] 8002708: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800270c: 2b01 cmp r3, #1 800270e: d101 bne.n 8002714 8002710: 2302 movs r3, #2 8002712: e0dc b.n 80028ce 8002714: 687b ldr r3, [r7, #4] 8002716: 2201 movs r2, #1 8002718: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800271c: 683b ldr r3, [r7, #0] 800271e: 685b ldr r3, [r3, #4] 8002720: 2b06 cmp r3, #6 8002722: d81c bhi.n 800275e { MODIFY_REG(hadc->Instance->SQR3 , 8002724: 687b ldr r3, [r7, #4] 8002726: 681b ldr r3, [r3, #0] 8002728: 6b59 ldr r1, [r3, #52] @ 0x34 800272a: 683b ldr r3, [r7, #0] 800272c: 685a ldr r2, [r3, #4] 800272e: 4613 mov r3, r2 8002730: 009b lsls r3, r3, #2 8002732: 4413 add r3, r2 8002734: 3b05 subs r3, #5 8002736: 221f movs r2, #31 8002738: fa02 f303 lsl.w r3, r2, r3 800273c: 43db mvns r3, r3 800273e: 4019 ands r1, r3 8002740: 683b ldr r3, [r7, #0] 8002742: 6818 ldr r0, [r3, #0] 8002744: 683b ldr r3, [r7, #0] 8002746: 685a ldr r2, [r3, #4] 8002748: 4613 mov r3, r2 800274a: 009b lsls r3, r3, #2 800274c: 4413 add r3, r2 800274e: 3b05 subs r3, #5 8002750: fa00 f203 lsl.w r2, r0, r3 8002754: 687b ldr r3, [r7, #4] 8002756: 681b ldr r3, [r3, #0] 8002758: 430a orrs r2, r1 800275a: 635a str r2, [r3, #52] @ 0x34 800275c: e03c b.n 80027d8 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800275e: 683b ldr r3, [r7, #0] 8002760: 685b ldr r3, [r3, #4] 8002762: 2b0c cmp r3, #12 8002764: d81c bhi.n 80027a0 { MODIFY_REG(hadc->Instance->SQR2 , 8002766: 687b ldr r3, [r7, #4] 8002768: 681b ldr r3, [r3, #0] 800276a: 6b19 ldr r1, [r3, #48] @ 0x30 800276c: 683b ldr r3, [r7, #0] 800276e: 685a ldr r2, [r3, #4] 8002770: 4613 mov r3, r2 8002772: 009b lsls r3, r3, #2 8002774: 4413 add r3, r2 8002776: 3b23 subs r3, #35 @ 0x23 8002778: 221f movs r2, #31 800277a: fa02 f303 lsl.w r3, r2, r3 800277e: 43db mvns r3, r3 8002780: 4019 ands r1, r3 8002782: 683b ldr r3, [r7, #0] 8002784: 6818 ldr r0, [r3, #0] 8002786: 683b ldr r3, [r7, #0] 8002788: 685a ldr r2, [r3, #4] 800278a: 4613 mov r3, r2 800278c: 009b lsls r3, r3, #2 800278e: 4413 add r3, r2 8002790: 3b23 subs r3, #35 @ 0x23 8002792: fa00 f203 lsl.w r2, r0, r3 8002796: 687b ldr r3, [r7, #4] 8002798: 681b ldr r3, [r3, #0] 800279a: 430a orrs r2, r1 800279c: 631a str r2, [r3, #48] @ 0x30 800279e: e01b b.n 80027d8 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 80027a0: 687b ldr r3, [r7, #4] 80027a2: 681b ldr r3, [r3, #0] 80027a4: 6ad9 ldr r1, [r3, #44] @ 0x2c 80027a6: 683b ldr r3, [r7, #0] 80027a8: 685a ldr r2, [r3, #4] 80027aa: 4613 mov r3, r2 80027ac: 009b lsls r3, r3, #2 80027ae: 4413 add r3, r2 80027b0: 3b41 subs r3, #65 @ 0x41 80027b2: 221f movs r2, #31 80027b4: fa02 f303 lsl.w r3, r2, r3 80027b8: 43db mvns r3, r3 80027ba: 4019 ands r1, r3 80027bc: 683b ldr r3, [r7, #0] 80027be: 6818 ldr r0, [r3, #0] 80027c0: 683b ldr r3, [r7, #0] 80027c2: 685a ldr r2, [r3, #4] 80027c4: 4613 mov r3, r2 80027c6: 009b lsls r3, r3, #2 80027c8: 4413 add r3, r2 80027ca: 3b41 subs r3, #65 @ 0x41 80027cc: fa00 f203 lsl.w r2, r0, r3 80027d0: 687b ldr r3, [r7, #4] 80027d2: 681b ldr r3, [r3, #0] 80027d4: 430a orrs r2, r1 80027d6: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 80027d8: 683b ldr r3, [r7, #0] 80027da: 681b ldr r3, [r3, #0] 80027dc: 2b09 cmp r3, #9 80027de: d91c bls.n 800281a { MODIFY_REG(hadc->Instance->SMPR1 , 80027e0: 687b ldr r3, [r7, #4] 80027e2: 681b ldr r3, [r3, #0] 80027e4: 68d9 ldr r1, [r3, #12] 80027e6: 683b ldr r3, [r7, #0] 80027e8: 681a ldr r2, [r3, #0] 80027ea: 4613 mov r3, r2 80027ec: 005b lsls r3, r3, #1 80027ee: 4413 add r3, r2 80027f0: 3b1e subs r3, #30 80027f2: 2207 movs r2, #7 80027f4: fa02 f303 lsl.w r3, r2, r3 80027f8: 43db mvns r3, r3 80027fa: 4019 ands r1, r3 80027fc: 683b ldr r3, [r7, #0] 80027fe: 6898 ldr r0, [r3, #8] 8002800: 683b ldr r3, [r7, #0] 8002802: 681a ldr r2, [r3, #0] 8002804: 4613 mov r3, r2 8002806: 005b lsls r3, r3, #1 8002808: 4413 add r3, r2 800280a: 3b1e subs r3, #30 800280c: fa00 f203 lsl.w r2, r0, r3 8002810: 687b ldr r3, [r7, #4] 8002812: 681b ldr r3, [r3, #0] 8002814: 430a orrs r2, r1 8002816: 60da str r2, [r3, #12] 8002818: e019 b.n 800284e ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800281a: 687b ldr r3, [r7, #4] 800281c: 681b ldr r3, [r3, #0] 800281e: 6919 ldr r1, [r3, #16] 8002820: 683b ldr r3, [r7, #0] 8002822: 681a ldr r2, [r3, #0] 8002824: 4613 mov r3, r2 8002826: 005b lsls r3, r3, #1 8002828: 4413 add r3, r2 800282a: 2207 movs r2, #7 800282c: fa02 f303 lsl.w r3, r2, r3 8002830: 43db mvns r3, r3 8002832: 4019 ands r1, r3 8002834: 683b ldr r3, [r7, #0] 8002836: 6898 ldr r0, [r3, #8] 8002838: 683b ldr r3, [r7, #0] 800283a: 681a ldr r2, [r3, #0] 800283c: 4613 mov r3, r2 800283e: 005b lsls r3, r3, #1 8002840: 4413 add r3, r2 8002842: fa00 f203 lsl.w r2, r0, r3 8002846: 687b ldr r3, [r7, #4] 8002848: 681b ldr r3, [r3, #0] 800284a: 430a orrs r2, r1 800284c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800284e: 683b ldr r3, [r7, #0] 8002850: 681b ldr r3, [r3, #0] 8002852: 2b10 cmp r3, #16 8002854: d003 beq.n 800285e (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8002856: 683b ldr r3, [r7, #0] 8002858: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800285a: 2b11 cmp r3, #17 800285c: d132 bne.n 80028c4 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800285e: 687b ldr r3, [r7, #4] 8002860: 681b ldr r3, [r3, #0] 8002862: 4a1d ldr r2, [pc, #116] @ (80028d8 ) 8002864: 4293 cmp r3, r2 8002866: d125 bne.n 80028b4 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8002868: 687b ldr r3, [r7, #4] 800286a: 681b ldr r3, [r3, #0] 800286c: 689b ldr r3, [r3, #8] 800286e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8002872: 2b00 cmp r3, #0 8002874: d126 bne.n 80028c4 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8002876: 687b ldr r3, [r7, #4] 8002878: 681b ldr r3, [r3, #0] 800287a: 689a ldr r2, [r3, #8] 800287c: 687b ldr r3, [r7, #4] 800287e: 681b ldr r3, [r3, #0] 8002880: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8002884: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8002886: 683b ldr r3, [r7, #0] 8002888: 681b ldr r3, [r3, #0] 800288a: 2b10 cmp r3, #16 800288c: d11a bne.n 80028c4 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800288e: 4b13 ldr r3, [pc, #76] @ (80028dc ) 8002890: 681b ldr r3, [r3, #0] 8002892: 4a13 ldr r2, [pc, #76] @ (80028e0 ) 8002894: fba2 2303 umull r2, r3, r2, r3 8002898: 0c9a lsrs r2, r3, #18 800289a: 4613 mov r3, r2 800289c: 009b lsls r3, r3, #2 800289e: 4413 add r3, r2 80028a0: 005b lsls r3, r3, #1 80028a2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80028a4: e002 b.n 80028ac { wait_loop_index--; 80028a6: 68bb ldr r3, [r7, #8] 80028a8: 3b01 subs r3, #1 80028aa: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80028ac: 68bb ldr r3, [r7, #8] 80028ae: 2b00 cmp r3, #0 80028b0: d1f9 bne.n 80028a6 80028b2: e007 b.n 80028c4 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80028b4: 687b ldr r3, [r7, #4] 80028b6: 6a9b ldr r3, [r3, #40] @ 0x28 80028b8: f043 0220 orr.w r2, r3, #32 80028bc: 687b ldr r3, [r7, #4] 80028be: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 80028c0: 2301 movs r3, #1 80028c2: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 80028c4: 687b ldr r3, [r7, #4] 80028c6: 2200 movs r2, #0 80028c8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 80028cc: 7bfb ldrb r3, [r7, #15] } 80028ce: 4618 mov r0, r3 80028d0: 3714 adds r7, #20 80028d2: 46bd mov sp, r7 80028d4: bc80 pop {r7} 80028d6: 4770 bx lr 80028d8: 40012400 .word 0x40012400 80028dc: 20000008 .word 0x20000008 80028e0: 431bde83 .word 0x431bde83 080028e4 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 80028e4: b580 push {r7, lr} 80028e6: b084 sub sp, #16 80028e8: af00 add r7, sp, #0 80028ea: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80028ec: 2300 movs r3, #0 80028ee: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 80028f0: 687b ldr r3, [r7, #4] 80028f2: 681b ldr r3, [r3, #0] 80028f4: 689b ldr r3, [r3, #8] 80028f6: f003 0301 and.w r3, r3, #1 80028fa: 2b01 cmp r3, #1 80028fc: d12e bne.n 800295c { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 80028fe: 687b ldr r3, [r7, #4] 8002900: 681b ldr r3, [r3, #0] 8002902: 689a ldr r2, [r3, #8] 8002904: 687b ldr r3, [r7, #4] 8002906: 681b ldr r3, [r3, #0] 8002908: f022 0201 bic.w r2, r2, #1 800290c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800290e: f7ff fe0f bl 8002530 8002912: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002914: e01b b.n 800294e { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002916: f7ff fe0b bl 8002530 800291a: 4602 mov r2, r0 800291c: 68fb ldr r3, [r7, #12] 800291e: 1ad3 subs r3, r2, r3 8002920: 2b02 cmp r3, #2 8002922: d914 bls.n 800294e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8002924: 687b ldr r3, [r7, #4] 8002926: 681b ldr r3, [r3, #0] 8002928: 689b ldr r3, [r3, #8] 800292a: f003 0301 and.w r3, r3, #1 800292e: 2b01 cmp r3, #1 8002930: d10d bne.n 800294e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002932: 687b ldr r3, [r7, #4] 8002934: 6a9b ldr r3, [r3, #40] @ 0x28 8002936: f043 0210 orr.w r2, r3, #16 800293a: 687b ldr r3, [r7, #4] 800293c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800293e: 687b ldr r3, [r7, #4] 8002940: 6adb ldr r3, [r3, #44] @ 0x2c 8002942: f043 0201 orr.w r2, r3, #1 8002946: 687b ldr r3, [r7, #4] 8002948: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800294a: 2301 movs r3, #1 800294c: e007 b.n 800295e while(ADC_IS_ENABLE(hadc) != RESET) 800294e: 687b ldr r3, [r7, #4] 8002950: 681b ldr r3, [r3, #0] 8002952: 689b ldr r3, [r3, #8] 8002954: f003 0301 and.w r3, r3, #1 8002958: 2b01 cmp r3, #1 800295a: d0dc beq.n 8002916 } } } /* Return HAL status */ return HAL_OK; 800295c: 2300 movs r3, #0 } 800295e: 4618 mov r0, r3 8002960: 3710 adds r7, #16 8002962: 46bd mov sp, r7 8002964: bd80 pop {r7, pc} ... 08002968 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002968: b480 push {r7} 800296a: b085 sub sp, #20 800296c: af00 add r7, sp, #0 800296e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002970: 687b ldr r3, [r7, #4] 8002972: f003 0307 and.w r3, r3, #7 8002976: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002978: 4b0c ldr r3, [pc, #48] @ (80029ac <__NVIC_SetPriorityGrouping+0x44>) 800297a: 68db ldr r3, [r3, #12] 800297c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800297e: 68ba ldr r2, [r7, #8] 8002980: f64f 03ff movw r3, #63743 @ 0xf8ff 8002984: 4013 ands r3, r2 8002986: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002988: 68fb ldr r3, [r7, #12] 800298a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800298c: 68bb ldr r3, [r7, #8] 800298e: 4313 orrs r3, r2 reg_value = (reg_value | 8002990: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002994: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8002998: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800299a: 4a04 ldr r2, [pc, #16] @ (80029ac <__NVIC_SetPriorityGrouping+0x44>) 800299c: 68bb ldr r3, [r7, #8] 800299e: 60d3 str r3, [r2, #12] } 80029a0: bf00 nop 80029a2: 3714 adds r7, #20 80029a4: 46bd mov sp, r7 80029a6: bc80 pop {r7} 80029a8: 4770 bx lr 80029aa: bf00 nop 80029ac: e000ed00 .word 0xe000ed00 080029b0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80029b0: b480 push {r7} 80029b2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80029b4: 4b04 ldr r3, [pc, #16] @ (80029c8 <__NVIC_GetPriorityGrouping+0x18>) 80029b6: 68db ldr r3, [r3, #12] 80029b8: 0a1b lsrs r3, r3, #8 80029ba: f003 0307 and.w r3, r3, #7 } 80029be: 4618 mov r0, r3 80029c0: 46bd mov sp, r7 80029c2: bc80 pop {r7} 80029c4: 4770 bx lr 80029c6: bf00 nop 80029c8: e000ed00 .word 0xe000ed00 080029cc <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80029cc: b480 push {r7} 80029ce: b083 sub sp, #12 80029d0: af00 add r7, sp, #0 80029d2: 4603 mov r3, r0 80029d4: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80029d6: f997 3007 ldrsb.w r3, [r7, #7] 80029da: 2b00 cmp r3, #0 80029dc: db0b blt.n 80029f6 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80029de: 79fb ldrb r3, [r7, #7] 80029e0: f003 021f and.w r2, r3, #31 80029e4: 4906 ldr r1, [pc, #24] @ (8002a00 <__NVIC_EnableIRQ+0x34>) 80029e6: f997 3007 ldrsb.w r3, [r7, #7] 80029ea: 095b lsrs r3, r3, #5 80029ec: 2001 movs r0, #1 80029ee: fa00 f202 lsl.w r2, r0, r2 80029f2: f841 2023 str.w r2, [r1, r3, lsl #2] } } 80029f6: bf00 nop 80029f8: 370c adds r7, #12 80029fa: 46bd mov sp, r7 80029fc: bc80 pop {r7} 80029fe: 4770 bx lr 8002a00: e000e100 .word 0xe000e100 08002a04 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002a04: b480 push {r7} 8002a06: b083 sub sp, #12 8002a08: af00 add r7, sp, #0 8002a0a: 4603 mov r3, r0 8002a0c: 6039 str r1, [r7, #0] 8002a0e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002a10: f997 3007 ldrsb.w r3, [r7, #7] 8002a14: 2b00 cmp r3, #0 8002a16: db0a blt.n 8002a2e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002a18: 683b ldr r3, [r7, #0] 8002a1a: b2da uxtb r2, r3 8002a1c: 490c ldr r1, [pc, #48] @ (8002a50 <__NVIC_SetPriority+0x4c>) 8002a1e: f997 3007 ldrsb.w r3, [r7, #7] 8002a22: 0112 lsls r2, r2, #4 8002a24: b2d2 uxtb r2, r2 8002a26: 440b add r3, r1 8002a28: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002a2c: e00a b.n 8002a44 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002a2e: 683b ldr r3, [r7, #0] 8002a30: b2da uxtb r2, r3 8002a32: 4908 ldr r1, [pc, #32] @ (8002a54 <__NVIC_SetPriority+0x50>) 8002a34: 79fb ldrb r3, [r7, #7] 8002a36: f003 030f and.w r3, r3, #15 8002a3a: 3b04 subs r3, #4 8002a3c: 0112 lsls r2, r2, #4 8002a3e: b2d2 uxtb r2, r2 8002a40: 440b add r3, r1 8002a42: 761a strb r2, [r3, #24] } 8002a44: bf00 nop 8002a46: 370c adds r7, #12 8002a48: 46bd mov sp, r7 8002a4a: bc80 pop {r7} 8002a4c: 4770 bx lr 8002a4e: bf00 nop 8002a50: e000e100 .word 0xe000e100 8002a54: e000ed00 .word 0xe000ed00 08002a58 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002a58: b480 push {r7} 8002a5a: b089 sub sp, #36 @ 0x24 8002a5c: af00 add r7, sp, #0 8002a5e: 60f8 str r0, [r7, #12] 8002a60: 60b9 str r1, [r7, #8] 8002a62: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002a64: 68fb ldr r3, [r7, #12] 8002a66: f003 0307 and.w r3, r3, #7 8002a6a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002a6c: 69fb ldr r3, [r7, #28] 8002a6e: f1c3 0307 rsb r3, r3, #7 8002a72: 2b04 cmp r3, #4 8002a74: bf28 it cs 8002a76: 2304 movcs r3, #4 8002a78: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002a7a: 69fb ldr r3, [r7, #28] 8002a7c: 3304 adds r3, #4 8002a7e: 2b06 cmp r3, #6 8002a80: d902 bls.n 8002a88 8002a82: 69fb ldr r3, [r7, #28] 8002a84: 3b03 subs r3, #3 8002a86: e000 b.n 8002a8a 8002a88: 2300 movs r3, #0 8002a8a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002a8c: f04f 32ff mov.w r2, #4294967295 8002a90: 69bb ldr r3, [r7, #24] 8002a92: fa02 f303 lsl.w r3, r2, r3 8002a96: 43da mvns r2, r3 8002a98: 68bb ldr r3, [r7, #8] 8002a9a: 401a ands r2, r3 8002a9c: 697b ldr r3, [r7, #20] 8002a9e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002aa0: f04f 31ff mov.w r1, #4294967295 8002aa4: 697b ldr r3, [r7, #20] 8002aa6: fa01 f303 lsl.w r3, r1, r3 8002aaa: 43d9 mvns r1, r3 8002aac: 687b ldr r3, [r7, #4] 8002aae: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002ab0: 4313 orrs r3, r2 ); } 8002ab2: 4618 mov r0, r3 8002ab4: 3724 adds r7, #36 @ 0x24 8002ab6: 46bd mov sp, r7 8002ab8: bc80 pop {r7} 8002aba: 4770 bx lr 08002abc : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002abc: b580 push {r7, lr} 8002abe: b082 sub sp, #8 8002ac0: af00 add r7, sp, #0 8002ac2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 3b01 subs r3, #1 8002ac8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002acc: d301 bcc.n 8002ad2 { return (1UL); /* Reload value impossible */ 8002ace: 2301 movs r3, #1 8002ad0: e00f b.n 8002af2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002ad2: 4a0a ldr r2, [pc, #40] @ (8002afc ) 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 3b01 subs r3, #1 8002ad8: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002ada: 210f movs r1, #15 8002adc: f04f 30ff mov.w r0, #4294967295 8002ae0: f7ff ff90 bl 8002a04 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002ae4: 4b05 ldr r3, [pc, #20] @ (8002afc ) 8002ae6: 2200 movs r2, #0 8002ae8: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002aea: 4b04 ldr r3, [pc, #16] @ (8002afc ) 8002aec: 2207 movs r2, #7 8002aee: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002af0: 2300 movs r3, #0 } 8002af2: 4618 mov r0, r3 8002af4: 3708 adds r7, #8 8002af6: 46bd mov sp, r7 8002af8: bd80 pop {r7, pc} 8002afa: bf00 nop 8002afc: e000e010 .word 0xe000e010 08002b00 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002b00: b580 push {r7, lr} 8002b02: b082 sub sp, #8 8002b04: af00 add r7, sp, #0 8002b06: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002b08: 6878 ldr r0, [r7, #4] 8002b0a: f7ff ff2d bl 8002968 <__NVIC_SetPriorityGrouping> } 8002b0e: bf00 nop 8002b10: 3708 adds r7, #8 8002b12: 46bd mov sp, r7 8002b14: bd80 pop {r7, pc} 08002b16 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002b16: b580 push {r7, lr} 8002b18: b086 sub sp, #24 8002b1a: af00 add r7, sp, #0 8002b1c: 4603 mov r3, r0 8002b1e: 60b9 str r1, [r7, #8] 8002b20: 607a str r2, [r7, #4] 8002b22: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8002b24: 2300 movs r3, #0 8002b26: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002b28: f7ff ff42 bl 80029b0 <__NVIC_GetPriorityGrouping> 8002b2c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002b2e: 687a ldr r2, [r7, #4] 8002b30: 68b9 ldr r1, [r7, #8] 8002b32: 6978 ldr r0, [r7, #20] 8002b34: f7ff ff90 bl 8002a58 8002b38: 4602 mov r2, r0 8002b3a: f997 300f ldrsb.w r3, [r7, #15] 8002b3e: 4611 mov r1, r2 8002b40: 4618 mov r0, r3 8002b42: f7ff ff5f bl 8002a04 <__NVIC_SetPriority> } 8002b46: bf00 nop 8002b48: 3718 adds r7, #24 8002b4a: 46bd mov sp, r7 8002b4c: bd80 pop {r7, pc} 08002b4e : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002b4e: b580 push {r7, lr} 8002b50: b082 sub sp, #8 8002b52: af00 add r7, sp, #0 8002b54: 4603 mov r3, r0 8002b56: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002b58: f997 3007 ldrsb.w r3, [r7, #7] 8002b5c: 4618 mov r0, r3 8002b5e: f7ff ff35 bl 80029cc <__NVIC_EnableIRQ> } 8002b62: bf00 nop 8002b64: 3708 adds r7, #8 8002b66: 46bd mov sp, r7 8002b68: bd80 pop {r7, pc} 08002b6a : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002b6a: b580 push {r7, lr} 8002b6c: b082 sub sp, #8 8002b6e: af00 add r7, sp, #0 8002b70: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002b72: 6878 ldr r0, [r7, #4] 8002b74: f7ff ffa2 bl 8002abc 8002b78: 4603 mov r3, r0 } 8002b7a: 4618 mov r0, r3 8002b7c: 3708 adds r7, #8 8002b7e: 46bd mov sp, r7 8002b80: bd80 pop {r7, pc} 08002b82 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002b82: b480 push {r7} 8002b84: b085 sub sp, #20 8002b86: af00 add r7, sp, #0 8002b88: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002b8a: 2300 movs r3, #0 8002b8c: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8002b8e: 687b ldr r3, [r7, #4] 8002b90: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002b94: b2db uxtb r3, r3 8002b96: 2b02 cmp r3, #2 8002b98: d008 beq.n 8002bac { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 2204 movs r2, #4 8002b9e: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002ba0: 687b ldr r3, [r7, #4] 8002ba2: 2200 movs r2, #0 8002ba4: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8002ba8: 2301 movs r3, #1 8002baa: e020 b.n 8002bee } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002bac: 687b ldr r3, [r7, #4] 8002bae: 681b ldr r3, [r3, #0] 8002bb0: 681a ldr r2, [r3, #0] 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 681b ldr r3, [r3, #0] 8002bb6: f022 020e bic.w r2, r2, #14 8002bba: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002bbc: 687b ldr r3, [r7, #4] 8002bbe: 681b ldr r3, [r3, #0] 8002bc0: 681a ldr r2, [r3, #0] 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: f022 0201 bic.w r2, r2, #1 8002bca: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002bcc: 687b ldr r3, [r7, #4] 8002bce: 6c1a ldr r2, [r3, #64] @ 0x40 8002bd0: 687b ldr r3, [r7, #4] 8002bd2: 6bdb ldr r3, [r3, #60] @ 0x3c 8002bd4: 2101 movs r1, #1 8002bd6: fa01 f202 lsl.w r2, r1, r2 8002bda: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002bdc: 687b ldr r3, [r7, #4] 8002bde: 2201 movs r2, #1 8002be0: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002be4: 687b ldr r3, [r7, #4] 8002be6: 2200 movs r2, #0 8002be8: f883 2020 strb.w r2, [r3, #32] return status; 8002bec: 7bfb ldrb r3, [r7, #15] } 8002bee: 4618 mov r0, r3 8002bf0: 3714 adds r7, #20 8002bf2: 46bd mov sp, r7 8002bf4: bc80 pop {r7} 8002bf6: 4770 bx lr 08002bf8 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002bf8: b580 push {r7, lr} 8002bfa: b084 sub sp, #16 8002bfc: af00 add r7, sp, #0 8002bfe: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002c00: 2300 movs r3, #0 8002c02: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8002c04: 687b ldr r3, [r7, #4] 8002c06: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002c0a: b2db uxtb r3, r3 8002c0c: 2b02 cmp r3, #2 8002c0e: d005 beq.n 8002c1c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002c10: 687b ldr r3, [r7, #4] 8002c12: 2204 movs r2, #4 8002c14: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8002c16: 2301 movs r3, #1 8002c18: 73fb strb r3, [r7, #15] 8002c1a: e051 b.n 8002cc0 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 681b ldr r3, [r3, #0] 8002c20: 681a ldr r2, [r3, #0] 8002c22: 687b ldr r3, [r7, #4] 8002c24: 681b ldr r3, [r3, #0] 8002c26: f022 020e bic.w r2, r2, #14 8002c2a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002c2c: 687b ldr r3, [r7, #4] 8002c2e: 681b ldr r3, [r3, #0] 8002c30: 681a ldr r2, [r3, #0] 8002c32: 687b ldr r3, [r7, #4] 8002c34: 681b ldr r3, [r3, #0] 8002c36: f022 0201 bic.w r2, r2, #1 8002c3a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8002c3c: 687b ldr r3, [r7, #4] 8002c3e: 681b ldr r3, [r3, #0] 8002c40: 4a22 ldr r2, [pc, #136] @ (8002ccc ) 8002c42: 4293 cmp r3, r2 8002c44: d029 beq.n 8002c9a 8002c46: 687b ldr r3, [r7, #4] 8002c48: 681b ldr r3, [r3, #0] 8002c4a: 4a21 ldr r2, [pc, #132] @ (8002cd0 ) 8002c4c: 4293 cmp r3, r2 8002c4e: d022 beq.n 8002c96 8002c50: 687b ldr r3, [r7, #4] 8002c52: 681b ldr r3, [r3, #0] 8002c54: 4a1f ldr r2, [pc, #124] @ (8002cd4 ) 8002c56: 4293 cmp r3, r2 8002c58: d01a beq.n 8002c90 8002c5a: 687b ldr r3, [r7, #4] 8002c5c: 681b ldr r3, [r3, #0] 8002c5e: 4a1e ldr r2, [pc, #120] @ (8002cd8 ) 8002c60: 4293 cmp r3, r2 8002c62: d012 beq.n 8002c8a 8002c64: 687b ldr r3, [r7, #4] 8002c66: 681b ldr r3, [r3, #0] 8002c68: 4a1c ldr r2, [pc, #112] @ (8002cdc ) 8002c6a: 4293 cmp r3, r2 8002c6c: d00a beq.n 8002c84 8002c6e: 687b ldr r3, [r7, #4] 8002c70: 681b ldr r3, [r3, #0] 8002c72: 4a1b ldr r2, [pc, #108] @ (8002ce0 ) 8002c74: 4293 cmp r3, r2 8002c76: d102 bne.n 8002c7e 8002c78: f44f 1380 mov.w r3, #1048576 @ 0x100000 8002c7c: e00e b.n 8002c9c 8002c7e: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8002c82: e00b b.n 8002c9c 8002c84: f44f 3380 mov.w r3, #65536 @ 0x10000 8002c88: e008 b.n 8002c9c 8002c8a: f44f 5380 mov.w r3, #4096 @ 0x1000 8002c8e: e005 b.n 8002c9c 8002c90: f44f 7380 mov.w r3, #256 @ 0x100 8002c94: e002 b.n 8002c9c 8002c96: 2310 movs r3, #16 8002c98: e000 b.n 8002c9c 8002c9a: 2301 movs r3, #1 8002c9c: 4a11 ldr r2, [pc, #68] @ (8002ce4 ) 8002c9e: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 2201 movs r2, #1 8002ca4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002ca8: 687b ldr r3, [r7, #4] 8002caa: 2200 movs r2, #0 8002cac: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002cb0: 687b ldr r3, [r7, #4] 8002cb2: 6b5b ldr r3, [r3, #52] @ 0x34 8002cb4: 2b00 cmp r3, #0 8002cb6: d003 beq.n 8002cc0 { hdma->XferAbortCallback(hdma); 8002cb8: 687b ldr r3, [r7, #4] 8002cba: 6b5b ldr r3, [r3, #52] @ 0x34 8002cbc: 6878 ldr r0, [r7, #4] 8002cbe: 4798 blx r3 } } return status; 8002cc0: 7bfb ldrb r3, [r7, #15] } 8002cc2: 4618 mov r0, r3 8002cc4: 3710 adds r7, #16 8002cc6: 46bd mov sp, r7 8002cc8: bd80 pop {r7, pc} 8002cca: bf00 nop 8002ccc: 40020008 .word 0x40020008 8002cd0: 4002001c .word 0x4002001c 8002cd4: 40020030 .word 0x40020030 8002cd8: 40020044 .word 0x40020044 8002cdc: 40020058 .word 0x40020058 8002ce0: 4002006c .word 0x4002006c 8002ce4: 40020000 .word 0x40020000 08002ce8 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002ce8: b480 push {r7} 8002cea: b08b sub sp, #44 @ 0x2c 8002cec: af00 add r7, sp, #0 8002cee: 6078 str r0, [r7, #4] 8002cf0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8002cf2: 2300 movs r3, #0 8002cf4: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8002cf6: 2300 movs r3, #0 8002cf8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8002cfa: e169 b.n 8002fd0 { /* Get the IO position */ ioposition = (0x01uL << position); 8002cfc: 2201 movs r2, #1 8002cfe: 6a7b ldr r3, [r7, #36] @ 0x24 8002d00: fa02 f303 lsl.w r3, r2, r3 8002d04: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002d06: 683b ldr r3, [r7, #0] 8002d08: 681b ldr r3, [r3, #0] 8002d0a: 69fa ldr r2, [r7, #28] 8002d0c: 4013 ands r3, r2 8002d0e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8002d10: 69ba ldr r2, [r7, #24] 8002d12: 69fb ldr r3, [r7, #28] 8002d14: 429a cmp r2, r3 8002d16: f040 8158 bne.w 8002fca { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8002d1a: 683b ldr r3, [r7, #0] 8002d1c: 685b ldr r3, [r3, #4] 8002d1e: 4a9a ldr r2, [pc, #616] @ (8002f88