Fertirrega_v6.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00005ddc 0800010c 0800010c 0000110c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000080 08005ee8 08005ee8 00006ee8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08005f68 08005f68 00007078 2**0 CONTENTS, READONLY 4 .ARM 00000008 08005f68 08005f68 00006f68 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08005f70 08005f70 00007078 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08005f70 08005f70 00006f70 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08005f74 08005f74 00006f74 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000078 20000000 08005f78 00007000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000003e4 20000078 08005ff0 00007078 2**2 ALLOC 10 ._user_heap_stack 00000604 2000045c 08005ff0 0000745c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00007078 2**0 CONTENTS, READONLY 12 .debug_info 0000e8a7 00000000 00000000 000070a1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002ca8 00000000 00000000 00015948 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000cb8 00000000 00000000 000185f0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 000009da 00000000 00000000 000192a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00019336 00000000 00000000 00019c82 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00012131 00000000 00000000 00032fb8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0008c894 00000000 00000000 000450e9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000d197d 2**0 CONTENTS, READONLY 20 .debug_frame 00003488 00000000 00000000 000d19c0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000052 00000000 00000000 000d4e48 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 20000078 .word 0x20000078 8000128: 00000000 .word 0x00000000 800012c: 08005ed0 .word 0x08005ed0 08000130 : 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] @ (8000140 ) 8000134: b11b cbz r3, 800013e 8000136: 4903 ldr r1, [pc, #12] @ (8000144 ) 8000138: 4803 ldr r0, [pc, #12] @ (8000148 ) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 2000007c .word 0x2000007c 8000148: 08005ed0 .word 0x08005ed0 0800014c : 800014c: 4603 mov r3, r0 800014e: f813 2b01 ldrb.w r2, [r3], #1 8000152: 2a00 cmp r2, #0 8000154: d1fb bne.n 800014e 8000156: 1a18 subs r0, r3, r0 8000158: 3801 subs r0, #1 800015a: 4770 bx lr 0800015c <__aeabi_dmul>: 800015c: b570 push {r4, r5, r6, lr} 800015e: f04f 0cff mov.w ip, #255 @ 0xff 8000162: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 8000166: ea1c 5411 ands.w r4, ip, r1, lsr #20 800016a: bf1d ittte ne 800016c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000170: ea94 0f0c teqne r4, ip 8000174: ea95 0f0c teqne r5, ip 8000178: f000 f8de bleq 8000338 <__aeabi_dmul+0x1dc> 800017c: 442c add r4, r5 800017e: ea81 0603 eor.w r6, r1, r3 8000182: ea21 514c bic.w r1, r1, ip, lsl #21 8000186: ea23 534c bic.w r3, r3, ip, lsl #21 800018a: ea50 3501 orrs.w r5, r0, r1, lsl #12 800018e: bf18 it ne 8000190: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000194: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000198: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800019c: d038 beq.n 8000210 <__aeabi_dmul+0xb4> 800019e: fba0 ce02 umull ip, lr, r0, r2 80001a2: f04f 0500 mov.w r5, #0 80001a6: fbe1 e502 umlal lr, r5, r1, r2 80001aa: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 80001ae: fbe0 e503 umlal lr, r5, r0, r3 80001b2: f04f 0600 mov.w r6, #0 80001b6: fbe1 5603 umlal r5, r6, r1, r3 80001ba: f09c 0f00 teq ip, #0 80001be: bf18 it ne 80001c0: f04e 0e01 orrne.w lr, lr, #1 80001c4: f1a4 04ff sub.w r4, r4, #255 @ 0xff 80001c8: f5b6 7f00 cmp.w r6, #512 @ 0x200 80001cc: f564 7440 sbc.w r4, r4, #768 @ 0x300 80001d0: d204 bcs.n 80001dc <__aeabi_dmul+0x80> 80001d2: ea5f 0e4e movs.w lr, lr, lsl #1 80001d6: 416d adcs r5, r5 80001d8: eb46 0606 adc.w r6, r6, r6 80001dc: ea42 21c6 orr.w r1, r2, r6, lsl #11 80001e0: ea41 5155 orr.w r1, r1, r5, lsr #21 80001e4: ea4f 20c5 mov.w r0, r5, lsl #11 80001e8: ea40 505e orr.w r0, r0, lr, lsr #21 80001ec: ea4f 2ece mov.w lr, lr, lsl #11 80001f0: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 80001f4: bf88 it hi 80001f6: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 80001fa: d81e bhi.n 800023a <__aeabi_dmul+0xde> 80001fc: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8000200: bf08 it eq 8000202: ea5f 0e50 movseq.w lr, r0, lsr #1 8000206: f150 0000 adcs.w r0, r0, #0 800020a: eb41 5104 adc.w r1, r1, r4, lsl #20 800020e: bd70 pop {r4, r5, r6, pc} 8000210: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8000214: ea46 0101 orr.w r1, r6, r1 8000218: ea40 0002 orr.w r0, r0, r2 800021c: ea81 0103 eor.w r1, r1, r3 8000220: ebb4 045c subs.w r4, r4, ip, lsr #1 8000224: bfc2 ittt gt 8000226: ebd4 050c rsbsgt r5, r4, ip 800022a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800022e: bd70 popgt {r4, r5, r6, pc} 8000230: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000234: f04f 0e00 mov.w lr, #0 8000238: 3c01 subs r4, #1 800023a: f300 80ab bgt.w 8000394 <__aeabi_dmul+0x238> 800023e: f114 0f36 cmn.w r4, #54 @ 0x36 8000242: bfde ittt le 8000244: 2000 movle r0, #0 8000246: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800024a: bd70 pople {r4, r5, r6, pc} 800024c: f1c4 0400 rsb r4, r4, #0 8000250: 3c20 subs r4, #32 8000252: da35 bge.n 80002c0 <__aeabi_dmul+0x164> 8000254: 340c adds r4, #12 8000256: dc1b bgt.n 8000290 <__aeabi_dmul+0x134> 8000258: f104 0414 add.w r4, r4, #20 800025c: f1c4 0520 rsb r5, r4, #32 8000260: fa00 f305 lsl.w r3, r0, r5 8000264: fa20 f004 lsr.w r0, r0, r4 8000268: fa01 f205 lsl.w r2, r1, r5 800026c: ea40 0002 orr.w r0, r0, r2 8000270: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 8000274: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000278: eb10 70d3 adds.w r0, r0, r3, lsr #31 800027c: fa21 f604 lsr.w r6, r1, r4 8000280: eb42 0106 adc.w r1, r2, r6 8000284: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000288: bf08 it eq 800028a: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800028e: bd70 pop {r4, r5, r6, pc} 8000290: f1c4 040c rsb r4, r4, #12 8000294: f1c4 0520 rsb r5, r4, #32 8000298: fa00 f304 lsl.w r3, r0, r4 800029c: fa20 f005 lsr.w r0, r0, r5 80002a0: fa01 f204 lsl.w r2, r1, r4 80002a4: ea40 0002 orr.w r0, r0, r2 80002a8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80002ac: eb10 70d3 adds.w r0, r0, r3, lsr #31 80002b0: f141 0100 adc.w r1, r1, #0 80002b4: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80002b8: bf08 it eq 80002ba: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80002be: bd70 pop {r4, r5, r6, pc} 80002c0: f1c4 0520 rsb r5, r4, #32 80002c4: fa00 f205 lsl.w r2, r0, r5 80002c8: ea4e 0e02 orr.w lr, lr, r2 80002cc: fa20 f304 lsr.w r3, r0, r4 80002d0: fa01 f205 lsl.w r2, r1, r5 80002d4: ea43 0302 orr.w r3, r3, r2 80002d8: fa21 f004 lsr.w r0, r1, r4 80002dc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80002e0: fa21 f204 lsr.w r2, r1, r4 80002e4: ea20 0002 bic.w r0, r0, r2 80002e8: eb00 70d3 add.w r0, r0, r3, lsr #31 80002ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80002f0: bf08 it eq 80002f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80002f6: bd70 pop {r4, r5, r6, pc} 80002f8: f094 0f00 teq r4, #0 80002fc: d10f bne.n 800031e <__aeabi_dmul+0x1c2> 80002fe: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8000302: 0040 lsls r0, r0, #1 8000304: eb41 0101 adc.w r1, r1, r1 8000308: f411 1f80 tst.w r1, #1048576 @ 0x100000 800030c: bf08 it eq 800030e: 3c01 subeq r4, #1 8000310: d0f7 beq.n 8000302 <__aeabi_dmul+0x1a6> 8000312: ea41 0106 orr.w r1, r1, r6 8000316: f095 0f00 teq r5, #0 800031a: bf18 it ne 800031c: 4770 bxne lr 800031e: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8000322: 0052 lsls r2, r2, #1 8000324: eb43 0303 adc.w r3, r3, r3 8000328: f413 1f80 tst.w r3, #1048576 @ 0x100000 800032c: bf08 it eq 800032e: 3d01 subeq r5, #1 8000330: d0f7 beq.n 8000322 <__aeabi_dmul+0x1c6> 8000332: ea43 0306 orr.w r3, r3, r6 8000336: 4770 bx lr 8000338: ea94 0f0c teq r4, ip 800033c: ea0c 5513 and.w r5, ip, r3, lsr #20 8000340: bf18 it ne 8000342: ea95 0f0c teqne r5, ip 8000346: d00c beq.n 8000362 <__aeabi_dmul+0x206> 8000348: ea50 0641 orrs.w r6, r0, r1, lsl #1 800034c: bf18 it ne 800034e: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8000352: d1d1 bne.n 80002f8 <__aeabi_dmul+0x19c> 8000354: ea81 0103 eor.w r1, r1, r3 8000358: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 800035c: f04f 0000 mov.w r0, #0 8000360: bd70 pop {r4, r5, r6, pc} 8000362: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000366: bf06 itte eq 8000368: 4610 moveq r0, r2 800036a: 4619 moveq r1, r3 800036c: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8000370: d019 beq.n 80003a6 <__aeabi_dmul+0x24a> 8000372: ea94 0f0c teq r4, ip 8000376: d102 bne.n 800037e <__aeabi_dmul+0x222> 8000378: ea50 3601 orrs.w r6, r0, r1, lsl #12 800037c: d113 bne.n 80003a6 <__aeabi_dmul+0x24a> 800037e: ea95 0f0c teq r5, ip 8000382: d105 bne.n 8000390 <__aeabi_dmul+0x234> 8000384: ea52 3603 orrs.w r6, r2, r3, lsl #12 8000388: bf1c itt ne 800038a: 4610 movne r0, r2 800038c: 4619 movne r1, r3 800038e: d10a bne.n 80003a6 <__aeabi_dmul+0x24a> 8000390: ea81 0103 eor.w r1, r1, r3 8000394: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000398: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 800039c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80003a0: f04f 0000 mov.w r0, #0 80003a4: bd70 pop {r4, r5, r6, pc} 80003a6: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80003aa: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 80003ae: bd70 pop {r4, r5, r6, pc} 080003b0 <__aeabi_drsub>: 80003b0: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 80003b4: e002 b.n 80003bc <__adddf3> 80003b6: bf00 nop 080003b8 <__aeabi_dsub>: 80003b8: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 080003bc <__adddf3>: 80003bc: b530 push {r4, r5, lr} 80003be: ea4f 0441 mov.w r4, r1, lsl #1 80003c2: ea4f 0543 mov.w r5, r3, lsl #1 80003c6: ea94 0f05 teq r4, r5 80003ca: bf08 it eq 80003cc: ea90 0f02 teqeq r0, r2 80003d0: bf1f itttt ne 80003d2: ea54 0c00 orrsne.w ip, r4, r0 80003d6: ea55 0c02 orrsne.w ip, r5, r2 80003da: ea7f 5c64 mvnsne.w ip, r4, asr #21 80003de: ea7f 5c65 mvnsne.w ip, r5, asr #21 80003e2: f000 80e2 beq.w 80005aa <__adddf3+0x1ee> 80003e6: ea4f 5454 mov.w r4, r4, lsr #21 80003ea: ebd4 5555 rsbs r5, r4, r5, lsr #21 80003ee: bfb8 it lt 80003f0: 426d neglt r5, r5 80003f2: dd0c ble.n 800040e <__adddf3+0x52> 80003f4: 442c add r4, r5 80003f6: ea80 0202 eor.w r2, r0, r2 80003fa: ea81 0303 eor.w r3, r1, r3 80003fe: ea82 0000 eor.w r0, r2, r0 8000402: ea83 0101 eor.w r1, r3, r1 8000406: ea80 0202 eor.w r2, r0, r2 800040a: ea81 0303 eor.w r3, r1, r3 800040e: 2d36 cmp r5, #54 @ 0x36 8000410: bf88 it hi 8000412: bd30 pophi {r4, r5, pc} 8000414: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000418: ea4f 3101 mov.w r1, r1, lsl #12 800041c: f44f 1c80 mov.w ip, #1048576 @ 0x100000 8000420: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000424: d002 beq.n 800042c <__adddf3+0x70> 8000426: 4240 negs r0, r0 8000428: eb61 0141 sbc.w r1, r1, r1, lsl #1 800042c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 8000430: ea4f 3303 mov.w r3, r3, lsl #12 8000434: ea4c 3313 orr.w r3, ip, r3, lsr #12 8000438: d002 beq.n 8000440 <__adddf3+0x84> 800043a: 4252 negs r2, r2 800043c: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000440: ea94 0f05 teq r4, r5 8000444: f000 80a7 beq.w 8000596 <__adddf3+0x1da> 8000448: f1a4 0401 sub.w r4, r4, #1 800044c: f1d5 0e20 rsbs lr, r5, #32 8000450: db0d blt.n 800046e <__adddf3+0xb2> 8000452: fa02 fc0e lsl.w ip, r2, lr 8000456: fa22 f205 lsr.w r2, r2, r5 800045a: 1880 adds r0, r0, r2 800045c: f141 0100 adc.w r1, r1, #0 8000460: fa03 f20e lsl.w r2, r3, lr 8000464: 1880 adds r0, r0, r2 8000466: fa43 f305 asr.w r3, r3, r5 800046a: 4159 adcs r1, r3 800046c: e00e b.n 800048c <__adddf3+0xd0> 800046e: f1a5 0520 sub.w r5, r5, #32 8000472: f10e 0e20 add.w lr, lr, #32 8000476: 2a01 cmp r2, #1 8000478: fa03 fc0e lsl.w ip, r3, lr 800047c: bf28 it cs 800047e: f04c 0c02 orrcs.w ip, ip, #2 8000482: fa43 f305 asr.w r3, r3, r5 8000486: 18c0 adds r0, r0, r3 8000488: eb51 71e3 adcs.w r1, r1, r3, asr #31 800048c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000490: d507 bpl.n 80004a2 <__adddf3+0xe6> 8000492: f04f 0e00 mov.w lr, #0 8000496: f1dc 0c00 rsbs ip, ip, #0 800049a: eb7e 0000 sbcs.w r0, lr, r0 800049e: eb6e 0101 sbc.w r1, lr, r1 80004a2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 80004a6: d31b bcc.n 80004e0 <__adddf3+0x124> 80004a8: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 80004ac: d30c bcc.n 80004c8 <__adddf3+0x10c> 80004ae: 0849 lsrs r1, r1, #1 80004b0: ea5f 0030 movs.w r0, r0, rrx 80004b4: ea4f 0c3c mov.w ip, ip, rrx 80004b8: f104 0401 add.w r4, r4, #1 80004bc: ea4f 5244 mov.w r2, r4, lsl #21 80004c0: f512 0f80 cmn.w r2, #4194304 @ 0x400000 80004c4: f080 809a bcs.w 80005fc <__adddf3+0x240> 80004c8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 80004cc: bf08 it eq 80004ce: ea5f 0c50 movseq.w ip, r0, lsr #1 80004d2: f150 0000 adcs.w r0, r0, #0 80004d6: eb41 5104 adc.w r1, r1, r4, lsl #20 80004da: ea41 0105 orr.w r1, r1, r5 80004de: bd30 pop {r4, r5, pc} 80004e0: ea5f 0c4c movs.w ip, ip, lsl #1 80004e4: 4140 adcs r0, r0 80004e6: eb41 0101 adc.w r1, r1, r1 80004ea: 3c01 subs r4, #1 80004ec: bf28 it cs 80004ee: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 80004f2: d2e9 bcs.n 80004c8 <__adddf3+0x10c> 80004f4: f091 0f00 teq r1, #0 80004f8: bf04 itt eq 80004fa: 4601 moveq r1, r0 80004fc: 2000 moveq r0, #0 80004fe: fab1 f381 clz r3, r1 8000502: bf08 it eq 8000504: 3320 addeq r3, #32 8000506: f1a3 030b sub.w r3, r3, #11 800050a: f1b3 0220 subs.w r2, r3, #32 800050e: da0c bge.n 800052a <__adddf3+0x16e> 8000510: 320c adds r2, #12 8000512: dd08 ble.n 8000526 <__adddf3+0x16a> 8000514: f102 0c14 add.w ip, r2, #20 8000518: f1c2 020c rsb r2, r2, #12 800051c: fa01 f00c lsl.w r0, r1, ip 8000520: fa21 f102 lsr.w r1, r1, r2 8000524: e00c b.n 8000540 <__adddf3+0x184> 8000526: f102 0214 add.w r2, r2, #20 800052a: bfd8 it le 800052c: f1c2 0c20 rsble ip, r2, #32 8000530: fa01 f102 lsl.w r1, r1, r2 8000534: fa20 fc0c lsr.w ip, r0, ip 8000538: bfdc itt le 800053a: ea41 010c orrle.w r1, r1, ip 800053e: 4090 lslle r0, r2 8000540: 1ae4 subs r4, r4, r3 8000542: bfa2 ittt ge 8000544: eb01 5104 addge.w r1, r1, r4, lsl #20 8000548: 4329 orrge r1, r5 800054a: bd30 popge {r4, r5, pc} 800054c: ea6f 0404 mvn.w r4, r4 8000550: 3c1f subs r4, #31 8000552: da1c bge.n 800058e <__adddf3+0x1d2> 8000554: 340c adds r4, #12 8000556: dc0e bgt.n 8000576 <__adddf3+0x1ba> 8000558: f104 0414 add.w r4, r4, #20 800055c: f1c4 0220 rsb r2, r4, #32 8000560: fa20 f004 lsr.w r0, r0, r4 8000564: fa01 f302 lsl.w r3, r1, r2 8000568: ea40 0003 orr.w r0, r0, r3 800056c: fa21 f304 lsr.w r3, r1, r4 8000570: ea45 0103 orr.w r1, r5, r3 8000574: bd30 pop {r4, r5, pc} 8000576: f1c4 040c rsb r4, r4, #12 800057a: f1c4 0220 rsb r2, r4, #32 800057e: fa20 f002 lsr.w r0, r0, r2 8000582: fa01 f304 lsl.w r3, r1, r4 8000586: ea40 0003 orr.w r0, r0, r3 800058a: 4629 mov r1, r5 800058c: bd30 pop {r4, r5, pc} 800058e: fa21 f004 lsr.w r0, r1, r4 8000592: 4629 mov r1, r5 8000594: bd30 pop {r4, r5, pc} 8000596: f094 0f00 teq r4, #0 800059a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 800059e: bf06 itte eq 80005a0: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 80005a4: 3401 addeq r4, #1 80005a6: 3d01 subne r5, #1 80005a8: e74e b.n 8000448 <__adddf3+0x8c> 80005aa: ea7f 5c64 mvns.w ip, r4, asr #21 80005ae: bf18 it ne 80005b0: ea7f 5c65 mvnsne.w ip, r5, asr #21 80005b4: d029 beq.n 800060a <__adddf3+0x24e> 80005b6: ea94 0f05 teq r4, r5 80005ba: bf08 it eq 80005bc: ea90 0f02 teqeq r0, r2 80005c0: d005 beq.n 80005ce <__adddf3+0x212> 80005c2: ea54 0c00 orrs.w ip, r4, r0 80005c6: bf04 itt eq 80005c8: 4619 moveq r1, r3 80005ca: 4610 moveq r0, r2 80005cc: bd30 pop {r4, r5, pc} 80005ce: ea91 0f03 teq r1, r3 80005d2: bf1e ittt ne 80005d4: 2100 movne r1, #0 80005d6: 2000 movne r0, #0 80005d8: bd30 popne {r4, r5, pc} 80005da: ea5f 5c54 movs.w ip, r4, lsr #21 80005de: d105 bne.n 80005ec <__adddf3+0x230> 80005e0: 0040 lsls r0, r0, #1 80005e2: 4149 adcs r1, r1 80005e4: bf28 it cs 80005e6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 80005ea: bd30 pop {r4, r5, pc} 80005ec: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 80005f0: bf3c itt cc 80005f2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 80005f6: bd30 popcc {r4, r5, pc} 80005f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 80005fc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8000600: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8000604: f04f 0000 mov.w r0, #0 8000608: bd30 pop {r4, r5, pc} 800060a: ea7f 5c64 mvns.w ip, r4, asr #21 800060e: bf1a itte ne 8000610: 4619 movne r1, r3 8000612: 4610 movne r0, r2 8000614: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000618: bf1c itt ne 800061a: 460b movne r3, r1 800061c: 4602 movne r2, r0 800061e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000622: bf06 itte eq 8000624: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000628: ea91 0f03 teqeq r1, r3 800062c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 8000630: bd30 pop {r4, r5, pc} 8000632: bf00 nop 08000634 <__aeabi_ui2d>: 8000634: f090 0f00 teq r0, #0 8000638: bf04 itt eq 800063a: 2100 moveq r1, #0 800063c: 4770 bxeq lr 800063e: b530 push {r4, r5, lr} 8000640: f44f 6480 mov.w r4, #1024 @ 0x400 8000644: f104 0432 add.w r4, r4, #50 @ 0x32 8000648: f04f 0500 mov.w r5, #0 800064c: f04f 0100 mov.w r1, #0 8000650: e750 b.n 80004f4 <__adddf3+0x138> 8000652: bf00 nop 08000654 <__aeabi_i2d>: 8000654: f090 0f00 teq r0, #0 8000658: bf04 itt eq 800065a: 2100 moveq r1, #0 800065c: 4770 bxeq lr 800065e: b530 push {r4, r5, lr} 8000660: f44f 6480 mov.w r4, #1024 @ 0x400 8000664: f104 0432 add.w r4, r4, #50 @ 0x32 8000668: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 800066c: bf48 it mi 800066e: 4240 negmi r0, r0 8000670: f04f 0100 mov.w r1, #0 8000674: e73e b.n 80004f4 <__adddf3+0x138> 8000676: bf00 nop 08000678 <__aeabi_f2d>: 8000678: 0042 lsls r2, r0, #1 800067a: ea4f 01e2 mov.w r1, r2, asr #3 800067e: ea4f 0131 mov.w r1, r1, rrx 8000682: ea4f 7002 mov.w r0, r2, lsl #28 8000686: bf1f itttt ne 8000688: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 800068c: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8000690: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 8000694: 4770 bxne lr 8000696: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 800069a: bf08 it eq 800069c: 4770 bxeq lr 800069e: f093 4f7f teq r3, #4278190080 @ 0xff000000 80006a2: bf04 itt eq 80006a4: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 80006a8: 4770 bxeq lr 80006aa: b530 push {r4, r5, lr} 80006ac: f44f 7460 mov.w r4, #896 @ 0x380 80006b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 80006b4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80006b8: e71c b.n 80004f4 <__adddf3+0x138> 80006ba: bf00 nop 080006bc <__aeabi_ul2d>: 80006bc: ea50 0201 orrs.w r2, r0, r1 80006c0: bf08 it eq 80006c2: 4770 bxeq lr 80006c4: b530 push {r4, r5, lr} 80006c6: f04f 0500 mov.w r5, #0 80006ca: e00a b.n 80006e2 <__aeabi_l2d+0x16> 080006cc <__aeabi_l2d>: 80006cc: ea50 0201 orrs.w r2, r0, r1 80006d0: bf08 it eq 80006d2: 4770 bxeq lr 80006d4: b530 push {r4, r5, lr} 80006d6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 80006da: d502 bpl.n 80006e2 <__aeabi_l2d+0x16> 80006dc: 4240 negs r0, r0 80006de: eb61 0141 sbc.w r1, r1, r1, lsl #1 80006e2: f44f 6480 mov.w r4, #1024 @ 0x400 80006e6: f104 0432 add.w r4, r4, #50 @ 0x32 80006ea: ea5f 5c91 movs.w ip, r1, lsr #22 80006ee: f43f aed8 beq.w 80004a2 <__adddf3+0xe6> 80006f2: f04f 0203 mov.w r2, #3 80006f6: ea5f 0cdc movs.w ip, ip, lsr #3 80006fa: bf18 it ne 80006fc: 3203 addne r2, #3 80006fe: ea5f 0cdc movs.w ip, ip, lsr #3 8000702: bf18 it ne 8000704: 3203 addne r2, #3 8000706: eb02 02dc add.w r2, r2, ip, lsr #3 800070a: f1c2 0320 rsb r3, r2, #32 800070e: fa00 fc03 lsl.w ip, r0, r3 8000712: fa20 f002 lsr.w r0, r0, r2 8000716: fa01 fe03 lsl.w lr, r1, r3 800071a: ea40 000e orr.w r0, r0, lr 800071e: fa21 f102 lsr.w r1, r1, r2 8000722: 4414 add r4, r2 8000724: e6bd b.n 80004a2 <__adddf3+0xe6> 8000726: bf00 nop 08000728 <__aeabi_d2iz>: 8000728: ea4f 0241 mov.w r2, r1, lsl #1 800072c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000730: d215 bcs.n 800075e <__aeabi_d2iz+0x36> 8000732: d511 bpl.n 8000758 <__aeabi_d2iz+0x30> 8000734: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000738: ebb3 5262 subs.w r2, r3, r2, asr #21 800073c: d912 bls.n 8000764 <__aeabi_d2iz+0x3c> 800073e: ea4f 23c1 mov.w r3, r1, lsl #11 8000742: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000746: ea43 5350 orr.w r3, r3, r0, lsr #21 800074a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 800074e: fa23 f002 lsr.w r0, r3, r2 8000752: bf18 it ne 8000754: 4240 negne r0, r0 8000756: 4770 bx lr 8000758: f04f 0000 mov.w r0, #0 800075c: 4770 bx lr 800075e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000762: d105 bne.n 8000770 <__aeabi_d2iz+0x48> 8000764: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8000768: bf08 it eq 800076a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 800076e: 4770 bx lr 8000770: f04f 0000 mov.w r0, #0 8000774: 4770 bx lr 8000776: bf00 nop 08000778 <__aeabi_frsub>: 8000778: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 800077c: e002 b.n 8000784 <__addsf3> 800077e: bf00 nop 08000780 <__aeabi_fsub>: 8000780: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08000784 <__addsf3>: 8000784: 0042 lsls r2, r0, #1 8000786: bf1f itttt ne 8000788: ea5f 0341 movsne.w r3, r1, lsl #1 800078c: ea92 0f03 teqne r2, r3 8000790: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000794: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000798: d06a beq.n 8000870 <__addsf3+0xec> 800079a: ea4f 6212 mov.w r2, r2, lsr #24 800079e: ebd2 6313 rsbs r3, r2, r3, lsr #24 80007a2: bfc1 itttt gt 80007a4: 18d2 addgt r2, r2, r3 80007a6: 4041 eorgt r1, r0 80007a8: 4048 eorgt r0, r1 80007aa: 4041 eorgt r1, r0 80007ac: bfb8 it lt 80007ae: 425b neglt r3, r3 80007b0: 2b19 cmp r3, #25 80007b2: bf88 it hi 80007b4: 4770 bxhi lr 80007b6: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80007ba: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 80007be: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 80007c2: bf18 it ne 80007c4: 4240 negne r0, r0 80007c6: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80007ca: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 80007ce: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 80007d2: bf18 it ne 80007d4: 4249 negne r1, r1 80007d6: ea92 0f03 teq r2, r3 80007da: d03f beq.n 800085c <__addsf3+0xd8> 80007dc: f1a2 0201 sub.w r2, r2, #1 80007e0: fa41 fc03 asr.w ip, r1, r3 80007e4: eb10 000c adds.w r0, r0, ip 80007e8: f1c3 0320 rsb r3, r3, #32 80007ec: fa01 f103 lsl.w r1, r1, r3 80007f0: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 80007f4: d502 bpl.n 80007fc <__addsf3+0x78> 80007f6: 4249 negs r1, r1 80007f8: eb60 0040 sbc.w r0, r0, r0, lsl #1 80007fc: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8000800: d313 bcc.n 800082a <__addsf3+0xa6> 8000802: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8000806: d306 bcc.n 8000816 <__addsf3+0x92> 8000808: 0840 lsrs r0, r0, #1 800080a: ea4f 0131 mov.w r1, r1, rrx 800080e: f102 0201 add.w r2, r2, #1 8000812: 2afe cmp r2, #254 @ 0xfe 8000814: d251 bcs.n 80008ba <__addsf3+0x136> 8000816: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 800081a: eb40 50c2 adc.w r0, r0, r2, lsl #23 800081e: bf08 it eq 8000820: f020 0001 biceq.w r0, r0, #1 8000824: ea40 0003 orr.w r0, r0, r3 8000828: 4770 bx lr 800082a: 0049 lsls r1, r1, #1 800082c: eb40 0000 adc.w r0, r0, r0 8000830: 3a01 subs r2, #1 8000832: bf28 it cs 8000834: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8000838: d2ed bcs.n 8000816 <__addsf3+0x92> 800083a: fab0 fc80 clz ip, r0 800083e: f1ac 0c08 sub.w ip, ip, #8 8000842: ebb2 020c subs.w r2, r2, ip 8000846: fa00 f00c lsl.w r0, r0, ip 800084a: bfaa itet ge 800084c: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000850: 4252 neglt r2, r2 8000852: 4318 orrge r0, r3 8000854: bfbc itt lt 8000856: 40d0 lsrlt r0, r2 8000858: 4318 orrlt r0, r3 800085a: 4770 bx lr 800085c: f092 0f00 teq r2, #0 8000860: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8000864: bf06 itte eq 8000866: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 800086a: 3201 addeq r2, #1 800086c: 3b01 subne r3, #1 800086e: e7b5 b.n 80007dc <__addsf3+0x58> 8000870: ea4f 0341 mov.w r3, r1, lsl #1 8000874: ea7f 6c22 mvns.w ip, r2, asr #24 8000878: bf18 it ne 800087a: ea7f 6c23 mvnsne.w ip, r3, asr #24 800087e: d021 beq.n 80008c4 <__addsf3+0x140> 8000880: ea92 0f03 teq r2, r3 8000884: d004 beq.n 8000890 <__addsf3+0x10c> 8000886: f092 0f00 teq r2, #0 800088a: bf08 it eq 800088c: 4608 moveq r0, r1 800088e: 4770 bx lr 8000890: ea90 0f01 teq r0, r1 8000894: bf1c itt ne 8000896: 2000 movne r0, #0 8000898: 4770 bxne lr 800089a: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 800089e: d104 bne.n 80008aa <__addsf3+0x126> 80008a0: 0040 lsls r0, r0, #1 80008a2: bf28 it cs 80008a4: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 80008a8: 4770 bx lr 80008aa: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 80008ae: bf3c itt cc 80008b0: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 80008b4: 4770 bxcc lr 80008b6: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 80008ba: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 80008be: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 80008c2: 4770 bx lr 80008c4: ea7f 6222 mvns.w r2, r2, asr #24 80008c8: bf16 itet ne 80008ca: 4608 movne r0, r1 80008cc: ea7f 6323 mvnseq.w r3, r3, asr #24 80008d0: 4601 movne r1, r0 80008d2: 0242 lsls r2, r0, #9 80008d4: bf06 itte eq 80008d6: ea5f 2341 movseq.w r3, r1, lsl #9 80008da: ea90 0f01 teqeq r0, r1 80008de: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 80008e2: 4770 bx lr 080008e4 <__aeabi_ui2f>: 80008e4: f04f 0300 mov.w r3, #0 80008e8: e004 b.n 80008f4 <__aeabi_i2f+0x8> 80008ea: bf00 nop 080008ec <__aeabi_i2f>: 80008ec: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 80008f0: bf48 it mi 80008f2: 4240 negmi r0, r0 80008f4: ea5f 0c00 movs.w ip, r0 80008f8: bf08 it eq 80008fa: 4770 bxeq lr 80008fc: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8000900: 4601 mov r1, r0 8000902: f04f 0000 mov.w r0, #0 8000906: e01c b.n 8000942 <__aeabi_l2f+0x2a> 08000908 <__aeabi_ul2f>: 8000908: ea50 0201 orrs.w r2, r0, r1 800090c: bf08 it eq 800090e: 4770 bxeq lr 8000910: f04f 0300 mov.w r3, #0 8000914: e00a b.n 800092c <__aeabi_l2f+0x14> 8000916: bf00 nop 08000918 <__aeabi_l2f>: 8000918: ea50 0201 orrs.w r2, r0, r1 800091c: bf08 it eq 800091e: 4770 bxeq lr 8000920: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8000924: d502 bpl.n 800092c <__aeabi_l2f+0x14> 8000926: 4240 negs r0, r0 8000928: eb61 0141 sbc.w r1, r1, r1, lsl #1 800092c: ea5f 0c01 movs.w ip, r1 8000930: bf02 ittt eq 8000932: 4684 moveq ip, r0 8000934: 4601 moveq r1, r0 8000936: 2000 moveq r0, #0 8000938: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 800093c: bf08 it eq 800093e: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8000942: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8000946: fabc f28c clz r2, ip 800094a: 3a08 subs r2, #8 800094c: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000950: db10 blt.n 8000974 <__aeabi_l2f+0x5c> 8000952: fa01 fc02 lsl.w ip, r1, r2 8000956: 4463 add r3, ip 8000958: fa00 fc02 lsl.w ip, r0, r2 800095c: f1c2 0220 rsb r2, r2, #32 8000960: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8000964: fa20 f202 lsr.w r2, r0, r2 8000968: eb43 0002 adc.w r0, r3, r2 800096c: bf08 it eq 800096e: f020 0001 biceq.w r0, r0, #1 8000972: 4770 bx lr 8000974: f102 0220 add.w r2, r2, #32 8000978: fa01 fc02 lsl.w ip, r1, r2 800097c: f1c2 0220 rsb r2, r2, #32 8000980: ea50 004c orrs.w r0, r0, ip, lsl #1 8000984: fa21 f202 lsr.w r2, r1, r2 8000988: eb43 0002 adc.w r0, r3, r2 800098c: bf08 it eq 800098e: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000992: 4770 bx lr 08000994 <__aeabi_fmul>: 8000994: f04f 0cff mov.w ip, #255 @ 0xff 8000998: ea1c 52d0 ands.w r2, ip, r0, lsr #23 800099c: bf1e ittt ne 800099e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 80009a2: ea92 0f0c teqne r2, ip 80009a6: ea93 0f0c teqne r3, ip 80009aa: d06f beq.n 8000a8c <__aeabi_fmul+0xf8> 80009ac: 441a add r2, r3 80009ae: ea80 0c01 eor.w ip, r0, r1 80009b2: 0240 lsls r0, r0, #9 80009b4: bf18 it ne 80009b6: ea5f 2141 movsne.w r1, r1, lsl #9 80009ba: d01e beq.n 80009fa <__aeabi_fmul+0x66> 80009bc: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80009c0: ea43 1050 orr.w r0, r3, r0, lsr #5 80009c4: ea43 1151 orr.w r1, r3, r1, lsr #5 80009c8: fba0 3101 umull r3, r1, r0, r1 80009cc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 80009d0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 80009d4: bf3e ittt cc 80009d6: 0049 lslcc r1, r1, #1 80009d8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 80009dc: 005b lslcc r3, r3, #1 80009de: ea40 0001 orr.w r0, r0, r1 80009e2: f162 027f sbc.w r2, r2, #127 @ 0x7f 80009e6: 2afd cmp r2, #253 @ 0xfd 80009e8: d81d bhi.n 8000a26 <__aeabi_fmul+0x92> 80009ea: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80009ee: eb40 50c2 adc.w r0, r0, r2, lsl #23 80009f2: bf08 it eq 80009f4: f020 0001 biceq.w r0, r0, #1 80009f8: 4770 bx lr 80009fa: f090 0f00 teq r0, #0 80009fe: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8000a02: bf08 it eq 8000a04: 0249 lsleq r1, r1, #9 8000a06: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000a0a: ea40 2051 orr.w r0, r0, r1, lsr #9 8000a0e: 3a7f subs r2, #127 @ 0x7f 8000a10: bfc2 ittt gt 8000a12: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8000a16: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000a1a: 4770 bxgt lr 8000a1c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000a20: f04f 0300 mov.w r3, #0 8000a24: 3a01 subs r2, #1 8000a26: dc5d bgt.n 8000ae4 <__aeabi_fmul+0x150> 8000a28: f112 0f19 cmn.w r2, #25 8000a2c: bfdc itt le 8000a2e: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8000a32: 4770 bxle lr 8000a34: f1c2 0200 rsb r2, r2, #0 8000a38: 0041 lsls r1, r0, #1 8000a3a: fa21 f102 lsr.w r1, r1, r2 8000a3e: f1c2 0220 rsb r2, r2, #32 8000a42: fa00 fc02 lsl.w ip, r0, r2 8000a46: ea5f 0031 movs.w r0, r1, rrx 8000a4a: f140 0000 adc.w r0, r0, #0 8000a4e: ea53 034c orrs.w r3, r3, ip, lsl #1 8000a52: bf08 it eq 8000a54: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000a58: 4770 bx lr 8000a5a: f092 0f00 teq r2, #0 8000a5e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8000a62: bf02 ittt eq 8000a64: 0040 lsleq r0, r0, #1 8000a66: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8000a6a: 3a01 subeq r2, #1 8000a6c: d0f9 beq.n 8000a62 <__aeabi_fmul+0xce> 8000a6e: ea40 000c orr.w r0, r0, ip 8000a72: f093 0f00 teq r3, #0 8000a76: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000a7a: bf02 ittt eq 8000a7c: 0049 lsleq r1, r1, #1 8000a7e: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8000a82: 3b01 subeq r3, #1 8000a84: d0f9 beq.n 8000a7a <__aeabi_fmul+0xe6> 8000a86: ea41 010c orr.w r1, r1, ip 8000a8a: e78f b.n 80009ac <__aeabi_fmul+0x18> 8000a8c: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000a90: ea92 0f0c teq r2, ip 8000a94: bf18 it ne 8000a96: ea93 0f0c teqne r3, ip 8000a9a: d00a beq.n 8000ab2 <__aeabi_fmul+0x11e> 8000a9c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8000aa0: bf18 it ne 8000aa2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8000aa6: d1d8 bne.n 8000a5a <__aeabi_fmul+0xc6> 8000aa8: ea80 0001 eor.w r0, r0, r1 8000aac: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8000ab0: 4770 bx lr 8000ab2: f090 0f00 teq r0, #0 8000ab6: bf17 itett ne 8000ab8: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8000abc: 4608 moveq r0, r1 8000abe: f091 0f00 teqne r1, #0 8000ac2: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8000ac6: d014 beq.n 8000af2 <__aeabi_fmul+0x15e> 8000ac8: ea92 0f0c teq r2, ip 8000acc: d101 bne.n 8000ad2 <__aeabi_fmul+0x13e> 8000ace: 0242 lsls r2, r0, #9 8000ad0: d10f bne.n 8000af2 <__aeabi_fmul+0x15e> 8000ad2: ea93 0f0c teq r3, ip 8000ad6: d103 bne.n 8000ae0 <__aeabi_fmul+0x14c> 8000ad8: 024b lsls r3, r1, #9 8000ada: bf18 it ne 8000adc: 4608 movne r0, r1 8000ade: d108 bne.n 8000af2 <__aeabi_fmul+0x15e> 8000ae0: ea80 0001 eor.w r0, r0, r1 8000ae4: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8000ae8: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000aec: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000af0: 4770 bx lr 8000af2: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000af6: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8000afa: 4770 bx lr 08000afc <__aeabi_fdiv>: 8000afc: f04f 0cff mov.w ip, #255 @ 0xff 8000b00: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000b04: bf1e ittt ne 8000b06: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000b0a: ea92 0f0c teqne r2, ip 8000b0e: ea93 0f0c teqne r3, ip 8000b12: d069 beq.n 8000be8 <__aeabi_fdiv+0xec> 8000b14: eba2 0203 sub.w r2, r2, r3 8000b18: ea80 0c01 eor.w ip, r0, r1 8000b1c: 0249 lsls r1, r1, #9 8000b1e: ea4f 2040 mov.w r0, r0, lsl #9 8000b22: d037 beq.n 8000b94 <__aeabi_fdiv+0x98> 8000b24: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8000b28: ea43 1111 orr.w r1, r3, r1, lsr #4 8000b2c: ea43 1310 orr.w r3, r3, r0, lsr #4 8000b30: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8000b34: 428b cmp r3, r1 8000b36: bf38 it cc 8000b38: 005b lslcc r3, r3, #1 8000b3a: f142 027d adc.w r2, r2, #125 @ 0x7d 8000b3e: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8000b42: 428b cmp r3, r1 8000b44: bf24 itt cs 8000b46: 1a5b subcs r3, r3, r1 8000b48: ea40 000c orrcs.w r0, r0, ip 8000b4c: ebb3 0f51 cmp.w r3, r1, lsr #1 8000b50: bf24 itt cs 8000b52: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000b56: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000b5a: ebb3 0f91 cmp.w r3, r1, lsr #2 8000b5e: bf24 itt cs 8000b60: eba3 0391 subcs.w r3, r3, r1, lsr #2 8000b64: ea40 009c orrcs.w r0, r0, ip, lsr #2 8000b68: ebb3 0fd1 cmp.w r3, r1, lsr #3 8000b6c: bf24 itt cs 8000b6e: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8000b72: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000b76: 011b lsls r3, r3, #4 8000b78: bf18 it ne 8000b7a: ea5f 1c1c movsne.w ip, ip, lsr #4 8000b7e: d1e0 bne.n 8000b42 <__aeabi_fdiv+0x46> 8000b80: 2afd cmp r2, #253 @ 0xfd 8000b82: f63f af50 bhi.w 8000a26 <__aeabi_fmul+0x92> 8000b86: 428b cmp r3, r1 8000b88: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000b8c: bf08 it eq 8000b8e: f020 0001 biceq.w r0, r0, #1 8000b92: 4770 bx lr 8000b94: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8000b98: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000b9c: 327f adds r2, #127 @ 0x7f 8000b9e: bfc2 ittt gt 8000ba0: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8000ba4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000ba8: 4770 bxgt lr 8000baa: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000bae: f04f 0300 mov.w r3, #0 8000bb2: 3a01 subs r2, #1 8000bb4: e737 b.n 8000a26 <__aeabi_fmul+0x92> 8000bb6: f092 0f00 teq r2, #0 8000bba: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8000bbe: bf02 ittt eq 8000bc0: 0040 lsleq r0, r0, #1 8000bc2: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8000bc6: 3a01 subeq r2, #1 8000bc8: d0f9 beq.n 8000bbe <__aeabi_fdiv+0xc2> 8000bca: ea40 000c orr.w r0, r0, ip 8000bce: f093 0f00 teq r3, #0 8000bd2: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000bd6: bf02 ittt eq 8000bd8: 0049 lsleq r1, r1, #1 8000bda: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8000bde: 3b01 subeq r3, #1 8000be0: d0f9 beq.n 8000bd6 <__aeabi_fdiv+0xda> 8000be2: ea41 010c orr.w r1, r1, ip 8000be6: e795 b.n 8000b14 <__aeabi_fdiv+0x18> 8000be8: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000bec: ea92 0f0c teq r2, ip 8000bf0: d108 bne.n 8000c04 <__aeabi_fdiv+0x108> 8000bf2: 0242 lsls r2, r0, #9 8000bf4: f47f af7d bne.w 8000af2 <__aeabi_fmul+0x15e> 8000bf8: ea93 0f0c teq r3, ip 8000bfc: f47f af70 bne.w 8000ae0 <__aeabi_fmul+0x14c> 8000c00: 4608 mov r0, r1 8000c02: e776 b.n 8000af2 <__aeabi_fmul+0x15e> 8000c04: ea93 0f0c teq r3, ip 8000c08: d104 bne.n 8000c14 <__aeabi_fdiv+0x118> 8000c0a: 024b lsls r3, r1, #9 8000c0c: f43f af4c beq.w 8000aa8 <__aeabi_fmul+0x114> 8000c10: 4608 mov r0, r1 8000c12: e76e b.n 8000af2 <__aeabi_fmul+0x15e> 8000c14: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8000c18: bf18 it ne 8000c1a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8000c1e: d1ca bne.n 8000bb6 <__aeabi_fdiv+0xba> 8000c20: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 8000c24: f47f af5c bne.w 8000ae0 <__aeabi_fmul+0x14c> 8000c28: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 8000c2c: f47f af3c bne.w 8000aa8 <__aeabi_fmul+0x114> 8000c30: e75f b.n 8000af2 <__aeabi_fmul+0x15e> 8000c32: bf00 nop 08000c34 <__gesf2>: 8000c34: f04f 3cff mov.w ip, #4294967295 8000c38: e006 b.n 8000c48 <__cmpsf2+0x4> 8000c3a: bf00 nop 08000c3c <__lesf2>: 8000c3c: f04f 0c01 mov.w ip, #1 8000c40: e002 b.n 8000c48 <__cmpsf2+0x4> 8000c42: bf00 nop 08000c44 <__cmpsf2>: 8000c44: f04f 0c01 mov.w ip, #1 8000c48: f84d cd04 str.w ip, [sp, #-4]! 8000c4c: ea4f 0240 mov.w r2, r0, lsl #1 8000c50: ea4f 0341 mov.w r3, r1, lsl #1 8000c54: ea7f 6c22 mvns.w ip, r2, asr #24 8000c58: bf18 it ne 8000c5a: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000c5e: d011 beq.n 8000c84 <__cmpsf2+0x40> 8000c60: b001 add sp, #4 8000c62: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8000c66: bf18 it ne 8000c68: ea90 0f01 teqne r0, r1 8000c6c: bf58 it pl 8000c6e: ebb2 0003 subspl.w r0, r2, r3 8000c72: bf88 it hi 8000c74: 17c8 asrhi r0, r1, #31 8000c76: bf38 it cc 8000c78: ea6f 70e1 mvncc.w r0, r1, asr #31 8000c7c: bf18 it ne 8000c7e: f040 0001 orrne.w r0, r0, #1 8000c82: 4770 bx lr 8000c84: ea7f 6c22 mvns.w ip, r2, asr #24 8000c88: d102 bne.n 8000c90 <__cmpsf2+0x4c> 8000c8a: ea5f 2c40 movs.w ip, r0, lsl #9 8000c8e: d105 bne.n 8000c9c <__cmpsf2+0x58> 8000c90: ea7f 6c23 mvns.w ip, r3, asr #24 8000c94: d1e4 bne.n 8000c60 <__cmpsf2+0x1c> 8000c96: ea5f 2c41 movs.w ip, r1, lsl #9 8000c9a: d0e1 beq.n 8000c60 <__cmpsf2+0x1c> 8000c9c: f85d 0b04 ldr.w r0, [sp], #4 8000ca0: 4770 bx lr 8000ca2: bf00 nop 08000ca4 <__aeabi_cfrcmple>: 8000ca4: 4684 mov ip, r0 8000ca6: 4608 mov r0, r1 8000ca8: 4661 mov r1, ip 8000caa: e7ff b.n 8000cac <__aeabi_cfcmpeq> 08000cac <__aeabi_cfcmpeq>: 8000cac: b50f push {r0, r1, r2, r3, lr} 8000cae: f7ff ffc9 bl 8000c44 <__cmpsf2> 8000cb2: 2800 cmp r0, #0 8000cb4: bf48 it mi 8000cb6: f110 0f00 cmnmi.w r0, #0 8000cba: bd0f pop {r0, r1, r2, r3, pc} 08000cbc <__aeabi_fcmpeq>: 8000cbc: f84d ed08 str.w lr, [sp, #-8]! 8000cc0: f7ff fff4 bl 8000cac <__aeabi_cfcmpeq> 8000cc4: bf0c ite eq 8000cc6: 2001 moveq r0, #1 8000cc8: 2000 movne r0, #0 8000cca: f85d fb08 ldr.w pc, [sp], #8 8000cce: bf00 nop 08000cd0 <__aeabi_fcmplt>: 8000cd0: f84d ed08 str.w lr, [sp, #-8]! 8000cd4: f7ff ffea bl 8000cac <__aeabi_cfcmpeq> 8000cd8: bf34 ite cc 8000cda: 2001 movcc r0, #1 8000cdc: 2000 movcs r0, #0 8000cde: f85d fb08 ldr.w pc, [sp], #8 8000ce2: bf00 nop 08000ce4 <__aeabi_fcmple>: 8000ce4: f84d ed08 str.w lr, [sp, #-8]! 8000ce8: f7ff ffe0 bl 8000cac <__aeabi_cfcmpeq> 8000cec: bf94 ite ls 8000cee: 2001 movls r0, #1 8000cf0: 2000 movhi r0, #0 8000cf2: f85d fb08 ldr.w pc, [sp], #8 8000cf6: bf00 nop 08000cf8 <__aeabi_fcmpge>: 8000cf8: f84d ed08 str.w lr, [sp, #-8]! 8000cfc: f7ff ffd2 bl 8000ca4 <__aeabi_cfrcmple> 8000d00: bf94 ite ls 8000d02: 2001 movls r0, #1 8000d04: 2000 movhi r0, #0 8000d06: f85d fb08 ldr.w pc, [sp], #8 8000d0a: bf00 nop 08000d0c <__aeabi_fcmpgt>: 8000d0c: f84d ed08 str.w lr, [sp, #-8]! 8000d10: f7ff ffc8 bl 8000ca4 <__aeabi_cfrcmple> 8000d14: bf34 ite cc 8000d16: 2001 movcc r0, #1 8000d18: 2000 movcs r0, #0 8000d1a: f85d fb08 ldr.w pc, [sp], #8 8000d1e: bf00 nop 08000d20 <__aeabi_fcmpun>: 8000d20: ea4f 0240 mov.w r2, r0, lsl #1 8000d24: ea4f 0341 mov.w r3, r1, lsl #1 8000d28: ea7f 6c22 mvns.w ip, r2, asr #24 8000d2c: d102 bne.n 8000d34 <__aeabi_fcmpun+0x14> 8000d2e: ea5f 2c40 movs.w ip, r0, lsl #9 8000d32: d108 bne.n 8000d46 <__aeabi_fcmpun+0x26> 8000d34: ea7f 6c23 mvns.w ip, r3, asr #24 8000d38: d102 bne.n 8000d40 <__aeabi_fcmpun+0x20> 8000d3a: ea5f 2c41 movs.w ip, r1, lsl #9 8000d3e: d102 bne.n 8000d46 <__aeabi_fcmpun+0x26> 8000d40: f04f 0000 mov.w r0, #0 8000d44: 4770 bx lr 8000d46: f04f 0001 mov.w r0, #1 8000d4a: 4770 bx lr 08000d4c <__aeabi_f2iz>: 8000d4c: ea4f 0240 mov.w r2, r0, lsl #1 8000d50: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 8000d54: d30f bcc.n 8000d76 <__aeabi_f2iz+0x2a> 8000d56: f04f 039e mov.w r3, #158 @ 0x9e 8000d5a: ebb3 6212 subs.w r2, r3, r2, lsr #24 8000d5e: d90d bls.n 8000d7c <__aeabi_f2iz+0x30> 8000d60: ea4f 2300 mov.w r3, r0, lsl #8 8000d64: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000d68: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8000d6c: fa23 f002 lsr.w r0, r3, r2 8000d70: bf18 it ne 8000d72: 4240 negne r0, r0 8000d74: 4770 bx lr 8000d76: f04f 0000 mov.w r0, #0 8000d7a: 4770 bx lr 8000d7c: f112 0f61 cmn.w r2, #97 @ 0x61 8000d80: d101 bne.n 8000d86 <__aeabi_f2iz+0x3a> 8000d82: 0242 lsls r2, r0, #9 8000d84: d105 bne.n 8000d92 <__aeabi_f2iz+0x46> 8000d86: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 8000d8a: bf08 it eq 8000d8c: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8000d90: 4770 bx lr 8000d92: f04f 0000 mov.w r0, #0 8000d96: 4770 bx lr 08000d98 : * @param numberOfBytes - Number of bytes to be written in the register * * @return None. ******************************************************************************/ void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes) { 8000d98: b580 push {r7, lr} 8000d9a: b086 sub sp, #24 8000d9c: af02 add r7, sp, #8 8000d9e: 4603 mov r3, r0 8000da0: 6039 str r1, [r7, #0] 8000da2: 71fb strb r3, [r7, #7] 8000da4: 4613 mov r3, r2 8000da6: 71bb strb r3, [r7, #6] uint8_t writeData[2] = {0, 0}; 8000da8: 2300 movs r3, #0 8000daa: 81bb strh r3, [r7, #12] HAL_StatusTypeDef status; union Bytes2Long AD5934_reg; AD5934_reg.number = registerValue; 8000dac: 683b ldr r3, [r7, #0] 8000dae: 60bb str r3, [r7, #8] for (uint8_t i = 0; i < numberOfBytes; i++) 8000db0: 2300 movs r3, #0 8000db2: 73fb strb r3, [r7, #15] 8000db4: e018 b.n 8000de8 { writeData[0] = registerAddress - i; 8000db6: 79fa ldrb r2, [r7, #7] 8000db8: 7bfb ldrb r3, [r7, #15] 8000dba: 1ad3 subs r3, r2, r3 8000dbc: b2db uxtb r3, r3 8000dbe: 733b strb r3, [r7, #12] writeData[1] = AD5934_reg.bytes[i]; 8000dc0: 7bfb ldrb r3, [r7, #15] 8000dc2: 3310 adds r3, #16 8000dc4: 443b add r3, r7 8000dc6: f813 3c08 ldrb.w r3, [r3, #-8] 8000dca: 737b strb r3, [r7, #13] status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5); 8000dcc: f107 020c add.w r2, r7, #12 8000dd0: 2305 movs r3, #5 8000dd2: 9300 str r3, [sp, #0] 8000dd4: 2302 movs r3, #2 8000dd6: 211a movs r1, #26 8000dd8: 4807 ldr r0, [pc, #28] @ (8000df8 ) 8000dda: f002 fdc5 bl 8003968 8000dde: 4603 mov r3, r0 8000de0: 73bb strb r3, [r7, #14] for (uint8_t i = 0; i < numberOfBytes; i++) 8000de2: 7bfb ldrb r3, [r7, #15] 8000de4: 3301 adds r3, #1 8000de6: 73fb strb r3, [r7, #15] 8000de8: 7bfa ldrb r2, [r7, #15] 8000dea: 79bb ldrb r3, [r7, #6] 8000dec: 429a cmp r2, r3 8000dee: d3e2 bcc.n 8000db6 } return; 8000df0: bf00 nop } 8000df2: 3710 adds r7, #16 8000df4: 46bd mov sp, r7 8000df6: bd80 pop {r7, pc} 8000df8: 20000228 .word 0x20000228 08000dfc : * @param numberOfBytes - Number of bytes to be read from the register. * * @return Register value. ******************************************************************************/ uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes) { 8000dfc: b580 push {r7, lr} 8000dfe: b088 sub sp, #32 8000e00: af02 add r7, sp, #8 8000e02: 4603 mov r3, r0 8000e04: 460a mov r2, r1 8000e06: 71fb strb r3, [r7, #7] 8000e08: 4613 mov r3, r2 8000e0a: 71bb strb r3, [r7, #6] uint8_t readData[1] = {0}; 8000e0c: 2300 movs r3, #0 8000e0e: 753b strb r3, [r7, #20] uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress}; union Bytes2Long AD5934_reg; HAL_StatusTypeDef status; if(numberOfBytes > 4) 8000e10: 79bb ldrb r3, [r7, #6] 8000e12: 2b04 cmp r3, #4 8000e14: d902 bls.n 8000e1c return 0xFFFFFFFF; //Overflow 8000e16: f04f 33ff mov.w r3, #4294967295 8000e1a: e031 b.n 8000e80 AD5934_reg.number = 0; 8000e1c: 2300 movs r3, #0 8000e1e: 60fb str r3, [r7, #12] for (uint8_t i = 0; i < numberOfBytes; i++) 8000e20: 2300 movs r3, #0 8000e22: 75fb strb r3, [r7, #23] 8000e24: e027 b.n 8000e76 { writeData[0] = AD5934_ADDR_POINTER; 8000e26: 23b0 movs r3, #176 @ 0xb0 8000e28: 743b strb r3, [r7, #16] writeData[1] = registerAddress - i; 8000e2a: 79fa ldrb r2, [r7, #7] 8000e2c: 7dfb ldrb r3, [r7, #23] 8000e2e: 1ad3 subs r3, r2, r3 8000e30: b2db uxtb r3, r3 8000e32: 747b strb r3, [r7, #17] status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5); 8000e34: f107 0210 add.w r2, r7, #16 8000e38: 2305 movs r3, #5 8000e3a: 9300 str r3, [sp, #0] 8000e3c: 2302 movs r3, #2 8000e3e: 211a movs r1, #26 8000e40: 4811 ldr r0, [pc, #68] @ (8000e88 ) 8000e42: f002 fd91 bl 8003968 8000e46: 4603 mov r3, r0 8000e48: 75bb strb r3, [r7, #22] //HAL_Delay(1); readData[0] = 0; 8000e4a: 2300 movs r3, #0 8000e4c: 753b strb r3, [r7, #20] status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5); 8000e4e: f107 0214 add.w r2, r7, #20 8000e52: 2305 movs r3, #5 8000e54: 9300 str r3, [sp, #0] 8000e56: 2301 movs r3, #1 8000e58: 211a movs r1, #26 8000e5a: 480b ldr r0, [pc, #44] @ (8000e88 ) 8000e5c: f002 fe82 bl 8003b64 8000e60: 4603 mov r3, r0 8000e62: 75bb strb r3, [r7, #22] AD5934_reg.bytes[i]=readData[0]; 8000e64: 7dfb ldrb r3, [r7, #23] 8000e66: 7d3a ldrb r2, [r7, #20] 8000e68: 3318 adds r3, #24 8000e6a: 443b add r3, r7 8000e6c: f803 2c0c strb.w r2, [r3, #-12] for (uint8_t i = 0; i < numberOfBytes; i++) 8000e70: 7dfb ldrb r3, [r7, #23] 8000e72: 3301 adds r3, #1 8000e74: 75fb strb r3, [r7, #23] 8000e76: 7dfa ldrb r2, [r7, #23] 8000e78: 79bb ldrb r3, [r7, #6] 8000e7a: 429a cmp r2, r3 8000e7c: d3d3 bcc.n 8000e26 /* AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048; AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048; */ return AD5934_reg.number; 8000e7e: 68fb ldr r3, [r7, #12] } 8000e80: 4618 mov r0, r3 8000e82: 3718 adds r7, #24 8000e84: 46bd mov sp, r7 8000e86: bd80 pop {r7, pc} 8000e88: 20000228 .word 0x20000228 08000e8c : * @param None. * * @return None. ******************************************************************************/ void AD5934_Init(void) { 8000e8c: b580 push {r7, lr} 8000e8e: af00 add r7, sp, #0 /************ Config Sweep******************/ // Place AD5934 in reset AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1); 8000e90: 2201 movs r2, #1 8000e92: f44f 7180 mov.w r1, #256 @ 0x100 8000e96: 2081 movs r0, #129 @ 0x81 8000e98: f7ff ff7e bl 8000d98 // Configure starting frequency AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_1K590HZ, 3); 8000e9c: 2203 movs r2, #3 8000e9e: 490a ldr r1, [pc, #40] @ (8000ec8 ) 8000ea0: 2084 movs r0, #132 @ 0x84 8000ea2: f7ff ff79 bl 8000d98 // Configure frequency increment step AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3); 8000ea6: 2203 movs r2, #3 8000ea8: 2100 movs r1, #0 8000eaa: 2087 movs r0, #135 @ 0x87 8000eac: f7ff ff74 bl 8000d98 // Configure number of steps AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2); 8000eb0: 2202 movs r2, #2 8000eb2: 2100 movs r1, #0 8000eb4: 2089 movs r0, #137 @ 0x89 8000eb6: f7ff ff6f bl 8000d98 // Set 128 Settling Time AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_0S01, 2); 8000eba: 2202 movs r2, #2 8000ebc: 210c movs r1, #12 8000ebe: 208b movs r0, #139 @ 0x8b 8000ec0: f7ff ff6a bl 8000d98 } 8000ec4: bf00 nop 8000ec6: bd80 pop {r7, pc} 8000ec8: 003419e3 .word 0x003419e3 08000ecc : * @param None. * * @return None. ******************************************************************************/ void AD5934_RestartSweep(void) { 8000ecc: b580 push {r7, lr} 8000ece: af00 add r7, sp, #0 // Place AD5934 in standby AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1); 8000ed0: 2201 movs r2, #1 8000ed2: 21b4 movs r1, #180 @ 0xb4 8000ed4: 2080 movs r0, #128 @ 0x80 8000ed6: f7ff ff5f bl 8000d98 // Initialize starting frequency, Start frequency sweep, standby AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1); 8000eda: 2201 movs r2, #1 8000edc: 2114 movs r1, #20 8000ede: 2080 movs r0, #128 @ 0x80 8000ee0: f7ff ff5a bl 8000d98 // Configure Range Output, PGA gain andPlace AD5934 in sweep AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1); 8000ee4: 2201 movs r2, #1 8000ee6: 2124 movs r1, #36 @ 0x24 8000ee8: 2080 movs r0, #128 @ 0x80 8000eea: f7ff ff55 bl 8000d98 // Wait for data to be valid AD5934_Wait_For_Data_Valid(); 8000eee: f000 fc37 bl 8001760 // Power Down AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) | AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1); 8000ef2: 2201 movs r2, #1 8000ef4: 21a4 movs r1, #164 @ 0xa4 8000ef6: 2080 movs r0, #128 @ 0x80 8000ef8: f7ff ff4e bl 8000d98 } 8000efc: bf00 nop 8000efe: bd80 pop {r7, pc} 08000f00 : * @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC * * @return Real(int16) and Imaginary(int16) numbers into a int32. ******************************************************************************/ uint32_t AD5934_Sweep(void) { 8000f00: b580 push {r7, lr} 8000f02: b082 sub sp, #8 8000f04: af00 add r7, sp, #0 int16_t real_value, imag_value; uint32_t value=0; 8000f06: 2300 movs r3, #0 8000f08: 607b str r3, [r7, #4] // Restart Sweeping AD5934_RestartSweep(); 8000f0a: f7ff ffdf bl 8000ecc real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2))); 8000f0e: 2102 movs r1, #2 8000f10: 2095 movs r0, #149 @ 0x95 8000f12: f7ff ff73 bl 8000dfc 8000f16: 4603 mov r3, r0 8000f18: 807b strh r3, [r7, #2] imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2))); 8000f1a: 2102 movs r1, #2 8000f1c: 2097 movs r0, #151 @ 0x97 8000f1e: f7ff ff6d bl 8000dfc 8000f22: 4603 mov r3, r0 8000f24: 803b strh r3, [r7, #0] // Get Real (16-bit) and Imaginary (16-bit) values into an unsigned 32-bit value = ((((uint16_t)(imag_value))<<16) | ((uint16_t)(real_value))); 8000f26: 883b ldrh r3, [r7, #0] 8000f28: 041b lsls r3, r3, #16 8000f2a: 887a ldrh r2, [r7, #2] 8000f2c: 4313 orrs r3, r2 8000f2e: 607b str r3, [r7, #4] return value; 8000f30: 687b ldr r3, [r7, #4] } 8000f32: 4618 mov r0, r3 8000f34: 3708 adds r7, #8 8000f36: 46bd mov sp, r7 8000f38: bd80 pop {r7, pc} ... 08000f3c : * @param channel - AD5934_CH_PT100 or AD5934_CH_PT1000. * * @return impedance. ******************************************************************************/ float AD5934_GetTemperature(void) { 8000f3c: b590 push {r4, r7, lr} 8000f3e: b093 sub sp, #76 @ 0x4c 8000f40: af00 add r7, sp, #0 uint8_t i, channel; uint32_t sample; int32_t ref_sum[2], dut_sum[2]; float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum; if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND 8000f42: 2180 movs r1, #128 @ 0x80 8000f44: 48aa ldr r0, [pc, #680] @ (80011f0 ) 8000f46: f002 fb83 bl 8003650 8000f4a: 4603 mov r3, r0 8000f4c: 2b01 cmp r3, #1 8000f4e: d103 bne.n 8000f58 channel = AD5934_CH_PT100; 8000f50: 2300 movs r3, #0 8000f52: f887 3046 strb.w r3, [r7, #70] @ 0x46 8000f56: e002 b.n 8000f5e else channel = AD5934_CH_PT1000; 8000f58: 2301 movs r3, #1 8000f5a: f887 3046 strb.w r3, [r7, #70] @ 0x46 ADG715_Update(channel + AD5934_CH_DELTA); // Set the Reference Resistor on board in the Analog Mux 8000f5e: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 8000f62: 3310 adds r3, #16 8000f64: b2db uxtb r3, r3 8000f66: 4618 mov r0, r3 8000f68: f000 fc9a bl 80018a0 HAL_Delay(2); //Wait a little 8000f6c: 2002 movs r0, #2 8000f6e: f001 fdf5 bl 8002b5c sample = AD5934_Sweep(); // Get Reference Resistor Values from ADC 8000f72: f7ff ffc5 bl 8000f00 8000f76: 63b8 str r0, [r7, #56] @ 0x38 // Move values in the vectors for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 8000f78: 2307 movs r3, #7 8000f7a: f887 3047 strb.w r3, [r7, #71] @ 0x47 8000f7e: e01e b.n 8000fbe { temperature_ref_samples[i][0] = temperature_ref_samples[i-1][0]; //real 8000f80: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000f84: 1e5a subs r2, r3, #1 8000f86: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000f8a: 499a ldr r1, [pc, #616] @ (80011f4 ) 8000f8c: f931 1022 ldrsh.w r1, [r1, r2, lsl #2] 8000f90: 4a98 ldr r2, [pc, #608] @ (80011f4 ) 8000f92: f822 1023 strh.w r1, [r2, r3, lsl #2] temperature_ref_samples[i][1] = temperature_ref_samples[i-1][1]; //imag 8000f96: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000f9a: 3b01 subs r3, #1 8000f9c: f897 2047 ldrb.w r2, [r7, #71] @ 0x47 8000fa0: 4994 ldr r1, [pc, #592] @ (80011f4 ) 8000fa2: 009b lsls r3, r3, #2 8000fa4: 440b add r3, r1 8000fa6: f9b3 0002 ldrsh.w r0, [r3, #2] 8000faa: 4992 ldr r1, [pc, #584] @ (80011f4 ) 8000fac: 0093 lsls r3, r2, #2 8000fae: 440b add r3, r1 8000fb0: 4602 mov r2, r0 8000fb2: 805a strh r2, [r3, #2] for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 8000fb4: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000fb8: 3b01 subs r3, #1 8000fba: f887 3047 strb.w r3, [r7, #71] @ 0x47 8000fbe: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000fc2: 2b00 cmp r3, #0 8000fc4: d1dc bne.n 8000f80 } // Read real and imaginary data temperature_ref_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real 8000fc6: 6bbb ldr r3, [r7, #56] @ 0x38 8000fc8: b21a sxth r2, r3 8000fca: 4b8a ldr r3, [pc, #552] @ (80011f4 ) 8000fcc: 801a strh r2, [r3, #0] //temperature_ref_samples[0][1] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag temperature_ref_samples[0][1] = (int16_t)((sample & 0xFFFF0000)>>16); //imag 8000fce: 6bbb ldr r3, [r7, #56] @ 0x38 8000fd0: 0c1b lsrs r3, r3, #16 8000fd2: b21a sxth r2, r3 8000fd4: 4b87 ldr r3, [pc, #540] @ (80011f4 ) 8000fd6: 805a strh r2, [r3, #2] // Sum values in the vectors for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++) 8000fd8: 2300 movs r3, #0 8000fda: f887 3047 strb.w r3, [r7, #71] @ 0x47 8000fde: 2300 movs r3, #0 8000fe0: 60fb str r3, [r7, #12] 8000fe2: 2300 movs r3, #0 8000fe4: 613b str r3, [r7, #16] 8000fe6: e016 b.n 8001016 { ref_sum[0] += (int32_t)temperature_ref_samples[i][0]; //real 8000fe8: 68fb ldr r3, [r7, #12] 8000fea: f897 2047 ldrb.w r2, [r7, #71] @ 0x47 8000fee: 4981 ldr r1, [pc, #516] @ (80011f4 ) 8000ff0: f931 2022 ldrsh.w r2, [r1, r2, lsl #2] 8000ff4: 4413 add r3, r2 8000ff6: 60fb str r3, [r7, #12] ref_sum[1] += (int32_t)temperature_ref_samples[i][1]; //imag 8000ff8: 693a ldr r2, [r7, #16] 8000ffa: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8000ffe: 497d ldr r1, [pc, #500] @ (80011f4 ) 8001000: 009b lsls r3, r3, #2 8001002: 440b add r3, r1 8001004: f9b3 3002 ldrsh.w r3, [r3, #2] 8001008: 4413 add r3, r2 800100a: 613b str r3, [r7, #16] for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++) 800100c: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8001010: 3301 adds r3, #1 8001012: f887 3047 strb.w r3, [r7, #71] @ 0x47 8001016: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800101a: 2b07 cmp r3, #7 800101c: d9e4 bls.n 8000fe8 } real_ref = ((float)ref_sum[0])/((float)AD5934_TEMP_AVERAGES); 800101e: 68fb ldr r3, [r7, #12] 8001020: 4618 mov r0, r3 8001022: f7ff fc63 bl 80008ec <__aeabi_i2f> 8001026: 4603 mov r3, r0 8001028: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 800102c: 4618 mov r0, r3 800102e: f7ff fd65 bl 8000afc <__aeabi_fdiv> 8001032: 4603 mov r3, r0 8001034: 637b str r3, [r7, #52] @ 0x34 imag_ref = ((float)ref_sum[1])/((float)AD5934_TEMP_AVERAGES); 8001036: 693b ldr r3, [r7, #16] 8001038: 4618 mov r0, r3 800103a: f7ff fc57 bl 80008ec <__aeabi_i2f> 800103e: 4603 mov r3, r0 8001040: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 8001044: 4618 mov r0, r3 8001046: f7ff fd59 bl 8000afc <__aeabi_fdiv> 800104a: 4603 mov r3, r0 800104c: 633b str r3, [r7, #48] @ 0x30 // Calculate gain factor impedance mag_ref = sqrtf((real_ref * real_ref) + (imag_ref * imag_ref)); 800104e: 6b79 ldr r1, [r7, #52] @ 0x34 8001050: 6b78 ldr r0, [r7, #52] @ 0x34 8001052: f7ff fc9f bl 8000994 <__aeabi_fmul> 8001056: 4603 mov r3, r0 8001058: 461c mov r4, r3 800105a: 6b39 ldr r1, [r7, #48] @ 0x30 800105c: 6b38 ldr r0, [r7, #48] @ 0x30 800105e: f7ff fc99 bl 8000994 <__aeabi_fmul> 8001062: 4603 mov r3, r0 8001064: 4619 mov r1, r3 8001066: 4620 mov r0, r4 8001068: f7ff fb8c bl 8000784 <__addsf3> 800106c: 4603 mov r3, r0 800106e: 4618 mov r0, r3 8001070: f004 fe7a bl 8005d68 8001074: 62f8 str r0, [r7, #44] @ 0x2c ADG715_Update(channel); 8001076: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 800107a: 4618 mov r0, r3 800107c: f000 fc10 bl 80018a0 HAL_Delay(2); 8001080: 2002 movs r0, #2 8001082: f001 fd6b bl 8002b5c sample = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC 8001086: f7ff ff3b bl 8000f00 800108a: 63b8 str r0, [r7, #56] @ 0x38 for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 800108c: 2307 movs r3, #7 800108e: f887 3047 strb.w r3, [r7, #71] @ 0x47 8001092: e01e b.n 80010d2 { temperature_dut_samples[i][0] = temperature_dut_samples[i-1][0]; //real 8001094: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8001098: 1e5a subs r2, r3, #1 800109a: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800109e: 4956 ldr r1, [pc, #344] @ (80011f8 ) 80010a0: f931 1022 ldrsh.w r1, [r1, r2, lsl #2] 80010a4: 4a54 ldr r2, [pc, #336] @ (80011f8 ) 80010a6: f822 1023 strh.w r1, [r2, r3, lsl #2] temperature_dut_samples[i][1] = temperature_dut_samples[i-1][1]; //imag 80010aa: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80010ae: 3b01 subs r3, #1 80010b0: f897 2047 ldrb.w r2, [r7, #71] @ 0x47 80010b4: 4950 ldr r1, [pc, #320] @ (80011f8 ) 80010b6: 009b lsls r3, r3, #2 80010b8: 440b add r3, r1 80010ba: f9b3 0002 ldrsh.w r0, [r3, #2] 80010be: 494e ldr r1, [pc, #312] @ (80011f8 ) 80010c0: 0093 lsls r3, r2, #2 80010c2: 440b add r3, r1 80010c4: 4602 mov r2, r0 80010c6: 805a strh r2, [r3, #2] for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 80010c8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80010cc: 3b01 subs r3, #1 80010ce: f887 3047 strb.w r3, [r7, #71] @ 0x47 80010d2: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80010d6: 2b00 cmp r3, #0 80010d8: d1dc bne.n 8001094 } // Read real and imaginary data temperature_dut_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real 80010da: 6bbb ldr r3, [r7, #56] @ 0x38 80010dc: b21a sxth r2, r3 80010de: 4b46 ldr r3, [pc, #280] @ (80011f8 ) 80010e0: 801a strh r2, [r3, #0] //temperature_dut_samples[0][1] = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag temperature_dut_samples[0][1] = (int16_t)((sample & 0xFFFF0000)>>16); //imag 80010e2: 6bbb ldr r3, [r7, #56] @ 0x38 80010e4: 0c1b lsrs r3, r3, #16 80010e6: b21a sxth r2, r3 80010e8: 4b43 ldr r3, [pc, #268] @ (80011f8 ) 80010ea: 805a strh r2, [r3, #2] for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++) 80010ec: 2300 movs r3, #0 80010ee: f887 3047 strb.w r3, [r7, #71] @ 0x47 80010f2: 2300 movs r3, #0 80010f4: 607b str r3, [r7, #4] 80010f6: 2300 movs r3, #0 80010f8: 60bb str r3, [r7, #8] 80010fa: e016 b.n 800112a { dut_sum[0] += (int32_t)temperature_dut_samples[i][0]; //real 80010fc: 687b ldr r3, [r7, #4] 80010fe: f897 2047 ldrb.w r2, [r7, #71] @ 0x47 8001102: 493d ldr r1, [pc, #244] @ (80011f8 ) 8001104: f931 2022 ldrsh.w r2, [r1, r2, lsl #2] 8001108: 4413 add r3, r2 800110a: 607b str r3, [r7, #4] dut_sum[1] += (int32_t)temperature_dut_samples[i][1]; //imag 800110c: 68ba ldr r2, [r7, #8] 800110e: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8001112: 4939 ldr r1, [pc, #228] @ (80011f8 ) 8001114: 009b lsls r3, r3, #2 8001116: 440b add r3, r1 8001118: f9b3 3002 ldrsh.w r3, [r3, #2] 800111c: 4413 add r3, r2 800111e: 60bb str r3, [r7, #8] for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++) 8001120: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8001124: 3301 adds r3, #1 8001126: f887 3047 strb.w r3, [r7, #71] @ 0x47 800112a: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800112e: 2b07 cmp r3, #7 8001130: d9e4 bls.n 80010fc } real_dut = ((float)dut_sum[0])/((float)AD5934_TEMP_AVERAGES); 8001132: 687b ldr r3, [r7, #4] 8001134: 4618 mov r0, r3 8001136: f7ff fbd9 bl 80008ec <__aeabi_i2f> 800113a: 4603 mov r3, r0 800113c: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 8001140: 4618 mov r0, r3 8001142: f7ff fcdb bl 8000afc <__aeabi_fdiv> 8001146: 4603 mov r3, r0 8001148: 62bb str r3, [r7, #40] @ 0x28 imag_dut = ((float)dut_sum[1])/((float)AD5934_TEMP_AVERAGES); 800114a: 68bb ldr r3, [r7, #8] 800114c: 4618 mov r0, r3 800114e: f7ff fbcd bl 80008ec <__aeabi_i2f> 8001152: 4603 mov r3, r0 8001154: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 8001158: 4618 mov r0, r3 800115a: f7ff fccf bl 8000afc <__aeabi_fdiv> 800115e: 4603 mov r3, r0 8001160: 627b str r3, [r7, #36] @ 0x24 // Calculate magnitude mag_dut = sqrtf((real_dut * real_dut) + (imag_dut * imag_dut)); 8001162: 6ab9 ldr r1, [r7, #40] @ 0x28 8001164: 6ab8 ldr r0, [r7, #40] @ 0x28 8001166: f7ff fc15 bl 8000994 <__aeabi_fmul> 800116a: 4603 mov r3, r0 800116c: 461c mov r4, r3 800116e: 6a79 ldr r1, [r7, #36] @ 0x24 8001170: 6a78 ldr r0, [r7, #36] @ 0x24 8001172: f7ff fc0f bl 8000994 <__aeabi_fmul> 8001176: 4603 mov r3, r0 8001178: 4619 mov r1, r3 800117a: 4620 mov r0, r4 800117c: f7ff fb02 bl 8000784 <__addsf3> 8001180: 4603 mov r3, r0 8001182: 4618 mov r0, r3 8001184: f004 fdf0 bl 8005d68 8001188: 6238 str r0, [r7, #32] for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 800118a: 2307 movs r3, #7 800118c: f887 3047 strb.w r3, [r7, #71] @ 0x47 8001190: e00f b.n 80011b2 temperature_display[i] = temperature_display[i-1]; 8001192: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8001196: 1e5a subs r2, r3, #1 8001198: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800119c: 4917 ldr r1, [pc, #92] @ (80011fc ) 800119e: f851 2022 ldr.w r2, [r1, r2, lsl #2] 80011a2: 4916 ldr r1, [pc, #88] @ (80011fc ) 80011a4: f841 2023 str.w r2, [r1, r3, lsl #2] for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--) 80011a8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80011ac: 3b01 subs r3, #1 80011ae: f887 3047 strb.w r3, [r7, #71] @ 0x47 80011b2: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80011b6: 2b00 cmp r3, #0 80011b8: d1eb bne.n 8001192 ratio_mag = mag_ref / mag_dut; 80011ba: 6a39 ldr r1, [r7, #32] 80011bc: 6af8 ldr r0, [r7, #44] @ 0x2c 80011be: f7ff fc9d bl 8000afc <__aeabi_fdiv> 80011c2: 4603 mov r3, r0 80011c4: 61fb str r3, [r7, #28] if(channel==AD5934_CH_PT100) 80011c6: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 80011ca: 2b00 cmp r3, #0 80011cc: d11a bne.n 8001204 impedance_dut = AD5934_Linear_Correction((calibrationResistance[channel & 0x0F]) * ratio_mag); 80011ce: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 80011d2: f003 030f and.w r3, r3, #15 80011d6: 4a0a ldr r2, [pc, #40] @ (8001200 ) 80011d8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80011dc: 69f9 ldr r1, [r7, #28] 80011de: 4618 mov r0, r3 80011e0: f7ff fbd8 bl 8000994 <__aeabi_fmul> 80011e4: 4603 mov r3, r0 80011e6: 4618 mov r0, r3 80011e8: f000 fb0e bl 8001808 80011ec: 6438 str r0, [r7, #64] @ 0x40 80011ee: e016 b.n 800121e 80011f0: 40010800 .word 0x40010800 80011f4: 200000b4 .word 0x200000b4 80011f8: 20000094 .word 0x20000094 80011fc: 200000d4 .word 0x200000d4 8001200: 08005ee8 .word 0x08005ee8 else impedance_dut = (calibrationResistance[channel & 0x0F]) * ratio_mag; 8001204: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 8001208: f003 030f and.w r3, r3, #15 800120c: 4a48 ldr r2, [pc, #288] @ (8001330 ) 800120e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001212: 4619 mov r1, r3 8001214: 69f8 ldr r0, [r7, #28] 8001216: f7ff fbbd bl 8000994 <__aeabi_fmul> 800121a: 4603 mov r3, r0 800121c: 643b str r3, [r7, #64] @ 0x40 // Calculate impedance ratio with the Reference Resistor ratio = impedance_dut / (calibrationResistance[channel & 0x0F]); 800121e: f897 3046 ldrb.w r3, [r7, #70] @ 0x46 8001222: f003 030f and.w r3, r3, #15 8001226: 4a42 ldr r2, [pc, #264] @ (8001330 ) 8001228: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800122c: 4619 mov r1, r3 800122e: 6c38 ldr r0, [r7, #64] @ 0x40 8001230: f7ff fc64 bl 8000afc <__aeabi_fdiv> 8001234: 4603 mov r3, r0 8001236: 61bb str r3, [r7, #24] // Calculate impedance discriminant with the ratio discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio)); 8001238: 69b9 ldr r1, [r7, #24] 800123a: f04f 507e mov.w r0, #1065353216 @ 0x3f800000 800123e: f7ff fa9f bl 8000780 <__aeabi_fsub> 8001242: 4603 mov r3, r0 8001244: 493b ldr r1, [pc, #236] @ (8001334 ) 8001246: 4618 mov r0, r3 8001248: f7ff fba4 bl 8000994 <__aeabi_fmul> 800124c: 4603 mov r3, r0 800124e: 493a ldr r1, [pc, #232] @ (8001338 ) 8001250: 4618 mov r0, r3 8001252: f7ff fa97 bl 8000784 <__addsf3> 8001256: 4603 mov r3, r0 8001258: 617b str r3, [r7, #20] // Calculate new temperature with the discriminant temperature_display[0] = (-AD5934_RTD_A + sqrtf(discriminant))/(2.0f * AD5934_RTD_B); 800125a: 6978 ldr r0, [r7, #20] 800125c: f004 fd84 bl 8005d68 8001260: 4603 mov r3, r0 8001262: 4936 ldr r1, [pc, #216] @ (800133c ) 8001264: 4618 mov r0, r3 8001266: f7ff fa8b bl 8000780 <__aeabi_fsub> 800126a: 4603 mov r3, r0 800126c: 4934 ldr r1, [pc, #208] @ (8001340 ) 800126e: 4618 mov r0, r3 8001270: f7ff fc44 bl 8000afc <__aeabi_fdiv> 8001274: 4603 mov r3, r0 8001276: 461a mov r2, r3 8001278: 4b32 ldr r3, [pc, #200] @ (8001344 ) 800127a: 601a str r2, [r3, #0] // Sum of all temperatures for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++) 800127c: 2300 movs r3, #0 800127e: f887 3047 strb.w r3, [r7, #71] @ 0x47 8001282: f04f 0300 mov.w r3, #0 8001286: 63fb str r3, [r7, #60] @ 0x3c 8001288: e00f b.n 80012aa temperature_sum += temperature_display[i]; 800128a: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 800128e: 4a2d ldr r2, [pc, #180] @ (8001344 ) 8001290: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001294: 4619 mov r1, r3 8001296: 6bf8 ldr r0, [r7, #60] @ 0x3c 8001298: f7ff fa74 bl 8000784 <__addsf3> 800129c: 4603 mov r3, r0 800129e: 63fb str r3, [r7, #60] @ 0x3c for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++) 80012a0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80012a4: 3301 adds r3, #1 80012a6: f887 3047 strb.w r3, [r7, #71] @ 0x47 80012aa: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80012ae: 2b07 cmp r3, #7 80012b0: d9eb bls.n 800128a // Is the temperature stable? if(temperature_display[0]>0.0f && (abs(temperature_display[0]-temperature_display[AD5934_TEMP_AVERAGES-1])/temperature_display[0])<0.1f) 80012b2: 4b24 ldr r3, [pc, #144] @ (8001344 ) 80012b4: 681b ldr r3, [r3, #0] 80012b6: f04f 0100 mov.w r1, #0 80012ba: 4618 mov r0, r3 80012bc: f7ff fd26 bl 8000d0c <__aeabi_fcmpgt> 80012c0: 4603 mov r3, r0 80012c2: 2b00 cmp r3, #0 80012c4: d02d beq.n 8001322 80012c6: 4b1f ldr r3, [pc, #124] @ (8001344 ) 80012c8: 681b ldr r3, [r3, #0] 80012ca: 4a1e ldr r2, [pc, #120] @ (8001344 ) 80012cc: 69d2 ldr r2, [r2, #28] 80012ce: 4611 mov r1, r2 80012d0: 4618 mov r0, r3 80012d2: f7ff fa55 bl 8000780 <__aeabi_fsub> 80012d6: 4603 mov r3, r0 80012d8: 4618 mov r0, r3 80012da: f7ff fd37 bl 8000d4c <__aeabi_f2iz> 80012de: 4603 mov r3, r0 80012e0: 2b00 cmp r3, #0 80012e2: bfb8 it lt 80012e4: 425b neglt r3, r3 80012e6: 4618 mov r0, r3 80012e8: f7ff fb00 bl 80008ec <__aeabi_i2f> 80012ec: 4602 mov r2, r0 80012ee: 4b15 ldr r3, [pc, #84] @ (8001344 ) 80012f0: 681b ldr r3, [r3, #0] 80012f2: 4619 mov r1, r3 80012f4: 4610 mov r0, r2 80012f6: f7ff fc01 bl 8000afc <__aeabi_fdiv> 80012fa: 4603 mov r3, r0 80012fc: 4912 ldr r1, [pc, #72] @ (8001348 ) 80012fe: 4618 mov r0, r3 8001300: f7ff fce6 bl 8000cd0 <__aeabi_fcmplt> 8001304: 4603 mov r3, r0 8001306: 2b00 cmp r3, #0 8001308: d00b beq.n 8001322 return(AD5934_Round_Float_Precision(temperature_sum/((float)AD5934_TEMP_AVERAGES),1)); // Sum / number of averages 800130a: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 800130e: 6bf8 ldr r0, [r7, #60] @ 0x3c 8001310: f7ff fbf4 bl 8000afc <__aeabi_fdiv> 8001314: 4603 mov r3, r0 8001316: 2101 movs r1, #1 8001318: 4618 mov r0, r3 800131a: f000 fa47 bl 80017ac 800131e: 4603 mov r3, r0 8001320: e001 b.n 8001326 else return 0.0f; //instable values return always 0 8001322: f04f 0300 mov.w r3, #0 } 8001326: 4618 mov r0, r3 8001328: 374c adds r7, #76 @ 0x4c 800132a: 46bd mov sp, r7 800132c: bd90 pop {r4, r7, pc} 800132e: bf00 nop 8001330: 08005ee8 .word 0x08005ee8 8001334: 361b057f .word 0x361b057f 8001338: 37802266 .word 0x37802266 800133c: 3b801132 .word 0x3b801132 8001340: b59b057f .word 0xb59b057f 8001344: 200000d4 .word 0x200000d4 8001348: 3dcccccd .word 0x3dcccccd 0800134c : * @param none. * * @return impedance. ******************************************************************************/ float AD5934_GetImpedance(void) { 800134c: b590 push {r4, r7, lr} 800134e: b095 sub sp, #84 @ 0x54 8001350: af00 add r7, sp, #0 int32_t ref_sum_H[2], ref_sum_L[2], dut_sum[2]; float real_number, imag_number, mag_dut, mag_ref_H, mag_ref_L, gain_factor_H, gain_factor_L, gain_factor_dut, slope, admittance; /* STEP 1: Two points reference curve */ ADG715_Update(AD5934_CH_REF_1K); // Set the Reference for High Resistor on board in the Analog Mux 8001352: 2011 movs r0, #17 8001354: f000 faa4 bl 80018a0 HAL_Delay(2); //Wait a little 8001358: 2002 movs r0, #2 800135a: f001 fbff bl 8002b5c sample_H = AD5934_Sweep(); // Get Reference Resistor 1 from ADC 800135e: f7ff fdcf bl 8000f00 8001362: 6438 str r0, [r7, #64] @ 0x40 ADG715_Update(AD5934_CH_REF_100R); // Set the Reference for Low Resistor on board in the Analog Mux 8001364: 2010 movs r0, #16 8001366: f000 fa9b bl 80018a0 HAL_Delay(2); //Wait a little 800136a: 2002 movs r0, #2 800136c: f001 fbf6 bl 8002b5c sample_L = AD5934_Sweep(); // Get Reference Resistor 2 from ADC 8001370: f7ff fdc6 bl 8000f00 8001374: 63f8 str r0, [r7, #60] @ 0x3c // Move values in the vectors for (i = (AD5934_EC_AVERAGES-1); i > 0; i--) 8001376: 2307 movs r3, #7 8001378: f887 304f strb.w r3, [r7, #79] @ 0x4f 800137c: e038 b.n 80013f0 { ec_ref_samples_H[i][0] = ec_ref_samples_H[i-1][0]; //real 800137e: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001382: 1e5a subs r2, r3, #1 8001384: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001388: 49ad ldr r1, [pc, #692] @ (8001640 ) 800138a: f931 1022 ldrsh.w r1, [r1, r2, lsl #2] 800138e: 4aac ldr r2, [pc, #688] @ (8001640 ) 8001390: f822 1023 strh.w r1, [r2, r3, lsl #2] ec_ref_samples_H[i][1] = ec_ref_samples_H[i-1][1]; //imag 8001394: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001398: 3b01 subs r3, #1 800139a: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 800139e: 49a8 ldr r1, [pc, #672] @ (8001640 ) 80013a0: 009b lsls r3, r3, #2 80013a2: 440b add r3, r1 80013a4: f9b3 0002 ldrsh.w r0, [r3, #2] 80013a8: 49a5 ldr r1, [pc, #660] @ (8001640 ) 80013aa: 0093 lsls r3, r2, #2 80013ac: 440b add r3, r1 80013ae: 4602 mov r2, r0 80013b0: 805a strh r2, [r3, #2] ec_ref_samples_L[i][0] = ec_ref_samples_L[i-1][0]; //real 80013b2: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80013b6: 1e5a subs r2, r3, #1 80013b8: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80013bc: 49a1 ldr r1, [pc, #644] @ (8001644 ) 80013be: f931 1022 ldrsh.w r1, [r1, r2, lsl #2] 80013c2: 4aa0 ldr r2, [pc, #640] @ (8001644 ) 80013c4: f822 1023 strh.w r1, [r2, r3, lsl #2] ec_ref_samples_L[i][1] = ec_ref_samples_L[i-1][1]; //imag 80013c8: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80013cc: 3b01 subs r3, #1 80013ce: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 80013d2: 499c ldr r1, [pc, #624] @ (8001644 ) 80013d4: 009b lsls r3, r3, #2 80013d6: 440b add r3, r1 80013d8: f9b3 0002 ldrsh.w r0, [r3, #2] 80013dc: 4999 ldr r1, [pc, #612] @ (8001644 ) 80013de: 0093 lsls r3, r2, #2 80013e0: 440b add r3, r1 80013e2: 4602 mov r2, r0 80013e4: 805a strh r2, [r3, #2] for (i = (AD5934_EC_AVERAGES-1); i > 0; i--) 80013e6: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80013ea: 3b01 subs r3, #1 80013ec: f887 304f strb.w r3, [r7, #79] @ 0x4f 80013f0: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80013f4: 2b00 cmp r3, #0 80013f6: d1c2 bne.n 800137e } // Read real and imaginary data ec_ref_samples_H[0][0] = (int16_t)(sample_H & 0x0000FFFF); //real 80013f8: 6c3b ldr r3, [r7, #64] @ 0x40 80013fa: b21a sxth r2, r3 80013fc: 4b90 ldr r3, [pc, #576] @ (8001640 ) 80013fe: 801a strh r2, [r3, #0] ec_ref_samples_H[0][1] = (int16_t)((sample_H & 0xFFFF0000)>>16); //imag 8001400: 6c3b ldr r3, [r7, #64] @ 0x40 8001402: 0c1b lsrs r3, r3, #16 8001404: b21a sxth r2, r3 8001406: 4b8e ldr r3, [pc, #568] @ (8001640 ) 8001408: 805a strh r2, [r3, #2] //ec_ref_samples_H[0][1] = (int16_t)((0xFFFF - (sample_H & 0xFFFF0000)>>16)); //imag // Read real and imaginary data ec_ref_samples_L[0][0] = (int16_t)(sample_L & 0x0000FFFF); //real 800140a: 6bfb ldr r3, [r7, #60] @ 0x3c 800140c: b21a sxth r2, r3 800140e: 4b8d ldr r3, [pc, #564] @ (8001644 ) 8001410: 801a strh r2, [r3, #0] ec_ref_samples_L[0][1] = (int16_t)((sample_L & 0xFFFF0000)>>16); //imag 8001412: 6bfb ldr r3, [r7, #60] @ 0x3c 8001414: 0c1b lsrs r3, r3, #16 8001416: b21a sxth r2, r3 8001418: 4b8a ldr r3, [pc, #552] @ (8001644 ) 800141a: 805a strh r2, [r3, #2] //ec_ref_samples_L[0][1] = (int16_t)((0xFFFF - (sample_L & 0xFFFF0000)>>16)); //imag // Sum values in the vectors for (i = 0, ref_sum_H[0]=0, ref_sum_H[1]=0, ref_sum_L[0]=0, ref_sum_L[1]=0; i < AD5934_EC_AVERAGES; i++) 800141c: 2300 movs r3, #0 800141e: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001422: 2300 movs r3, #0 8001424: 617b str r3, [r7, #20] 8001426: 2300 movs r3, #0 8001428: 61bb str r3, [r7, #24] 800142a: 2300 movs r3, #0 800142c: 60fb str r3, [r7, #12] 800142e: 2300 movs r3, #0 8001430: 613b str r3, [r7, #16] 8001432: e028 b.n 8001486 { ref_sum_H[0] += (int32_t)ec_ref_samples_H[i][0]; //real 8001434: 697b ldr r3, [r7, #20] 8001436: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 800143a: 4981 ldr r1, [pc, #516] @ (8001640 ) 800143c: f931 2022 ldrsh.w r2, [r1, r2, lsl #2] 8001440: 4413 add r3, r2 8001442: 617b str r3, [r7, #20] ref_sum_H[1] += (int32_t)ec_ref_samples_H[i][1]; //imag 8001444: 69ba ldr r2, [r7, #24] 8001446: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800144a: 497d ldr r1, [pc, #500] @ (8001640 ) 800144c: 009b lsls r3, r3, #2 800144e: 440b add r3, r1 8001450: f9b3 3002 ldrsh.w r3, [r3, #2] 8001454: 4413 add r3, r2 8001456: 61bb str r3, [r7, #24] ref_sum_L[0] += (int32_t)ec_ref_samples_L[i][0]; //real 8001458: 68fb ldr r3, [r7, #12] 800145a: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 800145e: 4979 ldr r1, [pc, #484] @ (8001644 ) 8001460: f931 2022 ldrsh.w r2, [r1, r2, lsl #2] 8001464: 4413 add r3, r2 8001466: 60fb str r3, [r7, #12] ref_sum_L[1] += (int32_t)ec_ref_samples_L[i][1]; //imag 8001468: 693a ldr r2, [r7, #16] 800146a: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800146e: 4975 ldr r1, [pc, #468] @ (8001644 ) 8001470: 009b lsls r3, r3, #2 8001472: 440b add r3, r1 8001474: f9b3 3002 ldrsh.w r3, [r3, #2] 8001478: 4413 add r3, r2 800147a: 613b str r3, [r7, #16] for (i = 0, ref_sum_H[0]=0, ref_sum_H[1]=0, ref_sum_L[0]=0, ref_sum_L[1]=0; i < AD5934_EC_AVERAGES; i++) 800147c: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001480: 3301 adds r3, #1 8001482: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001486: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800148a: 2b07 cmp r3, #7 800148c: d9d2 bls.n 8001434 } real_number = ((float)ref_sum_H[0])/((float)AD5934_EC_AVERAGES); 800148e: 697b ldr r3, [r7, #20] 8001490: 4618 mov r0, r3 8001492: f7ff fa2b bl 80008ec <__aeabi_i2f> 8001496: 4603 mov r3, r0 8001498: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 800149c: 4618 mov r0, r3 800149e: f7ff fb2d bl 8000afc <__aeabi_fdiv> 80014a2: 4603 mov r3, r0 80014a4: 63bb str r3, [r7, #56] @ 0x38 imag_number = ((float)ref_sum_H[1])/((float)AD5934_EC_AVERAGES); 80014a6: 69bb ldr r3, [r7, #24] 80014a8: 4618 mov r0, r3 80014aa: f7ff fa1f bl 80008ec <__aeabi_i2f> 80014ae: 4603 mov r3, r0 80014b0: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 80014b4: 4618 mov r0, r3 80014b6: f7ff fb21 bl 8000afc <__aeabi_fdiv> 80014ba: 4603 mov r3, r0 80014bc: 637b str r3, [r7, #52] @ 0x34 // Calculate gain factor impedance mag_ref_H = sqrtf((real_number * real_number) + (imag_number * imag_number)); 80014be: 6bb9 ldr r1, [r7, #56] @ 0x38 80014c0: 6bb8 ldr r0, [r7, #56] @ 0x38 80014c2: f7ff fa67 bl 8000994 <__aeabi_fmul> 80014c6: 4603 mov r3, r0 80014c8: 461c mov r4, r3 80014ca: 6b79 ldr r1, [r7, #52] @ 0x34 80014cc: 6b78 ldr r0, [r7, #52] @ 0x34 80014ce: f7ff fa61 bl 8000994 <__aeabi_fmul> 80014d2: 4603 mov r3, r0 80014d4: 4619 mov r1, r3 80014d6: 4620 mov r0, r4 80014d8: f7ff f954 bl 8000784 <__addsf3> 80014dc: 4603 mov r3, r0 80014de: 4618 mov r0, r3 80014e0: f004 fc42 bl 8005d68 80014e4: 6338 str r0, [r7, #48] @ 0x30 if(mag_ref_H > 0.0f) 80014e6: f04f 0100 mov.w r1, #0 80014ea: 6b38 ldr r0, [r7, #48] @ 0x30 80014ec: f7ff fc0e bl 8000d0c <__aeabi_fcmpgt> 80014f0: 4603 mov r3, r0 80014f2: 2b00 cmp r3, #0 80014f4: d00c beq.n 8001510 gain_factor_H = 1.0f / (1000.0f * mag_ref_H); 80014f6: 4954 ldr r1, [pc, #336] @ (8001648 ) 80014f8: 6b38 ldr r0, [r7, #48] @ 0x30 80014fa: f7ff fa4b bl 8000994 <__aeabi_fmul> 80014fe: 4603 mov r3, r0 8001500: 4619 mov r1, r3 8001502: f04f 507e mov.w r0, #1065353216 @ 0x3f800000 8001506: f7ff faf9 bl 8000afc <__aeabi_fdiv> 800150a: 4603 mov r3, r0 800150c: 64bb str r3, [r7, #72] @ 0x48 800150e: e002 b.n 8001516 else gain_factor_H = 0.0f; 8001510: f04f 0300 mov.w r3, #0 8001514: 64bb str r3, [r7, #72] @ 0x48 real_number = ((float)ref_sum_L[0])/((float)AD5934_EC_AVERAGES); 8001516: 68fb ldr r3, [r7, #12] 8001518: 4618 mov r0, r3 800151a: f7ff f9e7 bl 80008ec <__aeabi_i2f> 800151e: 4603 mov r3, r0 8001520: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 8001524: 4618 mov r0, r3 8001526: f7ff fae9 bl 8000afc <__aeabi_fdiv> 800152a: 4603 mov r3, r0 800152c: 63bb str r3, [r7, #56] @ 0x38 imag_number = ((float)ref_sum_L[1])/((float)AD5934_EC_AVERAGES); 800152e: 693b ldr r3, [r7, #16] 8001530: 4618 mov r0, r3 8001532: f7ff f9db bl 80008ec <__aeabi_i2f> 8001536: 4603 mov r3, r0 8001538: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 800153c: 4618 mov r0, r3 800153e: f7ff fadd bl 8000afc <__aeabi_fdiv> 8001542: 4603 mov r3, r0 8001544: 637b str r3, [r7, #52] @ 0x34 // Calculate gain factor impedance mag_ref_L = sqrtf((real_number * real_number) + (imag_number * imag_number)); 8001546: 6bb9 ldr r1, [r7, #56] @ 0x38 8001548: 6bb8 ldr r0, [r7, #56] @ 0x38 800154a: f7ff fa23 bl 8000994 <__aeabi_fmul> 800154e: 4603 mov r3, r0 8001550: 461c mov r4, r3 8001552: 6b79 ldr r1, [r7, #52] @ 0x34 8001554: 6b78 ldr r0, [r7, #52] @ 0x34 8001556: f7ff fa1d bl 8000994 <__aeabi_fmul> 800155a: 4603 mov r3, r0 800155c: 4619 mov r1, r3 800155e: 4620 mov r0, r4 8001560: f7ff f910 bl 8000784 <__addsf3> 8001564: 4603 mov r3, r0 8001566: 4618 mov r0, r3 8001568: f004 fbfe bl 8005d68 800156c: 62f8 str r0, [r7, #44] @ 0x2c if(mag_ref_L > 0.0f) 800156e: f04f 0100 mov.w r1, #0 8001572: 6af8 ldr r0, [r7, #44] @ 0x2c 8001574: f7ff fbca bl 8000d0c <__aeabi_fcmpgt> 8001578: 4603 mov r3, r0 800157a: 2b00 cmp r3, #0 800157c: d00c beq.n 8001598 gain_factor_L = 1.0f / (100.0f * mag_ref_L); 800157e: 4933 ldr r1, [pc, #204] @ (800164c ) 8001580: 6af8 ldr r0, [r7, #44] @ 0x2c 8001582: f7ff fa07 bl 8000994 <__aeabi_fmul> 8001586: 4603 mov r3, r0 8001588: 4619 mov r1, r3 800158a: f04f 507e mov.w r0, #1065353216 @ 0x3f800000 800158e: f7ff fab5 bl 8000afc <__aeabi_fdiv> 8001592: 4603 mov r3, r0 8001594: 647b str r3, [r7, #68] @ 0x44 8001596: e002 b.n 800159e else gain_factor_L = 0.0f; 8001598: f04f 0300 mov.w r3, #0 800159c: 647b str r3, [r7, #68] @ 0x44 /* STEP 2: Set the Amplification related to the maximum set value */ if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // PA6 has internal pull-up and the Switch connects to GND 800159e: 2140 movs r1, #64 @ 0x40 80015a0: 482b ldr r0, [pc, #172] @ (8001650 ) 80015a2: f002 f855 bl 8003650 80015a6: 4603 mov r3, r0 80015a8: 2b01 cmp r3, #1 80015aa: d103 bne.n 80015b4 channel = AD5934_CH_EC_5MS; // Switch OFF = 5 mS/cm 80015ac: 2322 movs r3, #34 @ 0x22 80015ae: f887 304e strb.w r3, [r7, #78] @ 0x4e 80015b2: e002 b.n 80015ba else channel = AD5934_CH_EC_10MS; // Switch ON = 10 mS/cm 80015b4: 2321 movs r3, #33 @ 0x21 80015b6: f887 304e strb.w r3, [r7, #78] @ 0x4e ADG715_Update(channel); 80015ba: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 80015be: 4618 mov r0, r3 80015c0: f000 f96e bl 80018a0 HAL_Delay(2); 80015c4: 2002 movs r0, #2 80015c6: f001 fac9 bl 8002b5c sample_dut = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC 80015ca: f7ff fc99 bl 8000f00 80015ce: 62b8 str r0, [r7, #40] @ 0x28 for (i = (AD5934_EC_AVERAGES-1); i > 0; i--) 80015d0: 2307 movs r3, #7 80015d2: f887 304f strb.w r3, [r7, #79] @ 0x4f 80015d6: e01e b.n 8001616 { ec_dut_samples[i][0] = ec_dut_samples[i-1][0]; //real 80015d8: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80015dc: 1e5a subs r2, r3, #1 80015de: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80015e2: 491c ldr r1, [pc, #112] @ (8001654 ) 80015e4: f931 1022 ldrsh.w r1, [r1, r2, lsl #2] 80015e8: 4a1a ldr r2, [pc, #104] @ (8001654 ) 80015ea: f822 1023 strh.w r1, [r2, r3, lsl #2] ec_dut_samples[i][1] = ec_dut_samples[i-1][1]; //imag 80015ee: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 80015f2: 3b01 subs r3, #1 80015f4: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 80015f8: 4916 ldr r1, [pc, #88] @ (8001654 ) 80015fa: 009b lsls r3, r3, #2 80015fc: 440b add r3, r1 80015fe: f9b3 0002 ldrsh.w r0, [r3, #2] 8001602: 4914 ldr r1, [pc, #80] @ (8001654 ) 8001604: 0093 lsls r3, r2, #2 8001606: 440b add r3, r1 8001608: 4602 mov r2, r0 800160a: 805a strh r2, [r3, #2] for (i = (AD5934_EC_AVERAGES-1); i > 0; i--) 800160c: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001610: 3b01 subs r3, #1 8001612: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001616: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800161a: 2b00 cmp r3, #0 800161c: d1dc bne.n 80015d8 } // Read real and imaginary data ec_dut_samples[0][0] = (int16_t)(sample_dut & 0x0000FFFF); //real 800161e: 6abb ldr r3, [r7, #40] @ 0x28 8001620: b21a sxth r2, r3 8001622: 4b0c ldr r3, [pc, #48] @ (8001654 ) 8001624: 801a strh r2, [r3, #0] ec_dut_samples[0][1] = (int16_t)((sample_dut & 0xFFFF0000)>>16); //imag 8001626: 6abb ldr r3, [r7, #40] @ 0x28 8001628: 0c1b lsrs r3, r3, #16 800162a: b21a sxth r2, r3 800162c: 4b09 ldr r3, [pc, #36] @ (8001654 ) 800162e: 805a strh r2, [r3, #2] //ec_dut_samples[0][1] = (int16_t)((0xFFFF - (sample_dut & 0xFFFF0000)>>16)); //imag for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_EC_AVERAGES; i++) 8001630: 2300 movs r3, #0 8001632: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001636: 2300 movs r3, #0 8001638: 607b str r3, [r7, #4] 800163a: 2300 movs r3, #0 800163c: 60bb str r3, [r7, #8] 800163e: e022 b.n 8001686 8001640: 20000114 .word 0x20000114 8001644: 20000134 .word 0x20000134 8001648: 447a0000 .word 0x447a0000 800164c: 42c80000 .word 0x42c80000 8001650: 40010800 .word 0x40010800 8001654: 200000f4 .word 0x200000f4 { dut_sum[0] += (int32_t)ec_dut_samples[i][0]; //real 8001658: 687b ldr r3, [r7, #4] 800165a: f897 204f ldrb.w r2, [r7, #79] @ 0x4f 800165e: 493e ldr r1, [pc, #248] @ (8001758 ) 8001660: f931 2022 ldrsh.w r2, [r1, r2, lsl #2] 8001664: 4413 add r3, r2 8001666: 607b str r3, [r7, #4] dut_sum[1] += (int32_t)ec_dut_samples[i][1]; //imag 8001668: 68ba ldr r2, [r7, #8] 800166a: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800166e: 493a ldr r1, [pc, #232] @ (8001758 ) 8001670: 009b lsls r3, r3, #2 8001672: 440b add r3, r1 8001674: f9b3 3002 ldrsh.w r3, [r3, #2] 8001678: 4413 add r3, r2 800167a: 60bb str r3, [r7, #8] for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_EC_AVERAGES; i++) 800167c: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001680: 3301 adds r3, #1 8001682: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001686: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800168a: 2b07 cmp r3, #7 800168c: d9e4 bls.n 8001658 } real_number = ((float)dut_sum[0])/((float)AD5934_EC_AVERAGES); 800168e: 687b ldr r3, [r7, #4] 8001690: 4618 mov r0, r3 8001692: f7ff f92b bl 80008ec <__aeabi_i2f> 8001696: 4603 mov r3, r0 8001698: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 800169c: 4618 mov r0, r3 800169e: f7ff fa2d bl 8000afc <__aeabi_fdiv> 80016a2: 4603 mov r3, r0 80016a4: 63bb str r3, [r7, #56] @ 0x38 imag_number = ((float)dut_sum[1])/((float)AD5934_EC_AVERAGES); 80016a6: 68bb ldr r3, [r7, #8] 80016a8: 4618 mov r0, r3 80016aa: f7ff f91f bl 80008ec <__aeabi_i2f> 80016ae: 4603 mov r3, r0 80016b0: f04f 4182 mov.w r1, #1090519040 @ 0x41000000 80016b4: 4618 mov r0, r3 80016b6: f7ff fa21 bl 8000afc <__aeabi_fdiv> 80016ba: 4603 mov r3, r0 80016bc: 637b str r3, [r7, #52] @ 0x34 // Calculate unknown magnitude mag_dut = sqrtf((real_number * real_number) + (imag_number * imag_number)); 80016be: 6bb9 ldr r1, [r7, #56] @ 0x38 80016c0: 6bb8 ldr r0, [r7, #56] @ 0x38 80016c2: f7ff f967 bl 8000994 <__aeabi_fmul> 80016c6: 4603 mov r3, r0 80016c8: 461c mov r4, r3 80016ca: 6b79 ldr r1, [r7, #52] @ 0x34 80016cc: 6b78 ldr r0, [r7, #52] @ 0x34 80016ce: f7ff f961 bl 8000994 <__aeabi_fmul> 80016d2: 4603 mov r3, r0 80016d4: 4619 mov r1, r3 80016d6: 4620 mov r0, r4 80016d8: f7ff f854 bl 8000784 <__addsf3> 80016dc: 4603 mov r3, r0 80016de: 4618 mov r0, r3 80016e0: f004 fb42 bl 8005d68 80016e4: 6278 str r0, [r7, #36] @ 0x24 // Calculate gain factor for the unknown magnitude if(mag_ref_H != mag_ref_L) 80016e6: 6af9 ldr r1, [r7, #44] @ 0x2c 80016e8: 6b38 ldr r0, [r7, #48] @ 0x30 80016ea: f7ff fae7 bl 8000cbc <__aeabi_fcmpeq> 80016ee: 4603 mov r3, r0 80016f0: 2b00 cmp r3, #0 80016f2: d12b bne.n 800174c slope = ((gain_factor_H - gain_factor_L)/(mag_ref_H - mag_ref_L)); 80016f4: 6c79 ldr r1, [r7, #68] @ 0x44 80016f6: 6cb8 ldr r0, [r7, #72] @ 0x48 80016f8: f7ff f842 bl 8000780 <__aeabi_fsub> 80016fc: 4603 mov r3, r0 80016fe: 461c mov r4, r3 8001700: 6af9 ldr r1, [r7, #44] @ 0x2c 8001702: 6b38 ldr r0, [r7, #48] @ 0x30 8001704: f7ff f83c bl 8000780 <__aeabi_fsub> 8001708: 4603 mov r3, r0 800170a: 4619 mov r1, r3 800170c: 4620 mov r0, r4 800170e: f7ff f9f5 bl 8000afc <__aeabi_fdiv> 8001712: 4603 mov r3, r0 8001714: 623b str r3, [r7, #32] //slope = ((gain_factor_H - gain_factor_L)/(log10f(mag_ref_H) - log10f(mag_ref_L))); else return 0.0f; //gain_factor_dut = gain_factor_L + (log10f(mag_dut) - log10f(mag_ref_L)) * slope; gain_factor_dut = gain_factor_L + (mag_dut - mag_ref_L) * slope; 8001716: 6af9 ldr r1, [r7, #44] @ 0x2c 8001718: 6a78 ldr r0, [r7, #36] @ 0x24 800171a: f7ff f831 bl 8000780 <__aeabi_fsub> 800171e: 4603 mov r3, r0 8001720: 6a39 ldr r1, [r7, #32] 8001722: 4618 mov r0, r3 8001724: f7ff f936 bl 8000994 <__aeabi_fmul> 8001728: 4603 mov r3, r0 800172a: 4619 mov r1, r3 800172c: 6c78 ldr r0, [r7, #68] @ 0x44 800172e: f7ff f829 bl 8000784 <__addsf3> 8001732: 4603 mov r3, r0 8001734: 61fb str r3, [r7, #28] // Calculate and return admittance in mS return(10.0f * mag_dut * gain_factor_dut); 8001736: 4909 ldr r1, [pc, #36] @ (800175c ) 8001738: 6a78 ldr r0, [r7, #36] @ 0x24 800173a: f7ff f92b bl 8000994 <__aeabi_fmul> 800173e: 4603 mov r3, r0 8001740: 69f9 ldr r1, [r7, #28] 8001742: 4618 mov r0, r3 8001744: f7ff f926 bl 8000994 <__aeabi_fmul> 8001748: 4603 mov r3, r0 800174a: e001 b.n 8001750 return 0.0f; 800174c: f04f 0300 mov.w r3, #0 } 8001750: 4618 mov r0, r3 8001752: 3754 adds r7, #84 @ 0x54 8001754: 46bd mov sp, r7 8001756: bd90 pop {r4, r7, pc} 8001758: 200000f4 .word 0x200000f4 800175c: 41200000 .word 0x41200000 08001760 : /** * @brief Monitora o status com TIMEOUT para evitar travamento do sistema. */ void AD5934_Wait_For_Data_Valid(void) { 8001760: b580 push {r7, lr} 8001762: b084 sub sp, #16 8001764: af00 add r7, sp, #0 uint32_t timeout_counter = 0; 8001766: 2300 movs r3, #0 8001768: 60fb str r3, [r7, #12] const uint32_t MAX_TIMEOUT = 10000; // Limite de tentativas 800176a: f242 7310 movw r3, #10000 @ 0x2710 800176e: 60bb str r3, [r7, #8] uint8_t status; while (1) { status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1); 8001770: 2101 movs r1, #1 8001772: 208f movs r0, #143 @ 0x8f 8001774: f7ff fb42 bl 8000dfc 8001778: 4603 mov r3, r0 800177a: 71fb strb r3, [r7, #7] if ((status & AD5934_STATUS_DATA_VALID) != 0) 800177c: 79fb ldrb r3, [r7, #7] 800177e: f003 0302 and.w r3, r3, #2 8001782: 2b00 cmp r3, #0 8001784: d10a bne.n 800179c { break; // Sucesso! } timeout_counter++; 8001786: 68fb ldr r3, [r7, #12] 8001788: 3301 adds r3, #1 800178a: 60fb str r3, [r7, #12] if (timeout_counter >= MAX_TIMEOUT) 800178c: 68fa ldr r2, [r7, #12] 800178e: 68bb ldr r3, [r7, #8] 8001790: 429a cmp r2, r3 8001792: d205 bcs.n 80017a0 { // TRATAMENTO DE ERRO: O sistema não travou, mas o chip falhou. break; } HAL_Delay(1); // Pequeno delay para não sobrecarregar o barramento I2C 8001794: 2001 movs r0, #1 8001796: f001 f9e1 bl 8002b5c status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1); 800179a: e7e9 b.n 8001770 break; // Sucesso! 800179c: bf00 nop 800179e: e000 b.n 80017a2 break; 80017a0: bf00 nop } } 80017a2: bf00 nop 80017a4: 3710 adds r7, #16 80017a6: 46bd mov sp, r7 80017a8: bd80 pop {r7, pc} ... 080017ac : * @param valor O valor float original. * @param casas_decimais Quantidade de casas que devem permanecer após a vírgula. * @return float O valor com as casas decimais excedentes removidas. */ float AD5934_Round_Float_Precision(float value, uint8_t number_of_decimals) { 80017ac: b580 push {r7, lr} 80017ae: b084 sub sp, #16 80017b0: af00 add r7, sp, #0 80017b2: 6078 str r0, [r7, #4] 80017b4: 460b mov r3, r1 80017b6: 70fb strb r3, [r7, #3] float multiply = 1.0f; 80017b8: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80017bc: 60fb str r3, [r7, #12] for (uint8_t i = 0; i < number_of_decimals; i++) 80017be: 2300 movs r3, #0 80017c0: 72fb strb r3, [r7, #11] 80017c2: e008 b.n 80017d6 multiply *= 10.0f; 80017c4: 490f ldr r1, [pc, #60] @ (8001804 ) 80017c6: 68f8 ldr r0, [r7, #12] 80017c8: f7ff f8e4 bl 8000994 <__aeabi_fmul> 80017cc: 4603 mov r3, r0 80017ce: 60fb str r3, [r7, #12] for (uint8_t i = 0; i < number_of_decimals; i++) 80017d0: 7afb ldrb r3, [r7, #11] 80017d2: 3301 adds r3, #1 80017d4: 72fb strb r3, [r7, #11] 80017d6: 7afa ldrb r2, [r7, #11] 80017d8: 78fb ldrb r3, [r7, #3] 80017da: 429a cmp r2, r3 80017dc: d3f2 bcc.n 80017c4 return roundf(value * multiply) / multiply; 80017de: 68f9 ldr r1, [r7, #12] 80017e0: 6878 ldr r0, [r7, #4] 80017e2: f7ff f8d7 bl 8000994 <__aeabi_fmul> 80017e6: 4603 mov r3, r0 80017e8: 4618 mov r0, r3 80017ea: f004 fb4d bl 8005e88 80017ee: 4603 mov r3, r0 80017f0: 68f9 ldr r1, [r7, #12] 80017f2: 4618 mov r0, r3 80017f4: f7ff f982 bl 8000afc <__aeabi_fdiv> 80017f8: 4603 mov r3, r0 } 80017fa: 4618 mov r0, r3 80017fc: 3710 adds r7, #16 80017fe: 46bd mov sp, r7 8001800: bd80 pop {r7, pc} 8001802: bf00 nop 8001804: 41200000 .word 0x41200000 08001808 : * * @param input_val The raw float value from sensor/ADC. * @return float The transformed value following the requested trend. */ float AD5934_Linear_Correction(float raw_value) { 8001808: b580 push {r7, lr} 800180a: b084 sub sp, #16 800180c: af00 add r7, sp, #0 800180e: 6078 str r0, [r7, #4] /* Pre-calculated constants from regression analysis */ const float slope = 1.02281f; 8001810: 4b08 ldr r3, [pc, #32] @ (8001834 ) 8001812: 60fb str r3, [r7, #12] const float offset = (-2.1409f); 8001814: 4b08 ldr r3, [pc, #32] @ (8001838 ) 8001816: 60bb str r3, [r7, #8] /* Single FPU instruction (if FPU available) or optimized software float mul/add */ return (raw_value * slope) + offset; 8001818: 68f9 ldr r1, [r7, #12] 800181a: 6878 ldr r0, [r7, #4] 800181c: f7ff f8ba bl 8000994 <__aeabi_fmul> 8001820: 4603 mov r3, r0 8001822: 68b9 ldr r1, [r7, #8] 8001824: 4618 mov r0, r3 8001826: f7fe ffad bl 8000784 <__addsf3> 800182a: 4603 mov r3, r0 } 800182c: 4618 mov r0, r3 800182e: 3710 adds r7, #16 8001830: 46bd mov sp, r7 8001832: bd80 pop {r7, pc} 8001834: 3f82eb70 .word 0x3f82eb70 8001838: c0090481 .word 0xc0090481 0800183c : * * @return None. *******************************************************************************/ void ADG715_SetRegisterValue(char value) { 800183c: b580 push {r7, lr} 800183e: b086 sub sp, #24 8001840: af02 add r7, sp, #8 8001842: 4603 mov r3, r0 8001844: 71fb strb r3, [r7, #7] uint8_t writeData[1] = {value}; 8001846: 79fb ldrb r3, [r7, #7] 8001848: 733b strb r3, [r7, #12] HAL_StatusTypeDef status; status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1); 800184a: f107 020c add.w r2, r7, #12 800184e: 2301 movs r3, #1 8001850: 9300 str r3, [sp, #0] 8001852: 2301 movs r3, #1 8001854: 2190 movs r1, #144 @ 0x90 8001856: 4804 ldr r0, [pc, #16] @ (8001868 ) 8001858: f002 f886 bl 8003968 800185c: 4603 mov r3, r0 800185e: 73fb strb r3, [r7, #15] return; 8001860: bf00 nop } 8001862: 3710 adds r7, #16 8001864: 46bd mov sp, r7 8001866: bd80 pop {r7, pc} 8001868: 20000228 .word 0x20000228 0800186c : void ADG715_SetChannels(uint8_t ch1, uint8_t ch2) { 800186c: b580 push {r7, lr} 800186e: b082 sub sp, #8 8001870: af00 add r7, sp, #0 8001872: 4603 mov r3, r0 8001874: 460a mov r2, r1 8001876: 71fb strb r3, [r7, #7] 8001878: 4613 mov r3, r2 800187a: 71bb strb r3, [r7, #6] ADG715_SetRegisterValue(ch1+ch2); 800187c: 79fa ldrb r2, [r7, #7] 800187e: 79bb ldrb r3, [r7, #6] 8001880: 4413 add r3, r2 8001882: b2db uxtb r3, r3 8001884: 4618 mov r0, r3 8001886: f7ff ffd9 bl 800183c } 800188a: bf00 nop 800188c: 3708 adds r7, #8 800188e: 46bd mov sp, r7 8001890: bd80 pop {r7, pc} 08001892 : void ADG715_ResetChannels(void) { 8001892: b580 push {r7, lr} 8001894: af00 add r7, sp, #0 ADG715_SetRegisterValue(0); 8001896: 2000 movs r0, #0 8001898: f7ff ffd0 bl 800183c } 800189c: bf00 nop 800189e: bd80 pop {r7, pc} 080018a0 : * @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC * * @return none. ******************************************************************************/ void ADG715_Update(uint8_t channel) { 80018a0: b580 push {r7, lr} 80018a2: b082 sub sp, #8 80018a4: af00 add r7, sp, #0 80018a6: 4603 mov r3, r0 80018a8: 71fb strb r3, [r7, #7] HAL_StatusTypeDef status; // Disconnect all Analog Switches ADG715_ResetChannels(); 80018aa: f7ff fff2 bl 8001892 // Set the pair of connections if(channel == AD5934_CH_REF_100R) 80018ae: 79fb ldrb r3, [r7, #7] 80018b0: 2b10 cmp r3, #16 80018b2: d104 bne.n 80018be { ADG715_SetChannels(ADG715_SW1, ADG715_SW4); // Rf = 150R, Ch = Ref_100R 80018b4: 2108 movs r1, #8 80018b6: 2001 movs r0, #1 80018b8: f7ff ffd8 bl 800186c else if(channel == AD5934_CH_EC_5MS) { ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC 5 mS/cm Max } } 80018bc: e02e b.n 800191c else if(channel == AD5934_CH_REF_1K) 80018be: 79fb ldrb r3, [r7, #7] 80018c0: 2b11 cmp r3, #17 80018c2: d104 bne.n 80018ce ADG715_SetChannels(ADG715_SW2, ADG715_SW5); // Rf = 1k5, Ch = Ref_1k 80018c4: 2110 movs r1, #16 80018c6: 2002 movs r0, #2 80018c8: f7ff ffd0 bl 800186c } 80018cc: e026 b.n 800191c else if(channel == AD5934_CH_REF_10K) 80018ce: 79fb ldrb r3, [r7, #7] 80018d0: 2b12 cmp r3, #18 80018d2: d104 bne.n 80018de ADG715_SetChannels(ADG715_SW3, ADG715_SW6); // Rf = 6k2, Ch = Ref_10k 80018d4: 2120 movs r1, #32 80018d6: 2004 movs r0, #4 80018d8: f7ff ffc8 bl 800186c } 80018dc: e01e b.n 800191c else if(channel == AD5934_CH_PT100) 80018de: 79fb ldrb r3, [r7, #7] 80018e0: 2b00 cmp r3, #0 80018e2: d104 bne.n 80018ee ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = PT100 80018e4: 2140 movs r1, #64 @ 0x40 80018e6: 2001 movs r0, #1 80018e8: f7ff ffc0 bl 800186c } 80018ec: e016 b.n 800191c else if(channel == AD5934_CH_PT1000) 80018ee: 79fb ldrb r3, [r7, #7] 80018f0: 2b01 cmp r3, #1 80018f2: d104 bne.n 80018fe ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = PT1000 80018f4: 2140 movs r1, #64 @ 0x40 80018f6: 2002 movs r0, #2 80018f8: f7ff ffb8 bl 800186c } 80018fc: e00e b.n 800191c else if(channel == AD5934_CH_EC_10MS) 80018fe: 79fb ldrb r3, [r7, #7] 8001900: 2b21 cmp r3, #33 @ 0x21 8001902: d104 bne.n 800190e ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC 10 mS/cm Max 8001904: 2180 movs r1, #128 @ 0x80 8001906: 2002 movs r0, #2 8001908: f7ff ffb0 bl 800186c } 800190c: e006 b.n 800191c else if(channel == AD5934_CH_EC_5MS) 800190e: 79fb ldrb r3, [r7, #7] 8001910: 2b22 cmp r3, #34 @ 0x22 8001912: d103 bne.n 800191c ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC 5 mS/cm Max 8001914: 2180 movs r1, #128 @ 0x80 8001916: 2004 movs r0, #4 8001918: f7ff ffa8 bl 800186c } 800191c: bf00 nop 800191e: 3708 adds r7, #8 8001920: 46bd mov sp, r7 8001922: bd80 pop {r7, pc} 08001924 : ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; /* ADC1 init function */ void MX_ADC1_Init(void) { 8001924: b580 push {r7, lr} 8001926: b084 sub sp, #16 8001928: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800192a: 1d3b adds r3, r7, #4 800192c: 2200 movs r2, #0 800192e: 601a str r2, [r3, #0] 8001930: 605a str r2, [r3, #4] 8001932: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8001934: 4b18 ldr r3, [pc, #96] @ (8001998 ) 8001936: 4a19 ldr r2, [pc, #100] @ (800199c ) 8001938: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 800193a: 4b17 ldr r3, [pc, #92] @ (8001998 ) 800193c: 2200 movs r2, #0 800193e: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8001940: 4b15 ldr r3, [pc, #84] @ (8001998 ) 8001942: 2200 movs r2, #0 8001944: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8001946: 4b14 ldr r3, [pc, #80] @ (8001998 ) 8001948: 2200 movs r2, #0 800194a: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 800194c: 4b12 ldr r3, [pc, #72] @ (8001998 ) 800194e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8001952: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001954: 4b10 ldr r3, [pc, #64] @ (8001998 ) 8001956: 2200 movs r2, #0 8001958: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800195a: 4b0f ldr r3, [pc, #60] @ (8001998 ) 800195c: 2201 movs r2, #1 800195e: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8001960: 480d ldr r0, [pc, #52] @ (8001998 ) 8001962: f001 f91f bl 8002ba4 8001966: 4603 mov r3, r0 8001968: 2b00 cmp r3, #0 800196a: d001 beq.n 8001970 { Error_Handler(); 800196c: f000 fe80 bl 8002670 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8001970: 2300 movs r3, #0 8001972: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8001974: 2301 movs r3, #1 8001976: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8001978: 2300 movs r3, #0 800197a: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800197c: 1d3b adds r3, r7, #4 800197e: 4619 mov r1, r3 8001980: 4805 ldr r0, [pc, #20] @ (8001998 ) 8001982: f001 f9e7 bl 8002d54 8001986: 4603 mov r3, r0 8001988: 2b00 cmp r3, #0 800198a: d001 beq.n 8001990 { Error_Handler(); 800198c: f000 fe70 bl 8002670 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001990: bf00 nop 8001992: 3710 adds r7, #16 8001994: 46bd mov sp, r7 8001996: bd80 pop {r7, pc} 8001998: 20000154 .word 0x20000154 800199c: 40012400 .word 0x40012400 080019a0 : /* ADC2 init function */ void MX_ADC2_Init(void) { 80019a0: b580 push {r7, lr} 80019a2: b084 sub sp, #16 80019a4: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80019a6: 1d3b adds r3, r7, #4 80019a8: 2200 movs r2, #0 80019aa: 601a str r2, [r3, #0] 80019ac: 605a str r2, [r3, #4] 80019ae: 609a str r2, [r3, #8] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 80019b0: 4b18 ldr r3, [pc, #96] @ (8001a14 ) 80019b2: 4a19 ldr r2, [pc, #100] @ (8001a18 ) 80019b4: 601a str r2, [r3, #0] hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 80019b6: 4b17 ldr r3, [pc, #92] @ (8001a14 ) 80019b8: 2200 movs r2, #0 80019ba: 609a str r2, [r3, #8] hadc2.Init.ContinuousConvMode = DISABLE; 80019bc: 4b15 ldr r3, [pc, #84] @ (8001a14 ) 80019be: 2200 movs r2, #0 80019c0: 731a strb r2, [r3, #12] hadc2.Init.DiscontinuousConvMode = DISABLE; 80019c2: 4b14 ldr r3, [pc, #80] @ (8001a14 ) 80019c4: 2200 movs r2, #0 80019c6: 751a strb r2, [r3, #20] hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80019c8: 4b12 ldr r3, [pc, #72] @ (8001a14 ) 80019ca: f44f 2260 mov.w r2, #917504 @ 0xe0000 80019ce: 61da str r2, [r3, #28] hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80019d0: 4b10 ldr r3, [pc, #64] @ (8001a14 ) 80019d2: 2200 movs r2, #0 80019d4: 605a str r2, [r3, #4] hadc2.Init.NbrOfConversion = 1; 80019d6: 4b0f ldr r3, [pc, #60] @ (8001a14 ) 80019d8: 2201 movs r2, #1 80019da: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc2) != HAL_OK) 80019dc: 480d ldr r0, [pc, #52] @ (8001a14 ) 80019de: f001 f8e1 bl 8002ba4 80019e2: 4603 mov r3, r0 80019e4: 2b00 cmp r3, #0 80019e6: d001 beq.n 80019ec { Error_Handler(); 80019e8: f000 fe42 bl 8002670 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80019ec: 2301 movs r3, #1 80019ee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80019f0: 2301 movs r3, #1 80019f2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80019f4: 2300 movs r3, #0 80019f6: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 80019f8: 1d3b adds r3, r7, #4 80019fa: 4619 mov r1, r3 80019fc: 4805 ldr r0, [pc, #20] @ (8001a14 ) 80019fe: f001 f9a9 bl 8002d54 8001a02: 4603 mov r3, r0 8001a04: 2b00 cmp r3, #0 8001a06: d001 beq.n 8001a0c { Error_Handler(); 8001a08: f000 fe32 bl 8002670 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 8001a0c: bf00 nop 8001a0e: 3710 adds r7, #16 8001a10: 46bd mov sp, r7 8001a12: bd80 pop {r7, pc} 8001a14: 20000184 .word 0x20000184 8001a18: 40012800 .word 0x40012800 08001a1c : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8001a1c: b580 push {r7, lr} 8001a1e: b08a sub sp, #40 @ 0x28 8001a20: af00 add r7, sp, #0 8001a22: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001a24: f107 0318 add.w r3, r7, #24 8001a28: 2200 movs r2, #0 8001a2a: 601a str r2, [r3, #0] 8001a2c: 605a str r2, [r3, #4] 8001a2e: 609a str r2, [r3, #8] 8001a30: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 8001a32: 687b ldr r3, [r7, #4] 8001a34: 681b ldr r3, [r3, #0] 8001a36: 4a28 ldr r2, [pc, #160] @ (8001ad8 ) 8001a38: 4293 cmp r3, r2 8001a3a: d122 bne.n 8001a82 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8001a3c: 4b27 ldr r3, [pc, #156] @ (8001adc ) 8001a3e: 699b ldr r3, [r3, #24] 8001a40: 4a26 ldr r2, [pc, #152] @ (8001adc ) 8001a42: f443 7300 orr.w r3, r3, #512 @ 0x200 8001a46: 6193 str r3, [r2, #24] 8001a48: 4b24 ldr r3, [pc, #144] @ (8001adc ) 8001a4a: 699b ldr r3, [r3, #24] 8001a4c: f403 7300 and.w r3, r3, #512 @ 0x200 8001a50: 617b str r3, [r7, #20] 8001a52: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001a54: 4b21 ldr r3, [pc, #132] @ (8001adc ) 8001a56: 699b ldr r3, [r3, #24] 8001a58: 4a20 ldr r2, [pc, #128] @ (8001adc ) 8001a5a: f043 0304 orr.w r3, r3, #4 8001a5e: 6193 str r3, [r2, #24] 8001a60: 4b1e ldr r3, [pc, #120] @ (8001adc ) 8001a62: 699b ldr r3, [r3, #24] 8001a64: f003 0304 and.w r3, r3, #4 8001a68: 613b str r3, [r7, #16] 8001a6a: 693b ldr r3, [r7, #16] /**ADC1 GPIO Configuration PA0-WKUP ------> ADC1_IN0 PA1 ------> ADC1_IN1 */ GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin; 8001a6c: 2303 movs r3, #3 8001a6e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001a70: 2303 movs r3, #3 8001a72: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001a74: f107 0318 add.w r3, r7, #24 8001a78: 4619 mov r1, r3 8001a7a: 4819 ldr r0, [pc, #100] @ (8001ae0 ) 8001a7c: f001 fc64 bl 8003348 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8001a80: e026 b.n 8001ad0 else if(adcHandle->Instance==ADC2) 8001a82: 687b ldr r3, [r7, #4] 8001a84: 681b ldr r3, [r3, #0] 8001a86: 4a17 ldr r2, [pc, #92] @ (8001ae4 ) 8001a88: 4293 cmp r3, r2 8001a8a: d121 bne.n 8001ad0 __HAL_RCC_ADC2_CLK_ENABLE(); 8001a8c: 4b13 ldr r3, [pc, #76] @ (8001adc ) 8001a8e: 699b ldr r3, [r3, #24] 8001a90: 4a12 ldr r2, [pc, #72] @ (8001adc ) 8001a92: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001a96: 6193 str r3, [r2, #24] 8001a98: 4b10 ldr r3, [pc, #64] @ (8001adc ) 8001a9a: 699b ldr r3, [r3, #24] 8001a9c: f403 6380 and.w r3, r3, #1024 @ 0x400 8001aa0: 60fb str r3, [r7, #12] 8001aa2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001aa4: 4b0d ldr r3, [pc, #52] @ (8001adc ) 8001aa6: 699b ldr r3, [r3, #24] 8001aa8: 4a0c ldr r2, [pc, #48] @ (8001adc ) 8001aaa: f043 0304 orr.w r3, r3, #4 8001aae: 6193 str r3, [r2, #24] 8001ab0: 4b0a ldr r3, [pc, #40] @ (8001adc ) 8001ab2: 699b ldr r3, [r3, #24] 8001ab4: f003 0304 and.w r3, r3, #4 8001ab8: 60bb str r3, [r7, #8] 8001aba: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = AIN2_Pin; 8001abc: 2302 movs r3, #2 8001abe: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001ac0: 2303 movs r3, #3 8001ac2: 61fb str r3, [r7, #28] HAL_GPIO_Init(AIN2_GPIO_Port, &GPIO_InitStruct); 8001ac4: f107 0318 add.w r3, r7, #24 8001ac8: 4619 mov r1, r3 8001aca: 4805 ldr r0, [pc, #20] @ (8001ae0 ) 8001acc: f001 fc3c bl 8003348 } 8001ad0: bf00 nop 8001ad2: 3728 adds r7, #40 @ 0x28 8001ad4: 46bd mov sp, r7 8001ad6: bd80 pop {r7, pc} 8001ad8: 40012400 .word 0x40012400 8001adc: 40021000 .word 0x40021000 8001ae0: 40010800 .word 0x40010800 8001ae4: 40012800 .word 0x40012800 08001ae8 : #include "main.h" // Assuming HAL is included via main.h float temp_calib, ph_compensated, v_ph4=0, v_ph7=0; // Write the register static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) { 8001ae8: b580 push {r7, lr} 8001aea: b086 sub sp, #24 8001aec: af02 add r7, sp, #8 8001aee: 6078 str r0, [r7, #4] 8001af0: 460b mov r3, r1 8001af2: 70fb strb r3, [r7, #3] 8001af4: 4613 mov r3, r2 8001af6: 803b strh r3, [r7, #0] uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) }; 8001af8: 78fb ldrb r3, [r7, #3] 8001afa: 733b strb r3, [r7, #12] 8001afc: 883b ldrh r3, [r7, #0] 8001afe: 0a1b lsrs r3, r3, #8 8001b00: b29b uxth r3, r3 8001b02: b2db uxtb r3, r3 8001b04: 737b strb r3, [r7, #13] 8001b06: 883b ldrh r3, [r7, #0] 8001b08: b2db uxtb r3, r3 8001b0a: 73bb strb r3, [r7, #14] HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10); 8001b0c: 687b ldr r3, [r7, #4] 8001b0e: 68d8 ldr r0, [r3, #12] 8001b10: 687b ldr r3, [r7, #4] 8001b12: 8819 ldrh r1, [r3, #0] 8001b14: f107 020c add.w r2, r7, #12 8001b18: 230a movs r3, #10 8001b1a: 9300 str r3, [sp, #0] 8001b1c: 2303 movs r3, #3 8001b1e: f001 ff23 bl 8003968 } 8001b22: bf00 nop 8001b24: 3710 adds r7, #16 8001b26: 46bd mov sp, r7 8001b28: bd80 pop {r7, pc} 08001b2a : // Read the register static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) { 8001b2a: b580 push {r7, lr} 8001b2c: b086 sub sp, #24 8001b2e: af02 add r7, sp, #8 8001b30: 6078 str r0, [r7, #4] 8001b32: 460b mov r3, r1 8001b34: 70fb strb r3, [r7, #3] HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, ®, 1, 10); 8001b36: 687b ldr r3, [r7, #4] 8001b38: 68d8 ldr r0, [r3, #12] 8001b3a: 687b ldr r3, [r7, #4] 8001b3c: 8819 ldrh r1, [r3, #0] 8001b3e: 1cfa adds r2, r7, #3 8001b40: 230a movs r3, #10 8001b42: 9300 str r3, [sp, #0] 8001b44: 2301 movs r3, #1 8001b46: f001 ff0f bl 8003968 uint8_t pData[2] = { 0, 0 }; 8001b4a: 2300 movs r3, #0 8001b4c: 81bb strh r3, [r7, #12] HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10); 8001b4e: 687b ldr r3, [r7, #4] 8001b50: 68d8 ldr r0, [r3, #12] 8001b52: 687b ldr r3, [r7, #4] 8001b54: 8819 ldrh r1, [r3, #0] 8001b56: f107 020c add.w r2, r7, #12 8001b5a: 230a movs r3, #10 8001b5c: 9300 str r3, [sp, #0] 8001b5e: 2302 movs r3, #2 8001b60: f002 f800 bl 8003b64 return ((pData[0] << 8) | pData[1]); 8001b64: 7b3b ldrb r3, [r7, #12] 8001b66: b21b sxth r3, r3 8001b68: 021b lsls r3, r3, #8 8001b6a: b21a sxth r2, r3 8001b6c: 7b7b ldrb r3, [r7, #13] 8001b6e: b21b sxth r3, r3 8001b70: 4313 orrs r3, r2 8001b72: b21b sxth r3, r3 8001b74: b29b uxth r3, r3 } 8001b76: 4618 mov r0, r3 8001b78: 3710 adds r7, #16 8001b7a: 46bd mov sp, r7 8001b7c: bd80 pop {r7, pc} 08001b7e : HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // This MUST have GPIO PA5 ready to use - ERROR I2C - Wrong address } // Declare an ADS1015 structure void ADS1015(ADS1015_I2C *i2c, I2C_HandleTypeDef *hi2c, uint8_t i2cAddress) { 8001b7e: b480 push {r7} 8001b80: b085 sub sp, #20 8001b82: af00 add r7, sp, #0 8001b84: 60f8 str r0, [r7, #12] 8001b86: 60b9 str r1, [r7, #8] 8001b88: 4613 mov r3, r2 8001b8a: 71fb strb r3, [r7, #7] i2c->hi2c = hi2c; 8001b8c: 68fb ldr r3, [r7, #12] 8001b8e: 68ba ldr r2, [r7, #8] 8001b90: 60da str r2, [r3, #12] i2c->m_i2cAddress = i2cAddress << 1; // It's Important to shift the address << 1 8001b92: 79fb ldrb r3, [r7, #7] 8001b94: b29b uxth r3, r3 8001b96: 005b lsls r3, r3, #1 8001b98: b29a uxth r2, r3 8001b9a: 68fb ldr r3, [r7, #12] 8001b9c: 801a strh r2, [r3, #0] i2c->m_conversionDelay = ADS1015_CONVERSIONDELAY; 8001b9e: 68fb ldr r3, [r7, #12] 8001ba0: 2204 movs r2, #4 8001ba2: 605a str r2, [r3, #4] i2c->m_bitShift = 4; 8001ba4: 68fb ldr r3, [r7, #12] 8001ba6: 2204 movs r2, #4 8001ba8: 721a strb r2, [r3, #8] i2c->m_gain = GAIN_TWOTHIRDS; /* +/- 6.144V range (limited to VDD +0.3V max!) */ 8001baa: 68fb ldr r3, [r7, #12] 8001bac: 2200 movs r2, #0 8001bae: 815a strh r2, [r3, #10] //ADSbegin(i2c); //Ready is not used } 8001bb0: bf00 nop 8001bb2: 3714 adds r7, #20 8001bb4: 46bd mov sp, r7 8001bb6: bc80 pop {r7} 8001bb8: 4770 bx lr 08001bba : // ADSsetGain(GAIN_TWO); // 2x gain +/- 2.048V 1 bit = 1mV 0.0625mV // ADSsetGain(GAIN_FOUR); // 4x gain +/- 1.024V 1 bit = 0.5mV 0.03125mV // ADSsetGain(GAIN_EIGHT); // 8x gain +/- 0.512V 1 bit = 0.25mV 0.015625mV // ADSsetGain(GAIN_SIXTEEN); // 16x gain +/- 0.256V 1 bit = 0.125mV 0.0078125mV */ void ADSsetGain(ADS1015_I2C *i2c, adsGain_t gain) { 8001bba: b480 push {r7} 8001bbc: b083 sub sp, #12 8001bbe: af00 add r7, sp, #0 8001bc0: 6078 str r0, [r7, #4] 8001bc2: 460b mov r3, r1 8001bc4: 807b strh r3, [r7, #2] i2c->m_gain = gain; 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 887a ldrh r2, [r7, #2] 8001bca: 815a strh r2, [r3, #10] } 8001bcc: bf00 nop 8001bce: 370c adds r7, #12 8001bd0: 46bd mov sp, r7 8001bd2: bc80 pop {r7} 8001bd4: 4770 bx lr 08001bd6 : /* * Reads the conversion results, measuring the voltage * difference between the P (AIN0) and N (AIN1) input. Generates * a signed value since the difference can be either positive or negative. */ int16_t ADSreadADC_Differential_0_1(ADS1015_I2C *i2c) { 8001bd6: b580 push {r7, lr} 8001bd8: b084 sub sp, #16 8001bda: af00 add r7, sp, #0 8001bdc: 6078 str r0, [r7, #4] // Start with default values uint16_t config = 8001bde: f240 1303 movw r3, #259 @ 0x103 8001be2: 81bb strh r3, [r7, #12] ADS1015_REG_CONFIG_CMODE_TRAD | // Traditional comparator (default val) ADS1015_REG_CONFIG_DR_128SPS | // 128 samples per second (default) ADS1015_REG_CONFIG_MODE_SINGLE; // Single-shot mode (default) // Set PGA/voltage range config |= i2c->m_gain; 8001be4: 687b ldr r3, [r7, #4] 8001be6: 895a ldrh r2, [r3, #10] 8001be8: 89bb ldrh r3, [r7, #12] 8001bea: 4313 orrs r3, r2 8001bec: 81bb strh r3, [r7, #12] // Set channels config |= ADS1015_REG_CONFIG_MUX_DIFF_0_1; // AIN0 = P, AIN1 = N // Set 'start single-conversion' bit config |= ADS1015_REG_CONFIG_OS_SINGLE; 8001bee: 89bb ldrh r3, [r7, #12] 8001bf0: ea6f 4343 mvn.w r3, r3, lsl #17 8001bf4: ea6f 4353 mvn.w r3, r3, lsr #17 8001bf8: 81bb strh r3, [r7, #12] // Write config register to the ADC writeRegister(i2c, ADS1015_REG_POINTER_CONFIG, config); 8001bfa: 89bb ldrh r3, [r7, #12] 8001bfc: 461a mov r2, r3 8001bfe: 2101 movs r1, #1 8001c00: 6878 ldr r0, [r7, #4] 8001c02: f7ff ff71 bl 8001ae8 // Wait for the conversion to complete HAL_Delay(i2c->m_conversionDelay); 8001c06: 687b ldr r3, [r7, #4] 8001c08: 685b ldr r3, [r3, #4] 8001c0a: 4618 mov r0, r3 8001c0c: f000 ffa6 bl 8002b5c // Read the conversion results uint16_t res = readRegister(i2c, ADS1015_REG_POINTER_CONVERT) >> i2c->m_bitShift; 8001c10: 2100 movs r1, #0 8001c12: 6878 ldr r0, [r7, #4] 8001c14: f7ff ff89 bl 8001b2a 8001c18: 4603 mov r3, r0 8001c1a: 461a mov r2, r3 8001c1c: 687b ldr r3, [r7, #4] 8001c1e: 7a1b ldrb r3, [r3, #8] 8001c20: fa42 f303 asr.w r3, r2, r3 8001c24: 81fb strh r3, [r7, #14] if (i2c->m_bitShift == 0) { 8001c26: 687b ldr r3, [r7, #4] 8001c28: 7a1b ldrb r3, [r3, #8] 8001c2a: 2b00 cmp r3, #0 8001c2c: d102 bne.n 8001c34 return (int16_t) res; 8001c2e: f9b7 300e ldrsh.w r3, [r7, #14] 8001c32: e00b b.n 8001c4c } else { // Shift 12-bit results right 4 bits for the ADS1015, // making sure we keep the sign bit intact if (res > 0x07FF) { 8001c34: 89fb ldrh r3, [r7, #14] 8001c36: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8001c3a: d305 bcc.n 8001c48 // negative number - extend the sign to 16th bit res |= 0xF000; 8001c3c: 89fb ldrh r3, [r7, #14] 8001c3e: ea6f 5303 mvn.w r3, r3, lsl #20 8001c42: ea6f 5313 mvn.w r3, r3, lsr #20 8001c46: 81fb strh r3, [r7, #14] } return (int16_t) res; 8001c48: f9b7 300e ldrsh.w r3, [r7, #14] } } 8001c4c: 4618 mov r0, r3 8001c4e: 3710 adds r7, #16 8001c50: 46bd mov sp, r7 8001c52: bd80 pop {r7, pc} 08001c54 : return (int16_t) res; } } float ADSCalculate_ph_Volts(int16_t adc_raw) { 8001c54: b580 push {r7, lr} 8001c56: b082 sub sp, #8 8001c58: af00 add r7, sp, #0 8001c5a: 4603 mov r3, r0 8001c5c: 80fb strh r3, [r7, #6] // 1. Converter leitura bruta do ADC para tensão real (Volts) return ((float)adc_raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX; 8001c5e: f9b7 3006 ldrsh.w r3, [r7, #6] 8001c62: 4618 mov r0, r3 8001c64: f7fe fe42 bl 80008ec <__aeabi_i2f> 8001c68: 4603 mov r3, r0 8001c6a: 4907 ldr r1, [pc, #28] @ (8001c88 ) 8001c6c: 4618 mov r0, r3 8001c6e: f7fe fe91 bl 8000994 <__aeabi_fmul> 8001c72: 4603 mov r3, r0 8001c74: 4905 ldr r1, [pc, #20] @ (8001c8c ) 8001c76: 4618 mov r0, r3 8001c78: f7fe ff40 bl 8000afc <__aeabi_fdiv> 8001c7c: 4603 mov r3, r0 } 8001c7e: 4618 mov r0, r3 8001c80: 3708 adds r7, #8 8001c82: 46bd mov sp, r7 8001c84: bd80 pop {r7, pc} 8001c86: bf00 nop 8001c88: 40533333 .word 0x40533333 8001c8c: 457ff000 .word 0x457ff000 08001c90 : * @param temp_dut Temperatura atual medida em Celsius. * * @return float Valor de pH calculado (0.0 a 14.0). */ float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut) { 8001c90: b590 push {r4, r7, lr} 8001c92: b08b sub sp, #44 @ 0x2c 8001c94: af00 add r7, sp, #0 8001c96: 4603 mov r3, r0 8001c98: 6039 str r1, [r7, #0] 8001c9a: 80fb strh r3, [r7, #6] // 1. Converter leitura bruta do ADC para tensão real (Volts) float v_measured = ((float)adc_raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX; 8001c9c: f9b7 3006 ldrsh.w r3, [r7, #6] 8001ca0: 4618 mov r0, r3 8001ca2: f7fe fe23 bl 80008ec <__aeabi_i2f> 8001ca6: 4603 mov r3, r0 8001ca8: 4935 ldr r1, [pc, #212] @ (8001d80 ) 8001caa: 4618 mov r0, r3 8001cac: f7fe fe72 bl 8000994 <__aeabi_fmul> 8001cb0: 4603 mov r3, r0 8001cb2: 4934 ldr r1, [pc, #208] @ (8001d84 ) 8001cb4: 4618 mov r0, r3 8001cb6: f7fe ff21 bl 8000afc <__aeabi_fdiv> 8001cba: 4603 mov r3, r0 8001cbc: 623b str r3, [r7, #32] // 2. Calcular o Slope original (medido na temperatura da calibração) // Delta pH é fixo em 3.0 (de pH 7 para pH 4) float delta_v_calib = v_ph7 - v_ph4; 8001cbe: 4b32 ldr r3, [pc, #200] @ (8001d88 ) 8001cc0: 681b ldr r3, [r3, #0] 8001cc2: 4a32 ldr r2, [pc, #200] @ (8001d8c ) 8001cc4: 6812 ldr r2, [r2, #0] 8001cc6: 4611 mov r1, r2 8001cc8: 4618 mov r0, r3 8001cca: f7fe fd59 bl 8000780 <__aeabi_fsub> 8001cce: 4603 mov r3, r0 8001cd0: 61fb str r3, [r7, #28] if (delta_v_calib == 0.0f) 8001cd2: f04f 0100 mov.w r1, #0 8001cd6: 69f8 ldr r0, [r7, #28] 8001cd8: f7fe fff0 bl 8000cbc <__aeabi_fcmpeq> 8001cdc: 4603 mov r3, r0 8001cde: 2b00 cmp r3, #0 8001ce0: d002 beq.n 8001ce8 { return 0.0f; // Proteção contra erro de calibração/divisão por zero 8001ce2: f04f 0300 mov.w r3, #0 8001ce6: e046 b.n 8001d76 } float slope_at_calib = 3.0f / delta_v_calib; 8001ce8: 69f9 ldr r1, [r7, #28] 8001cea: 4829 ldr r0, [pc, #164] @ (8001d90 ) 8001cec: f7fe ff06 bl 8000afc <__aeabi_fdiv> 8001cf0: 4603 mov r3, r0 8001cf2: 61bb str r3, [r7, #24] // 3. Calcular o Fator de Correção Térmica (Equação de Nernst) float temp_k_now = temp_dut + ADS1015_KELVIN_OFFSET; 8001cf4: 4927 ldr r1, [pc, #156] @ (8001d94 ) 8001cf6: 6838 ldr r0, [r7, #0] 8001cf8: f7fe fd44 bl 8000784 <__addsf3> 8001cfc: 4603 mov r3, r0 8001cfe: 617b str r3, [r7, #20] float temp_k_ref = temp_calib + ADS1015_KELVIN_OFFSET; 8001d00: 4b25 ldr r3, [pc, #148] @ (8001d98 ) 8001d02: 681b ldr r3, [r3, #0] 8001d04: 4923 ldr r1, [pc, #140] @ (8001d94 ) 8001d06: 4618 mov r0, r3 8001d08: f7fe fd3c bl 8000784 <__addsf3> 8001d0c: 4603 mov r3, r0 8001d0e: 613b str r3, [r7, #16] // Fator: (T_atual / T_referencia) float thermal_factor = temp_k_now / temp_k_ref; 8001d10: 6939 ldr r1, [r7, #16] 8001d12: 6978 ldr r0, [r7, #20] 8001d14: f7fe fef2 bl 8000afc <__aeabi_fdiv> 8001d18: 4603 mov r3, r0 8001d1a: 60fb str r3, [r7, #12] /* * 4. Cálculo Final do pH * O Slope ajustado para a temperatura atual é: slope_at_calib / thermal_factor * Fórmula: pH = pH_ref + (V_medido - V_ref_7) * Slope_ajustado */ float ph_result = 7.0f + ((v_measured - v_ph7) * (slope_at_calib / thermal_factor)); 8001d1c: 4b1a ldr r3, [pc, #104] @ (8001d88 ) 8001d1e: 681b ldr r3, [r3, #0] 8001d20: 4619 mov r1, r3 8001d22: 6a38 ldr r0, [r7, #32] 8001d24: f7fe fd2c bl 8000780 <__aeabi_fsub> 8001d28: 4603 mov r3, r0 8001d2a: 461c mov r4, r3 8001d2c: 68f9 ldr r1, [r7, #12] 8001d2e: 69b8 ldr r0, [r7, #24] 8001d30: f7fe fee4 bl 8000afc <__aeabi_fdiv> 8001d34: 4603 mov r3, r0 8001d36: 4619 mov r1, r3 8001d38: 4620 mov r0, r4 8001d3a: f7fe fe2b bl 8000994 <__aeabi_fmul> 8001d3e: 4603 mov r3, r0 8001d40: 4916 ldr r1, [pc, #88] @ (8001d9c ) 8001d42: 4618 mov r0, r3 8001d44: f7fe fd1e bl 8000784 <__addsf3> 8001d48: 4603 mov r3, r0 8001d4a: 627b str r3, [r7, #36] @ 0x24 // 5. Clamping (Garantir limites físicos) if (ph_result < 0.0f) ph_result = 0.0f; 8001d4c: f04f 0100 mov.w r1, #0 8001d50: 6a78 ldr r0, [r7, #36] @ 0x24 8001d52: f7fe ffbd bl 8000cd0 <__aeabi_fcmplt> 8001d56: 4603 mov r3, r0 8001d58: 2b00 cmp r3, #0 8001d5a: d002 beq.n 8001d62 8001d5c: f04f 0300 mov.w r3, #0 8001d60: 627b str r3, [r7, #36] @ 0x24 if (ph_result > 14.0f) ph_result = 14.0f; 8001d62: 490f ldr r1, [pc, #60] @ (8001da0 ) 8001d64: 6a78 ldr r0, [r7, #36] @ 0x24 8001d66: f7fe ffd1 bl 8000d0c <__aeabi_fcmpgt> 8001d6a: 4603 mov r3, r0 8001d6c: 2b00 cmp r3, #0 8001d6e: d001 beq.n 8001d74 8001d70: 4b0b ldr r3, [pc, #44] @ (8001da0 ) 8001d72: 627b str r3, [r7, #36] @ 0x24 return ph_result; 8001d74: 6a7b ldr r3, [r7, #36] @ 0x24 } 8001d76: 4618 mov r0, r3 8001d78: 372c adds r7, #44 @ 0x2c 8001d7a: 46bd mov sp, r7 8001d7c: bd90 pop {r4, r7, pc} 8001d7e: bf00 nop 8001d80: 40533333 .word 0x40533333 8001d84: 457ff000 .word 0x457ff000 8001d88: 200001c0 .word 0x200001c0 8001d8c: 200001bc .word 0x200001bc 8001d90: 40400000 .word 0x40400000 8001d94: 43889333 .word 0x43889333 8001d98: 200001b4 .word 0x200001b4 8001d9c: 40e00000 .word 0x40e00000 8001da0: 41600000 .word 0x41600000 08001da4 : * @brief Initializes the GPIO hardware and sets initial states. * @note This function replaces the handle-based init. * @retval None */ void digital_outputs_init(void) { 8001da4: b580 push {r7, lr} 8001da6: b086 sub sp, #24 8001da8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001daa: 1d3b adds r3, r7, #4 8001dac: 2200 movs r2, #0 8001dae: 601a str r2, [r3, #0] 8001db0: 605a str r2, [r3, #4] 8001db2: 609a str r2, [r3, #8] 8001db4: 60da str r2, [r3, #12] for (int i = 0; i < OUTPUT_PINS_COUNT; i++) { 8001db6: 2300 movs r3, #0 8001db8: 617b str r3, [r7, #20] 8001dba: e029 b.n 8001e10 GPIO_InitStruct.Pin = output_pins[i].pin; 8001dbc: 4a18 ldr r2, [pc, #96] @ (8001e20 ) 8001dbe: 697b ldr r3, [r7, #20] 8001dc0: 00db lsls r3, r3, #3 8001dc2: 4413 add r3, r2 8001dc4: 889b ldrh r3, [r3, #4] 8001dc6: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain 8001dc8: 2311 movs r3, #17 8001dca: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001dcc: 2300 movs r3, #0 8001dce: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001dd0: 2302 movs r3, #2 8001dd2: 613b str r3, [r7, #16] HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct); 8001dd4: 4a12 ldr r2, [pc, #72] @ (8001e20 ) 8001dd6: 697b ldr r3, [r7, #20] 8001dd8: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8001ddc: 1d3a adds r2, r7, #4 8001dde: 4611 mov r1, r2 8001de0: 4618 mov r0, r3 8001de2: f001 fab1 bl 8003348 // Force initial state to LOW (Reset) HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET); 8001de6: 4a0e ldr r2, [pc, #56] @ (8001e20 ) 8001de8: 697b ldr r3, [r7, #20] 8001dea: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8001dee: 4a0c ldr r2, [pc, #48] @ (8001e20 ) 8001df0: 697b ldr r3, [r7, #20] 8001df2: 00db lsls r3, r3, #3 8001df4: 4413 add r3, r2 8001df6: 889b ldrh r3, [r3, #4] 8001df8: 2200 movs r2, #0 8001dfa: 4619 mov r1, r3 8001dfc: f001 fc3f bl 800367e pin_states[i] = 0; 8001e00: 4a08 ldr r2, [pc, #32] @ (8001e24 ) 8001e02: 697b ldr r3, [r7, #20] 8001e04: 4413 add r3, r2 8001e06: 2200 movs r2, #0 8001e08: 701a strb r2, [r3, #0] for (int i = 0; i < OUTPUT_PINS_COUNT; i++) { 8001e0a: 697b ldr r3, [r7, #20] 8001e0c: 3301 adds r3, #1 8001e0e: 617b str r3, [r7, #20] 8001e10: 697b ldr r3, [r7, #20] 8001e12: 2b07 cmp r3, #7 8001e14: ddd2 ble.n 8001dbc } } 8001e16: bf00 nop 8001e18: bf00 nop 8001e1a: 3718 adds r7, #24 8001e1c: 46bd mov sp, r7 8001e1e: bd80 pop {r7, pc} 8001e20: 08005ef4 .word 0x08005ef4 8001e24: 200001c4 .word 0x200001c4 08001e28 : * EXTI * Free pins are configured automatically as Analog (this feature is enabled through * the Code Generation settings) */ void MX_GPIO_Init(void) { 8001e28: b580 push {r7, lr} 8001e2a: b088 sub sp, #32 8001e2c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001e2e: f107 0310 add.w r3, r7, #16 8001e32: 2200 movs r2, #0 8001e34: 601a str r2, [r3, #0] 8001e36: 605a str r2, [r3, #4] 8001e38: 609a str r2, [r3, #8] 8001e3a: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8001e3c: 4b50 ldr r3, [pc, #320] @ (8001f80 ) 8001e3e: 699b ldr r3, [r3, #24] 8001e40: 4a4f ldr r2, [pc, #316] @ (8001f80 ) 8001e42: f043 0310 orr.w r3, r3, #16 8001e46: 6193 str r3, [r2, #24] 8001e48: 4b4d ldr r3, [pc, #308] @ (8001f80 ) 8001e4a: 699b ldr r3, [r3, #24] 8001e4c: f003 0310 and.w r3, r3, #16 8001e50: 60fb str r3, [r7, #12] 8001e52: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001e54: 4b4a ldr r3, [pc, #296] @ (8001f80 ) 8001e56: 699b ldr r3, [r3, #24] 8001e58: 4a49 ldr r2, [pc, #292] @ (8001f80 ) 8001e5a: f043 0320 orr.w r3, r3, #32 8001e5e: 6193 str r3, [r2, #24] 8001e60: 4b47 ldr r3, [pc, #284] @ (8001f80 ) 8001e62: 699b ldr r3, [r3, #24] 8001e64: f003 0320 and.w r3, r3, #32 8001e68: 60bb str r3, [r7, #8] 8001e6a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001e6c: 4b44 ldr r3, [pc, #272] @ (8001f80 ) 8001e6e: 699b ldr r3, [r3, #24] 8001e70: 4a43 ldr r2, [pc, #268] @ (8001f80 ) 8001e72: f043 0304 orr.w r3, r3, #4 8001e76: 6193 str r3, [r2, #24] 8001e78: 4b41 ldr r3, [pc, #260] @ (8001f80 ) 8001e7a: 699b ldr r3, [r3, #24] 8001e7c: f003 0304 and.w r3, r3, #4 8001e80: 607b str r3, [r7, #4] 8001e82: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001e84: 4b3e ldr r3, [pc, #248] @ (8001f80 ) 8001e86: 699b ldr r3, [r3, #24] 8001e88: 4a3d ldr r2, [pc, #244] @ (8001f80 ) 8001e8a: f043 0308 orr.w r3, r3, #8 8001e8e: 6193 str r3, [r2, #24] 8001e90: 4b3b ldr r3, [pc, #236] @ (8001f80 ) 8001e92: 699b ldr r3, [r3, #24] 8001e94: f003 0308 and.w r3, r3, #8 8001e98: 603b str r3, [r7, #0] 8001e9a: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET); 8001e9c: 2200 movs r2, #0 8001e9e: f44f 4160 mov.w r1, #57344 @ 0xe000 8001ea2: 4838 ldr r0, [pc, #224] @ (8001f84 ) 8001ea4: f001 fbeb bl 800367e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin 8001ea8: 2200 movs r2, #0 8001eaa: f240 3137 movw r1, #823 @ 0x337 8001eae: 4836 ldr r0, [pc, #216] @ (8001f88 ) 8001eb0: f001 fbe5 bl 800367e |LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET); 8001eb4: 2200 movs r2, #0 8001eb6: f44f 5180 mov.w r1, #4096 @ 0x1000 8001eba: 4834 ldr r0, [pc, #208] @ (8001f8c ) 8001ebc: f001 fbdf bl 800367e /*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */ GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin; 8001ec0: f44f 4360 mov.w r3, #57344 @ 0xe000 8001ec4: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 8001ec6: 2311 movs r3, #17 8001ec8: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001eca: 2300 movs r3, #0 8001ecc: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001ece: 2302 movs r3, #2 8001ed0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001ed2: f107 0310 add.w r3, r7, #16 8001ed6: 4619 mov r1, r3 8001ed8: 482a ldr r0, [pc, #168] @ (8001f84 ) 8001eda: f001 fa35 bl 8003348 /*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin PG_PH_Pin */ GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin 8001ede: f648 13fc movw r3, #35324 @ 0x89fc 8001ee2: 613b str r3, [r7, #16] |SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin |PG_PH_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001ee4: 2300 movs r3, #0 8001ee6: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001ee8: 2301 movs r3, #1 8001eea: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001eec: f107 0310 add.w r3, r7, #16 8001ef0: 4619 mov r1, r3 8001ef2: 4826 ldr r0, [pc, #152] @ (8001f8c ) 8001ef4: f001 fa28 bl 8003348 /*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */ GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin 8001ef8: f240 3337 movw r3, #823 @ 0x337 8001efc: 613b str r3, [r7, #16] |LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 8001efe: 2311 movs r3, #17 8001f00: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001f02: 2300 movs r3, #0 8001f04: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001f06: 2302 movs r3, #2 8001f08: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001f0a: f107 0310 add.w r3, r7, #16 8001f0e: 4619 mov r1, r3 8001f10: 481d ldr r0, [pc, #116] @ (8001f88 ) 8001f12: f001 fa19 bl 8003348 /*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin */ GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin; 8001f16: f44f 4370 mov.w r3, #61440 @ 0xf000 8001f1a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001f1c: 2300 movs r3, #0 8001f1e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001f20: 2301 movs r3, #1 8001f22: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001f24: f107 0310 add.w r3, r7, #16 8001f28: 4619 mov r1, r3 8001f2a: 4817 ldr r0, [pc, #92] @ (8001f88 ) 8001f2c: f001 fa0c bl 8003348 /*Configure GPIO pin : TX_EN_RS485_Pin */ GPIO_InitStruct.Pin = TX_EN_RS485_Pin; 8001f30: f44f 5380 mov.w r3, #4096 @ 0x1000 8001f34: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001f36: 2301 movs r3, #1 8001f38: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001f3a: 2300 movs r3, #0 8001f3c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001f3e: 2302 movs r3, #2 8001f40: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct); 8001f42: f107 0310 add.w r3, r7, #16 8001f46: 4619 mov r1, r3 8001f48: 4810 ldr r0, [pc, #64] @ (8001f8c ) 8001f4a: f001 f9fd bl 8003348 /*Configure GPIO pin : Calib_PH_Pin */ GPIO_InitStruct.Pin = Calib_PH_Pin; 8001f4e: 2308 movs r3, #8 8001f50: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001f52: 4b0f ldr r3, [pc, #60] @ (8001f90 ) 8001f54: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001f56: 2301 movs r3, #1 8001f58: 61bb str r3, [r7, #24] HAL_GPIO_Init(Calib_PH_GPIO_Port, &GPIO_InitStruct); 8001f5a: f107 0310 add.w r3, r7, #16 8001f5e: 4619 mov r1, r3 8001f60: 4809 ldr r0, [pc, #36] @ (8001f88 ) 8001f62: f001 f9f1 bl 8003348 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0); 8001f66: 2200 movs r2, #0 8001f68: 2100 movs r1, #0 8001f6a: 2009 movs r0, #9 8001f6c: f001 f903 bl 8003176 HAL_NVIC_EnableIRQ(EXTI3_IRQn); 8001f70: 2009 movs r0, #9 8001f72: f001 f91c bl 80031ae } 8001f76: bf00 nop 8001f78: 3720 adds r7, #32 8001f7a: 46bd mov sp, r7 8001f7c: bd80 pop {r7, pc} 8001f7e: bf00 nop 8001f80: 40021000 .word 0x40021000 8001f84: 40011000 .word 0x40011000 8001f88: 40010c00 .word 0x40010c00 8001f8c: 40010800 .word 0x40010800 8001f90: 10310000 .word 0x10310000 08001f94 : * It distinguishes between rising and falling edges by reading the pin state. * @param GPIO_Pin: Specifies the pins connected to the EXTI line. * @retval None */ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8001f94: b580 push {r7, lr} 8001f96: b084 sub sp, #16 8001f98: af00 add r7, sp, #0 8001f9a: 4603 mov r3, r0 8001f9c: 80fb strh r3, [r7, #6] if (GPIO_Pin == Calib_PH_Pin) 8001f9e: 88fb ldrh r3, [r7, #6] 8001fa0: 2b08 cmp r3, #8 8001fa2: d13b bne.n 800201c { uint32_t current_time = HAL_GetTick(); 8001fa4: f000 fdd0 bl 8002b48 8001fa8: 60f8 str r0, [r7, #12] GPIO_PinState pin_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3); 8001faa: 2108 movs r1, #8 8001fac: 481d ldr r0, [pc, #116] @ (8002024 ) 8001fae: f001 fb4f bl 8003650 8001fb2: 4603 mov r3, r0 8001fb4: 72fb strb r3, [r7, #11] if(pin_state != last_original_pin) 8001fb6: 4b1c ldr r3, [pc, #112] @ (8002028 ) 8001fb8: 781b ldrb r3, [r3, #0] 8001fba: b2db uxtb r3, r3 8001fbc: 7afa ldrb r2, [r7, #11] 8001fbe: 429a cmp r2, r3 8001fc0: d02c beq.n 800201c { if(first_time_state == 1) 8001fc2: 4b1a ldr r3, [pc, #104] @ (800202c ) 8001fc4: 781b ldrb r3, [r3, #0] 8001fc6: b2db uxtb r3, r3 8001fc8: 2b01 cmp r3, #1 8001fca: d106 bne.n 8001fda { original_pin_state = pin_state; 8001fcc: 4a18 ldr r2, [pc, #96] @ (8002030 ) 8001fce: 7afb ldrb r3, [r7, #11] 8001fd0: 7013 strb r3, [r2, #0] first_time_state = 0; 8001fd2: 4b16 ldr r3, [pc, #88] @ (800202c ) 8001fd4: 2200 movs r2, #0 8001fd6: 701a strb r2, [r3, #0] last_original_pin = original_pin_state; first_time_state = 1; } } } } 8001fd8: e020 b.n 800201c else if(((current_time - last_interrupt_time) > 70U) && (pin_state == original_pin_state)) 8001fda: 4b16 ldr r3, [pc, #88] @ (8002034 ) 8001fdc: 681b ldr r3, [r3, #0] 8001fde: 68fa ldr r2, [r7, #12] 8001fe0: 1ad3 subs r3, r2, r3 8001fe2: 2b46 cmp r3, #70 @ 0x46 8001fe4: d91a bls.n 800201c 8001fe6: 4b12 ldr r3, [pc, #72] @ (8002030 ) 8001fe8: 781b ldrb r3, [r3, #0] 8001fea: b2db uxtb r3, r3 8001fec: 7afa ldrb r2, [r7, #11] 8001fee: 429a cmp r2, r3 8001ff0: d114 bne.n 800201c if(pin_state == GPIO_PIN_RESET) 8001ff2: 7afb ldrb r3, [r7, #11] 8001ff4: 2b00 cmp r3, #0 8001ff6: d103 bne.n 8002000 edge_state = FALLING_EDGE; 8001ff8: 4b0f ldr r3, [pc, #60] @ (8002038 ) 8001ffa: 22ff movs r2, #255 @ 0xff 8001ffc: 701a strb r2, [r3, #0] 8001ffe: e002 b.n 8002006 edge_state = RISING_EDGE; 8002000: 4b0d ldr r3, [pc, #52] @ (8002038 ) 8002002: 2201 movs r2, #1 8002004: 701a strb r2, [r3, #0] last_interrupt_time = current_time; 8002006: 4a0b ldr r2, [pc, #44] @ (8002034 ) 8002008: 68fb ldr r3, [r7, #12] 800200a: 6013 str r3, [r2, #0] last_original_pin = original_pin_state; 800200c: 4b08 ldr r3, [pc, #32] @ (8002030 ) 800200e: 781b ldrb r3, [r3, #0] 8002010: b2da uxtb r2, r3 8002012: 4b05 ldr r3, [pc, #20] @ (8002028 ) 8002014: 701a strb r2, [r3, #0] first_time_state = 1; 8002016: 4b05 ldr r3, [pc, #20] @ (800202c ) 8002018: 2201 movs r2, #1 800201a: 701a strb r2, [r3, #0] } 800201c: bf00 nop 800201e: 3710 adds r7, #16 8002020: 46bd mov sp, r7 8002022: bd80 pop {r7, pc} 8002024: 40010c00 .word 0x40010c00 8002028: 20000001 .word 0x20000001 800202c: 20000000 .word 0x20000000 8002030: 200001d0 .word 0x200001d0 8002034: 200001cc .word 0x200001cc 8002038: 200001d1 .word 0x200001d1 0800203c : I2C_HandleTypeDef hi2c1; I2C_HandleTypeDef hi2c2; /* I2C1 init function */ void MX_I2C1_Init(void) { 800203c: b580 push {r7, lr} 800203e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8002040: 4b12 ldr r3, [pc, #72] @ (800208c ) 8002042: 4a13 ldr r2, [pc, #76] @ (8002090 ) 8002044: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8002046: 4b11 ldr r3, [pc, #68] @ (800208c ) 8002048: 4a12 ldr r2, [pc, #72] @ (8002094 ) 800204a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800204c: 4b0f ldr r3, [pc, #60] @ (800208c ) 800204e: 2200 movs r2, #0 8002050: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8002052: 4b0e ldr r3, [pc, #56] @ (800208c ) 8002054: 2200 movs r2, #0 8002056: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8002058: 4b0c ldr r3, [pc, #48] @ (800208c ) 800205a: f44f 4280 mov.w r2, #16384 @ 0x4000 800205e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8002060: 4b0a ldr r3, [pc, #40] @ (800208c ) 8002062: 2200 movs r2, #0 8002064: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8002066: 4b09 ldr r3, [pc, #36] @ (800208c ) 8002068: 2200 movs r2, #0 800206a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800206c: 4b07 ldr r3, [pc, #28] @ (800208c ) 800206e: 2200 movs r2, #0 8002070: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8002072: 4b06 ldr r3, [pc, #24] @ (800208c ) 8002074: 2200 movs r2, #0 8002076: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8002078: 4804 ldr r0, [pc, #16] @ (800208c ) 800207a: f001 fb31 bl 80036e0 800207e: 4603 mov r3, r0 8002080: 2b00 cmp r3, #0 8002082: d001 beq.n 8002088 { Error_Handler(); 8002084: f000 faf4 bl 8002670 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8002088: bf00 nop 800208a: bd80 pop {r7, pc} 800208c: 200001d4 .word 0x200001d4 8002090: 40005400 .word 0x40005400 8002094: 000186a0 .word 0x000186a0 08002098 : /* I2C2 init function */ void MX_I2C2_Init(void) { 8002098: b580 push {r7, lr} 800209a: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 800209c: 4b12 ldr r3, [pc, #72] @ (80020e8 ) 800209e: 4a13 ldr r2, [pc, #76] @ (80020ec ) 80020a0: 601a str r2, [r3, #0] hi2c2.Init.ClockSpeed = 100000; 80020a2: 4b11 ldr r3, [pc, #68] @ (80020e8 ) 80020a4: 4a12 ldr r2, [pc, #72] @ (80020f0 ) 80020a6: 605a str r2, [r3, #4] hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; 80020a8: 4b0f ldr r3, [pc, #60] @ (80020e8 ) 80020aa: 2200 movs r2, #0 80020ac: 609a str r2, [r3, #8] hi2c2.Init.OwnAddress1 = 0; 80020ae: 4b0e ldr r3, [pc, #56] @ (80020e8 ) 80020b0: 2200 movs r2, #0 80020b2: 60da str r2, [r3, #12] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80020b4: 4b0c ldr r3, [pc, #48] @ (80020e8 ) 80020b6: f44f 4280 mov.w r2, #16384 @ 0x4000 80020ba: 611a str r2, [r3, #16] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80020bc: 4b0a ldr r3, [pc, #40] @ (80020e8 ) 80020be: 2200 movs r2, #0 80020c0: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2 = 0; 80020c2: 4b09 ldr r3, [pc, #36] @ (80020e8 ) 80020c4: 2200 movs r2, #0 80020c6: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80020c8: 4b07 ldr r3, [pc, #28] @ (80020e8 ) 80020ca: 2200 movs r2, #0 80020cc: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80020ce: 4b06 ldr r3, [pc, #24] @ (80020e8 ) 80020d0: 2200 movs r2, #0 80020d2: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 80020d4: 4804 ldr r0, [pc, #16] @ (80020e8 ) 80020d6: f001 fb03 bl 80036e0 80020da: 4603 mov r3, r0 80020dc: 2b00 cmp r3, #0 80020de: d001 beq.n 80020e4 { Error_Handler(); 80020e0: f000 fac6 bl 8002670 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80020e4: bf00 nop 80020e6: bd80 pop {r7, pc} 80020e8: 20000228 .word 0x20000228 80020ec: 40005800 .word 0x40005800 80020f0: 000186a0 .word 0x000186a0 080020f4 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 80020f4: b580 push {r7, lr} 80020f6: b08a sub sp, #40 @ 0x28 80020f8: af00 add r7, sp, #0 80020fa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80020fc: f107 0318 add.w r3, r7, #24 8002100: 2200 movs r2, #0 8002102: 601a str r2, [r3, #0] 8002104: 605a str r2, [r3, #4] 8002106: 609a str r2, [r3, #8] 8002108: 60da str r2, [r3, #12] if(i2cHandle->Instance==I2C1) 800210a: 687b ldr r3, [r7, #4] 800210c: 681b ldr r3, [r3, #0] 800210e: 4a2b ldr r2, [pc, #172] @ (80021bc ) 8002110: 4293 cmp r3, r2 8002112: d124 bne.n 800215e { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8002114: 4b2a ldr r3, [pc, #168] @ (80021c0 ) 8002116: 699b ldr r3, [r3, #24] 8002118: 4a29 ldr r2, [pc, #164] @ (80021c0 ) 800211a: f043 0308 orr.w r3, r3, #8 800211e: 6193 str r3, [r2, #24] 8002120: 4b27 ldr r3, [pc, #156] @ (80021c0 ) 8002122: 699b ldr r3, [r3, #24] 8002124: f003 0308 and.w r3, r3, #8 8002128: 617b str r3, [r7, #20] 800212a: 697b ldr r3, [r7, #20] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin; 800212c: 23c0 movs r3, #192 @ 0xc0 800212e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8002130: 2312 movs r3, #18 8002132: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002134: 2302 movs r3, #2 8002136: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002138: f107 0318 add.w r3, r7, #24 800213c: 4619 mov r1, r3 800213e: 4821 ldr r0, [pc, #132] @ (80021c4 ) 8002140: f001 f902 bl 8003348 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8002144: 4b1e ldr r3, [pc, #120] @ (80021c0 ) 8002146: 69db ldr r3, [r3, #28] 8002148: 4a1d ldr r2, [pc, #116] @ (80021c0 ) 800214a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800214e: 61d3 str r3, [r2, #28] 8002150: 4b1b ldr r3, [pc, #108] @ (80021c0 ) 8002152: 69db ldr r3, [r3, #28] 8002154: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002158: 613b str r3, [r7, #16] 800215a: 693b ldr r3, [r7, #16] __HAL_RCC_I2C2_CLK_ENABLE(); /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 800215c: e029 b.n 80021b2 else if(i2cHandle->Instance==I2C2) 800215e: 687b ldr r3, [r7, #4] 8002160: 681b ldr r3, [r3, #0] 8002162: 4a19 ldr r2, [pc, #100] @ (80021c8 ) 8002164: 4293 cmp r3, r2 8002166: d124 bne.n 80021b2 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002168: 4b15 ldr r3, [pc, #84] @ (80021c0 ) 800216a: 699b ldr r3, [r3, #24] 800216c: 4a14 ldr r2, [pc, #80] @ (80021c0 ) 800216e: f043 0308 orr.w r3, r3, #8 8002172: 6193 str r3, [r2, #24] 8002174: 4b12 ldr r3, [pc, #72] @ (80021c0 ) 8002176: 699b ldr r3, [r3, #24] 8002178: f003 0308 and.w r3, r3, #8 800217c: 60fb str r3, [r7, #12] 800217e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin; 8002180: f44f 6340 mov.w r3, #3072 @ 0xc00 8002184: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8002186: 2312 movs r3, #18 8002188: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800218a: 2302 movs r3, #2 800218c: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800218e: f107 0318 add.w r3, r7, #24 8002192: 4619 mov r1, r3 8002194: 480b ldr r0, [pc, #44] @ (80021c4 ) 8002196: f001 f8d7 bl 8003348 __HAL_RCC_I2C2_CLK_ENABLE(); 800219a: 4b09 ldr r3, [pc, #36] @ (80021c0 ) 800219c: 69db ldr r3, [r3, #28] 800219e: 4a08 ldr r2, [pc, #32] @ (80021c0 ) 80021a0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 80021a4: 61d3 str r3, [r2, #28] 80021a6: 4b06 ldr r3, [pc, #24] @ (80021c0 ) 80021a8: 69db ldr r3, [r3, #28] 80021aa: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80021ae: 60bb str r3, [r7, #8] 80021b0: 68bb ldr r3, [r7, #8] } 80021b2: bf00 nop 80021b4: 3728 adds r7, #40 @ 0x28 80021b6: 46bd mov sp, r7 80021b8: bd80 pop {r7, pc} 80021ba: bf00 nop 80021bc: 40005400 .word 0x40005400 80021c0: 40021000 .word 0x40021000 80021c4: 40010c00 .word 0x40010c00 80021c8: 40005800 .word 0x40005800 080021cc
: /** * @brief The application entry point. * @retval int */ int main(void) { 80021cc: b580 push {r7, lr} 80021ce: b08e sub sp, #56 @ 0x38 80021d0: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ HAL_StatusTypeDef status0,status1; // Variables to store previous LED states uint8_t previous_green_state = 0; 80021d2: 2300 movs r3, #0 80021d4: f887 3033 strb.w r3, [r7, #51] @ 0x33 uint8_t previous_red_state = 0; 80021d8: 2300 movs r3, #0 80021da: f887 3032 strb.w r3, [r7, #50] @ 0x32 // Variables for timing uint32_t previous_millis_green = 0; 80021de: 2300 movs r3, #0 80021e0: 637b str r3, [r7, #52] @ 0x34 uint32_t previous_millis_red = 0; 80021e2: 2300 movs r3, #0 80021e4: 62fb str r3, [r7, #44] @ 0x2c uint32_t current_millis; float temperature_RTD, admittance_EC; /*! Temporary variables */ char tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 80021e6: 1d3b adds r3, r7, #4 80021e8: 2200 movs r2, #0 80021ea: 601a str r2, [r3, #0] 80021ec: 605a str r2, [r3, #4] 80021ee: 811a strh r2, [r3, #8] long double tempValue = 0; 80021f0: f04f 0200 mov.w r2, #0 80021f4: f04f 0300 mov.w r3, #0 80021f8: e9c7 2308 strd r2, r3, [r7, #32] /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80021fc: f000 fc4c bl 8002a98 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8002200: f000 f910 bl 8002424 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8002204: f7ff fe10 bl 8001e28 MX_ADC1_Init(); 8002208: f7ff fb8c bl 8001924 MX_ADC2_Init(); 800220c: f7ff fbc8 bl 80019a0 MX_I2C1_Init(); 8002210: f7ff ff14 bl 800203c MX_I2C2_Init(); 8002214: f7ff ff40 bl 8002098 MX_USART1_UART_Init(); 8002218: f000 fb9a bl 8002950 /* USER CODE BEGIN 2 */ digital_outputs_init(); 800221c: f7ff fdc2 bl 8001da4 // Initialize RS-485 driver rs485_init(); 8002220: f000 fa38 bl 8002694 ADS1015(&i2c, &hi2c1, ADS_ADDR_GND); 8002224: 2248 movs r2, #72 @ 0x48 8002226: 4974 ldr r1, [pc, #464] @ (80023f8 ) 8002228: 4874 ldr r0, [pc, #464] @ (80023fc ) 800222a: f7ff fca8 bl 8001b7e ADSsetGain(&i2c, GAIN_SIXTEEN); 800222e: f44f 6120 mov.w r1, #2560 @ 0xa00 8002232: 4872 ldr r0, [pc, #456] @ (80023fc ) 8002234: f7ff fcc1 bl 8001bba // Start CE and RTD Measurement AD5934_Init(); 8002238: f7fe fe28 bl 8000e8c while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ current_millis = HAL_GetTick(); 800223c: f000 fc84 bl 8002b48 8002240: 61f8 str r0, [r7, #28] // Piscar LED verde em PB5 a cada 0,5 segundos if ((current_millis - previous_millis_green) >= 800) 8002242: 69fa ldr r2, [r7, #28] 8002244: 6b7b ldr r3, [r7, #52] @ 0x34 8002246: 1ad3 subs r3, r2, r3 8002248: f5b3 7f48 cmp.w r3, #800 @ 0x320 800224c: d3f6 bcc.n 800223c { previous_millis_green = current_millis; 800224e: 69fb ldr r3, [r7, #28] 8002250: 637b str r3, [r7, #52] @ 0x34 uint8_t led_data[2] = {0x01, current_green_state}; // Command 0x01 for green LED }*/ temperature_RTD = AD5934_GetTemperature(); 8002252: f7fe fe73 bl 8000f3c 8002256: 61b8 str r0, [r7, #24] FloatToString(tempString, temperature_RTD); 8002258: 69b8 ldr r0, [r7, #24] 800225a: f7fe fa0d bl 8000678 <__aeabi_f2d> 800225e: 4602 mov r2, r0 8002260: 460b mov r3, r1 8002262: 1d39 adds r1, r7, #4 8002264: 4608 mov r0, r1 8002266: f000 f939 bl 80024dc status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1)); 800226a: 1d3b adds r3, r7, #4 800226c: 4618 mov r0, r3 800226e: f7fd ff6d bl 800014c 8002272: 4603 mov r3, r0 8002274: b29b uxth r3, r3 8002276: 3b01 subs r3, #1 8002278: b29a uxth r2, r3 800227a: 1d3b adds r3, r7, #4 800227c: 4611 mov r1, r2 800227e: 4618 mov r0, r3 8002280: f000 fa34 bl 80026ec 8002284: 4603 mov r3, r0 8002286: 75fb strb r3, [r7, #23] status1 = rs485_send_broadcast(newline_real, strlen((char*)newline_real)); 8002288: 485d ldr r0, [pc, #372] @ (8002400 ) 800228a: f7fd ff5f bl 800014c 800228e: 4603 mov r3, r0 8002290: b29b uxth r3, r3 8002292: 4619 mov r1, r3 8002294: 485a ldr r0, [pc, #360] @ (8002400 ) 8002296: f000 fa29 bl 80026ec 800229a: 4603 mov r3, r0 800229c: 75bb strb r3, [r7, #22] if(edge_state == FALLING_EDGE) 800229e: 4b59 ldr r3, [pc, #356] @ (8002404 ) 80022a0: 781b ldrb r3, [r3, #0] 80022a2: b25b sxtb r3, r3 80022a4: f1b3 3fff cmp.w r3, #4294967295 80022a8: d123 bne.n 80022f2 { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); 80022aa: 2201 movs r2, #1 80022ac: 2110 movs r1, #16 80022ae: 4856 ldr r0, [pc, #344] @ (8002408 ) 80022b0: f001 f9e5 bl 800367e HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); 80022b4: 2200 movs r2, #0 80022b6: 2120 movs r1, #32 80022b8: 4853 ldr r0, [pc, #332] @ (8002408 ) 80022ba: f001 f9e0 bl 800367e temp_calib = temperature_RTD; 80022be: 4a53 ldr r2, [pc, #332] @ (800240c ) 80022c0: 69bb ldr r3, [r7, #24] 80022c2: 6013 str r3, [r2, #0] v_ph4 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c)); 80022c4: 484d ldr r0, [pc, #308] @ (80023fc ) 80022c6: f7ff fc86 bl 8001bd6 80022ca: 4603 mov r3, r0 80022cc: b29b uxth r3, r3 80022ce: f5c3 6300 rsb r3, r3, #2048 @ 0x800 80022d2: b29b uxth r3, r3 80022d4: b21b sxth r3, r3 80022d6: 4618 mov r0, r3 80022d8: f7ff fcbc bl 8001c54 80022dc: 4603 mov r3, r0 80022de: 4a4c ldr r2, [pc, #304] @ (8002410 ) 80022e0: 6013 str r3, [r2, #0] edge_state = NO_EDGE; 80022e2: 4b48 ldr r3, [pc, #288] @ (8002404 ) 80022e4: 2200 movs r2, #0 80022e6: 701a strb r2, [r3, #0] HAL_Delay(500); 80022e8: f44f 70fa mov.w r0, #500 @ 0x1f4 80022ec: f000 fc36 bl 8002b5c 80022f0: e024 b.n 800233c }else if(edge_state == RISING_EDGE) 80022f2: 4b44 ldr r3, [pc, #272] @ (8002404 ) 80022f4: 781b ldrb r3, [r3, #0] 80022f6: b25b sxtb r3, r3 80022f8: 2b01 cmp r3, #1 80022fa: d11f bne.n 800233c { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); 80022fc: 2200 movs r2, #0 80022fe: 2110 movs r1, #16 8002300: 4841 ldr r0, [pc, #260] @ (8002408 ) 8002302: f001 f9bc bl 800367e HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); 8002306: 2201 movs r2, #1 8002308: 2120 movs r1, #32 800230a: 483f ldr r0, [pc, #252] @ (8002408 ) 800230c: f001 f9b7 bl 800367e v_ph7 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c)); 8002310: 483a ldr r0, [pc, #232] @ (80023fc ) 8002312: f7ff fc60 bl 8001bd6 8002316: 4603 mov r3, r0 8002318: b29b uxth r3, r3 800231a: f5c3 6300 rsb r3, r3, #2048 @ 0x800 800231e: b29b uxth r3, r3 8002320: b21b sxth r3, r3 8002322: 4618 mov r0, r3 8002324: f7ff fc96 bl 8001c54 8002328: 4603 mov r3, r0 800232a: 4a3a ldr r2, [pc, #232] @ (8002414 ) 800232c: 6013 str r3, [r2, #0] edge_state = NO_EDGE; 800232e: 4b35 ldr r3, [pc, #212] @ (8002404 ) 8002330: 2200 movs r2, #0 8002332: 701a strb r2, [r3, #0] HAL_Delay(500); 8002334: f44f 70fa mov.w r0, #500 @ 0x1f4 8002338: f000 fc10 bl 8002b5c } ph_compensated = ADSCalculate_ph_Compensated((2048 - ADSreadADC_Differential_0_1(&i2c)),temp_calib); 800233c: 482f ldr r0, [pc, #188] @ (80023fc ) 800233e: f7ff fc4a bl 8001bd6 8002342: 4603 mov r3, r0 8002344: b29b uxth r3, r3 8002346: f5c3 6300 rsb r3, r3, #2048 @ 0x800 800234a: b29b uxth r3, r3 800234c: b21b sxth r3, r3 800234e: 4a2f ldr r2, [pc, #188] @ (800240c ) 8002350: 6812 ldr r2, [r2, #0] 8002352: 4611 mov r1, r2 8002354: 4618 mov r0, r3 8002356: f7ff fc9b bl 8001c90 800235a: 4603 mov r3, r0 800235c: 4a2e ldr r2, [pc, #184] @ (8002418 ) 800235e: 6013 str r3, [r2, #0] FloatToString(tempString, ph_compensated); 8002360: 4b2d ldr r3, [pc, #180] @ (8002418 ) 8002362: 681b ldr r3, [r3, #0] 8002364: 4618 mov r0, r3 8002366: f7fe f987 bl 8000678 <__aeabi_f2d> 800236a: 4602 mov r2, r0 800236c: 460b mov r3, r1 800236e: 1d39 adds r1, r7, #4 8002370: 4608 mov r0, r1 8002372: f000 f8b3 bl 80024dc status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1)); 8002376: 1d3b adds r3, r7, #4 8002378: 4618 mov r0, r3 800237a: f7fd fee7 bl 800014c 800237e: 4603 mov r3, r0 8002380: b29b uxth r3, r3 8002382: 3b01 subs r3, #1 8002384: b29a uxth r2, r3 8002386: 1d3b adds r3, r7, #4 8002388: 4611 mov r1, r2 800238a: 4618 mov r0, r3 800238c: f000 f9ae bl 80026ec 8002390: 4603 mov r3, r0 8002392: 75fb strb r3, [r7, #23] status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph)); 8002394: 4821 ldr r0, [pc, #132] @ (800241c ) 8002396: f7fd fed9 bl 800014c 800239a: 4603 mov r3, r0 800239c: b29b uxth r3, r3 800239e: 4619 mov r1, r3 80023a0: 481e ldr r0, [pc, #120] @ (800241c ) 80023a2: f000 f9a3 bl 80026ec 80023a6: 4603 mov r3, r0 80023a8: 75bb strb r3, [r7, #22] admittance_EC = AD5934_GetImpedance(); 80023aa: f7fe ffcf bl 800134c 80023ae: 6138 str r0, [r7, #16] FloatToString(tempString, admittance_EC); 80023b0: 6938 ldr r0, [r7, #16] 80023b2: f7fe f961 bl 8000678 <__aeabi_f2d> 80023b6: 4602 mov r2, r0 80023b8: 460b mov r3, r1 80023ba: 1d39 adds r1, r7, #4 80023bc: 4608 mov r0, r1 80023be: f000 f88d bl 80024dc status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1)); 80023c2: 1d3b adds r3, r7, #4 80023c4: 4618 mov r0, r3 80023c6: f7fd fec1 bl 800014c 80023ca: 4603 mov r3, r0 80023cc: b29b uxth r3, r3 80023ce: 3b01 subs r3, #1 80023d0: b29a uxth r2, r3 80023d2: 1d3b adds r3, r7, #4 80023d4: 4611 mov r1, r2 80023d6: 4618 mov r0, r3 80023d8: f000 f988 bl 80026ec 80023dc: 4603 mov r3, r0 80023de: 75fb strb r3, [r7, #23] status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi)); 80023e0: 480f ldr r0, [pc, #60] @ (8002420 ) 80023e2: f7fd feb3 bl 800014c 80023e6: 4603 mov r3, r0 80023e8: b29b uxth r3, r3 80023ea: 4619 mov r1, r3 80023ec: 480c ldr r0, [pc, #48] @ (8002420 ) 80023ee: f000 f97d bl 80026ec 80023f2: 4603 mov r3, r0 80023f4: 75bb strb r3, [r7, #22] current_millis = HAL_GetTick(); 80023f6: e721 b.n 800223c 80023f8: 200001d4 .word 0x200001d4 80023fc: 2000027c .word 0x2000027c 8002400: 20000014 .word 0x20000014 8002404: 200001d1 .word 0x200001d1 8002408: 40010c00 .word 0x40010c00 800240c: 200001b4 .word 0x200001b4 8002410: 200001bc .word 0x200001bc 8002414: 200001c0 .word 0x200001c0 8002418: 200001b8 .word 0x200001b8 800241c: 20000004 .word 0x20000004 8002420: 2000000c .word 0x2000000c 08002424 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8002424: b580 push {r7, lr} 8002426: b094 sub sp, #80 @ 0x50 8002428: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800242a: f107 0328 add.w r3, r7, #40 @ 0x28 800242e: 2228 movs r2, #40 @ 0x28 8002430: 2100 movs r1, #0 8002432: 4618 mov r0, r3 8002434: f003 fc66 bl 8005d04 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8002438: f107 0314 add.w r3, r7, #20 800243c: 2200 movs r2, #0 800243e: 601a str r2, [r3, #0] 8002440: 605a str r2, [r3, #4] 8002442: 609a str r2, [r3, #8] 8002444: 60da str r2, [r3, #12] 8002446: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8002448: 1d3b adds r3, r7, #4 800244a: 2200 movs r2, #0 800244c: 601a str r2, [r3, #0] 800244e: 605a str r2, [r3, #4] 8002450: 609a str r2, [r3, #8] 8002452: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8002454: 2301 movs r3, #1 8002456: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8002458: f44f 3380 mov.w r3, #65536 @ 0x10000 800245c: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 800245e: 2300 movs r3, #0 8002460: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8002462: 2301 movs r3, #1 8002464: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8002466: 2302 movs r3, #2 8002468: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800246a: f44f 3380 mov.w r3, #65536 @ 0x10000 800246e: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2; 8002470: 2300 movs r3, #0 8002472: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8002474: f107 0328 add.w r3, r7, #40 @ 0x28 8002478: 4618 mov r0, r3 800247a: f002 f965 bl 8004748 800247e: 4603 mov r3, r0 8002480: 2b00 cmp r3, #0 8002482: d001 beq.n 8002488 { Error_Handler(); 8002484: f000 f8f4 bl 8002670 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8002488: 230f movs r3, #15 800248a: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800248c: 2302 movs r3, #2 800248e: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8002490: 2300 movs r3, #0 8002492: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8002494: f44f 6380 mov.w r3, #1024 @ 0x400 8002498: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 800249a: f44f 6380 mov.w r3, #1024 @ 0x400 800249e: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80024a0: f107 0314 add.w r3, r7, #20 80024a4: 2100 movs r1, #0 80024a6: 4618 mov r0, r3 80024a8: f002 fbd0 bl 8004c4c 80024ac: 4603 mov r3, r0 80024ae: 2b00 cmp r3, #0 80024b0: d001 beq.n 80024b6 { Error_Handler(); 80024b2: f000 f8dd bl 8002670 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80024b6: 2302 movs r3, #2 80024b8: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 80024ba: f44f 4340 mov.w r3, #49152 @ 0xc000 80024be: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80024c0: 1d3b adds r3, r7, #4 80024c2: 4618 mov r0, r3 80024c4: f002 fd52 bl 8004f6c 80024c8: 4603 mov r3, r0 80024ca: 2b00 cmp r3, #0 80024cc: d001 beq.n 80024d2 { Error_Handler(); 80024ce: f000 f8cf bl 8002670 } } 80024d2: bf00 nop 80024d4: 3750 adds r7, #80 @ 0x50 80024d6: 46bd mov sp, r7 80024d8: bd80 pop {r7, pc} ... 080024dc : * @param val - value to be converted * * @return None. *******************************************************************************/ void FloatToString(char * buf, double val) { 80024dc: b580 push {r7, lr} 80024de: b08a sub sp, #40 @ 0x28 80024e0: af00 add r7, sp, #0 80024e2: 60f8 str r0, [r7, #12] 80024e4: e9c7 2300 strd r2, r3, [r7] long intPart = 0; 80024e8: 2300 movs r3, #0 80024ea: 627b str r3, [r7, #36] @ 0x24 short fracPart = 0; 80024ec: 2300 movs r3, #0 80024ee: 847b strh r3, [r7, #34] @ 0x22 short charPos = 0; 80024f0: 2300 movs r3, #0 80024f2: 843b strh r3, [r7, #32] char localBuf[12] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 80024f4: f107 0310 add.w r3, r7, #16 80024f8: 2200 movs r2, #0 80024fa: 601a str r2, [r3, #0] 80024fc: 605a str r2, [r3, #4] 80024fe: 609a str r2, [r3, #8] short i = sizeof(localBuf) - 1; 8002500: 230b movs r3, #11 8002502: 83fb strh r3, [r7, #30] intPart = (long)val; 8002504: e9d7 0100 ldrd r0, r1, [r7] 8002508: f7fe f90e bl 8000728 <__aeabi_d2iz> 800250c: 4603 mov r3, r0 800250e: 627b str r3, [r7, #36] @ 0x24 fracPart = (short)((val - intPart) * 1000 + 0.5); 8002510: 6a78 ldr r0, [r7, #36] @ 0x24 8002512: f7fe f89f bl 8000654 <__aeabi_i2d> 8002516: 4602 mov r2, r0 8002518: 460b mov r3, r1 800251a: e9d7 0100 ldrd r0, r1, [r7] 800251e: f7fd ff4b bl 80003b8 <__aeabi_dsub> 8002522: 4602 mov r2, r0 8002524: 460b mov r3, r1 8002526: 4610 mov r0, r2 8002528: 4619 mov r1, r3 800252a: f04f 0200 mov.w r2, #0 800252e: 4b4d ldr r3, [pc, #308] @ (8002664 ) 8002530: f7fd fe14 bl 800015c <__aeabi_dmul> 8002534: 4602 mov r2, r0 8002536: 460b mov r3, r1 8002538: 4610 mov r0, r2 800253a: 4619 mov r1, r3 800253c: f04f 0200 mov.w r2, #0 8002540: 4b49 ldr r3, [pc, #292] @ (8002668 ) 8002542: f7fd ff3b bl 80003bc <__adddf3> 8002546: 4602 mov r2, r0 8002548: 460b mov r3, r1 800254a: 4610 mov r0, r2 800254c: 4619 mov r1, r3 800254e: f7fe f8eb bl 8000728 <__aeabi_d2iz> 8002552: 4603 mov r3, r0 8002554: 847b strh r3, [r7, #34] @ 0x22 while(i > sizeof(localBuf) - 4) 8002556: e025 b.n 80025a4 { localBuf[i] = (fracPart % 10) + 0x30; 8002558: f9b7 2022 ldrsh.w r2, [r7, #34] @ 0x22 800255c: 4b43 ldr r3, [pc, #268] @ (800266c ) 800255e: fb83 1302 smull r1, r3, r3, r2 8002562: 1099 asrs r1, r3, #2 8002564: 17d3 asrs r3, r2, #31 8002566: 1ac9 subs r1, r1, r3 8002568: 460b mov r3, r1 800256a: 009b lsls r3, r3, #2 800256c: 440b add r3, r1 800256e: 005b lsls r3, r3, #1 8002570: 1ad3 subs r3, r2, r3 8002572: b21b sxth r3, r3 8002574: b2da uxtb r2, r3 8002576: f9b7 301e ldrsh.w r3, [r7, #30] 800257a: 3230 adds r2, #48 @ 0x30 800257c: b2d2 uxtb r2, r2 800257e: 3328 adds r3, #40 @ 0x28 8002580: 443b add r3, r7 8002582: f803 2c18 strb.w r2, [r3, #-24] fracPart /= 10; 8002586: f9b7 3022 ldrsh.w r3, [r7, #34] @ 0x22 800258a: 4a38 ldr r2, [pc, #224] @ (800266c ) 800258c: fb82 1203 smull r1, r2, r2, r3 8002590: 1092 asrs r2, r2, #2 8002592: 17db asrs r3, r3, #31 8002594: 1ad3 subs r3, r2, r3 8002596: 847b strh r3, [r7, #34] @ 0x22 i--; 8002598: f9b7 301e ldrsh.w r3, [r7, #30] 800259c: b29b uxth r3, r3 800259e: 3b01 subs r3, #1 80025a0: b29b uxth r3, r3 80025a2: 83fb strh r3, [r7, #30] while(i > sizeof(localBuf) - 4) 80025a4: 8bfb ldrh r3, [r7, #30] 80025a6: 2b08 cmp r3, #8 80025a8: d8d6 bhi.n 8002558 } localBuf[i] = '.'; 80025aa: f9b7 301e ldrsh.w r3, [r7, #30] 80025ae: 3328 adds r3, #40 @ 0x28 80025b0: 443b add r3, r7 80025b2: 222e movs r2, #46 @ 0x2e 80025b4: f803 2c18 strb.w r2, [r3, #-24] if(intPart == 0) 80025b8: 6a7b ldr r3, [r7, #36] @ 0x24 80025ba: 2b00 cmp r3, #0 80025bc: d130 bne.n 8002620 { i --; 80025be: f9b7 301e ldrsh.w r3, [r7, #30] 80025c2: b29b uxth r3, r3 80025c4: 3b01 subs r3, #1 80025c6: b29b uxth r3, r3 80025c8: 83fb strh r3, [r7, #30] localBuf[i] = '0'; 80025ca: f9b7 301e ldrsh.w r3, [r7, #30] 80025ce: 3328 adds r3, #40 @ 0x28 80025d0: 443b add r3, r7 80025d2: 2230 movs r2, #48 @ 0x30 80025d4: f803 2c18 strb.w r2, [r3, #-24] } while(intPart) 80025d8: e022 b.n 8002620 { i --; 80025da: f9b7 301e ldrsh.w r3, [r7, #30] 80025de: b29b uxth r3, r3 80025e0: 3b01 subs r3, #1 80025e2: b29b uxth r3, r3 80025e4: 83fb strh r3, [r7, #30] localBuf[i] =(intPart % 10) + 0x30; 80025e6: 6a7a ldr r2, [r7, #36] @ 0x24 80025e8: 4b20 ldr r3, [pc, #128] @ (800266c ) 80025ea: fb83 1302 smull r1, r3, r3, r2 80025ee: 1099 asrs r1, r3, #2 80025f0: 17d3 asrs r3, r2, #31 80025f2: 1ac9 subs r1, r1, r3 80025f4: 460b mov r3, r1 80025f6: 009b lsls r3, r3, #2 80025f8: 440b add r3, r1 80025fa: 005b lsls r3, r3, #1 80025fc: 1ad1 subs r1, r2, r3 80025fe: b2ca uxtb r2, r1 8002600: f9b7 301e ldrsh.w r3, [r7, #30] 8002604: 3230 adds r2, #48 @ 0x30 8002606: b2d2 uxtb r2, r2 8002608: 3328 adds r3, #40 @ 0x28 800260a: 443b add r3, r7 800260c: f803 2c18 strb.w r2, [r3, #-24] intPart /= 10; 8002610: 6a7b ldr r3, [r7, #36] @ 0x24 8002612: 4a16 ldr r2, [pc, #88] @ (800266c ) 8002614: fb82 1203 smull r1, r2, r2, r3 8002618: 1092 asrs r2, r2, #2 800261a: 17db asrs r3, r3, #31 800261c: 1ad3 subs r3, r2, r3 800261e: 627b str r3, [r7, #36] @ 0x24 while(intPart) 8002620: 6a7b ldr r3, [r7, #36] @ 0x24 8002622: 2b00 cmp r3, #0 8002624: d1d9 bne.n 80025da } for(charPos = i; charPos < sizeof(localBuf); charPos ++) 8002626: 8bfb ldrh r3, [r7, #30] 8002628: 843b strh r3, [r7, #32] 800262a: e010 b.n 800264e { *buf = localBuf[charPos]; 800262c: f9b7 3020 ldrsh.w r3, [r7, #32] 8002630: 3328 adds r3, #40 @ 0x28 8002632: 443b add r3, r7 8002634: f813 2c18 ldrb.w r2, [r3, #-24] 8002638: 68fb ldr r3, [r7, #12] 800263a: 701a strb r2, [r3, #0] buf ++; 800263c: 68fb ldr r3, [r7, #12] 800263e: 3301 adds r3, #1 8002640: 60fb str r3, [r7, #12] for(charPos = i; charPos < sizeof(localBuf); charPos ++) 8002642: f9b7 3020 ldrsh.w r3, [r7, #32] 8002646: b29b uxth r3, r3 8002648: 3301 adds r3, #1 800264a: b29b uxth r3, r3 800264c: 843b strh r3, [r7, #32] 800264e: 8c3b ldrh r3, [r7, #32] 8002650: 2b0b cmp r3, #11 8002652: d9eb bls.n 800262c } *buf = 0; 8002654: 68fb ldr r3, [r7, #12] 8002656: 2200 movs r2, #0 8002658: 701a strb r2, [r3, #0] } 800265a: bf00 nop 800265c: 3728 adds r7, #40 @ 0x28 800265e: 46bd mov sp, r7 8002660: bd80 pop {r7, pc} 8002662: bf00 nop 8002664: 408f4000 .word 0x408f4000 8002668: 3fe00000 .word 0x3fe00000 800266c: 66666667 .word 0x66666667 08002670 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002670: b480 push {r7} 8002672: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8002674: b672 cpsid i } 8002676: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8002678: bf00 nop 800267a: e7fd b.n 8002678 0800267c : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 800267c: b480 push {r7} 800267e: b083 sub sp, #12 8002680: af00 add r7, sp, #0 8002682: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 8002684: 687b ldr r3, [r7, #4] 8002686: 689b ldr r3, [r3, #8] } 8002688: 4618 mov r0, r3 800268a: 370c adds r7, #12 800268c: 46bd mov sp, r7 800268e: bc80 pop {r7} 8002690: 4770 bx lr ... 08002694 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 8002694: b580 push {r7, lr} 8002696: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 8002698: f000 f864 bl 8002764 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 800269c: f000 f8a8 bl 80027f0 /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 80026a0: f000 f808 bl 80026b4 80026a4: 4603 mov r3, r0 80026a6: 461a mov r2, r3 80026a8: 4b01 ldr r3, [pc, #4] @ (80026b0 ) 80026aa: 709a strb r2, [r3, #2] } 80026ac: bf00 nop 80026ae: bd80 pop {r7, pc} 80026b0: 2000028c .word 0x2000028c 080026b4 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 80026b4: b598 push {r3, r4, r7, lr} 80026b6: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 80026b8: 480a ldr r0, [pc, #40] @ (80026e4 ) 80026ba: f7ff ffdf bl 800267c 80026be: 4603 mov r3, r0 80026c0: 0a1b lsrs r3, r3, #8 80026c2: b2db uxtb r3, r3 80026c4: f023 030f bic.w r3, r3, #15 80026c8: b2dc uxtb r4, r3 80026ca: 4807 ldr r0, [pc, #28] @ (80026e8 ) 80026cc: f7ff ffd6 bl 800267c 80026d0: 4603 mov r3, r0 80026d2: 089b lsrs r3, r3, #2 80026d4: b2db uxtb r3, r3 80026d6: f003 030f and.w r3, r3, #15 80026da: b2db uxtb r3, r3 80026dc: 4323 orrs r3, r4 80026de: b2db uxtb r3, r3 } 80026e0: 4618 mov r0, r3 80026e2: bd98 pop {r3, r4, r7, pc} 80026e4: 40010c00 .word 0x40010c00 80026e8: 40010800 .word 0x40010800 080026ec : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 80026ec: b580 push {r7, lr} 80026ee: b084 sub sp, #16 80026f0: af00 add r7, sp, #0 80026f2: 6078 str r0, [r7, #4] 80026f4: 460b mov r3, r1 80026f6: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 80026f8: f000 f81c bl 8002734 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 80026fc: 2300 movs r3, #0 80026fe: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8002700: f107 010e add.w r1, r7, #14 8002704: f04f 33ff mov.w r3, #4294967295 8002708: 2201 movs r2, #1 800270a: 4809 ldr r0, [pc, #36] @ (8002730 ) 800270c: f002 fd34 bl 8005178 /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 8002710: 887a ldrh r2, [r7, #2] 8002712: f04f 33ff mov.w r3, #4294967295 8002716: 6879 ldr r1, [r7, #4] 8002718: 4805 ldr r0, [pc, #20] @ (8002730 ) 800271a: f002 fd2d bl 8005178 800271e: 4603 mov r3, r0 8002720: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 8002722: f000 f813 bl 800274c return status; 8002726: 7bfb ldrb r3, [r7, #15] } 8002728: 4618 mov r0, r3 800272a: 3710 adds r7, #16 800272c: 46bd mov sp, r7 800272e: bd80 pop {r7, pc} 8002730: 20000290 .word 0x20000290 08002734 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 8002734: b580 push {r7, lr} 8002736: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 8002738: 2201 movs r2, #1 800273a: f44f 5180 mov.w r1, #4096 @ 0x1000 800273e: 4802 ldr r0, [pc, #8] @ (8002748 ) 8002740: f000 ff9d bl 800367e } 8002744: bf00 nop 8002746: bd80 pop {r7, pc} 8002748: 40010800 .word 0x40010800 0800274c : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 800274c: b580 push {r7, lr} 800274e: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 8002750: 2200 movs r2, #0 8002752: f44f 5180 mov.w r1, #4096 @ 0x1000 8002756: 4802 ldr r0, [pc, #8] @ (8002760 ) 8002758: f000 ff91 bl 800367e } 800275c: bf00 nop 800275e: bd80 pop {r7, pc} 8002760: 40010800 .word 0x40010800 08002764 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 8002764: b580 push {r7, lr} 8002766: b086 sub sp, #24 8002768: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800276a: f107 0308 add.w r3, r7, #8 800276e: 2200 movs r2, #0 8002770: 601a str r2, [r3, #0] 8002772: 605a str r2, [r3, #4] 8002774: 609a str r2, [r3, #8] 8002776: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002778: 4b1a ldr r3, [pc, #104] @ (80027e4 ) 800277a: 699b ldr r3, [r3, #24] 800277c: 4a19 ldr r2, [pc, #100] @ (80027e4 ) 800277e: f043 0304 orr.w r3, r3, #4 8002782: 6193 str r3, [r2, #24] 8002784: 4b17 ldr r3, [pc, #92] @ (80027e4 ) 8002786: 699b ldr r3, [r3, #24] 8002788: f003 0304 and.w r3, r3, #4 800278c: 607b str r3, [r7, #4] 800278e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002790: 4b14 ldr r3, [pc, #80] @ (80027e4 ) 8002792: 699b ldr r3, [r3, #24] 8002794: 4a13 ldr r2, [pc, #76] @ (80027e4 ) 8002796: f043 0308 orr.w r3, r3, #8 800279a: 6193 str r3, [r2, #24] 800279c: 4b11 ldr r3, [pc, #68] @ (80027e4 ) 800279e: 699b ldr r3, [r3, #24] 80027a0: f003 0308 and.w r3, r3, #8 80027a4: 603b str r3, [r7, #0] 80027a6: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 80027a8: 233c movs r3, #60 @ 0x3c 80027aa: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80027ac: 2300 movs r3, #0 80027ae: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80027b0: 2301 movs r3, #1 80027b2: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80027b4: f107 0308 add.w r3, r7, #8 80027b8: 4619 mov r1, r3 80027ba: 480b ldr r0, [pc, #44] @ (80027e8 ) 80027bc: f000 fdc4 bl 8003348 /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 80027c0: f44f 4370 mov.w r3, #61440 @ 0xf000 80027c4: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80027c6: 2300 movs r3, #0 80027c8: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80027ca: 2301 movs r3, #1 80027cc: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80027ce: f107 0308 add.w r3, r7, #8 80027d2: 4619 mov r1, r3 80027d4: 4805 ldr r0, [pc, #20] @ (80027ec ) 80027d6: f000 fdb7 bl 8003348 } 80027da: bf00 nop 80027dc: 3718 adds r7, #24 80027de: 46bd mov sp, r7 80027e0: bd80 pop {r7, pc} 80027e2: bf00 nop 80027e4: 40021000 .word 0x40021000 80027e8: 40010800 .word 0x40010800 80027ec: 40010c00 .word 0x40010c00 080027f0 : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 80027f0: b580 push {r7, lr} 80027f2: b082 sub sp, #8 80027f4: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 80027f6: 4b18 ldr r3, [pc, #96] @ (8002858 ) 80027f8: 699b ldr r3, [r3, #24] 80027fa: 4a17 ldr r2, [pc, #92] @ (8002858 ) 80027fc: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002800: 6193 str r3, [r2, #24] 8002802: 4b15 ldr r3, [pc, #84] @ (8002858 ) 8002804: 699b ldr r3, [r3, #24] 8002806: f403 4380 and.w r3, r3, #16384 @ 0x4000 800280a: 607b str r3, [r7, #4] 800280c: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 800280e: 4b13 ldr r3, [pc, #76] @ (800285c ) 8002810: 4a13 ldr r2, [pc, #76] @ (8002860 ) 8002812: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002814: 4b11 ldr r3, [pc, #68] @ (800285c ) 8002816: f44f 5216 mov.w r2, #9600 @ 0x2580 800281a: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800281c: 4b0f ldr r3, [pc, #60] @ (800285c ) 800281e: 2200 movs r2, #0 8002820: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002822: 4b0e ldr r3, [pc, #56] @ (800285c ) 8002824: 2200 movs r2, #0 8002826: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8002828: 4b0c ldr r3, [pc, #48] @ (800285c ) 800282a: 2200 movs r2, #0 800282c: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800282e: 4b0b ldr r3, [pc, #44] @ (800285c ) 8002830: 220c movs r2, #12 8002832: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 8002834: 4b09 ldr r3, [pc, #36] @ (800285c ) 8002836: 2200 movs r2, #0 8002838: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800283a: 4b08 ldr r3, [pc, #32] @ (800285c ) 800283c: 2200 movs r2, #0 800283e: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002840: 4806 ldr r0, [pc, #24] @ (800285c ) 8002842: f002 fc49 bl 80050d8 8002846: 4603 mov r3, r0 8002848: 2b00 cmp r3, #0 800284a: d001 beq.n 8002850 { /* Initialization Error */ while(1); 800284c: bf00 nop 800284e: e7fd b.n 800284c } } 8002850: bf00 nop 8002852: 3708 adds r7, #8 8002854: 46bd mov sp, r7 8002856: bd80 pop {r7, pc} 8002858: 40021000 .word 0x40021000 800285c: 20000290 .word 0x20000290 8002860: 40013800 .word 0x40013800 08002864 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002864: b480 push {r7} 8002866: b085 sub sp, #20 8002868: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800286a: 4b15 ldr r3, [pc, #84] @ (80028c0 ) 800286c: 699b ldr r3, [r3, #24] 800286e: 4a14 ldr r2, [pc, #80] @ (80028c0 ) 8002870: f043 0301 orr.w r3, r3, #1 8002874: 6193 str r3, [r2, #24] 8002876: 4b12 ldr r3, [pc, #72] @ (80028c0 ) 8002878: 699b ldr r3, [r3, #24] 800287a: f003 0301 and.w r3, r3, #1 800287e: 60bb str r3, [r7, #8] 8002880: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8002882: 4b0f ldr r3, [pc, #60] @ (80028c0 ) 8002884: 69db ldr r3, [r3, #28] 8002886: 4a0e ldr r2, [pc, #56] @ (80028c0 ) 8002888: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800288c: 61d3 str r3, [r2, #28] 800288e: 4b0c ldr r3, [pc, #48] @ (80028c0 ) 8002890: 69db ldr r3, [r3, #28] 8002892: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002896: 607b str r3, [r7, #4] 8002898: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800289a: 4b0a ldr r3, [pc, #40] @ (80028c4 ) 800289c: 685b ldr r3, [r3, #4] 800289e: 60fb str r3, [r7, #12] 80028a0: 68fb ldr r3, [r7, #12] 80028a2: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 80028a6: 60fb str r3, [r7, #12] 80028a8: 68fb ldr r3, [r7, #12] 80028aa: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80028ae: 60fb str r3, [r7, #12] 80028b0: 4a04 ldr r2, [pc, #16] @ (80028c4 ) 80028b2: 68fb ldr r3, [r7, #12] 80028b4: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80028b6: bf00 nop 80028b8: 3714 adds r7, #20 80028ba: 46bd mov sp, r7 80028bc: bc80 pop {r7} 80028be: 4770 bx lr 80028c0: 40021000 .word 0x40021000 80028c4: 40010000 .word 0x40010000 080028c8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80028c8: b480 push {r7} 80028ca: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80028cc: bf00 nop 80028ce: e7fd b.n 80028cc 080028d0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80028d0: b480 push {r7} 80028d2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80028d4: bf00 nop 80028d6: e7fd b.n 80028d4 080028d8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80028d8: b480 push {r7} 80028da: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80028dc: bf00 nop 80028de: e7fd b.n 80028dc 080028e0 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80028e0: b480 push {r7} 80028e2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80028e4: bf00 nop 80028e6: e7fd b.n 80028e4 080028e8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80028e8: b480 push {r7} 80028ea: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80028ec: bf00 nop 80028ee: e7fd b.n 80028ec 080028f0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80028f0: b480 push {r7} 80028f2: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80028f4: bf00 nop 80028f6: 46bd mov sp, r7 80028f8: bc80 pop {r7} 80028fa: 4770 bx lr 080028fc : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80028fc: b480 push {r7} 80028fe: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002900: bf00 nop 8002902: 46bd mov sp, r7 8002904: bc80 pop {r7} 8002906: 4770 bx lr 08002908 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002908: b480 push {r7} 800290a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800290c: bf00 nop 800290e: 46bd mov sp, r7 8002910: bc80 pop {r7} 8002912: 4770 bx lr 08002914 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002914: b580 push {r7, lr} 8002916: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002918: f000 f904 bl 8002b24 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800291c: bf00 nop 800291e: bd80 pop {r7, pc} 08002920 : /** * @brief This function handles EXTI line3 interrupt. */ void EXTI3_IRQHandler(void) { 8002920: b580 push {r7, lr} 8002922: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI3_IRQn 0 */ /* USER CODE END EXTI3_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(Calib_PH_Pin); 8002924: 2008 movs r0, #8 8002926: f000 fec3 bl 80036b0 /* USER CODE BEGIN EXTI3_IRQn 1 */ /* USER CODE END EXTI3_IRQn 1 */ } 800292a: bf00 nop 800292c: bd80 pop {r7, pc} ... 08002930 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8002930: b580 push {r7, lr} 8002932: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8002934: 4802 ldr r0, [pc, #8] @ (8002940 ) 8002936: f002 fcab bl 8005290 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800293a: bf00 nop 800293c: bd80 pop {r7, pc} 800293e: bf00 nop 8002940: 200002d8 .word 0x200002d8 08002944 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8002944: b480 push {r7} 8002946: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002948: bf00 nop 800294a: 46bd mov sp, r7 800294c: bc80 pop {r7} 800294e: 4770 bx lr 08002950 : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 8002950: b580 push {r7, lr} 8002952: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8002954: 4b11 ldr r3, [pc, #68] @ (800299c ) 8002956: 4a12 ldr r2, [pc, #72] @ (80029a0 ) 8002958: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800295a: 4b10 ldr r3, [pc, #64] @ (800299c ) 800295c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8002960: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002962: 4b0e ldr r3, [pc, #56] @ (800299c ) 8002964: 2200 movs r2, #0 8002966: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002968: 4b0c ldr r3, [pc, #48] @ (800299c ) 800296a: 2200 movs r2, #0 800296c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800296e: 4b0b ldr r3, [pc, #44] @ (800299c ) 8002970: 2200 movs r2, #0 8002972: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002974: 4b09 ldr r3, [pc, #36] @ (800299c ) 8002976: 220c movs r2, #12 8002978: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800297a: 4b08 ldr r3, [pc, #32] @ (800299c ) 800297c: 2200 movs r2, #0 800297e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002980: 4b06 ldr r3, [pc, #24] @ (800299c ) 8002982: 2200 movs r2, #0 8002984: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002986: 4805 ldr r0, [pc, #20] @ (800299c ) 8002988: f002 fba6 bl 80050d8 800298c: 4603 mov r3, r0 800298e: 2b00 cmp r3, #0 8002990: d001 beq.n 8002996 { Error_Handler(); 8002992: f7ff fe6d bl 8002670 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8002996: bf00 nop 8002998: bd80 pop {r7, pc} 800299a: bf00 nop 800299c: 200002d8 .word 0x200002d8 80029a0: 40013800 .word 0x40013800 080029a4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80029a4: b580 push {r7, lr} 80029a6: b088 sub sp, #32 80029a8: af00 add r7, sp, #0 80029aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80029ac: f107 0310 add.w r3, r7, #16 80029b0: 2200 movs r2, #0 80029b2: 601a str r2, [r3, #0] 80029b4: 605a str r2, [r3, #4] 80029b6: 609a str r2, [r3, #8] 80029b8: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 80029ba: 687b ldr r3, [r7, #4] 80029bc: 681b ldr r3, [r3, #0] 80029be: 4a20 ldr r2, [pc, #128] @ (8002a40 ) 80029c0: 4293 cmp r3, r2 80029c2: d139 bne.n 8002a38 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80029c4: 4b1f ldr r3, [pc, #124] @ (8002a44 ) 80029c6: 699b ldr r3, [r3, #24] 80029c8: 4a1e ldr r2, [pc, #120] @ (8002a44 ) 80029ca: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80029ce: 6193 str r3, [r2, #24] 80029d0: 4b1c ldr r3, [pc, #112] @ (8002a44 ) 80029d2: 699b ldr r3, [r3, #24] 80029d4: f403 4380 and.w r3, r3, #16384 @ 0x4000 80029d8: 60fb str r3, [r7, #12] 80029da: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80029dc: 4b19 ldr r3, [pc, #100] @ (8002a44 ) 80029de: 699b ldr r3, [r3, #24] 80029e0: 4a18 ldr r2, [pc, #96] @ (8002a44 ) 80029e2: f043 0304 orr.w r3, r3, #4 80029e6: 6193 str r3, [r2, #24] 80029e8: 4b16 ldr r3, [pc, #88] @ (8002a44 ) 80029ea: 699b ldr r3, [r3, #24] 80029ec: f003 0304 and.w r3, r3, #4 80029f0: 60bb str r3, [r7, #8] 80029f2: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 80029f4: f44f 7300 mov.w r3, #512 @ 0x200 80029f8: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80029fa: 2302 movs r3, #2 80029fc: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 80029fe: 2301 movs r3, #1 8002a00: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 8002a02: f107 0310 add.w r3, r7, #16 8002a06: 4619 mov r1, r3 8002a08: 480f ldr r0, [pc, #60] @ (8002a48 ) 8002a0a: f000 fc9d bl 8003348 GPIO_InitStruct.Pin = RX_RS485_Pin; 8002a0e: f44f 6380 mov.w r3, #1024 @ 0x400 8002a12: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002a14: 2300 movs r3, #0 8002a16: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002a18: 2300 movs r3, #0 8002a1a: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 8002a1c: f107 0310 add.w r3, r7, #16 8002a20: 4619 mov r1, r3 8002a22: 4809 ldr r0, [pc, #36] @ (8002a48 ) 8002a24: f000 fc90 bl 8003348 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8002a28: 2200 movs r2, #0 8002a2a: 2100 movs r1, #0 8002a2c: 2025 movs r0, #37 @ 0x25 8002a2e: f000 fba2 bl 8003176 HAL_NVIC_EnableIRQ(USART1_IRQn); 8002a32: 2025 movs r0, #37 @ 0x25 8002a34: f000 fbbb bl 80031ae /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002a38: bf00 nop 8002a3a: 3720 adds r7, #32 8002a3c: 46bd mov sp, r7 8002a3e: bd80 pop {r7, pc} 8002a40: 40013800 .word 0x40013800 8002a44: 40021000 .word 0x40021000 8002a48: 40010800 .word 0x40010800 08002a4c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8002a4c: f7ff ff7a bl 8002944 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002a50: 480b ldr r0, [pc, #44] @ (8002a80 ) ldr r1, =_edata 8002a52: 490c ldr r1, [pc, #48] @ (8002a84 ) ldr r2, =_sidata 8002a54: 4a0c ldr r2, [pc, #48] @ (8002a88 ) movs r3, #0 8002a56: 2300 movs r3, #0 b LoopCopyDataInit 8002a58: e002 b.n 8002a60 08002a5a : CopyDataInit: ldr r4, [r2, r3] 8002a5a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002a5c: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002a5e: 3304 adds r3, #4 08002a60 : LoopCopyDataInit: adds r4, r0, r3 8002a60: 18c4 adds r4, r0, r3 cmp r4, r1 8002a62: 428c cmp r4, r1 bcc CopyDataInit 8002a64: d3f9 bcc.n 8002a5a /* Zero fill the bss segment. */ ldr r2, =_sbss 8002a66: 4a09 ldr r2, [pc, #36] @ (8002a8c ) ldr r4, =_ebss 8002a68: 4c09 ldr r4, [pc, #36] @ (8002a90 ) movs r3, #0 8002a6a: 2300 movs r3, #0 b LoopFillZerobss 8002a6c: e001 b.n 8002a72 08002a6e : FillZerobss: str r3, [r2] 8002a6e: 6013 str r3, [r2, #0] adds r2, r2, #4 8002a70: 3204 adds r2, #4 08002a72 : LoopFillZerobss: cmp r2, r4 8002a72: 42a2 cmp r2, r4 bcc FillZerobss 8002a74: d3fb bcc.n 8002a6e /* Call static constructors */ bl __libc_init_array 8002a76: f003 f953 bl 8005d20 <__libc_init_array> /* Call the application's entry point.*/ bl main 8002a7a: f7ff fba7 bl 80021cc
bx lr 8002a7e: 4770 bx lr ldr r0, =_sdata 8002a80: 20000000 .word 0x20000000 ldr r1, =_edata 8002a84: 20000078 .word 0x20000078 ldr r2, =_sidata 8002a88: 08005f78 .word 0x08005f78 ldr r2, =_sbss 8002a8c: 20000078 .word 0x20000078 ldr r4, =_ebss 8002a90: 2000045c .word 0x2000045c 08002a94 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002a94: e7fe b.n 8002a94 ... 08002a98 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002a98: b580 push {r7, lr} 8002a9a: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002a9c: 4b08 ldr r3, [pc, #32] @ (8002ac0 ) 8002a9e: 681b ldr r3, [r3, #0] 8002aa0: 4a07 ldr r2, [pc, #28] @ (8002ac0 ) 8002aa2: f043 0310 orr.w r3, r3, #16 8002aa6: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002aa8: 2003 movs r0, #3 8002aaa: f000 fb59 bl 8003160 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002aae: 200f movs r0, #15 8002ab0: f000 f808 bl 8002ac4 /* Init the low level hardware */ HAL_MspInit(); 8002ab4: f7ff fed6 bl 8002864 /* Return function status */ return HAL_OK; 8002ab8: 2300 movs r3, #0 } 8002aba: 4618 mov r0, r3 8002abc: bd80 pop {r7, pc} 8002abe: bf00 nop 8002ac0: 40022000 .word 0x40022000 08002ac4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8002ac4: b580 push {r7, lr} 8002ac6: b082 sub sp, #8 8002ac8: af00 add r7, sp, #0 8002aca: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8002acc: 4b12 ldr r3, [pc, #72] @ (8002b18 ) 8002ace: 681a ldr r2, [r3, #0] 8002ad0: 4b12 ldr r3, [pc, #72] @ (8002b1c ) 8002ad2: 781b ldrb r3, [r3, #0] 8002ad4: 4619 mov r1, r3 8002ad6: f44f 737a mov.w r3, #1000 @ 0x3e8 8002ada: fbb3 f3f1 udiv r3, r3, r1 8002ade: fbb2 f3f3 udiv r3, r2, r3 8002ae2: 4618 mov r0, r3 8002ae4: f000 fb71 bl 80031ca 8002ae8: 4603 mov r3, r0 8002aea: 2b00 cmp r3, #0 8002aec: d001 beq.n 8002af2 { return HAL_ERROR; 8002aee: 2301 movs r3, #1 8002af0: e00e b.n 8002b10 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8002af2: 687b ldr r3, [r7, #4] 8002af4: 2b0f cmp r3, #15 8002af6: d80a bhi.n 8002b0e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8002af8: 2200 movs r2, #0 8002afa: 6879 ldr r1, [r7, #4] 8002afc: f04f 30ff mov.w r0, #4294967295 8002b00: f000 fb39 bl 8003176 uwTickPrio = TickPriority; 8002b04: 4a06 ldr r2, [pc, #24] @ (8002b20 ) 8002b06: 687b ldr r3, [r7, #4] 8002b08: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8002b0a: 2300 movs r3, #0 8002b0c: e000 b.n 8002b10 return HAL_ERROR; 8002b0e: 2301 movs r3, #1 } 8002b10: 4618 mov r0, r3 8002b12: 3708 adds r7, #8 8002b14: 46bd mov sp, r7 8002b16: bd80 pop {r7, pc} 8002b18: 2000001c .word 0x2000001c 8002b1c: 20000024 .word 0x20000024 8002b20: 20000020 .word 0x20000020 08002b24 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8002b24: b480 push {r7} 8002b26: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002b28: 4b05 ldr r3, [pc, #20] @ (8002b40 ) 8002b2a: 781b ldrb r3, [r3, #0] 8002b2c: 461a mov r2, r3 8002b2e: 4b05 ldr r3, [pc, #20] @ (8002b44 ) 8002b30: 681b ldr r3, [r3, #0] 8002b32: 4413 add r3, r2 8002b34: 4a03 ldr r2, [pc, #12] @ (8002b44 ) 8002b36: 6013 str r3, [r2, #0] } 8002b38: bf00 nop 8002b3a: 46bd mov sp, r7 8002b3c: bc80 pop {r7} 8002b3e: 4770 bx lr 8002b40: 20000024 .word 0x20000024 8002b44: 20000320 .word 0x20000320 08002b48 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002b48: b480 push {r7} 8002b4a: af00 add r7, sp, #0 return uwTick; 8002b4c: 4b02 ldr r3, [pc, #8] @ (8002b58 ) 8002b4e: 681b ldr r3, [r3, #0] } 8002b50: 4618 mov r0, r3 8002b52: 46bd mov sp, r7 8002b54: bc80 pop {r7} 8002b56: 4770 bx lr 8002b58: 20000320 .word 0x20000320 08002b5c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8002b5c: b580 push {r7, lr} 8002b5e: b084 sub sp, #16 8002b60: af00 add r7, sp, #0 8002b62: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8002b64: f7ff fff0 bl 8002b48 8002b68: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8002b6e: 68fb ldr r3, [r7, #12] 8002b70: f1b3 3fff cmp.w r3, #4294967295 8002b74: d005 beq.n 8002b82 { wait += (uint32_t)(uwTickFreq); 8002b76: 4b0a ldr r3, [pc, #40] @ (8002ba0 ) 8002b78: 781b ldrb r3, [r3, #0] 8002b7a: 461a mov r2, r3 8002b7c: 68fb ldr r3, [r7, #12] 8002b7e: 4413 add r3, r2 8002b80: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8002b82: bf00 nop 8002b84: f7ff ffe0 bl 8002b48 8002b88: 4602 mov r2, r0 8002b8a: 68bb ldr r3, [r7, #8] 8002b8c: 1ad3 subs r3, r2, r3 8002b8e: 68fa ldr r2, [r7, #12] 8002b90: 429a cmp r2, r3 8002b92: d8f7 bhi.n 8002b84 { } } 8002b94: bf00 nop 8002b96: bf00 nop 8002b98: 3710 adds r7, #16 8002b9a: 46bd mov sp, r7 8002b9c: bd80 pop {r7, pc} 8002b9e: bf00 nop 8002ba0: 20000024 .word 0x20000024 08002ba4 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8002ba4: b580 push {r7, lr} 8002ba6: b086 sub sp, #24 8002ba8: af00 add r7, sp, #0 8002baa: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002bac: 2300 movs r3, #0 8002bae: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8002bb0: 2300 movs r3, #0 8002bb2: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8002bb4: 2300 movs r3, #0 8002bb6: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8002bb8: 2300 movs r3, #0 8002bba: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8002bbc: 687b ldr r3, [r7, #4] 8002bbe: 2b00 cmp r3, #0 8002bc0: d101 bne.n 8002bc6 { return HAL_ERROR; 8002bc2: 2301 movs r3, #1 8002bc4: e0be b.n 8002d44 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8002bc6: 687b ldr r3, [r7, #4] 8002bc8: 689b ldr r3, [r3, #8] 8002bca: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8002bcc: 687b ldr r3, [r7, #4] 8002bce: 6a9b ldr r3, [r3, #40] @ 0x28 8002bd0: 2b00 cmp r3, #0 8002bd2: d109 bne.n 8002be8 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8002bd4: 687b ldr r3, [r7, #4] 8002bd6: 2200 movs r2, #0 8002bd8: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8002bda: 687b ldr r3, [r7, #4] 8002bdc: 2200 movs r2, #0 8002bde: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8002be2: 6878 ldr r0, [r7, #4] 8002be4: f7fe ff1a bl 8001a1c /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8002be8: 6878 ldr r0, [r7, #4] 8002bea: f000 f9ab bl 8002f44 8002bee: 4603 mov r3, r0 8002bf0: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8002bf2: 687b ldr r3, [r7, #4] 8002bf4: 6a9b ldr r3, [r3, #40] @ 0x28 8002bf6: f003 0310 and.w r3, r3, #16 8002bfa: 2b00 cmp r3, #0 8002bfc: f040 8099 bne.w 8002d32 8002c00: 7dfb ldrb r3, [r7, #23] 8002c02: 2b00 cmp r3, #0 8002c04: f040 8095 bne.w 8002d32 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 6a9b ldr r3, [r3, #40] @ 0x28 8002c0c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8002c10: f023 0302 bic.w r3, r3, #2 8002c14: f043 0202 orr.w r2, r3, #2 8002c18: 687b ldr r3, [r7, #4] 8002c1a: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002c20: 687b ldr r3, [r7, #4] 8002c22: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8002c24: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8002c26: 687b ldr r3, [r7, #4] 8002c28: 7b1b ldrb r3, [r3, #12] 8002c2a: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8002c2c: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8002c2e: 68ba ldr r2, [r7, #8] 8002c30: 4313 orrs r3, r2 8002c32: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8002c34: 687b ldr r3, [r7, #4] 8002c36: 689b ldr r3, [r3, #8] 8002c38: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002c3c: d003 beq.n 8002c46 8002c3e: 687b ldr r3, [r7, #4] 8002c40: 689b ldr r3, [r3, #8] 8002c42: 2b01 cmp r3, #1 8002c44: d102 bne.n 8002c4c 8002c46: f44f 7380 mov.w r3, #256 @ 0x100 8002c4a: e000 b.n 8002c4e 8002c4c: 2300 movs r3, #0 8002c4e: 693a ldr r2, [r7, #16] 8002c50: 4313 orrs r3, r2 8002c52: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8002c54: 687b ldr r3, [r7, #4] 8002c56: 7d1b ldrb r3, [r3, #20] 8002c58: 2b01 cmp r3, #1 8002c5a: d119 bne.n 8002c90 { if (hadc->Init.ContinuousConvMode == DISABLE) 8002c5c: 687b ldr r3, [r7, #4] 8002c5e: 7b1b ldrb r3, [r3, #12] 8002c60: 2b00 cmp r3, #0 8002c62: d109 bne.n 8002c78 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8002c64: 687b ldr r3, [r7, #4] 8002c66: 699b ldr r3, [r3, #24] 8002c68: 3b01 subs r3, #1 8002c6a: 035a lsls r2, r3, #13 8002c6c: 693b ldr r3, [r7, #16] 8002c6e: 4313 orrs r3, r2 8002c70: f443 6300 orr.w r3, r3, #2048 @ 0x800 8002c74: 613b str r3, [r7, #16] 8002c76: e00b b.n 8002c90 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002c78: 687b ldr r3, [r7, #4] 8002c7a: 6a9b ldr r3, [r3, #40] @ 0x28 8002c7c: f043 0220 orr.w r2, r3, #32 8002c80: 687b ldr r3, [r7, #4] 8002c82: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002c84: 687b ldr r3, [r7, #4] 8002c86: 6adb ldr r3, [r3, #44] @ 0x2c 8002c88: f043 0201 orr.w r2, r3, #1 8002c8c: 687b ldr r3, [r7, #4] 8002c8e: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8002c90: 687b ldr r3, [r7, #4] 8002c92: 681b ldr r3, [r3, #0] 8002c94: 685b ldr r3, [r3, #4] 8002c96: f423 4169 bic.w r1, r3, #59648 @ 0xe900 8002c9a: 687b ldr r3, [r7, #4] 8002c9c: 681b ldr r3, [r3, #0] 8002c9e: 693a ldr r2, [r7, #16] 8002ca0: 430a orrs r2, r1 8002ca2: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8002ca4: 687b ldr r3, [r7, #4] 8002ca6: 681b ldr r3, [r3, #0] 8002ca8: 689a ldr r2, [r3, #8] 8002caa: 4b28 ldr r3, [pc, #160] @ (8002d4c ) 8002cac: 4013 ands r3, r2 8002cae: 687a ldr r2, [r7, #4] 8002cb0: 6812 ldr r2, [r2, #0] 8002cb2: 68b9 ldr r1, [r7, #8] 8002cb4: 430b orrs r3, r1 8002cb6: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8002cb8: 687b ldr r3, [r7, #4] 8002cba: 689b ldr r3, [r3, #8] 8002cbc: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002cc0: d003 beq.n 8002cca 8002cc2: 687b ldr r3, [r7, #4] 8002cc4: 689b ldr r3, [r3, #8] 8002cc6: 2b01 cmp r3, #1 8002cc8: d104 bne.n 8002cd4 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8002cca: 687b ldr r3, [r7, #4] 8002ccc: 691b ldr r3, [r3, #16] 8002cce: 3b01 subs r3, #1 8002cd0: 051b lsls r3, r3, #20 8002cd2: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8002cd4: 687b ldr r3, [r7, #4] 8002cd6: 681b ldr r3, [r3, #0] 8002cd8: 6adb ldr r3, [r3, #44] @ 0x2c 8002cda: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 681b ldr r3, [r3, #0] 8002ce2: 68fa ldr r2, [r7, #12] 8002ce4: 430a orrs r2, r1 8002ce6: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002ce8: 687b ldr r3, [r7, #4] 8002cea: 681b ldr r3, [r3, #0] 8002cec: 689a ldr r2, [r3, #8] 8002cee: 4b18 ldr r3, [pc, #96] @ (8002d50 ) 8002cf0: 4013 ands r3, r2 8002cf2: 68ba ldr r2, [r7, #8] 8002cf4: 429a cmp r2, r3 8002cf6: d10b bne.n 8002d10 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 2200 movs r2, #0 8002cfc: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002cfe: 687b ldr r3, [r7, #4] 8002d00: 6a9b ldr r3, [r3, #40] @ 0x28 8002d02: f023 0303 bic.w r3, r3, #3 8002d06: f043 0201 orr.w r2, r3, #1 8002d0a: 687b ldr r3, [r7, #4] 8002d0c: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002d0e: e018 b.n 8002d42 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002d10: 687b ldr r3, [r7, #4] 8002d12: 6a9b ldr r3, [r3, #40] @ 0x28 8002d14: f023 0312 bic.w r3, r3, #18 8002d18: f043 0210 orr.w r2, r3, #16 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002d20: 687b ldr r3, [r7, #4] 8002d22: 6adb ldr r3, [r3, #44] @ 0x2c 8002d24: f043 0201 orr.w r2, r3, #1 8002d28: 687b ldr r3, [r7, #4] 8002d2a: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8002d2c: 2301 movs r3, #1 8002d2e: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8002d30: e007 b.n 8002d42 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002d32: 687b ldr r3, [r7, #4] 8002d34: 6a9b ldr r3, [r3, #40] @ 0x28 8002d36: f043 0210 orr.w r2, r3, #16 8002d3a: 687b ldr r3, [r7, #4] 8002d3c: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8002d3e: 2301 movs r3, #1 8002d40: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8002d42: 7dfb ldrb r3, [r7, #23] } 8002d44: 4618 mov r0, r3 8002d46: 3718 adds r7, #24 8002d48: 46bd mov sp, r7 8002d4a: bd80 pop {r7, pc} 8002d4c: ffe1f7fd .word 0xffe1f7fd 8002d50: ff1f0efe .word 0xff1f0efe 08002d54 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002d54: b480 push {r7} 8002d56: b085 sub sp, #20 8002d58: af00 add r7, sp, #0 8002d5a: 6078 str r0, [r7, #4] 8002d5c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002d5e: 2300 movs r3, #0 8002d60: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8002d62: 2300 movs r3, #0 8002d64: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8002d66: 687b ldr r3, [r7, #4] 8002d68: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8002d6c: 2b01 cmp r3, #1 8002d6e: d101 bne.n 8002d74 8002d70: 2302 movs r3, #2 8002d72: e0dc b.n 8002f2e 8002d74: 687b ldr r3, [r7, #4] 8002d76: 2201 movs r2, #1 8002d78: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8002d7c: 683b ldr r3, [r7, #0] 8002d7e: 685b ldr r3, [r3, #4] 8002d80: 2b06 cmp r3, #6 8002d82: d81c bhi.n 8002dbe { MODIFY_REG(hadc->Instance->SQR3 , 8002d84: 687b ldr r3, [r7, #4] 8002d86: 681b ldr r3, [r3, #0] 8002d88: 6b59 ldr r1, [r3, #52] @ 0x34 8002d8a: 683b ldr r3, [r7, #0] 8002d8c: 685a ldr r2, [r3, #4] 8002d8e: 4613 mov r3, r2 8002d90: 009b lsls r3, r3, #2 8002d92: 4413 add r3, r2 8002d94: 3b05 subs r3, #5 8002d96: 221f movs r2, #31 8002d98: fa02 f303 lsl.w r3, r2, r3 8002d9c: 43db mvns r3, r3 8002d9e: 4019 ands r1, r3 8002da0: 683b ldr r3, [r7, #0] 8002da2: 6818 ldr r0, [r3, #0] 8002da4: 683b ldr r3, [r7, #0] 8002da6: 685a ldr r2, [r3, #4] 8002da8: 4613 mov r3, r2 8002daa: 009b lsls r3, r3, #2 8002dac: 4413 add r3, r2 8002dae: 3b05 subs r3, #5 8002db0: fa00 f203 lsl.w r2, r0, r3 8002db4: 687b ldr r3, [r7, #4] 8002db6: 681b ldr r3, [r3, #0] 8002db8: 430a orrs r2, r1 8002dba: 635a str r2, [r3, #52] @ 0x34 8002dbc: e03c b.n 8002e38 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8002dbe: 683b ldr r3, [r7, #0] 8002dc0: 685b ldr r3, [r3, #4] 8002dc2: 2b0c cmp r3, #12 8002dc4: d81c bhi.n 8002e00 { MODIFY_REG(hadc->Instance->SQR2 , 8002dc6: 687b ldr r3, [r7, #4] 8002dc8: 681b ldr r3, [r3, #0] 8002dca: 6b19 ldr r1, [r3, #48] @ 0x30 8002dcc: 683b ldr r3, [r7, #0] 8002dce: 685a ldr r2, [r3, #4] 8002dd0: 4613 mov r3, r2 8002dd2: 009b lsls r3, r3, #2 8002dd4: 4413 add r3, r2 8002dd6: 3b23 subs r3, #35 @ 0x23 8002dd8: 221f movs r2, #31 8002dda: fa02 f303 lsl.w r3, r2, r3 8002dde: 43db mvns r3, r3 8002de0: 4019 ands r1, r3 8002de2: 683b ldr r3, [r7, #0] 8002de4: 6818 ldr r0, [r3, #0] 8002de6: 683b ldr r3, [r7, #0] 8002de8: 685a ldr r2, [r3, #4] 8002dea: 4613 mov r3, r2 8002dec: 009b lsls r3, r3, #2 8002dee: 4413 add r3, r2 8002df0: 3b23 subs r3, #35 @ 0x23 8002df2: fa00 f203 lsl.w r2, r0, r3 8002df6: 687b ldr r3, [r7, #4] 8002df8: 681b ldr r3, [r3, #0] 8002dfa: 430a orrs r2, r1 8002dfc: 631a str r2, [r3, #48] @ 0x30 8002dfe: e01b b.n 8002e38 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8002e00: 687b ldr r3, [r7, #4] 8002e02: 681b ldr r3, [r3, #0] 8002e04: 6ad9 ldr r1, [r3, #44] @ 0x2c 8002e06: 683b ldr r3, [r7, #0] 8002e08: 685a ldr r2, [r3, #4] 8002e0a: 4613 mov r3, r2 8002e0c: 009b lsls r3, r3, #2 8002e0e: 4413 add r3, r2 8002e10: 3b41 subs r3, #65 @ 0x41 8002e12: 221f movs r2, #31 8002e14: fa02 f303 lsl.w r3, r2, r3 8002e18: 43db mvns r3, r3 8002e1a: 4019 ands r1, r3 8002e1c: 683b ldr r3, [r7, #0] 8002e1e: 6818 ldr r0, [r3, #0] 8002e20: 683b ldr r3, [r7, #0] 8002e22: 685a ldr r2, [r3, #4] 8002e24: 4613 mov r3, r2 8002e26: 009b lsls r3, r3, #2 8002e28: 4413 add r3, r2 8002e2a: 3b41 subs r3, #65 @ 0x41 8002e2c: fa00 f203 lsl.w r2, r0, r3 8002e30: 687b ldr r3, [r7, #4] 8002e32: 681b ldr r3, [r3, #0] 8002e34: 430a orrs r2, r1 8002e36: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8002e38: 683b ldr r3, [r7, #0] 8002e3a: 681b ldr r3, [r3, #0] 8002e3c: 2b09 cmp r3, #9 8002e3e: d91c bls.n 8002e7a { MODIFY_REG(hadc->Instance->SMPR1 , 8002e40: 687b ldr r3, [r7, #4] 8002e42: 681b ldr r3, [r3, #0] 8002e44: 68d9 ldr r1, [r3, #12] 8002e46: 683b ldr r3, [r7, #0] 8002e48: 681a ldr r2, [r3, #0] 8002e4a: 4613 mov r3, r2 8002e4c: 005b lsls r3, r3, #1 8002e4e: 4413 add r3, r2 8002e50: 3b1e subs r3, #30 8002e52: 2207 movs r2, #7 8002e54: fa02 f303 lsl.w r3, r2, r3 8002e58: 43db mvns r3, r3 8002e5a: 4019 ands r1, r3 8002e5c: 683b ldr r3, [r7, #0] 8002e5e: 6898 ldr r0, [r3, #8] 8002e60: 683b ldr r3, [r7, #0] 8002e62: 681a ldr r2, [r3, #0] 8002e64: 4613 mov r3, r2 8002e66: 005b lsls r3, r3, #1 8002e68: 4413 add r3, r2 8002e6a: 3b1e subs r3, #30 8002e6c: fa00 f203 lsl.w r2, r0, r3 8002e70: 687b ldr r3, [r7, #4] 8002e72: 681b ldr r3, [r3, #0] 8002e74: 430a orrs r2, r1 8002e76: 60da str r2, [r3, #12] 8002e78: e019 b.n 8002eae ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8002e7a: 687b ldr r3, [r7, #4] 8002e7c: 681b ldr r3, [r3, #0] 8002e7e: 6919 ldr r1, [r3, #16] 8002e80: 683b ldr r3, [r7, #0] 8002e82: 681a ldr r2, [r3, #0] 8002e84: 4613 mov r3, r2 8002e86: 005b lsls r3, r3, #1 8002e88: 4413 add r3, r2 8002e8a: 2207 movs r2, #7 8002e8c: fa02 f303 lsl.w r3, r2, r3 8002e90: 43db mvns r3, r3 8002e92: 4019 ands r1, r3 8002e94: 683b ldr r3, [r7, #0] 8002e96: 6898 ldr r0, [r3, #8] 8002e98: 683b ldr r3, [r7, #0] 8002e9a: 681a ldr r2, [r3, #0] 8002e9c: 4613 mov r3, r2 8002e9e: 005b lsls r3, r3, #1 8002ea0: 4413 add r3, r2 8002ea2: fa00 f203 lsl.w r2, r0, r3 8002ea6: 687b ldr r3, [r7, #4] 8002ea8: 681b ldr r3, [r3, #0] 8002eaa: 430a orrs r2, r1 8002eac: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002eae: 683b ldr r3, [r7, #0] 8002eb0: 681b ldr r3, [r3, #0] 8002eb2: 2b10 cmp r3, #16 8002eb4: d003 beq.n 8002ebe (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8002eb6: 683b ldr r3, [r7, #0] 8002eb8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002eba: 2b11 cmp r3, #17 8002ebc: d132 bne.n 8002f24 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8002ebe: 687b ldr r3, [r7, #4] 8002ec0: 681b ldr r3, [r3, #0] 8002ec2: 4a1d ldr r2, [pc, #116] @ (8002f38 ) 8002ec4: 4293 cmp r3, r2 8002ec6: d125 bne.n 8002f14 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8002ec8: 687b ldr r3, [r7, #4] 8002eca: 681b ldr r3, [r3, #0] 8002ecc: 689b ldr r3, [r3, #8] 8002ece: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8002ed2: 2b00 cmp r3, #0 8002ed4: d126 bne.n 8002f24 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8002ed6: 687b ldr r3, [r7, #4] 8002ed8: 681b ldr r3, [r3, #0] 8002eda: 689a ldr r2, [r3, #8] 8002edc: 687b ldr r3, [r7, #4] 8002ede: 681b ldr r3, [r3, #0] 8002ee0: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8002ee4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8002ee6: 683b ldr r3, [r7, #0] 8002ee8: 681b ldr r3, [r3, #0] 8002eea: 2b10 cmp r3, #16 8002eec: d11a bne.n 8002f24 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8002eee: 4b13 ldr r3, [pc, #76] @ (8002f3c ) 8002ef0: 681b ldr r3, [r3, #0] 8002ef2: 4a13 ldr r2, [pc, #76] @ (8002f40 ) 8002ef4: fba2 2303 umull r2, r3, r2, r3 8002ef8: 0c9a lsrs r2, r3, #18 8002efa: 4613 mov r3, r2 8002efc: 009b lsls r3, r3, #2 8002efe: 4413 add r3, r2 8002f00: 005b lsls r3, r3, #1 8002f02: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f04: e002 b.n 8002f0c { wait_loop_index--; 8002f06: 68bb ldr r3, [r7, #8] 8002f08: 3b01 subs r3, #1 8002f0a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002f0c: 68bb ldr r3, [r7, #8] 8002f0e: 2b00 cmp r3, #0 8002f10: d1f9 bne.n 8002f06 8002f12: e007 b.n 8002f24 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002f14: 687b ldr r3, [r7, #4] 8002f16: 6a9b ldr r3, [r3, #40] @ 0x28 8002f18: f043 0220 orr.w r2, r3, #32 8002f1c: 687b ldr r3, [r7, #4] 8002f1e: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8002f20: 2301 movs r3, #1 8002f22: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002f24: 687b ldr r3, [r7, #4] 8002f26: 2200 movs r2, #0 8002f28: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8002f2c: 7bfb ldrb r3, [r7, #15] } 8002f2e: 4618 mov r0, r3 8002f30: 3714 adds r7, #20 8002f32: 46bd mov sp, r7 8002f34: bc80 pop {r7} 8002f36: 4770 bx lr 8002f38: 40012400 .word 0x40012400 8002f3c: 2000001c .word 0x2000001c 8002f40: 431bde83 .word 0x431bde83 08002f44 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8002f44: b580 push {r7, lr} 8002f46: b084 sub sp, #16 8002f48: af00 add r7, sp, #0 8002f4a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002f4c: 2300 movs r3, #0 8002f4e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002f50: 687b ldr r3, [r7, #4] 8002f52: 681b ldr r3, [r3, #0] 8002f54: 689b ldr r3, [r3, #8] 8002f56: f003 0301 and.w r3, r3, #1 8002f5a: 2b01 cmp r3, #1 8002f5c: d12e bne.n 8002fbc { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8002f5e: 687b ldr r3, [r7, #4] 8002f60: 681b ldr r3, [r3, #0] 8002f62: 689a ldr r2, [r3, #8] 8002f64: 687b ldr r3, [r7, #4] 8002f66: 681b ldr r3, [r3, #0] 8002f68: f022 0201 bic.w r2, r2, #1 8002f6c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8002f6e: f7ff fdeb bl 8002b48 8002f72: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002f74: e01b b.n 8002fae { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002f76: f7ff fde7 bl 8002b48 8002f7a: 4602 mov r2, r0 8002f7c: 68fb ldr r3, [r7, #12] 8002f7e: 1ad3 subs r3, r2, r3 8002f80: 2b02 cmp r3, #2 8002f82: d914 bls.n 8002fae { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8002f84: 687b ldr r3, [r7, #4] 8002f86: 681b ldr r3, [r3, #0] 8002f88: 689b ldr r3, [r3, #8] 8002f8a: f003 0301 and.w r3, r3, #1 8002f8e: 2b01 cmp r3, #1 8002f90: d10d bne.n 8002fae { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002f92: 687b ldr r3, [r7, #4] 8002f94: 6a9b ldr r3, [r3, #40] @ 0x28 8002f96: f043 0210 orr.w r2, r3, #16 8002f9a: 687b ldr r3, [r7, #4] 8002f9c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002f9e: 687b ldr r3, [r7, #4] 8002fa0: 6adb ldr r3, [r3, #44] @ 0x2c 8002fa2: f043 0201 orr.w r2, r3, #1 8002fa6: 687b ldr r3, [r7, #4] 8002fa8: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 8002faa: 2301 movs r3, #1 8002fac: e007 b.n 8002fbe while(ADC_IS_ENABLE(hadc) != RESET) 8002fae: 687b ldr r3, [r7, #4] 8002fb0: 681b ldr r3, [r3, #0] 8002fb2: 689b ldr r3, [r3, #8] 8002fb4: f003 0301 and.w r3, r3, #1 8002fb8: 2b01 cmp r3, #1 8002fba: d0dc beq.n 8002f76 } } } /* Return HAL status */ return HAL_OK; 8002fbc: 2300 movs r3, #0 } 8002fbe: 4618 mov r0, r3 8002fc0: 3710 adds r7, #16 8002fc2: 46bd mov sp, r7 8002fc4: bd80 pop {r7, pc} ... 08002fc8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002fc8: b480 push {r7} 8002fca: b085 sub sp, #20 8002fcc: af00 add r7, sp, #0 8002fce: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002fd0: 687b ldr r3, [r7, #4] 8002fd2: f003 0307 and.w r3, r3, #7 8002fd6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002fd8: 4b0c ldr r3, [pc, #48] @ (800300c <__NVIC_SetPriorityGrouping+0x44>) 8002fda: 68db ldr r3, [r3, #12] 8002fdc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002fde: 68ba ldr r2, [r7, #8] 8002fe0: f64f 03ff movw r3, #63743 @ 0xf8ff 8002fe4: 4013 ands r3, r2 8002fe6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002fe8: 68fb ldr r3, [r7, #12] 8002fea: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002fec: 68bb ldr r3, [r7, #8] 8002fee: 4313 orrs r3, r2 reg_value = (reg_value | 8002ff0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002ff4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8002ff8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002ffa: 4a04 ldr r2, [pc, #16] @ (800300c <__NVIC_SetPriorityGrouping+0x44>) 8002ffc: 68bb ldr r3, [r7, #8] 8002ffe: 60d3 str r3, [r2, #12] } 8003000: bf00 nop 8003002: 3714 adds r7, #20 8003004: 46bd mov sp, r7 8003006: bc80 pop {r7} 8003008: 4770 bx lr 800300a: bf00 nop 800300c: e000ed00 .word 0xe000ed00 08003010 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8003010: b480 push {r7} 8003012: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8003014: 4b04 ldr r3, [pc, #16] @ (8003028 <__NVIC_GetPriorityGrouping+0x18>) 8003016: 68db ldr r3, [r3, #12] 8003018: 0a1b lsrs r3, r3, #8 800301a: f003 0307 and.w r3, r3, #7 } 800301e: 4618 mov r0, r3 8003020: 46bd mov sp, r7 8003022: bc80 pop {r7} 8003024: 4770 bx lr 8003026: bf00 nop 8003028: e000ed00 .word 0xe000ed00 0800302c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800302c: b480 push {r7} 800302e: b083 sub sp, #12 8003030: af00 add r7, sp, #0 8003032: 4603 mov r3, r0 8003034: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003036: f997 3007 ldrsb.w r3, [r7, #7] 800303a: 2b00 cmp r3, #0 800303c: db0b blt.n 8003056 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800303e: 79fb ldrb r3, [r7, #7] 8003040: f003 021f and.w r2, r3, #31 8003044: 4906 ldr r1, [pc, #24] @ (8003060 <__NVIC_EnableIRQ+0x34>) 8003046: f997 3007 ldrsb.w r3, [r7, #7] 800304a: 095b lsrs r3, r3, #5 800304c: 2001 movs r0, #1 800304e: fa00 f202 lsl.w r2, r0, r2 8003052: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8003056: bf00 nop 8003058: 370c adds r7, #12 800305a: 46bd mov sp, r7 800305c: bc80 pop {r7} 800305e: 4770 bx lr 8003060: e000e100 .word 0xe000e100 08003064 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8003064: b480 push {r7} 8003066: b083 sub sp, #12 8003068: af00 add r7, sp, #0 800306a: 4603 mov r3, r0 800306c: 6039 str r1, [r7, #0] 800306e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003070: f997 3007 ldrsb.w r3, [r7, #7] 8003074: 2b00 cmp r3, #0 8003076: db0a blt.n 800308e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003078: 683b ldr r3, [r7, #0] 800307a: b2da uxtb r2, r3 800307c: 490c ldr r1, [pc, #48] @ (80030b0 <__NVIC_SetPriority+0x4c>) 800307e: f997 3007 ldrsb.w r3, [r7, #7] 8003082: 0112 lsls r2, r2, #4 8003084: b2d2 uxtb r2, r2 8003086: 440b add r3, r1 8003088: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800308c: e00a b.n 80030a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800308e: 683b ldr r3, [r7, #0] 8003090: b2da uxtb r2, r3 8003092: 4908 ldr r1, [pc, #32] @ (80030b4 <__NVIC_SetPriority+0x50>) 8003094: 79fb ldrb r3, [r7, #7] 8003096: f003 030f and.w r3, r3, #15 800309a: 3b04 subs r3, #4 800309c: 0112 lsls r2, r2, #4 800309e: b2d2 uxtb r2, r2 80030a0: 440b add r3, r1 80030a2: 761a strb r2, [r3, #24] } 80030a4: bf00 nop 80030a6: 370c adds r7, #12 80030a8: 46bd mov sp, r7 80030aa: bc80 pop {r7} 80030ac: 4770 bx lr 80030ae: bf00 nop 80030b0: e000e100 .word 0xe000e100 80030b4: e000ed00 .word 0xe000ed00 080030b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80030b8: b480 push {r7} 80030ba: b089 sub sp, #36 @ 0x24 80030bc: af00 add r7, sp, #0 80030be: 60f8 str r0, [r7, #12] 80030c0: 60b9 str r1, [r7, #8] 80030c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80030c4: 68fb ldr r3, [r7, #12] 80030c6: f003 0307 and.w r3, r3, #7 80030ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80030cc: 69fb ldr r3, [r7, #28] 80030ce: f1c3 0307 rsb r3, r3, #7 80030d2: 2b04 cmp r3, #4 80030d4: bf28 it cs 80030d6: 2304 movcs r3, #4 80030d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80030da: 69fb ldr r3, [r7, #28] 80030dc: 3304 adds r3, #4 80030de: 2b06 cmp r3, #6 80030e0: d902 bls.n 80030e8 80030e2: 69fb ldr r3, [r7, #28] 80030e4: 3b03 subs r3, #3 80030e6: e000 b.n 80030ea 80030e8: 2300 movs r3, #0 80030ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80030ec: f04f 32ff mov.w r2, #4294967295 80030f0: 69bb ldr r3, [r7, #24] 80030f2: fa02 f303 lsl.w r3, r2, r3 80030f6: 43da mvns r2, r3 80030f8: 68bb ldr r3, [r7, #8] 80030fa: 401a ands r2, r3 80030fc: 697b ldr r3, [r7, #20] 80030fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8003100: f04f 31ff mov.w r1, #4294967295 8003104: 697b ldr r3, [r7, #20] 8003106: fa01 f303 lsl.w r3, r1, r3 800310a: 43d9 mvns r1, r3 800310c: 687b ldr r3, [r7, #4] 800310e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003110: 4313 orrs r3, r2 ); } 8003112: 4618 mov r0, r3 8003114: 3724 adds r7, #36 @ 0x24 8003116: 46bd mov sp, r7 8003118: bc80 pop {r7} 800311a: 4770 bx lr 0800311c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800311c: b580 push {r7, lr} 800311e: b082 sub sp, #8 8003120: af00 add r7, sp, #0 8003122: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8003124: 687b ldr r3, [r7, #4] 8003126: 3b01 subs r3, #1 8003128: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800312c: d301 bcc.n 8003132 { return (1UL); /* Reload value impossible */ 800312e: 2301 movs r3, #1 8003130: e00f b.n 8003152 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8003132: 4a0a ldr r2, [pc, #40] @ (800315c ) 8003134: 687b ldr r3, [r7, #4] 8003136: 3b01 subs r3, #1 8003138: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800313a: 210f movs r1, #15 800313c: f04f 30ff mov.w r0, #4294967295 8003140: f7ff ff90 bl 8003064 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8003144: 4b05 ldr r3, [pc, #20] @ (800315c ) 8003146: 2200 movs r2, #0 8003148: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800314a: 4b04 ldr r3, [pc, #16] @ (800315c ) 800314c: 2207 movs r2, #7 800314e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003150: 2300 movs r3, #0 } 8003152: 4618 mov r0, r3 8003154: 3708 adds r7, #8 8003156: 46bd mov sp, r7 8003158: bd80 pop {r7, pc} 800315a: bf00 nop 800315c: e000e010 .word 0xe000e010 08003160 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003160: b580 push {r7, lr} 8003162: b082 sub sp, #8 8003164: af00 add r7, sp, #0 8003166: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8003168: 6878 ldr r0, [r7, #4] 800316a: f7ff ff2d bl 8002fc8 <__NVIC_SetPriorityGrouping> } 800316e: bf00 nop 8003170: 3708 adds r7, #8 8003172: 46bd mov sp, r7 8003174: bd80 pop {r7, pc} 08003176 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8003176: b580 push {r7, lr} 8003178: b086 sub sp, #24 800317a: af00 add r7, sp, #0 800317c: 4603 mov r3, r0 800317e: 60b9 str r1, [r7, #8] 8003180: 607a str r2, [r7, #4] 8003182: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8003184: 2300 movs r3, #0 8003186: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8003188: f7ff ff42 bl 8003010 <__NVIC_GetPriorityGrouping> 800318c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800318e: 687a ldr r2, [r7, #4] 8003190: 68b9 ldr r1, [r7, #8] 8003192: 6978 ldr r0, [r7, #20] 8003194: f7ff ff90 bl 80030b8 8003198: 4602 mov r2, r0 800319a: f997 300f ldrsb.w r3, [r7, #15] 800319e: 4611 mov r1, r2 80031a0: 4618 mov r0, r3 80031a2: f7ff ff5f bl 8003064 <__NVIC_SetPriority> } 80031a6: bf00 nop 80031a8: 3718 adds r7, #24 80031aa: 46bd mov sp, r7 80031ac: bd80 pop {r7, pc} 080031ae : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80031ae: b580 push {r7, lr} 80031b0: b082 sub sp, #8 80031b2: af00 add r7, sp, #0 80031b4: 4603 mov r3, r0 80031b6: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80031b8: f997 3007 ldrsb.w r3, [r7, #7] 80031bc: 4618 mov r0, r3 80031be: f7ff ff35 bl 800302c <__NVIC_EnableIRQ> } 80031c2: bf00 nop 80031c4: 3708 adds r7, #8 80031c6: 46bd mov sp, r7 80031c8: bd80 pop {r7, pc} 080031ca : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80031ca: b580 push {r7, lr} 80031cc: b082 sub sp, #8 80031ce: af00 add r7, sp, #0 80031d0: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80031d2: 6878 ldr r0, [r7, #4] 80031d4: f7ff ffa2 bl 800311c 80031d8: 4603 mov r3, r0 } 80031da: 4618 mov r0, r3 80031dc: 3708 adds r7, #8 80031de: 46bd mov sp, r7 80031e0: bd80 pop {r7, pc} 080031e2 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80031e2: b480 push {r7} 80031e4: b085 sub sp, #20 80031e6: af00 add r7, sp, #0 80031e8: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80031ea: 2300 movs r3, #0 80031ec: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 80031ee: 687b ldr r3, [r7, #4] 80031f0: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80031f4: b2db uxtb r3, r3 80031f6: 2b02 cmp r3, #2 80031f8: d008 beq.n 800320c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80031fa: 687b ldr r3, [r7, #4] 80031fc: 2204 movs r2, #4 80031fe: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003200: 687b ldr r3, [r7, #4] 8003202: 2200 movs r2, #0 8003204: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8003208: 2301 movs r3, #1 800320a: e020 b.n 800324e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800320c: 687b ldr r3, [r7, #4] 800320e: 681b ldr r3, [r3, #0] 8003210: 681a ldr r2, [r3, #0] 8003212: 687b ldr r3, [r7, #4] 8003214: 681b ldr r3, [r3, #0] 8003216: f022 020e bic.w r2, r2, #14 800321a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800321c: 687b ldr r3, [r7, #4] 800321e: 681b ldr r3, [r3, #0] 8003220: 681a ldr r2, [r3, #0] 8003222: 687b ldr r3, [r7, #4] 8003224: 681b ldr r3, [r3, #0] 8003226: f022 0201 bic.w r2, r2, #1 800322a: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800322c: 687b ldr r3, [r7, #4] 800322e: 6c1a ldr r2, [r3, #64] @ 0x40 8003230: 687b ldr r3, [r7, #4] 8003232: 6bdb ldr r3, [r3, #60] @ 0x3c 8003234: 2101 movs r1, #1 8003236: fa01 f202 lsl.w r2, r1, r2 800323a: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800323c: 687b ldr r3, [r7, #4] 800323e: 2201 movs r2, #1 8003240: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003244: 687b ldr r3, [r7, #4] 8003246: 2200 movs r2, #0 8003248: f883 2020 strb.w r2, [r3, #32] return status; 800324c: 7bfb ldrb r3, [r7, #15] } 800324e: 4618 mov r0, r3 8003250: 3714 adds r7, #20 8003252: 46bd mov sp, r7 8003254: bc80 pop {r7} 8003256: 4770 bx lr 08003258 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003258: b580 push {r7, lr} 800325a: b084 sub sp, #16 800325c: af00 add r7, sp, #0 800325e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003260: 2300 movs r3, #0 8003262: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8003264: 687b ldr r3, [r7, #4] 8003266: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800326a: b2db uxtb r3, r3 800326c: 2b02 cmp r3, #2 800326e: d005 beq.n 800327c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003270: 687b ldr r3, [r7, #4] 8003272: 2204 movs r2, #4 8003274: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8003276: 2301 movs r3, #1 8003278: 73fb strb r3, [r7, #15] 800327a: e051 b.n 8003320 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800327c: 687b ldr r3, [r7, #4] 800327e: 681b ldr r3, [r3, #0] 8003280: 681a ldr r2, [r3, #0] 8003282: 687b ldr r3, [r7, #4] 8003284: 681b ldr r3, [r3, #0] 8003286: f022 020e bic.w r2, r2, #14 800328a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800328c: 687b ldr r3, [r7, #4] 800328e: 681b ldr r3, [r3, #0] 8003290: 681a ldr r2, [r3, #0] 8003292: 687b ldr r3, [r7, #4] 8003294: 681b ldr r3, [r3, #0] 8003296: f022 0201 bic.w r2, r2, #1 800329a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800329c: 687b ldr r3, [r7, #4] 800329e: 681b ldr r3, [r3, #0] 80032a0: 4a22 ldr r2, [pc, #136] @ (800332c ) 80032a2: 4293 cmp r3, r2 80032a4: d029 beq.n 80032fa 80032a6: 687b ldr r3, [r7, #4] 80032a8: 681b ldr r3, [r3, #0] 80032aa: 4a21 ldr r2, [pc, #132] @ (8003330 ) 80032ac: 4293 cmp r3, r2 80032ae: d022 beq.n 80032f6 80032b0: 687b ldr r3, [r7, #4] 80032b2: 681b ldr r3, [r3, #0] 80032b4: 4a1f ldr r2, [pc, #124] @ (8003334 ) 80032b6: 4293 cmp r3, r2 80032b8: d01a beq.n 80032f0 80032ba: 687b ldr r3, [r7, #4] 80032bc: 681b ldr r3, [r3, #0] 80032be: 4a1e ldr r2, [pc, #120] @ (8003338 ) 80032c0: 4293 cmp r3, r2 80032c2: d012 beq.n 80032ea 80032c4: 687b ldr r3, [r7, #4] 80032c6: 681b ldr r3, [r3, #0] 80032c8: 4a1c ldr r2, [pc, #112] @ (800333c ) 80032ca: 4293 cmp r3, r2 80032cc: d00a beq.n 80032e4 80032ce: 687b ldr r3, [r7, #4] 80032d0: 681b ldr r3, [r3, #0] 80032d2: 4a1b ldr r2, [pc, #108] @ (8003340 ) 80032d4: 4293 cmp r3, r2 80032d6: d102 bne.n 80032de 80032d8: f44f 1380 mov.w r3, #1048576 @ 0x100000 80032dc: e00e b.n 80032fc 80032de: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80032e2: e00b b.n 80032fc 80032e4: f44f 3380 mov.w r3, #65536 @ 0x10000 80032e8: e008 b.n 80032fc 80032ea: f44f 5380 mov.w r3, #4096 @ 0x1000 80032ee: e005 b.n 80032fc 80032f0: f44f 7380 mov.w r3, #256 @ 0x100 80032f4: e002 b.n 80032fc 80032f6: 2310 movs r3, #16 80032f8: e000 b.n 80032fc 80032fa: 2301 movs r3, #1 80032fc: 4a11 ldr r2, [pc, #68] @ (8003344 ) 80032fe: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003300: 687b ldr r3, [r7, #4] 8003302: 2201 movs r2, #1 8003304: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003308: 687b ldr r3, [r7, #4] 800330a: 2200 movs r2, #0 800330c: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8003310: 687b ldr r3, [r7, #4] 8003312: 6b5b ldr r3, [r3, #52] @ 0x34 8003314: 2b00 cmp r3, #0 8003316: d003 beq.n 8003320 { hdma->XferAbortCallback(hdma); 8003318: 687b ldr r3, [r7, #4] 800331a: 6b5b ldr r3, [r3, #52] @ 0x34 800331c: 6878 ldr r0, [r7, #4] 800331e: 4798 blx r3 } } return status; 8003320: 7bfb ldrb r3, [r7, #15] } 8003322: 4618 mov r0, r3 8003324: 3710 adds r7, #16 8003326: 46bd mov sp, r7 8003328: bd80 pop {r7, pc} 800332a: bf00 nop 800332c: 40020008 .word 0x40020008 8003330: 4002001c .word 0x4002001c 8003334: 40020030 .word 0x40020030 8003338: 40020044 .word 0x40020044 800333c: 40020058 .word 0x40020058 8003340: 4002006c .word 0x4002006c 8003344: 40020000 .word 0x40020000 08003348 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8003348: b480 push {r7} 800334a: b08b sub sp, #44 @ 0x2c 800334c: af00 add r7, sp, #0 800334e: 6078 str r0, [r7, #4] 8003350: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003352: 2300 movs r3, #0 8003354: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8003356: 2300 movs r3, #0 8003358: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800335a: e169 b.n 8003630 { /* Get the IO position */ ioposition = (0x01uL << position); 800335c: 2201 movs r2, #1 800335e: 6a7b ldr r3, [r7, #36] @ 0x24 8003360: fa02 f303 lsl.w r3, r2, r3 8003364: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8003366: 683b ldr r3, [r7, #0] 8003368: 681b ldr r3, [r3, #0] 800336a: 69fa ldr r2, [r7, #28] 800336c: 4013 ands r3, r2 800336e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8003370: 69ba ldr r2, [r7, #24] 8003372: 69fb ldr r3, [r7, #28] 8003374: 429a cmp r2, r3 8003376: f040 8158 bne.w 800362a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800337a: 683b ldr r3, [r7, #0] 800337c: 685b ldr r3, [r3, #4] 800337e: 4a9a ldr r2, [pc, #616] @ (80035e8 ) 8003380: 4293 cmp r3, r2 8003382: d05e beq.n 8003442 8003384: 4a98 ldr r2, [pc, #608] @ (80035e8 ) 8003386: 4293 cmp r3, r2 8003388: d875 bhi.n 8003476 800338a: 4a98 ldr r2, [pc, #608] @ (80035ec ) 800338c: 4293 cmp r3, r2 800338e: d058 beq.n 8003442 8003390: 4a96 ldr r2, [pc, #600] @ (80035ec ) 8003392: 4293 cmp r3, r2 8003394: d86f bhi.n 8003476 8003396: 4a96 ldr r2, [pc, #600] @ (80035f0 ) 8003398: 4293 cmp r3, r2 800339a: d052 beq.n 8003442 800339c: 4a94 ldr r2, [pc, #592] @ (80035f0 ) 800339e: 4293 cmp r3, r2 80033a0: d869 bhi.n 8003476 80033a2: 4a94 ldr r2, [pc, #592] @ (80035f4 ) 80033a4: 4293 cmp r3, r2 80033a6: d04c beq.n 8003442 80033a8: 4a92 ldr r2, [pc, #584] @ (80035f4 ) 80033aa: 4293 cmp r3, r2 80033ac: d863 bhi.n 8003476 80033ae: 4a92 ldr r2, [pc, #584] @ (80035f8 ) 80033b0: 4293 cmp r3, r2 80033b2: d046 beq.n 8003442 80033b4: 4a90 ldr r2, [pc, #576] @ (80035f8 ) 80033b6: 4293 cmp r3, r2 80033b8: d85d bhi.n 8003476 80033ba: 2b12 cmp r3, #18 80033bc: d82a bhi.n 8003414 80033be: 2b12 cmp r3, #18 80033c0: d859 bhi.n 8003476 80033c2: a201 add r2, pc, #4 @ (adr r2, 80033c8 ) 80033c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80033c8: 08003443 .word 0x08003443 80033cc: 0800341d .word 0x0800341d 80033d0: 0800342f .word 0x0800342f 80033d4: 08003471 .word 0x08003471 80033d8: 08003477 .word 0x08003477 80033dc: 08003477 .word 0x08003477 80033e0: 08003477 .word 0x08003477 80033e4: 08003477 .word 0x08003477 80033e8: 08003477 .word 0x08003477 80033ec: 08003477 .word 0x08003477 80033f0: 08003477 .word 0x08003477 80033f4: 08003477 .word 0x08003477 80033f8: 08003477 .word 0x08003477 80033fc: 08003477 .word 0x08003477 8003400: 08003477 .word 0x08003477 8003404: 08003477 .word 0x08003477 8003408: 08003477 .word 0x08003477 800340c: 08003425 .word 0x08003425 8003410: 08003439 .word 0x08003439 8003414: 4a79 ldr r2, [pc, #484] @ (80035fc ) 8003416: 4293 cmp r3, r2 8003418: d013 beq.n 8003442 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800341a: e02c b.n 8003476 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800341c: 683b ldr r3, [r7, #0] 800341e: 68db ldr r3, [r3, #12] 8003420: 623b str r3, [r7, #32] break; 8003422: e029 b.n 8003478 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8003424: 683b ldr r3, [r7, #0] 8003426: 68db ldr r3, [r3, #12] 8003428: 3304 adds r3, #4 800342a: 623b str r3, [r7, #32] break; 800342c: e024 b.n 8003478 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800342e: 683b ldr r3, [r7, #0] 8003430: 68db ldr r3, [r3, #12] 8003432: 3308 adds r3, #8 8003434: 623b str r3, [r7, #32] break; 8003436: e01f b.n 8003478 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8003438: 683b ldr r3, [r7, #0] 800343a: 68db ldr r3, [r3, #12] 800343c: 330c adds r3, #12 800343e: 623b str r3, [r7, #32] break; 8003440: e01a b.n 8003478 if (GPIO_Init->Pull == GPIO_NOPULL) 8003442: 683b ldr r3, [r7, #0] 8003444: 689b ldr r3, [r3, #8] 8003446: 2b00 cmp r3, #0 8003448: d102 bne.n 8003450 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800344a: 2304 movs r3, #4 800344c: 623b str r3, [r7, #32] break; 800344e: e013 b.n 8003478 else if (GPIO_Init->Pull == GPIO_PULLUP) 8003450: 683b ldr r3, [r7, #0] 8003452: 689b ldr r3, [r3, #8] 8003454: 2b01 cmp r3, #1 8003456: d105 bne.n 8003464 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8003458: 2308 movs r3, #8 800345a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 800345c: 687b ldr r3, [r7, #4] 800345e: 69fa ldr r2, [r7, #28] 8003460: 611a str r2, [r3, #16] break; 8003462: e009 b.n 8003478 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8003464: 2308 movs r3, #8 8003466: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8003468: 687b ldr r3, [r7, #4] 800346a: 69fa ldr r2, [r7, #28] 800346c: 615a str r2, [r3, #20] break; 800346e: e003 b.n 8003478 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8003470: 2300 movs r3, #0 8003472: 623b str r3, [r7, #32] break; 8003474: e000 b.n 8003478 break; 8003476: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8003478: 69bb ldr r3, [r7, #24] 800347a: 2bff cmp r3, #255 @ 0xff 800347c: d801 bhi.n 8003482 800347e: 687b ldr r3, [r7, #4] 8003480: e001 b.n 8003486 8003482: 687b ldr r3, [r7, #4] 8003484: 3304 adds r3, #4 8003486: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8003488: 69bb ldr r3, [r7, #24] 800348a: 2bff cmp r3, #255 @ 0xff 800348c: d802 bhi.n 8003494 800348e: 6a7b ldr r3, [r7, #36] @ 0x24 8003490: 009b lsls r3, r3, #2 8003492: e002 b.n 800349a 8003494: 6a7b ldr r3, [r7, #36] @ 0x24 8003496: 3b08 subs r3, #8 8003498: 009b lsls r3, r3, #2 800349a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800349c: 697b ldr r3, [r7, #20] 800349e: 681a ldr r2, [r3, #0] 80034a0: 210f movs r1, #15 80034a2: 693b ldr r3, [r7, #16] 80034a4: fa01 f303 lsl.w r3, r1, r3 80034a8: 43db mvns r3, r3 80034aa: 401a ands r2, r3 80034ac: 6a39 ldr r1, [r7, #32] 80034ae: 693b ldr r3, [r7, #16] 80034b0: fa01 f303 lsl.w r3, r1, r3 80034b4: 431a orrs r2, r3 80034b6: 697b ldr r3, [r7, #20] 80034b8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80034ba: 683b ldr r3, [r7, #0] 80034bc: 685b ldr r3, [r3, #4] 80034be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80034c2: 2b00 cmp r3, #0 80034c4: f000 80b1 beq.w 800362a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80034c8: 4b4d ldr r3, [pc, #308] @ (8003600 ) 80034ca: 699b ldr r3, [r3, #24] 80034cc: 4a4c ldr r2, [pc, #304] @ (8003600 ) 80034ce: f043 0301 orr.w r3, r3, #1 80034d2: 6193 str r3, [r2, #24] 80034d4: 4b4a ldr r3, [pc, #296] @ (8003600 ) 80034d6: 699b ldr r3, [r3, #24] 80034d8: f003 0301 and.w r3, r3, #1 80034dc: 60bb str r3, [r7, #8] 80034de: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80034e0: 4a48 ldr r2, [pc, #288] @ (8003604 ) 80034e2: 6a7b ldr r3, [r7, #36] @ 0x24 80034e4: 089b lsrs r3, r3, #2 80034e6: 3302 adds r3, #2 80034e8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80034ec: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80034ee: 6a7b ldr r3, [r7, #36] @ 0x24 80034f0: f003 0303 and.w r3, r3, #3 80034f4: 009b lsls r3, r3, #2 80034f6: 220f movs r2, #15 80034f8: fa02 f303 lsl.w r3, r2, r3 80034fc: 43db mvns r3, r3 80034fe: 68fa ldr r2, [r7, #12] 8003500: 4013 ands r3, r2 8003502: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8003504: 687b ldr r3, [r7, #4] 8003506: 4a40 ldr r2, [pc, #256] @ (8003608 ) 8003508: 4293 cmp r3, r2 800350a: d013 beq.n 8003534 800350c: 687b ldr r3, [r7, #4] 800350e: 4a3f ldr r2, [pc, #252] @ (800360c ) 8003510: 4293 cmp r3, r2 8003512: d00d beq.n 8003530 8003514: 687b ldr r3, [r7, #4] 8003516: 4a3e ldr r2, [pc, #248] @ (8003610 ) 8003518: 4293 cmp r3, r2 800351a: d007 beq.n 800352c 800351c: 687b ldr r3, [r7, #4] 800351e: 4a3d ldr r2, [pc, #244] @ (8003614 ) 8003520: 4293 cmp r3, r2 8003522: d101 bne.n 8003528 8003524: 2303 movs r3, #3 8003526: e006 b.n 8003536 8003528: 2304 movs r3, #4 800352a: e004 b.n 8003536 800352c: 2302 movs r3, #2 800352e: e002 b.n 8003536 8003530: 2301 movs r3, #1 8003532: e000 b.n 8003536 8003534: 2300 movs r3, #0 8003536: 6a7a ldr r2, [r7, #36] @ 0x24 8003538: f002 0203 and.w r2, r2, #3 800353c: 0092 lsls r2, r2, #2 800353e: 4093 lsls r3, r2 8003540: 68fa ldr r2, [r7, #12] 8003542: 4313 orrs r3, r2 8003544: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8003546: 492f ldr r1, [pc, #188] @ (8003604 ) 8003548: 6a7b ldr r3, [r7, #36] @ 0x24 800354a: 089b lsrs r3, r3, #2 800354c: 3302 adds r3, #2 800354e: 68fa ldr r2, [r7, #12] 8003550: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8003554: 683b ldr r3, [r7, #0] 8003556: 685b ldr r3, [r3, #4] 8003558: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800355c: 2b00 cmp r3, #0 800355e: d006 beq.n 800356e { SET_BIT(EXTI->RTSR, iocurrent); 8003560: 4b2d ldr r3, [pc, #180] @ (8003618 ) 8003562: 689a ldr r2, [r3, #8] 8003564: 492c ldr r1, [pc, #176] @ (8003618 ) 8003566: 69bb ldr r3, [r7, #24] 8003568: 4313 orrs r3, r2 800356a: 608b str r3, [r1, #8] 800356c: e006 b.n 800357c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800356e: 4b2a ldr r3, [pc, #168] @ (8003618 ) 8003570: 689a ldr r2, [r3, #8] 8003572: 69bb ldr r3, [r7, #24] 8003574: 43db mvns r3, r3 8003576: 4928 ldr r1, [pc, #160] @ (8003618 ) 8003578: 4013 ands r3, r2 800357a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800357c: 683b ldr r3, [r7, #0] 800357e: 685b ldr r3, [r3, #4] 8003580: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003584: 2b00 cmp r3, #0 8003586: d006 beq.n 8003596 { SET_BIT(EXTI->FTSR, iocurrent); 8003588: 4b23 ldr r3, [pc, #140] @ (8003618 ) 800358a: 68da ldr r2, [r3, #12] 800358c: 4922 ldr r1, [pc, #136] @ (8003618 ) 800358e: 69bb ldr r3, [r7, #24] 8003590: 4313 orrs r3, r2 8003592: 60cb str r3, [r1, #12] 8003594: e006 b.n 80035a4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8003596: 4b20 ldr r3, [pc, #128] @ (8003618 ) 8003598: 68da ldr r2, [r3, #12] 800359a: 69bb ldr r3, [r7, #24] 800359c: 43db mvns r3, r3 800359e: 491e ldr r1, [pc, #120] @ (8003618 ) 80035a0: 4013 ands r3, r2 80035a2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80035a4: 683b ldr r3, [r7, #0] 80035a6: 685b ldr r3, [r3, #4] 80035a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80035ac: 2b00 cmp r3, #0 80035ae: d006 beq.n 80035be { SET_BIT(EXTI->EMR, iocurrent); 80035b0: 4b19 ldr r3, [pc, #100] @ (8003618 ) 80035b2: 685a ldr r2, [r3, #4] 80035b4: 4918 ldr r1, [pc, #96] @ (8003618 ) 80035b6: 69bb ldr r3, [r7, #24] 80035b8: 4313 orrs r3, r2 80035ba: 604b str r3, [r1, #4] 80035bc: e006 b.n 80035cc } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80035be: 4b16 ldr r3, [pc, #88] @ (8003618 ) 80035c0: 685a ldr r2, [r3, #4] 80035c2: 69bb ldr r3, [r7, #24] 80035c4: 43db mvns r3, r3 80035c6: 4914 ldr r1, [pc, #80] @ (8003618 ) 80035c8: 4013 ands r3, r2 80035ca: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80035cc: 683b ldr r3, [r7, #0] 80035ce: 685b ldr r3, [r3, #4] 80035d0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80035d4: 2b00 cmp r3, #0 80035d6: d021 beq.n 800361c { SET_BIT(EXTI->IMR, iocurrent); 80035d8: 4b0f ldr r3, [pc, #60] @ (8003618 ) 80035da: 681a ldr r2, [r3, #0] 80035dc: 490e ldr r1, [pc, #56] @ (8003618 ) 80035de: 69bb ldr r3, [r7, #24] 80035e0: 4313 orrs r3, r2 80035e2: 600b str r3, [r1, #0] 80035e4: e021 b.n 800362a 80035e6: bf00 nop 80035e8: 10320000 .word 0x10320000 80035ec: 10310000 .word 0x10310000 80035f0: 10220000 .word 0x10220000 80035f4: 10210000 .word 0x10210000 80035f8: 10120000 .word 0x10120000 80035fc: 10110000 .word 0x10110000 8003600: 40021000 .word 0x40021000 8003604: 40010000 .word 0x40010000 8003608: 40010800 .word 0x40010800 800360c: 40010c00 .word 0x40010c00 8003610: 40011000 .word 0x40011000 8003614: 40011400 .word 0x40011400 8003618: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800361c: 4b0b ldr r3, [pc, #44] @ (800364c ) 800361e: 681a ldr r2, [r3, #0] 8003620: 69bb ldr r3, [r7, #24] 8003622: 43db mvns r3, r3 8003624: 4909 ldr r1, [pc, #36] @ (800364c ) 8003626: 4013 ands r3, r2 8003628: 600b str r3, [r1, #0] } } } position++; 800362a: 6a7b ldr r3, [r7, #36] @ 0x24 800362c: 3301 adds r3, #1 800362e: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8003630: 683b ldr r3, [r7, #0] 8003632: 681a ldr r2, [r3, #0] 8003634: 6a7b ldr r3, [r7, #36] @ 0x24 8003636: fa22 f303 lsr.w r3, r2, r3 800363a: 2b00 cmp r3, #0 800363c: f47f ae8e bne.w 800335c } } 8003640: bf00 nop 8003642: bf00 nop 8003644: 372c adds r7, #44 @ 0x2c 8003646: 46bd mov sp, r7 8003648: bc80 pop {r7} 800364a: 4770 bx lr 800364c: 40010400 .word 0x40010400 08003650 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8003650: b480 push {r7} 8003652: b085 sub sp, #20 8003654: af00 add r7, sp, #0 8003656: 6078 str r0, [r7, #4] 8003658: 460b mov r3, r1 800365a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800365c: 687b ldr r3, [r7, #4] 800365e: 689a ldr r2, [r3, #8] 8003660: 887b ldrh r3, [r7, #2] 8003662: 4013 ands r3, r2 8003664: 2b00 cmp r3, #0 8003666: d002 beq.n 800366e { bitstatus = GPIO_PIN_SET; 8003668: 2301 movs r3, #1 800366a: 73fb strb r3, [r7, #15] 800366c: e001 b.n 8003672 } else { bitstatus = GPIO_PIN_RESET; 800366e: 2300 movs r3, #0 8003670: 73fb strb r3, [r7, #15] } return bitstatus; 8003672: 7bfb ldrb r3, [r7, #15] } 8003674: 4618 mov r0, r3 8003676: 3714 adds r7, #20 8003678: 46bd mov sp, r7 800367a: bc80 pop {r7} 800367c: 4770 bx lr 0800367e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800367e: b480 push {r7} 8003680: b083 sub sp, #12 8003682: af00 add r7, sp, #0 8003684: 6078 str r0, [r7, #4] 8003686: 460b mov r3, r1 8003688: 807b strh r3, [r7, #2] 800368a: 4613 mov r3, r2 800368c: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800368e: 787b ldrb r3, [r7, #1] 8003690: 2b00 cmp r3, #0 8003692: d003 beq.n 800369c { GPIOx->BSRR = GPIO_Pin; 8003694: 887a ldrh r2, [r7, #2] 8003696: 687b ldr r3, [r7, #4] 8003698: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800369a: e003 b.n 80036a4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800369c: 887b ldrh r3, [r7, #2] 800369e: 041a lsls r2, r3, #16 80036a0: 687b ldr r3, [r7, #4] 80036a2: 611a str r2, [r3, #16] } 80036a4: bf00 nop 80036a6: 370c adds r7, #12 80036a8: 46bd mov sp, r7 80036aa: bc80 pop {r7} 80036ac: 4770 bx lr ... 080036b0 : * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 80036b0: b580 push {r7, lr} 80036b2: b082 sub sp, #8 80036b4: af00 add r7, sp, #0 80036b6: 4603 mov r3, r0 80036b8: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 80036ba: 4b08 ldr r3, [pc, #32] @ (80036dc ) 80036bc: 695a ldr r2, [r3, #20] 80036be: 88fb ldrh r3, [r7, #6] 80036c0: 4013 ands r3, r2 80036c2: 2b00 cmp r3, #0 80036c4: d006 beq.n 80036d4 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80036c6: 4a05 ldr r2, [pc, #20] @ (80036dc ) 80036c8: 88fb ldrh r3, [r7, #6] 80036ca: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 80036cc: 88fb ldrh r3, [r7, #6] 80036ce: 4618 mov r0, r3 80036d0: f7fe fc60 bl 8001f94 } } 80036d4: bf00 nop 80036d6: 3708 adds r7, #8 80036d8: 46bd mov sp, r7 80036da: bd80 pop {r7, pc} 80036dc: 40010400 .word 0x40010400 080036e0 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 80036e0: b580 push {r7, lr} 80036e2: b084 sub sp, #16 80036e4: af00 add r7, sp, #0 80036e6: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 80036e8: 687b ldr r3, [r7, #4] 80036ea: 2b00 cmp r3, #0 80036ec: d101 bne.n 80036f2 { return HAL_ERROR; 80036ee: 2301 movs r3, #1 80036f0: e12b b.n 800394a assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 80036f2: 687b ldr r3, [r7, #4] 80036f4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80036f8: b2db uxtb r3, r3 80036fa: 2b00 cmp r3, #0 80036fc: d106 bne.n 800370c { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80036fe: 687b ldr r3, [r7, #4] 8003700: 2200 movs r2, #0 8003702: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8003706: 6878 ldr r0, [r7, #4] 8003708: f7fe fcf4 bl 80020f4 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 800370c: 687b ldr r3, [r7, #4] 800370e: 2224 movs r2, #36 @ 0x24 8003710: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003714: 687b ldr r3, [r7, #4] 8003716: 681b ldr r3, [r3, #0] 8003718: 681a ldr r2, [r3, #0] 800371a: 687b ldr r3, [r7, #4] 800371c: 681b ldr r3, [r3, #0] 800371e: f022 0201 bic.w r2, r2, #1 8003722: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8003724: 687b ldr r3, [r7, #4] 8003726: 681b ldr r3, [r3, #0] 8003728: 681a ldr r2, [r3, #0] 800372a: 687b ldr r3, [r7, #4] 800372c: 681b ldr r3, [r3, #0] 800372e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8003732: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8003734: 687b ldr r3, [r7, #4] 8003736: 681b ldr r3, [r3, #0] 8003738: 681a ldr r2, [r3, #0] 800373a: 687b ldr r3, [r7, #4] 800373c: 681b ldr r3, [r3, #0] 800373e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8003742: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8003744: f001 fbcc bl 8004ee0 8003748: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 800374a: 687b ldr r3, [r7, #4] 800374c: 685b ldr r3, [r3, #4] 800374e: 4a81 ldr r2, [pc, #516] @ (8003954 ) 8003750: 4293 cmp r3, r2 8003752: d807 bhi.n 8003764 8003754: 68fb ldr r3, [r7, #12] 8003756: 4a80 ldr r2, [pc, #512] @ (8003958 ) 8003758: 4293 cmp r3, r2 800375a: bf94 ite ls 800375c: 2301 movls r3, #1 800375e: 2300 movhi r3, #0 8003760: b2db uxtb r3, r3 8003762: e006 b.n 8003772 8003764: 68fb ldr r3, [r7, #12] 8003766: 4a7d ldr r2, [pc, #500] @ (800395c ) 8003768: 4293 cmp r3, r2 800376a: bf94 ite ls 800376c: 2301 movls r3, #1 800376e: 2300 movhi r3, #0 8003770: b2db uxtb r3, r3 8003772: 2b00 cmp r3, #0 8003774: d001 beq.n 800377a { return HAL_ERROR; 8003776: 2301 movs r3, #1 8003778: e0e7 b.n 800394a } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 800377a: 68fb ldr r3, [r7, #12] 800377c: 4a78 ldr r2, [pc, #480] @ (8003960 ) 800377e: fba2 2303 umull r2, r3, r2, r3 8003782: 0c9b lsrs r3, r3, #18 8003784: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8003786: 687b ldr r3, [r7, #4] 8003788: 681b ldr r3, [r3, #0] 800378a: 685b ldr r3, [r3, #4] 800378c: f023 013f bic.w r1, r3, #63 @ 0x3f 8003790: 687b ldr r3, [r7, #4] 8003792: 681b ldr r3, [r3, #0] 8003794: 68ba ldr r2, [r7, #8] 8003796: 430a orrs r2, r1 8003798: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 800379a: 687b ldr r3, [r7, #4] 800379c: 681b ldr r3, [r3, #0] 800379e: 6a1b ldr r3, [r3, #32] 80037a0: f023 013f bic.w r1, r3, #63 @ 0x3f 80037a4: 687b ldr r3, [r7, #4] 80037a6: 685b ldr r3, [r3, #4] 80037a8: 4a6a ldr r2, [pc, #424] @ (8003954 ) 80037aa: 4293 cmp r3, r2 80037ac: d802 bhi.n 80037b4 80037ae: 68bb ldr r3, [r7, #8] 80037b0: 3301 adds r3, #1 80037b2: e009 b.n 80037c8 80037b4: 68bb ldr r3, [r7, #8] 80037b6: f44f 7296 mov.w r2, #300 @ 0x12c 80037ba: fb02 f303 mul.w r3, r2, r3 80037be: 4a69 ldr r2, [pc, #420] @ (8003964 ) 80037c0: fba2 2303 umull r2, r3, r2, r3 80037c4: 099b lsrs r3, r3, #6 80037c6: 3301 adds r3, #1 80037c8: 687a ldr r2, [r7, #4] 80037ca: 6812 ldr r2, [r2, #0] 80037cc: 430b orrs r3, r1 80037ce: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 80037d0: 687b ldr r3, [r7, #4] 80037d2: 681b ldr r3, [r3, #0] 80037d4: 69db ldr r3, [r3, #28] 80037d6: f423 424f bic.w r2, r3, #52992 @ 0xcf00 80037da: f022 02ff bic.w r2, r2, #255 @ 0xff 80037de: 687b ldr r3, [r7, #4] 80037e0: 685b ldr r3, [r3, #4] 80037e2: 495c ldr r1, [pc, #368] @ (8003954 ) 80037e4: 428b cmp r3, r1 80037e6: d819 bhi.n 800381c 80037e8: 68fb ldr r3, [r7, #12] 80037ea: 1e59 subs r1, r3, #1 80037ec: 687b ldr r3, [r7, #4] 80037ee: 685b ldr r3, [r3, #4] 80037f0: 005b lsls r3, r3, #1 80037f2: fbb1 f3f3 udiv r3, r1, r3 80037f6: 1c59 adds r1, r3, #1 80037f8: f640 73fc movw r3, #4092 @ 0xffc 80037fc: 400b ands r3, r1 80037fe: 2b00 cmp r3, #0 8003800: d00a beq.n 8003818 8003802: 68fb ldr r3, [r7, #12] 8003804: 1e59 subs r1, r3, #1 8003806: 687b ldr r3, [r7, #4] 8003808: 685b ldr r3, [r3, #4] 800380a: 005b lsls r3, r3, #1 800380c: fbb1 f3f3 udiv r3, r1, r3 8003810: 3301 adds r3, #1 8003812: f3c3 030b ubfx r3, r3, #0, #12 8003816: e051 b.n 80038bc 8003818: 2304 movs r3, #4 800381a: e04f b.n 80038bc 800381c: 687b ldr r3, [r7, #4] 800381e: 689b ldr r3, [r3, #8] 8003820: 2b00 cmp r3, #0 8003822: d111 bne.n 8003848 8003824: 68fb ldr r3, [r7, #12] 8003826: 1e58 subs r0, r3, #1 8003828: 687b ldr r3, [r7, #4] 800382a: 6859 ldr r1, [r3, #4] 800382c: 460b mov r3, r1 800382e: 005b lsls r3, r3, #1 8003830: 440b add r3, r1 8003832: fbb0 f3f3 udiv r3, r0, r3 8003836: 3301 adds r3, #1 8003838: f3c3 030b ubfx r3, r3, #0, #12 800383c: 2b00 cmp r3, #0 800383e: bf0c ite eq 8003840: 2301 moveq r3, #1 8003842: 2300 movne r3, #0 8003844: b2db uxtb r3, r3 8003846: e012 b.n 800386e 8003848: 68fb ldr r3, [r7, #12] 800384a: 1e58 subs r0, r3, #1 800384c: 687b ldr r3, [r7, #4] 800384e: 6859 ldr r1, [r3, #4] 8003850: 460b mov r3, r1 8003852: 009b lsls r3, r3, #2 8003854: 440b add r3, r1 8003856: 0099 lsls r1, r3, #2 8003858: 440b add r3, r1 800385a: fbb0 f3f3 udiv r3, r0, r3 800385e: 3301 adds r3, #1 8003860: f3c3 030b ubfx r3, r3, #0, #12 8003864: 2b00 cmp r3, #0 8003866: bf0c ite eq 8003868: 2301 moveq r3, #1 800386a: 2300 movne r3, #0 800386c: b2db uxtb r3, r3 800386e: 2b00 cmp r3, #0 8003870: d001 beq.n 8003876 8003872: 2301 movs r3, #1 8003874: e022 b.n 80038bc 8003876: 687b ldr r3, [r7, #4] 8003878: 689b ldr r3, [r3, #8] 800387a: 2b00 cmp r3, #0 800387c: d10e bne.n 800389c 800387e: 68fb ldr r3, [r7, #12] 8003880: 1e58 subs r0, r3, #1 8003882: 687b ldr r3, [r7, #4] 8003884: 6859 ldr r1, [r3, #4] 8003886: 460b mov r3, r1 8003888: 005b lsls r3, r3, #1 800388a: 440b add r3, r1 800388c: fbb0 f3f3 udiv r3, r0, r3 8003890: 3301 adds r3, #1 8003892: f3c3 030b ubfx r3, r3, #0, #12 8003896: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800389a: e00f b.n 80038bc 800389c: 68fb ldr r3, [r7, #12] 800389e: 1e58 subs r0, r3, #1 80038a0: 687b ldr r3, [r7, #4] 80038a2: 6859 ldr r1, [r3, #4] 80038a4: 460b mov r3, r1 80038a6: 009b lsls r3, r3, #2 80038a8: 440b add r3, r1 80038aa: 0099 lsls r1, r3, #2 80038ac: 440b add r3, r1 80038ae: fbb0 f3f3 udiv r3, r0, r3 80038b2: 3301 adds r3, #1 80038b4: f3c3 030b ubfx r3, r3, #0, #12 80038b8: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80038bc: 6879 ldr r1, [r7, #4] 80038be: 6809 ldr r1, [r1, #0] 80038c0: 4313 orrs r3, r2 80038c2: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 80038c4: 687b ldr r3, [r7, #4] 80038c6: 681b ldr r3, [r3, #0] 80038c8: 681b ldr r3, [r3, #0] 80038ca: f023 01c0 bic.w r1, r3, #192 @ 0xc0 80038ce: 687b ldr r3, [r7, #4] 80038d0: 69da ldr r2, [r3, #28] 80038d2: 687b ldr r3, [r7, #4] 80038d4: 6a1b ldr r3, [r3, #32] 80038d6: 431a orrs r2, r3 80038d8: 687b ldr r3, [r7, #4] 80038da: 681b ldr r3, [r3, #0] 80038dc: 430a orrs r2, r1 80038de: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 80038e0: 687b ldr r3, [r7, #4] 80038e2: 681b ldr r3, [r3, #0] 80038e4: 689b ldr r3, [r3, #8] 80038e6: f423 4303 bic.w r3, r3, #33536 @ 0x8300 80038ea: f023 03ff bic.w r3, r3, #255 @ 0xff 80038ee: 687a ldr r2, [r7, #4] 80038f0: 6911 ldr r1, [r2, #16] 80038f2: 687a ldr r2, [r7, #4] 80038f4: 68d2 ldr r2, [r2, #12] 80038f6: 4311 orrs r1, r2 80038f8: 687a ldr r2, [r7, #4] 80038fa: 6812 ldr r2, [r2, #0] 80038fc: 430b orrs r3, r1 80038fe: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8003900: 687b ldr r3, [r7, #4] 8003902: 681b ldr r3, [r3, #0] 8003904: 68db ldr r3, [r3, #12] 8003906: f023 01ff bic.w r1, r3, #255 @ 0xff 800390a: 687b ldr r3, [r7, #4] 800390c: 695a ldr r2, [r3, #20] 800390e: 687b ldr r3, [r7, #4] 8003910: 699b ldr r3, [r3, #24] 8003912: 431a orrs r2, r3 8003914: 687b ldr r3, [r7, #4] 8003916: 681b ldr r3, [r3, #0] 8003918: 430a orrs r2, r1 800391a: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800391c: 687b ldr r3, [r7, #4] 800391e: 681b ldr r3, [r3, #0] 8003920: 681a ldr r2, [r3, #0] 8003922: 687b ldr r3, [r7, #4] 8003924: 681b ldr r3, [r3, #0] 8003926: f042 0201 orr.w r2, r2, #1 800392a: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800392c: 687b ldr r3, [r7, #4] 800392e: 2200 movs r2, #0 8003930: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8003932: 687b ldr r3, [r7, #4] 8003934: 2220 movs r2, #32 8003936: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 800393a: 687b ldr r3, [r7, #4] 800393c: 2200 movs r2, #0 800393e: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8003940: 687b ldr r3, [r7, #4] 8003942: 2200 movs r2, #0 8003944: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8003948: 2300 movs r3, #0 } 800394a: 4618 mov r0, r3 800394c: 3710 adds r7, #16 800394e: 46bd mov sp, r7 8003950: bd80 pop {r7, pc} 8003952: bf00 nop 8003954: 000186a0 .word 0x000186a0 8003958: 001e847f .word 0x001e847f 800395c: 003d08ff .word 0x003d08ff 8003960: 431bde83 .word 0x431bde83 8003964: 10624dd3 .word 0x10624dd3 08003968 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003968: b580 push {r7, lr} 800396a: b088 sub sp, #32 800396c: af02 add r7, sp, #8 800396e: 60f8 str r0, [r7, #12] 8003970: 607a str r2, [r7, #4] 8003972: 461a mov r2, r3 8003974: 460b mov r3, r1 8003976: 817b strh r3, [r7, #10] 8003978: 4613 mov r3, r2 800397a: 813b strh r3, [r7, #8] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 800397c: f7ff f8e4 bl 8002b48 8003980: 6178 str r0, [r7, #20] if (hi2c->State == HAL_I2C_STATE_READY) 8003982: 68fb ldr r3, [r7, #12] 8003984: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003988: b2db uxtb r3, r3 800398a: 2b20 cmp r3, #32 800398c: f040 80e0 bne.w 8003b50 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 8003990: 697b ldr r3, [r7, #20] 8003992: 9300 str r3, [sp, #0] 8003994: 2319 movs r3, #25 8003996: 2201 movs r2, #1 8003998: 4970 ldr r1, [pc, #448] @ (8003b5c ) 800399a: 68f8 ldr r0, [r7, #12] 800399c: f000 fc9e bl 80042dc 80039a0: 4603 mov r3, r0 80039a2: 2b00 cmp r3, #0 80039a4: d001 beq.n 80039aa { return HAL_BUSY; 80039a6: 2302 movs r3, #2 80039a8: e0d3 b.n 8003b52 } /* Process Locked */ __HAL_LOCK(hi2c); 80039aa: 68fb ldr r3, [r7, #12] 80039ac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80039b0: 2b01 cmp r3, #1 80039b2: d101 bne.n 80039b8 80039b4: 2302 movs r3, #2 80039b6: e0cc b.n 8003b52 80039b8: 68fb ldr r3, [r7, #12] 80039ba: 2201 movs r2, #1 80039bc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 80039c0: 68fb ldr r3, [r7, #12] 80039c2: 681b ldr r3, [r3, #0] 80039c4: 681b ldr r3, [r3, #0] 80039c6: f003 0301 and.w r3, r3, #1 80039ca: 2b01 cmp r3, #1 80039cc: d007 beq.n 80039de { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80039ce: 68fb ldr r3, [r7, #12] 80039d0: 681b ldr r3, [r3, #0] 80039d2: 681a ldr r2, [r3, #0] 80039d4: 68fb ldr r3, [r7, #12] 80039d6: 681b ldr r3, [r3, #0] 80039d8: f042 0201 orr.w r2, r2, #1 80039dc: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 80039de: 68fb ldr r3, [r7, #12] 80039e0: 681b ldr r3, [r3, #0] 80039e2: 681a ldr r2, [r3, #0] 80039e4: 68fb ldr r3, [r7, #12] 80039e6: 681b ldr r3, [r3, #0] 80039e8: f422 6200 bic.w r2, r2, #2048 @ 0x800 80039ec: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_TX; 80039ee: 68fb ldr r3, [r7, #12] 80039f0: 2221 movs r2, #33 @ 0x21 80039f2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_MASTER; 80039f6: 68fb ldr r3, [r7, #12] 80039f8: 2210 movs r2, #16 80039fa: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80039fe: 68fb ldr r3, [r7, #12] 8003a00: 2200 movs r2, #0 8003a02: 641a str r2, [r3, #64] @ 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8003a04: 68fb ldr r3, [r7, #12] 8003a06: 687a ldr r2, [r7, #4] 8003a08: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 8003a0a: 68fb ldr r3, [r7, #12] 8003a0c: 893a ldrh r2, [r7, #8] 8003a0e: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize = hi2c->XferCount; 8003a10: 68fb ldr r3, [r7, #12] 8003a12: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003a14: b29a uxth r2, r3 8003a16: 68fb ldr r3, [r7, #12] 8003a18: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8003a1a: 68fb ldr r3, [r7, #12] 8003a1c: 4a50 ldr r2, [pc, #320] @ (8003b60 ) 8003a1e: 62da str r2, [r3, #44] @ 0x2c /* Send Slave Address */ if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 8003a20: 8979 ldrh r1, [r7, #10] 8003a22: 697b ldr r3, [r7, #20] 8003a24: 6a3a ldr r2, [r7, #32] 8003a26: 68f8 ldr r0, [r7, #12] 8003a28: f000 fb08 bl 800403c 8003a2c: 4603 mov r3, r0 8003a2e: 2b00 cmp r3, #0 8003a30: d001 beq.n 8003a36 { return HAL_ERROR; 8003a32: 2301 movs r3, #1 8003a34: e08d b.n 8003b52 } /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8003a36: 2300 movs r3, #0 8003a38: 613b str r3, [r7, #16] 8003a3a: 68fb ldr r3, [r7, #12] 8003a3c: 681b ldr r3, [r3, #0] 8003a3e: 695b ldr r3, [r3, #20] 8003a40: 613b str r3, [r7, #16] 8003a42: 68fb ldr r3, [r7, #12] 8003a44: 681b ldr r3, [r3, #0] 8003a46: 699b ldr r3, [r3, #24] 8003a48: 613b str r3, [r7, #16] 8003a4a: 693b ldr r3, [r7, #16] while (hi2c->XferSize > 0U) 8003a4c: e066 b.n 8003b1c { /* Wait until TXE flag is set */ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003a4e: 697a ldr r2, [r7, #20] 8003a50: 6a39 ldr r1, [r7, #32] 8003a52: 68f8 ldr r0, [r7, #12] 8003a54: f000 fd5c bl 8004510 8003a58: 4603 mov r3, r0 8003a5a: 2b00 cmp r3, #0 8003a5c: d00d beq.n 8003a7a { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 8003a5e: 68fb ldr r3, [r7, #12] 8003a60: 6c1b ldr r3, [r3, #64] @ 0x40 8003a62: 2b04 cmp r3, #4 8003a64: d107 bne.n 8003a76 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003a66: 68fb ldr r3, [r7, #12] 8003a68: 681b ldr r3, [r3, #0] 8003a6a: 681a ldr r2, [r3, #0] 8003a6c: 68fb ldr r3, [r7, #12] 8003a6e: 681b ldr r3, [r3, #0] 8003a70: f442 7200 orr.w r2, r2, #512 @ 0x200 8003a74: 601a str r2, [r3, #0] } return HAL_ERROR; 8003a76: 2301 movs r3, #1 8003a78: e06b b.n 8003b52 } /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8003a7a: 68fb ldr r3, [r7, #12] 8003a7c: 6a5b ldr r3, [r3, #36] @ 0x24 8003a7e: 781a ldrb r2, [r3, #0] 8003a80: 68fb ldr r3, [r7, #12] 8003a82: 681b ldr r3, [r3, #0] 8003a84: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003a86: 68fb ldr r3, [r7, #12] 8003a88: 6a5b ldr r3, [r3, #36] @ 0x24 8003a8a: 1c5a adds r2, r3, #1 8003a8c: 68fb ldr r3, [r7, #12] 8003a8e: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferCount--; 8003a90: 68fb ldr r3, [r7, #12] 8003a92: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003a94: b29b uxth r3, r3 8003a96: 3b01 subs r3, #1 8003a98: b29a uxth r2, r3 8003a9a: 68fb ldr r3, [r7, #12] 8003a9c: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8003a9e: 68fb ldr r3, [r7, #12] 8003aa0: 8d1b ldrh r3, [r3, #40] @ 0x28 8003aa2: 3b01 subs r3, #1 8003aa4: b29a uxth r2, r3 8003aa6: 68fb ldr r3, [r7, #12] 8003aa8: 851a strh r2, [r3, #40] @ 0x28 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 8003aaa: 68fb ldr r3, [r7, #12] 8003aac: 681b ldr r3, [r3, #0] 8003aae: 695b ldr r3, [r3, #20] 8003ab0: f003 0304 and.w r3, r3, #4 8003ab4: 2b04 cmp r3, #4 8003ab6: d11b bne.n 8003af0 8003ab8: 68fb ldr r3, [r7, #12] 8003aba: 8d1b ldrh r3, [r3, #40] @ 0x28 8003abc: 2b00 cmp r3, #0 8003abe: d017 beq.n 8003af0 { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8003ac0: 68fb ldr r3, [r7, #12] 8003ac2: 6a5b ldr r3, [r3, #36] @ 0x24 8003ac4: 781a ldrb r2, [r3, #0] 8003ac6: 68fb ldr r3, [r7, #12] 8003ac8: 681b ldr r3, [r3, #0] 8003aca: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003acc: 68fb ldr r3, [r7, #12] 8003ace: 6a5b ldr r3, [r3, #36] @ 0x24 8003ad0: 1c5a adds r2, r3, #1 8003ad2: 68fb ldr r3, [r7, #12] 8003ad4: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferCount--; 8003ad6: 68fb ldr r3, [r7, #12] 8003ad8: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003ada: b29b uxth r3, r3 8003adc: 3b01 subs r3, #1 8003ade: b29a uxth r2, r3 8003ae0: 68fb ldr r3, [r7, #12] 8003ae2: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8003ae4: 68fb ldr r3, [r7, #12] 8003ae6: 8d1b ldrh r3, [r3, #40] @ 0x28 8003ae8: 3b01 subs r3, #1 8003aea: b29a uxth r2, r3 8003aec: 68fb ldr r3, [r7, #12] 8003aee: 851a strh r2, [r3, #40] @ 0x28 } /* Wait until BTF flag is set */ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003af0: 697a ldr r2, [r7, #20] 8003af2: 6a39 ldr r1, [r7, #32] 8003af4: 68f8 ldr r0, [r7, #12] 8003af6: f000 fd53 bl 80045a0 8003afa: 4603 mov r3, r0 8003afc: 2b00 cmp r3, #0 8003afe: d00d beq.n 8003b1c { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 8003b00: 68fb ldr r3, [r7, #12] 8003b02: 6c1b ldr r3, [r3, #64] @ 0x40 8003b04: 2b04 cmp r3, #4 8003b06: d107 bne.n 8003b18 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003b08: 68fb ldr r3, [r7, #12] 8003b0a: 681b ldr r3, [r3, #0] 8003b0c: 681a ldr r2, [r3, #0] 8003b0e: 68fb ldr r3, [r7, #12] 8003b10: 681b ldr r3, [r3, #0] 8003b12: f442 7200 orr.w r2, r2, #512 @ 0x200 8003b16: 601a str r2, [r3, #0] } return HAL_ERROR; 8003b18: 2301 movs r3, #1 8003b1a: e01a b.n 8003b52 while (hi2c->XferSize > 0U) 8003b1c: 68fb ldr r3, [r7, #12] 8003b1e: 8d1b ldrh r3, [r3, #40] @ 0x28 8003b20: 2b00 cmp r3, #0 8003b22: d194 bne.n 8003a4e } } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003b24: 68fb ldr r3, [r7, #12] 8003b26: 681b ldr r3, [r3, #0] 8003b28: 681a ldr r2, [r3, #0] 8003b2a: 68fb ldr r3, [r7, #12] 8003b2c: 681b ldr r3, [r3, #0] 8003b2e: f442 7200 orr.w r2, r2, #512 @ 0x200 8003b32: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003b34: 68fb ldr r3, [r7, #12] 8003b36: 2220 movs r2, #32 8003b38: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8003b3c: 68fb ldr r3, [r7, #12] 8003b3e: 2200 movs r2, #0 8003b40: f883 203e strb.w r2, [r3, #62] @ 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003b44: 68fb ldr r3, [r7, #12] 8003b46: 2200 movs r2, #0 8003b48: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8003b4c: 2300 movs r3, #0 8003b4e: e000 b.n 8003b52 } else { return HAL_BUSY; 8003b50: 2302 movs r3, #2 } } 8003b52: 4618 mov r0, r3 8003b54: 3718 adds r7, #24 8003b56: 46bd mov sp, r7 8003b58: bd80 pop {r7, pc} 8003b5a: bf00 nop 8003b5c: 00100002 .word 0x00100002 8003b60: ffff0000 .word 0xffff0000 08003b64 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003b64: b580 push {r7, lr} 8003b66: b08c sub sp, #48 @ 0x30 8003b68: af02 add r7, sp, #8 8003b6a: 60f8 str r0, [r7, #12] 8003b6c: 607a str r2, [r7, #4] 8003b6e: 461a mov r2, r3 8003b70: 460b mov r3, r1 8003b72: 817b strh r3, [r7, #10] 8003b74: 4613 mov r3, r2 8003b76: 813b strh r3, [r7, #8] __IO uint32_t count = 0U; 8003b78: 2300 movs r3, #0 8003b7a: 623b str r3, [r7, #32] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 8003b7c: f7fe ffe4 bl 8002b48 8003b80: 6278 str r0, [r7, #36] @ 0x24 if (hi2c->State == HAL_I2C_STATE_READY) 8003b82: 68fb ldr r3, [r7, #12] 8003b84: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003b88: b2db uxtb r3, r3 8003b8a: 2b20 cmp r3, #32 8003b8c: f040 824b bne.w 8004026 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 8003b90: 6a7b ldr r3, [r7, #36] @ 0x24 8003b92: 9300 str r3, [sp, #0] 8003b94: 2319 movs r3, #25 8003b96: 2201 movs r2, #1 8003b98: 497f ldr r1, [pc, #508] @ (8003d98 ) 8003b9a: 68f8 ldr r0, [r7, #12] 8003b9c: f000 fb9e bl 80042dc 8003ba0: 4603 mov r3, r0 8003ba2: 2b00 cmp r3, #0 8003ba4: d001 beq.n 8003baa { return HAL_BUSY; 8003ba6: 2302 movs r3, #2 8003ba8: e23e b.n 8004028 } /* Process Locked */ __HAL_LOCK(hi2c); 8003baa: 68fb ldr r3, [r7, #12] 8003bac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8003bb0: 2b01 cmp r3, #1 8003bb2: d101 bne.n 8003bb8 8003bb4: 2302 movs r3, #2 8003bb6: e237 b.n 8004028 8003bb8: 68fb ldr r3, [r7, #12] 8003bba: 2201 movs r2, #1 8003bbc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 8003bc0: 68fb ldr r3, [r7, #12] 8003bc2: 681b ldr r3, [r3, #0] 8003bc4: 681b ldr r3, [r3, #0] 8003bc6: f003 0301 and.w r3, r3, #1 8003bca: 2b01 cmp r3, #1 8003bcc: d007 beq.n 8003bde { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8003bce: 68fb ldr r3, [r7, #12] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: 681a ldr r2, [r3, #0] 8003bd4: 68fb ldr r3, [r7, #12] 8003bd6: 681b ldr r3, [r3, #0] 8003bd8: f042 0201 orr.w r2, r2, #1 8003bdc: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8003bde: 68fb ldr r3, [r7, #12] 8003be0: 681b ldr r3, [r3, #0] 8003be2: 681a ldr r2, [r3, #0] 8003be4: 68fb ldr r3, [r7, #12] 8003be6: 681b ldr r3, [r3, #0] 8003be8: f422 6200 bic.w r2, r2, #2048 @ 0x800 8003bec: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_RX; 8003bee: 68fb ldr r3, [r7, #12] 8003bf0: 2222 movs r2, #34 @ 0x22 8003bf2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_MASTER; 8003bf6: 68fb ldr r3, [r7, #12] 8003bf8: 2210 movs r2, #16 8003bfa: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003bfe: 68fb ldr r3, [r7, #12] 8003c00: 2200 movs r2, #0 8003c02: 641a str r2, [r3, #64] @ 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8003c04: 68fb ldr r3, [r7, #12] 8003c06: 687a ldr r2, [r7, #4] 8003c08: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 8003c0a: 68fb ldr r3, [r7, #12] 8003c0c: 893a ldrh r2, [r7, #8] 8003c0e: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize = hi2c->XferCount; 8003c10: 68fb ldr r3, [r7, #12] 8003c12: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003c14: b29a uxth r2, r3 8003c16: 68fb ldr r3, [r7, #12] 8003c18: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8003c1a: 68fb ldr r3, [r7, #12] 8003c1c: 4a5f ldr r2, [pc, #380] @ (8003d9c ) 8003c1e: 62da str r2, [r3, #44] @ 0x2c /* Send Slave Address */ if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 8003c20: 8979 ldrh r1, [r7, #10] 8003c22: 6a7b ldr r3, [r7, #36] @ 0x24 8003c24: 6b3a ldr r2, [r7, #48] @ 0x30 8003c26: 68f8 ldr r0, [r7, #12] 8003c28: f000 fa8a bl 8004140 8003c2c: 4603 mov r3, r0 8003c2e: 2b00 cmp r3, #0 8003c30: d001 beq.n 8003c36 { return HAL_ERROR; 8003c32: 2301 movs r3, #1 8003c34: e1f8 b.n 8004028 } if (hi2c->XferSize == 0U) 8003c36: 68fb ldr r3, [r7, #12] 8003c38: 8d1b ldrh r3, [r3, #40] @ 0x28 8003c3a: 2b00 cmp r3, #0 8003c3c: d113 bne.n 8003c66 { /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8003c3e: 2300 movs r3, #0 8003c40: 61fb str r3, [r7, #28] 8003c42: 68fb ldr r3, [r7, #12] 8003c44: 681b ldr r3, [r3, #0] 8003c46: 695b ldr r3, [r3, #20] 8003c48: 61fb str r3, [r7, #28] 8003c4a: 68fb ldr r3, [r7, #12] 8003c4c: 681b ldr r3, [r3, #0] 8003c4e: 699b ldr r3, [r3, #24] 8003c50: 61fb str r3, [r7, #28] 8003c52: 69fb ldr r3, [r7, #28] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003c54: 68fb ldr r3, [r7, #12] 8003c56: 681b ldr r3, [r3, #0] 8003c58: 681a ldr r2, [r3, #0] 8003c5a: 68fb ldr r3, [r7, #12] 8003c5c: 681b ldr r3, [r3, #0] 8003c5e: f442 7200 orr.w r2, r2, #512 @ 0x200 8003c62: 601a str r2, [r3, #0] 8003c64: e1cc b.n 8004000 } else if (hi2c->XferSize == 1U) 8003c66: 68fb ldr r3, [r7, #12] 8003c68: 8d1b ldrh r3, [r3, #40] @ 0x28 8003c6a: 2b01 cmp r3, #1 8003c6c: d11e bne.n 8003cac { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8003c6e: 68fb ldr r3, [r7, #12] 8003c70: 681b ldr r3, [r3, #0] 8003c72: 681a ldr r2, [r3, #0] 8003c74: 68fb ldr r3, [r7, #12] 8003c76: 681b ldr r3, [r3, #0] 8003c78: f422 6280 bic.w r2, r2, #1024 @ 0x400 8003c7c: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8003c7e: b672 cpsid i } 8003c80: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8003c82: 2300 movs r3, #0 8003c84: 61bb str r3, [r7, #24] 8003c86: 68fb ldr r3, [r7, #12] 8003c88: 681b ldr r3, [r3, #0] 8003c8a: 695b ldr r3, [r3, #20] 8003c8c: 61bb str r3, [r7, #24] 8003c8e: 68fb ldr r3, [r7, #12] 8003c90: 681b ldr r3, [r3, #0] 8003c92: 699b ldr r3, [r3, #24] 8003c94: 61bb str r3, [r7, #24] 8003c96: 69bb ldr r3, [r7, #24] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003c98: 68fb ldr r3, [r7, #12] 8003c9a: 681b ldr r3, [r3, #0] 8003c9c: 681a ldr r2, [r3, #0] 8003c9e: 68fb ldr r3, [r7, #12] 8003ca0: 681b ldr r3, [r3, #0] 8003ca2: f442 7200 orr.w r2, r2, #512 @ 0x200 8003ca6: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8003ca8: b662 cpsie i } 8003caa: e035 b.n 8003d18 /* Re-enable IRQs */ __enable_irq(); } else if (hi2c->XferSize == 2U) 8003cac: 68fb ldr r3, [r7, #12] 8003cae: 8d1b ldrh r3, [r3, #40] @ 0x28 8003cb0: 2b02 cmp r3, #2 8003cb2: d11e bne.n 8003cf2 { /* Enable Pos */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8003cb4: 68fb ldr r3, [r7, #12] 8003cb6: 681b ldr r3, [r3, #0] 8003cb8: 681a ldr r2, [r3, #0] 8003cba: 68fb ldr r3, [r7, #12] 8003cbc: 681b ldr r3, [r3, #0] 8003cbe: f442 6200 orr.w r2, r2, #2048 @ 0x800 8003cc2: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8003cc4: b672 cpsid i } 8003cc6: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8003cc8: 2300 movs r3, #0 8003cca: 617b str r3, [r7, #20] 8003ccc: 68fb ldr r3, [r7, #12] 8003cce: 681b ldr r3, [r3, #0] 8003cd0: 695b ldr r3, [r3, #20] 8003cd2: 617b str r3, [r7, #20] 8003cd4: 68fb ldr r3, [r7, #12] 8003cd6: 681b ldr r3, [r3, #0] 8003cd8: 699b ldr r3, [r3, #24] 8003cda: 617b str r3, [r7, #20] 8003cdc: 697b ldr r3, [r7, #20] /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8003cde: 68fb ldr r3, [r7, #12] 8003ce0: 681b ldr r3, [r3, #0] 8003ce2: 681a ldr r2, [r3, #0] 8003ce4: 68fb ldr r3, [r7, #12] 8003ce6: 681b ldr r3, [r3, #0] 8003ce8: f422 6280 bic.w r2, r2, #1024 @ 0x400 8003cec: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8003cee: b662 cpsie i } 8003cf0: e012 b.n 8003d18 __enable_irq(); } else { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8003cf2: 68fb ldr r3, [r7, #12] 8003cf4: 681b ldr r3, [r3, #0] 8003cf6: 681a ldr r2, [r3, #0] 8003cf8: 68fb ldr r3, [r7, #12] 8003cfa: 681b ldr r3, [r3, #0] 8003cfc: f442 6280 orr.w r2, r2, #1024 @ 0x400 8003d00: 601a str r2, [r3, #0] /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8003d02: 2300 movs r3, #0 8003d04: 613b str r3, [r7, #16] 8003d06: 68fb ldr r3, [r7, #12] 8003d08: 681b ldr r3, [r3, #0] 8003d0a: 695b ldr r3, [r3, #20] 8003d0c: 613b str r3, [r7, #16] 8003d0e: 68fb ldr r3, [r7, #12] 8003d10: 681b ldr r3, [r3, #0] 8003d12: 699b ldr r3, [r3, #24] 8003d14: 613b str r3, [r7, #16] 8003d16: 693b ldr r3, [r7, #16] } while (hi2c->XferSize > 0U) 8003d18: e172 b.n 8004000 { if (hi2c->XferSize <= 3U) 8003d1a: 68fb ldr r3, [r7, #12] 8003d1c: 8d1b ldrh r3, [r3, #40] @ 0x28 8003d1e: 2b03 cmp r3, #3 8003d20: f200 811f bhi.w 8003f62 { /* One byte */ if (hi2c->XferSize == 1U) 8003d24: 68fb ldr r3, [r7, #12] 8003d26: 8d1b ldrh r3, [r3, #40] @ 0x28 8003d28: 2b01 cmp r3, #1 8003d2a: d123 bne.n 8003d74 { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003d2c: 6a7a ldr r2, [r7, #36] @ 0x24 8003d2e: 6b39 ldr r1, [r7, #48] @ 0x30 8003d30: 68f8 ldr r0, [r7, #12] 8003d32: f000 fc7d bl 8004630 8003d36: 4603 mov r3, r0 8003d38: 2b00 cmp r3, #0 8003d3a: d001 beq.n 8003d40 { return HAL_ERROR; 8003d3c: 2301 movs r3, #1 8003d3e: e173 b.n 8004028 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003d40: 68fb ldr r3, [r7, #12] 8003d42: 681b ldr r3, [r3, #0] 8003d44: 691a ldr r2, [r3, #16] 8003d46: 68fb ldr r3, [r7, #12] 8003d48: 6a5b ldr r3, [r3, #36] @ 0x24 8003d4a: b2d2 uxtb r2, r2 8003d4c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003d4e: 68fb ldr r3, [r7, #12] 8003d50: 6a5b ldr r3, [r3, #36] @ 0x24 8003d52: 1c5a adds r2, r3, #1 8003d54: 68fb ldr r3, [r7, #12] 8003d56: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003d58: 68fb ldr r3, [r7, #12] 8003d5a: 8d1b ldrh r3, [r3, #40] @ 0x28 8003d5c: 3b01 subs r3, #1 8003d5e: b29a uxth r2, r3 8003d60: 68fb ldr r3, [r7, #12] 8003d62: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003d64: 68fb ldr r3, [r7, #12] 8003d66: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003d68: b29b uxth r3, r3 8003d6a: 3b01 subs r3, #1 8003d6c: b29a uxth r2, r3 8003d6e: 68fb ldr r3, [r7, #12] 8003d70: 855a strh r2, [r3, #42] @ 0x2a 8003d72: e145 b.n 8004000 } /* Two bytes */ else if (hi2c->XferSize == 2U) 8003d74: 68fb ldr r3, [r7, #12] 8003d76: 8d1b ldrh r3, [r3, #40] @ 0x28 8003d78: 2b02 cmp r3, #2 8003d7a: d152 bne.n 8003e22 { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 8003d7c: 6a7b ldr r3, [r7, #36] @ 0x24 8003d7e: 9300 str r3, [sp, #0] 8003d80: 6b3b ldr r3, [r7, #48] @ 0x30 8003d82: 2200 movs r2, #0 8003d84: 4906 ldr r1, [pc, #24] @ (8003da0 ) 8003d86: 68f8 ldr r0, [r7, #12] 8003d88: f000 faa8 bl 80042dc 8003d8c: 4603 mov r3, r0 8003d8e: 2b00 cmp r3, #0 8003d90: d008 beq.n 8003da4 { return HAL_ERROR; 8003d92: 2301 movs r3, #1 8003d94: e148 b.n 8004028 8003d96: bf00 nop 8003d98: 00100002 .word 0x00100002 8003d9c: ffff0000 .word 0xffff0000 8003da0: 00010004 .word 0x00010004 __ASM volatile ("cpsid i" : : : "memory"); 8003da4: b672 cpsid i } 8003da6: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003da8: 68fb ldr r3, [r7, #12] 8003daa: 681b ldr r3, [r3, #0] 8003dac: 681a ldr r2, [r3, #0] 8003dae: 68fb ldr r3, [r7, #12] 8003db0: 681b ldr r3, [r3, #0] 8003db2: f442 7200 orr.w r2, r2, #512 @ 0x200 8003db6: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003db8: 68fb ldr r3, [r7, #12] 8003dba: 681b ldr r3, [r3, #0] 8003dbc: 691a ldr r2, [r3, #16] 8003dbe: 68fb ldr r3, [r7, #12] 8003dc0: 6a5b ldr r3, [r3, #36] @ 0x24 8003dc2: b2d2 uxtb r2, r2 8003dc4: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003dc6: 68fb ldr r3, [r7, #12] 8003dc8: 6a5b ldr r3, [r3, #36] @ 0x24 8003dca: 1c5a adds r2, r3, #1 8003dcc: 68fb ldr r3, [r7, #12] 8003dce: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003dd0: 68fb ldr r3, [r7, #12] 8003dd2: 8d1b ldrh r3, [r3, #40] @ 0x28 8003dd4: 3b01 subs r3, #1 8003dd6: b29a uxth r2, r3 8003dd8: 68fb ldr r3, [r7, #12] 8003dda: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003ddc: 68fb ldr r3, [r7, #12] 8003dde: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003de0: b29b uxth r3, r3 8003de2: 3b01 subs r3, #1 8003de4: b29a uxth r2, r3 8003de6: 68fb ldr r3, [r7, #12] 8003de8: 855a strh r2, [r3, #42] @ 0x2a __ASM volatile ("cpsie i" : : : "memory"); 8003dea: b662 cpsie i } 8003dec: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003dee: 68fb ldr r3, [r7, #12] 8003df0: 681b ldr r3, [r3, #0] 8003df2: 691a ldr r2, [r3, #16] 8003df4: 68fb ldr r3, [r7, #12] 8003df6: 6a5b ldr r3, [r3, #36] @ 0x24 8003df8: b2d2 uxtb r2, r2 8003dfa: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003dfc: 68fb ldr r3, [r7, #12] 8003dfe: 6a5b ldr r3, [r3, #36] @ 0x24 8003e00: 1c5a adds r2, r3, #1 8003e02: 68fb ldr r3, [r7, #12] 8003e04: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003e06: 68fb ldr r3, [r7, #12] 8003e08: 8d1b ldrh r3, [r3, #40] @ 0x28 8003e0a: 3b01 subs r3, #1 8003e0c: b29a uxth r2, r3 8003e0e: 68fb ldr r3, [r7, #12] 8003e10: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003e12: 68fb ldr r3, [r7, #12] 8003e14: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003e16: b29b uxth r3, r3 8003e18: 3b01 subs r3, #1 8003e1a: b29a uxth r2, r3 8003e1c: 68fb ldr r3, [r7, #12] 8003e1e: 855a strh r2, [r3, #42] @ 0x2a 8003e20: e0ee b.n 8004000 } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 8003e22: 6a7b ldr r3, [r7, #36] @ 0x24 8003e24: 9300 str r3, [sp, #0] 8003e26: 6b3b ldr r3, [r7, #48] @ 0x30 8003e28: 2200 movs r2, #0 8003e2a: 4981 ldr r1, [pc, #516] @ (8004030 ) 8003e2c: 68f8 ldr r0, [r7, #12] 8003e2e: f000 fa55 bl 80042dc 8003e32: 4603 mov r3, r0 8003e34: 2b00 cmp r3, #0 8003e36: d001 beq.n 8003e3c { return HAL_ERROR; 8003e38: 2301 movs r3, #1 8003e3a: e0f5 b.n 8004028 } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8003e3c: 68fb ldr r3, [r7, #12] 8003e3e: 681b ldr r3, [r3, #0] 8003e40: 681a ldr r2, [r3, #0] 8003e42: 68fb ldr r3, [r7, #12] 8003e44: 681b ldr r3, [r3, #0] 8003e46: f422 6280 bic.w r2, r2, #1024 @ 0x400 8003e4a: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8003e4c: b672 cpsid i } 8003e4e: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003e50: 68fb ldr r3, [r7, #12] 8003e52: 681b ldr r3, [r3, #0] 8003e54: 691a ldr r2, [r3, #16] 8003e56: 68fb ldr r3, [r7, #12] 8003e58: 6a5b ldr r3, [r3, #36] @ 0x24 8003e5a: b2d2 uxtb r2, r2 8003e5c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003e5e: 68fb ldr r3, [r7, #12] 8003e60: 6a5b ldr r3, [r3, #36] @ 0x24 8003e62: 1c5a adds r2, r3, #1 8003e64: 68fb ldr r3, [r7, #12] 8003e66: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003e68: 68fb ldr r3, [r7, #12] 8003e6a: 8d1b ldrh r3, [r3, #40] @ 0x28 8003e6c: 3b01 subs r3, #1 8003e6e: b29a uxth r2, r3 8003e70: 68fb ldr r3, [r7, #12] 8003e72: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003e74: 68fb ldr r3, [r7, #12] 8003e76: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003e78: b29b uxth r3, r3 8003e7a: 3b01 subs r3, #1 8003e7c: b29a uxth r2, r3 8003e7e: 68fb ldr r3, [r7, #12] 8003e80: 855a strh r2, [r3, #42] @ 0x2a /* Wait until BTF flag is set */ count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 8003e82: 4b6c ldr r3, [pc, #432] @ (8004034 ) 8003e84: 681b ldr r3, [r3, #0] 8003e86: 08db lsrs r3, r3, #3 8003e88: 4a6b ldr r2, [pc, #428] @ (8004038 ) 8003e8a: fba2 2303 umull r2, r3, r2, r3 8003e8e: 0a1a lsrs r2, r3, #8 8003e90: 4613 mov r3, r2 8003e92: 009b lsls r3, r3, #2 8003e94: 4413 add r3, r2 8003e96: 00da lsls r2, r3, #3 8003e98: 1ad3 subs r3, r2, r3 8003e9a: 623b str r3, [r7, #32] do { count--; 8003e9c: 6a3b ldr r3, [r7, #32] 8003e9e: 3b01 subs r3, #1 8003ea0: 623b str r3, [r7, #32] if (count == 0U) 8003ea2: 6a3b ldr r3, [r7, #32] 8003ea4: 2b00 cmp r3, #0 8003ea6: d118 bne.n 8003eda { hi2c->PreviousState = I2C_STATE_NONE; 8003ea8: 68fb ldr r3, [r7, #12] 8003eaa: 2200 movs r2, #0 8003eac: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8003eae: 68fb ldr r3, [r7, #12] 8003eb0: 2220 movs r2, #32 8003eb2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8003eb6: 68fb ldr r3, [r7, #12] 8003eb8: 2200 movs r2, #0 8003eba: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8003ebe: 68fb ldr r3, [r7, #12] 8003ec0: 6c1b ldr r3, [r3, #64] @ 0x40 8003ec2: f043 0220 orr.w r2, r3, #32 8003ec6: 68fb ldr r3, [r7, #12] 8003ec8: 641a str r2, [r3, #64] @ 0x40 __ASM volatile ("cpsie i" : : : "memory"); 8003eca: b662 cpsie i } 8003ecc: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003ece: 68fb ldr r3, [r7, #12] 8003ed0: 2200 movs r2, #0 8003ed2: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 8003ed6: 2301 movs r3, #1 8003ed8: e0a6 b.n 8004028 } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 8003eda: 68fb ldr r3, [r7, #12] 8003edc: 681b ldr r3, [r3, #0] 8003ede: 695b ldr r3, [r3, #20] 8003ee0: f003 0304 and.w r3, r3, #4 8003ee4: 2b04 cmp r3, #4 8003ee6: d1d9 bne.n 8003e9c /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8003ee8: 68fb ldr r3, [r7, #12] 8003eea: 681b ldr r3, [r3, #0] 8003eec: 681a ldr r2, [r3, #0] 8003eee: 68fb ldr r3, [r7, #12] 8003ef0: 681b ldr r3, [r3, #0] 8003ef2: f442 7200 orr.w r2, r2, #512 @ 0x200 8003ef6: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003ef8: 68fb ldr r3, [r7, #12] 8003efa: 681b ldr r3, [r3, #0] 8003efc: 691a ldr r2, [r3, #16] 8003efe: 68fb ldr r3, [r7, #12] 8003f00: 6a5b ldr r3, [r3, #36] @ 0x24 8003f02: b2d2 uxtb r2, r2 8003f04: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003f06: 68fb ldr r3, [r7, #12] 8003f08: 6a5b ldr r3, [r3, #36] @ 0x24 8003f0a: 1c5a adds r2, r3, #1 8003f0c: 68fb ldr r3, [r7, #12] 8003f0e: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003f10: 68fb ldr r3, [r7, #12] 8003f12: 8d1b ldrh r3, [r3, #40] @ 0x28 8003f14: 3b01 subs r3, #1 8003f16: b29a uxth r2, r3 8003f18: 68fb ldr r3, [r7, #12] 8003f1a: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003f1c: 68fb ldr r3, [r7, #12] 8003f1e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003f20: b29b uxth r3, r3 8003f22: 3b01 subs r3, #1 8003f24: b29a uxth r2, r3 8003f26: 68fb ldr r3, [r7, #12] 8003f28: 855a strh r2, [r3, #42] @ 0x2a __ASM volatile ("cpsie i" : : : "memory"); 8003f2a: b662 cpsie i } 8003f2c: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003f2e: 68fb ldr r3, [r7, #12] 8003f30: 681b ldr r3, [r3, #0] 8003f32: 691a ldr r2, [r3, #16] 8003f34: 68fb ldr r3, [r7, #12] 8003f36: 6a5b ldr r3, [r3, #36] @ 0x24 8003f38: b2d2 uxtb r2, r2 8003f3a: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003f3c: 68fb ldr r3, [r7, #12] 8003f3e: 6a5b ldr r3, [r3, #36] @ 0x24 8003f40: 1c5a adds r2, r3, #1 8003f42: 68fb ldr r3, [r7, #12] 8003f44: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003f46: 68fb ldr r3, [r7, #12] 8003f48: 8d1b ldrh r3, [r3, #40] @ 0x28 8003f4a: 3b01 subs r3, #1 8003f4c: b29a uxth r2, r3 8003f4e: 68fb ldr r3, [r7, #12] 8003f50: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003f52: 68fb ldr r3, [r7, #12] 8003f54: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003f56: b29b uxth r3, r3 8003f58: 3b01 subs r3, #1 8003f5a: b29a uxth r2, r3 8003f5c: 68fb ldr r3, [r7, #12] 8003f5e: 855a strh r2, [r3, #42] @ 0x2a 8003f60: e04e b.n 8004000 } } else { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003f62: 6a7a ldr r2, [r7, #36] @ 0x24 8003f64: 6b39 ldr r1, [r7, #48] @ 0x30 8003f66: 68f8 ldr r0, [r7, #12] 8003f68: f000 fb62 bl 8004630 8003f6c: 4603 mov r3, r0 8003f6e: 2b00 cmp r3, #0 8003f70: d001 beq.n 8003f76 { return HAL_ERROR; 8003f72: 2301 movs r3, #1 8003f74: e058 b.n 8004028 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003f76: 68fb ldr r3, [r7, #12] 8003f78: 681b ldr r3, [r3, #0] 8003f7a: 691a ldr r2, [r3, #16] 8003f7c: 68fb ldr r3, [r7, #12] 8003f7e: 6a5b ldr r3, [r3, #36] @ 0x24 8003f80: b2d2 uxtb r2, r2 8003f82: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003f84: 68fb ldr r3, [r7, #12] 8003f86: 6a5b ldr r3, [r3, #36] @ 0x24 8003f88: 1c5a adds r2, r3, #1 8003f8a: 68fb ldr r3, [r7, #12] 8003f8c: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003f8e: 68fb ldr r3, [r7, #12] 8003f90: 8d1b ldrh r3, [r3, #40] @ 0x28 8003f92: 3b01 subs r3, #1 8003f94: b29a uxth r2, r3 8003f96: 68fb ldr r3, [r7, #12] 8003f98: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003f9a: 68fb ldr r3, [r7, #12] 8003f9c: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003f9e: b29b uxth r3, r3 8003fa0: 3b01 subs r3, #1 8003fa2: b29a uxth r2, r3 8003fa4: 68fb ldr r3, [r7, #12] 8003fa6: 855a strh r2, [r3, #42] @ 0x2a if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 8003fa8: 68fb ldr r3, [r7, #12] 8003faa: 681b ldr r3, [r3, #0] 8003fac: 695b ldr r3, [r3, #20] 8003fae: f003 0304 and.w r3, r3, #4 8003fb2: 2b04 cmp r3, #4 8003fb4: d124 bne.n 8004000 { if (hi2c->XferSize == 3U) 8003fb6: 68fb ldr r3, [r7, #12] 8003fb8: 8d1b ldrh r3, [r3, #40] @ 0x28 8003fba: 2b03 cmp r3, #3 8003fbc: d107 bne.n 8003fce { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8003fbe: 68fb ldr r3, [r7, #12] 8003fc0: 681b ldr r3, [r3, #0] 8003fc2: 681a ldr r2, [r3, #0] 8003fc4: 68fb ldr r3, [r7, #12] 8003fc6: 681b ldr r3, [r3, #0] 8003fc8: f422 6280 bic.w r2, r2, #1024 @ 0x400 8003fcc: 601a str r2, [r3, #0] } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8003fce: 68fb ldr r3, [r7, #12] 8003fd0: 681b ldr r3, [r3, #0] 8003fd2: 691a ldr r2, [r3, #16] 8003fd4: 68fb ldr r3, [r7, #12] 8003fd6: 6a5b ldr r3, [r3, #36] @ 0x24 8003fd8: b2d2 uxtb r2, r2 8003fda: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003fdc: 68fb ldr r3, [r7, #12] 8003fde: 6a5b ldr r3, [r3, #36] @ 0x24 8003fe0: 1c5a adds r2, r3, #1 8003fe2: 68fb ldr r3, [r7, #12] 8003fe4: 625a str r2, [r3, #36] @ 0x24 /* Update counter */ hi2c->XferSize--; 8003fe6: 68fb ldr r3, [r7, #12] 8003fe8: 8d1b ldrh r3, [r3, #40] @ 0x28 8003fea: 3b01 subs r3, #1 8003fec: b29a uxth r2, r3 8003fee: 68fb ldr r3, [r7, #12] 8003ff0: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8003ff2: 68fb ldr r3, [r7, #12] 8003ff4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8003ff6: b29b uxth r3, r3 8003ff8: 3b01 subs r3, #1 8003ffa: b29a uxth r2, r3 8003ffc: 68fb ldr r3, [r7, #12] 8003ffe: 855a strh r2, [r3, #42] @ 0x2a while (hi2c->XferSize > 0U) 8004000: 68fb ldr r3, [r7, #12] 8004002: 8d1b ldrh r3, [r3, #40] @ 0x28 8004004: 2b00 cmp r3, #0 8004006: f47f ae88 bne.w 8003d1a } } } hi2c->State = HAL_I2C_STATE_READY; 800400a: 68fb ldr r3, [r7, #12] 800400c: 2220 movs r2, #32 800400e: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8004012: 68fb ldr r3, [r7, #12] 8004014: 2200 movs r2, #0 8004016: f883 203e strb.w r2, [r3, #62] @ 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800401a: 68fb ldr r3, [r7, #12] 800401c: 2200 movs r2, #0 800401e: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8004022: 2300 movs r3, #0 8004024: e000 b.n 8004028 } else { return HAL_BUSY; 8004026: 2302 movs r3, #2 } } 8004028: 4618 mov r0, r3 800402a: 3728 adds r7, #40 @ 0x28 800402c: 46bd mov sp, r7 800402e: bd80 pop {r7, pc} 8004030: 00010004 .word 0x00010004 8004034: 2000001c .word 0x2000001c 8004038: 14f8b589 .word 0x14f8b589 0800403c : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) { 800403c: b580 push {r7, lr} 800403e: b088 sub sp, #32 8004040: af02 add r7, sp, #8 8004042: 60f8 str r0, [r7, #12] 8004044: 607a str r2, [r7, #4] 8004046: 603b str r3, [r7, #0] 8004048: 460b mov r3, r1 800404a: 817b strh r3, [r7, #10] /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ uint32_t CurrentXferOptions = hi2c->XferOptions; 800404c: 68fb ldr r3, [r7, #12] 800404e: 6adb ldr r3, [r3, #44] @ 0x2c 8004050: 617b str r3, [r7, #20] /* Generate Start condition if first transfer */ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 8004052: 697b ldr r3, [r7, #20] 8004054: 2b08 cmp r3, #8 8004056: d006 beq.n 8004066 8004058: 697b ldr r3, [r7, #20] 800405a: 2b01 cmp r3, #1 800405c: d003 beq.n 8004066 800405e: 697b ldr r3, [r7, #20] 8004060: f513 3f80 cmn.w r3, #65536 @ 0x10000 8004064: d108 bne.n 8004078 { /* Generate Start */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 8004066: 68fb ldr r3, [r7, #12] 8004068: 681b ldr r3, [r3, #0] 800406a: 681a ldr r2, [r3, #0] 800406c: 68fb ldr r3, [r7, #12] 800406e: 681b ldr r3, [r3, #0] 8004070: f442 7280 orr.w r2, r2, #256 @ 0x100 8004074: 601a str r2, [r3, #0] 8004076: e00b b.n 8004090 } else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) 8004078: 68fb ldr r3, [r7, #12] 800407a: 6b1b ldr r3, [r3, #48] @ 0x30 800407c: 2b12 cmp r3, #18 800407e: d107 bne.n 8004090 { /* Generate ReStart */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 8004080: 68fb ldr r3, [r7, #12] 8004082: 681b ldr r3, [r3, #0] 8004084: 681a ldr r2, [r3, #0] 8004086: 68fb ldr r3, [r7, #12] 8004088: 681b ldr r3, [r3, #0] 800408a: f442 7280 orr.w r2, r2, #256 @ 0x100 800408e: 601a str r2, [r3, #0] { /* Do nothing */ } /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 8004090: 683b ldr r3, [r7, #0] 8004092: 9300 str r3, [sp, #0] 8004094: 687b ldr r3, [r7, #4] 8004096: 2200 movs r2, #0 8004098: f04f 1101 mov.w r1, #65537 @ 0x10001 800409c: 68f8 ldr r0, [r7, #12] 800409e: f000 f91d bl 80042dc 80040a2: 4603 mov r3, r0 80040a4: 2b00 cmp r3, #0 80040a6: d00d beq.n 80040c4 { if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 80040a8: 68fb ldr r3, [r7, #12] 80040aa: 681b ldr r3, [r3, #0] 80040ac: 681b ldr r3, [r3, #0] 80040ae: f403 7380 and.w r3, r3, #256 @ 0x100 80040b2: f5b3 7f80 cmp.w r3, #256 @ 0x100 80040b6: d103 bne.n 80040c0 { hi2c->ErrorCode = HAL_I2C_WRONG_START; 80040b8: 68fb ldr r3, [r7, #12] 80040ba: f44f 7200 mov.w r2, #512 @ 0x200 80040be: 641a str r2, [r3, #64] @ 0x40 } return HAL_TIMEOUT; 80040c0: 2303 movs r3, #3 80040c2: e035 b.n 8004130 } if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 80040c4: 68fb ldr r3, [r7, #12] 80040c6: 691b ldr r3, [r3, #16] 80040c8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80040cc: d108 bne.n 80040e0 { /* Send slave address */ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 80040ce: 897b ldrh r3, [r7, #10] 80040d0: b2db uxtb r3, r3 80040d2: 461a mov r2, r3 80040d4: 68fb ldr r3, [r7, #12] 80040d6: 681b ldr r3, [r3, #0] 80040d8: f002 02fe and.w r2, r2, #254 @ 0xfe 80040dc: 611a str r2, [r3, #16] 80040de: e01b b.n 8004118 } else { /* Send header of slave address */ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 80040e0: 897b ldrh r3, [r7, #10] 80040e2: 11db asrs r3, r3, #7 80040e4: b2db uxtb r3, r3 80040e6: f003 0306 and.w r3, r3, #6 80040ea: b2db uxtb r3, r3 80040ec: f063 030f orn r3, r3, #15 80040f0: b2da uxtb r2, r3 80040f2: 68fb ldr r3, [r7, #12] 80040f4: 681b ldr r3, [r3, #0] 80040f6: 611a str r2, [r3, #16] /* Wait until ADD10 flag is set */ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 80040f8: 683b ldr r3, [r7, #0] 80040fa: 687a ldr r2, [r7, #4] 80040fc: 490e ldr r1, [pc, #56] @ (8004138 ) 80040fe: 68f8 ldr r0, [r7, #12] 8004100: f000 f966 bl 80043d0 8004104: 4603 mov r3, r0 8004106: 2b00 cmp r3, #0 8004108: d001 beq.n 800410e { return HAL_ERROR; 800410a: 2301 movs r3, #1 800410c: e010 b.n 8004130 } /* Send slave address */ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 800410e: 897b ldrh r3, [r7, #10] 8004110: b2da uxtb r2, r3 8004112: 68fb ldr r3, [r7, #12] 8004114: 681b ldr r3, [r3, #0] 8004116: 611a str r2, [r3, #16] } /* Wait until ADDR flag is set */ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 8004118: 683b ldr r3, [r7, #0] 800411a: 687a ldr r2, [r7, #4] 800411c: 4907 ldr r1, [pc, #28] @ (800413c ) 800411e: 68f8 ldr r0, [r7, #12] 8004120: f000 f956 bl 80043d0 8004124: 4603 mov r3, r0 8004126: 2b00 cmp r3, #0 8004128: d001 beq.n 800412e { return HAL_ERROR; 800412a: 2301 movs r3, #1 800412c: e000 b.n 8004130 } return HAL_OK; 800412e: 2300 movs r3, #0 } 8004130: 4618 mov r0, r3 8004132: 3718 adds r7, #24 8004134: 46bd mov sp, r7 8004136: bd80 pop {r7, pc} 8004138: 00010008 .word 0x00010008 800413c: 00010002 .word 0x00010002 08004140 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) { 8004140: b580 push {r7, lr} 8004142: b088 sub sp, #32 8004144: af02 add r7, sp, #8 8004146: 60f8 str r0, [r7, #12] 8004148: 607a str r2, [r7, #4] 800414a: 603b str r3, [r7, #0] 800414c: 460b mov r3, r1 800414e: 817b strh r3, [r7, #10] /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ uint32_t CurrentXferOptions = hi2c->XferOptions; 8004150: 68fb ldr r3, [r7, #12] 8004152: 6adb ldr r3, [r3, #44] @ 0x2c 8004154: 617b str r3, [r7, #20] /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8004156: 68fb ldr r3, [r7, #12] 8004158: 681b ldr r3, [r3, #0] 800415a: 681a ldr r2, [r3, #0] 800415c: 68fb ldr r3, [r7, #12] 800415e: 681b ldr r3, [r3, #0] 8004160: f442 6280 orr.w r2, r2, #1024 @ 0x400 8004164: 601a str r2, [r3, #0] /* Generate Start condition if first transfer */ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 8004166: 697b ldr r3, [r7, #20] 8004168: 2b08 cmp r3, #8 800416a: d006 beq.n 800417a 800416c: 697b ldr r3, [r7, #20] 800416e: 2b01 cmp r3, #1 8004170: d003 beq.n 800417a 8004172: 697b ldr r3, [r7, #20] 8004174: f513 3f80 cmn.w r3, #65536 @ 0x10000 8004178: d108 bne.n 800418c { /* Generate Start */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 800417a: 68fb ldr r3, [r7, #12] 800417c: 681b ldr r3, [r3, #0] 800417e: 681a ldr r2, [r3, #0] 8004180: 68fb ldr r3, [r7, #12] 8004182: 681b ldr r3, [r3, #0] 8004184: f442 7280 orr.w r2, r2, #256 @ 0x100 8004188: 601a str r2, [r3, #0] 800418a: e00b b.n 80041a4 } else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) 800418c: 68fb ldr r3, [r7, #12] 800418e: 6b1b ldr r3, [r3, #48] @ 0x30 8004190: 2b11 cmp r3, #17 8004192: d107 bne.n 80041a4 { /* Generate ReStart */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 8004194: 68fb ldr r3, [r7, #12] 8004196: 681b ldr r3, [r3, #0] 8004198: 681a ldr r2, [r3, #0] 800419a: 68fb ldr r3, [r7, #12] 800419c: 681b ldr r3, [r3, #0] 800419e: f442 7280 orr.w r2, r2, #256 @ 0x100 80041a2: 601a str r2, [r3, #0] { /* Do nothing */ } /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 80041a4: 683b ldr r3, [r7, #0] 80041a6: 9300 str r3, [sp, #0] 80041a8: 687b ldr r3, [r7, #4] 80041aa: 2200 movs r2, #0 80041ac: f04f 1101 mov.w r1, #65537 @ 0x10001 80041b0: 68f8 ldr r0, [r7, #12] 80041b2: f000 f893 bl 80042dc 80041b6: 4603 mov r3, r0 80041b8: 2b00 cmp r3, #0 80041ba: d00d beq.n 80041d8 { if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 80041bc: 68fb ldr r3, [r7, #12] 80041be: 681b ldr r3, [r3, #0] 80041c0: 681b ldr r3, [r3, #0] 80041c2: f403 7380 and.w r3, r3, #256 @ 0x100 80041c6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80041ca: d103 bne.n 80041d4 { hi2c->ErrorCode = HAL_I2C_WRONG_START; 80041cc: 68fb ldr r3, [r7, #12] 80041ce: f44f 7200 mov.w r2, #512 @ 0x200 80041d2: 641a str r2, [r3, #64] @ 0x40 } return HAL_TIMEOUT; 80041d4: 2303 movs r3, #3 80041d6: e079 b.n 80042cc } if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 80041d8: 68fb ldr r3, [r7, #12] 80041da: 691b ldr r3, [r3, #16] 80041dc: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80041e0: d108 bne.n 80041f4 { /* Send slave address */ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); 80041e2: 897b ldrh r3, [r7, #10] 80041e4: b2db uxtb r3, r3 80041e6: f043 0301 orr.w r3, r3, #1 80041ea: b2da uxtb r2, r3 80041ec: 68fb ldr r3, [r7, #12] 80041ee: 681b ldr r3, [r3, #0] 80041f0: 611a str r2, [r3, #16] 80041f2: e05f b.n 80042b4 } else { /* Send header of slave address */ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 80041f4: 897b ldrh r3, [r7, #10] 80041f6: 11db asrs r3, r3, #7 80041f8: b2db uxtb r3, r3 80041fa: f003 0306 and.w r3, r3, #6 80041fe: b2db uxtb r3, r3 8004200: f063 030f orn r3, r3, #15 8004204: b2da uxtb r2, r3 8004206: 68fb ldr r3, [r7, #12] 8004208: 681b ldr r3, [r3, #0] 800420a: 611a str r2, [r3, #16] /* Wait until ADD10 flag is set */ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 800420c: 683b ldr r3, [r7, #0] 800420e: 687a ldr r2, [r7, #4] 8004210: 4930 ldr r1, [pc, #192] @ (80042d4 ) 8004212: 68f8 ldr r0, [r7, #12] 8004214: f000 f8dc bl 80043d0 8004218: 4603 mov r3, r0 800421a: 2b00 cmp r3, #0 800421c: d001 beq.n 8004222 { return HAL_ERROR; 800421e: 2301 movs r3, #1 8004220: e054 b.n 80042cc } /* Send slave address */ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 8004222: 897b ldrh r3, [r7, #10] 8004224: b2da uxtb r2, r3 8004226: 68fb ldr r3, [r7, #12] 8004228: 681b ldr r3, [r3, #0] 800422a: 611a str r2, [r3, #16] /* Wait until ADDR flag is set */ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 800422c: 683b ldr r3, [r7, #0] 800422e: 687a ldr r2, [r7, #4] 8004230: 4929 ldr r1, [pc, #164] @ (80042d8 ) 8004232: 68f8 ldr r0, [r7, #12] 8004234: f000 f8cc bl 80043d0 8004238: 4603 mov r3, r0 800423a: 2b00 cmp r3, #0 800423c: d001 beq.n 8004242 { return HAL_ERROR; 800423e: 2301 movs r3, #1 8004240: e044 b.n 80042cc } /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8004242: 2300 movs r3, #0 8004244: 613b str r3, [r7, #16] 8004246: 68fb ldr r3, [r7, #12] 8004248: 681b ldr r3, [r3, #0] 800424a: 695b ldr r3, [r3, #20] 800424c: 613b str r3, [r7, #16] 800424e: 68fb ldr r3, [r7, #12] 8004250: 681b ldr r3, [r3, #0] 8004252: 699b ldr r3, [r3, #24] 8004254: 613b str r3, [r7, #16] 8004256: 693b ldr r3, [r7, #16] /* Generate Restart */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 8004258: 68fb ldr r3, [r7, #12] 800425a: 681b ldr r3, [r3, #0] 800425c: 681a ldr r2, [r3, #0] 800425e: 68fb ldr r3, [r7, #12] 8004260: 681b ldr r3, [r3, #0] 8004262: f442 7280 orr.w r2, r2, #256 @ 0x100 8004266: 601a str r2, [r3, #0] /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 8004268: 683b ldr r3, [r7, #0] 800426a: 9300 str r3, [sp, #0] 800426c: 687b ldr r3, [r7, #4] 800426e: 2200 movs r2, #0 8004270: f04f 1101 mov.w r1, #65537 @ 0x10001 8004274: 68f8 ldr r0, [r7, #12] 8004276: f000 f831 bl 80042dc 800427a: 4603 mov r3, r0 800427c: 2b00 cmp r3, #0 800427e: d00d beq.n 800429c { if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 8004280: 68fb ldr r3, [r7, #12] 8004282: 681b ldr r3, [r3, #0] 8004284: 681b ldr r3, [r3, #0] 8004286: f403 7380 and.w r3, r3, #256 @ 0x100 800428a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800428e: d103 bne.n 8004298 { hi2c->ErrorCode = HAL_I2C_WRONG_START; 8004290: 68fb ldr r3, [r7, #12] 8004292: f44f 7200 mov.w r2, #512 @ 0x200 8004296: 641a str r2, [r3, #64] @ 0x40 } return HAL_TIMEOUT; 8004298: 2303 movs r3, #3 800429a: e017 b.n 80042cc } /* Send header of slave address */ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); 800429c: 897b ldrh r3, [r7, #10] 800429e: 11db asrs r3, r3, #7 80042a0: b2db uxtb r3, r3 80042a2: f003 0306 and.w r3, r3, #6 80042a6: b2db uxtb r3, r3 80042a8: f063 030e orn r3, r3, #14 80042ac: b2da uxtb r2, r3 80042ae: 68fb ldr r3, [r7, #12] 80042b0: 681b ldr r3, [r3, #0] 80042b2: 611a str r2, [r3, #16] } /* Wait until ADDR flag is set */ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 80042b4: 683b ldr r3, [r7, #0] 80042b6: 687a ldr r2, [r7, #4] 80042b8: 4907 ldr r1, [pc, #28] @ (80042d8 ) 80042ba: 68f8 ldr r0, [r7, #12] 80042bc: f000 f888 bl 80043d0 80042c0: 4603 mov r3, r0 80042c2: 2b00 cmp r3, #0 80042c4: d001 beq.n 80042ca { return HAL_ERROR; 80042c6: 2301 movs r3, #1 80042c8: e000 b.n 80042cc } return HAL_OK; 80042ca: 2300 movs r3, #0 } 80042cc: 4618 mov r0, r3 80042ce: 3718 adds r7, #24 80042d0: 46bd mov sp, r7 80042d2: bd80 pop {r7, pc} 80042d4: 00010008 .word 0x00010008 80042d8: 00010002 .word 0x00010002 080042dc : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { 80042dc: b580 push {r7, lr} 80042de: b084 sub sp, #16 80042e0: af00 add r7, sp, #0 80042e2: 60f8 str r0, [r7, #12] 80042e4: 60b9 str r1, [r7, #8] 80042e6: 603b str r3, [r7, #0] 80042e8: 4613 mov r3, r2 80042ea: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 80042ec: e048 b.n 8004380 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80042ee: 683b ldr r3, [r7, #0] 80042f0: f1b3 3fff cmp.w r3, #4294967295 80042f4: d044 beq.n 8004380 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80042f6: f7fe fc27 bl 8002b48 80042fa: 4602 mov r2, r0 80042fc: 69bb ldr r3, [r7, #24] 80042fe: 1ad3 subs r3, r2, r3 8004300: 683a ldr r2, [r7, #0] 8004302: 429a cmp r2, r3 8004304: d302 bcc.n 800430c 8004306: 683b ldr r3, [r7, #0] 8004308: 2b00 cmp r3, #0 800430a: d139 bne.n 8004380 { if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) 800430c: 68bb ldr r3, [r7, #8] 800430e: 0c1b lsrs r3, r3, #16 8004310: b2db uxtb r3, r3 8004312: 2b01 cmp r3, #1 8004314: d10d bne.n 8004332 8004316: 68fb ldr r3, [r7, #12] 8004318: 681b ldr r3, [r3, #0] 800431a: 695b ldr r3, [r3, #20] 800431c: 43da mvns r2, r3 800431e: 68bb ldr r3, [r7, #8] 8004320: 4013 ands r3, r2 8004322: b29b uxth r3, r3 8004324: 2b00 cmp r3, #0 8004326: bf0c ite eq 8004328: 2301 moveq r3, #1 800432a: 2300 movne r3, #0 800432c: b2db uxtb r3, r3 800432e: 461a mov r2, r3 8004330: e00c b.n 800434c 8004332: 68fb ldr r3, [r7, #12] 8004334: 681b ldr r3, [r3, #0] 8004336: 699b ldr r3, [r3, #24] 8004338: 43da mvns r2, r3 800433a: 68bb ldr r3, [r7, #8] 800433c: 4013 ands r3, r2 800433e: b29b uxth r3, r3 8004340: 2b00 cmp r3, #0 8004342: bf0c ite eq 8004344: 2301 moveq r3, #1 8004346: 2300 movne r3, #0 8004348: b2db uxtb r3, r3 800434a: 461a mov r2, r3 800434c: 79fb ldrb r3, [r7, #7] 800434e: 429a cmp r2, r3 8004350: d116 bne.n 8004380 { hi2c->PreviousState = I2C_STATE_NONE; 8004352: 68fb ldr r3, [r7, #12] 8004354: 2200 movs r2, #0 8004356: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8004358: 68fb ldr r3, [r7, #12] 800435a: 2220 movs r2, #32 800435c: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8004360: 68fb ldr r3, [r7, #12] 8004362: 2200 movs r2, #0 8004364: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8004368: 68fb ldr r3, [r7, #12] 800436a: 6c1b ldr r3, [r3, #64] @ 0x40 800436c: f043 0220 orr.w r2, r3, #32 8004370: 68fb ldr r3, [r7, #12] 8004372: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004374: 68fb ldr r3, [r7, #12] 8004376: 2200 movs r2, #0 8004378: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 800437c: 2301 movs r3, #1 800437e: e023 b.n 80043c8 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 8004380: 68bb ldr r3, [r7, #8] 8004382: 0c1b lsrs r3, r3, #16 8004384: b2db uxtb r3, r3 8004386: 2b01 cmp r3, #1 8004388: d10d bne.n 80043a6 800438a: 68fb ldr r3, [r7, #12] 800438c: 681b ldr r3, [r3, #0] 800438e: 695b ldr r3, [r3, #20] 8004390: 43da mvns r2, r3 8004392: 68bb ldr r3, [r7, #8] 8004394: 4013 ands r3, r2 8004396: b29b uxth r3, r3 8004398: 2b00 cmp r3, #0 800439a: bf0c ite eq 800439c: 2301 moveq r3, #1 800439e: 2300 movne r3, #0 80043a0: b2db uxtb r3, r3 80043a2: 461a mov r2, r3 80043a4: e00c b.n 80043c0 80043a6: 68fb ldr r3, [r7, #12] 80043a8: 681b ldr r3, [r3, #0] 80043aa: 699b ldr r3, [r3, #24] 80043ac: 43da mvns r2, r3 80043ae: 68bb ldr r3, [r7, #8] 80043b0: 4013 ands r3, r2 80043b2: b29b uxth r3, r3 80043b4: 2b00 cmp r3, #0 80043b6: bf0c ite eq 80043b8: 2301 moveq r3, #1 80043ba: 2300 movne r3, #0 80043bc: b2db uxtb r3, r3 80043be: 461a mov r2, r3 80043c0: 79fb ldrb r3, [r7, #7] 80043c2: 429a cmp r2, r3 80043c4: d093 beq.n 80042ee } } } } return HAL_OK; 80043c6: 2300 movs r3, #0 } 80043c8: 4618 mov r0, r3 80043ca: 3710 adds r7, #16 80043cc: 46bd mov sp, r7 80043ce: bd80 pop {r7, pc} 080043d0 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) { 80043d0: b580 push {r7, lr} 80043d2: b084 sub sp, #16 80043d4: af00 add r7, sp, #0 80043d6: 60f8 str r0, [r7, #12] 80043d8: 60b9 str r1, [r7, #8] 80043da: 607a str r2, [r7, #4] 80043dc: 603b str r3, [r7, #0] while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) 80043de: e071 b.n 80044c4 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 80043e0: 68fb ldr r3, [r7, #12] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 695b ldr r3, [r3, #20] 80043e6: f403 6380 and.w r3, r3, #1024 @ 0x400 80043ea: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80043ee: d123 bne.n 8004438 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80043f0: 68fb ldr r3, [r7, #12] 80043f2: 681b ldr r3, [r3, #0] 80043f4: 681a ldr r2, [r3, #0] 80043f6: 68fb ldr r3, [r7, #12] 80043f8: 681b ldr r3, [r3, #0] 80043fa: f442 7200 orr.w r2, r2, #512 @ 0x200 80043fe: 601a str r2, [r3, #0] /* Clear AF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8004400: 68fb ldr r3, [r7, #12] 8004402: 681b ldr r3, [r3, #0] 8004404: f46f 6280 mvn.w r2, #1024 @ 0x400 8004408: 615a str r2, [r3, #20] hi2c->PreviousState = I2C_STATE_NONE; 800440a: 68fb ldr r3, [r7, #12] 800440c: 2200 movs r2, #0 800440e: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8004410: 68fb ldr r3, [r7, #12] 8004412: 2220 movs r2, #32 8004414: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8004418: 68fb ldr r3, [r7, #12] 800441a: 2200 movs r2, #0 800441c: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8004420: 68fb ldr r3, [r7, #12] 8004422: 6c1b ldr r3, [r3, #64] @ 0x40 8004424: f043 0204 orr.w r2, r3, #4 8004428: 68fb ldr r3, [r7, #12] 800442a: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800442c: 68fb ldr r3, [r7, #12] 800442e: 2200 movs r2, #0 8004430: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 8004434: 2301 movs r3, #1 8004436: e067 b.n 8004508 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004438: 687b ldr r3, [r7, #4] 800443a: f1b3 3fff cmp.w r3, #4294967295 800443e: d041 beq.n 80044c4 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004440: f7fe fb82 bl 8002b48 8004444: 4602 mov r2, r0 8004446: 683b ldr r3, [r7, #0] 8004448: 1ad3 subs r3, r2, r3 800444a: 687a ldr r2, [r7, #4] 800444c: 429a cmp r2, r3 800444e: d302 bcc.n 8004456 8004450: 687b ldr r3, [r7, #4] 8004452: 2b00 cmp r3, #0 8004454: d136 bne.n 80044c4 { if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) 8004456: 68bb ldr r3, [r7, #8] 8004458: 0c1b lsrs r3, r3, #16 800445a: b2db uxtb r3, r3 800445c: 2b01 cmp r3, #1 800445e: d10c bne.n 800447a 8004460: 68fb ldr r3, [r7, #12] 8004462: 681b ldr r3, [r3, #0] 8004464: 695b ldr r3, [r3, #20] 8004466: 43da mvns r2, r3 8004468: 68bb ldr r3, [r7, #8] 800446a: 4013 ands r3, r2 800446c: b29b uxth r3, r3 800446e: 2b00 cmp r3, #0 8004470: bf14 ite ne 8004472: 2301 movne r3, #1 8004474: 2300 moveq r3, #0 8004476: b2db uxtb r3, r3 8004478: e00b b.n 8004492 800447a: 68fb ldr r3, [r7, #12] 800447c: 681b ldr r3, [r3, #0] 800447e: 699b ldr r3, [r3, #24] 8004480: 43da mvns r2, r3 8004482: 68bb ldr r3, [r7, #8] 8004484: 4013 ands r3, r2 8004486: b29b uxth r3, r3 8004488: 2b00 cmp r3, #0 800448a: bf14 ite ne 800448c: 2301 movne r3, #1 800448e: 2300 moveq r3, #0 8004490: b2db uxtb r3, r3 8004492: 2b00 cmp r3, #0 8004494: d016 beq.n 80044c4 { hi2c->PreviousState = I2C_STATE_NONE; 8004496: 68fb ldr r3, [r7, #12] 8004498: 2200 movs r2, #0 800449a: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 800449c: 68fb ldr r3, [r7, #12] 800449e: 2220 movs r2, #32 80044a0: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80044a4: 68fb ldr r3, [r7, #12] 80044a6: 2200 movs r2, #0 80044a8: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80044ac: 68fb ldr r3, [r7, #12] 80044ae: 6c1b ldr r3, [r3, #64] @ 0x40 80044b0: f043 0220 orr.w r2, r3, #32 80044b4: 68fb ldr r3, [r7, #12] 80044b6: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80044b8: 68fb ldr r3, [r7, #12] 80044ba: 2200 movs r2, #0 80044bc: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 80044c0: 2301 movs r3, #1 80044c2: e021 b.n 8004508 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) 80044c4: 68bb ldr r3, [r7, #8] 80044c6: 0c1b lsrs r3, r3, #16 80044c8: b2db uxtb r3, r3 80044ca: 2b01 cmp r3, #1 80044cc: d10c bne.n 80044e8 80044ce: 68fb ldr r3, [r7, #12] 80044d0: 681b ldr r3, [r3, #0] 80044d2: 695b ldr r3, [r3, #20] 80044d4: 43da mvns r2, r3 80044d6: 68bb ldr r3, [r7, #8] 80044d8: 4013 ands r3, r2 80044da: b29b uxth r3, r3 80044dc: 2b00 cmp r3, #0 80044de: bf14 ite ne 80044e0: 2301 movne r3, #1 80044e2: 2300 moveq r3, #0 80044e4: b2db uxtb r3, r3 80044e6: e00b b.n 8004500 80044e8: 68fb ldr r3, [r7, #12] 80044ea: 681b ldr r3, [r3, #0] 80044ec: 699b ldr r3, [r3, #24] 80044ee: 43da mvns r2, r3 80044f0: 68bb ldr r3, [r7, #8] 80044f2: 4013 ands r3, r2 80044f4: b29b uxth r3, r3 80044f6: 2b00 cmp r3, #0 80044f8: bf14 ite ne 80044fa: 2301 movne r3, #1 80044fc: 2300 moveq r3, #0 80044fe: b2db uxtb r3, r3 8004500: 2b00 cmp r3, #0 8004502: f47f af6d bne.w 80043e0 } } } } return HAL_OK; 8004506: 2300 movs r3, #0 } 8004508: 4618 mov r0, r3 800450a: 3710 adds r7, #16 800450c: 46bd mov sp, r7 800450e: bd80 pop {r7, pc} 08004510 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8004510: b580 push {r7, lr} 8004512: b084 sub sp, #16 8004514: af00 add r7, sp, #0 8004516: 60f8 str r0, [r7, #12] 8004518: 60b9 str r1, [r7, #8] 800451a: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 800451c: e034 b.n 8004588 { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 800451e: 68f8 ldr r0, [r7, #12] 8004520: f000 f8e3 bl 80046ea 8004524: 4603 mov r3, r0 8004526: 2b00 cmp r3, #0 8004528: d001 beq.n 800452e { return HAL_ERROR; 800452a: 2301 movs r3, #1 800452c: e034 b.n 8004598 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800452e: 68bb ldr r3, [r7, #8] 8004530: f1b3 3fff cmp.w r3, #4294967295 8004534: d028 beq.n 8004588 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004536: f7fe fb07 bl 8002b48 800453a: 4602 mov r2, r0 800453c: 687b ldr r3, [r7, #4] 800453e: 1ad3 subs r3, r2, r3 8004540: 68ba ldr r2, [r7, #8] 8004542: 429a cmp r2, r3 8004544: d302 bcc.n 800454c 8004546: 68bb ldr r3, [r7, #8] 8004548: 2b00 cmp r3, #0 800454a: d11d bne.n 8004588 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) 800454c: 68fb ldr r3, [r7, #12] 800454e: 681b ldr r3, [r3, #0] 8004550: 695b ldr r3, [r3, #20] 8004552: f003 0380 and.w r3, r3, #128 @ 0x80 8004556: 2b80 cmp r3, #128 @ 0x80 8004558: d016 beq.n 8004588 { hi2c->PreviousState = I2C_STATE_NONE; 800455a: 68fb ldr r3, [r7, #12] 800455c: 2200 movs r2, #0 800455e: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8004560: 68fb ldr r3, [r7, #12] 8004562: 2220 movs r2, #32 8004564: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8004568: 68fb ldr r3, [r7, #12] 800456a: 2200 movs r2, #0 800456c: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8004570: 68fb ldr r3, [r7, #12] 8004572: 6c1b ldr r3, [r3, #64] @ 0x40 8004574: f043 0220 orr.w r2, r3, #32 8004578: 68fb ldr r3, [r7, #12] 800457a: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800457c: 68fb ldr r3, [r7, #12] 800457e: 2200 movs r2, #0 8004580: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 8004584: 2301 movs r3, #1 8004586: e007 b.n 8004598 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8004588: 68fb ldr r3, [r7, #12] 800458a: 681b ldr r3, [r3, #0] 800458c: 695b ldr r3, [r3, #20] 800458e: f003 0380 and.w r3, r3, #128 @ 0x80 8004592: 2b80 cmp r3, #128 @ 0x80 8004594: d1c3 bne.n 800451e } } } } return HAL_OK; 8004596: 2300 movs r3, #0 } 8004598: 4618 mov r0, r3 800459a: 3710 adds r7, #16 800459c: 46bd mov sp, r7 800459e: bd80 pop {r7, pc} 080045a0 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 80045a0: b580 push {r7, lr} 80045a2: b084 sub sp, #16 80045a4: af00 add r7, sp, #0 80045a6: 60f8 str r0, [r7, #12] 80045a8: 60b9 str r1, [r7, #8] 80045aa: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) 80045ac: e034 b.n 8004618 { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 80045ae: 68f8 ldr r0, [r7, #12] 80045b0: f000 f89b bl 80046ea 80045b4: 4603 mov r3, r0 80045b6: 2b00 cmp r3, #0 80045b8: d001 beq.n 80045be { return HAL_ERROR; 80045ba: 2301 movs r3, #1 80045bc: e034 b.n 8004628 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80045be: 68bb ldr r3, [r7, #8] 80045c0: f1b3 3fff cmp.w r3, #4294967295 80045c4: d028 beq.n 8004618 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80045c6: f7fe fabf bl 8002b48 80045ca: 4602 mov r2, r0 80045cc: 687b ldr r3, [r7, #4] 80045ce: 1ad3 subs r3, r2, r3 80045d0: 68ba ldr r2, [r7, #8] 80045d2: 429a cmp r2, r3 80045d4: d302 bcc.n 80045dc 80045d6: 68bb ldr r3, [r7, #8] 80045d8: 2b00 cmp r3, #0 80045da: d11d bne.n 8004618 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) 80045dc: 68fb ldr r3, [r7, #12] 80045de: 681b ldr r3, [r3, #0] 80045e0: 695b ldr r3, [r3, #20] 80045e2: f003 0304 and.w r3, r3, #4 80045e6: 2b04 cmp r3, #4 80045e8: d016 beq.n 8004618 { hi2c->PreviousState = I2C_STATE_NONE; 80045ea: 68fb ldr r3, [r7, #12] 80045ec: 2200 movs r2, #0 80045ee: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 80045f0: 68fb ldr r3, [r7, #12] 80045f2: 2220 movs r2, #32 80045f4: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80045f8: 68fb ldr r3, [r7, #12] 80045fa: 2200 movs r2, #0 80045fc: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8004600: 68fb ldr r3, [r7, #12] 8004602: 6c1b ldr r3, [r3, #64] @ 0x40 8004604: f043 0220 orr.w r2, r3, #32 8004608: 68fb ldr r3, [r7, #12] 800460a: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800460c: 68fb ldr r3, [r7, #12] 800460e: 2200 movs r2, #0 8004610: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 8004614: 2301 movs r3, #1 8004616: e007 b.n 8004628 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) 8004618: 68fb ldr r3, [r7, #12] 800461a: 681b ldr r3, [r3, #0] 800461c: 695b ldr r3, [r3, #20] 800461e: f003 0304 and.w r3, r3, #4 8004622: 2b04 cmp r3, #4 8004624: d1c3 bne.n 80045ae } } } } return HAL_OK; 8004626: 2300 movs r3, #0 } 8004628: 4618 mov r0, r3 800462a: 3710 adds r7, #16 800462c: 46bd mov sp, r7 800462e: bd80 pop {r7, pc} 08004630 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8004630: b580 push {r7, lr} 8004632: b084 sub sp, #16 8004634: af00 add r7, sp, #0 8004636: 60f8 str r0, [r7, #12] 8004638: 60b9 str r1, [r7, #8] 800463a: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 800463c: e049 b.n 80046d2 { /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 800463e: 68fb ldr r3, [r7, #12] 8004640: 681b ldr r3, [r3, #0] 8004642: 695b ldr r3, [r3, #20] 8004644: f003 0310 and.w r3, r3, #16 8004648: 2b10 cmp r3, #16 800464a: d119 bne.n 8004680 { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800464c: 68fb ldr r3, [r7, #12] 800464e: 681b ldr r3, [r3, #0] 8004650: f06f 0210 mvn.w r2, #16 8004654: 615a str r2, [r3, #20] hi2c->PreviousState = I2C_STATE_NONE; 8004656: 68fb ldr r3, [r7, #12] 8004658: 2200 movs r2, #0 800465a: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 800465c: 68fb ldr r3, [r7, #12] 800465e: 2220 movs r2, #32 8004660: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8004664: 68fb ldr r3, [r7, #12] 8004666: 2200 movs r2, #0 8004668: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; 800466c: 68fb ldr r3, [r7, #12] 800466e: 6c1a ldr r2, [r3, #64] @ 0x40 8004670: 68fb ldr r3, [r7, #12] 8004672: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004674: 68fb ldr r3, [r7, #12] 8004676: 2200 movs r2, #0 8004678: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 800467c: 2301 movs r3, #1 800467e: e030 b.n 80046e2 } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004680: f7fe fa62 bl 8002b48 8004684: 4602 mov r2, r0 8004686: 687b ldr r3, [r7, #4] 8004688: 1ad3 subs r3, r2, r3 800468a: 68ba ldr r2, [r7, #8] 800468c: 429a cmp r2, r3 800468e: d302 bcc.n 8004696 8004690: 68bb ldr r3, [r7, #8] 8004692: 2b00 cmp r3, #0 8004694: d11d bne.n 80046d2 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) 8004696: 68fb ldr r3, [r7, #12] 8004698: 681b ldr r3, [r3, #0] 800469a: 695b ldr r3, [r3, #20] 800469c: f003 0340 and.w r3, r3, #64 @ 0x40 80046a0: 2b40 cmp r3, #64 @ 0x40 80046a2: d016 beq.n 80046d2 { hi2c->PreviousState = I2C_STATE_NONE; 80046a4: 68fb ldr r3, [r7, #12] 80046a6: 2200 movs r2, #0 80046a8: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 80046aa: 68fb ldr r3, [r7, #12] 80046ac: 2220 movs r2, #32 80046ae: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80046b2: 68fb ldr r3, [r7, #12] 80046b4: 2200 movs r2, #0 80046b6: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80046ba: 68fb ldr r3, [r7, #12] 80046bc: 6c1b ldr r3, [r3, #64] @ 0x40 80046be: f043 0220 orr.w r2, r3, #32 80046c2: 68fb ldr r3, [r7, #12] 80046c4: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80046c6: 68fb ldr r3, [r7, #12] 80046c8: 2200 movs r2, #0 80046ca: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 80046ce: 2301 movs r3, #1 80046d0: e007 b.n 80046e2 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 80046d2: 68fb ldr r3, [r7, #12] 80046d4: 681b ldr r3, [r3, #0] 80046d6: 695b ldr r3, [r3, #20] 80046d8: f003 0340 and.w r3, r3, #64 @ 0x40 80046dc: 2b40 cmp r3, #64 @ 0x40 80046de: d1ae bne.n 800463e } } } return HAL_OK; 80046e0: 2300 movs r3, #0 } 80046e2: 4618 mov r0, r3 80046e4: 3710 adds r7, #16 80046e6: 46bd mov sp, r7 80046e8: bd80 pop {r7, pc} 080046ea : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) { 80046ea: b480 push {r7} 80046ec: b083 sub sp, #12 80046ee: af00 add r7, sp, #0 80046f0: 6078 str r0, [r7, #4] if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 80046f2: 687b ldr r3, [r7, #4] 80046f4: 681b ldr r3, [r3, #0] 80046f6: 695b ldr r3, [r3, #20] 80046f8: f403 6380 and.w r3, r3, #1024 @ 0x400 80046fc: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004700: d11b bne.n 800473a { /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8004702: 687b ldr r3, [r7, #4] 8004704: 681b ldr r3, [r3, #0] 8004706: f46f 6280 mvn.w r2, #1024 @ 0x400 800470a: 615a str r2, [r3, #20] hi2c->PreviousState = I2C_STATE_NONE; 800470c: 687b ldr r3, [r7, #4] 800470e: 2200 movs r2, #0 8004710: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8004712: 687b ldr r3, [r7, #4] 8004714: 2220 movs r2, #32 8004716: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 800471a: 687b ldr r3, [r7, #4] 800471c: 2200 movs r2, #0 800471e: f883 203e strb.w r2, [r3, #62] @ 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8004722: 687b ldr r3, [r7, #4] 8004724: 6c1b ldr r3, [r3, #64] @ 0x40 8004726: f043 0204 orr.w r2, r3, #4 800472a: 687b ldr r3, [r7, #4] 800472c: 641a str r2, [r3, #64] @ 0x40 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800472e: 687b ldr r3, [r7, #4] 8004730: 2200 movs r2, #0 8004732: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_ERROR; 8004736: 2301 movs r3, #1 8004738: e000 b.n 800473c } return HAL_OK; 800473a: 2300 movs r3, #0 } 800473c: 4618 mov r0, r3 800473e: 370c adds r7, #12 8004740: 46bd mov sp, r7 8004742: bc80 pop {r7} 8004744: 4770 bx lr ... 08004748 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004748: b580 push {r7, lr} 800474a: b086 sub sp, #24 800474c: af00 add r7, sp, #0 800474e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004750: 687b ldr r3, [r7, #4] 8004752: 2b00 cmp r3, #0 8004754: d101 bne.n 800475a { return HAL_ERROR; 8004756: 2301 movs r3, #1 8004758: e272 b.n 8004c40 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800475a: 687b ldr r3, [r7, #4] 800475c: 681b ldr r3, [r3, #0] 800475e: f003 0301 and.w r3, r3, #1 8004762: 2b00 cmp r3, #0 8004764: f000 8087 beq.w 8004876 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8004768: 4b92 ldr r3, [pc, #584] @ (80049b4 ) 800476a: 685b ldr r3, [r3, #4] 800476c: f003 030c and.w r3, r3, #12 8004770: 2b04 cmp r3, #4 8004772: d00c beq.n 800478e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8004774: 4b8f ldr r3, [pc, #572] @ (80049b4 ) 8004776: 685b ldr r3, [r3, #4] 8004778: f003 030c and.w r3, r3, #12 800477c: 2b08 cmp r3, #8 800477e: d112 bne.n 80047a6 8004780: 4b8c ldr r3, [pc, #560] @ (80049b4 ) 8004782: 685b ldr r3, [r3, #4] 8004784: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004788: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800478c: d10b bne.n 80047a6 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800478e: 4b89 ldr r3, [pc, #548] @ (80049b4 ) 8004790: 681b ldr r3, [r3, #0] 8004792: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004796: 2b00 cmp r3, #0 8004798: d06c beq.n 8004874 800479a: 687b ldr r3, [r7, #4] 800479c: 685b ldr r3, [r3, #4] 800479e: 2b00 cmp r3, #0 80047a0: d168 bne.n 8004874 { return HAL_ERROR; 80047a2: 2301 movs r3, #1 80047a4: e24c b.n 8004c40 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80047a6: 687b ldr r3, [r7, #4] 80047a8: 685b ldr r3, [r3, #4] 80047aa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80047ae: d106 bne.n 80047be 80047b0: 4b80 ldr r3, [pc, #512] @ (80049b4 ) 80047b2: 681b ldr r3, [r3, #0] 80047b4: 4a7f ldr r2, [pc, #508] @ (80049b4 ) 80047b6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80047ba: 6013 str r3, [r2, #0] 80047bc: e02e b.n 800481c 80047be: 687b ldr r3, [r7, #4] 80047c0: 685b ldr r3, [r3, #4] 80047c2: 2b00 cmp r3, #0 80047c4: d10c bne.n 80047e0 80047c6: 4b7b ldr r3, [pc, #492] @ (80049b4 ) 80047c8: 681b ldr r3, [r3, #0] 80047ca: 4a7a ldr r2, [pc, #488] @ (80049b4 ) 80047cc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80047d0: 6013 str r3, [r2, #0] 80047d2: 4b78 ldr r3, [pc, #480] @ (80049b4 ) 80047d4: 681b ldr r3, [r3, #0] 80047d6: 4a77 ldr r2, [pc, #476] @ (80049b4 ) 80047d8: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80047dc: 6013 str r3, [r2, #0] 80047de: e01d b.n 800481c 80047e0: 687b ldr r3, [r7, #4] 80047e2: 685b ldr r3, [r3, #4] 80047e4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80047e8: d10c bne.n 8004804 80047ea: 4b72 ldr r3, [pc, #456] @ (80049b4 ) 80047ec: 681b ldr r3, [r3, #0] 80047ee: 4a71 ldr r2, [pc, #452] @ (80049b4 ) 80047f0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80047f4: 6013 str r3, [r2, #0] 80047f6: 4b6f ldr r3, [pc, #444] @ (80049b4 ) 80047f8: 681b ldr r3, [r3, #0] 80047fa: 4a6e ldr r2, [pc, #440] @ (80049b4 ) 80047fc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004800: 6013 str r3, [r2, #0] 8004802: e00b b.n 800481c 8004804: 4b6b ldr r3, [pc, #428] @ (80049b4 ) 8004806: 681b ldr r3, [r3, #0] 8004808: 4a6a ldr r2, [pc, #424] @ (80049b4 ) 800480a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800480e: 6013 str r3, [r2, #0] 8004810: 4b68 ldr r3, [pc, #416] @ (80049b4 ) 8004812: 681b ldr r3, [r3, #0] 8004814: 4a67 ldr r2, [pc, #412] @ (80049b4 ) 8004816: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800481a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800481c: 687b ldr r3, [r7, #4] 800481e: 685b ldr r3, [r3, #4] 8004820: 2b00 cmp r3, #0 8004822: d013 beq.n 800484c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004824: f7fe f990 bl 8002b48 8004828: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800482a: e008 b.n 800483e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800482c: f7fe f98c bl 8002b48 8004830: 4602 mov r2, r0 8004832: 693b ldr r3, [r7, #16] 8004834: 1ad3 subs r3, r2, r3 8004836: 2b64 cmp r3, #100 @ 0x64 8004838: d901 bls.n 800483e { return HAL_TIMEOUT; 800483a: 2303 movs r3, #3 800483c: e200 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800483e: 4b5d ldr r3, [pc, #372] @ (80049b4 ) 8004840: 681b ldr r3, [r3, #0] 8004842: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004846: 2b00 cmp r3, #0 8004848: d0f0 beq.n 800482c 800484a: e014 b.n 8004876 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800484c: f7fe f97c bl 8002b48 8004850: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004852: e008 b.n 8004866 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004854: f7fe f978 bl 8002b48 8004858: 4602 mov r2, r0 800485a: 693b ldr r3, [r7, #16] 800485c: 1ad3 subs r3, r2, r3 800485e: 2b64 cmp r3, #100 @ 0x64 8004860: d901 bls.n 8004866 { return HAL_TIMEOUT; 8004862: 2303 movs r3, #3 8004864: e1ec b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004866: 4b53 ldr r3, [pc, #332] @ (80049b4 ) 8004868: 681b ldr r3, [r3, #0] 800486a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800486e: 2b00 cmp r3, #0 8004870: d1f0 bne.n 8004854 8004872: e000 b.n 8004876 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004874: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004876: 687b ldr r3, [r7, #4] 8004878: 681b ldr r3, [r3, #0] 800487a: f003 0302 and.w r3, r3, #2 800487e: 2b00 cmp r3, #0 8004880: d063 beq.n 800494a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8004882: 4b4c ldr r3, [pc, #304] @ (80049b4 ) 8004884: 685b ldr r3, [r3, #4] 8004886: f003 030c and.w r3, r3, #12 800488a: 2b00 cmp r3, #0 800488c: d00b beq.n 80048a6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800488e: 4b49 ldr r3, [pc, #292] @ (80049b4 ) 8004890: 685b ldr r3, [r3, #4] 8004892: f003 030c and.w r3, r3, #12 8004896: 2b08 cmp r3, #8 8004898: d11c bne.n 80048d4 800489a: 4b46 ldr r3, [pc, #280] @ (80049b4 ) 800489c: 685b ldr r3, [r3, #4] 800489e: f403 3380 and.w r3, r3, #65536 @ 0x10000 80048a2: 2b00 cmp r3, #0 80048a4: d116 bne.n 80048d4 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80048a6: 4b43 ldr r3, [pc, #268] @ (80049b4 ) 80048a8: 681b ldr r3, [r3, #0] 80048aa: f003 0302 and.w r3, r3, #2 80048ae: 2b00 cmp r3, #0 80048b0: d005 beq.n 80048be 80048b2: 687b ldr r3, [r7, #4] 80048b4: 691b ldr r3, [r3, #16] 80048b6: 2b01 cmp r3, #1 80048b8: d001 beq.n 80048be { return HAL_ERROR; 80048ba: 2301 movs r3, #1 80048bc: e1c0 b.n 8004c40 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80048be: 4b3d ldr r3, [pc, #244] @ (80049b4 ) 80048c0: 681b ldr r3, [r3, #0] 80048c2: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80048c6: 687b ldr r3, [r7, #4] 80048c8: 695b ldr r3, [r3, #20] 80048ca: 00db lsls r3, r3, #3 80048cc: 4939 ldr r1, [pc, #228] @ (80049b4 ) 80048ce: 4313 orrs r3, r2 80048d0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80048d2: e03a b.n 800494a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80048d4: 687b ldr r3, [r7, #4] 80048d6: 691b ldr r3, [r3, #16] 80048d8: 2b00 cmp r3, #0 80048da: d020 beq.n 800491e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80048dc: 4b36 ldr r3, [pc, #216] @ (80049b8 ) 80048de: 2201 movs r2, #1 80048e0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80048e2: f7fe f931 bl 8002b48 80048e6: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80048e8: e008 b.n 80048fc { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80048ea: f7fe f92d bl 8002b48 80048ee: 4602 mov r2, r0 80048f0: 693b ldr r3, [r7, #16] 80048f2: 1ad3 subs r3, r2, r3 80048f4: 2b02 cmp r3, #2 80048f6: d901 bls.n 80048fc { return HAL_TIMEOUT; 80048f8: 2303 movs r3, #3 80048fa: e1a1 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80048fc: 4b2d ldr r3, [pc, #180] @ (80049b4 ) 80048fe: 681b ldr r3, [r3, #0] 8004900: f003 0302 and.w r3, r3, #2 8004904: 2b00 cmp r3, #0 8004906: d0f0 beq.n 80048ea } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004908: 4b2a ldr r3, [pc, #168] @ (80049b4 ) 800490a: 681b ldr r3, [r3, #0] 800490c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004910: 687b ldr r3, [r7, #4] 8004912: 695b ldr r3, [r3, #20] 8004914: 00db lsls r3, r3, #3 8004916: 4927 ldr r1, [pc, #156] @ (80049b4 ) 8004918: 4313 orrs r3, r2 800491a: 600b str r3, [r1, #0] 800491c: e015 b.n 800494a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800491e: 4b26 ldr r3, [pc, #152] @ (80049b8 ) 8004920: 2200 movs r2, #0 8004922: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004924: f7fe f910 bl 8002b48 8004928: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800492a: e008 b.n 800493e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800492c: f7fe f90c bl 8002b48 8004930: 4602 mov r2, r0 8004932: 693b ldr r3, [r7, #16] 8004934: 1ad3 subs r3, r2, r3 8004936: 2b02 cmp r3, #2 8004938: d901 bls.n 800493e { return HAL_TIMEOUT; 800493a: 2303 movs r3, #3 800493c: e180 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800493e: 4b1d ldr r3, [pc, #116] @ (80049b4 ) 8004940: 681b ldr r3, [r3, #0] 8004942: f003 0302 and.w r3, r3, #2 8004946: 2b00 cmp r3, #0 8004948: d1f0 bne.n 800492c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800494a: 687b ldr r3, [r7, #4] 800494c: 681b ldr r3, [r3, #0] 800494e: f003 0308 and.w r3, r3, #8 8004952: 2b00 cmp r3, #0 8004954: d03a beq.n 80049cc { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8004956: 687b ldr r3, [r7, #4] 8004958: 699b ldr r3, [r3, #24] 800495a: 2b00 cmp r3, #0 800495c: d019 beq.n 8004992 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800495e: 4b17 ldr r3, [pc, #92] @ (80049bc ) 8004960: 2201 movs r2, #1 8004962: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004964: f7fe f8f0 bl 8002b48 8004968: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800496a: e008 b.n 800497e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800496c: f7fe f8ec bl 8002b48 8004970: 4602 mov r2, r0 8004972: 693b ldr r3, [r7, #16] 8004974: 1ad3 subs r3, r2, r3 8004976: 2b02 cmp r3, #2 8004978: d901 bls.n 800497e { return HAL_TIMEOUT; 800497a: 2303 movs r3, #3 800497c: e160 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800497e: 4b0d ldr r3, [pc, #52] @ (80049b4 ) 8004980: 6a5b ldr r3, [r3, #36] @ 0x24 8004982: f003 0302 and.w r3, r3, #2 8004986: 2b00 cmp r3, #0 8004988: d0f0 beq.n 800496c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800498a: 2001 movs r0, #1 800498c: f000 fad0 bl 8004f30 8004990: e01c b.n 80049cc } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004992: 4b0a ldr r3, [pc, #40] @ (80049bc ) 8004994: 2200 movs r2, #0 8004996: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004998: f7fe f8d6 bl 8002b48 800499c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800499e: e00f b.n 80049c0 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80049a0: f7fe f8d2 bl 8002b48 80049a4: 4602 mov r2, r0 80049a6: 693b ldr r3, [r7, #16] 80049a8: 1ad3 subs r3, r2, r3 80049aa: 2b02 cmp r3, #2 80049ac: d908 bls.n 80049c0 { return HAL_TIMEOUT; 80049ae: 2303 movs r3, #3 80049b0: e146 b.n 8004c40 80049b2: bf00 nop 80049b4: 40021000 .word 0x40021000 80049b8: 42420000 .word 0x42420000 80049bc: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80049c0: 4b92 ldr r3, [pc, #584] @ (8004c0c ) 80049c2: 6a5b ldr r3, [r3, #36] @ 0x24 80049c4: f003 0302 and.w r3, r3, #2 80049c8: 2b00 cmp r3, #0 80049ca: d1e9 bne.n 80049a0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80049cc: 687b ldr r3, [r7, #4] 80049ce: 681b ldr r3, [r3, #0] 80049d0: f003 0304 and.w r3, r3, #4 80049d4: 2b00 cmp r3, #0 80049d6: f000 80a6 beq.w 8004b26 { FlagStatus pwrclkchanged = RESET; 80049da: 2300 movs r3, #0 80049dc: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80049de: 4b8b ldr r3, [pc, #556] @ (8004c0c ) 80049e0: 69db ldr r3, [r3, #28] 80049e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80049e6: 2b00 cmp r3, #0 80049e8: d10d bne.n 8004a06 { __HAL_RCC_PWR_CLK_ENABLE(); 80049ea: 4b88 ldr r3, [pc, #544] @ (8004c0c ) 80049ec: 69db ldr r3, [r3, #28] 80049ee: 4a87 ldr r2, [pc, #540] @ (8004c0c ) 80049f0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80049f4: 61d3 str r3, [r2, #28] 80049f6: 4b85 ldr r3, [pc, #532] @ (8004c0c ) 80049f8: 69db ldr r3, [r3, #28] 80049fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80049fe: 60bb str r3, [r7, #8] 8004a00: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004a02: 2301 movs r3, #1 8004a04: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004a06: 4b82 ldr r3, [pc, #520] @ (8004c10 ) 8004a08: 681b ldr r3, [r3, #0] 8004a0a: f403 7380 and.w r3, r3, #256 @ 0x100 8004a0e: 2b00 cmp r3, #0 8004a10: d118 bne.n 8004a44 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004a12: 4b7f ldr r3, [pc, #508] @ (8004c10 ) 8004a14: 681b ldr r3, [r3, #0] 8004a16: 4a7e ldr r2, [pc, #504] @ (8004c10 ) 8004a18: f443 7380 orr.w r3, r3, #256 @ 0x100 8004a1c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004a1e: f7fe f893 bl 8002b48 8004a22: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004a24: e008 b.n 8004a38 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004a26: f7fe f88f bl 8002b48 8004a2a: 4602 mov r2, r0 8004a2c: 693b ldr r3, [r7, #16] 8004a2e: 1ad3 subs r3, r2, r3 8004a30: 2b64 cmp r3, #100 @ 0x64 8004a32: d901 bls.n 8004a38 { return HAL_TIMEOUT; 8004a34: 2303 movs r3, #3 8004a36: e103 b.n 8004c40 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004a38: 4b75 ldr r3, [pc, #468] @ (8004c10 ) 8004a3a: 681b ldr r3, [r3, #0] 8004a3c: f403 7380 and.w r3, r3, #256 @ 0x100 8004a40: 2b00 cmp r3, #0 8004a42: d0f0 beq.n 8004a26 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004a44: 687b ldr r3, [r7, #4] 8004a46: 68db ldr r3, [r3, #12] 8004a48: 2b01 cmp r3, #1 8004a4a: d106 bne.n 8004a5a 8004a4c: 4b6f ldr r3, [pc, #444] @ (8004c0c ) 8004a4e: 6a1b ldr r3, [r3, #32] 8004a50: 4a6e ldr r2, [pc, #440] @ (8004c0c ) 8004a52: f043 0301 orr.w r3, r3, #1 8004a56: 6213 str r3, [r2, #32] 8004a58: e02d b.n 8004ab6 8004a5a: 687b ldr r3, [r7, #4] 8004a5c: 68db ldr r3, [r3, #12] 8004a5e: 2b00 cmp r3, #0 8004a60: d10c bne.n 8004a7c 8004a62: 4b6a ldr r3, [pc, #424] @ (8004c0c ) 8004a64: 6a1b ldr r3, [r3, #32] 8004a66: 4a69 ldr r2, [pc, #420] @ (8004c0c ) 8004a68: f023 0301 bic.w r3, r3, #1 8004a6c: 6213 str r3, [r2, #32] 8004a6e: 4b67 ldr r3, [pc, #412] @ (8004c0c ) 8004a70: 6a1b ldr r3, [r3, #32] 8004a72: 4a66 ldr r2, [pc, #408] @ (8004c0c ) 8004a74: f023 0304 bic.w r3, r3, #4 8004a78: 6213 str r3, [r2, #32] 8004a7a: e01c b.n 8004ab6 8004a7c: 687b ldr r3, [r7, #4] 8004a7e: 68db ldr r3, [r3, #12] 8004a80: 2b05 cmp r3, #5 8004a82: d10c bne.n 8004a9e 8004a84: 4b61 ldr r3, [pc, #388] @ (8004c0c ) 8004a86: 6a1b ldr r3, [r3, #32] 8004a88: 4a60 ldr r2, [pc, #384] @ (8004c0c ) 8004a8a: f043 0304 orr.w r3, r3, #4 8004a8e: 6213 str r3, [r2, #32] 8004a90: 4b5e ldr r3, [pc, #376] @ (8004c0c ) 8004a92: 6a1b ldr r3, [r3, #32] 8004a94: 4a5d ldr r2, [pc, #372] @ (8004c0c ) 8004a96: f043 0301 orr.w r3, r3, #1 8004a9a: 6213 str r3, [r2, #32] 8004a9c: e00b b.n 8004ab6 8004a9e: 4b5b ldr r3, [pc, #364] @ (8004c0c ) 8004aa0: 6a1b ldr r3, [r3, #32] 8004aa2: 4a5a ldr r2, [pc, #360] @ (8004c0c ) 8004aa4: f023 0301 bic.w r3, r3, #1 8004aa8: 6213 str r3, [r2, #32] 8004aaa: 4b58 ldr r3, [pc, #352] @ (8004c0c ) 8004aac: 6a1b ldr r3, [r3, #32] 8004aae: 4a57 ldr r2, [pc, #348] @ (8004c0c ) 8004ab0: f023 0304 bic.w r3, r3, #4 8004ab4: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8004ab6: 687b ldr r3, [r7, #4] 8004ab8: 68db ldr r3, [r3, #12] 8004aba: 2b00 cmp r3, #0 8004abc: d015 beq.n 8004aea { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004abe: f7fe f843 bl 8002b48 8004ac2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004ac4: e00a b.n 8004adc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004ac6: f7fe f83f bl 8002b48 8004aca: 4602 mov r2, r0 8004acc: 693b ldr r3, [r7, #16] 8004ace: 1ad3 subs r3, r2, r3 8004ad0: f241 3288 movw r2, #5000 @ 0x1388 8004ad4: 4293 cmp r3, r2 8004ad6: d901 bls.n 8004adc { return HAL_TIMEOUT; 8004ad8: 2303 movs r3, #3 8004ada: e0b1 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004adc: 4b4b ldr r3, [pc, #300] @ (8004c0c ) 8004ade: 6a1b ldr r3, [r3, #32] 8004ae0: f003 0302 and.w r3, r3, #2 8004ae4: 2b00 cmp r3, #0 8004ae6: d0ee beq.n 8004ac6 8004ae8: e014 b.n 8004b14 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004aea: f7fe f82d bl 8002b48 8004aee: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004af0: e00a b.n 8004b08 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004af2: f7fe f829 bl 8002b48 8004af6: 4602 mov r2, r0 8004af8: 693b ldr r3, [r7, #16] 8004afa: 1ad3 subs r3, r2, r3 8004afc: f241 3288 movw r2, #5000 @ 0x1388 8004b00: 4293 cmp r3, r2 8004b02: d901 bls.n 8004b08 { return HAL_TIMEOUT; 8004b04: 2303 movs r3, #3 8004b06: e09b b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004b08: 4b40 ldr r3, [pc, #256] @ (8004c0c ) 8004b0a: 6a1b ldr r3, [r3, #32] 8004b0c: f003 0302 and.w r3, r3, #2 8004b10: 2b00 cmp r3, #0 8004b12: d1ee bne.n 8004af2 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8004b14: 7dfb ldrb r3, [r7, #23] 8004b16: 2b01 cmp r3, #1 8004b18: d105 bne.n 8004b26 { __HAL_RCC_PWR_CLK_DISABLE(); 8004b1a: 4b3c ldr r3, [pc, #240] @ (8004c0c ) 8004b1c: 69db ldr r3, [r3, #28] 8004b1e: 4a3b ldr r2, [pc, #236] @ (8004c0c ) 8004b20: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8004b24: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8004b26: 687b ldr r3, [r7, #4] 8004b28: 69db ldr r3, [r3, #28] 8004b2a: 2b00 cmp r3, #0 8004b2c: f000 8087 beq.w 8004c3e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8004b30: 4b36 ldr r3, [pc, #216] @ (8004c0c ) 8004b32: 685b ldr r3, [r3, #4] 8004b34: f003 030c and.w r3, r3, #12 8004b38: 2b08 cmp r3, #8 8004b3a: d061 beq.n 8004c00 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004b3c: 687b ldr r3, [r7, #4] 8004b3e: 69db ldr r3, [r3, #28] 8004b40: 2b02 cmp r3, #2 8004b42: d146 bne.n 8004bd2 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8004b44: 4b33 ldr r3, [pc, #204] @ (8004c14 ) 8004b46: 2200 movs r2, #0 8004b48: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004b4a: f7fd fffd bl 8002b48 8004b4e: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004b50: e008 b.n 8004b64 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004b52: f7fd fff9 bl 8002b48 8004b56: 4602 mov r2, r0 8004b58: 693b ldr r3, [r7, #16] 8004b5a: 1ad3 subs r3, r2, r3 8004b5c: 2b02 cmp r3, #2 8004b5e: d901 bls.n 8004b64 { return HAL_TIMEOUT; 8004b60: 2303 movs r3, #3 8004b62: e06d b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004b64: 4b29 ldr r3, [pc, #164] @ (8004c0c ) 8004b66: 681b ldr r3, [r3, #0] 8004b68: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004b6c: 2b00 cmp r3, #0 8004b6e: d1f0 bne.n 8004b52 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8004b70: 687b ldr r3, [r7, #4] 8004b72: 6a1b ldr r3, [r3, #32] 8004b74: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004b78: d108 bne.n 8004b8c /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8004b7a: 4b24 ldr r3, [pc, #144] @ (8004c0c ) 8004b7c: 685b ldr r3, [r3, #4] 8004b7e: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8004b82: 687b ldr r3, [r7, #4] 8004b84: 689b ldr r3, [r3, #8] 8004b86: 4921 ldr r1, [pc, #132] @ (8004c0c ) 8004b88: 4313 orrs r3, r2 8004b8a: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8004b8c: 4b1f ldr r3, [pc, #124] @ (8004c0c ) 8004b8e: 685b ldr r3, [r3, #4] 8004b90: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8004b94: 687b ldr r3, [r7, #4] 8004b96: 6a19 ldr r1, [r3, #32] 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 6a5b ldr r3, [r3, #36] @ 0x24 8004b9c: 430b orrs r3, r1 8004b9e: 491b ldr r1, [pc, #108] @ (8004c0c ) 8004ba0: 4313 orrs r3, r2 8004ba2: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8004ba4: 4b1b ldr r3, [pc, #108] @ (8004c14 ) 8004ba6: 2201 movs r2, #1 8004ba8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004baa: f7fd ffcd bl 8002b48 8004bae: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004bb0: e008 b.n 8004bc4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004bb2: f7fd ffc9 bl 8002b48 8004bb6: 4602 mov r2, r0 8004bb8: 693b ldr r3, [r7, #16] 8004bba: 1ad3 subs r3, r2, r3 8004bbc: 2b02 cmp r3, #2 8004bbe: d901 bls.n 8004bc4 { return HAL_TIMEOUT; 8004bc0: 2303 movs r3, #3 8004bc2: e03d b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004bc4: 4b11 ldr r3, [pc, #68] @ (8004c0c ) 8004bc6: 681b ldr r3, [r3, #0] 8004bc8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004bcc: 2b00 cmp r3, #0 8004bce: d0f0 beq.n 8004bb2 8004bd0: e035 b.n 8004c3e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8004bd2: 4b10 ldr r3, [pc, #64] @ (8004c14 ) 8004bd4: 2200 movs r2, #0 8004bd6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004bd8: f7fd ffb6 bl 8002b48 8004bdc: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004bde: e008 b.n 8004bf2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004be0: f7fd ffb2 bl 8002b48 8004be4: 4602 mov r2, r0 8004be6: 693b ldr r3, [r7, #16] 8004be8: 1ad3 subs r3, r2, r3 8004bea: 2b02 cmp r3, #2 8004bec: d901 bls.n 8004bf2 { return HAL_TIMEOUT; 8004bee: 2303 movs r3, #3 8004bf0: e026 b.n 8004c40 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004bf2: 4b06 ldr r3, [pc, #24] @ (8004c0c ) 8004bf4: 681b ldr r3, [r3, #0] 8004bf6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004bfa: 2b00 cmp r3, #0 8004bfc: d1f0 bne.n 8004be0 8004bfe: e01e b.n 8004c3e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8004c00: 687b ldr r3, [r7, #4] 8004c02: 69db ldr r3, [r3, #28] 8004c04: 2b01 cmp r3, #1 8004c06: d107 bne.n 8004c18 { return HAL_ERROR; 8004c08: 2301 movs r3, #1 8004c0a: e019 b.n 8004c40 8004c0c: 40021000 .word 0x40021000 8004c10: 40007000 .word 0x40007000 8004c14: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8004c18: 4b0b ldr r3, [pc, #44] @ (8004c48 ) 8004c1a: 685b ldr r3, [r3, #4] 8004c1c: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004c1e: 68fb ldr r3, [r7, #12] 8004c20: f403 3280 and.w r2, r3, #65536 @ 0x10000 8004c24: 687b ldr r3, [r7, #4] 8004c26: 6a1b ldr r3, [r3, #32] 8004c28: 429a cmp r2, r3 8004c2a: d106 bne.n 8004c3a (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8004c2c: 68fb ldr r3, [r7, #12] 8004c2e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8004c32: 687b ldr r3, [r7, #4] 8004c34: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004c36: 429a cmp r2, r3 8004c38: d001 beq.n 8004c3e { return HAL_ERROR; 8004c3a: 2301 movs r3, #1 8004c3c: e000 b.n 8004c40 } } } } return HAL_OK; 8004c3e: 2300 movs r3, #0 } 8004c40: 4618 mov r0, r3 8004c42: 3718 adds r7, #24 8004c44: 46bd mov sp, r7 8004c46: bd80 pop {r7, pc} 8004c48: 40021000 .word 0x40021000 08004c4c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004c4c: b580 push {r7, lr} 8004c4e: b084 sub sp, #16 8004c50: af00 add r7, sp, #0 8004c52: 6078 str r0, [r7, #4] 8004c54: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8004c56: 687b ldr r3, [r7, #4] 8004c58: 2b00 cmp r3, #0 8004c5a: d101 bne.n 8004c60 { return HAL_ERROR; 8004c5c: 2301 movs r3, #1 8004c5e: e0d0 b.n 8004e02 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004c60: 4b6a ldr r3, [pc, #424] @ (8004e0c ) 8004c62: 681b ldr r3, [r3, #0] 8004c64: f003 0307 and.w r3, r3, #7 8004c68: 683a ldr r2, [r7, #0] 8004c6a: 429a cmp r2, r3 8004c6c: d910 bls.n 8004c90 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004c6e: 4b67 ldr r3, [pc, #412] @ (8004e0c ) 8004c70: 681b ldr r3, [r3, #0] 8004c72: f023 0207 bic.w r2, r3, #7 8004c76: 4965 ldr r1, [pc, #404] @ (8004e0c ) 8004c78: 683b ldr r3, [r7, #0] 8004c7a: 4313 orrs r3, r2 8004c7c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004c7e: 4b63 ldr r3, [pc, #396] @ (8004e0c ) 8004c80: 681b ldr r3, [r3, #0] 8004c82: f003 0307 and.w r3, r3, #7 8004c86: 683a ldr r2, [r7, #0] 8004c88: 429a cmp r2, r3 8004c8a: d001 beq.n 8004c90 { return HAL_ERROR; 8004c8c: 2301 movs r3, #1 8004c8e: e0b8 b.n 8004e02 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004c90: 687b ldr r3, [r7, #4] 8004c92: 681b ldr r3, [r3, #0] 8004c94: f003 0302 and.w r3, r3, #2 8004c98: 2b00 cmp r3, #0 8004c9a: d020 beq.n 8004cde { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004c9c: 687b ldr r3, [r7, #4] 8004c9e: 681b ldr r3, [r3, #0] 8004ca0: f003 0304 and.w r3, r3, #4 8004ca4: 2b00 cmp r3, #0 8004ca6: d005 beq.n 8004cb4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004ca8: 4b59 ldr r3, [pc, #356] @ (8004e10 ) 8004caa: 685b ldr r3, [r3, #4] 8004cac: 4a58 ldr r2, [pc, #352] @ (8004e10 ) 8004cae: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8004cb2: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004cb4: 687b ldr r3, [r7, #4] 8004cb6: 681b ldr r3, [r3, #0] 8004cb8: f003 0308 and.w r3, r3, #8 8004cbc: 2b00 cmp r3, #0 8004cbe: d005 beq.n 8004ccc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004cc0: 4b53 ldr r3, [pc, #332] @ (8004e10 ) 8004cc2: 685b ldr r3, [r3, #4] 8004cc4: 4a52 ldr r2, [pc, #328] @ (8004e10 ) 8004cc6: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8004cca: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004ccc: 4b50 ldr r3, [pc, #320] @ (8004e10 ) 8004cce: 685b ldr r3, [r3, #4] 8004cd0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004cd4: 687b ldr r3, [r7, #4] 8004cd6: 689b ldr r3, [r3, #8] 8004cd8: 494d ldr r1, [pc, #308] @ (8004e10 ) 8004cda: 4313 orrs r3, r2 8004cdc: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004cde: 687b ldr r3, [r7, #4] 8004ce0: 681b ldr r3, [r3, #0] 8004ce2: f003 0301 and.w r3, r3, #1 8004ce6: 2b00 cmp r3, #0 8004ce8: d040 beq.n 8004d6c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004cea: 687b ldr r3, [r7, #4] 8004cec: 685b ldr r3, [r3, #4] 8004cee: 2b01 cmp r3, #1 8004cf0: d107 bne.n 8004d02 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004cf2: 4b47 ldr r3, [pc, #284] @ (8004e10 ) 8004cf4: 681b ldr r3, [r3, #0] 8004cf6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004cfa: 2b00 cmp r3, #0 8004cfc: d115 bne.n 8004d2a { return HAL_ERROR; 8004cfe: 2301 movs r3, #1 8004d00: e07f b.n 8004e02 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8004d02: 687b ldr r3, [r7, #4] 8004d04: 685b ldr r3, [r3, #4] 8004d06: 2b02 cmp r3, #2 8004d08: d107 bne.n 8004d1a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004d0a: 4b41 ldr r3, [pc, #260] @ (8004e10 ) 8004d0c: 681b ldr r3, [r3, #0] 8004d0e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004d12: 2b00 cmp r3, #0 8004d14: d109 bne.n 8004d2a { return HAL_ERROR; 8004d16: 2301 movs r3, #1 8004d18: e073 b.n 8004e02 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004d1a: 4b3d ldr r3, [pc, #244] @ (8004e10 ) 8004d1c: 681b ldr r3, [r3, #0] 8004d1e: f003 0302 and.w r3, r3, #2 8004d22: 2b00 cmp r3, #0 8004d24: d101 bne.n 8004d2a { return HAL_ERROR; 8004d26: 2301 movs r3, #1 8004d28: e06b b.n 8004e02 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004d2a: 4b39 ldr r3, [pc, #228] @ (8004e10 ) 8004d2c: 685b ldr r3, [r3, #4] 8004d2e: f023 0203 bic.w r2, r3, #3 8004d32: 687b ldr r3, [r7, #4] 8004d34: 685b ldr r3, [r3, #4] 8004d36: 4936 ldr r1, [pc, #216] @ (8004e10 ) 8004d38: 4313 orrs r3, r2 8004d3a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004d3c: f7fd ff04 bl 8002b48 8004d40: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004d42: e00a b.n 8004d5a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004d44: f7fd ff00 bl 8002b48 8004d48: 4602 mov r2, r0 8004d4a: 68fb ldr r3, [r7, #12] 8004d4c: 1ad3 subs r3, r2, r3 8004d4e: f241 3288 movw r2, #5000 @ 0x1388 8004d52: 4293 cmp r3, r2 8004d54: d901 bls.n 8004d5a { return HAL_TIMEOUT; 8004d56: 2303 movs r3, #3 8004d58: e053 b.n 8004e02 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004d5a: 4b2d ldr r3, [pc, #180] @ (8004e10 ) 8004d5c: 685b ldr r3, [r3, #4] 8004d5e: f003 020c and.w r2, r3, #12 8004d62: 687b ldr r3, [r7, #4] 8004d64: 685b ldr r3, [r3, #4] 8004d66: 009b lsls r3, r3, #2 8004d68: 429a cmp r2, r3 8004d6a: d1eb bne.n 8004d44 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004d6c: 4b27 ldr r3, [pc, #156] @ (8004e0c ) 8004d6e: 681b ldr r3, [r3, #0] 8004d70: f003 0307 and.w r3, r3, #7 8004d74: 683a ldr r2, [r7, #0] 8004d76: 429a cmp r2, r3 8004d78: d210 bcs.n 8004d9c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004d7a: 4b24 ldr r3, [pc, #144] @ (8004e0c ) 8004d7c: 681b ldr r3, [r3, #0] 8004d7e: f023 0207 bic.w r2, r3, #7 8004d82: 4922 ldr r1, [pc, #136] @ (8004e0c ) 8004d84: 683b ldr r3, [r7, #0] 8004d86: 4313 orrs r3, r2 8004d88: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004d8a: 4b20 ldr r3, [pc, #128] @ (8004e0c ) 8004d8c: 681b ldr r3, [r3, #0] 8004d8e: f003 0307 and.w r3, r3, #7 8004d92: 683a ldr r2, [r7, #0] 8004d94: 429a cmp r2, r3 8004d96: d001 beq.n 8004d9c { return HAL_ERROR; 8004d98: 2301 movs r3, #1 8004d9a: e032 b.n 8004e02 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004d9c: 687b ldr r3, [r7, #4] 8004d9e: 681b ldr r3, [r3, #0] 8004da0: f003 0304 and.w r3, r3, #4 8004da4: 2b00 cmp r3, #0 8004da6: d008 beq.n 8004dba { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004da8: 4b19 ldr r3, [pc, #100] @ (8004e10 ) 8004daa: 685b ldr r3, [r3, #4] 8004dac: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8004db0: 687b ldr r3, [r7, #4] 8004db2: 68db ldr r3, [r3, #12] 8004db4: 4916 ldr r1, [pc, #88] @ (8004e10 ) 8004db6: 4313 orrs r3, r2 8004db8: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004dba: 687b ldr r3, [r7, #4] 8004dbc: 681b ldr r3, [r3, #0] 8004dbe: f003 0308 and.w r3, r3, #8 8004dc2: 2b00 cmp r3, #0 8004dc4: d009 beq.n 8004dda { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8004dc6: 4b12 ldr r3, [pc, #72] @ (8004e10 ) 8004dc8: 685b ldr r3, [r3, #4] 8004dca: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8004dce: 687b ldr r3, [r7, #4] 8004dd0: 691b ldr r3, [r3, #16] 8004dd2: 00db lsls r3, r3, #3 8004dd4: 490e ldr r1, [pc, #56] @ (8004e10 ) 8004dd6: 4313 orrs r3, r2 8004dd8: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004dda: f000 f821 bl 8004e20 8004dde: 4602 mov r2, r0 8004de0: 4b0b ldr r3, [pc, #44] @ (8004e10 ) 8004de2: 685b ldr r3, [r3, #4] 8004de4: 091b lsrs r3, r3, #4 8004de6: f003 030f and.w r3, r3, #15 8004dea: 490a ldr r1, [pc, #40] @ (8004e14 ) 8004dec: 5ccb ldrb r3, [r1, r3] 8004dee: fa22 f303 lsr.w r3, r2, r3 8004df2: 4a09 ldr r2, [pc, #36] @ (8004e18 ) 8004df4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8004df6: 4b09 ldr r3, [pc, #36] @ (8004e1c ) 8004df8: 681b ldr r3, [r3, #0] 8004dfa: 4618 mov r0, r3 8004dfc: f7fd fe62 bl 8002ac4 return HAL_OK; 8004e00: 2300 movs r3, #0 } 8004e02: 4618 mov r0, r3 8004e04: 3710 adds r7, #16 8004e06: 46bd mov sp, r7 8004e08: bd80 pop {r7, pc} 8004e0a: bf00 nop 8004e0c: 40022000 .word 0x40022000 8004e10: 40021000 .word 0x40021000 8004e14: 08005f34 .word 0x08005f34 8004e18: 2000001c .word 0x2000001c 8004e1c: 20000020 .word 0x20000020 08004e20 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004e20: b480 push {r7} 8004e22: b087 sub sp, #28 8004e24: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8004e26: 2300 movs r3, #0 8004e28: 60fb str r3, [r7, #12] 8004e2a: 2300 movs r3, #0 8004e2c: 60bb str r3, [r7, #8] 8004e2e: 2300 movs r3, #0 8004e30: 617b str r3, [r7, #20] 8004e32: 2300 movs r3, #0 8004e34: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 8004e36: 2300 movs r3, #0 8004e38: 613b str r3, [r7, #16] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8004e3a: 4b1e ldr r3, [pc, #120] @ (8004eb4 ) 8004e3c: 685b ldr r3, [r3, #4] 8004e3e: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8004e40: 68fb ldr r3, [r7, #12] 8004e42: f003 030c and.w r3, r3, #12 8004e46: 2b04 cmp r3, #4 8004e48: d002 beq.n 8004e50 8004e4a: 2b08 cmp r3, #8 8004e4c: d003 beq.n 8004e56 8004e4e: e027 b.n 8004ea0 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8004e50: 4b19 ldr r3, [pc, #100] @ (8004eb8 ) 8004e52: 613b str r3, [r7, #16] break; 8004e54: e027 b.n 8004ea6 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8004e56: 68fb ldr r3, [r7, #12] 8004e58: 0c9b lsrs r3, r3, #18 8004e5a: f003 030f and.w r3, r3, #15 8004e5e: 4a17 ldr r2, [pc, #92] @ (8004ebc ) 8004e60: 5cd3 ldrb r3, [r2, r3] 8004e62: 607b str r3, [r7, #4] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8004e64: 68fb ldr r3, [r7, #12] 8004e66: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004e6a: 2b00 cmp r3, #0 8004e6c: d010 beq.n 8004e90 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004e6e: 4b11 ldr r3, [pc, #68] @ (8004eb4 ) 8004e70: 685b ldr r3, [r3, #4] 8004e72: 0c5b lsrs r3, r3, #17 8004e74: f003 0301 and.w r3, r3, #1 8004e78: 4a11 ldr r2, [pc, #68] @ (8004ec0 ) 8004e7a: 5cd3 ldrb r3, [r2, r3] 8004e7c: 60bb str r3, [r7, #8] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8004e7e: 687b ldr r3, [r7, #4] 8004e80: 4a0d ldr r2, [pc, #52] @ (8004eb8 ) 8004e82: fb03 f202 mul.w r2, r3, r2 8004e86: 68bb ldr r3, [r7, #8] 8004e88: fbb2 f3f3 udiv r3, r2, r3 8004e8c: 617b str r3, [r7, #20] 8004e8e: e004 b.n 8004e9a #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8004e90: 687b ldr r3, [r7, #4] 8004e92: 4a0c ldr r2, [pc, #48] @ (8004ec4 ) 8004e94: fb02 f303 mul.w r3, r2, r3 8004e98: 617b str r3, [r7, #20] } sysclockfreq = pllclk; 8004e9a: 697b ldr r3, [r7, #20] 8004e9c: 613b str r3, [r7, #16] break; 8004e9e: e002 b.n 8004ea6 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8004ea0: 4b09 ldr r3, [pc, #36] @ (8004ec8 ) 8004ea2: 613b str r3, [r7, #16] break; 8004ea4: bf00 nop } } return sysclockfreq; 8004ea6: 693b ldr r3, [r7, #16] } 8004ea8: 4618 mov r0, r3 8004eaa: 371c adds r7, #28 8004eac: 46bd mov sp, r7 8004eae: bc80 pop {r7} 8004eb0: 4770 bx lr 8004eb2: bf00 nop 8004eb4: 40021000 .word 0x40021000 8004eb8: 00b71b00 .word 0x00b71b00 8004ebc: 08005f4c .word 0x08005f4c 8004ec0: 08005f5c .word 0x08005f5c 8004ec4: 003d0900 .word 0x003d0900 8004ec8: 007a1200 .word 0x007a1200 08004ecc : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8004ecc: b480 push {r7} 8004ece: af00 add r7, sp, #0 return SystemCoreClock; 8004ed0: 4b02 ldr r3, [pc, #8] @ (8004edc ) 8004ed2: 681b ldr r3, [r3, #0] } 8004ed4: 4618 mov r0, r3 8004ed6: 46bd mov sp, r7 8004ed8: bc80 pop {r7} 8004eda: 4770 bx lr 8004edc: 2000001c .word 0x2000001c 08004ee0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004ee0: b580 push {r7, lr} 8004ee2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004ee4: f7ff fff2 bl 8004ecc 8004ee8: 4602 mov r2, r0 8004eea: 4b05 ldr r3, [pc, #20] @ (8004f00 ) 8004eec: 685b ldr r3, [r3, #4] 8004eee: 0a1b lsrs r3, r3, #8 8004ef0: f003 0307 and.w r3, r3, #7 8004ef4: 4903 ldr r1, [pc, #12] @ (8004f04 ) 8004ef6: 5ccb ldrb r3, [r1, r3] 8004ef8: fa22 f303 lsr.w r3, r2, r3 } 8004efc: 4618 mov r0, r3 8004efe: bd80 pop {r7, pc} 8004f00: 40021000 .word 0x40021000 8004f04: 08005f44 .word 0x08005f44 08004f08 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004f08: b580 push {r7, lr} 8004f0a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004f0c: f7ff ffde bl 8004ecc 8004f10: 4602 mov r2, r0 8004f12: 4b05 ldr r3, [pc, #20] @ (8004f28 ) 8004f14: 685b ldr r3, [r3, #4] 8004f16: 0adb lsrs r3, r3, #11 8004f18: f003 0307 and.w r3, r3, #7 8004f1c: 4903 ldr r1, [pc, #12] @ (8004f2c ) 8004f1e: 5ccb ldrb r3, [r1, r3] 8004f20: fa22 f303 lsr.w r3, r2, r3 } 8004f24: 4618 mov r0, r3 8004f26: bd80 pop {r7, pc} 8004f28: 40021000 .word 0x40021000 8004f2c: 08005f44 .word 0x08005f44 08004f30 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8004f30: b480 push {r7} 8004f32: b085 sub sp, #20 8004f34: af00 add r7, sp, #0 8004f36: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8004f38: 4b0a ldr r3, [pc, #40] @ (8004f64 ) 8004f3a: 681b ldr r3, [r3, #0] 8004f3c: 4a0a ldr r2, [pc, #40] @ (8004f68 ) 8004f3e: fba2 2303 umull r2, r3, r2, r3 8004f42: 0a5b lsrs r3, r3, #9 8004f44: 687a ldr r2, [r7, #4] 8004f46: fb02 f303 mul.w r3, r2, r3 8004f4a: 60fb str r3, [r7, #12] do { __NOP(); 8004f4c: bf00 nop } while (Delay --); 8004f4e: 68fb ldr r3, [r7, #12] 8004f50: 1e5a subs r2, r3, #1 8004f52: 60fa str r2, [r7, #12] 8004f54: 2b00 cmp r3, #0 8004f56: d1f9 bne.n 8004f4c } 8004f58: bf00 nop 8004f5a: bf00 nop 8004f5c: 3714 adds r7, #20 8004f5e: 46bd mov sp, r7 8004f60: bc80 pop {r7} 8004f62: 4770 bx lr 8004f64: 2000001c .word 0x2000001c 8004f68: 10624dd3 .word 0x10624dd3 08004f6c : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004f6c: b580 push {r7, lr} 8004f6e: b086 sub sp, #24 8004f70: af00 add r7, sp, #0 8004f72: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8004f74: 2300 movs r3, #0 8004f76: 613b str r3, [r7, #16] 8004f78: 2300 movs r3, #0 8004f7a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8004f7c: 687b ldr r3, [r7, #4] 8004f7e: 681b ldr r3, [r3, #0] 8004f80: f003 0301 and.w r3, r3, #1 8004f84: 2b00 cmp r3, #0 8004f86: d07d beq.n 8005084 { FlagStatus pwrclkchanged = RESET; 8004f88: 2300 movs r3, #0 8004f8a: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004f8c: 4b4f ldr r3, [pc, #316] @ (80050cc ) 8004f8e: 69db ldr r3, [r3, #28] 8004f90: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004f94: 2b00 cmp r3, #0 8004f96: d10d bne.n 8004fb4 { __HAL_RCC_PWR_CLK_ENABLE(); 8004f98: 4b4c ldr r3, [pc, #304] @ (80050cc ) 8004f9a: 69db ldr r3, [r3, #28] 8004f9c: 4a4b ldr r2, [pc, #300] @ (80050cc ) 8004f9e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004fa2: 61d3 str r3, [r2, #28] 8004fa4: 4b49 ldr r3, [pc, #292] @ (80050cc ) 8004fa6: 69db ldr r3, [r3, #28] 8004fa8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004fac: 60bb str r3, [r7, #8] 8004fae: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004fb0: 2301 movs r3, #1 8004fb2: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fb4: 4b46 ldr r3, [pc, #280] @ (80050d0 ) 8004fb6: 681b ldr r3, [r3, #0] 8004fb8: f403 7380 and.w r3, r3, #256 @ 0x100 8004fbc: 2b00 cmp r3, #0 8004fbe: d118 bne.n 8004ff2 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004fc0: 4b43 ldr r3, [pc, #268] @ (80050d0 ) 8004fc2: 681b ldr r3, [r3, #0] 8004fc4: 4a42 ldr r2, [pc, #264] @ (80050d0 ) 8004fc6: f443 7380 orr.w r3, r3, #256 @ 0x100 8004fca: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004fcc: f7fd fdbc bl 8002b48 8004fd0: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fd2: e008 b.n 8004fe6 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004fd4: f7fd fdb8 bl 8002b48 8004fd8: 4602 mov r2, r0 8004fda: 693b ldr r3, [r7, #16] 8004fdc: 1ad3 subs r3, r2, r3 8004fde: 2b64 cmp r3, #100 @ 0x64 8004fe0: d901 bls.n 8004fe6 { return HAL_TIMEOUT; 8004fe2: 2303 movs r3, #3 8004fe4: e06d b.n 80050c2 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fe6: 4b3a ldr r3, [pc, #232] @ (80050d0 ) 8004fe8: 681b ldr r3, [r3, #0] 8004fea: f403 7380 and.w r3, r3, #256 @ 0x100 8004fee: 2b00 cmp r3, #0 8004ff0: d0f0 beq.n 8004fd4 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8004ff2: 4b36 ldr r3, [pc, #216] @ (80050cc ) 8004ff4: 6a1b ldr r3, [r3, #32] 8004ff6: f403 7340 and.w r3, r3, #768 @ 0x300 8004ffa: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8004ffc: 68fb ldr r3, [r7, #12] 8004ffe: 2b00 cmp r3, #0 8005000: d02e beq.n 8005060 8005002: 687b ldr r3, [r7, #4] 8005004: 685b ldr r3, [r3, #4] 8005006: f403 7340 and.w r3, r3, #768 @ 0x300 800500a: 68fa ldr r2, [r7, #12] 800500c: 429a cmp r2, r3 800500e: d027 beq.n 8005060 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8005010: 4b2e ldr r3, [pc, #184] @ (80050cc ) 8005012: 6a1b ldr r3, [r3, #32] 8005014: f423 7340 bic.w r3, r3, #768 @ 0x300 8005018: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800501a: 4b2e ldr r3, [pc, #184] @ (80050d4 ) 800501c: 2201 movs r2, #1 800501e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8005020: 4b2c ldr r3, [pc, #176] @ (80050d4 ) 8005022: 2200 movs r2, #0 8005024: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8005026: 4a29 ldr r2, [pc, #164] @ (80050cc ) 8005028: 68fb ldr r3, [r7, #12] 800502a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 800502c: 68fb ldr r3, [r7, #12] 800502e: f003 0301 and.w r3, r3, #1 8005032: 2b00 cmp r3, #0 8005034: d014 beq.n 8005060 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005036: f7fd fd87 bl 8002b48 800503a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800503c: e00a b.n 8005054 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800503e: f7fd fd83 bl 8002b48 8005042: 4602 mov r2, r0 8005044: 693b ldr r3, [r7, #16] 8005046: 1ad3 subs r3, r2, r3 8005048: f241 3288 movw r2, #5000 @ 0x1388 800504c: 4293 cmp r3, r2 800504e: d901 bls.n 8005054 { return HAL_TIMEOUT; 8005050: 2303 movs r3, #3 8005052: e036 b.n 80050c2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005054: 4b1d ldr r3, [pc, #116] @ (80050cc ) 8005056: 6a1b ldr r3, [r3, #32] 8005058: f003 0302 and.w r3, r3, #2 800505c: 2b00 cmp r3, #0 800505e: d0ee beq.n 800503e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8005060: 4b1a ldr r3, [pc, #104] @ (80050cc ) 8005062: 6a1b ldr r3, [r3, #32] 8005064: f423 7240 bic.w r2, r3, #768 @ 0x300 8005068: 687b ldr r3, [r7, #4] 800506a: 685b ldr r3, [r3, #4] 800506c: 4917 ldr r1, [pc, #92] @ (80050cc ) 800506e: 4313 orrs r3, r2 8005070: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8005072: 7dfb ldrb r3, [r7, #23] 8005074: 2b01 cmp r3, #1 8005076: d105 bne.n 8005084 { __HAL_RCC_PWR_CLK_DISABLE(); 8005078: 4b14 ldr r3, [pc, #80] @ (80050cc ) 800507a: 69db ldr r3, [r3, #28] 800507c: 4a13 ldr r2, [pc, #76] @ (80050cc ) 800507e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005082: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8005084: 687b ldr r3, [r7, #4] 8005086: 681b ldr r3, [r3, #0] 8005088: f003 0302 and.w r3, r3, #2 800508c: 2b00 cmp r3, #0 800508e: d008 beq.n 80050a2 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8005090: 4b0e ldr r3, [pc, #56] @ (80050cc ) 8005092: 685b ldr r3, [r3, #4] 8005094: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8005098: 687b ldr r3, [r7, #4] 800509a: 689b ldr r3, [r3, #8] 800509c: 490b ldr r1, [pc, #44] @ (80050cc ) 800509e: 4313 orrs r3, r2 80050a0: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80050a2: 687b ldr r3, [r7, #4] 80050a4: 681b ldr r3, [r3, #0] 80050a6: f003 0310 and.w r3, r3, #16 80050aa: 2b00 cmp r3, #0 80050ac: d008 beq.n 80050c0 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80050ae: 4b07 ldr r3, [pc, #28] @ (80050cc ) 80050b0: 685b ldr r3, [r3, #4] 80050b2: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 80050b6: 687b ldr r3, [r7, #4] 80050b8: 68db ldr r3, [r3, #12] 80050ba: 4904 ldr r1, [pc, #16] @ (80050cc ) 80050bc: 4313 orrs r3, r2 80050be: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80050c0: 2300 movs r3, #0 } 80050c2: 4618 mov r0, r3 80050c4: 3718 adds r7, #24 80050c6: 46bd mov sp, r7 80050c8: bd80 pop {r7, pc} 80050ca: bf00 nop 80050cc: 40021000 .word 0x40021000 80050d0: 40007000 .word 0x40007000 80050d4: 42420440 .word 0x42420440 080050d8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80050d8: b580 push {r7, lr} 80050da: b082 sub sp, #8 80050dc: af00 add r7, sp, #0 80050de: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80050e0: 687b ldr r3, [r7, #4] 80050e2: 2b00 cmp r3, #0 80050e4: d101 bne.n 80050ea { return HAL_ERROR; 80050e6: 2301 movs r3, #1 80050e8: e042 b.n 8005170 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 80050ea: 687b ldr r3, [r7, #4] 80050ec: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80050f0: b2db uxtb r3, r3 80050f2: 2b00 cmp r3, #0 80050f4: d106 bne.n 8005104 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80050f6: 687b ldr r3, [r7, #4] 80050f8: 2200 movs r2, #0 80050fa: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80050fe: 6878 ldr r0, [r7, #4] 8005100: f7fd fc50 bl 80029a4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005104: 687b ldr r3, [r7, #4] 8005106: 2224 movs r2, #36 @ 0x24 8005108: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 800510c: 687b ldr r3, [r7, #4] 800510e: 681b ldr r3, [r3, #0] 8005110: 68da ldr r2, [r3, #12] 8005112: 687b ldr r3, [r7, #4] 8005114: 681b ldr r3, [r3, #0] 8005116: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800511a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 800511c: 6878 ldr r0, [r7, #4] 800511e: f000 fd63 bl 8005be8 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005122: 687b ldr r3, [r7, #4] 8005124: 681b ldr r3, [r3, #0] 8005126: 691a ldr r2, [r3, #16] 8005128: 687b ldr r3, [r7, #4] 800512a: 681b ldr r3, [r3, #0] 800512c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005130: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005132: 687b ldr r3, [r7, #4] 8005134: 681b ldr r3, [r3, #0] 8005136: 695a ldr r2, [r3, #20] 8005138: 687b ldr r3, [r7, #4] 800513a: 681b ldr r3, [r3, #0] 800513c: f022 022a bic.w r2, r2, #42 @ 0x2a 8005140: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005142: 687b ldr r3, [r7, #4] 8005144: 681b ldr r3, [r3, #0] 8005146: 68da ldr r2, [r3, #12] 8005148: 687b ldr r3, [r7, #4] 800514a: 681b ldr r3, [r3, #0] 800514c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005150: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005152: 687b ldr r3, [r7, #4] 8005154: 2200 movs r2, #0 8005156: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005158: 687b ldr r3, [r7, #4] 800515a: 2220 movs r2, #32 800515c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005160: 687b ldr r3, [r7, #4] 8005162: 2220 movs r2, #32 8005164: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005168: 687b ldr r3, [r7, #4] 800516a: 2200 movs r2, #0 800516c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 800516e: 2300 movs r3, #0 } 8005170: 4618 mov r0, r3 8005172: 3708 adds r7, #8 8005174: 46bd mov sp, r7 8005176: bd80 pop {r7, pc} 08005178 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8005178: b580 push {r7, lr} 800517a: b08a sub sp, #40 @ 0x28 800517c: af02 add r7, sp, #8 800517e: 60f8 str r0, [r7, #12] 8005180: 60b9 str r1, [r7, #8] 8005182: 603b str r3, [r7, #0] 8005184: 4613 mov r3, r2 8005186: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8005188: 2300 movs r3, #0 800518a: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800518c: 68fb ldr r3, [r7, #12] 800518e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005192: b2db uxtb r3, r3 8005194: 2b20 cmp r3, #32 8005196: d175 bne.n 8005284 { if ((pData == NULL) || (Size == 0U)) 8005198: 68bb ldr r3, [r7, #8] 800519a: 2b00 cmp r3, #0 800519c: d002 beq.n 80051a4 800519e: 88fb ldrh r3, [r7, #6] 80051a0: 2b00 cmp r3, #0 80051a2: d101 bne.n 80051a8 { return HAL_ERROR; 80051a4: 2301 movs r3, #1 80051a6: e06e b.n 8005286 } huart->ErrorCode = HAL_UART_ERROR_NONE; 80051a8: 68fb ldr r3, [r7, #12] 80051aa: 2200 movs r2, #0 80051ac: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 80051ae: 68fb ldr r3, [r7, #12] 80051b0: 2221 movs r2, #33 @ 0x21 80051b2: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 80051b6: f7fd fcc7 bl 8002b48 80051ba: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 80051bc: 68fb ldr r3, [r7, #12] 80051be: 88fa ldrh r2, [r7, #6] 80051c0: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 80051c2: 68fb ldr r3, [r7, #12] 80051c4: 88fa ldrh r2, [r7, #6] 80051c6: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80051c8: 68fb ldr r3, [r7, #12] 80051ca: 689b ldr r3, [r3, #8] 80051cc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80051d0: d108 bne.n 80051e4 80051d2: 68fb ldr r3, [r7, #12] 80051d4: 691b ldr r3, [r3, #16] 80051d6: 2b00 cmp r3, #0 80051d8: d104 bne.n 80051e4 { pdata8bits = NULL; 80051da: 2300 movs r3, #0 80051dc: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 80051de: 68bb ldr r3, [r7, #8] 80051e0: 61bb str r3, [r7, #24] 80051e2: e003 b.n 80051ec } else { pdata8bits = pData; 80051e4: 68bb ldr r3, [r7, #8] 80051e6: 61fb str r3, [r7, #28] pdata16bits = NULL; 80051e8: 2300 movs r3, #0 80051ea: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 80051ec: e02e b.n 800524c { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80051ee: 683b ldr r3, [r7, #0] 80051f0: 9300 str r3, [sp, #0] 80051f2: 697b ldr r3, [r7, #20] 80051f4: 2200 movs r2, #0 80051f6: 2180 movs r1, #128 @ 0x80 80051f8: 68f8 ldr r0, [r7, #12] 80051fa: f000 fb01 bl 8005800 80051fe: 4603 mov r3, r0 8005200: 2b00 cmp r3, #0 8005202: d005 beq.n 8005210 { huart->gState = HAL_UART_STATE_READY; 8005204: 68fb ldr r3, [r7, #12] 8005206: 2220 movs r2, #32 8005208: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 800520c: 2303 movs r3, #3 800520e: e03a b.n 8005286 } if (pdata8bits == NULL) 8005210: 69fb ldr r3, [r7, #28] 8005212: 2b00 cmp r3, #0 8005214: d10b bne.n 800522e { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8005216: 69bb ldr r3, [r7, #24] 8005218: 881b ldrh r3, [r3, #0] 800521a: 461a mov r2, r3 800521c: 68fb ldr r3, [r7, #12] 800521e: 681b ldr r3, [r3, #0] 8005220: f3c2 0208 ubfx r2, r2, #0, #9 8005224: 605a str r2, [r3, #4] pdata16bits++; 8005226: 69bb ldr r3, [r7, #24] 8005228: 3302 adds r3, #2 800522a: 61bb str r3, [r7, #24] 800522c: e007 b.n 800523e } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 800522e: 69fb ldr r3, [r7, #28] 8005230: 781a ldrb r2, [r3, #0] 8005232: 68fb ldr r3, [r7, #12] 8005234: 681b ldr r3, [r3, #0] 8005236: 605a str r2, [r3, #4] pdata8bits++; 8005238: 69fb ldr r3, [r7, #28] 800523a: 3301 adds r3, #1 800523c: 61fb str r3, [r7, #28] } huart->TxXferCount--; 800523e: 68fb ldr r3, [r7, #12] 8005240: 8cdb ldrh r3, [r3, #38] @ 0x26 8005242: b29b uxth r3, r3 8005244: 3b01 subs r3, #1 8005246: b29a uxth r2, r3 8005248: 68fb ldr r3, [r7, #12] 800524a: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 800524c: 68fb ldr r3, [r7, #12] 800524e: 8cdb ldrh r3, [r3, #38] @ 0x26 8005250: b29b uxth r3, r3 8005252: 2b00 cmp r3, #0 8005254: d1cb bne.n 80051ee } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8005256: 683b ldr r3, [r7, #0] 8005258: 9300 str r3, [sp, #0] 800525a: 697b ldr r3, [r7, #20] 800525c: 2200 movs r2, #0 800525e: 2140 movs r1, #64 @ 0x40 8005260: 68f8 ldr r0, [r7, #12] 8005262: f000 facd bl 8005800 8005266: 4603 mov r3, r0 8005268: 2b00 cmp r3, #0 800526a: d005 beq.n 8005278 { huart->gState = HAL_UART_STATE_READY; 800526c: 68fb ldr r3, [r7, #12] 800526e: 2220 movs r2, #32 8005270: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8005274: 2303 movs r3, #3 8005276: e006 b.n 8005286 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8005278: 68fb ldr r3, [r7, #12] 800527a: 2220 movs r2, #32 800527c: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8005280: 2300 movs r3, #0 8005282: e000 b.n 8005286 } else { return HAL_BUSY; 8005284: 2302 movs r3, #2 } } 8005286: 4618 mov r0, r3 8005288: 3720 adds r7, #32 800528a: 46bd mov sp, r7 800528c: bd80 pop {r7, pc} ... 08005290 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005290: b580 push {r7, lr} 8005292: b0ba sub sp, #232 @ 0xe8 8005294: af00 add r7, sp, #0 8005296: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005298: 687b ldr r3, [r7, #4] 800529a: 681b ldr r3, [r3, #0] 800529c: 681b ldr r3, [r3, #0] 800529e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80052a2: 687b ldr r3, [r7, #4] 80052a4: 681b ldr r3, [r3, #0] 80052a6: 68db ldr r3, [r3, #12] 80052a8: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80052ac: 687b ldr r3, [r7, #4] 80052ae: 681b ldr r3, [r3, #0] 80052b0: 695b ldr r3, [r3, #20] 80052b2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 80052b6: 2300 movs r3, #0 80052b8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 80052bc: 2300 movs r3, #0 80052be: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80052c2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80052c6: f003 030f and.w r3, r3, #15 80052ca: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 80052ce: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80052d2: 2b00 cmp r3, #0 80052d4: d10f bne.n 80052f6 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80052d6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80052da: f003 0320 and.w r3, r3, #32 80052de: 2b00 cmp r3, #0 80052e0: d009 beq.n 80052f6 80052e2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80052e6: f003 0320 and.w r3, r3, #32 80052ea: 2b00 cmp r3, #0 80052ec: d003 beq.n 80052f6 { UART_Receive_IT(huart); 80052ee: 6878 ldr r0, [r7, #4] 80052f0: f000 fbbc bl 8005a6c return; 80052f4: e25b b.n 80057ae } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80052f6: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80052fa: 2b00 cmp r3, #0 80052fc: f000 80de beq.w 80054bc 8005300: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005304: f003 0301 and.w r3, r3, #1 8005308: 2b00 cmp r3, #0 800530a: d106 bne.n 800531a || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 800530c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005310: f403 7390 and.w r3, r3, #288 @ 0x120 8005314: 2b00 cmp r3, #0 8005316: f000 80d1 beq.w 80054bc { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 800531a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800531e: f003 0301 and.w r3, r3, #1 8005322: 2b00 cmp r3, #0 8005324: d00b beq.n 800533e 8005326: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800532a: f403 7380 and.w r3, r3, #256 @ 0x100 800532e: 2b00 cmp r3, #0 8005330: d005 beq.n 800533e { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005332: 687b ldr r3, [r7, #4] 8005334: 6c5b ldr r3, [r3, #68] @ 0x44 8005336: f043 0201 orr.w r2, r3, #1 800533a: 687b ldr r3, [r7, #4] 800533c: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 800533e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005342: f003 0304 and.w r3, r3, #4 8005346: 2b00 cmp r3, #0 8005348: d00b beq.n 8005362 800534a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800534e: f003 0301 and.w r3, r3, #1 8005352: 2b00 cmp r3, #0 8005354: d005 beq.n 8005362 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005356: 687b ldr r3, [r7, #4] 8005358: 6c5b ldr r3, [r3, #68] @ 0x44 800535a: f043 0202 orr.w r2, r3, #2 800535e: 687b ldr r3, [r7, #4] 8005360: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005362: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005366: f003 0302 and.w r3, r3, #2 800536a: 2b00 cmp r3, #0 800536c: d00b beq.n 8005386 800536e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005372: f003 0301 and.w r3, r3, #1 8005376: 2b00 cmp r3, #0 8005378: d005 beq.n 8005386 { huart->ErrorCode |= HAL_UART_ERROR_FE; 800537a: 687b ldr r3, [r7, #4] 800537c: 6c5b ldr r3, [r3, #68] @ 0x44 800537e: f043 0204 orr.w r2, r3, #4 8005382: 687b ldr r3, [r7, #4] 8005384: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005386: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800538a: f003 0308 and.w r3, r3, #8 800538e: 2b00 cmp r3, #0 8005390: d011 beq.n 80053b6 8005392: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005396: f003 0320 and.w r3, r3, #32 800539a: 2b00 cmp r3, #0 800539c: d105 bne.n 80053aa || ((cr3its & USART_CR3_EIE) != RESET))) 800539e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80053a2: f003 0301 and.w r3, r3, #1 80053a6: 2b00 cmp r3, #0 80053a8: d005 beq.n 80053b6 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80053aa: 687b ldr r3, [r7, #4] 80053ac: 6c5b ldr r3, [r3, #68] @ 0x44 80053ae: f043 0208 orr.w r2, r3, #8 80053b2: 687b ldr r3, [r7, #4] 80053b4: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80053b6: 687b ldr r3, [r7, #4] 80053b8: 6c5b ldr r3, [r3, #68] @ 0x44 80053ba: 2b00 cmp r3, #0 80053bc: f000 81f2 beq.w 80057a4 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80053c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80053c4: f003 0320 and.w r3, r3, #32 80053c8: 2b00 cmp r3, #0 80053ca: d008 beq.n 80053de 80053cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80053d0: f003 0320 and.w r3, r3, #32 80053d4: 2b00 cmp r3, #0 80053d6: d002 beq.n 80053de { UART_Receive_IT(huart); 80053d8: 6878 ldr r0, [r7, #4] 80053da: f000 fb47 bl 8005a6c } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80053de: 687b ldr r3, [r7, #4] 80053e0: 681b ldr r3, [r3, #0] 80053e2: 695b ldr r3, [r3, #20] 80053e4: f003 0340 and.w r3, r3, #64 @ 0x40 80053e8: 2b00 cmp r3, #0 80053ea: bf14 ite ne 80053ec: 2301 movne r3, #1 80053ee: 2300 moveq r3, #0 80053f0: b2db uxtb r3, r3 80053f2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80053f6: 687b ldr r3, [r7, #4] 80053f8: 6c5b ldr r3, [r3, #68] @ 0x44 80053fa: f003 0308 and.w r3, r3, #8 80053fe: 2b00 cmp r3, #0 8005400: d103 bne.n 800540a 8005402: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005406: 2b00 cmp r3, #0 8005408: d04f beq.n 80054aa { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 800540a: 6878 ldr r0, [r7, #4] 800540c: f000 fa51 bl 80058b2 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005410: 687b ldr r3, [r7, #4] 8005412: 681b ldr r3, [r3, #0] 8005414: 695b ldr r3, [r3, #20] 8005416: f003 0340 and.w r3, r3, #64 @ 0x40 800541a: 2b00 cmp r3, #0 800541c: d041 beq.n 80054a2 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800541e: 687b ldr r3, [r7, #4] 8005420: 681b ldr r3, [r3, #0] 8005422: 3314 adds r3, #20 8005424: f8c7 309c str.w r3, [r7, #156] @ 0x9c */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005428: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800542c: e853 3f00 ldrex r3, [r3] 8005430: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005434: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005438: f023 0340 bic.w r3, r3, #64 @ 0x40 800543c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005440: 687b ldr r3, [r7, #4] 8005442: 681b ldr r3, [r3, #0] 8005444: 3314 adds r3, #20 8005446: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 800544a: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 800544e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005452: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005456: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 800545a: e841 2300 strex r3, r2, [r1] 800545e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005462: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005466: 2b00 cmp r3, #0 8005468: d1d9 bne.n 800541e /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 800546a: 687b ldr r3, [r7, #4] 800546c: 6bdb ldr r3, [r3, #60] @ 0x3c 800546e: 2b00 cmp r3, #0 8005470: d013 beq.n 800549a { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005472: 687b ldr r3, [r7, #4] 8005474: 6bdb ldr r3, [r3, #60] @ 0x3c 8005476: 4a7e ldr r2, [pc, #504] @ (8005670 ) 8005478: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 800547a: 687b ldr r3, [r7, #4] 800547c: 6bdb ldr r3, [r3, #60] @ 0x3c 800547e: 4618 mov r0, r3 8005480: f7fd feea bl 8003258 8005484: 4603 mov r3, r0 8005486: 2b00 cmp r3, #0 8005488: d016 beq.n 80054b8 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 800548a: 687b ldr r3, [r7, #4] 800548c: 6bdb ldr r3, [r3, #60] @ 0x3c 800548e: 6b5b ldr r3, [r3, #52] @ 0x34 8005490: 687a ldr r2, [r7, #4] 8005492: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005494: 4610 mov r0, r2 8005496: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005498: e00e b.n 80054b8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800549a: 6878 ldr r0, [r7, #4] 800549c: f000 f99c bl 80057d8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80054a0: e00a b.n 80054b8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80054a2: 6878 ldr r0, [r7, #4] 80054a4: f000 f998 bl 80057d8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80054a8: e006 b.n 80054b8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80054aa: 6878 ldr r0, [r7, #4] 80054ac: f000 f994 bl 80057d8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80054b0: 687b ldr r3, [r7, #4] 80054b2: 2200 movs r2, #0 80054b4: 645a str r2, [r3, #68] @ 0x44 } } return; 80054b6: e175 b.n 80057a4 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80054b8: bf00 nop return; 80054ba: e173 b.n 80057a4 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80054bc: 687b ldr r3, [r7, #4] 80054be: 6b1b ldr r3, [r3, #48] @ 0x30 80054c0: 2b01 cmp r3, #1 80054c2: f040 814f bne.w 8005764 && ((isrflags & USART_SR_IDLE) != 0U) 80054c6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80054ca: f003 0310 and.w r3, r3, #16 80054ce: 2b00 cmp r3, #0 80054d0: f000 8148 beq.w 8005764 && ((cr1its & USART_SR_IDLE) != 0U)) 80054d4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80054d8: f003 0310 and.w r3, r3, #16 80054dc: 2b00 cmp r3, #0 80054de: f000 8141 beq.w 8005764 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80054e2: 2300 movs r3, #0 80054e4: 60bb str r3, [r7, #8] 80054e6: 687b ldr r3, [r7, #4] 80054e8: 681b ldr r3, [r3, #0] 80054ea: 681b ldr r3, [r3, #0] 80054ec: 60bb str r3, [r7, #8] 80054ee: 687b ldr r3, [r7, #4] 80054f0: 681b ldr r3, [r3, #0] 80054f2: 685b ldr r3, [r3, #4] 80054f4: 60bb str r3, [r7, #8] 80054f6: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80054f8: 687b ldr r3, [r7, #4] 80054fa: 681b ldr r3, [r3, #0] 80054fc: 695b ldr r3, [r3, #20] 80054fe: f003 0340 and.w r3, r3, #64 @ 0x40 8005502: 2b00 cmp r3, #0 8005504: f000 80b6 beq.w 8005674 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005508: 687b ldr r3, [r7, #4] 800550a: 6bdb ldr r3, [r3, #60] @ 0x3c 800550c: 681b ldr r3, [r3, #0] 800550e: 685b ldr r3, [r3, #4] 8005510: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005514: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005518: 2b00 cmp r3, #0 800551a: f000 8145 beq.w 80057a8 && (nb_remaining_rx_data < huart->RxXferSize)) 800551e: 687b ldr r3, [r7, #4] 8005520: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005522: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005526: 429a cmp r2, r3 8005528: f080 813e bcs.w 80057a8 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 800552c: 687b ldr r3, [r7, #4] 800552e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005532: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8005534: 687b ldr r3, [r7, #4] 8005536: 6bdb ldr r3, [r3, #60] @ 0x3c 8005538: 699b ldr r3, [r3, #24] 800553a: 2b20 cmp r3, #32 800553c: f000 8088 beq.w 8005650 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005540: 687b ldr r3, [r7, #4] 8005542: 681b ldr r3, [r3, #0] 8005544: 330c adds r3, #12 8005546: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800554a: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800554e: e853 3f00 ldrex r3, [r3] 8005552: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005556: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800555a: f423 7380 bic.w r3, r3, #256 @ 0x100 800555e: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005562: 687b ldr r3, [r7, #4] 8005564: 681b ldr r3, [r3, #0] 8005566: 330c adds r3, #12 8005568: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 800556c: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8005570: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005574: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005578: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800557c: e841 2300 strex r3, r2, [r1] 8005580: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005584: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005588: 2b00 cmp r3, #0 800558a: d1d9 bne.n 8005540 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800558c: 687b ldr r3, [r7, #4] 800558e: 681b ldr r3, [r3, #0] 8005590: 3314 adds r3, #20 8005592: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005594: 6f7b ldr r3, [r7, #116] @ 0x74 8005596: e853 3f00 ldrex r3, [r3] 800559a: 673b str r3, [r7, #112] @ 0x70 return(result); 800559c: 6f3b ldr r3, [r7, #112] @ 0x70 800559e: f023 0301 bic.w r3, r3, #1 80055a2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80055a6: 687b ldr r3, [r7, #4] 80055a8: 681b ldr r3, [r3, #0] 80055aa: 3314 adds r3, #20 80055ac: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80055b0: f8c7 2080 str.w r2, [r7, #128] @ 0x80 80055b4: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80055b6: 6ff9 ldr r1, [r7, #124] @ 0x7c 80055b8: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80055bc: e841 2300 strex r3, r2, [r1] 80055c0: 67bb str r3, [r7, #120] @ 0x78 return(result); 80055c2: 6fbb ldr r3, [r7, #120] @ 0x78 80055c4: 2b00 cmp r3, #0 80055c6: d1e1 bne.n 800558c /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80055c8: 687b ldr r3, [r7, #4] 80055ca: 681b ldr r3, [r3, #0] 80055cc: 3314 adds r3, #20 80055ce: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80055d0: 6e3b ldr r3, [r7, #96] @ 0x60 80055d2: e853 3f00 ldrex r3, [r3] 80055d6: 65fb str r3, [r7, #92] @ 0x5c return(result); 80055d8: 6dfb ldr r3, [r7, #92] @ 0x5c 80055da: f023 0340 bic.w r3, r3, #64 @ 0x40 80055de: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80055e2: 687b ldr r3, [r7, #4] 80055e4: 681b ldr r3, [r3, #0] 80055e6: 3314 adds r3, #20 80055e8: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80055ec: 66fa str r2, [r7, #108] @ 0x6c 80055ee: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80055f0: 6eb9 ldr r1, [r7, #104] @ 0x68 80055f2: 6efa ldr r2, [r7, #108] @ 0x6c 80055f4: e841 2300 strex r3, r2, [r1] 80055f8: 667b str r3, [r7, #100] @ 0x64 return(result); 80055fa: 6e7b ldr r3, [r7, #100] @ 0x64 80055fc: 2b00 cmp r3, #0 80055fe: d1e3 bne.n 80055c8 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005600: 687b ldr r3, [r7, #4] 8005602: 2220 movs r2, #32 8005604: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005608: 687b ldr r3, [r7, #4] 800560a: 2200 movs r2, #0 800560c: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800560e: 687b ldr r3, [r7, #4] 8005610: 681b ldr r3, [r3, #0] 8005612: 330c adds r3, #12 8005614: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005616: 6cfb ldr r3, [r7, #76] @ 0x4c 8005618: e853 3f00 ldrex r3, [r3] 800561c: 64bb str r3, [r7, #72] @ 0x48 return(result); 800561e: 6cbb ldr r3, [r7, #72] @ 0x48 8005620: f023 0310 bic.w r3, r3, #16 8005624: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8005628: 687b ldr r3, [r7, #4] 800562a: 681b ldr r3, [r3, #0] 800562c: 330c adds r3, #12 800562e: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8005632: 65ba str r2, [r7, #88] @ 0x58 8005634: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005636: 6d79 ldr r1, [r7, #84] @ 0x54 8005638: 6dba ldr r2, [r7, #88] @ 0x58 800563a: e841 2300 strex r3, r2, [r1] 800563e: 653b str r3, [r7, #80] @ 0x50 return(result); 8005640: 6d3b ldr r3, [r7, #80] @ 0x50 8005642: 2b00 cmp r3, #0 8005644: d1e3 bne.n 800560e /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8005646: 687b ldr r3, [r7, #4] 8005648: 6bdb ldr r3, [r3, #60] @ 0x3c 800564a: 4618 mov r0, r3 800564c: f7fd fdc9 bl 80031e2 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005650: 687b ldr r3, [r7, #4] 8005652: 2202 movs r2, #2 8005654: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8005656: 687b ldr r3, [r7, #4] 8005658: 8d9a ldrh r2, [r3, #44] @ 0x2c 800565a: 687b ldr r3, [r7, #4] 800565c: 8ddb ldrh r3, [r3, #46] @ 0x2e 800565e: b29b uxth r3, r3 8005660: 1ad3 subs r3, r2, r3 8005662: b29b uxth r3, r3 8005664: 4619 mov r1, r3 8005666: 6878 ldr r0, [r7, #4] 8005668: f000 f8bf bl 80057ea #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 800566c: e09c b.n 80057a8 800566e: bf00 nop 8005670: 08005977 .word 0x08005977 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8005674: 687b ldr r3, [r7, #4] 8005676: 8d9a ldrh r2, [r3, #44] @ 0x2c 8005678: 687b ldr r3, [r7, #4] 800567a: 8ddb ldrh r3, [r3, #46] @ 0x2e 800567c: b29b uxth r3, r3 800567e: 1ad3 subs r3, r2, r3 8005680: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8005684: 687b ldr r3, [r7, #4] 8005686: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005688: b29b uxth r3, r3 800568a: 2b00 cmp r3, #0 800568c: f000 808e beq.w 80057ac && (nb_rx_data > 0U)) 8005690: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8005694: 2b00 cmp r3, #0 8005696: f000 8089 beq.w 80057ac { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800569a: 687b ldr r3, [r7, #4] 800569c: 681b ldr r3, [r3, #0] 800569e: 330c adds r3, #12 80056a0: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80056a2: 6bbb ldr r3, [r7, #56] @ 0x38 80056a4: e853 3f00 ldrex r3, [r3] 80056a8: 637b str r3, [r7, #52] @ 0x34 return(result); 80056aa: 6b7b ldr r3, [r7, #52] @ 0x34 80056ac: f423 7390 bic.w r3, r3, #288 @ 0x120 80056b0: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80056b4: 687b ldr r3, [r7, #4] 80056b6: 681b ldr r3, [r3, #0] 80056b8: 330c adds r3, #12 80056ba: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80056be: 647a str r2, [r7, #68] @ 0x44 80056c0: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80056c2: 6c39 ldr r1, [r7, #64] @ 0x40 80056c4: 6c7a ldr r2, [r7, #68] @ 0x44 80056c6: e841 2300 strex r3, r2, [r1] 80056ca: 63fb str r3, [r7, #60] @ 0x3c return(result); 80056cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80056ce: 2b00 cmp r3, #0 80056d0: d1e3 bne.n 800569a /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80056d2: 687b ldr r3, [r7, #4] 80056d4: 681b ldr r3, [r3, #0] 80056d6: 3314 adds r3, #20 80056d8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80056da: 6a7b ldr r3, [r7, #36] @ 0x24 80056dc: e853 3f00 ldrex r3, [r3] 80056e0: 623b str r3, [r7, #32] return(result); 80056e2: 6a3b ldr r3, [r7, #32] 80056e4: f023 0301 bic.w r3, r3, #1 80056e8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80056ec: 687b ldr r3, [r7, #4] 80056ee: 681b ldr r3, [r3, #0] 80056f0: 3314 adds r3, #20 80056f2: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80056f6: 633a str r2, [r7, #48] @ 0x30 80056f8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80056fa: 6af9 ldr r1, [r7, #44] @ 0x2c 80056fc: 6b3a ldr r2, [r7, #48] @ 0x30 80056fe: e841 2300 strex r3, r2, [r1] 8005702: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005704: 6abb ldr r3, [r7, #40] @ 0x28 8005706: 2b00 cmp r3, #0 8005708: d1e3 bne.n 80056d2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800570a: 687b ldr r3, [r7, #4] 800570c: 2220 movs r2, #32 800570e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005712: 687b ldr r3, [r7, #4] 8005714: 2200 movs r2, #0 8005716: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005718: 687b ldr r3, [r7, #4] 800571a: 681b ldr r3, [r3, #0] 800571c: 330c adds r3, #12 800571e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005720: 693b ldr r3, [r7, #16] 8005722: e853 3f00 ldrex r3, [r3] 8005726: 60fb str r3, [r7, #12] return(result); 8005728: 68fb ldr r3, [r7, #12] 800572a: f023 0310 bic.w r3, r3, #16 800572e: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005732: 687b ldr r3, [r7, #4] 8005734: 681b ldr r3, [r3, #0] 8005736: 330c adds r3, #12 8005738: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 800573c: 61fa str r2, [r7, #28] 800573e: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005740: 69b9 ldr r1, [r7, #24] 8005742: 69fa ldr r2, [r7, #28] 8005744: e841 2300 strex r3, r2, [r1] 8005748: 617b str r3, [r7, #20] return(result); 800574a: 697b ldr r3, [r7, #20] 800574c: 2b00 cmp r3, #0 800574e: d1e3 bne.n 8005718 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005750: 687b ldr r3, [r7, #4] 8005752: 2202 movs r2, #2 8005754: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8005756: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800575a: 4619 mov r1, r3 800575c: 6878 ldr r0, [r7, #4] 800575e: f000 f844 bl 80057ea #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8005762: e023 b.n 80057ac } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8005764: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005768: f003 0380 and.w r3, r3, #128 @ 0x80 800576c: 2b00 cmp r3, #0 800576e: d009 beq.n 8005784 8005770: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005774: f003 0380 and.w r3, r3, #128 @ 0x80 8005778: 2b00 cmp r3, #0 800577a: d003 beq.n 8005784 { UART_Transmit_IT(huart); 800577c: 6878 ldr r0, [r7, #4] 800577e: f000 f90e bl 800599e return; 8005782: e014 b.n 80057ae } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8005784: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005788: f003 0340 and.w r3, r3, #64 @ 0x40 800578c: 2b00 cmp r3, #0 800578e: d00e beq.n 80057ae 8005790: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005794: f003 0340 and.w r3, r3, #64 @ 0x40 8005798: 2b00 cmp r3, #0 800579a: d008 beq.n 80057ae { UART_EndTransmit_IT(huart); 800579c: 6878 ldr r0, [r7, #4] 800579e: f000 f94d bl 8005a3c return; 80057a2: e004 b.n 80057ae return; 80057a4: bf00 nop 80057a6: e002 b.n 80057ae return; 80057a8: bf00 nop 80057aa: e000 b.n 80057ae return; 80057ac: bf00 nop } } 80057ae: 37e8 adds r7, #232 @ 0xe8 80057b0: 46bd mov sp, r7 80057b2: bd80 pop {r7, pc} 080057b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 80057b4: b480 push {r7} 80057b6: b083 sub sp, #12 80057b8: af00 add r7, sp, #0 80057ba: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 80057bc: bf00 nop 80057be: 370c adds r7, #12 80057c0: 46bd mov sp, r7 80057c2: bc80 pop {r7} 80057c4: 4770 bx lr 080057c6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80057c6: b480 push {r7} 80057c8: b083 sub sp, #12 80057ca: af00 add r7, sp, #0 80057cc: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 80057ce: bf00 nop 80057d0: 370c adds r7, #12 80057d2: 46bd mov sp, r7 80057d4: bc80 pop {r7} 80057d6: 4770 bx lr 080057d8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 80057d8: b480 push {r7} 80057da: b083 sub sp, #12 80057dc: af00 add r7, sp, #0 80057de: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 80057e0: bf00 nop 80057e2: 370c adds r7, #12 80057e4: 46bd mov sp, r7 80057e6: bc80 pop {r7} 80057e8: 4770 bx lr 080057ea : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 80057ea: b480 push {r7} 80057ec: b083 sub sp, #12 80057ee: af00 add r7, sp, #0 80057f0: 6078 str r0, [r7, #4] 80057f2: 460b mov r3, r1 80057f4: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 80057f6: bf00 nop 80057f8: 370c adds r7, #12 80057fa: 46bd mov sp, r7 80057fc: bc80 pop {r7} 80057fe: 4770 bx lr 08005800 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8005800: b580 push {r7, lr} 8005802: b086 sub sp, #24 8005804: af00 add r7, sp, #0 8005806: 60f8 str r0, [r7, #12] 8005808: 60b9 str r1, [r7, #8] 800580a: 603b str r3, [r7, #0] 800580c: 4613 mov r3, r2 800580e: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8005810: e03b b.n 800588a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8005812: 6a3b ldr r3, [r7, #32] 8005814: f1b3 3fff cmp.w r3, #4294967295 8005818: d037 beq.n 800588a { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800581a: f7fd f995 bl 8002b48 800581e: 4602 mov r2, r0 8005820: 683b ldr r3, [r7, #0] 8005822: 1ad3 subs r3, r2, r3 8005824: 6a3a ldr r2, [r7, #32] 8005826: 429a cmp r2, r3 8005828: d302 bcc.n 8005830 800582a: 6a3b ldr r3, [r7, #32] 800582c: 2b00 cmp r3, #0 800582e: d101 bne.n 8005834 { return HAL_TIMEOUT; 8005830: 2303 movs r3, #3 8005832: e03a b.n 80058aa } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8005834: 68fb ldr r3, [r7, #12] 8005836: 681b ldr r3, [r3, #0] 8005838: 68db ldr r3, [r3, #12] 800583a: f003 0304 and.w r3, r3, #4 800583e: 2b00 cmp r3, #0 8005840: d023 beq.n 800588a 8005842: 68bb ldr r3, [r7, #8] 8005844: 2b80 cmp r3, #128 @ 0x80 8005846: d020 beq.n 800588a 8005848: 68bb ldr r3, [r7, #8] 800584a: 2b40 cmp r3, #64 @ 0x40 800584c: d01d beq.n 800588a { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800584e: 68fb ldr r3, [r7, #12] 8005850: 681b ldr r3, [r3, #0] 8005852: 681b ldr r3, [r3, #0] 8005854: f003 0308 and.w r3, r3, #8 8005858: 2b08 cmp r3, #8 800585a: d116 bne.n 800588a { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 800585c: 2300 movs r3, #0 800585e: 617b str r3, [r7, #20] 8005860: 68fb ldr r3, [r7, #12] 8005862: 681b ldr r3, [r3, #0] 8005864: 681b ldr r3, [r3, #0] 8005866: 617b str r3, [r7, #20] 8005868: 68fb ldr r3, [r7, #12] 800586a: 681b ldr r3, [r3, #0] 800586c: 685b ldr r3, [r3, #4] 800586e: 617b str r3, [r7, #20] 8005870: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8005872: 68f8 ldr r0, [r7, #12] 8005874: f000 f81d bl 80058b2 huart->ErrorCode = HAL_UART_ERROR_ORE; 8005878: 68fb ldr r3, [r7, #12] 800587a: 2208 movs r2, #8 800587c: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 800587e: 68fb ldr r3, [r7, #12] 8005880: 2200 movs r2, #0 8005882: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8005886: 2301 movs r3, #1 8005888: e00f b.n 80058aa while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800588a: 68fb ldr r3, [r7, #12] 800588c: 681b ldr r3, [r3, #0] 800588e: 681a ldr r2, [r3, #0] 8005890: 68bb ldr r3, [r7, #8] 8005892: 4013 ands r3, r2 8005894: 68ba ldr r2, [r7, #8] 8005896: 429a cmp r2, r3 8005898: bf0c ite eq 800589a: 2301 moveq r3, #1 800589c: 2300 movne r3, #0 800589e: b2db uxtb r3, r3 80058a0: 461a mov r2, r3 80058a2: 79fb ldrb r3, [r7, #7] 80058a4: 429a cmp r2, r3 80058a6: d0b4 beq.n 8005812 } } } } return HAL_OK; 80058a8: 2300 movs r3, #0 } 80058aa: 4618 mov r0, r3 80058ac: 3718 adds r7, #24 80058ae: 46bd mov sp, r7 80058b0: bd80 pop {r7, pc} 080058b2 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80058b2: b480 push {r7} 80058b4: b095 sub sp, #84 @ 0x54 80058b6: af00 add r7, sp, #0 80058b8: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80058ba: 687b ldr r3, [r7, #4] 80058bc: 681b ldr r3, [r3, #0] 80058be: 330c adds r3, #12 80058c0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80058c2: 6b7b ldr r3, [r7, #52] @ 0x34 80058c4: e853 3f00 ldrex r3, [r3] 80058c8: 633b str r3, [r7, #48] @ 0x30 return(result); 80058ca: 6b3b ldr r3, [r7, #48] @ 0x30 80058cc: f423 7390 bic.w r3, r3, #288 @ 0x120 80058d0: 64fb str r3, [r7, #76] @ 0x4c 80058d2: 687b ldr r3, [r7, #4] 80058d4: 681b ldr r3, [r3, #0] 80058d6: 330c adds r3, #12 80058d8: 6cfa ldr r2, [r7, #76] @ 0x4c 80058da: 643a str r2, [r7, #64] @ 0x40 80058dc: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80058de: 6bf9 ldr r1, [r7, #60] @ 0x3c 80058e0: 6c3a ldr r2, [r7, #64] @ 0x40 80058e2: e841 2300 strex r3, r2, [r1] 80058e6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80058e8: 6bbb ldr r3, [r7, #56] @ 0x38 80058ea: 2b00 cmp r3, #0 80058ec: d1e5 bne.n 80058ba ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80058ee: 687b ldr r3, [r7, #4] 80058f0: 681b ldr r3, [r3, #0] 80058f2: 3314 adds r3, #20 80058f4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80058f6: 6a3b ldr r3, [r7, #32] 80058f8: e853 3f00 ldrex r3, [r3] 80058fc: 61fb str r3, [r7, #28] return(result); 80058fe: 69fb ldr r3, [r7, #28] 8005900: f023 0301 bic.w r3, r3, #1 8005904: 64bb str r3, [r7, #72] @ 0x48 8005906: 687b ldr r3, [r7, #4] 8005908: 681b ldr r3, [r3, #0] 800590a: 3314 adds r3, #20 800590c: 6cba ldr r2, [r7, #72] @ 0x48 800590e: 62fa str r2, [r7, #44] @ 0x2c 8005910: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005912: 6ab9 ldr r1, [r7, #40] @ 0x28 8005914: 6afa ldr r2, [r7, #44] @ 0x2c 8005916: e841 2300 strex r3, r2, [r1] 800591a: 627b str r3, [r7, #36] @ 0x24 return(result); 800591c: 6a7b ldr r3, [r7, #36] @ 0x24 800591e: 2b00 cmp r3, #0 8005920: d1e5 bne.n 80058ee /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005922: 687b ldr r3, [r7, #4] 8005924: 6b1b ldr r3, [r3, #48] @ 0x30 8005926: 2b01 cmp r3, #1 8005928: d119 bne.n 800595e { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800592a: 687b ldr r3, [r7, #4] 800592c: 681b ldr r3, [r3, #0] 800592e: 330c adds r3, #12 8005930: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005932: 68fb ldr r3, [r7, #12] 8005934: e853 3f00 ldrex r3, [r3] 8005938: 60bb str r3, [r7, #8] return(result); 800593a: 68bb ldr r3, [r7, #8] 800593c: f023 0310 bic.w r3, r3, #16 8005940: 647b str r3, [r7, #68] @ 0x44 8005942: 687b ldr r3, [r7, #4] 8005944: 681b ldr r3, [r3, #0] 8005946: 330c adds r3, #12 8005948: 6c7a ldr r2, [r7, #68] @ 0x44 800594a: 61ba str r2, [r7, #24] 800594c: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800594e: 6979 ldr r1, [r7, #20] 8005950: 69ba ldr r2, [r7, #24] 8005952: e841 2300 strex r3, r2, [r1] 8005956: 613b str r3, [r7, #16] return(result); 8005958: 693b ldr r3, [r7, #16] 800595a: 2b00 cmp r3, #0 800595c: d1e5 bne.n 800592a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800595e: 687b ldr r3, [r7, #4] 8005960: 2220 movs r2, #32 8005962: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005966: 687b ldr r3, [r7, #4] 8005968: 2200 movs r2, #0 800596a: 631a str r2, [r3, #48] @ 0x30 } 800596c: bf00 nop 800596e: 3754 adds r7, #84 @ 0x54 8005970: 46bd mov sp, r7 8005972: bc80 pop {r7} 8005974: 4770 bx lr 08005976 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8005976: b580 push {r7, lr} 8005978: b084 sub sp, #16 800597a: af00 add r7, sp, #0 800597c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800597e: 687b ldr r3, [r7, #4] 8005980: 6a5b ldr r3, [r3, #36] @ 0x24 8005982: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8005984: 68fb ldr r3, [r7, #12] 8005986: 2200 movs r2, #0 8005988: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 800598a: 68fb ldr r3, [r7, #12] 800598c: 2200 movs r2, #0 800598e: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005990: 68f8 ldr r0, [r7, #12] 8005992: f7ff ff21 bl 80057d8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8005996: bf00 nop 8005998: 3710 adds r7, #16 800599a: 46bd mov sp, r7 800599c: bd80 pop {r7, pc} 0800599e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800599e: b480 push {r7} 80059a0: b085 sub sp, #20 80059a2: af00 add r7, sp, #0 80059a4: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80059a6: 687b ldr r3, [r7, #4] 80059a8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80059ac: b2db uxtb r3, r3 80059ae: 2b21 cmp r3, #33 @ 0x21 80059b0: d13e bne.n 8005a30 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80059b2: 687b ldr r3, [r7, #4] 80059b4: 689b ldr r3, [r3, #8] 80059b6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80059ba: d114 bne.n 80059e6 80059bc: 687b ldr r3, [r7, #4] 80059be: 691b ldr r3, [r3, #16] 80059c0: 2b00 cmp r3, #0 80059c2: d110 bne.n 80059e6 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80059c4: 687b ldr r3, [r7, #4] 80059c6: 6a1b ldr r3, [r3, #32] 80059c8: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80059ca: 68fb ldr r3, [r7, #12] 80059cc: 881b ldrh r3, [r3, #0] 80059ce: 461a mov r2, r3 80059d0: 687b ldr r3, [r7, #4] 80059d2: 681b ldr r3, [r3, #0] 80059d4: f3c2 0208 ubfx r2, r2, #0, #9 80059d8: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 80059da: 687b ldr r3, [r7, #4] 80059dc: 6a1b ldr r3, [r3, #32] 80059de: 1c9a adds r2, r3, #2 80059e0: 687b ldr r3, [r7, #4] 80059e2: 621a str r2, [r3, #32] 80059e4: e008 b.n 80059f8 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80059e6: 687b ldr r3, [r7, #4] 80059e8: 6a1b ldr r3, [r3, #32] 80059ea: 1c59 adds r1, r3, #1 80059ec: 687a ldr r2, [r7, #4] 80059ee: 6211 str r1, [r2, #32] 80059f0: 781a ldrb r2, [r3, #0] 80059f2: 687b ldr r3, [r7, #4] 80059f4: 681b ldr r3, [r3, #0] 80059f6: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 80059f8: 687b ldr r3, [r7, #4] 80059fa: 8cdb ldrh r3, [r3, #38] @ 0x26 80059fc: b29b uxth r3, r3 80059fe: 3b01 subs r3, #1 8005a00: b29b uxth r3, r3 8005a02: 687a ldr r2, [r7, #4] 8005a04: 4619 mov r1, r3 8005a06: 84d1 strh r1, [r2, #38] @ 0x26 8005a08: 2b00 cmp r3, #0 8005a0a: d10f bne.n 8005a2c { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8005a0c: 687b ldr r3, [r7, #4] 8005a0e: 681b ldr r3, [r3, #0] 8005a10: 68da ldr r2, [r3, #12] 8005a12: 687b ldr r3, [r7, #4] 8005a14: 681b ldr r3, [r3, #0] 8005a16: f022 0280 bic.w r2, r2, #128 @ 0x80 8005a1a: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8005a1c: 687b ldr r3, [r7, #4] 8005a1e: 681b ldr r3, [r3, #0] 8005a20: 68da ldr r2, [r3, #12] 8005a22: 687b ldr r3, [r7, #4] 8005a24: 681b ldr r3, [r3, #0] 8005a26: f042 0240 orr.w r2, r2, #64 @ 0x40 8005a2a: 60da str r2, [r3, #12] } return HAL_OK; 8005a2c: 2300 movs r3, #0 8005a2e: e000 b.n 8005a32 } else { return HAL_BUSY; 8005a30: 2302 movs r3, #2 } } 8005a32: 4618 mov r0, r3 8005a34: 3714 adds r7, #20 8005a36: 46bd mov sp, r7 8005a38: bc80 pop {r7} 8005a3a: 4770 bx lr 08005a3c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8005a3c: b580 push {r7, lr} 8005a3e: b082 sub sp, #8 8005a40: af00 add r7, sp, #0 8005a42: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8005a44: 687b ldr r3, [r7, #4] 8005a46: 681b ldr r3, [r3, #0] 8005a48: 68da ldr r2, [r3, #12] 8005a4a: 687b ldr r3, [r7, #4] 8005a4c: 681b ldr r3, [r3, #0] 8005a4e: f022 0240 bic.w r2, r2, #64 @ 0x40 8005a52: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8005a54: 687b ldr r3, [r7, #4] 8005a56: 2220 movs r2, #32 8005a58: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8005a5c: 6878 ldr r0, [r7, #4] 8005a5e: f7ff fea9 bl 80057b4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8005a62: 2300 movs r3, #0 } 8005a64: 4618 mov r0, r3 8005a66: 3708 adds r7, #8 8005a68: 46bd mov sp, r7 8005a6a: bd80 pop {r7, pc} 08005a6c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8005a6c: b580 push {r7, lr} 8005a6e: b08c sub sp, #48 @ 0x30 8005a70: af00 add r7, sp, #0 8005a72: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8005a74: 687b ldr r3, [r7, #4] 8005a76: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005a7a: b2db uxtb r3, r3 8005a7c: 2b22 cmp r3, #34 @ 0x22 8005a7e: f040 80ae bne.w 8005bde { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8005a82: 687b ldr r3, [r7, #4] 8005a84: 689b ldr r3, [r3, #8] 8005a86: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005a8a: d117 bne.n 8005abc 8005a8c: 687b ldr r3, [r7, #4] 8005a8e: 691b ldr r3, [r3, #16] 8005a90: 2b00 cmp r3, #0 8005a92: d113 bne.n 8005abc { pdata8bits = NULL; 8005a94: 2300 movs r3, #0 8005a96: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8005a98: 687b ldr r3, [r7, #4] 8005a9a: 6a9b ldr r3, [r3, #40] @ 0x28 8005a9c: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8005a9e: 687b ldr r3, [r7, #4] 8005aa0: 681b ldr r3, [r3, #0] 8005aa2: 685b ldr r3, [r3, #4] 8005aa4: b29b uxth r3, r3 8005aa6: f3c3 0308 ubfx r3, r3, #0, #9 8005aaa: b29a uxth r2, r3 8005aac: 6abb ldr r3, [r7, #40] @ 0x28 8005aae: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8005ab0: 687b ldr r3, [r7, #4] 8005ab2: 6a9b ldr r3, [r3, #40] @ 0x28 8005ab4: 1c9a adds r2, r3, #2 8005ab6: 687b ldr r3, [r7, #4] 8005ab8: 629a str r2, [r3, #40] @ 0x28 8005aba: e026 b.n 8005b0a } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8005abc: 687b ldr r3, [r7, #4] 8005abe: 6a9b ldr r3, [r3, #40] @ 0x28 8005ac0: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8005ac2: 2300 movs r3, #0 8005ac4: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8005ac6: 687b ldr r3, [r7, #4] 8005ac8: 689b ldr r3, [r3, #8] 8005aca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005ace: d007 beq.n 8005ae0 8005ad0: 687b ldr r3, [r7, #4] 8005ad2: 689b ldr r3, [r3, #8] 8005ad4: 2b00 cmp r3, #0 8005ad6: d10a bne.n 8005aee 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 691b ldr r3, [r3, #16] 8005adc: 2b00 cmp r3, #0 8005ade: d106 bne.n 8005aee { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8005ae0: 687b ldr r3, [r7, #4] 8005ae2: 681b ldr r3, [r3, #0] 8005ae4: 685b ldr r3, [r3, #4] 8005ae6: b2da uxtb r2, r3 8005ae8: 6afb ldr r3, [r7, #44] @ 0x2c 8005aea: 701a strb r2, [r3, #0] 8005aec: e008 b.n 8005b00 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8005aee: 687b ldr r3, [r7, #4] 8005af0: 681b ldr r3, [r3, #0] 8005af2: 685b ldr r3, [r3, #4] 8005af4: b2db uxtb r3, r3 8005af6: f003 037f and.w r3, r3, #127 @ 0x7f 8005afa: b2da uxtb r2, r3 8005afc: 6afb ldr r3, [r7, #44] @ 0x2c 8005afe: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8005b00: 687b ldr r3, [r7, #4] 8005b02: 6a9b ldr r3, [r3, #40] @ 0x28 8005b04: 1c5a adds r2, r3, #1 8005b06: 687b ldr r3, [r7, #4] 8005b08: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8005b0a: 687b ldr r3, [r7, #4] 8005b0c: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005b0e: b29b uxth r3, r3 8005b10: 3b01 subs r3, #1 8005b12: b29b uxth r3, r3 8005b14: 687a ldr r2, [r7, #4] 8005b16: 4619 mov r1, r3 8005b18: 85d1 strh r1, [r2, #46] @ 0x2e 8005b1a: 2b00 cmp r3, #0 8005b1c: d15d bne.n 8005bda { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8005b1e: 687b ldr r3, [r7, #4] 8005b20: 681b ldr r3, [r3, #0] 8005b22: 68da ldr r2, [r3, #12] 8005b24: 687b ldr r3, [r7, #4] 8005b26: 681b ldr r3, [r3, #0] 8005b28: f022 0220 bic.w r2, r2, #32 8005b2c: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8005b2e: 687b ldr r3, [r7, #4] 8005b30: 681b ldr r3, [r3, #0] 8005b32: 68da ldr r2, [r3, #12] 8005b34: 687b ldr r3, [r7, #4] 8005b36: 681b ldr r3, [r3, #0] 8005b38: f422 7280 bic.w r2, r2, #256 @ 0x100 8005b3c: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8005b3e: 687b ldr r3, [r7, #4] 8005b40: 681b ldr r3, [r3, #0] 8005b42: 695a ldr r2, [r3, #20] 8005b44: 687b ldr r3, [r7, #4] 8005b46: 681b ldr r3, [r3, #0] 8005b48: f022 0201 bic.w r2, r2, #1 8005b4c: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005b4e: 687b ldr r3, [r7, #4] 8005b50: 2220 movs r2, #32 8005b52: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8005b56: 687b ldr r3, [r7, #4] 8005b58: 2200 movs r2, #0 8005b5a: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005b5c: 687b ldr r3, [r7, #4] 8005b5e: 6b1b ldr r3, [r3, #48] @ 0x30 8005b60: 2b01 cmp r3, #1 8005b62: d135 bne.n 8005bd0 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005b64: 687b ldr r3, [r7, #4] 8005b66: 2200 movs r2, #0 8005b68: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005b6a: 687b ldr r3, [r7, #4] 8005b6c: 681b ldr r3, [r3, #0] 8005b6e: 330c adds r3, #12 8005b70: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b72: 697b ldr r3, [r7, #20] 8005b74: e853 3f00 ldrex r3, [r3] 8005b78: 613b str r3, [r7, #16] return(result); 8005b7a: 693b ldr r3, [r7, #16] 8005b7c: f023 0310 bic.w r3, r3, #16 8005b80: 627b str r3, [r7, #36] @ 0x24 8005b82: 687b ldr r3, [r7, #4] 8005b84: 681b ldr r3, [r3, #0] 8005b86: 330c adds r3, #12 8005b88: 6a7a ldr r2, [r7, #36] @ 0x24 8005b8a: 623a str r2, [r7, #32] 8005b8c: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005b8e: 69f9 ldr r1, [r7, #28] 8005b90: 6a3a ldr r2, [r7, #32] 8005b92: e841 2300 strex r3, r2, [r1] 8005b96: 61bb str r3, [r7, #24] return(result); 8005b98: 69bb ldr r3, [r7, #24] 8005b9a: 2b00 cmp r3, #0 8005b9c: d1e5 bne.n 8005b6a /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8005b9e: 687b ldr r3, [r7, #4] 8005ba0: 681b ldr r3, [r3, #0] 8005ba2: 681b ldr r3, [r3, #0] 8005ba4: f003 0310 and.w r3, r3, #16 8005ba8: 2b10 cmp r3, #16 8005baa: d10a bne.n 8005bc2 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8005bac: 2300 movs r3, #0 8005bae: 60fb str r3, [r7, #12] 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 681b ldr r3, [r3, #0] 8005bb4: 681b ldr r3, [r3, #0] 8005bb6: 60fb str r3, [r7, #12] 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 681b ldr r3, [r3, #0] 8005bbc: 685b ldr r3, [r3, #4] 8005bbe: 60fb str r3, [r7, #12] 8005bc0: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8005bc2: 687b ldr r3, [r7, #4] 8005bc4: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005bc6: 4619 mov r1, r3 8005bc8: 6878 ldr r0, [r7, #4] 8005bca: f7ff fe0e bl 80057ea 8005bce: e002 b.n 8005bd6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8005bd0: 6878 ldr r0, [r7, #4] 8005bd2: f7ff fdf8 bl 80057c6 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8005bd6: 2300 movs r3, #0 8005bd8: e002 b.n 8005be0 } return HAL_OK; 8005bda: 2300 movs r3, #0 8005bdc: e000 b.n 8005be0 } else { return HAL_BUSY; 8005bde: 2302 movs r3, #2 } } 8005be0: 4618 mov r0, r3 8005be2: 3730 adds r7, #48 @ 0x30 8005be4: 46bd mov sp, r7 8005be6: bd80 pop {r7, pc} 08005be8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8005be8: b580 push {r7, lr} 8005bea: b084 sub sp, #16 8005bec: af00 add r7, sp, #0 8005bee: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 681b ldr r3, [r3, #0] 8005bf4: 691b ldr r3, [r3, #16] 8005bf6: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8005bfa: 687b ldr r3, [r7, #4] 8005bfc: 68da ldr r2, [r3, #12] 8005bfe: 687b ldr r3, [r7, #4] 8005c00: 681b ldr r3, [r3, #0] 8005c02: 430a orrs r2, r1 8005c04: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8005c06: 687b ldr r3, [r7, #4] 8005c08: 689a ldr r2, [r3, #8] 8005c0a: 687b ldr r3, [r7, #4] 8005c0c: 691b ldr r3, [r3, #16] 8005c0e: 431a orrs r2, r3 8005c10: 687b ldr r3, [r7, #4] 8005c12: 695b ldr r3, [r3, #20] 8005c14: 4313 orrs r3, r2 8005c16: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8005c18: 687b ldr r3, [r7, #4] 8005c1a: 681b ldr r3, [r3, #0] 8005c1c: 68db ldr r3, [r3, #12] 8005c1e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8005c22: f023 030c bic.w r3, r3, #12 8005c26: 687a ldr r2, [r7, #4] 8005c28: 6812 ldr r2, [r2, #0] 8005c2a: 68b9 ldr r1, [r7, #8] 8005c2c: 430b orrs r3, r1 8005c2e: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8005c30: 687b ldr r3, [r7, #4] 8005c32: 681b ldr r3, [r3, #0] 8005c34: 695b ldr r3, [r3, #20] 8005c36: f423 7140 bic.w r1, r3, #768 @ 0x300 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 699a ldr r2, [r3, #24] 8005c3e: 687b ldr r3, [r7, #4] 8005c40: 681b ldr r3, [r3, #0] 8005c42: 430a orrs r2, r1 8005c44: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8005c46: 687b ldr r3, [r7, #4] 8005c48: 681b ldr r3, [r3, #0] 8005c4a: 4a2c ldr r2, [pc, #176] @ (8005cfc ) 8005c4c: 4293 cmp r3, r2 8005c4e: d103 bne.n 8005c58 { pclk = HAL_RCC_GetPCLK2Freq(); 8005c50: f7ff f95a bl 8004f08 8005c54: 60f8 str r0, [r7, #12] 8005c56: e002 b.n 8005c5e } else { pclk = HAL_RCC_GetPCLK1Freq(); 8005c58: f7ff f942 bl 8004ee0 8005c5c: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8005c5e: 68fa ldr r2, [r7, #12] 8005c60: 4613 mov r3, r2 8005c62: 009b lsls r3, r3, #2 8005c64: 4413 add r3, r2 8005c66: 009a lsls r2, r3, #2 8005c68: 441a add r2, r3 8005c6a: 687b ldr r3, [r7, #4] 8005c6c: 685b ldr r3, [r3, #4] 8005c6e: 009b lsls r3, r3, #2 8005c70: fbb2 f3f3 udiv r3, r2, r3 8005c74: 4a22 ldr r2, [pc, #136] @ (8005d00 ) 8005c76: fba2 2303 umull r2, r3, r2, r3 8005c7a: 095b lsrs r3, r3, #5 8005c7c: 0119 lsls r1, r3, #4 8005c7e: 68fa ldr r2, [r7, #12] 8005c80: 4613 mov r3, r2 8005c82: 009b lsls r3, r3, #2 8005c84: 4413 add r3, r2 8005c86: 009a lsls r2, r3, #2 8005c88: 441a add r2, r3 8005c8a: 687b ldr r3, [r7, #4] 8005c8c: 685b ldr r3, [r3, #4] 8005c8e: 009b lsls r3, r3, #2 8005c90: fbb2 f2f3 udiv r2, r2, r3 8005c94: 4b1a ldr r3, [pc, #104] @ (8005d00 ) 8005c96: fba3 0302 umull r0, r3, r3, r2 8005c9a: 095b lsrs r3, r3, #5 8005c9c: 2064 movs r0, #100 @ 0x64 8005c9e: fb00 f303 mul.w r3, r0, r3 8005ca2: 1ad3 subs r3, r2, r3 8005ca4: 011b lsls r3, r3, #4 8005ca6: 3332 adds r3, #50 @ 0x32 8005ca8: 4a15 ldr r2, [pc, #84] @ (8005d00 ) 8005caa: fba2 2303 umull r2, r3, r2, r3 8005cae: 095b lsrs r3, r3, #5 8005cb0: f003 03f0 and.w r3, r3, #240 @ 0xf0 8005cb4: 4419 add r1, r3 8005cb6: 68fa ldr r2, [r7, #12] 8005cb8: 4613 mov r3, r2 8005cba: 009b lsls r3, r3, #2 8005cbc: 4413 add r3, r2 8005cbe: 009a lsls r2, r3, #2 8005cc0: 441a add r2, r3 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 685b ldr r3, [r3, #4] 8005cc6: 009b lsls r3, r3, #2 8005cc8: fbb2 f2f3 udiv r2, r2, r3 8005ccc: 4b0c ldr r3, [pc, #48] @ (8005d00 ) 8005cce: fba3 0302 umull r0, r3, r3, r2 8005cd2: 095b lsrs r3, r3, #5 8005cd4: 2064 movs r0, #100 @ 0x64 8005cd6: fb00 f303 mul.w r3, r0, r3 8005cda: 1ad3 subs r3, r2, r3 8005cdc: 011b lsls r3, r3, #4 8005cde: 3332 adds r3, #50 @ 0x32 8005ce0: 4a07 ldr r2, [pc, #28] @ (8005d00 ) 8005ce2: fba2 2303 umull r2, r3, r2, r3 8005ce6: 095b lsrs r3, r3, #5 8005ce8: f003 020f and.w r2, r3, #15 8005cec: 687b ldr r3, [r7, #4] 8005cee: 681b ldr r3, [r3, #0] 8005cf0: 440a add r2, r1 8005cf2: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8005cf4: bf00 nop 8005cf6: 3710 adds r7, #16 8005cf8: 46bd mov sp, r7 8005cfa: bd80 pop {r7, pc} 8005cfc: 40013800 .word 0x40013800 8005d00: 51eb851f .word 0x51eb851f 08005d04 : 8005d04: 4603 mov r3, r0 8005d06: 4402 add r2, r0 8005d08: 4293 cmp r3, r2 8005d0a: d100 bne.n 8005d0e 8005d0c: 4770 bx lr 8005d0e: f803 1b01 strb.w r1, [r3], #1 8005d12: e7f9 b.n 8005d08 08005d14 <__errno>: 8005d14: 4b01 ldr r3, [pc, #4] @ (8005d1c <__errno+0x8>) 8005d16: 6818 ldr r0, [r3, #0] 8005d18: 4770 bx lr 8005d1a: bf00 nop 8005d1c: 20000028 .word 0x20000028 08005d20 <__libc_init_array>: 8005d20: b570 push {r4, r5, r6, lr} 8005d22: 2600 movs r6, #0 8005d24: 4d0c ldr r5, [pc, #48] @ (8005d58 <__libc_init_array+0x38>) 8005d26: 4b0d ldr r3, [pc, #52] @ (8005d5c <__libc_init_array+0x3c>) 8005d28: 1b5b subs r3, r3, r5 8005d2a: 109c asrs r4, r3, #2 8005d2c: 42a6 cmp r6, r4 8005d2e: d109 bne.n 8005d44 <__libc_init_array+0x24> 8005d30: 2600 movs r6, #0 8005d32: f000 f8cd bl 8005ed0 <_init> 8005d36: 4d0a ldr r5, [pc, #40] @ (8005d60 <__libc_init_array+0x40>) 8005d38: 4b0a ldr r3, [pc, #40] @ (8005d64 <__libc_init_array+0x44>) 8005d3a: 1b5b subs r3, r3, r5 8005d3c: 109c asrs r4, r3, #2 8005d3e: 42a6 cmp r6, r4 8005d40: d105 bne.n 8005d4e <__libc_init_array+0x2e> 8005d42: bd70 pop {r4, r5, r6, pc} 8005d44: f855 3b04 ldr.w r3, [r5], #4 8005d48: 4798 blx r3 8005d4a: 3601 adds r6, #1 8005d4c: e7ee b.n 8005d2c <__libc_init_array+0xc> 8005d4e: f855 3b04 ldr.w r3, [r5], #4 8005d52: 4798 blx r3 8005d54: 3601 adds r6, #1 8005d56: e7f2 b.n 8005d3e <__libc_init_array+0x1e> 8005d58: 08005f70 .word 0x08005f70 8005d5c: 08005f70 .word 0x08005f70 8005d60: 08005f70 .word 0x08005f70 8005d64: 08005f74 .word 0x08005f74 08005d68 : 8005d68: b538 push {r3, r4, r5, lr} 8005d6a: 4604 mov r4, r0 8005d6c: f000 f81a bl 8005da4 <__ieee754_sqrtf> 8005d70: 4621 mov r1, r4 8005d72: 4605 mov r5, r0 8005d74: 4620 mov r0, r4 8005d76: f7fa ffd3 bl 8000d20 <__aeabi_fcmpun> 8005d7a: b920 cbnz r0, 8005d86 8005d7c: 4620 mov r0, r4 8005d7e: 2100 movs r1, #0 8005d80: f7fa ffa6 bl 8000cd0 <__aeabi_fcmplt> 8005d84: b908 cbnz r0, 8005d8a 8005d86: 4628 mov r0, r5 8005d88: bd38 pop {r3, r4, r5, pc} 8005d8a: f7ff ffc3 bl 8005d14 <__errno> 8005d8e: 2221 movs r2, #33 @ 0x21 8005d90: 4603 mov r3, r0 8005d92: 2100 movs r1, #0 8005d94: 601a str r2, [r3, #0] 8005d96: 4608 mov r0, r1 8005d98: f7fa feb0 bl 8000afc <__aeabi_fdiv> 8005d9c: 4605 mov r5, r0 8005d9e: 4628 mov r0, r5 8005da0: bd38 pop {r3, r4, r5, pc} 8005da2: bf00 nop 08005da4 <__ieee754_sqrtf>: 8005da4: f020 4200 bic.w r2, r0, #2147483648 @ 0x80000000 8005da8: f1b2 4fff cmp.w r2, #2139095040 @ 0x7f800000 8005dac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8005db0: 4604 mov r4, r0 8005db2: d24f bcs.n 8005e54 <__ieee754_sqrtf+0xb0> 8005db4: 2a00 cmp r2, #0 8005db6: d04b beq.n 8005e50 <__ieee754_sqrtf+0xac> 8005db8: 2800 cmp r0, #0 8005dba: 4603 mov r3, r0 8005dbc: db54 blt.n 8005e68 <__ieee754_sqrtf+0xc4> 8005dbe: f010 42ff ands.w r2, r0, #2139095040 @ 0x7f800000 8005dc2: d14f bne.n 8005e64 <__ieee754_sqrtf+0xc0> 8005dc4: 005b lsls r3, r3, #1 8005dc6: 0218 lsls r0, r3, #8 8005dc8: 4611 mov r1, r2 8005dca: f102 0201 add.w r2, r2, #1 8005dce: d5f9 bpl.n 8005dc4 <__ieee754_sqrtf+0x20> 8005dd0: 4249 negs r1, r1 8005dd2: 2400 movs r4, #0 8005dd4: f3c3 0216 ubfx r2, r3, #0, #23 8005dd8: f1a1 057f sub.w r5, r1, #127 @ 0x7f 8005ddc: 07cb lsls r3, r1, #31 8005dde: f04f 0e19 mov.w lr, #25 8005de2: f04f 7c80 mov.w ip, #16777216 @ 0x1000000 8005de6: 4621 mov r1, r4 8005de8: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8005dec: bf58 it pl 8005dee: 0052 lslpl r2, r2, #1 8005df0: 106d asrs r5, r5, #1 8005df2: 0052 lsls r2, r2, #1 8005df4: eb01 030c add.w r3, r1, ip 8005df8: 4293 cmp r3, r2 8005dfa: bfcf iteee gt 8005dfc: 4613 movgt r3, r2 8005dfe: eb03 010c addle.w r1, r3, ip 8005e02: 4464 addle r4, ip 8005e04: 1ad3 suble r3, r2, r3 8005e06: f1be 0e01 subs.w lr, lr, #1 8005e0a: ea4f 0243 mov.w r2, r3, lsl #1 8005e0e: ea4f 0c5c mov.w ip, ip, lsr #1 8005e12: d1ef bne.n 8005df4 <__ieee754_sqrtf+0x50> 8005e14: b1bb cbz r3, 8005e46 <__ieee754_sqrtf+0xa2> 8005e16: 4e1a ldr r6, [pc, #104] @ (8005e80 <__ieee754_sqrtf+0xdc>) 8005e18: 4f1a ldr r7, [pc, #104] @ (8005e84 <__ieee754_sqrtf+0xe0>) 8005e1a: 6830 ldr r0, [r6, #0] 8005e1c: 6839 ldr r1, [r7, #0] 8005e1e: f7fa fcaf bl 8000780 <__aeabi_fsub> 8005e22: f8d6 8000 ldr.w r8, [r6] 8005e26: 4601 mov r1, r0 8005e28: 4640 mov r0, r8 8005e2a: f7fa ff5b bl 8000ce4 <__aeabi_fcmple> 8005e2e: b150 cbz r0, 8005e46 <__ieee754_sqrtf+0xa2> 8005e30: 6830 ldr r0, [r6, #0] 8005e32: 6839 ldr r1, [r7, #0] 8005e34: f7fa fca6 bl 8000784 <__addsf3> 8005e38: 6836 ldr r6, [r6, #0] 8005e3a: 4601 mov r1, r0 8005e3c: 4630 mov r0, r6 8005e3e: f7fa ff47 bl 8000cd0 <__aeabi_fcmplt> 8005e42: b1c8 cbz r0, 8005e78 <__ieee754_sqrtf+0xd4> 8005e44: 3402 adds r4, #2 8005e46: 1060 asrs r0, r4, #1 8005e48: f100 507c add.w r0, r0, #1056964608 @ 0x3f000000 8005e4c: eb00 50c5 add.w r0, r0, r5, lsl #23 8005e50: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8005e54: 4601 mov r1, r0 8005e56: f7fa fd9d bl 8000994 <__aeabi_fmul> 8005e5a: 4621 mov r1, r4 8005e5c: f7fa fc92 bl 8000784 <__addsf3> 8005e60: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8005e64: 15c1 asrs r1, r0, #23 8005e66: e7b4 b.n 8005dd2 <__ieee754_sqrtf+0x2e> 8005e68: 4601 mov r1, r0 8005e6a: f7fa fc89 bl 8000780 <__aeabi_fsub> 8005e6e: 4601 mov r1, r0 8005e70: f7fa fe44 bl 8000afc <__aeabi_fdiv> 8005e74: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8005e78: 3401 adds r4, #1 8005e7a: f024 0401 bic.w r4, r4, #1 8005e7e: e7e2 b.n 8005e46 <__ieee754_sqrtf+0xa2> 8005e80: 08005f64 .word 0x08005f64 8005e84: 08005f60 .word 0x08005f60 08005e88 : 8005e88: b508 push {r3, lr} 8005e8a: f3c0 53c7 ubfx r3, r0, #23, #8 8005e8e: 3b7f subs r3, #127 @ 0x7f 8005e90: 2b16 cmp r3, #22 8005e92: 4601 mov r1, r0 8005e94: dc0e bgt.n 8005eb4 8005e96: 2b00 cmp r3, #0 8005e98: 4602 mov r2, r0 8005e9a: db10 blt.n 8005ebe 8005e9c: 480b ldr r0, [pc, #44] @ (8005ecc ) 8005e9e: 4118 asrs r0, r3 8005ea0: 4201 tst r1, r0 8005ea2: d005 beq.n 8005eb0 8005ea4: f44f 0180 mov.w r1, #4194304 @ 0x400000 8005ea8: 4119 asrs r1, r3 8005eaa: 4411 add r1, r2 8005eac: ea21 0100 bic.w r1, r1, r0 8005eb0: 4608 mov r0, r1 8005eb2: bd08 pop {r3, pc} 8005eb4: 2b80 cmp r3, #128 @ 0x80 8005eb6: d1fb bne.n 8005eb0 8005eb8: f7fa fc64 bl 8000784 <__addsf3> 8005ebc: bd08 pop {r3, pc} 8005ebe: 3301 adds r3, #1 8005ec0: f000 4100 and.w r1, r0, #2147483648 @ 0x80000000 8005ec4: d1f4 bne.n 8005eb0 8005ec6: f041 517e orr.w r1, r1, #1065353216 @ 0x3f800000 8005eca: e7f1 b.n 8005eb0 8005ecc: 007fffff .word 0x007fffff 08005ed0 <_init>: 8005ed0: b5f8 push {r3, r4, r5, r6, r7, lr} 8005ed2: bf00 nop 8005ed4: bcf8 pop {r3, r4, r5, r6, r7} 8005ed6: bc08 pop {r3} 8005ed8: 469e mov lr, r3 8005eda: 4770 bx lr 08005edc <_fini>: 8005edc: b5f8 push {r3, r4, r5, r6, r7, lr} 8005ede: bf00 nop 8005ee0: bcf8 pop {r3, r4, r5, r6, r7} 8005ee2: bc08 pop {r3} 8005ee4: 469e mov lr, r3 8005ee6: 4770 bx lr