: /** * @brief The application entry point. * @retval int */ int main(void) { 8001c64: b580 push {r7, lr} 8001c66: b08c sub sp, #48 @ 0x30 8001c68: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ uint8_t tempString[15] = {0}; 8001c6a: f107 0308 add.w r3, r7, #8 8001c6e: 2200 movs r2, #0 8001c70: 601a str r2, [r3, #0] 8001c72: 605a str r2, [r3, #4] 8001c74: 609a str r2, [r3, #8] 8001c76: f8c3 200b str.w r2, [r3, #11] uint8_t averages = 0; 8001c7a: 2300 movs r3, #0 8001c7c: f887 302f strb.w r3, [r7, #47] @ 0x2f uint8_t newline = '\n'; 8001c80: 230a movs r3, #10 8001c82: 71fb strb r3, [r7, #7] // Variables for timing uint32_t previous_millis_green = 0; 8001c84: 2300 movs r3, #0 8001c86: 62bb str r3, [r7, #40] @ 0x28 uint32_t previous_millis_red = 0; 8001c88: 2300 movs r3, #0 8001c8a: 627b str r3, [r7, #36] @ 0x24 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001c8c: f000 fd04 bl 8002698 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001c90: f000 f944 bl 8001f1c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001c94: f7ff fe7e bl 8001994 MX_ADC1_Init(); 8001c98: f7ff fa66 bl 8001168 MX_ADC2_Init(); 8001c9c: f7ff faa2 bl 80011e4 MX_I2C1_Init(); 8001ca0: f7ff ff18 bl 8001ad4 MX_I2C2_Init(); 8001ca4: f7ff ff44 bl 8001b30 MX_USART1_UART_Init(); 8001ca8: f000 fc52 bl 8002550 MX_TIM3_Init(); 8001cac: f000 fbdc bl 8002468 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim3); 8001cb0: 488b ldr r0, [pc, #556] @ (8001ee0 ) 8001cb2: f003 f83d bl 8004d30 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET); // LED Green Off 8001cb6: 2201 movs r2, #1 8001cb8: 2110 movs r1, #16 8001cba: 488a ldr r0, [pc, #552] @ (8001ee4 ) 8001cbc: f001 fabb bl 8003236 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); // LED Red Off 8001cc0: 2201 movs r2, #1 8001cc2: 2120 movs r1, #32 8001cc4: 4887 ldr r0, [pc, #540] @ (8001ee4 ) 8001cc6: f001 fab6 bl 8003236 digital_outputs_init(); 8001cca: f7ff fdcb bl 8001864 rs485_init(); 8001cce: f000 fa6b bl 80021a8 ADS1015_Init(); // Initializes pH Measurement 8001cd2: f7ff fb77 bl 80013c4 AD5934_Init(); // Initializes CE and RTD Measurement 8001cd6: f7fe fdc5 bl 8000864 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while(averages<15) 8001cda: e02d b.n 8001d38 { AD5934_Process_System(); 8001cdc: f7fe ff62 bl 8000ba4 ADS1015_Process_System(); 8001ce0: f7ff fbce bl 8001480 current_millis = g_ms_counter; 8001ce4: 4b80 ldr r3, [pc, #512] @ (8001ee8 ) 8001ce6: 681b ldr r3, [r3, #0] 8001ce8: 623b str r3, [r7, #32] if((current_millis % 20) == 0) // Send data each 20ms 8001cea: 6a39 ldr r1, [r7, #32] 8001cec: 4b7f ldr r3, [pc, #508] @ (8001eec ) 8001cee: fba3 2301 umull r2, r3, r3, r1 8001cf2: 091a lsrs r2, r3, #4 8001cf4: 4613 mov r3, r2 8001cf6: 009b lsls r3, r3, #2 8001cf8: 4413 add r3, r2 8001cfa: 009b lsls r3, r3, #2 8001cfc: 1aca subs r2, r1, r3 8001cfe: 2a00 cmp r2, #0 8001d00: d11a bne.n 8001d38 { if (g_ref_filter.value_valid) // Reference Resistor on Board: 100 Ohms or 1000 Ohms 8001d02: 4b7b ldr r3, [pc, #492] @ (8001ef0 ) 8001d04: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001d08: 2b00 cmp r3, #0 8001d0a: d015 beq.n 8001d38 { reference_resistor = g_ref_filter.filtered_value; 8001d0c: 4b78 ldr r3, [pc, #480] @ (8001ef0 ) 8001d0e: 6b9b ldr r3, [r3, #56] @ 0x38 8001d10: 4a78 ldr r2, [pc, #480] @ (8001ef4 ) 8001d12: 6013 str r3, [r2, #0] uint16_t reference_final = AD5934_REF_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(g_ref_filter.filtered_value, current_ref_mux); 8001d14: 4b76 ldr r3, [pc, #472] @ (8001ef0 ) 8001d16: 6b9b ldr r3, [r3, #56] @ 0x38 8001d18: 4a77 ldr r2, [pc, #476] @ (8001ef8 ) 8001d1a: 7812 ldrb r2, [r2, #0] 8001d1c: 4611 mov r1, r2 8001d1e: 4618 mov r0, r3 8001d20: f7fe feb2 bl 8000a88 8001d24: 4603 mov r3, r0 8001d26: f5c3 637f rsb r3, r3, #4080 @ 0xff0 8001d2a: 330f adds r3, #15 8001d2c: 833b strh r3, [r7, #24] averages++; 8001d2e: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8001d32: 3301 adds r3, #1 8001d34: f887 302f strb.w r3, [r7, #47] @ 0x2f while(averages<15) 8001d38: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8001d3c: 2b0e cmp r3, #14 8001d3e: d9cd bls.n 8001cdc } } } digital_outputs_toggle(0); 8001d40: 2000 movs r0, #0 8001d42: f7ff fe09 bl 8001958 digital_outputs_toggle(1); 8001d46: 2001 movs r0, #1 8001d48: f7ff fe06 bl 8001958 digital_outputs_toggle(2); 8001d4c: 2002 movs r0, #2 8001d4e: f7ff fe03 bl 8001958 digital_outputs_toggle(3); 8001d52: 2003 movs r0, #3 8001d54: f7ff fe00 bl 8001958 digital_outputs_toggle(4); 8001d58: 2004 movs r0, #4 8001d5a: f7ff fdfd bl 8001958 digital_outputs_toggle(5); 8001d5e: 2005 movs r0, #5 8001d60: f7ff fdfa bl 8001958 digital_outputs_toggle(6); 8001d64: 2006 movs r0, #6 8001d66: f7ff fdf7 bl 8001958 digital_outputs_toggle(7); 8001d6a: 2007 movs r0, #7 8001d6c: f7ff fdf4 bl 8001958 while (1) { AD5934_Process_System(); 8001d70: f7fe ff18 bl 8000ba4 ADS1015_Process_System(); 8001d74: f7ff fb84 bl 8001480 current_millis = g_ms_counter; 8001d78: 4b5b ldr r3, [pc, #364] @ (8001ee8 ) 8001d7a: 681b ldr r3, [r3, #0] 8001d7c: 623b str r3, [r7, #32] if((current_millis % 500) == 0) // Send data each 100ms 8001d7e: 6a3a ldr r2, [r7, #32] 8001d80: 4b5e ldr r3, [pc, #376] @ (8001efc ) 8001d82: fba3 1302 umull r1, r3, r3, r2 8001d86: 095b lsrs r3, r3, #5 8001d88: f44f 71fa mov.w r1, #500 @ 0x1f4 8001d8c: fb01 f303 mul.w r3, r1, r3 8001d90: 1ad3 subs r3, r2, r3 8001d92: 2b00 cmp r3, #0 8001d94: f040 8095 bne.w 8001ec2 //FloatToString(tempString, ref_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); rs485_send_broadcast(&newline, 1); }*/ if (g_rtd_filter.value_valid) // PT100 or PT1000 in °C 8001d98: 4b59 ldr r3, [pc, #356] @ (8001f00 ) 8001d9a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001d9e: 2b00 cmp r3, #0 8001da0: d030 beq.n 8001e04 { temperature_RTD = AD5934_Calculate_Temperature(reference_resistor, g_rtd_filter.filtered_value); 8001da2: 4b54 ldr r3, [pc, #336] @ (8001ef4 ) 8001da4: 681b ldr r3, [r3, #0] 8001da6: 4a56 ldr r2, [pc, #344] @ (8001f00 ) 8001da8: 6b92 ldr r2, [r2, #56] @ 0x38 8001daa: 4611 mov r1, r2 8001dac: 4618 mov r0, r3 8001dae: f7fe fda5 bl 80008fc 8001db2: 4603 mov r3, r0 8001db4: 4a53 ldr r2, [pc, #332] @ (8001f04 ) 8001db6: 6013 str r3, [r2, #0] uint16_t rtd_final = AD5934_RTD_OUT_SCALE_MAX - AD5934_Compress_To_IntScale(temperature_RTD, current_rtd_mux); 8001db8: 4b52 ldr r3, [pc, #328] @ (8001f04 ) 8001dba: 681b ldr r3, [r3, #0] 8001dbc: 4a52 ldr r2, [pc, #328] @ (8001f08 ) 8001dbe: 7812 ldrb r2, [r2, #0] 8001dc0: 4611 mov r1, r2 8001dc2: 4618 mov r0, r3 8001dc4: f7fe fe60 bl 8000a88 8001dc8: 4603 mov r3, r0 8001dca: f5c3 7348 rsb r3, r3, #800 @ 0x320 8001dce: 83fb strh r3, [r7, #30] intToStr(rtd_final, tempString); 8001dd0: f9b7 301e ldrsh.w r3, [r7, #30] 8001dd4: f107 0208 add.w r2, r7, #8 8001dd8: 4611 mov r1, r2 8001dda: 4618 mov r0, r3 8001ddc: f000 f8ee bl 8001fbc //float rtd_final = g_rtd_filter.filtered_value; //FloatToString(tempString, rtd_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001de0: f107 0308 add.w r3, r7, #8 8001de4: 4618 mov r0, r3 8001de6: f7fe f9b1 bl 800014c 8001dea: 4603 mov r3, r0 8001dec: b29a uxth r2, r3 8001dee: f107 0308 add.w r3, r7, #8 8001df2: 4611 mov r1, r2 8001df4: 4618 mov r0, r3 8001df6: f000 fa03 bl 8002200 rs485_send_broadcast(&newline, 1); 8001dfa: 1dfb adds r3, r7, #7 8001dfc: 2101 movs r1, #1 8001dfe: 4618 mov r0, r3 8001e00: f000 f9fe bl 8002200 } if (g_ec_filter.value_valid) // EC 8001e04: 4b41 ldr r3, [pc, #260] @ (8001f0c ) 8001e06: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001e0a: 2b00 cmp r3, #0 8001e0c: d02e beq.n 8001e6c { thermal_compensaded_EC = AD5934_EC_Compensate_Magnitude_To_25C(g_ec_filter.filtered_value, temperature_RTD); 8001e0e: 4b3f ldr r3, [pc, #252] @ (8001f0c ) 8001e10: 6b9b ldr r3, [r3, #56] @ 0x38 8001e12: 4a3c ldr r2, [pc, #240] @ (8001f04 ) 8001e14: 6812 ldr r2, [r2, #0] 8001e16: 4611 mov r1, r2 8001e18: 4618 mov r0, r3 8001e1a: f7fe fdc7 bl 80009ac 8001e1e: 4603 mov r3, r0 8001e20: 4a3b ldr r2, [pc, #236] @ (8001f10 ) 8001e22: 6013 str r3, [r2, #0] uint16_t ec_final = AD5934_Compress_To_IntScale(thermal_compensaded_EC, current_ec_mux); 8001e24: 4b3a ldr r3, [pc, #232] @ (8001f10 ) 8001e26: 681b ldr r3, [r3, #0] 8001e28: 4a3a ldr r2, [pc, #232] @ (8001f14 ) 8001e2a: 7812 ldrb r2, [r2, #0] 8001e2c: 4611 mov r1, r2 8001e2e: 4618 mov r0, r3 8001e30: f7fe fe2a bl 8000a88 8001e34: 4603 mov r3, r0 8001e36: 83bb strh r3, [r7, #28] intToStr(ec_final, tempString); 8001e38: f9b7 301c ldrsh.w r3, [r7, #28] 8001e3c: f107 0208 add.w r2, r7, #8 8001e40: 4611 mov r1, r2 8001e42: 4618 mov r0, r3 8001e44: f000 f8ba bl 8001fbc // float ec_final = g_ec_filter.filtered_value; // FloatToString(tempString, ec_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001e48: f107 0308 add.w r3, r7, #8 8001e4c: 4618 mov r0, r3 8001e4e: f7fe f97d bl 800014c 8001e52: 4603 mov r3, r0 8001e54: b29a uxth r2, r3 8001e56: f107 0308 add.w r3, r7, #8 8001e5a: 4611 mov r1, r2 8001e5c: 4618 mov r0, r3 8001e5e: f000 f9cf bl 8002200 rs485_send_broadcast(&newline, 1); 8001e62: 1dfb adds r3, r7, #7 8001e64: 2101 movs r1, #1 8001e66: 4618 mov r0, r3 8001e68: f000 f9ca bl 8002200 } if (g_ph_filter.value_valid) // pH 8001e6c: 4b2a ldr r3, [pc, #168] @ (8001f18 ) 8001e6e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8001e72: 2b00 cmp r3, #0 8001e74: d020 beq.n 8001eb8 { uint16_t ph_final = ADS1015_Compress_To_IntScale(g_ph_filter.filtered_value); 8001e76: 4b28 ldr r3, [pc, #160] @ (8001f18 ) 8001e78: 6b9b ldr r3, [r3, #56] @ 0x38 8001e7a: 4618 mov r0, r3 8001e7c: f7ff fabc bl 80013f8 8001e80: 4603 mov r3, r0 8001e82: 837b strh r3, [r7, #26] intToStr(ph_final, tempString); 8001e84: f9b7 301a ldrsh.w r3, [r7, #26] 8001e88: f107 0208 add.w r2, r7, #8 8001e8c: 4611 mov r1, r2 8001e8e: 4618 mov r0, r3 8001e90: f000 f894 bl 8001fbc //float ph_final = g_ph_filter.filtered_value; //FloatToString(tempString, ph_final); rs485_send_broadcast(tempString, (strlen((uint8_t*)tempString))); 8001e94: f107 0308 add.w r3, r7, #8 8001e98: 4618 mov r0, r3 8001e9a: f7fe f957 bl 800014c 8001e9e: 4603 mov r3, r0 8001ea0: b29a uxth r2, r3 8001ea2: f107 0308 add.w r3, r7, #8 8001ea6: 4611 mov r1, r2 8001ea8: 4618 mov r0, r3 8001eaa: f000 f9a9 bl 8002200 rs485_send_broadcast(&newline, 1); 8001eae: 1dfb adds r3, r7, #7 8001eb0: 2101 movs r1, #1 8001eb2: 4618 mov r0, r3 8001eb4: f000 f9a4 bl 8002200 } rs485_send_broadcast(&newline, 1); 8001eb8: 1dfb adds r3, r7, #7 8001eba: 2101 movs r1, #1 8001ebc: 4618 mov r0, r3 8001ebe: f000 f99f bl 8002200 } // Piscar LED verde em PB4 a cada 1 segundo if ((current_millis - previous_millis_green) >= 1000) 8001ec2: 6a3a ldr r2, [r7, #32] 8001ec4: 6abb ldr r3, [r7, #40] @ 0x28 8001ec6: 1ad3 subs r3, r2, r3 8001ec8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001ecc: f4ff af50 bcc.w 8001d70 { previous_millis_green = current_millis; 8001ed0: 6a3b ldr r3, [r7, #32] 8001ed2: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_4); 8001ed4: 2110 movs r1, #16 8001ed6: 4803 ldr r0, [pc, #12] @ (8001ee4 ) 8001ed8: f001 f9c5 bl 8003266 AD5934_Process_System(); 8001edc: e748 b.n 8001d70 8001ede: bf00 nop 8001ee0: 20000310 .word 0x20000310 8001ee4: 40010c00 .word 0x40010c00 8001ee8: 20000080 .word 0x20000080 8001eec: cccccccd .word 0xcccccccd 8001ef0: 20000114 .word 0x20000114 8001ef4: 20000084 .word 0x20000084 8001ef8: 20000091 .word 0x20000091 8001efc: 10624dd3 .word 0x10624dd3 8001f00: 20000094 .word 0x20000094 8001f04: 20000088 .word 0x20000088 8001f08: 20000002 .word 0x20000002 8001f0c: 200000d4 .word 0x200000d4 8001f10: 2000008c .word 0x2000008c 8001f14: 20000001 .word 0x20000001 8001f18: 200001c8 .word 0x200001c8 08001f1c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001f1c: b580 push {r7, lr} 8001f1e: b094 sub sp, #80 @ 0x50 8001f20: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001f22: f107 0328 add.w r3, r7, #40 @ 0x28 8001f26: 2228 movs r2, #40 @ 0x28 8001f28: 2100 movs r1, #0 8001f2a: 4618 mov r0, r3 8001f2c: f004 f8b8 bl 80060a0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001f30: f107 0314 add.w r3, r7, #20 8001f34: 2200 movs r2, #0 8001f36: 601a str r2, [r3, #0] 8001f38: 605a str r2, [r3, #4] 8001f3a: 609a str r2, [r3, #8] 8001f3c: 60da str r2, [r3, #12] 8001f3e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001f40: 1d3b adds r3, r7, #4 8001f42: 2200 movs r2, #0 8001f44: 601a str r2, [r3, #0] 8001f46: 605a str r2, [r3, #4] 8001f48: 609a str r2, [r3, #8] 8001f4a: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001f4c: 2301 movs r3, #1 8001f4e: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001f50: f44f 3380 mov.w r3, #65536 @ 0x10000 8001f54: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8001f56: 2300 movs r3, #0 8001f58: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001f5a: f107 0328 add.w r3, r7, #40 @ 0x28 8001f5e: 4618 mov r0, r3 8001f60: f002 f9ce bl 8004300 8001f64: 4603 mov r3, r0 8001f66: 2b00 cmp r3, #0 8001f68: d001 beq.n 8001f6e { Error_Handler(); 8001f6a: f000 f90b bl 8002184 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001f6e: 230f movs r3, #15 8001f70: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8001f72: 2301 movs r3, #1 8001f74: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001f76: 2300 movs r3, #0 8001f78: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001f7a: 2300 movs r3, #0 8001f7c: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001f7e: 2300 movs r3, #0 8001f80: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8001f82: f107 0314 add.w r3, r7, #20 8001f86: 2100 movs r1, #0 8001f88: 4618 mov r0, r3 8001f8a: f002 fc3b bl 8004804 8001f8e: 4603 mov r3, r0 8001f90: 2b00 cmp r3, #0 8001f92: d001 beq.n 8001f98 { Error_Handler(); 8001f94: f000 f8f6 bl 8002184 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8001f98: 2302 movs r3, #2 8001f9a: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; 8001f9c: f44f 4340 mov.w r3, #49152 @ 0xc000 8001fa0: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001fa2: 1d3b adds r3, r7, #4 8001fa4: 4618 mov r0, r3 8001fa6: f002 fdbd bl 8004b24 8001faa: 4603 mov r3, r0 8001fac: 2b00 cmp r3, #0 8001fae: d001 beq.n 8001fb4 { Error_Handler(); 8001fb0: f000 f8e8 bl 8002184 } } 8001fb4: bf00 nop 8001fb6: 3750 adds r7, #80 @ 0x50 8001fb8: 46bd mov sp, r7 8001fba: bd80 pop {r7, pc} 08001fbc : } void intToStr(int16_t N, uint8_t *str) { 8001fbc: b480 push {r7} 8001fbe: b087 sub sp, #28 8001fc0: af00 add r7, sp, #0 8001fc2: 4603 mov r3, r0 8001fc4: 6039 str r1, [r7, #0] 8001fc6: 80fb strh r3, [r7, #6] int16_t i = 0; 8001fc8: 2300 movs r3, #0 8001fca: 82fb strh r3, [r7, #22] int16_t sign = N; 8001fcc: 88fb ldrh r3, [r7, #6] 8001fce: 823b strh r3, [r7, #16] uint8_t max_len = 15; // Tamanho máximo do buffer 8001fd0: 230f movs r3, #15 8001fd2: 73fb strb r3, [r7, #15] uint8_t width = 4; // mínimo 4 caracteres 8001fd4: 2304 movs r3, #4 8001fd6: 757b strb r3, [r7, #21] // Trata o caso do número zero isoladamente if (N == 0) 8001fd8: f9b7 3006 ldrsh.w r3, [r7, #6] 8001fdc: 2b00 cmp r3, #0 8001fde: d127 bne.n 8002030 { // Preenche com zeros à esquerda até atingir a largura desejada while (width > 1 && i < (max_len - 1)) 8001fe0: e00c b.n 8001ffc { str[i++] = '0'; 8001fe2: f9b7 2016 ldrsh.w r2, [r7, #22] 8001fe6: b293 uxth r3, r2 8001fe8: 3301 adds r3, #1 8001fea: b29b uxth r3, r3 8001fec: 82fb strh r3, [r7, #22] 8001fee: 683b ldr r3, [r7, #0] 8001ff0: 4413 add r3, r2 8001ff2: 2230 movs r2, #48 @ 0x30 8001ff4: 701a strb r2, [r3, #0] width--; 8001ff6: 7d7b ldrb r3, [r7, #21] 8001ff8: 3b01 subs r3, #1 8001ffa: 757b strb r3, [r7, #21] while (width > 1 && i < (max_len - 1)) 8001ffc: 7d7b ldrb r3, [r7, #21] 8001ffe: 2b01 cmp r3, #1 8002000: d905 bls.n 800200e 8002002: f9b7 2016 ldrsh.w r2, [r7, #22] 8002006: 7bfb ldrb r3, [r7, #15] 8002008: 3b01 subs r3, #1 800200a: 429a cmp r2, r3 800200c: dbe9 blt.n 8001fe2 } str[i++] = '0'; 800200e: f9b7 2016 ldrsh.w r2, [r7, #22] 8002012: b293 uxth r3, r2 8002014: 3301 adds r3, #1 8002016: b29b uxth r3, r3 8002018: 82fb strh r3, [r7, #22] 800201a: 683b ldr r3, [r7, #0] 800201c: 4413 add r3, r2 800201e: 2230 movs r2, #48 @ 0x30 8002020: 701a strb r2, [r3, #0] str[i] = '\0'; 8002022: f9b7 3016 ldrsh.w r3, [r7, #22] 8002026: 683a ldr r2, [r7, #0] 8002028: 4413 add r3, r2 800202a: 2200 movs r2, #0 800202c: 701a strb r2, [r3, #0] return; 800202e: e08a b.n 8002146 } if (N < 0) 8002030: f9b7 3006 ldrsh.w r3, [r7, #6] 8002034: 2b00 cmp r3, #0 8002036: da2d bge.n 8002094 N = -N; 8002038: 88fb ldrh r3, [r7, #6] 800203a: 425b negs r3, r3 800203c: b29b uxth r3, r3 800203e: 80fb strh r3, [r7, #6] // Extração dos dígitos while (N > 0) 8002040: e028 b.n 8002094 { if (i >= (max_len - 1)) 8002042: f9b7 2016 ldrsh.w r2, [r7, #22] 8002046: 7bfb ldrb r3, [r7, #15] 8002048: 3b01 subs r3, #1 800204a: 429a cmp r2, r3 800204c: da27 bge.n 800209e break; // Proteção de estouro str[i++] = (N % 10) + '0'; 800204e: f9b7 2006 ldrsh.w r2, [r7, #6] 8002052: 4b3f ldr r3, [pc, #252] @ (8002150 ) 8002054: fb83 1302 smull r1, r3, r3, r2 8002058: 1099 asrs r1, r3, #2 800205a: 17d3 asrs r3, r2, #31 800205c: 1ac9 subs r1, r1, r3 800205e: 460b mov r3, r1 8002060: 009b lsls r3, r3, #2 8002062: 440b add r3, r1 8002064: 005b lsls r3, r3, #1 8002066: 1ad3 subs r3, r2, r3 8002068: b21b sxth r3, r3 800206a: b2da uxtb r2, r3 800206c: f9b7 1016 ldrsh.w r1, [r7, #22] 8002070: b28b uxth r3, r1 8002072: 3301 adds r3, #1 8002074: b29b uxth r3, r3 8002076: 82fb strh r3, [r7, #22] 8002078: 683b ldr r3, [r7, #0] 800207a: 440b add r3, r1 800207c: 3230 adds r2, #48 @ 0x30 800207e: b2d2 uxtb r2, r2 8002080: 701a strb r2, [r3, #0] N /= 10; 8002082: f9b7 3006 ldrsh.w r3, [r7, #6] 8002086: 4a32 ldr r2, [pc, #200] @ (8002150 ) 8002088: fb82 1203 smull r1, r2, r2, r3 800208c: 1092 asrs r2, r2, #2 800208e: 17db asrs r3, r3, #31 8002090: 1ad3 subs r3, r2, r3 8002092: 80fb strh r3, [r7, #6] while (N > 0) 8002094: f9b7 3006 ldrsh.w r3, [r7, #6] 8002098: 2b00 cmp r3, #0 800209a: dcd2 bgt.n 8002042 800209c: e000 b.n 80020a0 break; // Proteção de estouro 800209e: bf00 nop } // Adiciona o sinal de menos se necessário if (sign < 0) 80020a0: f9b7 3010 ldrsh.w r3, [r7, #16] 80020a4: 2b00 cmp r3, #0 80020a6: da1a bge.n 80020de { if (i < (max_len - 1)) 80020a8: f9b7 2016 ldrsh.w r2, [r7, #22] 80020ac: 7bfb ldrb r3, [r7, #15] 80020ae: 3b01 subs r3, #1 80020b0: 429a cmp r2, r3 80020b2: da14 bge.n 80020de str[i++] = '-'; 80020b4: f9b7 2016 ldrsh.w r2, [r7, #22] 80020b8: b293 uxth r3, r2 80020ba: 3301 adds r3, #1 80020bc: b29b uxth r3, r3 80020be: 82fb strh r3, [r7, #22] 80020c0: 683b ldr r3, [r7, #0] 80020c2: 4413 add r3, r2 80020c4: 222d movs r2, #45 @ 0x2d 80020c6: 701a strb r2, [r3, #0] } // Preenche com zeros à esquerda (considerando o espaço ocupado pelos dígitos e sinal) while (i < width && i < (max_len - 1)) 80020c8: e009 b.n 80020de { str[i++] = '0'; 80020ca: f9b7 2016 ldrsh.w r2, [r7, #22] 80020ce: b293 uxth r3, r2 80020d0: 3301 adds r3, #1 80020d2: b29b uxth r3, r3 80020d4: 82fb strh r3, [r7, #22] 80020d6: 683b ldr r3, [r7, #0] 80020d8: 4413 add r3, r2 80020da: 2230 movs r2, #48 @ 0x30 80020dc: 701a strb r2, [r3, #0] while (i < width && i < (max_len - 1)) 80020de: f9b7 2016 ldrsh.w r2, [r7, #22] 80020e2: 7d7b ldrb r3, [r7, #21] 80020e4: 429a cmp r2, r3 80020e6: da05 bge.n 80020f4 80020e8: f9b7 2016 ldrsh.w r2, [r7, #22] 80020ec: 7bfb ldrb r3, [r7, #15] 80020ee: 3b01 subs r3, #1 80020f0: 429a cmp r2, r3 80020f2: dbea blt.n 80020ca } str[i] = '\0'; 80020f4: f9b7 3016 ldrsh.w r3, [r7, #22] 80020f8: 683a ldr r2, [r7, #0] 80020fa: 4413 add r3, r2 80020fc: 2200 movs r2, #0 80020fe: 701a strb r2, [r3, #0] // Inverte a string para colocar na ordem correta for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002100: 2300 movs r3, #0 8002102: 753b strb r3, [r7, #20] 8002104: 8afb ldrh r3, [r7, #22] 8002106: b2db uxtb r3, r3 8002108: 3b01 subs r3, #1 800210a: 74fb strb r3, [r7, #19] 800210c: e017 b.n 800213e { uint8_t temp = str[j]; 800210e: 7d3b ldrb r3, [r7, #20] 8002110: 683a ldr r2, [r7, #0] 8002112: 4413 add r3, r2 8002114: 781b ldrb r3, [r3, #0] 8002116: 73bb strb r3, [r7, #14] str[j] = str[k]; 8002118: 7cfb ldrb r3, [r7, #19] 800211a: 683a ldr r2, [r7, #0] 800211c: 441a add r2, r3 800211e: 7d3b ldrb r3, [r7, #20] 8002120: 6839 ldr r1, [r7, #0] 8002122: 440b add r3, r1 8002124: 7812 ldrb r2, [r2, #0] 8002126: 701a strb r2, [r3, #0] str[k] = temp; 8002128: 7cfb ldrb r3, [r7, #19] 800212a: 683a ldr r2, [r7, #0] 800212c: 4413 add r3, r2 800212e: 7bba ldrb r2, [r7, #14] 8002130: 701a strb r2, [r3, #0] for (uint8_t j = 0, k = i - 1; j < k; j++, k--) 8002132: 7d3b ldrb r3, [r7, #20] 8002134: 3301 adds r3, #1 8002136: 753b strb r3, [r7, #20] 8002138: 7cfb ldrb r3, [r7, #19] 800213a: 3b01 subs r3, #1 800213c: 74fb strb r3, [r7, #19] 800213e: 7d3a ldrb r2, [r7, #20] 8002140: 7cfb ldrb r3, [r7, #19] 8002142: 429a cmp r2, r3 8002144: d3e3 bcc.n 800210e } } 8002146: 371c adds r7, #28 8002148: 46bd mov sp, r7 800214a: bc80 pop {r7} 800214c: 4770 bx lr 800214e: bf00 nop 8002150: 66666667 .word 0x66666667 08002154 : /* TIM3 Timer Interrupt */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8002154: b480 push {r7} 8002156: b083 sub sp, #12 8002158: af00 add r7, sp, #0 800215a: 6078 str r0, [r7, #4] if (htim->Instance == TIM3) 800215c: 687b ldr r3, [r7, #4] 800215e: 681b ldr r3, [r3, #0] 8002160: 4a06 ldr r2, [pc, #24] @ (800217c ) 8002162: 4293 cmp r3, r2 8002164: d104 bne.n 8002170 { g_ms_counter++; /* Relógio global do sistema */ 8002166: 4b06 ldr r3, [pc, #24] @ (8002180 ) 8002168: 681b ldr r3, [r3, #0] 800216a: 3301 adds r3, #1 800216c: 4a04 ldr r2, [pc, #16] @ (8002180 ) 800216e: 6013 str r3, [r2, #0] } } 8002170: bf00 nop 8002172: 370c adds r7, #12 8002174: 46bd mov sp, r7 8002176: bc80 pop {r7} 8002178: 4770 bx lr 800217a: bf00 nop 800217c: 40000400 .word 0x40000400 8002180: 20000080 .word 0x20000080 08002184 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002184: b480 push {r7} 8002186: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8002188: b672 cpsid i } 800218a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800218c: bf00 nop 800218e: e7fd b.n 800218c 08002190 : * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { 8002190: b480 push {r7} 8002192: b083 sub sp, #12 8002194: af00 add r7, sp, #0 8002196: 6078 str r0, [r7, #4] return (READ_REG(GPIOx->IDR)); 8002198: 687b ldr r3, [r7, #4] 800219a: 689b ldr r3, [r3, #8] } 800219c: 4618 mov r0, r3 800219e: 370c adds r7, #12 80021a0: 46bd mov sp, r7 80021a2: bc80 pop {r7} 80021a4: 4770 bx lr ... 080021a8 : /** * @brief Initializes the RS-485 driver. * @note This function configures GPIOs for address detection and USART1 for communication. */ void rs485_init(void) { 80021a8: b580 push {r7, lr} 80021aa: af00 add r7, sp, #0 /* Configure GPIOs for address detection */ rs485_configure_gpio_address(); 80021ac: f000 f864 bl 8002278 /* Configure USART1 for RS-485 communication */ rs485_configure_usart1(); 80021b0: f000 f8a8 bl 8002304 /* Get the current device address from GPIOs */ device_address.full_address = rs485_get_address(); 80021b4: f000 f808 bl 80021c8 80021b8: 4603 mov r3, r0 80021ba: 461a mov r2, r3 80021bc: 4b01 ldr r3, [pc, #4] @ (80021c4 ) 80021be: 709a strb r2, [r3, #2] } 80021c0: bf00 nop 80021c2: bd80 pop {r7, pc} 80021c4: 200002c4 .word 0x200002c4 080021c8 : /** * @brief Gets the current device address from GPIOs. * @return The 8-bit device address. */ uint8_t rs485_get_address(void) { 80021c8: b598 push {r3, r4, r7, lr} 80021ca: af00 add r7, sp, #0 return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW))); 80021cc: 480a ldr r0, [pc, #40] @ (80021f8 ) 80021ce: f7ff ffdf bl 8002190 80021d2: 4603 mov r3, r0 80021d4: 0a1b lsrs r3, r3, #8 80021d6: b2db uxtb r3, r3 80021d8: f023 030f bic.w r3, r3, #15 80021dc: b2dc uxtb r4, r3 80021de: 4807 ldr r0, [pc, #28] @ (80021fc ) 80021e0: f7ff ffd6 bl 8002190 80021e4: 4603 mov r3, r0 80021e6: 089b lsrs r3, r3, #2 80021e8: b2db uxtb r3, r3 80021ea: f003 030f and.w r3, r3, #15 80021ee: b2db uxtb r3, r3 80021f0: 4323 orrs r3, r4 80021f2: b2db uxtb r3, r3 } 80021f4: 4618 mov r0, r3 80021f6: bd98 pop {r3, r4, r7, pc} 80021f8: 40010c00 .word 0x40010c00 80021fc: 40010800 .word 0x40010800 08002200 : * @param data Pointer to the data buffer. * @param length Number of bytes to send. * @retval HAL_OK on success, otherwise error code. */ HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length) { 8002200: b580 push {r7, lr} 8002202: b084 sub sp, #16 8002204: af00 add r7, sp, #0 8002206: 6078 str r0, [r7, #4] 8002208: 460b mov r3, r1 800220a: 807b strh r3, [r7, #2] /* Enable transmission mode */ rs485_enable_tx(); 800220c: f000 f81c bl 8002248 /* Send the broadcast address (0x00) first */ uint8_t broadcast_address = 0x00; 8002210: 2300 movs r3, #0 8002212: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY); 8002214: f107 010e add.w r1, r7, #14 8002218: f04f 33ff mov.w r3, #4294967295 800221c: 2201 movs r2, #1 800221e: 4809 ldr r0, [pc, #36] @ (8002244 ) 8002220: f003 f978 bl 8005514 /* Send the data */ HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY); 8002224: 887a ldrh r2, [r7, #2] 8002226: f04f 33ff mov.w r3, #4294967295 800222a: 6879 ldr r1, [r7, #4] 800222c: 4805 ldr r0, [pc, #20] @ (8002244 ) 800222e: f003 f971 bl 8005514 8002232: 4603 mov r3, r0 8002234: 73fb strb r3, [r7, #15] /* Disable transmission mode after sending */ rs485_disable_tx(); 8002236: f000 f813 bl 8002260 return status; 800223a: 7bfb ldrb r3, [r7, #15] } 800223c: 4618 mov r0, r3 800223e: 3710 adds r7, #16 8002240: 46bd mov sp, r7 8002242: bd80 pop {r7, pc} 8002244: 200002c8 .word 0x200002c8 08002248 : /** * @brief Enables transmission mode on RS-485 transceiver. */ void rs485_enable_tx(void) { 8002248: b580 push {r7, lr} 800224a: af00 add r7, sp, #0 /* Set TX EN pin high to enable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET); 800224c: 2201 movs r2, #1 800224e: f44f 5180 mov.w r1, #4096 @ 0x1000 8002252: 4802 ldr r0, [pc, #8] @ (800225c ) 8002254: f000 ffef bl 8003236 } 8002258: bf00 nop 800225a: bd80 pop {r7, pc} 800225c: 40010800 .word 0x40010800 08002260 : /** * @brief Disables transmission mode on RS-485 transceiver. */ void rs485_disable_tx(void) { 8002260: b580 push {r7, lr} 8002262: af00 add r7, sp, #0 /* Set TX EN pin low to disable transmitter */ HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET); 8002264: 2200 movs r2, #0 8002266: f44f 5180 mov.w r1, #4096 @ 0x1000 800226a: 4802 ldr r0, [pc, #8] @ (8002274 ) 800226c: f000 ffe3 bl 8003236 } 8002270: bf00 nop 8002272: bd80 pop {r7, pc} 8002274: 40010800 .word 0x40010800 08002278 : /** * @brief Configures GPIOs for address detection. */ static void rs485_configure_gpio_address(void) { 8002278: b580 push {r7, lr} 800227a: b086 sub sp, #24 800227c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800227e: f107 0308 add.w r3, r7, #8 8002282: 2200 movs r2, #0 8002284: 601a str r2, [r3, #0] 8002286: 605a str r2, [r3, #4] 8002288: 609a str r2, [r3, #8] 800228a: 60da str r2, [r3, #12] /* Enable clock for GPIOA and GPIOB */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800228c: 4b1a ldr r3, [pc, #104] @ (80022f8 ) 800228e: 699b ldr r3, [r3, #24] 8002290: 4a19 ldr r2, [pc, #100] @ (80022f8 ) 8002292: f043 0304 orr.w r3, r3, #4 8002296: 6193 str r3, [r2, #24] 8002298: 4b17 ldr r3, [pc, #92] @ (80022f8 ) 800229a: 699b ldr r3, [r3, #24] 800229c: f003 0304 and.w r3, r3, #4 80022a0: 607b str r3, [r7, #4] 80022a2: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 80022a4: 4b14 ldr r3, [pc, #80] @ (80022f8 ) 80022a6: 699b ldr r3, [r3, #24] 80022a8: 4a13 ldr r2, [pc, #76] @ (80022f8 ) 80022aa: f043 0308 orr.w r3, r3, #8 80022ae: 6193 str r3, [r2, #24] 80022b0: 4b11 ldr r3, [pc, #68] @ (80022f8 ) 80022b2: 699b ldr r3, [r3, #24] 80022b4: f003 0308 and.w r3, r3, #8 80022b8: 603b str r3, [r7, #0] 80022ba: 683b ldr r3, [r7, #0] /* Configure PA2-PA5 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 80022bc: 233c movs r3, #60 @ 0x3c 80022be: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80022c0: 2300 movs r3, #0 80022c2: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80022c4: 2301 movs r3, #1 80022c6: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80022c8: f107 0308 add.w r3, r7, #8 80022cc: 4619 mov r1, r3 80022ce: 480b ldr r0, [pc, #44] @ (80022fc ) 80022d0: f000 fe16 bl 8002f00 /* Configure PB12-PB15 as input with pull-up */ GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 80022d4: f44f 4370 mov.w r3, #61440 @ 0xf000 80022d8: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80022da: 2300 movs r3, #0 80022dc: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_PULLUP; 80022de: 2301 movs r3, #1 80022e0: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80022e2: f107 0308 add.w r3, r7, #8 80022e6: 4619 mov r1, r3 80022e8: 4805 ldr r0, [pc, #20] @ (8002300 ) 80022ea: f000 fe09 bl 8002f00 } 80022ee: bf00 nop 80022f0: 3718 adds r7, #24 80022f2: 46bd mov sp, r7 80022f4: bd80 pop {r7, pc} 80022f6: bf00 nop 80022f8: 40021000 .word 0x40021000 80022fc: 40010800 .word 0x40010800 8002300: 40010c00 .word 0x40010c00 08002304 : /** * @brief Configures USART1 for RS-485 communication. */ static void rs485_configure_usart1(void) { 8002304: b580 push {r7, lr} 8002306: b082 sub sp, #8 8002308: af00 add r7, sp, #0 /* Enable clock for USART1 */ __HAL_RCC_USART1_CLK_ENABLE(); 800230a: 4b18 ldr r3, [pc, #96] @ (800236c ) 800230c: 699b ldr r3, [r3, #24] 800230e: 4a17 ldr r2, [pc, #92] @ (800236c ) 8002310: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002314: 6193 str r3, [r2, #24] 8002316: 4b15 ldr r3, [pc, #84] @ (800236c ) 8002318: 699b ldr r3, [r3, #24] 800231a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800231e: 607b str r3, [r7, #4] 8002320: 687b ldr r3, [r7, #4] huart1.Instance = USART1; 8002322: 4b13 ldr r3, [pc, #76] @ (8002370 ) 8002324: 4a13 ldr r2, [pc, #76] @ (8002374 ) 8002326: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; /*!< Default baud rate for RS-485 */ 8002328: 4b11 ldr r3, [pc, #68] @ (8002370 ) 800232a: f44f 5216 mov.w r2, #9600 @ 0x2580 800232e: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002330: 4b0f ldr r3, [pc, #60] @ (8002370 ) 8002332: 2200 movs r2, #0 8002334: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002336: 4b0e ldr r3, [pc, #56] @ (8002370 ) 8002338: 2200 movs r2, #0 800233a: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800233c: 4b0c ldr r3, [pc, #48] @ (8002370 ) 800233e: 2200 movs r2, #0 8002340: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002342: 4b0b ldr r3, [pc, #44] @ (8002370 ) 8002344: 220c movs r2, #12 8002346: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */ 8002348: 4b09 ldr r3, [pc, #36] @ (8002370 ) 800234a: 2200 movs r2, #0 800234c: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800234e: 4b08 ldr r3, [pc, #32] @ (8002370 ) 8002350: 2200 movs r2, #0 8002352: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002354: 4806 ldr r0, [pc, #24] @ (8002370 ) 8002356: f003 f88d bl 8005474 800235a: 4603 mov r3, r0 800235c: 2b00 cmp r3, #0 800235e: d001 beq.n 8002364 { /* Initialization Error */ while(1); 8002360: bf00 nop 8002362: e7fd b.n 8002360 } } 8002364: bf00 nop 8002366: 3708 adds r7, #8 8002368: 46bd mov sp, r7 800236a: bd80 pop {r7, pc} 800236c: 40021000 .word 0x40021000 8002370: 200002c8 .word 0x200002c8 8002374: 40013800 .word 0x40013800 08002378 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002378: b480 push {r7} 800237a: b085 sub sp, #20 800237c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800237e: 4b15 ldr r3, [pc, #84] @ (80023d4 ) 8002380: 699b ldr r3, [r3, #24] 8002382: 4a14 ldr r2, [pc, #80] @ (80023d4 ) 8002384: f043 0301 orr.w r3, r3, #1 8002388: 6193 str r3, [r2, #24] 800238a: 4b12 ldr r3, [pc, #72] @ (80023d4 ) 800238c: 699b ldr r3, [r3, #24] 800238e: f003 0301 and.w r3, r3, #1 8002392: 60bb str r3, [r7, #8] 8002394: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8002396: 4b0f ldr r3, [pc, #60] @ (80023d4 ) 8002398: 69db ldr r3, [r3, #28] 800239a: 4a0e ldr r2, [pc, #56] @ (80023d4 ) 800239c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80023a0: 61d3 str r3, [r2, #28] 80023a2: 4b0c ldr r3, [pc, #48] @ (80023d4 ) 80023a4: 69db ldr r3, [r3, #28] 80023a6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80023aa: 607b str r3, [r7, #4] 80023ac: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80023ae: 4b0a ldr r3, [pc, #40] @ (80023d8 ) 80023b0: 685b ldr r3, [r3, #4] 80023b2: 60fb str r3, [r7, #12] 80023b4: 68fb ldr r3, [r7, #12] 80023b6: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 80023ba: 60fb str r3, [r7, #12] 80023bc: 68fb ldr r3, [r7, #12] 80023be: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80023c2: 60fb str r3, [r7, #12] 80023c4: 4a04 ldr r2, [pc, #16] @ (80023d8 ) 80023c6: 68fb ldr r3, [r7, #12] 80023c8: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80023ca: bf00 nop 80023cc: 3714 adds r7, #20 80023ce: 46bd mov sp, r7 80023d0: bc80 pop {r7} 80023d2: 4770 bx lr 80023d4: 40021000 .word 0x40021000 80023d8: 40010000 .word 0x40010000 080023dc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80023dc: b480 push {r7} 80023de: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80023e0: bf00 nop 80023e2: e7fd b.n 80023e0 080023e4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80023e4: b480 push {r7} 80023e6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80023e8: bf00 nop 80023ea: e7fd b.n 80023e8 080023ec : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80023ec: b480 push {r7} 80023ee: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80023f0: bf00 nop 80023f2: e7fd b.n 80023f0 080023f4 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80023f4: b480 push {r7} 80023f6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80023f8: bf00 nop 80023fa: e7fd b.n 80023f8 080023fc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80023fc: b480 push {r7} 80023fe: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002400: bf00 nop 8002402: e7fd b.n 8002400 08002404 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002404: b480 push {r7} 8002406: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002408: bf00 nop 800240a: 46bd mov sp, r7 800240c: bc80 pop {r7} 800240e: 4770 bx lr 08002410 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002410: b480 push {r7} 8002412: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002414: bf00 nop 8002416: 46bd mov sp, r7 8002418: bc80 pop {r7} 800241a: 4770 bx lr 0800241c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800241c: b480 push {r7} 800241e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002420: bf00 nop 8002422: 46bd mov sp, r7 8002424: bc80 pop {r7} 8002426: 4770 bx lr 08002428 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002428: b580 push {r7, lr} 800242a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800242c: f000 f97a bl 8002724 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002430: bf00 nop 8002432: bd80 pop {r7, pc} 08002434 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8002434: b580 push {r7, lr} 8002436: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8002438: 4802 ldr r0, [pc, #8] @ (8002444 ) 800243a: f002 fccb bl 8004dd4 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800243e: bf00 nop 8002440: bd80 pop {r7, pc} 8002442: bf00 nop 8002444: 20000310 .word 0x20000310 08002448 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8002448: b580 push {r7, lr} 800244a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800244c: 4802 ldr r0, [pc, #8] @ (8002458 ) 800244e: f003 f8ed bl 800562c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8002452: bf00 nop 8002454: bd80 pop {r7, pc} 8002456: bf00 nop 8002458: 20000358 .word 0x20000358 0800245c : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800245c: b480 push {r7} 800245e: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002460: bf00 nop 8002462: 46bd mov sp, r7 8002464: bc80 pop {r7} 8002466: 4770 bx lr 08002468 : TIM_HandleTypeDef htim3; /* TIM3 init function */ void MX_TIM3_Init(void) { 8002468: b580 push {r7, lr} 800246a: b086 sub sp, #24 800246c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800246e: f107 0308 add.w r3, r7, #8 8002472: 2200 movs r2, #0 8002474: 601a str r2, [r3, #0] 8002476: 605a str r2, [r3, #4] 8002478: 609a str r2, [r3, #8] 800247a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800247c: 463b mov r3, r7 800247e: 2200 movs r2, #0 8002480: 601a str r2, [r3, #0] 8002482: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8002484: 4b1d ldr r3, [pc, #116] @ (80024fc ) 8002486: 4a1e ldr r2, [pc, #120] @ (8002500 ) 8002488: 601a str r2, [r3, #0] htim3.Init.Prescaler = 2; 800248a: 4b1c ldr r3, [pc, #112] @ (80024fc ) 800248c: 2202 movs r2, #2 800248e: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8002490: 4b1a ldr r3, [pc, #104] @ (80024fc ) 8002492: 2200 movs r2, #0 8002494: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8002496: 4b19 ldr r3, [pc, #100] @ (80024fc ) 8002498: f240 32e7 movw r2, #999 @ 0x3e7 800249c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800249e: 4b17 ldr r3, [pc, #92] @ (80024fc ) 80024a0: 2200 movs r2, #0 80024a2: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80024a4: 4b15 ldr r3, [pc, #84] @ (80024fc ) 80024a6: 2280 movs r2, #128 @ 0x80 80024a8: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 80024aa: 4814 ldr r0, [pc, #80] @ (80024fc ) 80024ac: f002 fbf0 bl 8004c90 80024b0: 4603 mov r3, r0 80024b2: 2b00 cmp r3, #0 80024b4: d001 beq.n 80024ba { Error_Handler(); 80024b6: f7ff fe65 bl 8002184 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80024ba: f44f 5380 mov.w r3, #4096 @ 0x1000 80024be: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 80024c0: f107 0308 add.w r3, r7, #8 80024c4: 4619 mov r1, r3 80024c6: 480d ldr r0, [pc, #52] @ (80024fc ) 80024c8: f002 fd74 bl 8004fb4 80024cc: 4603 mov r3, r0 80024ce: 2b00 cmp r3, #0 80024d0: d001 beq.n 80024d6 { Error_Handler(); 80024d2: f7ff fe57 bl 8002184 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80024d6: 2300 movs r3, #0 80024d8: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80024da: 2300 movs r3, #0 80024dc: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80024de: 463b mov r3, r7 80024e0: 4619 mov r1, r3 80024e2: 4806 ldr r0, [pc, #24] @ (80024fc ) 80024e4: f002 ff56 bl 8005394 80024e8: 4603 mov r3, r0 80024ea: 2b00 cmp r3, #0 80024ec: d001 beq.n 80024f2 { Error_Handler(); 80024ee: f7ff fe49 bl 8002184 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80024f2: bf00 nop 80024f4: 3718 adds r7, #24 80024f6: 46bd mov sp, r7 80024f8: bd80 pop {r7, pc} 80024fa: bf00 nop 80024fc: 20000310 .word 0x20000310 8002500: 40000400 .word 0x40000400 08002504 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8002504: b580 push {r7, lr} 8002506: b084 sub sp, #16 8002508: af00 add r7, sp, #0 800250a: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800250c: 687b ldr r3, [r7, #4] 800250e: 681b ldr r3, [r3, #0] 8002510: 4a0d ldr r2, [pc, #52] @ (8002548 ) 8002512: 4293 cmp r3, r2 8002514: d113 bne.n 800253e { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8002516: 4b0d ldr r3, [pc, #52] @ (800254c ) 8002518: 69db ldr r3, [r3, #28] 800251a: 4a0c ldr r2, [pc, #48] @ (800254c ) 800251c: f043 0302 orr.w r3, r3, #2 8002520: 61d3 str r3, [r2, #28] 8002522: 4b0a ldr r3, [pc, #40] @ (800254c ) 8002524: 69db ldr r3, [r3, #28] 8002526: f003 0302 and.w r3, r3, #2 800252a: 60fb str r3, [r7, #12] 800252c: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800252e: 2200 movs r2, #0 8002530: 2100 movs r1, #0 8002532: 201d movs r0, #29 8002534: f000 fbfb bl 8002d2e HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002538: 201d movs r0, #29 800253a: f000 fc14 bl 8002d66 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800253e: bf00 nop 8002540: 3710 adds r7, #16 8002542: 46bd mov sp, r7 8002544: bd80 pop {r7, pc} 8002546: bf00 nop 8002548: 40000400 .word 0x40000400 800254c: 40021000 .word 0x40021000 08002550 : UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { 8002550: b580 push {r7, lr} 8002552: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8002554: 4b11 ldr r3, [pc, #68] @ (800259c ) 8002556: 4a12 ldr r2, [pc, #72] @ (80025a0 ) 8002558: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800255a: 4b10 ldr r3, [pc, #64] @ (800259c ) 800255c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8002560: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8002562: 4b0e ldr r3, [pc, #56] @ (800259c ) 8002564: 2200 movs r2, #0 8002566: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8002568: 4b0c ldr r3, [pc, #48] @ (800259c ) 800256a: 2200 movs r2, #0 800256c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800256e: 4b0b ldr r3, [pc, #44] @ (800259c ) 8002570: 2200 movs r2, #0 8002572: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8002574: 4b09 ldr r3, [pc, #36] @ (800259c ) 8002576: 220c movs r2, #12 8002578: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800257a: 4b08 ldr r3, [pc, #32] @ (800259c ) 800257c: 2200 movs r2, #0 800257e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8002580: 4b06 ldr r3, [pc, #24] @ (800259c ) 8002582: 2200 movs r2, #0 8002584: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8002586: 4805 ldr r0, [pc, #20] @ (800259c ) 8002588: f002 ff74 bl 8005474 800258c: 4603 mov r3, r0 800258e: 2b00 cmp r3, #0 8002590: d001 beq.n 8002596 { Error_Handler(); 8002592: f7ff fdf7 bl 8002184 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8002596: bf00 nop 8002598: bd80 pop {r7, pc} 800259a: bf00 nop 800259c: 20000358 .word 0x20000358 80025a0: 40013800 .word 0x40013800 080025a4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80025a4: b580 push {r7, lr} 80025a6: b088 sub sp, #32 80025a8: af00 add r7, sp, #0 80025aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80025ac: f107 0310 add.w r3, r7, #16 80025b0: 2200 movs r2, #0 80025b2: 601a str r2, [r3, #0] 80025b4: 605a str r2, [r3, #4] 80025b6: 609a str r2, [r3, #8] 80025b8: 60da str r2, [r3, #12] if(uartHandle->Instance==USART1) 80025ba: 687b ldr r3, [r7, #4] 80025bc: 681b ldr r3, [r3, #0] 80025be: 4a20 ldr r2, [pc, #128] @ (8002640 ) 80025c0: 4293 cmp r3, r2 80025c2: d139 bne.n 8002638 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80025c4: 4b1f ldr r3, [pc, #124] @ (8002644 ) 80025c6: 699b ldr r3, [r3, #24] 80025c8: 4a1e ldr r2, [pc, #120] @ (8002644 ) 80025ca: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80025ce: 6193 str r3, [r2, #24] 80025d0: 4b1c ldr r3, [pc, #112] @ (8002644 ) 80025d2: 699b ldr r3, [r3, #24] 80025d4: f403 4380 and.w r3, r3, #16384 @ 0x4000 80025d8: 60fb str r3, [r7, #12] 80025da: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80025dc: 4b19 ldr r3, [pc, #100] @ (8002644 ) 80025de: 699b ldr r3, [r3, #24] 80025e0: 4a18 ldr r2, [pc, #96] @ (8002644 ) 80025e2: f043 0304 orr.w r3, r3, #4 80025e6: 6193 str r3, [r2, #24] 80025e8: 4b16 ldr r3, [pc, #88] @ (8002644 ) 80025ea: 699b ldr r3, [r3, #24] 80025ec: f003 0304 and.w r3, r3, #4 80025f0: 60bb str r3, [r7, #8] 80025f2: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = TX_RS485_Pin; 80025f4: f44f 7300 mov.w r3, #512 @ 0x200 80025f8: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80025fa: 2302 movs r3, #2 80025fc: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 80025fe: 2301 movs r3, #1 8002600: 61fb str r3, [r7, #28] HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct); 8002602: f107 0310 add.w r3, r7, #16 8002606: 4619 mov r1, r3 8002608: 480f ldr r0, [pc, #60] @ (8002648 ) 800260a: f000 fc79 bl 8002f00 GPIO_InitStruct.Pin = RX_RS485_Pin; 800260e: f44f 6380 mov.w r3, #1024 @ 0x400 8002612: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002614: 2300 movs r3, #0 8002616: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002618: 2300 movs r3, #0 800261a: 61bb str r3, [r7, #24] HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct); 800261c: f107 0310 add.w r3, r7, #16 8002620: 4619 mov r1, r3 8002622: 4809 ldr r0, [pc, #36] @ (8002648 ) 8002624: f000 fc6c bl 8002f00 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8002628: 2200 movs r2, #0 800262a: 2100 movs r1, #0 800262c: 2025 movs r0, #37 @ 0x25 800262e: f000 fb7e bl 8002d2e HAL_NVIC_EnableIRQ(USART1_IRQn); 8002632: 2025 movs r0, #37 @ 0x25 8002634: f000 fb97 bl 8002d66 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002638: bf00 nop 800263a: 3720 adds r7, #32 800263c: 46bd mov sp, r7 800263e: bd80 pop {r7, pc} 8002640: 40013800 .word 0x40013800 8002644: 40021000 .word 0x40021000 8002648: 40010800 .word 0x40010800 0800264c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800264c: f7ff ff06 bl 800245c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002650: 480b ldr r0, [pc, #44] @ (8002680 ) ldr r1, =_edata 8002652: 490c ldr r1, [pc, #48] @ (8002684 ) ldr r2, =_sidata 8002654: 4a0c ldr r2, [pc, #48] @ (8002688 ) movs r3, #0 8002656: 2300 movs r3, #0 b LoopCopyDataInit 8002658: e002 b.n 8002660 0800265a : CopyDataInit: ldr r4, [r2, r3] 800265a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800265c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800265e: 3304 adds r3, #4 08002660 : LoopCopyDataInit: adds r4, r0, r3 8002660: 18c4 adds r4, r0, r3 cmp r4, r1 8002662: 428c cmp r4, r1 bcc CopyDataInit 8002664: d3f9 bcc.n 800265a /* Zero fill the bss segment. */ ldr r2, =_sbss 8002666: 4a09 ldr r2, [pc, #36] @ (800268c ) ldr r4, =_ebss 8002668: 4c09 ldr r4, [pc, #36] @ (8002690 ) movs r3, #0 800266a: 2300 movs r3, #0 b LoopFillZerobss 800266c: e001 b.n 8002672 0800266e : FillZerobss: str r3, [r2] 800266e: 6013 str r3, [r2, #0] adds r2, r2, #4 8002670: 3204 adds r2, #4 08002672 : LoopFillZerobss: cmp r2, r4 8002672: 42a2 cmp r2, r4 bcc FillZerobss 8002674: d3fb bcc.n 800266e /* Call static constructors */ bl __libc_init_array 8002676: f003 fd21 bl 80060bc <__libc_init_array> /* Call the application's entry point.*/ bl main 800267a: f7ff faf3 bl 8001c64

bx lr 800267e: 4770 bx lr ldr r0, =_sdata 8002680: 20000000 .word 0x20000000 ldr r1, =_edata 8002684: 20000060 .word 0x20000060 ldr r2, =_sidata 8002688: 08006388 .word 0x08006388 ldr r2, =_sbss 800268c: 20000060 .word 0x20000060 ldr r4, =_ebss 8002690: 200004dc .word 0x200004dc 08002694 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002694: e7fe b.n 8002694 ... 08002698 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002698: b580 push {r7, lr} 800269a: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800269c: 4b08 ldr r3, [pc, #32] @ (80026c0 ) 800269e: 681b ldr r3, [r3, #0] 80026a0: 4a07 ldr r2, [pc, #28] @ (80026c0 ) 80026a2: f043 0310 orr.w r3, r3, #16 80026a6: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80026a8: 2003 movs r0, #3 80026aa: f000 fb35 bl 8002d18 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80026ae: 200f movs r0, #15 80026b0: f000 f808 bl 80026c4 /* Init the low level hardware */ HAL_MspInit(); 80026b4: f7ff fe60 bl 8002378 /* Return function status */ return HAL_OK; 80026b8: 2300 movs r3, #0 } 80026ba: 4618 mov r0, r3 80026bc: bd80 pop {r7, pc} 80026be: bf00 nop 80026c0: 40022000 .word 0x40022000 080026c4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80026c4: b580 push {r7, lr} 80026c6: b082 sub sp, #8 80026c8: af00 add r7, sp, #0 80026ca: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80026cc: 4b12 ldr r3, [pc, #72] @ (8002718 ) 80026ce: 681a ldr r2, [r3, #0] 80026d0: 4b12 ldr r3, [pc, #72] @ (800271c ) 80026d2: 781b ldrb r3, [r3, #0] 80026d4: 4619 mov r1, r3 80026d6: f44f 737a mov.w r3, #1000 @ 0x3e8 80026da: fbb3 f3f1 udiv r3, r3, r1 80026de: fbb2 f3f3 udiv r3, r2, r3 80026e2: 4618 mov r0, r3 80026e4: f000 fb4d bl 8002d82 80026e8: 4603 mov r3, r0 80026ea: 2b00 cmp r3, #0 80026ec: d001 beq.n 80026f2 { return HAL_ERROR; 80026ee: 2301 movs r3, #1 80026f0: e00e b.n 8002710 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80026f2: 687b ldr r3, [r7, #4] 80026f4: 2b0f cmp r3, #15 80026f6: d80a bhi.n 800270e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80026f8: 2200 movs r2, #0 80026fa: 6879 ldr r1, [r7, #4] 80026fc: f04f 30ff mov.w r0, #4294967295 8002700: f000 fb15 bl 8002d2e uwTickPrio = TickPriority; 8002704: 4a06 ldr r2, [pc, #24] @ (8002720 ) 8002706: 687b ldr r3, [r7, #4] 8002708: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800270a: 2300 movs r3, #0 800270c: e000 b.n 8002710 return HAL_ERROR; 800270e: 2301 movs r3, #1 } 8002710: 4618 mov r0, r3 8002712: 3708 adds r7, #8 8002714: 46bd mov sp, r7 8002716: bd80 pop {r7, pc} 8002718: 20000004 .word 0x20000004 800271c: 2000000c .word 0x2000000c 8002720: 20000008 .word 0x20000008 08002724 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8002724: b480 push {r7} 8002726: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002728: 4b05 ldr r3, [pc, #20] @ (8002740 ) 800272a: 781b ldrb r3, [r3, #0] 800272c: 461a mov r2, r3 800272e: 4b05 ldr r3, [pc, #20] @ (8002744 ) 8002730: 681b ldr r3, [r3, #0] 8002732: 4413 add r3, r2 8002734: 4a03 ldr r2, [pc, #12] @ (8002744 ) 8002736: 6013 str r3, [r2, #0] } 8002738: bf00 nop 800273a: 46bd mov sp, r7 800273c: bc80 pop {r7} 800273e: 4770 bx lr 8002740: 2000000c .word 0x2000000c 8002744: 200003a0 .word 0x200003a0 08002748 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002748: b480 push {r7} 800274a: af00 add r7, sp, #0 return uwTick; 800274c: 4b02 ldr r3, [pc, #8] @ (8002758 ) 800274e: 681b ldr r3, [r3, #0] } 8002750: 4618 mov r0, r3 8002752: 46bd mov sp, r7 8002754: bc80 pop {r7} 8002756: 4770 bx lr 8002758: 200003a0 .word 0x200003a0 0800275c : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800275c: b580 push {r7, lr} 800275e: b086 sub sp, #24 8002760: af00 add r7, sp, #0 8002762: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002764: 2300 movs r3, #0 8002766: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8002768: 2300 movs r3, #0 800276a: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800276c: 2300 movs r3, #0 800276e: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8002770: 2300 movs r3, #0 8002772: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8002774: 687b ldr r3, [r7, #4] 8002776: 2b00 cmp r3, #0 8002778: d101 bne.n 800277e { return HAL_ERROR; 800277a: 2301 movs r3, #1 800277c: e0be b.n 80028fc assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800277e: 687b ldr r3, [r7, #4] 8002780: 689b ldr r3, [r3, #8] 8002782: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8002784: 687b ldr r3, [r7, #4] 8002786: 6a9b ldr r3, [r3, #40] @ 0x28 8002788: 2b00 cmp r3, #0 800278a: d109 bne.n 80027a0 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800278c: 687b ldr r3, [r7, #4] 800278e: 2200 movs r2, #0 8002790: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8002792: 687b ldr r3, [r7, #4] 8002794: 2200 movs r2, #0 8002796: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800279a: 6878 ldr r0, [r7, #4] 800279c: f7fe fd60 bl 8001260 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80027a0: 6878 ldr r0, [r7, #4] 80027a2: f000 f9ab bl 8002afc 80027a6: 4603 mov r3, r0 80027a8: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80027aa: 687b ldr r3, [r7, #4] 80027ac: 6a9b ldr r3, [r3, #40] @ 0x28 80027ae: f003 0310 and.w r3, r3, #16 80027b2: 2b00 cmp r3, #0 80027b4: f040 8099 bne.w 80028ea 80027b8: 7dfb ldrb r3, [r7, #23] 80027ba: 2b00 cmp r3, #0 80027bc: f040 8095 bne.w 80028ea (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80027c0: 687b ldr r3, [r7, #4] 80027c2: 6a9b ldr r3, [r3, #40] @ 0x28 80027c4: f423 5388 bic.w r3, r3, #4352 @ 0x1100 80027c8: f023 0302 bic.w r3, r3, #2 80027cc: f043 0202 orr.w r2, r3, #2 80027d0: 687b ldr r3, [r7, #4] 80027d2: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 80027d4: 687b ldr r3, [r7, #4] 80027d6: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80027d8: 687b ldr r3, [r7, #4] 80027da: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 80027dc: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 80027de: 687b ldr r3, [r7, #4] 80027e0: 7b1b ldrb r3, [r3, #12] 80027e2: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80027e4: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 80027e6: 68ba ldr r2, [r7, #8] 80027e8: 4313 orrs r3, r2 80027ea: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80027ec: 687b ldr r3, [r7, #4] 80027ee: 689b ldr r3, [r3, #8] 80027f0: f5b3 7f80 cmp.w r3, #256 @ 0x100 80027f4: d003 beq.n 80027fe 80027f6: 687b ldr r3, [r7, #4] 80027f8: 689b ldr r3, [r3, #8] 80027fa: 2b01 cmp r3, #1 80027fc: d102 bne.n 8002804 80027fe: f44f 7380 mov.w r3, #256 @ 0x100 8002802: e000 b.n 8002806 8002804: 2300 movs r3, #0 8002806: 693a ldr r2, [r7, #16] 8002808: 4313 orrs r3, r2 800280a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800280c: 687b ldr r3, [r7, #4] 800280e: 7d1b ldrb r3, [r3, #20] 8002810: 2b01 cmp r3, #1 8002812: d119 bne.n 8002848 { if (hadc->Init.ContinuousConvMode == DISABLE) 8002814: 687b ldr r3, [r7, #4] 8002816: 7b1b ldrb r3, [r3, #12] 8002818: 2b00 cmp r3, #0 800281a: d109 bne.n 8002830 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800281c: 687b ldr r3, [r7, #4] 800281e: 699b ldr r3, [r3, #24] 8002820: 3b01 subs r3, #1 8002822: 035a lsls r2, r3, #13 8002824: 693b ldr r3, [r7, #16] 8002826: 4313 orrs r3, r2 8002828: f443 6300 orr.w r3, r3, #2048 @ 0x800 800282c: 613b str r3, [r7, #16] 800282e: e00b b.n 8002848 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002830: 687b ldr r3, [r7, #4] 8002832: 6a9b ldr r3, [r3, #40] @ 0x28 8002834: f043 0220 orr.w r2, r3, #32 8002838: 687b ldr r3, [r7, #4] 800283a: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800283c: 687b ldr r3, [r7, #4] 800283e: 6adb ldr r3, [r3, #44] @ 0x2c 8002840: f043 0201 orr.w r2, r3, #1 8002844: 687b ldr r3, [r7, #4] 8002846: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8002848: 687b ldr r3, [r7, #4] 800284a: 681b ldr r3, [r3, #0] 800284c: 685b ldr r3, [r3, #4] 800284e: f423 4169 bic.w r1, r3, #59648 @ 0xe900 8002852: 687b ldr r3, [r7, #4] 8002854: 681b ldr r3, [r3, #0] 8002856: 693a ldr r2, [r7, #16] 8002858: 430a orrs r2, r1 800285a: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800285c: 687b ldr r3, [r7, #4] 800285e: 681b ldr r3, [r3, #0] 8002860: 689a ldr r2, [r3, #8] 8002862: 4b28 ldr r3, [pc, #160] @ (8002904 ) 8002864: 4013 ands r3, r2 8002866: 687a ldr r2, [r7, #4] 8002868: 6812 ldr r2, [r2, #0] 800286a: 68b9 ldr r1, [r7, #8] 800286c: 430b orrs r3, r1 800286e: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8002870: 687b ldr r3, [r7, #4] 8002872: 689b ldr r3, [r3, #8] 8002874: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002878: d003 beq.n 8002882 800287a: 687b ldr r3, [r7, #4] 800287c: 689b ldr r3, [r3, #8] 800287e: 2b01 cmp r3, #1 8002880: d104 bne.n 800288c { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8002882: 687b ldr r3, [r7, #4] 8002884: 691b ldr r3, [r3, #16] 8002886: 3b01 subs r3, #1 8002888: 051b lsls r3, r3, #20 800288a: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800288c: 687b ldr r3, [r7, #4] 800288e: 681b ldr r3, [r3, #0] 8002890: 6adb ldr r3, [r3, #44] @ 0x2c 8002892: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 8002896: 687b ldr r3, [r7, #4] 8002898: 681b ldr r3, [r3, #0] 800289a: 68fa ldr r2, [r7, #12] 800289c: 430a orrs r2, r1 800289e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80028a0: 687b ldr r3, [r7, #4] 80028a2: 681b ldr r3, [r3, #0] 80028a4: 689a ldr r2, [r3, #8] 80028a6: 4b18 ldr r3, [pc, #96] @ (8002908 ) 80028a8: 4013 ands r3, r2 80028aa: 68ba ldr r2, [r7, #8] 80028ac: 429a cmp r2, r3 80028ae: d10b bne.n 80028c8 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 80028b0: 687b ldr r3, [r7, #4] 80028b2: 2200 movs r2, #0 80028b4: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 80028b6: 687b ldr r3, [r7, #4] 80028b8: 6a9b ldr r3, [r3, #40] @ 0x28 80028ba: f023 0303 bic.w r3, r3, #3 80028be: f043 0201 orr.w r2, r3, #1 80028c2: 687b ldr r3, [r7, #4] 80028c4: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80028c6: e018 b.n 80028fa HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80028c8: 687b ldr r3, [r7, #4] 80028ca: 6a9b ldr r3, [r3, #40] @ 0x28 80028cc: f023 0312 bic.w r3, r3, #18 80028d0: f043 0210 orr.w r2, r3, #16 80028d4: 687b ldr r3, [r7, #4] 80028d6: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80028d8: 687b ldr r3, [r7, #4] 80028da: 6adb ldr r3, [r3, #44] @ 0x2c 80028dc: f043 0201 orr.w r2, r3, #1 80028e0: 687b ldr r3, [r7, #4] 80028e2: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 80028e4: 2301 movs r3, #1 80028e6: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80028e8: e007 b.n 80028fa } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80028ea: 687b ldr r3, [r7, #4] 80028ec: 6a9b ldr r3, [r3, #40] @ 0x28 80028ee: f043 0210 orr.w r2, r3, #16 80028f2: 687b ldr r3, [r7, #4] 80028f4: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 80028f6: 2301 movs r3, #1 80028f8: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80028fa: 7dfb ldrb r3, [r7, #23] } 80028fc: 4618 mov r0, r3 80028fe: 3718 adds r7, #24 8002900: 46bd mov sp, r7 8002902: bd80 pop {r7, pc} 8002904: ffe1f7fd .word 0xffe1f7fd 8002908: ff1f0efe .word 0xff1f0efe 0800290c : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800290c: b480 push {r7} 800290e: b085 sub sp, #20 8002910: af00 add r7, sp, #0 8002912: 6078 str r0, [r7, #4] 8002914: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002916: 2300 movs r3, #0 8002918: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800291a: 2300 movs r3, #0 800291c: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800291e: 687b ldr r3, [r7, #4] 8002920: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8002924: 2b01 cmp r3, #1 8002926: d101 bne.n 800292c 8002928: 2302 movs r3, #2 800292a: e0dc b.n 8002ae6 800292c: 687b ldr r3, [r7, #4] 800292e: 2201 movs r2, #1 8002930: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8002934: 683b ldr r3, [r7, #0] 8002936: 685b ldr r3, [r3, #4] 8002938: 2b06 cmp r3, #6 800293a: d81c bhi.n 8002976 { MODIFY_REG(hadc->Instance->SQR3 , 800293c: 687b ldr r3, [r7, #4] 800293e: 681b ldr r3, [r3, #0] 8002940: 6b59 ldr r1, [r3, #52] @ 0x34 8002942: 683b ldr r3, [r7, #0] 8002944: 685a ldr r2, [r3, #4] 8002946: 4613 mov r3, r2 8002948: 009b lsls r3, r3, #2 800294a: 4413 add r3, r2 800294c: 3b05 subs r3, #5 800294e: 221f movs r2, #31 8002950: fa02 f303 lsl.w r3, r2, r3 8002954: 43db mvns r3, r3 8002956: 4019 ands r1, r3 8002958: 683b ldr r3, [r7, #0] 800295a: 6818 ldr r0, [r3, #0] 800295c: 683b ldr r3, [r7, #0] 800295e: 685a ldr r2, [r3, #4] 8002960: 4613 mov r3, r2 8002962: 009b lsls r3, r3, #2 8002964: 4413 add r3, r2 8002966: 3b05 subs r3, #5 8002968: fa00 f203 lsl.w r2, r0, r3 800296c: 687b ldr r3, [r7, #4] 800296e: 681b ldr r3, [r3, #0] 8002970: 430a orrs r2, r1 8002972: 635a str r2, [r3, #52] @ 0x34 8002974: e03c b.n 80029f0 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8002976: 683b ldr r3, [r7, #0] 8002978: 685b ldr r3, [r3, #4] 800297a: 2b0c cmp r3, #12 800297c: d81c bhi.n 80029b8 { MODIFY_REG(hadc->Instance->SQR2 , 800297e: 687b ldr r3, [r7, #4] 8002980: 681b ldr r3, [r3, #0] 8002982: 6b19 ldr r1, [r3, #48] @ 0x30 8002984: 683b ldr r3, [r7, #0] 8002986: 685a ldr r2, [r3, #4] 8002988: 4613 mov r3, r2 800298a: 009b lsls r3, r3, #2 800298c: 4413 add r3, r2 800298e: 3b23 subs r3, #35 @ 0x23 8002990: 221f movs r2, #31 8002992: fa02 f303 lsl.w r3, r2, r3 8002996: 43db mvns r3, r3 8002998: 4019 ands r1, r3 800299a: 683b ldr r3, [r7, #0] 800299c: 6818 ldr r0, [r3, #0] 800299e: 683b ldr r3, [r7, #0] 80029a0: 685a ldr r2, [r3, #4] 80029a2: 4613 mov r3, r2 80029a4: 009b lsls r3, r3, #2 80029a6: 4413 add r3, r2 80029a8: 3b23 subs r3, #35 @ 0x23 80029aa: fa00 f203 lsl.w r2, r0, r3 80029ae: 687b ldr r3, [r7, #4] 80029b0: 681b ldr r3, [r3, #0] 80029b2: 430a orrs r2, r1 80029b4: 631a str r2, [r3, #48] @ 0x30 80029b6: e01b b.n 80029f0 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 80029b8: 687b ldr r3, [r7, #4] 80029ba: 681b ldr r3, [r3, #0] 80029bc: 6ad9 ldr r1, [r3, #44] @ 0x2c 80029be: 683b ldr r3, [r7, #0] 80029c0: 685a ldr r2, [r3, #4] 80029c2: 4613 mov r3, r2 80029c4: 009b lsls r3, r3, #2 80029c6: 4413 add r3, r2 80029c8: 3b41 subs r3, #65 @ 0x41 80029ca: 221f movs r2, #31 80029cc: fa02 f303 lsl.w r3, r2, r3 80029d0: 43db mvns r3, r3 80029d2: 4019 ands r1, r3 80029d4: 683b ldr r3, [r7, #0] 80029d6: 6818 ldr r0, [r3, #0] 80029d8: 683b ldr r3, [r7, #0] 80029da: 685a ldr r2, [r3, #4] 80029dc: 4613 mov r3, r2 80029de: 009b lsls r3, r3, #2 80029e0: 4413 add r3, r2 80029e2: 3b41 subs r3, #65 @ 0x41 80029e4: fa00 f203 lsl.w r2, r0, r3 80029e8: 687b ldr r3, [r7, #4] 80029ea: 681b ldr r3, [r3, #0] 80029ec: 430a orrs r2, r1 80029ee: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 80029f0: 683b ldr r3, [r7, #0] 80029f2: 681b ldr r3, [r3, #0] 80029f4: 2b09 cmp r3, #9 80029f6: d91c bls.n 8002a32 { MODIFY_REG(hadc->Instance->SMPR1 , 80029f8: 687b ldr r3, [r7, #4] 80029fa: 681b ldr r3, [r3, #0] 80029fc: 68d9 ldr r1, [r3, #12] 80029fe: 683b ldr r3, [r7, #0] 8002a00: 681a ldr r2, [r3, #0] 8002a02: 4613 mov r3, r2 8002a04: 005b lsls r3, r3, #1 8002a06: 4413 add r3, r2 8002a08: 3b1e subs r3, #30 8002a0a: 2207 movs r2, #7 8002a0c: fa02 f303 lsl.w r3, r2, r3 8002a10: 43db mvns r3, r3 8002a12: 4019 ands r1, r3 8002a14: 683b ldr r3, [r7, #0] 8002a16: 6898 ldr r0, [r3, #8] 8002a18: 683b ldr r3, [r7, #0] 8002a1a: 681a ldr r2, [r3, #0] 8002a1c: 4613 mov r3, r2 8002a1e: 005b lsls r3, r3, #1 8002a20: 4413 add r3, r2 8002a22: 3b1e subs r3, #30 8002a24: fa00 f203 lsl.w r2, r0, r3 8002a28: 687b ldr r3, [r7, #4] 8002a2a: 681b ldr r3, [r3, #0] 8002a2c: 430a orrs r2, r1 8002a2e: 60da str r2, [r3, #12] 8002a30: e019 b.n 8002a66 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8002a32: 687b ldr r3, [r7, #4] 8002a34: 681b ldr r3, [r3, #0] 8002a36: 6919 ldr r1, [r3, #16] 8002a38: 683b ldr r3, [r7, #0] 8002a3a: 681a ldr r2, [r3, #0] 8002a3c: 4613 mov r3, r2 8002a3e: 005b lsls r3, r3, #1 8002a40: 4413 add r3, r2 8002a42: 2207 movs r2, #7 8002a44: fa02 f303 lsl.w r3, r2, r3 8002a48: 43db mvns r3, r3 8002a4a: 4019 ands r1, r3 8002a4c: 683b ldr r3, [r7, #0] 8002a4e: 6898 ldr r0, [r3, #8] 8002a50: 683b ldr r3, [r7, #0] 8002a52: 681a ldr r2, [r3, #0] 8002a54: 4613 mov r3, r2 8002a56: 005b lsls r3, r3, #1 8002a58: 4413 add r3, r2 8002a5a: fa00 f203 lsl.w r2, r0, r3 8002a5e: 687b ldr r3, [r7, #4] 8002a60: 681b ldr r3, [r3, #0] 8002a62: 430a orrs r2, r1 8002a64: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002a66: 683b ldr r3, [r7, #0] 8002a68: 681b ldr r3, [r3, #0] 8002a6a: 2b10 cmp r3, #16 8002a6c: d003 beq.n 8002a76 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8002a6e: 683b ldr r3, [r7, #0] 8002a70: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8002a72: 2b11 cmp r3, #17 8002a74: d132 bne.n 8002adc { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8002a76: 687b ldr r3, [r7, #4] 8002a78: 681b ldr r3, [r3, #0] 8002a7a: 4a1d ldr r2, [pc, #116] @ (8002af0 ) 8002a7c: 4293 cmp r3, r2 8002a7e: d125 bne.n 8002acc { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8002a80: 687b ldr r3, [r7, #4] 8002a82: 681b ldr r3, [r3, #0] 8002a84: 689b ldr r3, [r3, #8] 8002a86: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8002a8a: 2b00 cmp r3, #0 8002a8c: d126 bne.n 8002adc { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8002a8e: 687b ldr r3, [r7, #4] 8002a90: 681b ldr r3, [r3, #0] 8002a92: 689a ldr r2, [r3, #8] 8002a94: 687b ldr r3, [r7, #4] 8002a96: 681b ldr r3, [r3, #0] 8002a98: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8002a9c: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8002a9e: 683b ldr r3, [r7, #0] 8002aa0: 681b ldr r3, [r3, #0] 8002aa2: 2b10 cmp r3, #16 8002aa4: d11a bne.n 8002adc { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8002aa6: 4b13 ldr r3, [pc, #76] @ (8002af4 ) 8002aa8: 681b ldr r3, [r3, #0] 8002aaa: 4a13 ldr r2, [pc, #76] @ (8002af8 ) 8002aac: fba2 2303 umull r2, r3, r2, r3 8002ab0: 0c9a lsrs r2, r3, #18 8002ab2: 4613 mov r3, r2 8002ab4: 009b lsls r3, r3, #2 8002ab6: 4413 add r3, r2 8002ab8: 005b lsls r3, r3, #1 8002aba: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002abc: e002 b.n 8002ac4 { wait_loop_index--; 8002abe: 68bb ldr r3, [r7, #8] 8002ac0: 3b01 subs r3, #1 8002ac2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002ac4: 68bb ldr r3, [r7, #8] 8002ac6: 2b00 cmp r3, #0 8002ac8: d1f9 bne.n 8002abe 8002aca: e007 b.n 8002adc } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002acc: 687b ldr r3, [r7, #4] 8002ace: 6a9b ldr r3, [r3, #40] @ 0x28 8002ad0: f043 0220 orr.w r2, r3, #32 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8002ad8: 2301 movs r3, #1 8002ada: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002adc: 687b ldr r3, [r7, #4] 8002ade: 2200 movs r2, #0 8002ae0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8002ae4: 7bfb ldrb r3, [r7, #15] } 8002ae6: 4618 mov r0, r3 8002ae8: 3714 adds r7, #20 8002aea: 46bd mov sp, r7 8002aec: bc80 pop {r7} 8002aee: 4770 bx lr 8002af0: 40012400 .word 0x40012400 8002af4: 20000004 .word 0x20000004 8002af8: 431bde83 .word 0x431bde83 08002afc : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8002afc: b580 push {r7, lr} 8002afe: b084 sub sp, #16 8002b00: af00 add r7, sp, #0 8002b02: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002b04: 2300 movs r3, #0 8002b06: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 681b ldr r3, [r3, #0] 8002b0c: 689b ldr r3, [r3, #8] 8002b0e: f003 0301 and.w r3, r3, #1 8002b12: 2b01 cmp r3, #1 8002b14: d12e bne.n 8002b74 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8002b16: 687b ldr r3, [r7, #4] 8002b18: 681b ldr r3, [r3, #0] 8002b1a: 689a ldr r2, [r3, #8] 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 681b ldr r3, [r3, #0] 8002b20: f022 0201 bic.w r2, r2, #1 8002b24: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8002b26: f7ff fe0f bl 8002748 8002b2a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002b2c: e01b b.n 8002b66 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002b2e: f7ff fe0b bl 8002748 8002b32: 4602 mov r2, r0 8002b34: 68fb ldr r3, [r7, #12] 8002b36: 1ad3 subs r3, r2, r3 8002b38: 2b02 cmp r3, #2 8002b3a: d914 bls.n 8002b66 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8002b3c: 687b ldr r3, [r7, #4] 8002b3e: 681b ldr r3, [r3, #0] 8002b40: 689b ldr r3, [r3, #8] 8002b42: f003 0301 and.w r3, r3, #1 8002b46: 2b01 cmp r3, #1 8002b48: d10d bne.n 8002b66 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002b4a: 687b ldr r3, [r7, #4] 8002b4c: 6a9b ldr r3, [r3, #40] @ 0x28 8002b4e: f043 0210 orr.w r2, r3, #16 8002b52: 687b ldr r3, [r7, #4] 8002b54: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002b56: 687b ldr r3, [r7, #4] 8002b58: 6adb ldr r3, [r3, #44] @ 0x2c 8002b5a: f043 0201 orr.w r2, r3, #1 8002b5e: 687b ldr r3, [r7, #4] 8002b60: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 8002b62: 2301 movs r3, #1 8002b64: e007 b.n 8002b76 while(ADC_IS_ENABLE(hadc) != RESET) 8002b66: 687b ldr r3, [r7, #4] 8002b68: 681b ldr r3, [r3, #0] 8002b6a: 689b ldr r3, [r3, #8] 8002b6c: f003 0301 and.w r3, r3, #1 8002b70: 2b01 cmp r3, #1 8002b72: d0dc beq.n 8002b2e } } } /* Return HAL status */ return HAL_OK; 8002b74: 2300 movs r3, #0 } 8002b76: 4618 mov r0, r3 8002b78: 3710 adds r7, #16 8002b7a: 46bd mov sp, r7 8002b7c: bd80 pop {r7, pc} ... 08002b80 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002b80: b480 push {r7} 8002b82: b085 sub sp, #20 8002b84: af00 add r7, sp, #0 8002b86: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002b88: 687b ldr r3, [r7, #4] 8002b8a: f003 0307 and.w r3, r3, #7 8002b8e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002b90: 4b0c ldr r3, [pc, #48] @ (8002bc4 <__NVIC_SetPriorityGrouping+0x44>) 8002b92: 68db ldr r3, [r3, #12] 8002b94: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002b96: 68ba ldr r2, [r7, #8] 8002b98: f64f 03ff movw r3, #63743 @ 0xf8ff 8002b9c: 4013 ands r3, r2 8002b9e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002ba0: 68fb ldr r3, [r7, #12] 8002ba2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002ba4: 68bb ldr r3, [r7, #8] 8002ba6: 4313 orrs r3, r2 reg_value = (reg_value | 8002ba8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002bac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8002bb0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002bb2: 4a04 ldr r2, [pc, #16] @ (8002bc4 <__NVIC_SetPriorityGrouping+0x44>) 8002bb4: 68bb ldr r3, [r7, #8] 8002bb6: 60d3 str r3, [r2, #12] } 8002bb8: bf00 nop 8002bba: 3714 adds r7, #20 8002bbc: 46bd mov sp, r7 8002bbe: bc80 pop {r7} 8002bc0: 4770 bx lr 8002bc2: bf00 nop 8002bc4: e000ed00 .word 0xe000ed00 08002bc8 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8002bc8: b480 push {r7} 8002bca: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002bcc: 4b04 ldr r3, [pc, #16] @ (8002be0 <__NVIC_GetPriorityGrouping+0x18>) 8002bce: 68db ldr r3, [r3, #12] 8002bd0: 0a1b lsrs r3, r3, #8 8002bd2: f003 0307 and.w r3, r3, #7 } 8002bd6: 4618 mov r0, r3 8002bd8: 46bd mov sp, r7 8002bda: bc80 pop {r7} 8002bdc: 4770 bx lr 8002bde: bf00 nop 8002be0: e000ed00 .word 0xe000ed00 08002be4 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002be4: b480 push {r7} 8002be6: b083 sub sp, #12 8002be8: af00 add r7, sp, #0 8002bea: 4603 mov r3, r0 8002bec: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002bee: f997 3007 ldrsb.w r3, [r7, #7] 8002bf2: 2b00 cmp r3, #0 8002bf4: db0b blt.n 8002c0e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002bf6: 79fb ldrb r3, [r7, #7] 8002bf8: f003 021f and.w r2, r3, #31 8002bfc: 4906 ldr r1, [pc, #24] @ (8002c18 <__NVIC_EnableIRQ+0x34>) 8002bfe: f997 3007 ldrsb.w r3, [r7, #7] 8002c02: 095b lsrs r3, r3, #5 8002c04: 2001 movs r0, #1 8002c06: fa00 f202 lsl.w r2, r0, r2 8002c0a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8002c0e: bf00 nop 8002c10: 370c adds r7, #12 8002c12: 46bd mov sp, r7 8002c14: bc80 pop {r7} 8002c16: 4770 bx lr 8002c18: e000e100 .word 0xe000e100 08002c1c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002c1c: b480 push {r7} 8002c1e: b083 sub sp, #12 8002c20: af00 add r7, sp, #0 8002c22: 4603 mov r3, r0 8002c24: 6039 str r1, [r7, #0] 8002c26: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002c28: f997 3007 ldrsb.w r3, [r7, #7] 8002c2c: 2b00 cmp r3, #0 8002c2e: db0a blt.n 8002c46 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002c30: 683b ldr r3, [r7, #0] 8002c32: b2da uxtb r2, r3 8002c34: 490c ldr r1, [pc, #48] @ (8002c68 <__NVIC_SetPriority+0x4c>) 8002c36: f997 3007 ldrsb.w r3, [r7, #7] 8002c3a: 0112 lsls r2, r2, #4 8002c3c: b2d2 uxtb r2, r2 8002c3e: 440b add r3, r1 8002c40: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002c44: e00a b.n 8002c5c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002c46: 683b ldr r3, [r7, #0] 8002c48: b2da uxtb r2, r3 8002c4a: 4908 ldr r1, [pc, #32] @ (8002c6c <__NVIC_SetPriority+0x50>) 8002c4c: 79fb ldrb r3, [r7, #7] 8002c4e: f003 030f and.w r3, r3, #15 8002c52: 3b04 subs r3, #4 8002c54: 0112 lsls r2, r2, #4 8002c56: b2d2 uxtb r2, r2 8002c58: 440b add r3, r1 8002c5a: 761a strb r2, [r3, #24] } 8002c5c: bf00 nop 8002c5e: 370c adds r7, #12 8002c60: 46bd mov sp, r7 8002c62: bc80 pop {r7} 8002c64: 4770 bx lr 8002c66: bf00 nop 8002c68: e000e100 .word 0xe000e100 8002c6c: e000ed00 .word 0xe000ed00 08002c70 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002c70: b480 push {r7} 8002c72: b089 sub sp, #36 @ 0x24 8002c74: af00 add r7, sp, #0 8002c76: 60f8 str r0, [r7, #12] 8002c78: 60b9 str r1, [r7, #8] 8002c7a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002c7c: 68fb ldr r3, [r7, #12] 8002c7e: f003 0307 and.w r3, r3, #7 8002c82: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002c84: 69fb ldr r3, [r7, #28] 8002c86: f1c3 0307 rsb r3, r3, #7 8002c8a: 2b04 cmp r3, #4 8002c8c: bf28 it cs 8002c8e: 2304 movcs r3, #4 8002c90: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002c92: 69fb ldr r3, [r7, #28] 8002c94: 3304 adds r3, #4 8002c96: 2b06 cmp r3, #6 8002c98: d902 bls.n 8002ca0 8002c9a: 69fb ldr r3, [r7, #28] 8002c9c: 3b03 subs r3, #3 8002c9e: e000 b.n 8002ca2 8002ca0: 2300 movs r3, #0 8002ca2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002ca4: f04f 32ff mov.w r2, #4294967295 8002ca8: 69bb ldr r3, [r7, #24] 8002caa: fa02 f303 lsl.w r3, r2, r3 8002cae: 43da mvns r2, r3 8002cb0: 68bb ldr r3, [r7, #8] 8002cb2: 401a ands r2, r3 8002cb4: 697b ldr r3, [r7, #20] 8002cb6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002cb8: f04f 31ff mov.w r1, #4294967295 8002cbc: 697b ldr r3, [r7, #20] 8002cbe: fa01 f303 lsl.w r3, r1, r3 8002cc2: 43d9 mvns r1, r3 8002cc4: 687b ldr r3, [r7, #4] 8002cc6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002cc8: 4313 orrs r3, r2 ); } 8002cca: 4618 mov r0, r3 8002ccc: 3724 adds r7, #36 @ 0x24 8002cce: 46bd mov sp, r7 8002cd0: bc80 pop {r7} 8002cd2: 4770 bx lr 08002cd4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002cd4: b580 push {r7, lr} 8002cd6: b082 sub sp, #8 8002cd8: af00 add r7, sp, #0 8002cda: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002cdc: 687b ldr r3, [r7, #4] 8002cde: 3b01 subs r3, #1 8002ce0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002ce4: d301 bcc.n 8002cea { return (1UL); /* Reload value impossible */ 8002ce6: 2301 movs r3, #1 8002ce8: e00f b.n 8002d0a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002cea: 4a0a ldr r2, [pc, #40] @ (8002d14 ) 8002cec: 687b ldr r3, [r7, #4] 8002cee: 3b01 subs r3, #1 8002cf0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002cf2: 210f movs r1, #15 8002cf4: f04f 30ff mov.w r0, #4294967295 8002cf8: f7ff ff90 bl 8002c1c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002cfc: 4b05 ldr r3, [pc, #20] @ (8002d14 ) 8002cfe: 2200 movs r2, #0 8002d00: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002d02: 4b04 ldr r3, [pc, #16] @ (8002d14 ) 8002d04: 2207 movs r2, #7 8002d06: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002d08: 2300 movs r3, #0 } 8002d0a: 4618 mov r0, r3 8002d0c: 3708 adds r7, #8 8002d0e: 46bd mov sp, r7 8002d10: bd80 pop {r7, pc} 8002d12: bf00 nop 8002d14: e000e010 .word 0xe000e010 08002d18 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002d18: b580 push {r7, lr} 8002d1a: b082 sub sp, #8 8002d1c: af00 add r7, sp, #0 8002d1e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002d20: 6878 ldr r0, [r7, #4] 8002d22: f7ff ff2d bl 8002b80 <__NVIC_SetPriorityGrouping> } 8002d26: bf00 nop 8002d28: 3708 adds r7, #8 8002d2a: 46bd mov sp, r7 8002d2c: bd80 pop {r7, pc} 08002d2e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002d2e: b580 push {r7, lr} 8002d30: b086 sub sp, #24 8002d32: af00 add r7, sp, #0 8002d34: 4603 mov r3, r0 8002d36: 60b9 str r1, [r7, #8] 8002d38: 607a str r2, [r7, #4] 8002d3a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8002d3c: 2300 movs r3, #0 8002d3e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002d40: f7ff ff42 bl 8002bc8 <__NVIC_GetPriorityGrouping> 8002d44: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002d46: 687a ldr r2, [r7, #4] 8002d48: 68b9 ldr r1, [r7, #8] 8002d4a: 6978 ldr r0, [r7, #20] 8002d4c: f7ff ff90 bl 8002c70 8002d50: 4602 mov r2, r0 8002d52: f997 300f ldrsb.w r3, [r7, #15] 8002d56: 4611 mov r1, r2 8002d58: 4618 mov r0, r3 8002d5a: f7ff ff5f bl 8002c1c <__NVIC_SetPriority> } 8002d5e: bf00 nop 8002d60: 3718 adds r7, #24 8002d62: 46bd mov sp, r7 8002d64: bd80 pop {r7, pc} 08002d66 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002d66: b580 push {r7, lr} 8002d68: b082 sub sp, #8 8002d6a: af00 add r7, sp, #0 8002d6c: 4603 mov r3, r0 8002d6e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002d70: f997 3007 ldrsb.w r3, [r7, #7] 8002d74: 4618 mov r0, r3 8002d76: f7ff ff35 bl 8002be4 <__NVIC_EnableIRQ> } 8002d7a: bf00 nop 8002d7c: 3708 adds r7, #8 8002d7e: 46bd mov sp, r7 8002d80: bd80 pop {r7, pc} 08002d82 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002d82: b580 push {r7, lr} 8002d84: b082 sub sp, #8 8002d86: af00 add r7, sp, #0 8002d88: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002d8a: 6878 ldr r0, [r7, #4] 8002d8c: f7ff ffa2 bl 8002cd4 8002d90: 4603 mov r3, r0 } 8002d92: 4618 mov r0, r3 8002d94: 3708 adds r7, #8 8002d96: 46bd mov sp, r7 8002d98: bd80 pop {r7, pc} 08002d9a : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002d9a: b480 push {r7} 8002d9c: b085 sub sp, #20 8002d9e: af00 add r7, sp, #0 8002da0: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002da2: 2300 movs r3, #0 8002da4: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8002da6: 687b ldr r3, [r7, #4] 8002da8: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002dac: b2db uxtb r3, r3 8002dae: 2b02 cmp r3, #2 8002db0: d008 beq.n 8002dc4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002db2: 687b ldr r3, [r7, #4] 8002db4: 2204 movs r2, #4 8002db6: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002db8: 687b ldr r3, [r7, #4] 8002dba: 2200 movs r2, #0 8002dbc: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8002dc0: 2301 movs r3, #1 8002dc2: e020 b.n 8002e06 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 681b ldr r3, [r3, #0] 8002dc8: 681a ldr r2, [r3, #0] 8002dca: 687b ldr r3, [r7, #4] 8002dcc: 681b ldr r3, [r3, #0] 8002dce: f022 020e bic.w r2, r2, #14 8002dd2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 681b ldr r3, [r3, #0] 8002dd8: 681a ldr r2, [r3, #0] 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 681b ldr r3, [r3, #0] 8002dde: f022 0201 bic.w r2, r2, #1 8002de2: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002de4: 687b ldr r3, [r7, #4] 8002de6: 6c1a ldr r2, [r3, #64] @ 0x40 8002de8: 687b ldr r3, [r7, #4] 8002dea: 6bdb ldr r3, [r3, #60] @ 0x3c 8002dec: 2101 movs r1, #1 8002dee: fa01 f202 lsl.w r2, r1, r2 8002df2: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002df4: 687b ldr r3, [r7, #4] 8002df6: 2201 movs r2, #1 8002df8: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002dfc: 687b ldr r3, [r7, #4] 8002dfe: 2200 movs r2, #0 8002e00: f883 2020 strb.w r2, [r3, #32] return status; 8002e04: 7bfb ldrb r3, [r7, #15] } 8002e06: 4618 mov r0, r3 8002e08: 3714 adds r7, #20 8002e0a: 46bd mov sp, r7 8002e0c: bc80 pop {r7} 8002e0e: 4770 bx lr 08002e10 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002e10: b580 push {r7, lr} 8002e12: b084 sub sp, #16 8002e14: af00 add r7, sp, #0 8002e16: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002e18: 2300 movs r3, #0 8002e1a: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8002e1c: 687b ldr r3, [r7, #4] 8002e1e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8002e22: b2db uxtb r3, r3 8002e24: 2b02 cmp r3, #2 8002e26: d005 beq.n 8002e34 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002e28: 687b ldr r3, [r7, #4] 8002e2a: 2204 movs r2, #4 8002e2c: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8002e2e: 2301 movs r3, #1 8002e30: 73fb strb r3, [r7, #15] 8002e32: e051 b.n 8002ed8 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002e34: 687b ldr r3, [r7, #4] 8002e36: 681b ldr r3, [r3, #0] 8002e38: 681a ldr r2, [r3, #0] 8002e3a: 687b ldr r3, [r7, #4] 8002e3c: 681b ldr r3, [r3, #0] 8002e3e: f022 020e bic.w r2, r2, #14 8002e42: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002e44: 687b ldr r3, [r7, #4] 8002e46: 681b ldr r3, [r3, #0] 8002e48: 681a ldr r2, [r3, #0] 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 681b ldr r3, [r3, #0] 8002e4e: f022 0201 bic.w r2, r2, #1 8002e52: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8002e54: 687b ldr r3, [r7, #4] 8002e56: 681b ldr r3, [r3, #0] 8002e58: 4a22 ldr r2, [pc, #136] @ (8002ee4 ) 8002e5a: 4293 cmp r3, r2 8002e5c: d029 beq.n 8002eb2 8002e5e: 687b ldr r3, [r7, #4] 8002e60: 681b ldr r3, [r3, #0] 8002e62: 4a21 ldr r2, [pc, #132] @ (8002ee8 ) 8002e64: 4293 cmp r3, r2 8002e66: d022 beq.n 8002eae 8002e68: 687b ldr r3, [r7, #4] 8002e6a: 681b ldr r3, [r3, #0] 8002e6c: 4a1f ldr r2, [pc, #124] @ (8002eec ) 8002e6e: 4293 cmp r3, r2 8002e70: d01a beq.n 8002ea8 8002e72: 687b ldr r3, [r7, #4] 8002e74: 681b ldr r3, [r3, #0] 8002e76: 4a1e ldr r2, [pc, #120] @ (8002ef0 ) 8002e78: 4293 cmp r3, r2 8002e7a: d012 beq.n 8002ea2 8002e7c: 687b ldr r3, [r7, #4] 8002e7e: 681b ldr r3, [r3, #0] 8002e80: 4a1c ldr r2, [pc, #112] @ (8002ef4 ) 8002e82: 4293 cmp r3, r2 8002e84: d00a beq.n 8002e9c 8002e86: 687b ldr r3, [r7, #4] 8002e88: 681b ldr r3, [r3, #0] 8002e8a: 4a1b ldr r2, [pc, #108] @ (8002ef8 ) 8002e8c: 4293 cmp r3, r2 8002e8e: d102 bne.n 8002e96 8002e90: f44f 1380 mov.w r3, #1048576 @ 0x100000 8002e94: e00e b.n 8002eb4 8002e96: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8002e9a: e00b b.n 8002eb4 8002e9c: f44f 3380 mov.w r3, #65536 @ 0x10000 8002ea0: e008 b.n 8002eb4 8002ea2: f44f 5380 mov.w r3, #4096 @ 0x1000 8002ea6: e005 b.n 8002eb4 8002ea8: f44f 7380 mov.w r3, #256 @ 0x100 8002eac: e002 b.n 8002eb4 8002eae: 2310 movs r3, #16 8002eb0: e000 b.n 8002eb4 8002eb2: 2301 movs r3, #1 8002eb4: 4a11 ldr r2, [pc, #68] @ (8002efc ) 8002eb6: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002eb8: 687b ldr r3, [r7, #4] 8002eba: 2201 movs r2, #1 8002ebc: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 2200 movs r2, #0 8002ec4: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002ec8: 687b ldr r3, [r7, #4] 8002eca: 6b5b ldr r3, [r3, #52] @ 0x34 8002ecc: 2b00 cmp r3, #0 8002ece: d003 beq.n 8002ed8 { hdma->XferAbortCallback(hdma); 8002ed0: 687b ldr r3, [r7, #4] 8002ed2: 6b5b ldr r3, [r3, #52] @ 0x34 8002ed4: 6878 ldr r0, [r7, #4] 8002ed6: 4798 blx r3 } } return status; 8002ed8: 7bfb ldrb r3, [r7, #15] } 8002eda: 4618 mov r0, r3 8002edc: 3710 adds r7, #16 8002ede: 46bd mov sp, r7 8002ee0: bd80 pop {r7, pc} 8002ee2: bf00 nop 8002ee4: 40020008 .word 0x40020008 8002ee8: 4002001c .word 0x4002001c 8002eec: 40020030 .word 0x40020030 8002ef0: 40020044 .word 0x40020044 8002ef4: 40020058 .word 0x40020058 8002ef8: 4002006c .word 0x4002006c 8002efc: 40020000 .word 0x40020000 08002f00 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002f00: b480 push {r7} 8002f02: b08b sub sp, #44 @ 0x2c 8002f04: af00 add r7, sp, #0 8002f06: 6078 str r0, [r7, #4] 8002f08: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8002f0a: 2300 movs r3, #0 8002f0c: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8002f0e: 2300 movs r3, #0 8002f10: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8002f12: e169 b.n 80031e8 { /* Get the IO position */ ioposition = (0x01uL << position); 8002f14: 2201 movs r2, #1 8002f16: 6a7b ldr r3, [r7, #36] @ 0x24 8002f18: fa02 f303 lsl.w r3, r2, r3 8002f1c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002f1e: 683b ldr r3, [r7, #0] 8002f20: 681b ldr r3, [r3, #0] 8002f22: 69fa ldr r2, [r7, #28] 8002f24: 4013 ands r3, r2 8002f26: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8002f28: 69ba ldr r2, [r7, #24] 8002f2a: 69fb ldr r3, [r7, #28] 8002f2c: 429a cmp r2, r3 8002f2e: f040 8158 bne.w 80031e2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8002f32: 683b ldr r3, [r7, #0] 8002f34: 685b ldr r3, [r3, #4] 8002f36: 4a9a ldr r2, [pc, #616] @ (80031a0 ) 8002f38: 4293 cmp r3, r2 8002f3a: d05e beq.n 8002ffa 8002f3c: 4a98 ldr r2, [pc, #608] @ (80031a0 ) 8002f3e: 4293 cmp r3, r2 8002f40: d875 bhi.n 800302e