diff --git a/Fertirrega_v6/.cproject b/Fertirrega_v6/.cproject
index 101edd0..5343474 100644
--- a/Fertirrega_v6/.cproject
+++ b/Fertirrega_v6/.cproject
@@ -22,7 +22,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1300994539" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1159445424" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1559131597" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F103C8Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F103xB ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F103C8TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  ||  || ::" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.711064352" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="24" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.711064352" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="12" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.213506800" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Fertirrega_v6}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.31873527" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1210620532" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -100,7 +100,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1343902751" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1177435666" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.459852496" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F103C8Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F103xB ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F103C8TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  ||  || ::" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.948545308" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="24" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.948545308" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="12" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.865704468" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Fertirrega_v6}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1462031276" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.114926246" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/Fertirrega_v6/.mxproject b/Fertirrega_v6/.mxproject
index c5b50cc..dd7b9cd 100644
--- a/Fertirrega_v6/.mxproject
+++ b/Fertirrega_v6/.mxproject
@@ -1,32 +1,36 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_adc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
 
 [PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\adc.c;Core\Src\i2c.c;Core\Src\usart.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;;;
+SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\adc.c;Core\Src\dma.c;Core\Src\i2c.c;Core\Src\tim.c;Core\Src\usart.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;;;
 HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Core\Inc;
 CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
 [PreviousGenFiles]
 AdvancedFolderStructure=true
-HeaderFileListSize=7
+HeaderFileListSize=9
 HeaderFiles#0=..\Core\Inc\gpio.h
 HeaderFiles#1=..\Core\Inc\adc.h
-HeaderFiles#2=..\Core\Inc\i2c.h
-HeaderFiles#3=..\Core\Inc\usart.h
-HeaderFiles#4=..\Core\Inc\stm32f1xx_it.h
-HeaderFiles#5=..\Core\Inc\stm32f1xx_hal_conf.h
-HeaderFiles#6=..\Core\Inc\main.h
+HeaderFiles#2=..\Core\Inc\dma.h
+HeaderFiles#3=..\Core\Inc\i2c.h
+HeaderFiles#4=..\Core\Inc\tim.h
+HeaderFiles#5=..\Core\Inc\usart.h
+HeaderFiles#6=..\Core\Inc\stm32f1xx_it.h
+HeaderFiles#7=..\Core\Inc\stm32f1xx_hal_conf.h
+HeaderFiles#8=..\Core\Inc\main.h
 HeaderFolderListSize=1
 HeaderPath#0=..\Core\Inc
 HeaderFiles=;
-SourceFileListSize=7
+SourceFileListSize=9
 SourceFiles#0=..\Core\Src\gpio.c
 SourceFiles#1=..\Core\Src\adc.c
-SourceFiles#2=..\Core\Src\i2c.c
-SourceFiles#3=..\Core\Src\usart.c
-SourceFiles#4=..\Core\Src\stm32f1xx_it.c
-SourceFiles#5=..\Core\Src\stm32f1xx_hal_msp.c
-SourceFiles#6=..\Core\Src\main.c
+SourceFiles#2=..\Core\Src\dma.c
+SourceFiles#3=..\Core\Src\i2c.c
+SourceFiles#4=..\Core\Src\tim.c
+SourceFiles#5=..\Core\Src\usart.c
+SourceFiles#6=..\Core\Src\stm32f1xx_it.c
+SourceFiles#7=..\Core\Src\stm32f1xx_hal_msp.c
+SourceFiles#8=..\Core\Src\main.c
 SourceFolderListSize=1
 SourcePath#0=..\Core\Src
 SourceFiles=;
diff --git a/Fertirrega_v6/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/Fertirrega_v6/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs
new file mode 100644
index 0000000..98a69fc
--- /dev/null
+++ b/Fertirrega_v6/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}}
diff --git a/Fertirrega_v6/Core/Inc/ad5934_driver.h b/Fertirrega_v6/Core/Inc/ad5934_driver.h
index c2b19ae..9428805 100644
--- a/Fertirrega_v6/Core/Inc/ad5934_driver.h
+++ b/Fertirrega_v6/Core/Inc/ad5934_driver.h
@@ -13,6 +13,8 @@
 #define INC_AD5934_DRIVER_H_
 
 #include "stm32f1xx_hal.h"
+#include "flash_manager.h"
+#include "main.h"
 #include <math.h>
 #include <stdlib.h>
 
@@ -111,6 +113,7 @@ extern "C" {
 #define ADG715_SW7	    				0x40 //RTD Input
 #define ADG715_SW8	    				0x80 //CE Input
 
+/*
 #define AD5934_CH_REF_100R				0x10
 #define AD5934_CH_REF_1K				0x11
 #define AD5934_CH_REF_10K				0x12
@@ -118,6 +121,32 @@ extern "C" {
 #define AD5934_CH_PT1000				0x01
 #define AD5934_CH_EC_10MS				0x21
 #define AD5934_CH_EC_5MS				0x22
+*/
+
+#define AD5934_CH_REF100R_LOW_GAIN		0x09
+#define AD5934_CH_REF100R_MID_GAIN		0x0A
+#define AD5934_CH_REF100R_HIGH_GAIN		0x0C
+#define AD5934_CH_REF1K_LOW_GAIN		0x11
+#define AD5934_CH_REF1K_MID_GAIN		0x12
+#define AD5934_CH_REF1K_HIGH_GAIN		0x14
+#define AD5934_CH_REF10K_LOW_GAIN		0x21
+#define AD5934_CH_REF10K_MID_GAIN		0x22
+#define AD5934_CH_REF10K_HIGH_GAIN		0x24
+#define AD5934_CH_RTD_LOW_GAIN			0x41
+#define AD5934_CH_RTD_MID_GAIN			0x42
+#define AD5934_CH_RTD_HIGH_GAIN			0x44
+#define AD5934_CH_EC_LOW_GAIN			0x81
+#define AD5934_CH_EC_MID_GAIN			0x82
+#define AD5934_CH_EC_HIGH_GAIN			0x84
+
+#define AD5934_LOW_GAIN_BASE			0x01
+#define AD5934_MID_GAIN_BASE			0x02
+#define AD5934_HIGH_GAIN_BASE			0x04
+#define AD5934_REF100R_BASE				0x08
+#define AD5934_REF1K_BASE				0x10
+#define AD5934_REF10K_BASE				0x20
+#define AD5934_RTD_BASE					0x40
+#define AD5934_CE_BASE					0x80
 
 
 #define AD5934_CH_DELTA					0x10
@@ -126,6 +155,9 @@ extern "C" {
 #define AD5934_GAIN_FACTOR_1K			1000.0f
 #define AD5934_GAIN_FACTOR_10K			10000.0f
 
+#define AD5934_GAIN_FACTOR_1413US		1413.0f
+#define AD5934_GAIN_FACTOR_12880US		12880.0f
+
 #define AD5934_RTD_A					3.9083e-3f
 #define AD5934_RTD_B					(-5.775e-7f)
 
@@ -160,8 +192,6 @@ extern int16_t ec_ref1_samples[AD5934_EC_AVERAGES][2];
 extern int16_t ec_ref2_samples[AD5934_EC_AVERAGES][2];
 extern float ec_display[AD5934_EC_AVERAGES];
 extern float ec_temp_dut[AD5934_EC_AVERAGES];
-extern float ec_temp_ref1[AD5934_EC_AVERAGES];
-extern float ec_temp_ref2[AD5934_EC_AVERAGES];
 
 extern I2C_HandleTypeDef hi2c2;
 
diff --git a/Fertirrega_v6/Core/Inc/ads1015_driver.h b/Fertirrega_v6/Core/Inc/ads1015_driver.h
index 6f28dd9..fa7c083 100644
--- a/Fertirrega_v6/Core/Inc/ads1015_driver.h
+++ b/Fertirrega_v6/Core/Inc/ads1015_driver.h
@@ -13,7 +13,9 @@
 #define INC_ADS1015_DRIVER_H_
 
 #include <stdint.h>
+#include "main.h" // Assuming HAL is included via main.h
 #include "stm32f1xx_hal.h"
+#include "flash_manager.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -124,6 +126,7 @@ extern "C" {
 #define 		ADS1015_KELVIN_OFFSET	  	273.15f // Constante de conversão Kelvin
 #define			ADS1015_ADC_MAX 			4095.0f
 #define		 	ADS1015_ADC_VREF 			3.3f
+#define			ADS1015_PH_AVERAGES			8
 
 /*=========================================================================*/
 
@@ -146,8 +149,9 @@ typedef struct {
 	I2C_HandleTypeDef* hi2c;    // Handle for I2C
 }ADS1015_I2C;
 
-extern float temp_calib, ph_compensated, v_ph4, v_ph7;
+extern float ph_averages[ADS1015_PH_AVERAGES];
 
+extern ADS1015_I2C i2c;
 
 void ADS1015(ADS1015_I2C* i2c, I2C_HandleTypeDef* hi2c, uint8_t i2cAddress);
 uint16_t ADSreadADC_SingleEnded(ADS1015_I2C* i2c, uint8_t channel);
@@ -157,7 +161,7 @@ void  ADSstartComparator_SingleEnded(ADS1015_I2C* i2c, uint8_t channel, int16_t
 int16_t  ADSgetLastConversionResults();
 void  ADSsetGain(ADS1015_I2C* i2c, adsGain_t gain);
 adsGain_t  ADSgetGain(ADS1015_I2C* i2c);
-float ADSCalculate_ph_Volts(int16_t adc_raw);
+float ADSCalculate_ph_Volts(void);
 float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut);
 
 #endif /* INC_ADS1015_DRIVER_H_ */
diff --git a/Fertirrega_v6/Core/Inc/dma.h b/Fertirrega_v6/Core/Inc/dma.h
new file mode 100644
index 0000000..afad30d
--- /dev/null
+++ b/Fertirrega_v6/Core/Inc/dma.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dma.h
+  * @brief   This file contains all the function prototypes for
+  *          the dma.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* DMA memory to memory transfer handles -------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DMA_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_H__ */
+
diff --git a/Fertirrega_v6/Core/Inc/flash_manager.h b/Fertirrega_v6/Core/Inc/flash_manager.h
index 5289c82..9fb76b9 100644
--- a/Fertirrega_v6/Core/Inc/flash_manager.h
+++ b/Fertirrega_v6/Core/Inc/flash_manager.h
@@ -25,14 +25,19 @@
  * @brief Estrutura de 1KB alinhada e preenchida.
  * O uso de padding manual garante que não haja surpresas com o compilador.
  */
-typedef struct __attribute__((packed, aligned(4))) {
-    uint32_t magic_number;      // 4 bytes (Validação)
-    float    calibration_offset; // 4 bytes
-    uint16_t sensor_threshold;   // 2 bytes
-    uint8_t  status_flag;        // 1 byte
-    uint8_t  reserved[1013];     // Preenchimento para completar 1024 bytes (1KB)
+typedef struct __attribute__((packed, aligned(4)))
+{
+	uint32_t magic_number; // 4 bytes (Validação)
+	float ph4_value;		// 4 bytes
+	float ph7_value;		// 4 bytes
+	float ec1413_value;		// 4 bytes
+	float ec12880_value;	// 4 bytes
+	float temperature_value;// 4 bytes
+    uint8_t  reserved[1000];     // Preenchimento para completar 1024 bytes (1KB)
 } FlashPage_t;
 
+extern FlashPage_t flash_data;
+
 /* Protótipos */
 HAL_StatusTypeDef Flash_Save_Page(FlashPage_t *pPage);
 HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest);
diff --git a/Fertirrega_v6/Core/Inc/main.h b/Fertirrega_v6/Core/Inc/main.h
index 0ae077b..af211c0 100644
--- a/Fertirrega_v6/Core/Inc/main.h
+++ b/Fertirrega_v6/Core/Inc/main.h
@@ -127,8 +127,15 @@ void Error_Handler(void);
 
 /* USER CODE BEGIN Private defines */
 
+#define 	STATE_RUNNING_OK				0x00
+#define 	STATE_SETUP_CALIBRATION			0x01
+#define 	STATE_RS485_SUPPLY_FAULT		0x02
+#define 	STATE_PH_SUPPLY_FAULT			0x03
+#define 	STATE_EC_RTD_SUPPLY_FAULT		0x04
+#define 	STATE_NO_SETUP_CALIBRATION		0x05
+#define 	STATE_HIGH_AMBIENT_TEMPERATURE	0x06
 
-
+extern uint8_t main_state;
 /* USER CODE END Private defines */
 
 #ifdef __cplusplus
diff --git a/Fertirrega_v6/Core/Inc/stm32f1xx_hal_conf.h b/Fertirrega_v6/Core/Inc/stm32f1xx_hal_conf.h
index 33379ab..e745e9c 100644
--- a/Fertirrega_v6/Core/Inc/stm32f1xx_hal_conf.h
+++ b/Fertirrega_v6/Core/Inc/stm32f1xx_hal_conf.h
@@ -42,7 +42,7 @@
 /*#define HAL_CORTEX_MODULE_ENABLED   */
 /*#define HAL_CRC_MODULE_ENABLED   */
 /*#define HAL_DAC_MODULE_ENABLED   */
-/*#define HAL_DMA_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
 /*#define HAL_ETH_MODULE_ENABLED   */
 /*#define HAL_FLASH_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED
@@ -64,7 +64,7 @@
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 /*#define HAL_SPI_MODULE_ENABLED   */
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */
diff --git a/Fertirrega_v6/Core/Inc/stm32f1xx_it.h b/Fertirrega_v6/Core/Inc/stm32f1xx_it.h
index d5b375b..5170559 100644
--- a/Fertirrega_v6/Core/Inc/stm32f1xx_it.h
+++ b/Fertirrega_v6/Core/Inc/stm32f1xx_it.h
@@ -56,6 +56,7 @@ void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
 void EXTI3_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
 void USART1_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
diff --git a/Fertirrega_v6/Core/Inc/tim.h b/Fertirrega_v6/Core/Inc/tim.h
new file mode 100644
index 0000000..a3c3067
--- /dev/null
+++ b/Fertirrega_v6/Core/Inc/tim.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for
+  *          the tim.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim3;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM3_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+
diff --git a/Fertirrega_v6/Core/Src/ad5934_driver.c b/Fertirrega_v6/Core/Src/ad5934_driver.c
index cba3984..7e591a9 100644
--- a/Fertirrega_v6/Core/Src/ad5934_driver.c
+++ b/Fertirrega_v6/Core/Src/ad5934_driver.c
@@ -11,19 +11,14 @@
 
 #include "ad5934_driver.h"
 
-const float calibrationResistance[3] = {AD5934_GAIN_FACTOR_100R, AD5934_GAIN_FACTOR_1K, AD5934_GAIN_FACTOR_10K};
-
 int16_t temperature_dut_samples[AD5934_TEMP_AVERAGES][2]={{0},{0}};
 int16_t temperature_ref_samples[AD5934_TEMP_AVERAGES][2]={{0},{0}};
 float temperature_display[AD5934_TEMP_AVERAGES] = {0};
 
 
 int16_t ec_dut_samples[AD5934_EC_AVERAGES][2]={{0},{0}};
-int16_t ec_ref_samples_H[AD5934_EC_AVERAGES][2]={{0},{0}};
-int16_t ec_ref_samples_L[AD5934_EC_AVERAGES][2]={{0},{0}};
 float ec_display[AD5934_EC_AVERAGES] = {0};
 
-
 /******************************************************************************
 * @brief Set an AD5934 internal register value.
 *
@@ -221,17 +216,25 @@ uint32_t AD5934_Sweep(void)
 ******************************************************************************/
 float AD5934_GetTemperature(void)
 {
-	uint8_t i, channel;
+	uint8_t i, ch_dut, ch_ref;
 	uint32_t sample;
 	int32_t ref_sum[2], dut_sum[2];
-	float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum;
+	float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum, gain_factor;
 
 	if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
-		channel = AD5934_CH_PT100;
+	{
+		ch_ref = AD5934_CH_REF100R_LOW_GAIN;
+		ch_dut = AD5934_CH_RTD_LOW_GAIN; //PT100
+		gain_factor = 100.0f;
+	}
 	else
-		channel = AD5934_CH_PT1000;
+	{
+		ch_ref = AD5934_CH_REF1K_MID_GAIN;
+		ch_dut = AD5934_CH_RTD_MID_GAIN; //PT1000
+		gain_factor = 1000.0f;
+	}
 
-	ADG715_Update(channel + AD5934_CH_DELTA); // Set the Reference Resistor on board in the Analog Mux
+	ADG715_Update(ch_ref); // Set the Reference Resistor on board in the Analog Mux
 	HAL_Delay(2); //Wait a little
 
 	sample = AD5934_Sweep(); // Get Reference Resistor Values from ADC
@@ -261,7 +264,7 @@ float AD5934_GetTemperature(void)
 	// Calculate gain factor impedance
 	mag_ref = sqrtf((real_ref * real_ref) + (imag_ref * imag_ref));
 
-	ADG715_Update(channel);
+	ADG715_Update(ch_dut);
 	HAL_Delay(2);
 
 	sample = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
@@ -295,13 +298,13 @@ float AD5934_GetTemperature(void)
 
 	ratio_mag = mag_ref / mag_dut;
 
-	if(channel==AD5934_CH_PT100)
-		impedance_dut = AD5934_Linear_Correction((calibrationResistance[channel & 0x0F]) * ratio_mag);
+	if(ch_ref==AD5934_CH_REF100R_LOW_GAIN) // only for PT100
+		impedance_dut = AD5934_Linear_Correction(gain_factor * ratio_mag);
 	else
-		impedance_dut = (calibrationResistance[channel & 0x0F]) * ratio_mag;
+		impedance_dut = gain_factor * ratio_mag;
 
 	// Calculate impedance ratio with the Reference Resistor
-	ratio = impedance_dut / (calibrationResistance[channel & 0x0F]);
+	ratio = impedance_dut / gain_factor;
 
 	// Calculate impedance discriminant with the ratio
 	discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio));
@@ -330,92 +333,24 @@ float AD5934_GetTemperature(void)
 ******************************************************************************/
 float AD5934_GetImpedance(void)
 {
-	uint8_t i, channel;
-	uint32_t sample_H, sample_L, sample_dut;
-	int32_t ref_sum_H[2], ref_sum_L[2], dut_sum[2];
-	float real_number, imag_number, mag_dut, mag_ref_H, mag_ref_L, gain_factor_H, gain_factor_L, gain_factor_dut, slope, admittance;
-
-	/* STEP 1: Two points reference curve  */
-
-	ADG715_Update(AD5934_CH_REF_1K); // Set the Reference for High Resistor on board in the Analog Mux
-	HAL_Delay(2); //Wait a little
-
-	sample_H = AD5934_Sweep(); // Get Reference Resistor 1 from ADC
-
-	ADG715_Update(AD5934_CH_REF_100R); // Set the Reference for Low Resistor on board in the Analog Mux
-	HAL_Delay(2); //Wait a little
-
-	sample_L = AD5934_Sweep(); // Get Reference Resistor 2 from ADC
-
-
-	// Move values in the vectors
-	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
-	{
-		ec_ref_samples_H[i][0] = ec_ref_samples_H[i-1][0]; //real
-		ec_ref_samples_H[i][1] = ec_ref_samples_H[i-1][1]; //imag
-
-		ec_ref_samples_L[i][0] = ec_ref_samples_L[i-1][0]; //real
-		ec_ref_samples_L[i][1] = ec_ref_samples_L[i-1][1]; //imag
-
-	}
-
-	// Read real and imaginary data
-	ec_ref_samples_H[0][0] = (int16_t)(sample_H & 0x0000FFFF); //real
-	ec_ref_samples_H[0][1]  = (int16_t)((sample_H & 0xFFFF0000)>>16); //imag
-	//ec_ref_samples_H[0][1]  = (int16_t)((0xFFFF - (sample_H & 0xFFFF0000)>>16)); //imag
-
-	// Read real and imaginary data
-	ec_ref_samples_L[0][0] = (int16_t)(sample_L & 0x0000FFFF); //real
-	ec_ref_samples_L[0][1]  = (int16_t)((sample_L & 0xFFFF0000)>>16); //imag
-	//ec_ref_samples_L[0][1]  = (int16_t)((0xFFFF - (sample_L & 0xFFFF0000)>>16)); //imag
-
-
-	// Sum values in the vectors
-	for (i = 0, ref_sum_H[0]=0, ref_sum_H[1]=0, ref_sum_L[0]=0, ref_sum_L[1]=0; i < AD5934_EC_AVERAGES; i++)
-	{
-		ref_sum_H[0] += (int32_t)ec_ref_samples_H[i][0]; //real
-		ref_sum_H[1] += (int32_t)ec_ref_samples_H[i][1]; //imag
-
-		ref_sum_L[0] += (int32_t)ec_ref_samples_L[i][0]; //real
-		ref_sum_L[1] += (int32_t)ec_ref_samples_L[i][1]; //imag
-	}
-
-	real_number = ((float)ref_sum_H[0])/((float)AD5934_EC_AVERAGES);
-	imag_number = ((float)ref_sum_H[1])/((float)AD5934_EC_AVERAGES);
-
-	// Calculate gain factor impedance
-	mag_ref_H = sqrtf((real_number * real_number) + (imag_number * imag_number));
-
-	if(mag_ref_H > 0.0f)
-		gain_factor_H = 1.0f / (1000.0f * mag_ref_H);
-	else
-		gain_factor_H = 0.0f;
-
-	real_number = ((float)ref_sum_L[0])/((float)AD5934_EC_AVERAGES);
-	imag_number = ((float)ref_sum_L[1])/((float)AD5934_EC_AVERAGES);
-
-		// Calculate gain factor impedance
-	mag_ref_L = sqrtf((real_number * real_number) + (imag_number * imag_number));
-
-	if(mag_ref_L > 0.0f)
-		gain_factor_L = 1.0f / (100.0f * mag_ref_L);
-	else
-		gain_factor_L = 0.0f;
+	uint8_t i, ec_gain;
+	uint32_t sample_dut;
+	int32_t dut_sum[2];
+	float real_number, imag_number, mag_dut, slope;
 
 
 	/* STEP 2: Set the Amplification related to the maximum set value  */
 
 	if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // PA6 has internal pull-up and the Switch connects to GND
-		channel = AD5934_CH_EC_5MS;		// Switch OFF = 5 mS/cm
+		ec_gain = AD5934_CH_EC_HIGH_GAIN;		// Switch OFF = 5 mS/cm, HIGH GAIN,
 	else
-		channel = AD5934_CH_EC_10MS;	// Switch ON = 10 mS/cm
+		ec_gain = AD5934_CH_EC_MID_GAIN;		// Switch ON = 10 mS/cm, MID GAIN,
 
-	ADG715_Update(channel);
+	ADG715_Update(ec_gain);
 	HAL_Delay(2);
 
 	sample_dut = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
 
-
 	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
 	{
 		ec_dut_samples[i][0] = ec_dut_samples[i-1][0]; //real
@@ -425,7 +360,6 @@ float AD5934_GetImpedance(void)
 	// Read real and imaginary data
 	ec_dut_samples[0][0] = (int16_t)(sample_dut & 0x0000FFFF); //real
 	ec_dut_samples[0][1] = (int16_t)((sample_dut & 0xFFFF0000)>>16); //imag
-	//ec_dut_samples[0][1] = (int16_t)((0xFFFF - (sample_dut & 0xFFFF0000)>>16)); //imag
 
 	for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_EC_AVERAGES; i++)
 	{
@@ -439,20 +373,19 @@ float AD5934_GetImpedance(void)
 	// Calculate unknown magnitude
 	mag_dut = sqrtf((real_number * real_number) + (imag_number * imag_number));
 
+
 	// Calculate gain factor for the unknown magnitude
 
-	if(mag_ref_H != mag_ref_L)
-		slope = ((gain_factor_H - gain_factor_L)/(mag_ref_H - mag_ref_L));
-		//slope = ((gain_factor_H - gain_factor_L)/(log10f(mag_ref_H) - log10f(mag_ref_L)));
+	if(main_state == STATE_SETUP_CALIBRATION)
+		return(mag_dut);
+	else if(flash_data.ec12880_value != flash_data.ec1413_value)
+	{
+		slope = ((AD5934_GAIN_FACTOR_12880US - AD5934_GAIN_FACTOR_1413US)/(flash_data.ec12880_value - flash_data.ec1413_value));
+
+		return(AD5934_GAIN_FACTOR_1413US + (mag_dut - flash_data.ec1413_value) * slope);
+	}
 	else
 		return 0.0f;
-
-	//gain_factor_dut = gain_factor_L + (log10f(mag_dut) - log10f(mag_ref_L)) * slope;
-	gain_factor_dut = gain_factor_L + (mag_dut - mag_ref_L) * slope;
-
-	// Calculate and return admittance in mS
-	return(10.0f * mag_dut * gain_factor_dut);
-
 }
 
 
@@ -576,33 +509,65 @@ void ADG715_Update(uint8_t channel)
 	ADG715_ResetChannels();
 
 	// Set the pair of connections
-	if(channel == AD5934_CH_REF_100R)
+	if(channel == AD5934_CH_REF100R_LOW_GAIN)
 	{
 		ADG715_SetChannels(ADG715_SW1, ADG715_SW4); // Rf = 150R, Ch = Ref_100R
 	}
-	else if(channel == AD5934_CH_REF_1K)
+	else if(channel == AD5934_CH_REF100R_MID_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW4); // Rf = 1k5, Ch = Ref_100R
+	}
+	else if(channel == AD5934_CH_REF100R_HIGH_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW4); // Rf = 6k2, Ch = Ref_100R
+	}
+	else if(channel == AD5934_CH_REF1K_LOW_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW5); // Rf = 150R, Ch = Ref_1k
+	}
+	else if(channel == AD5934_CH_REF1K_MID_GAIN)
 	{
 		ADG715_SetChannels(ADG715_SW2, ADG715_SW5); // Rf = 1k5, Ch = Ref_1k
 	}
-	else if(channel == AD5934_CH_REF_10K)
+	else if(channel == AD5934_CH_REF1K_HIGH_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW5); // Rf = 6k2, Ch = Ref_1k
+	}
+	else if(channel == AD5934_CH_REF10K_LOW_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW6); // Rf = 150R, Ch = Ref_10k
+	}
+	else if(channel == AD5934_CH_REF10K_MID_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW6); // Rf = 1k5, Ch = Ref_10k
+	}
+	else if(channel == AD5934_CH_REF10K_HIGH_GAIN)
 	{
 		ADG715_SetChannels(ADG715_SW3, ADG715_SW6); // Rf = 6k2, Ch = Ref_10k
 	}
-	else if(channel == AD5934_CH_PT100)
+	else if(channel == AD5934_CH_RTD_LOW_GAIN)
 	{
-		ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = PT100
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = RTD
 	}
-	else if(channel == AD5934_CH_PT1000)
+	else if(channel == AD5934_CH_RTD_MID_GAIN)
 	{
-		ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = PT1000
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = RTD
 	}
-	else if(channel == AD5934_CH_EC_10MS)
+	else if(channel == AD5934_CH_RTD_HIGH_GAIN)
 	{
-		ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC 10 mS/cm Max
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW7); // Rf = 6k2, Ch = RTD
 	}
-	else if(channel == AD5934_CH_EC_5MS)
+	else if(channel == AD5934_CH_EC_LOW_GAIN)
 	{
-		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC 5 mS/cm Max
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW8); // Rf = 150R, Ch = EC
+	}
+	else if(channel == AD5934_CH_EC_MID_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC
+	}
+	else if(channel == AD5934_CH_EC_HIGH_GAIN)
+	{
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC
 	}
 
 }
diff --git a/Fertirrega_v6/Core/Src/adc.c b/Fertirrega_v6/Core/Src/adc.c
index f512c86..1c0673f 100644
--- a/Fertirrega_v6/Core/Src/adc.c
+++ b/Fertirrega_v6/Core/Src/adc.c
@@ -26,6 +26,7 @@
 
 ADC_HandleTypeDef hadc1;
 ADC_HandleTypeDef hadc2;
+DMA_HandleTypeDef hdma_adc1;
 
 /* ADC1 init function */
 void MX_ADC1_Init(void)
@@ -44,12 +45,12 @@ void MX_ADC1_Init(void)
   /** Common config
   */
   hadc1.Instance = ADC1;
-  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
   hadc1.Init.ContinuousConvMode = DISABLE;
   hadc1.Init.DiscontinuousConvMode = DISABLE;
-  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO;
   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
-  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.NbrOfConversion = 2;
   if (HAL_ADC_Init(&hadc1) != HAL_OK)
   {
     Error_Handler();
@@ -57,9 +58,18 @@ void MX_ADC1_Init(void)
 
   /** Configure Regular Channel
   */
-  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Channel = ADC_CHANNEL_VREFINT;
   sConfig.Rank = ADC_REGULAR_RANK_1;
-  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
   {
     Error_Handler();
@@ -133,6 +143,23 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance = DMA1_Channel1;
+    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_adc1.Init.Mode = DMA_CIRCULAR;
+    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1);
+
   /* USER CODE BEGIN ADC1_MspInit 1 */
 
   /* USER CODE END ADC1_MspInit 1 */
@@ -147,11 +174,12 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
     /**ADC2 GPIO Configuration
+    PA0-WKUP     ------> ADC2_IN0
     PA1     ------> ADC2_IN1
     */
-    GPIO_InitStruct.Pin = AIN2_Pin;
+    GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-    HAL_GPIO_Init(AIN2_GPIO_Port, &GPIO_InitStruct);
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   /* USER CODE BEGIN ADC2_MspInit 1 */
 
@@ -176,6 +204,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
     */
     HAL_GPIO_DeInit(GPIOA, AIN1_Pin|AIN2_Pin);
 
+    /* ADC1 DMA DeInit */
+    HAL_DMA_DeInit(adcHandle->DMA_Handle);
   /* USER CODE BEGIN ADC1_MspDeInit 1 */
 
   /* USER CODE END ADC1_MspDeInit 1 */
@@ -189,9 +219,10 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
     __HAL_RCC_ADC2_CLK_DISABLE();
 
     /**ADC2 GPIO Configuration
+    PA0-WKUP     ------> ADC2_IN0
     PA1     ------> ADC2_IN1
     */
-    HAL_GPIO_DeInit(AIN2_GPIO_Port, AIN2_Pin);
+    HAL_GPIO_DeInit(GPIOA, AIN1_Pin|AIN2_Pin);
 
   /* USER CODE BEGIN ADC2_MspDeInit 1 */
 
diff --git a/Fertirrega_v6/Core/Src/ads1015_driver.c b/Fertirrega_v6/Core/Src/ads1015_driver.c
index f41518a..3e92a0d 100644
--- a/Fertirrega_v6/Core/Src/ads1015_driver.c
+++ b/Fertirrega_v6/Core/Src/ads1015_driver.c
@@ -8,9 +8,9 @@
  */
 
 #include "ads1015_driver.h"
-#include "main.h" // Assuming HAL is included via main.h
 
-float temp_calib, ph_compensated, v_ph4=0, v_ph7=0;
+ADS1015_I2C i2c;
+float ph_dut_samples[ADS1015_PH_AVERAGES]={0};
 
 // Write the register
 static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
@@ -271,10 +271,22 @@ int16_t ADSgetLastConversionResults(ADS1015_I2C *i2c) {
 	}
 }
 
-float ADSCalculate_ph_Volts(int16_t adc_raw)
+float ADSCalculate_ph_Volts(void)
 {
-    // 1. Converter leitura bruta do ADC para tensão real (Volts)
-    return ((float)adc_raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX;
+	float ph_dut_sum;
+	uint8_t i;
+
+	for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
+		ph_dut_samples[i] = ph_dut_samples[i-1];
+
+	ph_dut_samples[0] = (((float)(2048 - ADSreadADC_Differential_0_1(&i2c)) * ADS1015_ADC_VREF) / ADS1015_ADC_MAX); 	// 1. Converter leitura bruta do ADC para tensão real (Volts)
+
+	for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
+		ph_dut_sum += ph_dut_samples[i];
+
+	ph_dut_sum /= ADS1015_PH_AVERAGES;
+
+    return (ph_dut_sum);
 }
 
 
@@ -295,7 +307,7 @@ float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut)
 
     // 2. Calcular o Slope original (medido na temperatura da calibração)
     // Delta pH é fixo em 3.0 (de pH 7 para pH 4)
-    float delta_v_calib = v_ph7 - v_ph4;
+    float delta_v_calib = flash_data.ph7_value - flash_data.ph4_value;
 
     if (delta_v_calib == 0.0f)
     {
@@ -306,7 +318,7 @@ float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut)
 
     // 3. Calcular o Fator de Correção Térmica (Equação de Nernst)
     float temp_k_now = temp_dut + ADS1015_KELVIN_OFFSET;
-	float temp_k_ref = temp_calib + ADS1015_KELVIN_OFFSET;
+	float temp_k_ref = flash_data.temperature_value + ADS1015_KELVIN_OFFSET;
 
 	// Fator: (T_atual / T_referencia)
 	float thermal_factor = temp_k_now / temp_k_ref;
@@ -316,7 +328,7 @@ float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut)
 	 * O Slope ajustado para a temperatura atual é: slope_at_calib / thermal_factor
 	 * Fórmula: pH = pH_ref + (V_medido - V_ref_7) * Slope_ajustado
 	 */
-	float ph_result = 7.0f + ((v_measured - v_ph7) * (slope_at_calib / thermal_factor));
+	float ph_result = 7.0f + ((v_measured - flash_data.ph7_value) * (slope_at_calib / thermal_factor));
 
 	// 5. Clamping (Garantir limites físicos)
 	if (ph_result < 0.0f) ph_result = 0.0f;
diff --git a/Fertirrega_v6/Core/Src/dma.c b/Fertirrega_v6/Core/Src/dma.c
new file mode 100644
index 0000000..fd7e0ca
--- /dev/null
+++ b/Fertirrega_v6/Core/Src/dma.c
@@ -0,0 +1,55 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dma.c
+  * @brief   This file provides code for the configuration
+  *          of all the requested memory to memory DMA transfers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "dma.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure DMA                                                              */
+/*----------------------------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * Enable DMA controller clock
+  */
+void MX_DMA_Init(void)
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
diff --git a/Fertirrega_v6/Core/Src/flash_manager.c b/Fertirrega_v6/Core/Src/flash_manager.c
index f3e4b7f..ecfadab 100644
--- a/Fertirrega_v6/Core/Src/flash_manager.c
+++ b/Fertirrega_v6/Core/Src/flash_manager.c
@@ -9,6 +9,9 @@
  * @param pPage Ponteiro para a estrutura de 1KB na RAM.
  * @return HAL_OK em caso de sucesso.
  */
+
+FlashPage_t flash_data;
+
 HAL_StatusTypeDef Flash_Save_Page(FlashPage_t *pPage) {
     if (pPage == NULL) return HAL_ERROR;
 
diff --git a/Fertirrega_v6/Core/Src/gpio.c b/Fertirrega_v6/Core/Src/gpio.c
index 353e5f0..77dc378 100644
--- a/Fertirrega_v6/Core/Src/gpio.c
+++ b/Fertirrega_v6/Core/Src/gpio.c
@@ -28,7 +28,6 @@
 
 /* USER CODE END 0 */
 
-
 /*----------------------------------------------------------------------------*/
 /* Configure GPIO                                                             */
 /*----------------------------------------------------------------------------*/
@@ -133,7 +132,7 @@ void MX_GPIO_Init(void)
  */
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
-    if (GPIO_Pin == Calib_PH_Pin)
+    if ((GPIO_Pin == Calib_PH_Pin) && (main_state == STATE_RUNNING_OK))
     {
     	uint32_t current_time = HAL_GetTick();
     	GPIO_PinState pin_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3);
diff --git a/Fertirrega_v6/Core/Src/main.c b/Fertirrega_v6/Core/Src/main.c
index ff48451..f9f884d 100644
--- a/Fertirrega_v6/Core/Src/main.c
+++ b/Fertirrega_v6/Core/Src/main.c
@@ -19,7 +19,9 @@
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 #include "adc.h"
+#include "dma.h"
 #include "i2c.h"
+#include "tim.h"
 #include "usart.h"
 #include "gpio.h"
 
@@ -29,6 +31,8 @@
 #include "digital_outputs_driver.h"
 #include "ad5934_driver.h"
 #include "rs485_driver.h"
+#include "flash_manager.h"
+
 
 #include <string.h>
 /* USER CODE END Includes */
@@ -40,8 +44,10 @@
 
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN PD */
-
-
+#define AVG_SLOPE (4.3F)
+#define V_AT_25C  (1.43F)
+#define V_REF_INT (1.2F)
+#define STM32_TEMPERATURE_AVERAGES 4
 /* USER CODE END PD */
 
 /* Private macro -------------------------------------------------------------*/
@@ -62,20 +68,25 @@ uint8_t imag_text[6];
 uint8_t rs485_text[6];
 
 
-uint8_t newline[]={'\r','\n'};
+uint8_t newline[]={'\n','\0'};
 uint8_t doubleSpace[]={'_','_'};
-uint8_t newline_ph[]={'_','p','H','\r','\n'};
-uint8_t newline_admi[]={'_','m','S','\r','\n'};
-uint8_t newline_real[]={'_','°','C','\r','\n'};
-uint8_t newline_imag[]={'_','O','h','m','\r','\n'};
-uint8_t newline_485[]={'_','a','d','\r','\n'};
+uint8_t newline_ph[]={'_','p','H','\n','\0'};
+uint8_t newline_admi[]={'_','u','S','\n','\0'};
+uint8_t newline_temp[]={' ','°','C','\n','\0'};
+uint8_t newline_real[]={'_','°','C','\n','\0'};
+uint8_t newline_imag[]={'_','O','h','m','\n','\0'};
+uint8_t newline_485[]={'_','a','d','\n','\0'};
 uint8_t minus[]={'-',' '};
 
 
+uint8_t main_state = STATE_RUNNING_OK;
 uint8_t rs485_address=0;
 
-ADS1015_I2C i2c;
 
+uint16_t AD_RES[2];
+uint8_t UpdateEvent = 0;
+float Temperature, Temp_Sum, V_Sense, V_Ref;
+float Temp_Samples[STM32_TEMPERATURE_AVERAGES]={0};
 
 /* USER CODE END PV */
 
@@ -113,11 +124,15 @@ int main(void)
 	   uint32_t previous_millis_red = 0;
 	   uint32_t current_millis;
 
-	float temperature_RTD, admittance_EC;
+	float temperature_RTD, admittance_EC, ph_compensated;
+
+
+
 
 	/*! Temporary variables */
-	char  tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-	long double         tempValue = 0;
+	uint8_t  tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+	uint8_t i;
 
   /* USER CODE END 1 */
 
@@ -139,13 +154,24 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
+  MX_DMA_Init();
   MX_ADC1_Init();
   MX_ADC2_Init();
   MX_I2C1_Init();
   MX_I2C2_Init();
   MX_USART1_UART_Init();
+  MX_TIM3_Init();
   /* USER CODE BEGIN 2 */
 
+  Flash_Load_Page(&flash_data);
+
+  //TempSensor_Init(&hadc1);
+
+
+  HAL_TIM_Base_Start(&htim3);
+  HAL_ADCEx_Calibration_Start(&hadc1);
+  HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2);   // Start ADC Conversion
+
   digital_outputs_init();
 
   // Initialize RS-485 driver
@@ -158,20 +184,59 @@ int main(void)
 	AD5934_Init();
 
 
+
   /* USER CODE END 2 */
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
-   while (1)
-   {
+
+	if(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET)
+	{
+		main_state = STATE_SETUP_CALIBRATION;
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
+
+		for(i=0;i<32;i++)
+		{
+			flash_data.temperature_value = temperature_RTD;
+			flash_data.ph4_value = ADSCalculate_ph_Volts();
+			flash_data.ec1413_value = AD5934_GetImpedance();
+		}
+
+
+		while(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET);
+		HAL_Delay(500);
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
+
+		for(i=0;i<32;i++)
+		{
+			flash_data.ph7_value = ADSCalculate_ph_Volts();
+			flash_data.ec12880_value = AD5934_GetImpedance();
+			Flash_Save_Page(&flash_data);
+		}
+
+		HAL_Delay(500);
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
+
+		main_state = STATE_RUNNING_OK;
+	}
+	while (1)
+	{
     /* USER CODE END WHILE */
 
     /* USER CODE BEGIN 3 */
      current_millis = HAL_GetTick();
 
 
+
+
      // Piscar LED verde em PB5 a cada 0,5 segundos
-     if ((current_millis - previous_millis_green) >= 800)
+     if ((current_millis - previous_millis_green) >= 500)
      {
        previous_millis_green = current_millis;
 
@@ -186,6 +251,10 @@ int main(void)
 
        }*/
 
+       FloatToString(tempString, Temperature);
+       status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
+       status1 = rs485_send_broadcast(newline_temp, strlen((char*)newline_temp));
+
 
   	 temperature_RTD = AD5934_GetTemperature();
   	 FloatToString(tempString, temperature_RTD);
@@ -193,24 +262,8 @@ int main(void)
   	 status1 = rs485_send_broadcast(newline_real, strlen((char*)newline_real));
 
 
-  	if(edge_state == FALLING_EDGE)
-  	     {
-  			HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
-  			HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET);
-  			temp_calib = temperature_RTD;
-  	    	 v_ph4 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c));
-  	    	 edge_state = NO_EDGE;
-  	    	 HAL_Delay(500);
-  	     }else if(edge_state == RISING_EDGE)
-  	     {
-  	    	HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET);
-  	    	HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
-  	    	v_ph7 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c));
-  	    	 edge_state = NO_EDGE;
-  	    	HAL_Delay(500);
-  	     }
 
-  	     ph_compensated = ADSCalculate_ph_Compensated((2048 - ADSreadADC_Differential_0_1(&i2c)),temp_calib);
+  	     ph_compensated = ADSCalculate_ph_Compensated((2048 - ADSreadADC_Differential_0_1(&i2c)),flash_data.temperature_value);
   	     FloatToString(tempString, ph_compensated);
   	     status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
   	     status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph));
@@ -222,6 +275,28 @@ int main(void)
   	   status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi));
 
      }
+     else if(UpdateEvent)
+     {
+
+		 for (i = (STM32_TEMPERATURE_AVERAGES-1); i > 0; i--)
+		 	 Temp_Samples[i] = Temp_Samples[i-1];
+
+
+		 	// Read real and imaginary data
+		 	 if(AD_RES[0]>0.0f)
+		 		 V_Ref = (float)((V_REF_INT * 4095.0)/AD_RES[0]);
+		 	 else
+		 		V_Ref = 0.0f;
+		 	 V_Sense = (float)(AD_RES[1] * V_Ref) / 4095.0;
+		 	Temp_Samples[0] = (((V_AT_25C - V_Sense) * 1000.0) /AVG_SLOPE) + 25.0;
+
+		 	for (i = 0, Temp_Sum=0; i < STM32_TEMPERATURE_AVERAGES; i++)
+		 		Temp_Sum += Temp_Samples[i];
+
+		 	Temperature = Temp_Sum/((float)STM32_TEMPERATURE_AVERAGES);
+
+		 	UpdateEvent = 0;
+     }
 
 
 
@@ -333,11 +408,7 @@ void SystemClock_Config(void)
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     Error_Handler();
@@ -347,10 +418,10 @@ void SystemClock_Config(void)
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
   {
@@ -377,43 +448,68 @@ void SystemClock_Config(void)
  *
  * @return None.
 *******************************************************************************/
-void FloatToString(char * buf, double val)
+void FloatToString(char *buf, double val)
 {
-    long  intPart  = 0;
-    short fracPart = 0;
-    short  charPos  = 0;
-    char  localBuf[12] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-    short  i = sizeof(localBuf) - 1;
+    char temp[20]; // Buffer auxiliar para construção segura
+    int i = 0;
 
-    intPart = (long)val;
-    fracPart = (short)((val - intPart) * 1000 + 0.5);
-    while(i > sizeof(localBuf) - 4)
-    {
-        localBuf[i] = (fracPart % 10) + 0x30;
-        fracPart /= 10;
-        i--;
+    // 1. Tratar sinal negativo
+    if (val < 0) {
+        temp[i++] = '-';
+        val = -val;
     }
-    localBuf[i] = '.';
-    if(intPart == 0)
-    {
-        i --;
-        localBuf[i] = '0';
+
+    // 2. Separar parte inteira e fracionária
+    long intPart = (long)val;
+    // Multiplicamos por 1000 para obter 3 casas decimais fixas
+    int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
+
+    // 3. Converter a parte inteira para o buffer temp
+    // Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
+    char intRev[12];
+    int j = 0;
+
+    if (intPart == 0) {
+        intRev[j++] = '0';
+    } else {
+        while (intPart > 0) {
+            intRev[j++] = (intPart % 10) + '0';
+            intPart /= 10;
+        }
     }
-    while(intPart)
-    {
-        i --;
-        localBuf[i] =(intPart % 10)  + 0x30;
-        intPart /= 10;
+
+    // Inverter a parte inteira de volta para o buffer principal
+    for (int k = j - 1; k >= 0; k--) {
+        temp[i++] = intRev[k];
     }
-    for(charPos = i; charPos < sizeof(localBuf); charPos ++)
-    {
-        *buf = localBuf[charPos];
-        buf ++;
+
+    // 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
+    temp[i++] = '.';
+
+    // Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
+    int fracBuffer[3];
+    fracBuffer[2] = fracPart % 10;          // Unidade
+    fracBuffer[1] = (fracPart / 10) % 10;   // Dezena
+    fracBuffer[0] = (fracPart / 100) % 10;  // Centena
+
+    for (int k = 2; k >= 0; k--) {
+        temp[i++] = fracBuffer[k] + '0';
     }
-	*buf = 0;
+
+    // 5. Finalizar a string com o caractere nulo
+    temp[i] = '\0';
+
+    // 6. Copiar para o buffer de destino final (sem risco de lixo)
+    int destIdx = 0;
+    while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
+        buf[destIdx] = temp[destIdx];
+        destIdx++;
+    }
+    buf[destIdx] = '\0';
 }
 
 
+
 void intToStr(int N, char *str) {
     int i = 0;
 
@@ -452,6 +548,10 @@ void intToStr(int N, char *str) {
 }
 
 
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+     UpdateEvent = 1;
+}
 
 /* USER CODE END 4 */
 
diff --git a/Fertirrega_v6/Core/Src/stm32f1xx_it.c b/Fertirrega_v6/Core/Src/stm32f1xx_it.c
index 820e2b7..81ff9d6 100644
--- a/Fertirrega_v6/Core/Src/stm32f1xx_it.c
+++ b/Fertirrega_v6/Core/Src/stm32f1xx_it.c
@@ -55,6 +55,7 @@
 /* USER CODE END 0 */
 
 /* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_adc1;
 extern UART_HandleTypeDef huart1;
 /* USER CODE BEGIN EV */
 
@@ -212,6 +213,20 @@ void EXTI3_IRQHandler(void)
   /* USER CODE END EXTI3_IRQn 1 */
 }
 
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_adc1);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
 /**
   * @brief This function handles USART1 global interrupt.
   */
diff --git a/Fertirrega_v6/Core/Src/tim.c b/Fertirrega_v6/Core/Src/tim.c
new file mode 100644
index 0000000..0cb96ce
--- /dev/null
+++ b/Fertirrega_v6/Core/Src/tim.c
@@ -0,0 +1,105 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration
+  *          of the TIM instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim3;
+
+/* TIM3 init function */
+void MX_TIM3_Init(void)
+{
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+  htim3.Init.Prescaler = 3;
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim3.Init.Period = 59999;
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* TIM3 clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+  /* USER CODE END TIM3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM3_CLK_DISABLE();
+  /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+  /* USER CODE END TIM3_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
diff --git a/Fertirrega_v6/Core/Startup/startup_stm32f103c8tx.s b/Fertirrega_v6/Core/Startup/startup_stm32f103c8tx.s
index 7614285..d1af5c5 100644
--- a/Fertirrega_v6/Core/Startup/startup_stm32f103c8tx.s
+++ b/Fertirrega_v6/Core/Startup/startup_stm32f103c8tx.s
@@ -61,7 +61,7 @@ defined in linker script */
 Reset_Handler:
 
 /* Call the clock system initialization function.*/
-    bl  SystemInit
+     bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   ldr r0, =_sdata
diff --git a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.cyclo b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.cyclo
index 0c39546..9c96e62 100644
--- a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.cyclo
@@ -1,15 +1,15 @@
-../Core/Src/ad5934_driver.c:38:6:AD5934_SetRegisterValue	2
-../Core/Src/ad5934_driver.c:66:10:AD5934_GetRegisterValue	3
-../Core/Src/ad5934_driver.c:105:10:AD5934_ReadRegister	3
-../Core/Src/ad5934_driver.c:142:6:AD5934_Init	1
-../Core/Src/ad5934_driver.c:170:6:AD5934_RestartSweep	1
-../Core/Src/ad5934_driver.c:197:10:AD5934_Sweep	1
-../Core/Src/ad5934_driver.c:222:7:AD5934_GetTemperature	11
-../Core/Src/ad5934_driver.c:331:7:AD5934_GetImpedance	9
-../Core/Src/ad5934_driver.c:462:6:AD5934_Wait_For_Data_Valid	3
-../Core/Src/ad5934_driver.c:497:7:AD5934_Round_Float_Precision	2
-../Core/Src/ad5934_driver.c:522:7:AD5934_Linear_Correction	1
-../Core/Src/ad5934_driver.c:544:6:ADG715_SetRegisterValue	1
-../Core/Src/ad5934_driver.c:554:6:ADG715_SetChannels	1
-../Core/Src/ad5934_driver.c:559:6:ADG715_ResetChannels	1
-../Core/Src/ad5934_driver.c:571:6:ADG715_Update	8
+../Core/Src/ad5934_driver.c:33:6:AD5934_SetRegisterValue	2
+../Core/Src/ad5934_driver.c:61:10:AD5934_GetRegisterValue	3
+../Core/Src/ad5934_driver.c:100:10:AD5934_ReadRegister	3
+../Core/Src/ad5934_driver.c:137:6:AD5934_Init	1
+../Core/Src/ad5934_driver.c:165:6:AD5934_RestartSweep	1
+../Core/Src/ad5934_driver.c:192:10:AD5934_Sweep	1
+../Core/Src/ad5934_driver.c:217:7:AD5934_GetTemperature	11
+../Core/Src/ad5934_driver.c:334:7:AD5934_GetImpedance	6
+../Core/Src/ad5934_driver.c:395:6:AD5934_Wait_For_Data_Valid	3
+../Core/Src/ad5934_driver.c:430:7:AD5934_Round_Float_Precision	2
+../Core/Src/ad5934_driver.c:455:7:AD5934_Linear_Correction	1
+../Core/Src/ad5934_driver.c:477:6:ADG715_SetRegisterValue	1
+../Core/Src/ad5934_driver.c:487:6:ADG715_SetChannels	1
+../Core/Src/ad5934_driver.c:492:6:ADG715_ResetChannels	1
+../Core/Src/ad5934_driver.c:504:6:ADG715_Update	16
diff --git a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.d b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.d
index 252f8b2..ead93b8 100644
--- a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.d
+++ b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.d
@@ -25,7 +25,10 @@ Core/Src/ad5934_driver.o: ../Core/Src/ad5934_driver.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
- ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h \
+ ../Core/Inc/flash_manager.h ../Core/Inc/main.h
 ../Core/Inc/ad5934_driver.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -52,4 +55,8 @@ Core/Src/ad5934_driver.o: ../Core/Src/ad5934_driver.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
+../Core/Inc/flash_manager.h:
+../Core/Inc/main.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.o b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.o
index b67e5c8..2270f05 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.o and b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.su b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.su
index 2e42a5c..d82fc0b 100644
--- a/Fertirrega_v6/Debug/Core/Src/ad5934_driver.su
+++ b/Fertirrega_v6/Debug/Core/Src/ad5934_driver.su
@@ -1,15 +1,15 @@
-../Core/Src/ad5934_driver.c:38:6:AD5934_SetRegisterValue	32	static
-../Core/Src/ad5934_driver.c:66:10:AD5934_GetRegisterValue	40	static
-../Core/Src/ad5934_driver.c:105:10:AD5934_ReadRegister	48	static
-../Core/Src/ad5934_driver.c:142:6:AD5934_Init	8	static
-../Core/Src/ad5934_driver.c:170:6:AD5934_RestartSweep	8	static
-../Core/Src/ad5934_driver.c:197:10:AD5934_Sweep	16	static
-../Core/Src/ad5934_driver.c:222:7:AD5934_GetTemperature	88	static
-../Core/Src/ad5934_driver.c:331:7:AD5934_GetImpedance	96	static
-../Core/Src/ad5934_driver.c:462:6:AD5934_Wait_For_Data_Valid	24	static
-../Core/Src/ad5934_driver.c:497:7:AD5934_Round_Float_Precision	24	static
-../Core/Src/ad5934_driver.c:522:7:AD5934_Linear_Correction	24	static
-../Core/Src/ad5934_driver.c:544:6:ADG715_SetRegisterValue	32	static
-../Core/Src/ad5934_driver.c:554:6:ADG715_SetChannels	16	static
-../Core/Src/ad5934_driver.c:559:6:ADG715_ResetChannels	8	static
-../Core/Src/ad5934_driver.c:571:6:ADG715_Update	16	static
+../Core/Src/ad5934_driver.c:33:6:AD5934_SetRegisterValue	32	static
+../Core/Src/ad5934_driver.c:61:10:AD5934_GetRegisterValue	40	static
+../Core/Src/ad5934_driver.c:100:10:AD5934_ReadRegister	48	static
+../Core/Src/ad5934_driver.c:137:6:AD5934_Init	8	static
+../Core/Src/ad5934_driver.c:165:6:AD5934_RestartSweep	8	static
+../Core/Src/ad5934_driver.c:192:10:AD5934_Sweep	16	static
+../Core/Src/ad5934_driver.c:217:7:AD5934_GetTemperature	88	static
+../Core/Src/ad5934_driver.c:334:7:AD5934_GetImpedance	48	static
+../Core/Src/ad5934_driver.c:395:6:AD5934_Wait_For_Data_Valid	24	static
+../Core/Src/ad5934_driver.c:430:7:AD5934_Round_Float_Precision	24	static
+../Core/Src/ad5934_driver.c:455:7:AD5934_Linear_Correction	24	static
+../Core/Src/ad5934_driver.c:477:6:ADG715_SetRegisterValue	32	static
+../Core/Src/ad5934_driver.c:487:6:ADG715_SetChannels	16	static
+../Core/Src/ad5934_driver.c:492:6:ADG715_ResetChannels	8	static
+../Core/Src/ad5934_driver.c:504:6:ADG715_Update	16	static
diff --git a/Fertirrega_v6/Debug/Core/Src/adc.cyclo b/Fertirrega_v6/Debug/Core/Src/adc.cyclo
index ef14848..dc33b58 100644
--- a/Fertirrega_v6/Debug/Core/Src/adc.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/adc.cyclo
@@ -1,4 +1,4 @@
-../Core/Src/adc.c:31:6:MX_ADC1_Init	3
-../Core/Src/adc.c:73:6:MX_ADC2_Init	3
-../Core/Src/adc.c:115:6:HAL_ADC_MspInit	3
-../Core/Src/adc.c:162:6:HAL_ADC_MspDeInit	3
+../Core/Src/adc.c:32:6:MX_ADC1_Init	4
+../Core/Src/adc.c:83:6:MX_ADC2_Init	3
+../Core/Src/adc.c:125:6:HAL_ADC_MspInit	4
+../Core/Src/adc.c:190:6:HAL_ADC_MspDeInit	3
diff --git a/Fertirrega_v6/Debug/Core/Src/adc.d b/Fertirrega_v6/Debug/Core/Src/adc.d
index b806d53..9c14eca 100644
--- a/Fertirrega_v6/Debug/Core/Src/adc.d
+++ b/Fertirrega_v6/Debug/Core/Src/adc.d
@@ -24,6 +24,8 @@ Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/adc.h:
 ../Core/Inc/main.h:
@@ -52,4 +54,6 @@ Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/adc.o b/Fertirrega_v6/Debug/Core/Src/adc.o
index d86b188..a90ac5a 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/adc.o and b/Fertirrega_v6/Debug/Core/Src/adc.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/adc.su b/Fertirrega_v6/Debug/Core/Src/adc.su
index b74348e..7af9722 100644
--- a/Fertirrega_v6/Debug/Core/Src/adc.su
+++ b/Fertirrega_v6/Debug/Core/Src/adc.su
@@ -1,4 +1,4 @@
-../Core/Src/adc.c:31:6:MX_ADC1_Init	24	static
-../Core/Src/adc.c:73:6:MX_ADC2_Init	24	static
-../Core/Src/adc.c:115:6:HAL_ADC_MspInit	48	static
-../Core/Src/adc.c:162:6:HAL_ADC_MspDeInit	16	static
+../Core/Src/adc.c:32:6:MX_ADC1_Init	24	static
+../Core/Src/adc.c:83:6:MX_ADC2_Init	24	static
+../Core/Src/adc.c:125:6:HAL_ADC_MspInit	48	static
+../Core/Src/adc.c:190:6:HAL_ADC_MspDeInit	16	static
diff --git a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.cyclo b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.cyclo
index 966af14..d3dd754 100644
--- a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.cyclo
@@ -9,5 +9,5 @@
 ../Core/Src/ads1015_driver.c:167:9:ADSreadADC_Differential_2_3	3
 ../Core/Src/ads1015_driver.c:213:6:ADSstartComparator_SingleEnded	5
 ../Core/Src/ads1015_driver.c:255:9:ADSgetLastConversionResults	3
-../Core/Src/ads1015_driver.c:274:7:ADSCalculate_ph_Volts	1
-../Core/Src/ads1015_driver.c:289:7:ADSCalculate_ph_Compensated	4
+../Core/Src/ads1015_driver.c:274:7:ADSCalculate_ph_Volts	3
+../Core/Src/ads1015_driver.c:301:7:ADSCalculate_ph_Compensated	4
diff --git a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.d b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.d
index fb679e7..a1eda2d 100644
--- a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.d
+++ b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.d
@@ -1,5 +1,5 @@
 Core/Src/ads1015_driver.o: ../Core/Src/ads1015_driver.c \
- ../Core/Inc/ads1015_driver.h \
+ ../Core/Inc/ads1015_driver.h ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
  ../Core/Inc/stm32f1xx_hal_conf.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
@@ -25,9 +25,12 @@ Core/Src/ads1015_driver.o: ../Core/Src/ads1015_driver.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h \
- ../Core/Inc/main.h
+ ../Core/Inc/flash_manager.h
 ../Core/Inc/ads1015_driver.h:
+../Core/Inc/main.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
@@ -53,5 +56,7 @@ Core/Src/ads1015_driver.o: ../Core/Src/ads1015_driver.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
-../Core/Inc/main.h:
+../Core/Inc/flash_manager.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.o b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.o
index acf17b2..72d16ea 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.o and b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.su b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.su
index 1253a8e..6d56dc7 100644
--- a/Fertirrega_v6/Debug/Core/Src/ads1015_driver.su
+++ b/Fertirrega_v6/Debug/Core/Src/ads1015_driver.su
@@ -10,4 +10,4 @@
 ../Core/Src/ads1015_driver.c:213:6:ADSstartComparator_SingleEnded	24	static
 ../Core/Src/ads1015_driver.c:255:9:ADSgetLastConversionResults	24	static
 ../Core/Src/ads1015_driver.c:274:7:ADSCalculate_ph_Volts	16	static
-../Core/Src/ads1015_driver.c:289:7:ADSCalculate_ph_Compensated	56	static
+../Core/Src/ads1015_driver.c:301:7:ADSCalculate_ph_Compensated	56	static
diff --git a/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.d b/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.d
index 509fe81..cd3a92c 100644
--- a/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.d
+++ b/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.d
@@ -25,6 +25,8 @@ Core/Src/analog_loop_driver.o: ../Core/Src/analog_loop_driver.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/analog_loop_driver.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
@@ -52,4 +54,6 @@ Core/Src/analog_loop_driver.o: ../Core/Src/analog_loop_driver.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.o b/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.o
index aac2451..3b92821 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.o and b/Fertirrega_v6/Debug/Core/Src/analog_loop_driver.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.d b/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.d
index 5cf2c04..0a14171 100644
--- a/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.d
+++ b/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.d
@@ -25,6 +25,8 @@ Core/Src/digital_outputs_driver.o: ../Core/Src/digital_outputs_driver.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/digital_outputs_driver.h:
 ../Core/Inc/main.h:
@@ -53,4 +55,6 @@ Core/Src/digital_outputs_driver.o: ../Core/Src/digital_outputs_driver.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.o b/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.o
index bfde12e..afec9aa 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.o and b/Fertirrega_v6/Debug/Core/Src/digital_outputs_driver.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/dma.cyclo b/Fertirrega_v6/Debug/Core/Src/dma.cyclo
new file mode 100644
index 0000000..a9d9f42
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/dma.cyclo
@@ -0,0 +1 @@
+../Core/Src/dma.c:39:6:MX_DMA_Init	1
diff --git a/Fertirrega_v6/Debug/Core/Src/dma.d b/Fertirrega_v6/Debug/Core/Src/dma.d
new file mode 100644
index 0000000..8c6193e
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/dma.d
@@ -0,0 +1,59 @@
+Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
+ ../Core/Inc/stm32f1xx_hal_conf.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
+../Core/Inc/stm32f1xx_hal_conf.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/dma.o b/Fertirrega_v6/Debug/Core/Src/dma.o
new file mode 100644
index 0000000..13a0977
Binary files /dev/null and b/Fertirrega_v6/Debug/Core/Src/dma.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/dma.su b/Fertirrega_v6/Debug/Core/Src/dma.su
new file mode 100644
index 0000000..802020b
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/dma.su
@@ -0,0 +1 @@
+../Core/Src/dma.c:39:6:MX_DMA_Init	16	static
diff --git a/Fertirrega_v6/Debug/Core/Src/flash_manager.cyclo b/Fertirrega_v6/Debug/Core/Src/flash_manager.cyclo
index cfdd72f..1ab4934 100644
--- a/Fertirrega_v6/Debug/Core/Src/flash_manager.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/flash_manager.cyclo
@@ -1,2 +1,2 @@
-../Core/Src/flash_manager.c:12:19:Flash_Save_Page	5
-../Core/Src/flash_manager.c:57:19:Flash_Load_Page	3
+../Core/Src/flash_manager.c:15:19:Flash_Save_Page	5
+../Core/Src/flash_manager.c:60:19:Flash_Load_Page	3
diff --git a/Fertirrega_v6/Debug/Core/Src/flash_manager.d b/Fertirrega_v6/Debug/Core/Src/flash_manager.d
index 46cfc5a..4954169 100644
--- a/Fertirrega_v6/Debug/Core/Src/flash_manager.d
+++ b/Fertirrega_v6/Debug/Core/Src/flash_manager.d
@@ -25,6 +25,8 @@ Core/Src/flash_manager.o: ../Core/Src/flash_manager.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/flash_manager.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
@@ -52,4 +54,6 @@ Core/Src/flash_manager.o: ../Core/Src/flash_manager.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/flash_manager.o b/Fertirrega_v6/Debug/Core/Src/flash_manager.o
index 8598bc7..8a13eb6 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/flash_manager.o and b/Fertirrega_v6/Debug/Core/Src/flash_manager.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/flash_manager.su b/Fertirrega_v6/Debug/Core/Src/flash_manager.su
index d99ae06..5f040e6 100644
--- a/Fertirrega_v6/Debug/Core/Src/flash_manager.su
+++ b/Fertirrega_v6/Debug/Core/Src/flash_manager.su
@@ -1,2 +1,2 @@
-../Core/Src/flash_manager.c:12:19:Flash_Save_Page	64	static
-../Core/Src/flash_manager.c:57:19:Flash_Load_Page	16	static
+../Core/Src/flash_manager.c:15:19:Flash_Save_Page	64	static
+../Core/Src/flash_manager.c:60:19:Flash_Load_Page	16	static
diff --git a/Fertirrega_v6/Debug/Core/Src/gpio.cyclo b/Fertirrega_v6/Debug/Core/Src/gpio.cyclo
index bf047c5..b137c57 100644
--- a/Fertirrega_v6/Debug/Core/Src/gpio.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/gpio.cyclo
@@ -1,2 +1,2 @@
-../Core/Src/gpio.c:53:6:MX_GPIO_Init	1
-../Core/Src/gpio.c:134:6:HAL_GPIO_EXTI_Callback	7
+../Core/Src/gpio.c:52:6:MX_GPIO_Init	1
+../Core/Src/gpio.c:133:6:HAL_GPIO_EXTI_Callback	8
diff --git a/Fertirrega_v6/Debug/Core/Src/gpio.d b/Fertirrega_v6/Debug/Core/Src/gpio.d
index 20d43e5..9fa10f8 100644
--- a/Fertirrega_v6/Debug/Core/Src/gpio.d
+++ b/Fertirrega_v6/Debug/Core/Src/gpio.d
@@ -24,6 +24,8 @@ Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/gpio.h:
 ../Core/Inc/main.h:
@@ -52,4 +54,6 @@ Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/gpio.o b/Fertirrega_v6/Debug/Core/Src/gpio.o
index 65aa435..933dd52 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/gpio.o and b/Fertirrega_v6/Debug/Core/Src/gpio.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/gpio.su b/Fertirrega_v6/Debug/Core/Src/gpio.su
index 98828a5..b33e591 100644
--- a/Fertirrega_v6/Debug/Core/Src/gpio.su
+++ b/Fertirrega_v6/Debug/Core/Src/gpio.su
@@ -1,2 +1,2 @@
-../Core/Src/gpio.c:53:6:MX_GPIO_Init	40	static
-../Core/Src/gpio.c:134:6:HAL_GPIO_EXTI_Callback	24	static
+../Core/Src/gpio.c:52:6:MX_GPIO_Init	40	static
+../Core/Src/gpio.c:133:6:HAL_GPIO_EXTI_Callback	24	static
diff --git a/Fertirrega_v6/Debug/Core/Src/i2c.d b/Fertirrega_v6/Debug/Core/Src/i2c.d
index 949fc8b..7d7127c 100644
--- a/Fertirrega_v6/Debug/Core/Src/i2c.d
+++ b/Fertirrega_v6/Debug/Core/Src/i2c.d
@@ -24,6 +24,8 @@ Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/i2c.h:
 ../Core/Inc/main.h:
@@ -52,4 +54,6 @@ Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h ../Core/Inc/main.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/i2c.o b/Fertirrega_v6/Debug/Core/Src/i2c.o
index 62b22ce..7759925 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/i2c.o and b/Fertirrega_v6/Debug/Core/Src/i2c.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/main.cyclo b/Fertirrega_v6/Debug/Core/Src/main.cyclo
index adaca9c..214fbb0 100644
--- a/Fertirrega_v6/Debug/Core/Src/main.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/main.cyclo
@@ -1,5 +1,6 @@
-../Core/Src/main.c:100:5:main	4
-../Core/Src/main.c:325:6:SystemClock_Config	4
-../Core/Src/main.c:380:6:FloatToString	5
-../Core/Src/main.c:417:6:intToStr	5
-../Core/Src/main.c:462:6:Error_Handler	1
+../Core/Src/main.c:111:5:main	10
+../Core/Src/main.c:400:6:SystemClock_Config	4
+../Core/Src/main.c:455:6:FloatToString	8
+../Core/Src/main.c:517:6:intToStr	5
+../Core/Src/main.c:555:6:HAL_ADC_ConvCpltCallback	1
+../Core/Src/main.c:566:6:Error_Handler	1
diff --git a/Fertirrega_v6/Debug/Core/Src/main.d b/Fertirrega_v6/Debug/Core/Src/main.d
index be961b0..c6b3df6 100644
--- a/Fertirrega_v6/Debug/Core/Src/main.d
+++ b/Fertirrega_v6/Debug/Core/Src/main.d
@@ -24,12 +24,16 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h \
- ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/i2c.h \
- ../Core/Inc/usart.h ../Core/Inc/gpio.h ../Core/Inc/ads1015_driver.h \
+ ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/dma.h ../Core/Inc/i2c.h \
+ ../Core/Inc/tim.h ../Core/Inc/usart.h ../Core/Inc/gpio.h \
+ ../Core/Inc/ads1015_driver.h ../Core/Inc/flash_manager.h \
  ../Core/Inc/digital_outputs_driver.h ../Core/Inc/ad5934_driver.h \
  ../Core/Inc/rs485_driver.h \
- ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h \
+ ../Core/Inc/flash_manager.h
 ../Core/Inc/main.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -56,14 +60,20 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
 ../Core/Inc/adc.h:
 ../Core/Inc/main.h:
+../Core/Inc/dma.h:
 ../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
 ../Core/Inc/usart.h:
 ../Core/Inc/gpio.h:
 ../Core/Inc/ads1015_driver.h:
+../Core/Inc/flash_manager.h:
 ../Core/Inc/digital_outputs_driver.h:
 ../Core/Inc/ad5934_driver.h:
 ../Core/Inc/rs485_driver.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h:
+../Core/Inc/flash_manager.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/main.o b/Fertirrega_v6/Debug/Core/Src/main.o
index a5bb39e..3be848f 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/main.o and b/Fertirrega_v6/Debug/Core/Src/main.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/main.su b/Fertirrega_v6/Debug/Core/Src/main.su
index 38bc0f8..b74fde1 100644
--- a/Fertirrega_v6/Debug/Core/Src/main.su
+++ b/Fertirrega_v6/Debug/Core/Src/main.su
@@ -1,5 +1,6 @@
-../Core/Src/main.c:100:5:main	64	static
-../Core/Src/main.c:325:6:SystemClock_Config	88	static
-../Core/Src/main.c:380:6:FloatToString	48	static
-../Core/Src/main.c:417:6:intToStr	40	static
-../Core/Src/main.c:462:6:Error_Handler	4	static,ignoring_inline_asm
+../Core/Src/main.c:111:5:main	56	static
+../Core/Src/main.c:400:6:SystemClock_Config	88	static
+../Core/Src/main.c:455:6:FloatToString	104	static
+../Core/Src/main.c:517:6:intToStr	40	static
+../Core/Src/main.c:555:6:HAL_ADC_ConvCpltCallback	16	static
+../Core/Src/main.c:566:6:Error_Handler	4	static,ignoring_inline_asm
diff --git a/Fertirrega_v6/Debug/Core/Src/rs485_driver.d b/Fertirrega_v6/Debug/Core/Src/rs485_driver.d
index ade9ed2..2293930 100644
--- a/Fertirrega_v6/Debug/Core/Src/rs485_driver.d
+++ b/Fertirrega_v6/Debug/Core/Src/rs485_driver.d
@@ -25,6 +25,8 @@ Core/Src/rs485_driver.o: ../Core/Src/rs485_driver.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
 ../Core/Inc/rs485_driver.h:
@@ -53,5 +55,7 @@ Core/Src/rs485_driver.o: ../Core/Src/rs485_driver.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/rs485_driver.o b/Fertirrega_v6/Debug/Core/Src/rs485_driver.o
index 730f958..709bfd2 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/rs485_driver.o and b/Fertirrega_v6/Debug/Core/Src/rs485_driver.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.d b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.d
index c188687..1880f45 100644
--- a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.d
+++ b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.d
@@ -24,6 +24,8 @@ Core/Src/stm32f1xx_hal_msp.o: ../Core/Src/stm32f1xx_hal_msp.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/main.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
@@ -51,4 +53,6 @@ Core/Src/stm32f1xx_hal_msp.o: ../Core/Src/stm32f1xx_hal_msp.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.o b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.o
index 21d988f..bb4cf1b 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.o and b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_hal_msp.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.cyclo b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.cyclo
index 0e4b92e..fc1b485 100644
--- a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.cyclo
+++ b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.cyclo
@@ -1,11 +1,12 @@
-../Core/Src/stm32f1xx_it.c:69:6:NMI_Handler	1
-../Core/Src/stm32f1xx_it.c:84:6:HardFault_Handler	1
-../Core/Src/stm32f1xx_it.c:99:6:MemManage_Handler	1
-../Core/Src/stm32f1xx_it.c:114:6:BusFault_Handler	1
-../Core/Src/stm32f1xx_it.c:129:6:UsageFault_Handler	1
-../Core/Src/stm32f1xx_it.c:144:6:SVC_Handler	1
-../Core/Src/stm32f1xx_it.c:157:6:DebugMon_Handler	1
-../Core/Src/stm32f1xx_it.c:170:6:PendSV_Handler	1
-../Core/Src/stm32f1xx_it.c:183:6:SysTick_Handler	1
-../Core/Src/stm32f1xx_it.c:204:6:EXTI3_IRQHandler	1
-../Core/Src/stm32f1xx_it.c:218:6:USART1_IRQHandler	1
+../Core/Src/stm32f1xx_it.c:70:6:NMI_Handler	1
+../Core/Src/stm32f1xx_it.c:85:6:HardFault_Handler	1
+../Core/Src/stm32f1xx_it.c:100:6:MemManage_Handler	1
+../Core/Src/stm32f1xx_it.c:115:6:BusFault_Handler	1
+../Core/Src/stm32f1xx_it.c:130:6:UsageFault_Handler	1
+../Core/Src/stm32f1xx_it.c:145:6:SVC_Handler	1
+../Core/Src/stm32f1xx_it.c:158:6:DebugMon_Handler	1
+../Core/Src/stm32f1xx_it.c:171:6:PendSV_Handler	1
+../Core/Src/stm32f1xx_it.c:184:6:SysTick_Handler	1
+../Core/Src/stm32f1xx_it.c:205:6:EXTI3_IRQHandler	1
+../Core/Src/stm32f1xx_it.c:219:6:DMA1_Channel1_IRQHandler	1
+../Core/Src/stm32f1xx_it.c:233:6:USART1_IRQHandler	1
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.d b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.d
index e7d4e3b..025ab30 100644
--- a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.d
+++ b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.d
@@ -24,6 +24,8 @@ Core/Src/stm32f1xx_it.o: ../Core/Src/stm32f1xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h \
  ../Core/Inc/stm32f1xx_it.h
 ../Core/Inc/main.h:
@@ -52,5 +54,7 @@ Core/Src/stm32f1xx_it.o: ../Core/Src/stm32f1xx_it.c ../Core/Inc/main.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
 ../Core/Inc/stm32f1xx_it.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.o b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.o
index a046586..f1a70c5 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.o and b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.su b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.su
index 1472945..5b7b256 100644
--- a/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.su
+++ b/Fertirrega_v6/Debug/Core/Src/stm32f1xx_it.su
@@ -1,11 +1,12 @@
-../Core/Src/stm32f1xx_it.c:69:6:NMI_Handler	4	static
-../Core/Src/stm32f1xx_it.c:84:6:HardFault_Handler	4	static
-../Core/Src/stm32f1xx_it.c:99:6:MemManage_Handler	4	static
-../Core/Src/stm32f1xx_it.c:114:6:BusFault_Handler	4	static
-../Core/Src/stm32f1xx_it.c:129:6:UsageFault_Handler	4	static
-../Core/Src/stm32f1xx_it.c:144:6:SVC_Handler	4	static
-../Core/Src/stm32f1xx_it.c:157:6:DebugMon_Handler	4	static
-../Core/Src/stm32f1xx_it.c:170:6:PendSV_Handler	4	static
-../Core/Src/stm32f1xx_it.c:183:6:SysTick_Handler	8	static
-../Core/Src/stm32f1xx_it.c:204:6:EXTI3_IRQHandler	8	static
-../Core/Src/stm32f1xx_it.c:218:6:USART1_IRQHandler	8	static
+../Core/Src/stm32f1xx_it.c:70:6:NMI_Handler	4	static
+../Core/Src/stm32f1xx_it.c:85:6:HardFault_Handler	4	static
+../Core/Src/stm32f1xx_it.c:100:6:MemManage_Handler	4	static
+../Core/Src/stm32f1xx_it.c:115:6:BusFault_Handler	4	static
+../Core/Src/stm32f1xx_it.c:130:6:UsageFault_Handler	4	static
+../Core/Src/stm32f1xx_it.c:145:6:SVC_Handler	4	static
+../Core/Src/stm32f1xx_it.c:158:6:DebugMon_Handler	4	static
+../Core/Src/stm32f1xx_it.c:171:6:PendSV_Handler	4	static
+../Core/Src/stm32f1xx_it.c:184:6:SysTick_Handler	8	static
+../Core/Src/stm32f1xx_it.c:205:6:EXTI3_IRQHandler	8	static
+../Core/Src/stm32f1xx_it.c:219:6:DMA1_Channel1_IRQHandler	8	static
+../Core/Src/stm32f1xx_it.c:233:6:USART1_IRQHandler	8	static
diff --git a/Fertirrega_v6/Debug/Core/Src/subdir.mk b/Fertirrega_v6/Debug/Core/Src/subdir.mk
index 0ebb4a7..107e122 100644
--- a/Fertirrega_v6/Debug/Core/Src/subdir.mk
+++ b/Fertirrega_v6/Debug/Core/Src/subdir.mk
@@ -10,6 +10,7 @@ C_SRCS += \
 ../Core/Src/ads1015_driver.c \
 ../Core/Src/analog_loop_driver.c \
 ../Core/Src/digital_outputs_driver.c \
+../Core/Src/dma.c \
 ../Core/Src/flash_manager.c \
 ../Core/Src/gpio.c \
 ../Core/Src/i2c.c \
@@ -20,6 +21,7 @@ C_SRCS += \
 ../Core/Src/syscalls.c \
 ../Core/Src/sysmem.c \
 ../Core/Src/system_stm32f1xx.c \
+../Core/Src/tim.c \
 ../Core/Src/usart.c 
 
 OBJS += \
@@ -28,6 +30,7 @@ OBJS += \
 ./Core/Src/ads1015_driver.o \
 ./Core/Src/analog_loop_driver.o \
 ./Core/Src/digital_outputs_driver.o \
+./Core/Src/dma.o \
 ./Core/Src/flash_manager.o \
 ./Core/Src/gpio.o \
 ./Core/Src/i2c.o \
@@ -38,6 +41,7 @@ OBJS += \
 ./Core/Src/syscalls.o \
 ./Core/Src/sysmem.o \
 ./Core/Src/system_stm32f1xx.o \
+./Core/Src/tim.o \
 ./Core/Src/usart.o 
 
 C_DEPS += \
@@ -46,6 +50,7 @@ C_DEPS += \
 ./Core/Src/ads1015_driver.d \
 ./Core/Src/analog_loop_driver.d \
 ./Core/Src/digital_outputs_driver.d \
+./Core/Src/dma.d \
 ./Core/Src/flash_manager.d \
 ./Core/Src/gpio.d \
 ./Core/Src/i2c.d \
@@ -56,6 +61,7 @@ C_DEPS += \
 ./Core/Src/syscalls.d \
 ./Core/Src/sysmem.d \
 ./Core/Src/system_stm32f1xx.d \
+./Core/Src/tim.d \
 ./Core/Src/usart.d 
 
 
@@ -66,7 +72,7 @@ Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
 clean: clean-Core-2f-Src
 
 clean-Core-2f-Src:
-	-$(RM) ./Core/Src/ad5934_driver.cyclo ./Core/Src/ad5934_driver.d ./Core/Src/ad5934_driver.o ./Core/Src/ad5934_driver.su ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/ads1015_driver.cyclo ./Core/Src/ads1015_driver.d ./Core/Src/ads1015_driver.o ./Core/Src/ads1015_driver.su ./Core/Src/analog_loop_driver.cyclo ./Core/Src/analog_loop_driver.d ./Core/Src/analog_loop_driver.o ./Core/Src/analog_loop_driver.su ./Core/Src/digital_outputs_driver.cyclo ./Core/Src/digital_outputs_driver.d ./Core/Src/digital_outputs_driver.o ./Core/Src/digital_outputs_driver.su ./Core/Src/flash_manager.cyclo ./Core/Src/flash_manager.d ./Core/Src/flash_manager.o ./Core/Src/flash_manager.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/i2c.cyclo ./Core/Src/i2c.d ./Core/Src/i2c.o ./Core/Src/i2c.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/rs485_driver.cyclo ./Core/Src/rs485_driver.d ./Core/Src/rs485_driver.o ./Core/Src/rs485_driver.su ./Core/Src/stm32f1xx_hal_msp.cyclo ./Core/Src/stm32f1xx_hal_msp.d ./Core/Src/stm32f1xx_hal_msp.o ./Core/Src/stm32f1xx_hal_msp.su ./Core/Src/stm32f1xx_it.cyclo ./Core/Src/stm32f1xx_it.d ./Core/Src/stm32f1xx_it.o ./Core/Src/stm32f1xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f1xx.cyclo ./Core/Src/system_stm32f1xx.d ./Core/Src/system_stm32f1xx.o ./Core/Src/system_stm32f1xx.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su
+	-$(RM) ./Core/Src/ad5934_driver.cyclo ./Core/Src/ad5934_driver.d ./Core/Src/ad5934_driver.o ./Core/Src/ad5934_driver.su ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/ads1015_driver.cyclo ./Core/Src/ads1015_driver.d ./Core/Src/ads1015_driver.o ./Core/Src/ads1015_driver.su ./Core/Src/analog_loop_driver.cyclo ./Core/Src/analog_loop_driver.d ./Core/Src/analog_loop_driver.o ./Core/Src/analog_loop_driver.su ./Core/Src/digital_outputs_driver.cyclo ./Core/Src/digital_outputs_driver.d ./Core/Src/digital_outputs_driver.o ./Core/Src/digital_outputs_driver.su ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/flash_manager.cyclo ./Core/Src/flash_manager.d ./Core/Src/flash_manager.o ./Core/Src/flash_manager.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/i2c.cyclo ./Core/Src/i2c.d ./Core/Src/i2c.o ./Core/Src/i2c.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/rs485_driver.cyclo ./Core/Src/rs485_driver.d ./Core/Src/rs485_driver.o ./Core/Src/rs485_driver.su ./Core/Src/stm32f1xx_hal_msp.cyclo ./Core/Src/stm32f1xx_hal_msp.d ./Core/Src/stm32f1xx_hal_msp.o ./Core/Src/stm32f1xx_hal_msp.su ./Core/Src/stm32f1xx_it.cyclo ./Core/Src/stm32f1xx_it.d ./Core/Src/stm32f1xx_it.o ./Core/Src/stm32f1xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f1xx.cyclo ./Core/Src/system_stm32f1xx.d ./Core/Src/system_stm32f1xx.o ./Core/Src/system_stm32f1xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su
 
 .PHONY: clean-Core-2f-Src
 
diff --git a/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.d b/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.d
index 7122ee9..55fea71 100644
--- a/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.d
+++ b/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.d
@@ -24,6 +24,8 @@ Core/Src/system_stm32f1xx.o: ../Core/Src/system_stm32f1xx.c \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
 ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
@@ -50,4 +52,6 @@ Core/Src/system_stm32f1xx.o: ../Core/Src/system_stm32f1xx.c \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.o b/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.o
index 7b57512..bd6a4f4 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.o and b/Fertirrega_v6/Debug/Core/Src/system_stm32f1xx.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/tim.cyclo b/Fertirrega_v6/Debug/Core/Src/tim.cyclo
new file mode 100644
index 0000000..f4822c4
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/tim.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/tim.c:30:6:MX_TIM3_Init	4
+../Core/Src/tim.c:70:6:HAL_TIM_Base_MspInit	2
+../Core/Src/tim.c:86:6:HAL_TIM_Base_MspDeInit	2
diff --git a/Fertirrega_v6/Debug/Core/Src/tim.d b/Fertirrega_v6/Debug/Core/Src/tim.d
new file mode 100644
index 0000000..122baad
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/tim.d
@@ -0,0 +1,59 @@
+Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
+ ../Core/Inc/stm32f1xx_hal_conf.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
+../Core/Inc/tim.h:
+../Core/Inc/main.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
+../Core/Inc/stm32f1xx_hal_conf.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/tim.o b/Fertirrega_v6/Debug/Core/Src/tim.o
new file mode 100644
index 0000000..a68e764
Binary files /dev/null and b/Fertirrega_v6/Debug/Core/Src/tim.o differ
diff --git a/Fertirrega_v6/Debug/Core/Src/tim.su b/Fertirrega_v6/Debug/Core/Src/tim.su
new file mode 100644
index 0000000..abe4c8c
--- /dev/null
+++ b/Fertirrega_v6/Debug/Core/Src/tim.su
@@ -0,0 +1,3 @@
+../Core/Src/tim.c:30:6:MX_TIM3_Init	32	static
+../Core/Src/tim.c:70:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/tim.c:86:6:HAL_TIM_Base_MspDeInit	16	static
diff --git a/Fertirrega_v6/Debug/Core/Src/usart.d b/Fertirrega_v6/Debug/Core/Src/usart.d
index 1eded02..0634dec 100644
--- a/Fertirrega_v6/Debug/Core/Src/usart.d
+++ b/Fertirrega_v6/Debug/Core/Src/usart.d
@@ -24,6 +24,8 @@ Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Core/Inc/usart.h:
 ../Core/Inc/main.h:
@@ -52,4 +54,6 @@ Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Core/Src/usart.o b/Fertirrega_v6/Debug/Core/Src/usart.o
index 4ec4c8c..19ef41d 100644
Binary files a/Fertirrega_v6/Debug/Core/Src/usart.o and b/Fertirrega_v6/Debug/Core/Src/usart.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d
index 40df42e..e2af949 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
index 3e8e575..17a8c1e 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d
index 7afef2c..4ec10ed 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
index c3824dc..984931e 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d
index dd47056..0598434 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
index 27d7969..aff4237 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d
index c3cc888..af1bfc2 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
index 3ff547b..5a122d7 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d
index c5a1679..ee268e7 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
index b30d90f..81d96ce 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d
index 1680ca8..8f8489e 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
index d4636a4..e5f678b 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d
index c1445b4..302e289 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
index cebd1c6..430aae6 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d
index 664d9a0..53fc879 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
index 33e7656..15a8aa4 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d
index 78d4ced..d03bd45 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
index ea04d0d..1c3338c 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d
index 9687a4c..6322251 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
index 0a7fc52..2fed438 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d
index 29581c9..11d0215 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
index b9d6ead..2dbb40a 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d
index 5bd36cd..0f68693 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
index 0d449b8..46dc1bb 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d
index f5a74be..b040f87 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
index 6853e69..f1d32d6 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d
index 8a1f798..cd21565 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
index 38a6683..2351580 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo
new file mode 100644
index 0000000..49af5bb
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo
@@ -0,0 +1,119 @@
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:266:19:HAL_TIM_Base_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:400:19:HAL_TIM_Base_Start	7
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:439:19:HAL_TIM_Base_Stop	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT	7
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA	11
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:650:19:HAL_TIM_OC_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:789:19:HAL_TIM_OC_Start	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:843:19:HAL_TIM_OC_Stop	9
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT	19
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA	29
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop	9
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT	19
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA	29
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1979:19:HAL_TIM_IC_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2118:19:HAL_TIM_IC_Start	20
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop	9
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT	25
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA	32
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3133:19:HAL_TIM_Encoder_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3178:13:HAL_TIM_Encoder_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3193:13:HAL_TIM_Encoder_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3213:19:HAL_TIM_Encoder_Start	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3307:19:HAL_TIM_Encoder_Stop	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3367:19:HAL_TIM_Encoder_Start_IT	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3467:19:HAL_TIM_Encoder_Stop_IT	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3532:19:HAL_TIM_Encoder_Start_DMA	32
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3745:19:HAL_TIM_Encoder_Stop_DMA	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3822:6:HAL_TIM_IRQHandler	21
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4040:19:HAL_TIM_OC_ConfigChannel	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4119:19:HAL_TIM_IC_ConfigChannel	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4218:19:HAL_TIM_PWM_ConfigChannel	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4332:19:HAL_TIM_OnePulse_ConfigChannel	8
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4480:19:HAL_TIM_DMABurst_WriteStart	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4533:19:HAL_TIM_DMABurst_MultiWriteStart	25
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4717:19:HAL_TIM_DMABurst_WriteStop	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4818:19:HAL_TIM_DMABurst_ReadStart	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4869:19:HAL_TIM_DMABurst_MultiReadStart	25
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5053:19:HAL_TIM_DMABurst_ReadStop	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5136:19:HAL_TIM_GenerateEvent	2
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5173:19:HAL_TIM_ConfigOCrefClear	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5303:19:HAL_TIM_ConfigClockSource	20
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5457:19:HAL_TIM_ConfigTI1Input	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5489:19:HAL_TIM_SlaveConfigSynchro	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5529:19:HAL_TIM_SlaveConfigSynchro_IT	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5572:10:HAL_TIM_ReadCapturedValue	5
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5656:13:HAL_TIM_PeriodElapsedCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5671:13:HAL_TIM_PeriodElapsedHalfCpltCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5686:13:HAL_TIM_OC_DelayElapsedCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5701:13:HAL_TIM_IC_CaptureCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5716:13:HAL_TIM_IC_CaptureHalfCpltCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5731:13:HAL_TIM_PWM_PulseFinishedCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5746:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5761:13:HAL_TIM_TriggerCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5776:13:HAL_TIM_TriggerHalfCpltCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5791:13:HAL_TIM_ErrorCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6338:22:HAL_TIM_Base_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6348:22:HAL_TIM_OC_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6358:22:HAL_TIM_PWM_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6368:22:HAL_TIM_IC_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6378:22:HAL_TIM_OnePulse_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6388:22:HAL_TIM_Encoder_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6398:23:HAL_TIM_GetActiveChannel	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6416:29:HAL_TIM_GetChannelState	4
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6433:30:HAL_TIM_DMABurstState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6458:6:TIM_DMAError	5
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6501:13:TIM_DMADelayPulseCplt	9
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6560:6:TIM_DMADelayPulseHalfCplt	5
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6599:6:TIM_DMACaptureCplt	9
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6662:6:TIM_DMACaptureHalfCplt	5
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6701:13:TIM_DMAPeriodElapsedCplt	2
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6722:13:TIM_DMAPeriodElapsedHalfCplt	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6738:13:TIM_DMATriggerCplt	2
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6759:13:TIM_DMATriggerHalfCplt	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6776:6:TIM_Base_SetConfig	11
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6831:13:TIM_OC1_SetConfig	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6907:6:TIM_OC2_SetConfig	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6983:13:TIM_OC3_SetConfig	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7058:13:TIM_OC4_SetConfig	2
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7119:26:TIM_SlaveTimer_SetConfig	16
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7253:6:TIM_TI1_SetConfig	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7300:13:TIM_TI1_ConfigInputStage	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7343:13:TIM_TI2_SetConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7383:13:TIM_TI2_ConfigInputStage	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7425:13:TIM_TI3_SetConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7472:13:TIM_TI4_SetConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7545:6:TIM_ETR_SetConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7575:6:TIM_CCxChannelCmd	1
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d
new file mode 100644
index 0000000..00bd782
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d
@@ -0,0 +1,58 @@
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o: \
+ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
+ ../Core/Inc/stm32f1xx_hal_conf.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
+../Core/Inc/stm32f1xx_hal_conf.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
new file mode 100644
index 0000000..1ab13ac
Binary files /dev/null and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su
new file mode 100644
index 0000000..250a0bd
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su
@@ -0,0 +1,119 @@
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:266:19:HAL_TIM_Base_Init	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:400:19:HAL_TIM_Base_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:439:19:HAL_TIM_Base_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:650:19:HAL_TIM_OC_Init	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:789:19:HAL_TIM_OC_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:843:19:HAL_TIM_OC_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1979:19:HAL_TIM_IC_Init	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2118:19:HAL_TIM_IC_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3133:19:HAL_TIM_Encoder_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3178:13:HAL_TIM_Encoder_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3193:13:HAL_TIM_Encoder_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3213:19:HAL_TIM_Encoder_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3307:19:HAL_TIM_Encoder_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3367:19:HAL_TIM_Encoder_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3467:19:HAL_TIM_Encoder_Stop_IT	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3532:19:HAL_TIM_Encoder_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3745:19:HAL_TIM_Encoder_Stop_DMA	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3822:6:HAL_TIM_IRQHandler	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4040:19:HAL_TIM_OC_ConfigChannel	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4119:19:HAL_TIM_IC_ConfigChannel	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4218:19:HAL_TIM_PWM_ConfigChannel	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4332:19:HAL_TIM_OnePulse_ConfigChannel	56	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4480:19:HAL_TIM_DMABurst_WriteStart	40	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4533:19:HAL_TIM_DMABurst_MultiWriteStart	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4717:19:HAL_TIM_DMABurst_WriteStop	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4818:19:HAL_TIM_DMABurst_ReadStart	40	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:4869:19:HAL_TIM_DMABurst_MultiReadStart	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5053:19:HAL_TIM_DMABurst_ReadStop	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5136:19:HAL_TIM_GenerateEvent	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5173:19:HAL_TIM_ConfigOCrefClear	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5303:19:HAL_TIM_ConfigClockSource	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5457:19:HAL_TIM_ConfigTI1Input	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5489:19:HAL_TIM_SlaveConfigSynchro	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5529:19:HAL_TIM_SlaveConfigSynchro_IT	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5572:10:HAL_TIM_ReadCapturedValue	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5656:13:HAL_TIM_PeriodElapsedCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5671:13:HAL_TIM_PeriodElapsedHalfCpltCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5686:13:HAL_TIM_OC_DelayElapsedCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5701:13:HAL_TIM_IC_CaptureCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5716:13:HAL_TIM_IC_CaptureHalfCpltCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5731:13:HAL_TIM_PWM_PulseFinishedCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5746:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5761:13:HAL_TIM_TriggerCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5776:13:HAL_TIM_TriggerHalfCpltCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:5791:13:HAL_TIM_ErrorCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6338:22:HAL_TIM_Base_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6348:22:HAL_TIM_OC_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6358:22:HAL_TIM_PWM_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6368:22:HAL_TIM_IC_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6378:22:HAL_TIM_OnePulse_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6388:22:HAL_TIM_Encoder_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6398:23:HAL_TIM_GetActiveChannel	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6416:29:HAL_TIM_GetChannelState	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6433:30:HAL_TIM_DMABurstState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6458:6:TIM_DMAError	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6501:13:TIM_DMADelayPulseCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6560:6:TIM_DMADelayPulseHalfCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6599:6:TIM_DMACaptureCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6662:6:TIM_DMACaptureHalfCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6701:13:TIM_DMAPeriodElapsedCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6722:13:TIM_DMAPeriodElapsedHalfCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6738:13:TIM_DMATriggerCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6759:13:TIM_DMATriggerHalfCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6776:6:TIM_Base_SetConfig	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6831:13:TIM_OC1_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6907:6:TIM_OC2_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6983:13:TIM_OC3_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7058:13:TIM_OC4_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7119:26:TIM_SlaveTimer_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7253:6:TIM_TI1_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7300:13:TIM_TI1_ConfigInputStage	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7343:13:TIM_TI2_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7383:13:TIM_TI2_ConfigInputStage	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7425:13:TIM_TI3_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7472:13:TIM_TI4_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7545:6:TIM_ETR_SetConfig	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7575:6:TIM_CCxChannelCmd	32	static
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo
new file mode 100644
index 0000000..32fe42a
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo
@@ -0,0 +1,42 @@
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start	10
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT	10
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA	3
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop	8
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT	18
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA	27
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop	8
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT	18
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT	14
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA	27
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA	13
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization	6
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime	2
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2062:19:HAL_TIMEx_RemapConfig	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2096:13:HAL_TIMEx_CommutCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2110:13:HAL_TIMEx_CommutHalfCpltCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2125:13:HAL_TIMEx_BreakCallback	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2158:22:HAL_TIMEx_HallSensor_GetState	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2173:29:HAL_TIMEx_GetChannelNState	4
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2202:6:TIMEx_DMACommutationCplt	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2221:6:TIMEx_DMACommutationHalfCplt	1
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2241:13:TIM_DMADelayPulseNCplt	7
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2291:13:TIM_DMAErrorCCxN	4
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2336:13:TIM_CCxNChannelCmd	1
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d
new file mode 100644
index 0000000..3fb0dcb
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d
@@ -0,0 +1,58 @@
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o: \
+ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
+ ../Core/Inc/stm32f1xx_hal_conf.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
+../Core/Inc/stm32f1xx_hal_conf.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
new file mode 100644
index 0000000..afb9fe9
Binary files /dev/null and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su
new file mode 100644
index 0000000..905fd6f
--- /dev/null
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su
@@ -0,0 +1,42 @@
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init	48	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA	32	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2062:19:HAL_TIMEx_RemapConfig	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2096:13:HAL_TIMEx_CommutCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2110:13:HAL_TIMEx_CommutHalfCpltCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2125:13:HAL_TIMEx_BreakCallback	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2158:22:HAL_TIMEx_HallSensor_GetState	16	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2173:29:HAL_TIMEx_GetChannelNState	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2202:6:TIMEx_DMACommutationCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2221:6:TIMEx_DMACommutationHalfCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2241:13:TIM_DMADelayPulseNCplt	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2291:13:TIM_DMAErrorCCxN	24	static
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2336:13:TIM_CCxNChannelCmd	32	static
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d
index 4e2c2df..146fba3 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d
@@ -25,6 +25,8 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o: \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h \
+ ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h \
  ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
 ../Core/Inc/stm32f1xx_hal_conf.h:
@@ -51,4 +53,6 @@ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o: \
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h:
+../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
 ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h:
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
index 8f8ab7c..1ddb398 100644
Binary files a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o and b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o differ
diff --git a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
index b2d0f1e..990cf88 100644
--- a/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
+++ b/Fertirrega_v6/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
@@ -19,6 +19,8 @@ C_SRCS += \
 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \
 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \
 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \
 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c 
 
 OBJS += \
@@ -36,6 +38,8 @@ OBJS += \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o 
 
 C_DEPS += \
@@ -53,6 +57,8 @@ C_DEPS += \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \
 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d 
 
 
@@ -63,7 +69,7 @@ Drivers/STM32F1xx_HAL_Driver/Src/%.o Drivers/STM32F1xx_HAL_Driver/Src/%.su Drive
 clean: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src
 
 clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src:
-	-$(RM) ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su
+	-$(RM) ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su
 
 .PHONY: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src
 
diff --git a/Fertirrega_v6/Debug/Fertirrega_v6.elf b/Fertirrega_v6/Debug/Fertirrega_v6.elf
index 6c29b00..b2d051b 100644
Binary files a/Fertirrega_v6/Debug/Fertirrega_v6.elf and b/Fertirrega_v6/Debug/Fertirrega_v6.elf differ
diff --git a/Fertirrega_v6/Debug/Fertirrega_v6.list b/Fertirrega_v6/Debug/Fertirrega_v6.list
index e52561a..dc6e7b1 100644
--- a/Fertirrega_v6/Debug/Fertirrega_v6.list
+++ b/Fertirrega_v6/Debug/Fertirrega_v6.list
@@ -5,14922 +5,19597 @@ Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .isr_vector   0000010c  08000000  08000000  00001000  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         00005ddc  0800010c  0800010c  0000110c  2**2
+  1 .text         00007910  08000110  08000110  00001110  2**3
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       00000080  08005ee8  08005ee8  00006ee8  2**2
+  2 .rodata       00000088  08007a20  08007a20  00008a20  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08005f68  08005f68  00007078  2**0
+  3 .ARM.extab    00000000  08007aa8  08007aa8  00009080  2**0
                   CONTENTS, READONLY
-  4 .ARM          00000008  08005f68  08005f68  00006f68  2**2
+  4 .ARM          00000008  08007aa8  08007aa8  00008aa8  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  5 .preinit_array 00000000  08005f70  08005f70  00007078  2**0
+  5 .preinit_array 00000000  08007ab0  08007ab0  00009080  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  08005f70  08005f70  00006f70  2**2
+  6 .init_array   00000004  08007ab0  08007ab0  00008ab0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  7 .fini_array   00000004  08005f74  08005f74  00006f74  2**2
+  7 .fini_array   00000004  08007ab4  08007ab4  00008ab4  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  8 .data         00000078  20000000  08005f78  00007000  2**2
+  8 .data         00000080  20000000  08007ab8  00009000  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  9 .bss          000003e4  20000078  08005ff0  00007078  2**2
+  9 .bss          00000890  20000080  08007b38  00009080  2**3
                   ALLOC
- 10 ._user_heap_stack 00000604  2000045c  08005ff0  0000745c  2**0
+ 10 ._user_heap_stack 00000600  20000910  08007b38  00009910  2**0
                   ALLOC
- 11 .ARM.attributes 00000029  00000000  00000000  00007078  2**0
+ 11 .ARM.attributes 00000029  00000000  00000000  00009080  2**0
                   CONTENTS, READONLY
- 12 .debug_info   0000e8a7  00000000  00000000  000070a1  2**0
+ 12 .debug_info   000153e7  00000000  00000000  000090a9  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 13 .debug_abbrev 00002ca8  00000000  00000000  00015948  2**0
+ 13 .debug_abbrev 00003e1d  00000000  00000000  0001e490  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_aranges 00000cb8  00000000  00000000  000185f0  2**3
+ 14 .debug_aranges 00001418  00000000  00000000  000222b0  2**3
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_rnglists 000009da  00000000  00000000  000192a8  2**0
+ 15 .debug_rnglists 00000fb2  00000000  00000000  000236c8  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_macro  00019336  00000000  00000000  00019c82  2**0
+ 16 .debug_macro  0001ae5b  00000000  00000000  0002467a  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_line   00012131  00000000  00000000  00032fb8  2**0
+ 17 .debug_line   0001b209  00000000  00000000  0003f4d5  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_str    0008c894  00000000  00000000  000450e9  2**0
+ 18 .debug_str    0009592c  00000000  00000000  0005a6de  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .comment      00000043  00000000  00000000  000d197d  2**0
+ 19 .comment      00000043  00000000  00000000  000f000a  2**0
                   CONTENTS, READONLY
- 20 .debug_frame  00003488  00000000  00000000  000d19c0  2**2
+ 20 .debug_frame  00005410  00000000  00000000  000f0050  2**2
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 21 .debug_line_str 00000052  00000000  00000000  000d4e48  2**0
+ 21 .debug_line_str 00000052  00000000  00000000  000f5460  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
 
 Disassembly of section .text:
 
-0800010c <__do_global_dtors_aux>:
- 800010c:	b510      	push	{r4, lr}
- 800010e:	4c05      	ldr	r4, [pc, #20]	@ (8000124 <__do_global_dtors_aux+0x18>)
- 8000110:	7823      	ldrb	r3, [r4, #0]
- 8000112:	b933      	cbnz	r3, 8000122 <__do_global_dtors_aux+0x16>
- 8000114:	4b04      	ldr	r3, [pc, #16]	@ (8000128 <__do_global_dtors_aux+0x1c>)
- 8000116:	b113      	cbz	r3, 800011e <__do_global_dtors_aux+0x12>
- 8000118:	4804      	ldr	r0, [pc, #16]	@ (800012c <__do_global_dtors_aux+0x20>)
- 800011a:	f3af 8000 	nop.w
- 800011e:	2301      	movs	r3, #1
- 8000120:	7023      	strb	r3, [r4, #0]
- 8000122:	bd10      	pop	{r4, pc}
- 8000124:	20000078 	.word	0x20000078
- 8000128:	00000000 	.word	0x00000000
- 800012c:	08005ed0 	.word	0x08005ed0
+08000110 <__do_global_dtors_aux>:
+ 8000110:	b510      	push	{r4, lr}
+ 8000112:	4c05      	ldr	r4, [pc, #20]	@ (8000128 <__do_global_dtors_aux+0x18>)
+ 8000114:	7823      	ldrb	r3, [r4, #0]
+ 8000116:	b933      	cbnz	r3, 8000126 <__do_global_dtors_aux+0x16>
+ 8000118:	4b04      	ldr	r3, [pc, #16]	@ (800012c <__do_global_dtors_aux+0x1c>)
+ 800011a:	b113      	cbz	r3, 8000122 <__do_global_dtors_aux+0x12>
+ 800011c:	4804      	ldr	r0, [pc, #16]	@ (8000130 <__do_global_dtors_aux+0x20>)
+ 800011e:	f3af 8000 	nop.w
+ 8000122:	2301      	movs	r3, #1
+ 8000124:	7023      	strb	r3, [r4, #0]
+ 8000126:	bd10      	pop	{r4, pc}
+ 8000128:	20000080 	.word	0x20000080
+ 800012c:	00000000 	.word	0x00000000
+ 8000130:	08007a08 	.word	0x08007a08
 
-08000130 <frame_dummy>:
- 8000130:	b508      	push	{r3, lr}
- 8000132:	4b03      	ldr	r3, [pc, #12]	@ (8000140 <frame_dummy+0x10>)
- 8000134:	b11b      	cbz	r3, 800013e <frame_dummy+0xe>
- 8000136:	4903      	ldr	r1, [pc, #12]	@ (8000144 <frame_dummy+0x14>)
- 8000138:	4803      	ldr	r0, [pc, #12]	@ (8000148 <frame_dummy+0x18>)
- 800013a:	f3af 8000 	nop.w
- 800013e:	bd08      	pop	{r3, pc}
- 8000140:	00000000 	.word	0x00000000
- 8000144:	2000007c 	.word	0x2000007c
- 8000148:	08005ed0 	.word	0x08005ed0
+08000134 <frame_dummy>:
+ 8000134:	b508      	push	{r3, lr}
+ 8000136:	4b03      	ldr	r3, [pc, #12]	@ (8000144 <frame_dummy+0x10>)
+ 8000138:	b11b      	cbz	r3, 8000142 <frame_dummy+0xe>
+ 800013a:	4903      	ldr	r1, [pc, #12]	@ (8000148 <frame_dummy+0x14>)
+ 800013c:	4803      	ldr	r0, [pc, #12]	@ (800014c <frame_dummy+0x18>)
+ 800013e:	f3af 8000 	nop.w
+ 8000142:	bd08      	pop	{r3, pc}
+ 8000144:	00000000 	.word	0x00000000
+ 8000148:	20000084 	.word	0x20000084
+ 800014c:	08007a08 	.word	0x08007a08
 
-0800014c <strlen>:
- 800014c:	4603      	mov	r3, r0
- 800014e:	f813 2b01 	ldrb.w	r2, [r3], #1
- 8000152:	2a00      	cmp	r2, #0
- 8000154:	d1fb      	bne.n	800014e <strlen+0x2>
- 8000156:	1a18      	subs	r0, r3, r0
- 8000158:	3801      	subs	r0, #1
- 800015a:	4770      	bx	lr
+08000150 <strlen>:
+ 8000150:	4603      	mov	r3, r0
+ 8000152:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 8000156:	2a00      	cmp	r2, #0
+ 8000158:	d1fb      	bne.n	8000152 <strlen+0x2>
+ 800015a:	1a18      	subs	r0, r3, r0
+ 800015c:	3801      	subs	r0, #1
+ 800015e:	4770      	bx	lr
 
-0800015c <__aeabi_dmul>:
- 800015c:	b570      	push	{r4, r5, r6, lr}
- 800015e:	f04f 0cff 	mov.w	ip, #255	@ 0xff
- 8000162:	f44c 6ce0 	orr.w	ip, ip, #1792	@ 0x700
- 8000166:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
- 800016a:	bf1d      	ittte	ne
- 800016c:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
- 8000170:	ea94 0f0c 	teqne	r4, ip
- 8000174:	ea95 0f0c 	teqne	r5, ip
- 8000178:	f000 f8de 	bleq	8000338 <__aeabi_dmul+0x1dc>
- 800017c:	442c      	add	r4, r5
- 800017e:	ea81 0603 	eor.w	r6, r1, r3
- 8000182:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
- 8000186:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
- 800018a:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
- 800018e:	bf18      	it	ne
- 8000190:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
- 8000194:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
- 8000198:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
- 800019c:	d038      	beq.n	8000210 <__aeabi_dmul+0xb4>
- 800019e:	fba0 ce02 	umull	ip, lr, r0, r2
- 80001a2:	f04f 0500 	mov.w	r5, #0
- 80001a6:	fbe1 e502 	umlal	lr, r5, r1, r2
- 80001aa:	f006 4200 	and.w	r2, r6, #2147483648	@ 0x80000000
- 80001ae:	fbe0 e503 	umlal	lr, r5, r0, r3
- 80001b2:	f04f 0600 	mov.w	r6, #0
- 80001b6:	fbe1 5603 	umlal	r5, r6, r1, r3
- 80001ba:	f09c 0f00 	teq	ip, #0
- 80001be:	bf18      	it	ne
- 80001c0:	f04e 0e01 	orrne.w	lr, lr, #1
- 80001c4:	f1a4 04ff 	sub.w	r4, r4, #255	@ 0xff
- 80001c8:	f5b6 7f00 	cmp.w	r6, #512	@ 0x200
- 80001cc:	f564 7440 	sbc.w	r4, r4, #768	@ 0x300
- 80001d0:	d204      	bcs.n	80001dc <__aeabi_dmul+0x80>
- 80001d2:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
- 80001d6:	416d      	adcs	r5, r5
- 80001d8:	eb46 0606 	adc.w	r6, r6, r6
- 80001dc:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
- 80001e0:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
- 80001e4:	ea4f 20c5 	mov.w	r0, r5, lsl #11
- 80001e8:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
- 80001ec:	ea4f 2ece 	mov.w	lr, lr, lsl #11
- 80001f0:	f1b4 0cfd 	subs.w	ip, r4, #253	@ 0xfd
- 80001f4:	bf88      	it	hi
- 80001f6:	f5bc 6fe0 	cmphi.w	ip, #1792	@ 0x700
- 80001fa:	d81e      	bhi.n	800023a <__aeabi_dmul+0xde>
- 80001fc:	f1be 4f00 	cmp.w	lr, #2147483648	@ 0x80000000
- 8000200:	bf08      	it	eq
- 8000202:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
- 8000206:	f150 0000 	adcs.w	r0, r0, #0
- 800020a:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
- 800020e:	bd70      	pop	{r4, r5, r6, pc}
- 8000210:	f006 4600 	and.w	r6, r6, #2147483648	@ 0x80000000
- 8000214:	ea46 0101 	orr.w	r1, r6, r1
- 8000218:	ea40 0002 	orr.w	r0, r0, r2
- 800021c:	ea81 0103 	eor.w	r1, r1, r3
- 8000220:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
- 8000224:	bfc2      	ittt	gt
- 8000226:	ebd4 050c 	rsbsgt	r5, r4, ip
- 800022a:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
- 800022e:	bd70      	popgt	{r4, r5, r6, pc}
- 8000230:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
- 8000234:	f04f 0e00 	mov.w	lr, #0
- 8000238:	3c01      	subs	r4, #1
- 800023a:	f300 80ab 	bgt.w	8000394 <__aeabi_dmul+0x238>
- 800023e:	f114 0f36 	cmn.w	r4, #54	@ 0x36
- 8000242:	bfde      	ittt	le
- 8000244:	2000      	movle	r0, #0
- 8000246:	f001 4100 	andle.w	r1, r1, #2147483648	@ 0x80000000
- 800024a:	bd70      	pople	{r4, r5, r6, pc}
- 800024c:	f1c4 0400 	rsb	r4, r4, #0
- 8000250:	3c20      	subs	r4, #32
- 8000252:	da35      	bge.n	80002c0 <__aeabi_dmul+0x164>
- 8000254:	340c      	adds	r4, #12
- 8000256:	dc1b      	bgt.n	8000290 <__aeabi_dmul+0x134>
- 8000258:	f104 0414 	add.w	r4, r4, #20
- 800025c:	f1c4 0520 	rsb	r5, r4, #32
- 8000260:	fa00 f305 	lsl.w	r3, r0, r5
- 8000264:	fa20 f004 	lsr.w	r0, r0, r4
- 8000268:	fa01 f205 	lsl.w	r2, r1, r5
- 800026c:	ea40 0002 	orr.w	r0, r0, r2
- 8000270:	f001 4200 	and.w	r2, r1, #2147483648	@ 0x80000000
- 8000274:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
- 8000278:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
- 800027c:	fa21 f604 	lsr.w	r6, r1, r4
- 8000280:	eb42 0106 	adc.w	r1, r2, r6
- 8000284:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
- 8000288:	bf08      	it	eq
- 800028a:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
- 800028e:	bd70      	pop	{r4, r5, r6, pc}
- 8000290:	f1c4 040c 	rsb	r4, r4, #12
- 8000294:	f1c4 0520 	rsb	r5, r4, #32
- 8000298:	fa00 f304 	lsl.w	r3, r0, r4
- 800029c:	fa20 f005 	lsr.w	r0, r0, r5
- 80002a0:	fa01 f204 	lsl.w	r2, r1, r4
- 80002a4:	ea40 0002 	orr.w	r0, r0, r2
- 80002a8:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
- 80002ac:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
- 80002b0:	f141 0100 	adc.w	r1, r1, #0
- 80002b4:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
- 80002b8:	bf08      	it	eq
- 80002ba:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
- 80002be:	bd70      	pop	{r4, r5, r6, pc}
- 80002c0:	f1c4 0520 	rsb	r5, r4, #32
- 80002c4:	fa00 f205 	lsl.w	r2, r0, r5
- 80002c8:	ea4e 0e02 	orr.w	lr, lr, r2
- 80002cc:	fa20 f304 	lsr.w	r3, r0, r4
- 80002d0:	fa01 f205 	lsl.w	r2, r1, r5
- 80002d4:	ea43 0302 	orr.w	r3, r3, r2
- 80002d8:	fa21 f004 	lsr.w	r0, r1, r4
- 80002dc:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
- 80002e0:	fa21 f204 	lsr.w	r2, r1, r4
- 80002e4:	ea20 0002 	bic.w	r0, r0, r2
- 80002e8:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
- 80002ec:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
- 80002f0:	bf08      	it	eq
- 80002f2:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
- 80002f6:	bd70      	pop	{r4, r5, r6, pc}
- 80002f8:	f094 0f00 	teq	r4, #0
- 80002fc:	d10f      	bne.n	800031e <__aeabi_dmul+0x1c2>
- 80002fe:	f001 4600 	and.w	r6, r1, #2147483648	@ 0x80000000
- 8000302:	0040      	lsls	r0, r0, #1
- 8000304:	eb41 0101 	adc.w	r1, r1, r1
- 8000308:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
- 800030c:	bf08      	it	eq
- 800030e:	3c01      	subeq	r4, #1
- 8000310:	d0f7      	beq.n	8000302 <__aeabi_dmul+0x1a6>
- 8000312:	ea41 0106 	orr.w	r1, r1, r6
- 8000316:	f095 0f00 	teq	r5, #0
- 800031a:	bf18      	it	ne
- 800031c:	4770      	bxne	lr
- 800031e:	f003 4600 	and.w	r6, r3, #2147483648	@ 0x80000000
- 8000322:	0052      	lsls	r2, r2, #1
- 8000324:	eb43 0303 	adc.w	r3, r3, r3
- 8000328:	f413 1f80 	tst.w	r3, #1048576	@ 0x100000
- 800032c:	bf08      	it	eq
- 800032e:	3d01      	subeq	r5, #1
- 8000330:	d0f7      	beq.n	8000322 <__aeabi_dmul+0x1c6>
- 8000332:	ea43 0306 	orr.w	r3, r3, r6
- 8000336:	4770      	bx	lr
- 8000338:	ea94 0f0c 	teq	r4, ip
- 800033c:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
- 8000340:	bf18      	it	ne
- 8000342:	ea95 0f0c 	teqne	r5, ip
- 8000346:	d00c      	beq.n	8000362 <__aeabi_dmul+0x206>
- 8000348:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
- 800034c:	bf18      	it	ne
- 800034e:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
- 8000352:	d1d1      	bne.n	80002f8 <__aeabi_dmul+0x19c>
- 8000354:	ea81 0103 	eor.w	r1, r1, r3
- 8000358:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
- 800035c:	f04f 0000 	mov.w	r0, #0
- 8000360:	bd70      	pop	{r4, r5, r6, pc}
- 8000362:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
- 8000366:	bf06      	itte	eq
- 8000368:	4610      	moveq	r0, r2
- 800036a:	4619      	moveq	r1, r3
- 800036c:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
- 8000370:	d019      	beq.n	80003a6 <__aeabi_dmul+0x24a>
- 8000372:	ea94 0f0c 	teq	r4, ip
- 8000376:	d102      	bne.n	800037e <__aeabi_dmul+0x222>
- 8000378:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
- 800037c:	d113      	bne.n	80003a6 <__aeabi_dmul+0x24a>
- 800037e:	ea95 0f0c 	teq	r5, ip
- 8000382:	d105      	bne.n	8000390 <__aeabi_dmul+0x234>
- 8000384:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
- 8000388:	bf1c      	itt	ne
- 800038a:	4610      	movne	r0, r2
- 800038c:	4619      	movne	r1, r3
- 800038e:	d10a      	bne.n	80003a6 <__aeabi_dmul+0x24a>
- 8000390:	ea81 0103 	eor.w	r1, r1, r3
- 8000394:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
- 8000398:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
- 800039c:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
- 80003a0:	f04f 0000 	mov.w	r0, #0
- 80003a4:	bd70      	pop	{r4, r5, r6, pc}
- 80003a6:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
- 80003aa:	f441 0178 	orr.w	r1, r1, #16252928	@ 0xf80000
- 80003ae:	bd70      	pop	{r4, r5, r6, pc}
+08000160 <__aeabi_drsub>:
+ 8000160:	f081 4100 	eor.w	r1, r1, #2147483648	@ 0x80000000
+ 8000164:	e002      	b.n	800016c <__adddf3>
+ 8000166:	bf00      	nop
 
-080003b0 <__aeabi_drsub>:
- 80003b0:	f081 4100 	eor.w	r1, r1, #2147483648	@ 0x80000000
- 80003b4:	e002      	b.n	80003bc <__adddf3>
- 80003b6:	bf00      	nop
+08000168 <__aeabi_dsub>:
+ 8000168:	f083 4300 	eor.w	r3, r3, #2147483648	@ 0x80000000
 
-080003b8 <__aeabi_dsub>:
- 80003b8:	f083 4300 	eor.w	r3, r3, #2147483648	@ 0x80000000
+0800016c <__adddf3>:
+ 800016c:	b530      	push	{r4, r5, lr}
+ 800016e:	ea4f 0441 	mov.w	r4, r1, lsl #1
+ 8000172:	ea4f 0543 	mov.w	r5, r3, lsl #1
+ 8000176:	ea94 0f05 	teq	r4, r5
+ 800017a:	bf08      	it	eq
+ 800017c:	ea90 0f02 	teqeq	r0, r2
+ 8000180:	bf1f      	itttt	ne
+ 8000182:	ea54 0c00 	orrsne.w	ip, r4, r0
+ 8000186:	ea55 0c02 	orrsne.w	ip, r5, r2
+ 800018a:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
+ 800018e:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
+ 8000192:	f000 80e2 	beq.w	800035a <__adddf3+0x1ee>
+ 8000196:	ea4f 5454 	mov.w	r4, r4, lsr #21
+ 800019a:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
+ 800019e:	bfb8      	it	lt
+ 80001a0:	426d      	neglt	r5, r5
+ 80001a2:	dd0c      	ble.n	80001be <__adddf3+0x52>
+ 80001a4:	442c      	add	r4, r5
+ 80001a6:	ea80 0202 	eor.w	r2, r0, r2
+ 80001aa:	ea81 0303 	eor.w	r3, r1, r3
+ 80001ae:	ea82 0000 	eor.w	r0, r2, r0
+ 80001b2:	ea83 0101 	eor.w	r1, r3, r1
+ 80001b6:	ea80 0202 	eor.w	r2, r0, r2
+ 80001ba:	ea81 0303 	eor.w	r3, r1, r3
+ 80001be:	2d36      	cmp	r5, #54	@ 0x36
+ 80001c0:	bf88      	it	hi
+ 80001c2:	bd30      	pophi	{r4, r5, pc}
+ 80001c4:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
+ 80001c8:	ea4f 3101 	mov.w	r1, r1, lsl #12
+ 80001cc:	f44f 1c80 	mov.w	ip, #1048576	@ 0x100000
+ 80001d0:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
+ 80001d4:	d002      	beq.n	80001dc <__adddf3+0x70>
+ 80001d6:	4240      	negs	r0, r0
+ 80001d8:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
+ 80001dc:	f013 4f00 	tst.w	r3, #2147483648	@ 0x80000000
+ 80001e0:	ea4f 3303 	mov.w	r3, r3, lsl #12
+ 80001e4:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
+ 80001e8:	d002      	beq.n	80001f0 <__adddf3+0x84>
+ 80001ea:	4252      	negs	r2, r2
+ 80001ec:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
+ 80001f0:	ea94 0f05 	teq	r4, r5
+ 80001f4:	f000 80a7 	beq.w	8000346 <__adddf3+0x1da>
+ 80001f8:	f1a4 0401 	sub.w	r4, r4, #1
+ 80001fc:	f1d5 0e20 	rsbs	lr, r5, #32
+ 8000200:	db0d      	blt.n	800021e <__adddf3+0xb2>
+ 8000202:	fa02 fc0e 	lsl.w	ip, r2, lr
+ 8000206:	fa22 f205 	lsr.w	r2, r2, r5
+ 800020a:	1880      	adds	r0, r0, r2
+ 800020c:	f141 0100 	adc.w	r1, r1, #0
+ 8000210:	fa03 f20e 	lsl.w	r2, r3, lr
+ 8000214:	1880      	adds	r0, r0, r2
+ 8000216:	fa43 f305 	asr.w	r3, r3, r5
+ 800021a:	4159      	adcs	r1, r3
+ 800021c:	e00e      	b.n	800023c <__adddf3+0xd0>
+ 800021e:	f1a5 0520 	sub.w	r5, r5, #32
+ 8000222:	f10e 0e20 	add.w	lr, lr, #32
+ 8000226:	2a01      	cmp	r2, #1
+ 8000228:	fa03 fc0e 	lsl.w	ip, r3, lr
+ 800022c:	bf28      	it	cs
+ 800022e:	f04c 0c02 	orrcs.w	ip, ip, #2
+ 8000232:	fa43 f305 	asr.w	r3, r3, r5
+ 8000236:	18c0      	adds	r0, r0, r3
+ 8000238:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
+ 800023c:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
+ 8000240:	d507      	bpl.n	8000252 <__adddf3+0xe6>
+ 8000242:	f04f 0e00 	mov.w	lr, #0
+ 8000246:	f1dc 0c00 	rsbs	ip, ip, #0
+ 800024a:	eb7e 0000 	sbcs.w	r0, lr, r0
+ 800024e:	eb6e 0101 	sbc.w	r1, lr, r1
+ 8000252:	f5b1 1f80 	cmp.w	r1, #1048576	@ 0x100000
+ 8000256:	d31b      	bcc.n	8000290 <__adddf3+0x124>
+ 8000258:	f5b1 1f00 	cmp.w	r1, #2097152	@ 0x200000
+ 800025c:	d30c      	bcc.n	8000278 <__adddf3+0x10c>
+ 800025e:	0849      	lsrs	r1, r1, #1
+ 8000260:	ea5f 0030 	movs.w	r0, r0, rrx
+ 8000264:	ea4f 0c3c 	mov.w	ip, ip, rrx
+ 8000268:	f104 0401 	add.w	r4, r4, #1
+ 800026c:	ea4f 5244 	mov.w	r2, r4, lsl #21
+ 8000270:	f512 0f80 	cmn.w	r2, #4194304	@ 0x400000
+ 8000274:	f080 809a 	bcs.w	80003ac <__adddf3+0x240>
+ 8000278:	f1bc 4f00 	cmp.w	ip, #2147483648	@ 0x80000000
+ 800027c:	bf08      	it	eq
+ 800027e:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
+ 8000282:	f150 0000 	adcs.w	r0, r0, #0
+ 8000286:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
+ 800028a:	ea41 0105 	orr.w	r1, r1, r5
+ 800028e:	bd30      	pop	{r4, r5, pc}
+ 8000290:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
+ 8000294:	4140      	adcs	r0, r0
+ 8000296:	eb41 0101 	adc.w	r1, r1, r1
+ 800029a:	3c01      	subs	r4, #1
+ 800029c:	bf28      	it	cs
+ 800029e:	f5b1 1f80 	cmpcs.w	r1, #1048576	@ 0x100000
+ 80002a2:	d2e9      	bcs.n	8000278 <__adddf3+0x10c>
+ 80002a4:	f091 0f00 	teq	r1, #0
+ 80002a8:	bf04      	itt	eq
+ 80002aa:	4601      	moveq	r1, r0
+ 80002ac:	2000      	moveq	r0, #0
+ 80002ae:	fab1 f381 	clz	r3, r1
+ 80002b2:	bf08      	it	eq
+ 80002b4:	3320      	addeq	r3, #32
+ 80002b6:	f1a3 030b 	sub.w	r3, r3, #11
+ 80002ba:	f1b3 0220 	subs.w	r2, r3, #32
+ 80002be:	da0c      	bge.n	80002da <__adddf3+0x16e>
+ 80002c0:	320c      	adds	r2, #12
+ 80002c2:	dd08      	ble.n	80002d6 <__adddf3+0x16a>
+ 80002c4:	f102 0c14 	add.w	ip, r2, #20
+ 80002c8:	f1c2 020c 	rsb	r2, r2, #12
+ 80002cc:	fa01 f00c 	lsl.w	r0, r1, ip
+ 80002d0:	fa21 f102 	lsr.w	r1, r1, r2
+ 80002d4:	e00c      	b.n	80002f0 <__adddf3+0x184>
+ 80002d6:	f102 0214 	add.w	r2, r2, #20
+ 80002da:	bfd8      	it	le
+ 80002dc:	f1c2 0c20 	rsble	ip, r2, #32
+ 80002e0:	fa01 f102 	lsl.w	r1, r1, r2
+ 80002e4:	fa20 fc0c 	lsr.w	ip, r0, ip
+ 80002e8:	bfdc      	itt	le
+ 80002ea:	ea41 010c 	orrle.w	r1, r1, ip
+ 80002ee:	4090      	lslle	r0, r2
+ 80002f0:	1ae4      	subs	r4, r4, r3
+ 80002f2:	bfa2      	ittt	ge
+ 80002f4:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
+ 80002f8:	4329      	orrge	r1, r5
+ 80002fa:	bd30      	popge	{r4, r5, pc}
+ 80002fc:	ea6f 0404 	mvn.w	r4, r4
+ 8000300:	3c1f      	subs	r4, #31
+ 8000302:	da1c      	bge.n	800033e <__adddf3+0x1d2>
+ 8000304:	340c      	adds	r4, #12
+ 8000306:	dc0e      	bgt.n	8000326 <__adddf3+0x1ba>
+ 8000308:	f104 0414 	add.w	r4, r4, #20
+ 800030c:	f1c4 0220 	rsb	r2, r4, #32
+ 8000310:	fa20 f004 	lsr.w	r0, r0, r4
+ 8000314:	fa01 f302 	lsl.w	r3, r1, r2
+ 8000318:	ea40 0003 	orr.w	r0, r0, r3
+ 800031c:	fa21 f304 	lsr.w	r3, r1, r4
+ 8000320:	ea45 0103 	orr.w	r1, r5, r3
+ 8000324:	bd30      	pop	{r4, r5, pc}
+ 8000326:	f1c4 040c 	rsb	r4, r4, #12
+ 800032a:	f1c4 0220 	rsb	r2, r4, #32
+ 800032e:	fa20 f002 	lsr.w	r0, r0, r2
+ 8000332:	fa01 f304 	lsl.w	r3, r1, r4
+ 8000336:	ea40 0003 	orr.w	r0, r0, r3
+ 800033a:	4629      	mov	r1, r5
+ 800033c:	bd30      	pop	{r4, r5, pc}
+ 800033e:	fa21 f004 	lsr.w	r0, r1, r4
+ 8000342:	4629      	mov	r1, r5
+ 8000344:	bd30      	pop	{r4, r5, pc}
+ 8000346:	f094 0f00 	teq	r4, #0
+ 800034a:	f483 1380 	eor.w	r3, r3, #1048576	@ 0x100000
+ 800034e:	bf06      	itte	eq
+ 8000350:	f481 1180 	eoreq.w	r1, r1, #1048576	@ 0x100000
+ 8000354:	3401      	addeq	r4, #1
+ 8000356:	3d01      	subne	r5, #1
+ 8000358:	e74e      	b.n	80001f8 <__adddf3+0x8c>
+ 800035a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
+ 800035e:	bf18      	it	ne
+ 8000360:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
+ 8000364:	d029      	beq.n	80003ba <__adddf3+0x24e>
+ 8000366:	ea94 0f05 	teq	r4, r5
+ 800036a:	bf08      	it	eq
+ 800036c:	ea90 0f02 	teqeq	r0, r2
+ 8000370:	d005      	beq.n	800037e <__adddf3+0x212>
+ 8000372:	ea54 0c00 	orrs.w	ip, r4, r0
+ 8000376:	bf04      	itt	eq
+ 8000378:	4619      	moveq	r1, r3
+ 800037a:	4610      	moveq	r0, r2
+ 800037c:	bd30      	pop	{r4, r5, pc}
+ 800037e:	ea91 0f03 	teq	r1, r3
+ 8000382:	bf1e      	ittt	ne
+ 8000384:	2100      	movne	r1, #0
+ 8000386:	2000      	movne	r0, #0
+ 8000388:	bd30      	popne	{r4, r5, pc}
+ 800038a:	ea5f 5c54 	movs.w	ip, r4, lsr #21
+ 800038e:	d105      	bne.n	800039c <__adddf3+0x230>
+ 8000390:	0040      	lsls	r0, r0, #1
+ 8000392:	4149      	adcs	r1, r1
+ 8000394:	bf28      	it	cs
+ 8000396:	f041 4100 	orrcs.w	r1, r1, #2147483648	@ 0x80000000
+ 800039a:	bd30      	pop	{r4, r5, pc}
+ 800039c:	f514 0480 	adds.w	r4, r4, #4194304	@ 0x400000
+ 80003a0:	bf3c      	itt	cc
+ 80003a2:	f501 1180 	addcc.w	r1, r1, #1048576	@ 0x100000
+ 80003a6:	bd30      	popcc	{r4, r5, pc}
+ 80003a8:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
+ 80003ac:	f045 41fe 	orr.w	r1, r5, #2130706432	@ 0x7f000000
+ 80003b0:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
+ 80003b4:	f04f 0000 	mov.w	r0, #0
+ 80003b8:	bd30      	pop	{r4, r5, pc}
+ 80003ba:	ea7f 5c64 	mvns.w	ip, r4, asr #21
+ 80003be:	bf1a      	itte	ne
+ 80003c0:	4619      	movne	r1, r3
+ 80003c2:	4610      	movne	r0, r2
+ 80003c4:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
+ 80003c8:	bf1c      	itt	ne
+ 80003ca:	460b      	movne	r3, r1
+ 80003cc:	4602      	movne	r2, r0
+ 80003ce:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
+ 80003d2:	bf06      	itte	eq
+ 80003d4:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
+ 80003d8:	ea91 0f03 	teqeq	r1, r3
+ 80003dc:	f441 2100 	orrne.w	r1, r1, #524288	@ 0x80000
+ 80003e0:	bd30      	pop	{r4, r5, pc}
+ 80003e2:	bf00      	nop
 
-080003bc <__adddf3>:
- 80003bc:	b530      	push	{r4, r5, lr}
- 80003be:	ea4f 0441 	mov.w	r4, r1, lsl #1
- 80003c2:	ea4f 0543 	mov.w	r5, r3, lsl #1
- 80003c6:	ea94 0f05 	teq	r4, r5
- 80003ca:	bf08      	it	eq
- 80003cc:	ea90 0f02 	teqeq	r0, r2
- 80003d0:	bf1f      	itttt	ne
- 80003d2:	ea54 0c00 	orrsne.w	ip, r4, r0
- 80003d6:	ea55 0c02 	orrsne.w	ip, r5, r2
- 80003da:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
- 80003de:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
- 80003e2:	f000 80e2 	beq.w	80005aa <__adddf3+0x1ee>
- 80003e6:	ea4f 5454 	mov.w	r4, r4, lsr #21
- 80003ea:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
- 80003ee:	bfb8      	it	lt
- 80003f0:	426d      	neglt	r5, r5
- 80003f2:	dd0c      	ble.n	800040e <__adddf3+0x52>
- 80003f4:	442c      	add	r4, r5
- 80003f6:	ea80 0202 	eor.w	r2, r0, r2
- 80003fa:	ea81 0303 	eor.w	r3, r1, r3
- 80003fe:	ea82 0000 	eor.w	r0, r2, r0
- 8000402:	ea83 0101 	eor.w	r1, r3, r1
- 8000406:	ea80 0202 	eor.w	r2, r0, r2
- 800040a:	ea81 0303 	eor.w	r3, r1, r3
- 800040e:	2d36      	cmp	r5, #54	@ 0x36
- 8000410:	bf88      	it	hi
- 8000412:	bd30      	pophi	{r4, r5, pc}
- 8000414:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
- 8000418:	ea4f 3101 	mov.w	r1, r1, lsl #12
- 800041c:	f44f 1c80 	mov.w	ip, #1048576	@ 0x100000
- 8000420:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
- 8000424:	d002      	beq.n	800042c <__adddf3+0x70>
- 8000426:	4240      	negs	r0, r0
- 8000428:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
- 800042c:	f013 4f00 	tst.w	r3, #2147483648	@ 0x80000000
- 8000430:	ea4f 3303 	mov.w	r3, r3, lsl #12
- 8000434:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
- 8000438:	d002      	beq.n	8000440 <__adddf3+0x84>
- 800043a:	4252      	negs	r2, r2
- 800043c:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
- 8000440:	ea94 0f05 	teq	r4, r5
- 8000444:	f000 80a7 	beq.w	8000596 <__adddf3+0x1da>
- 8000448:	f1a4 0401 	sub.w	r4, r4, #1
- 800044c:	f1d5 0e20 	rsbs	lr, r5, #32
- 8000450:	db0d      	blt.n	800046e <__adddf3+0xb2>
- 8000452:	fa02 fc0e 	lsl.w	ip, r2, lr
- 8000456:	fa22 f205 	lsr.w	r2, r2, r5
- 800045a:	1880      	adds	r0, r0, r2
- 800045c:	f141 0100 	adc.w	r1, r1, #0
- 8000460:	fa03 f20e 	lsl.w	r2, r3, lr
- 8000464:	1880      	adds	r0, r0, r2
- 8000466:	fa43 f305 	asr.w	r3, r3, r5
- 800046a:	4159      	adcs	r1, r3
- 800046c:	e00e      	b.n	800048c <__adddf3+0xd0>
- 800046e:	f1a5 0520 	sub.w	r5, r5, #32
- 8000472:	f10e 0e20 	add.w	lr, lr, #32
- 8000476:	2a01      	cmp	r2, #1
- 8000478:	fa03 fc0e 	lsl.w	ip, r3, lr
- 800047c:	bf28      	it	cs
- 800047e:	f04c 0c02 	orrcs.w	ip, ip, #2
- 8000482:	fa43 f305 	asr.w	r3, r3, r5
- 8000486:	18c0      	adds	r0, r0, r3
- 8000488:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
- 800048c:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
- 8000490:	d507      	bpl.n	80004a2 <__adddf3+0xe6>
- 8000492:	f04f 0e00 	mov.w	lr, #0
- 8000496:	f1dc 0c00 	rsbs	ip, ip, #0
- 800049a:	eb7e 0000 	sbcs.w	r0, lr, r0
- 800049e:	eb6e 0101 	sbc.w	r1, lr, r1
- 80004a2:	f5b1 1f80 	cmp.w	r1, #1048576	@ 0x100000
- 80004a6:	d31b      	bcc.n	80004e0 <__adddf3+0x124>
- 80004a8:	f5b1 1f00 	cmp.w	r1, #2097152	@ 0x200000
- 80004ac:	d30c      	bcc.n	80004c8 <__adddf3+0x10c>
- 80004ae:	0849      	lsrs	r1, r1, #1
- 80004b0:	ea5f 0030 	movs.w	r0, r0, rrx
- 80004b4:	ea4f 0c3c 	mov.w	ip, ip, rrx
- 80004b8:	f104 0401 	add.w	r4, r4, #1
- 80004bc:	ea4f 5244 	mov.w	r2, r4, lsl #21
- 80004c0:	f512 0f80 	cmn.w	r2, #4194304	@ 0x400000
- 80004c4:	f080 809a 	bcs.w	80005fc <__adddf3+0x240>
- 80004c8:	f1bc 4f00 	cmp.w	ip, #2147483648	@ 0x80000000
- 80004cc:	bf08      	it	eq
- 80004ce:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
- 80004d2:	f150 0000 	adcs.w	r0, r0, #0
- 80004d6:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
- 80004da:	ea41 0105 	orr.w	r1, r1, r5
- 80004de:	bd30      	pop	{r4, r5, pc}
- 80004e0:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
- 80004e4:	4140      	adcs	r0, r0
- 80004e6:	eb41 0101 	adc.w	r1, r1, r1
- 80004ea:	3c01      	subs	r4, #1
- 80004ec:	bf28      	it	cs
- 80004ee:	f5b1 1f80 	cmpcs.w	r1, #1048576	@ 0x100000
- 80004f2:	d2e9      	bcs.n	80004c8 <__adddf3+0x10c>
- 80004f4:	f091 0f00 	teq	r1, #0
- 80004f8:	bf04      	itt	eq
- 80004fa:	4601      	moveq	r1, r0
- 80004fc:	2000      	moveq	r0, #0
- 80004fe:	fab1 f381 	clz	r3, r1
- 8000502:	bf08      	it	eq
- 8000504:	3320      	addeq	r3, #32
- 8000506:	f1a3 030b 	sub.w	r3, r3, #11
- 800050a:	f1b3 0220 	subs.w	r2, r3, #32
- 800050e:	da0c      	bge.n	800052a <__adddf3+0x16e>
- 8000510:	320c      	adds	r2, #12
- 8000512:	dd08      	ble.n	8000526 <__adddf3+0x16a>
- 8000514:	f102 0c14 	add.w	ip, r2, #20
- 8000518:	f1c2 020c 	rsb	r2, r2, #12
- 800051c:	fa01 f00c 	lsl.w	r0, r1, ip
- 8000520:	fa21 f102 	lsr.w	r1, r1, r2
- 8000524:	e00c      	b.n	8000540 <__adddf3+0x184>
- 8000526:	f102 0214 	add.w	r2, r2, #20
- 800052a:	bfd8      	it	le
- 800052c:	f1c2 0c20 	rsble	ip, r2, #32
- 8000530:	fa01 f102 	lsl.w	r1, r1, r2
- 8000534:	fa20 fc0c 	lsr.w	ip, r0, ip
- 8000538:	bfdc      	itt	le
- 800053a:	ea41 010c 	orrle.w	r1, r1, ip
- 800053e:	4090      	lslle	r0, r2
- 8000540:	1ae4      	subs	r4, r4, r3
- 8000542:	bfa2      	ittt	ge
- 8000544:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
- 8000548:	4329      	orrge	r1, r5
- 800054a:	bd30      	popge	{r4, r5, pc}
- 800054c:	ea6f 0404 	mvn.w	r4, r4
- 8000550:	3c1f      	subs	r4, #31
- 8000552:	da1c      	bge.n	800058e <__adddf3+0x1d2>
- 8000554:	340c      	adds	r4, #12
- 8000556:	dc0e      	bgt.n	8000576 <__adddf3+0x1ba>
- 8000558:	f104 0414 	add.w	r4, r4, #20
- 800055c:	f1c4 0220 	rsb	r2, r4, #32
- 8000560:	fa20 f004 	lsr.w	r0, r0, r4
- 8000564:	fa01 f302 	lsl.w	r3, r1, r2
- 8000568:	ea40 0003 	orr.w	r0, r0, r3
- 800056c:	fa21 f304 	lsr.w	r3, r1, r4
- 8000570:	ea45 0103 	orr.w	r1, r5, r3
- 8000574:	bd30      	pop	{r4, r5, pc}
- 8000576:	f1c4 040c 	rsb	r4, r4, #12
- 800057a:	f1c4 0220 	rsb	r2, r4, #32
- 800057e:	fa20 f002 	lsr.w	r0, r0, r2
- 8000582:	fa01 f304 	lsl.w	r3, r1, r4
- 8000586:	ea40 0003 	orr.w	r0, r0, r3
- 800058a:	4629      	mov	r1, r5
- 800058c:	bd30      	pop	{r4, r5, pc}
- 800058e:	fa21 f004 	lsr.w	r0, r1, r4
- 8000592:	4629      	mov	r1, r5
- 8000594:	bd30      	pop	{r4, r5, pc}
- 8000596:	f094 0f00 	teq	r4, #0
- 800059a:	f483 1380 	eor.w	r3, r3, #1048576	@ 0x100000
- 800059e:	bf06      	itte	eq
- 80005a0:	f481 1180 	eoreq.w	r1, r1, #1048576	@ 0x100000
- 80005a4:	3401      	addeq	r4, #1
- 80005a6:	3d01      	subne	r5, #1
- 80005a8:	e74e      	b.n	8000448 <__adddf3+0x8c>
- 80005aa:	ea7f 5c64 	mvns.w	ip, r4, asr #21
- 80005ae:	bf18      	it	ne
- 80005b0:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
- 80005b4:	d029      	beq.n	800060a <__adddf3+0x24e>
- 80005b6:	ea94 0f05 	teq	r4, r5
- 80005ba:	bf08      	it	eq
- 80005bc:	ea90 0f02 	teqeq	r0, r2
- 80005c0:	d005      	beq.n	80005ce <__adddf3+0x212>
- 80005c2:	ea54 0c00 	orrs.w	ip, r4, r0
- 80005c6:	bf04      	itt	eq
- 80005c8:	4619      	moveq	r1, r3
- 80005ca:	4610      	moveq	r0, r2
- 80005cc:	bd30      	pop	{r4, r5, pc}
- 80005ce:	ea91 0f03 	teq	r1, r3
- 80005d2:	bf1e      	ittt	ne
- 80005d4:	2100      	movne	r1, #0
- 80005d6:	2000      	movne	r0, #0
- 80005d8:	bd30      	popne	{r4, r5, pc}
- 80005da:	ea5f 5c54 	movs.w	ip, r4, lsr #21
- 80005de:	d105      	bne.n	80005ec <__adddf3+0x230>
- 80005e0:	0040      	lsls	r0, r0, #1
- 80005e2:	4149      	adcs	r1, r1
- 80005e4:	bf28      	it	cs
- 80005e6:	f041 4100 	orrcs.w	r1, r1, #2147483648	@ 0x80000000
- 80005ea:	bd30      	pop	{r4, r5, pc}
- 80005ec:	f514 0480 	adds.w	r4, r4, #4194304	@ 0x400000
- 80005f0:	bf3c      	itt	cc
- 80005f2:	f501 1180 	addcc.w	r1, r1, #1048576	@ 0x100000
- 80005f6:	bd30      	popcc	{r4, r5, pc}
- 80005f8:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
- 80005fc:	f045 41fe 	orr.w	r1, r5, #2130706432	@ 0x7f000000
- 8000600:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
- 8000604:	f04f 0000 	mov.w	r0, #0
- 8000608:	bd30      	pop	{r4, r5, pc}
- 800060a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
- 800060e:	bf1a      	itte	ne
- 8000610:	4619      	movne	r1, r3
- 8000612:	4610      	movne	r0, r2
- 8000614:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
- 8000618:	bf1c      	itt	ne
- 800061a:	460b      	movne	r3, r1
- 800061c:	4602      	movne	r2, r0
- 800061e:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
- 8000622:	bf06      	itte	eq
- 8000624:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
- 8000628:	ea91 0f03 	teqeq	r1, r3
- 800062c:	f441 2100 	orrne.w	r1, r1, #524288	@ 0x80000
- 8000630:	bd30      	pop	{r4, r5, pc}
- 8000632:	bf00      	nop
+080003e4 <__aeabi_ui2d>:
+ 80003e4:	f090 0f00 	teq	r0, #0
+ 80003e8:	bf04      	itt	eq
+ 80003ea:	2100      	moveq	r1, #0
+ 80003ec:	4770      	bxeq	lr
+ 80003ee:	b530      	push	{r4, r5, lr}
+ 80003f0:	f44f 6480 	mov.w	r4, #1024	@ 0x400
+ 80003f4:	f104 0432 	add.w	r4, r4, #50	@ 0x32
+ 80003f8:	f04f 0500 	mov.w	r5, #0
+ 80003fc:	f04f 0100 	mov.w	r1, #0
+ 8000400:	e750      	b.n	80002a4 <__adddf3+0x138>
+ 8000402:	bf00      	nop
 
-08000634 <__aeabi_ui2d>:
- 8000634:	f090 0f00 	teq	r0, #0
- 8000638:	bf04      	itt	eq
- 800063a:	2100      	moveq	r1, #0
- 800063c:	4770      	bxeq	lr
- 800063e:	b530      	push	{r4, r5, lr}
- 8000640:	f44f 6480 	mov.w	r4, #1024	@ 0x400
- 8000644:	f104 0432 	add.w	r4, r4, #50	@ 0x32
- 8000648:	f04f 0500 	mov.w	r5, #0
- 800064c:	f04f 0100 	mov.w	r1, #0
- 8000650:	e750      	b.n	80004f4 <__adddf3+0x138>
- 8000652:	bf00      	nop
+08000404 <__aeabi_i2d>:
+ 8000404:	f090 0f00 	teq	r0, #0
+ 8000408:	bf04      	itt	eq
+ 800040a:	2100      	moveq	r1, #0
+ 800040c:	4770      	bxeq	lr
+ 800040e:	b530      	push	{r4, r5, lr}
+ 8000410:	f44f 6480 	mov.w	r4, #1024	@ 0x400
+ 8000414:	f104 0432 	add.w	r4, r4, #50	@ 0x32
+ 8000418:	f010 4500 	ands.w	r5, r0, #2147483648	@ 0x80000000
+ 800041c:	bf48      	it	mi
+ 800041e:	4240      	negmi	r0, r0
+ 8000420:	f04f 0100 	mov.w	r1, #0
+ 8000424:	e73e      	b.n	80002a4 <__adddf3+0x138>
+ 8000426:	bf00      	nop
 
-08000654 <__aeabi_i2d>:
- 8000654:	f090 0f00 	teq	r0, #0
- 8000658:	bf04      	itt	eq
- 800065a:	2100      	moveq	r1, #0
- 800065c:	4770      	bxeq	lr
- 800065e:	b530      	push	{r4, r5, lr}
- 8000660:	f44f 6480 	mov.w	r4, #1024	@ 0x400
- 8000664:	f104 0432 	add.w	r4, r4, #50	@ 0x32
- 8000668:	f010 4500 	ands.w	r5, r0, #2147483648	@ 0x80000000
- 800066c:	bf48      	it	mi
- 800066e:	4240      	negmi	r0, r0
- 8000670:	f04f 0100 	mov.w	r1, #0
- 8000674:	e73e      	b.n	80004f4 <__adddf3+0x138>
- 8000676:	bf00      	nop
+08000428 <__aeabi_f2d>:
+ 8000428:	0042      	lsls	r2, r0, #1
+ 800042a:	ea4f 01e2 	mov.w	r1, r2, asr #3
+ 800042e:	ea4f 0131 	mov.w	r1, r1, rrx
+ 8000432:	ea4f 7002 	mov.w	r0, r2, lsl #28
+ 8000436:	bf1f      	itttt	ne
+ 8000438:	f012 437f 	andsne.w	r3, r2, #4278190080	@ 0xff000000
+ 800043c:	f093 4f7f 	teqne	r3, #4278190080	@ 0xff000000
+ 8000440:	f081 5160 	eorne.w	r1, r1, #939524096	@ 0x38000000
+ 8000444:	4770      	bxne	lr
+ 8000446:	f032 427f 	bics.w	r2, r2, #4278190080	@ 0xff000000
+ 800044a:	bf08      	it	eq
+ 800044c:	4770      	bxeq	lr
+ 800044e:	f093 4f7f 	teq	r3, #4278190080	@ 0xff000000
+ 8000452:	bf04      	itt	eq
+ 8000454:	f441 2100 	orreq.w	r1, r1, #524288	@ 0x80000
+ 8000458:	4770      	bxeq	lr
+ 800045a:	b530      	push	{r4, r5, lr}
+ 800045c:	f44f 7460 	mov.w	r4, #896	@ 0x380
+ 8000460:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
+ 8000464:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
+ 8000468:	e71c      	b.n	80002a4 <__adddf3+0x138>
+ 800046a:	bf00      	nop
 
-08000678 <__aeabi_f2d>:
- 8000678:	0042      	lsls	r2, r0, #1
- 800067a:	ea4f 01e2 	mov.w	r1, r2, asr #3
- 800067e:	ea4f 0131 	mov.w	r1, r1, rrx
- 8000682:	ea4f 7002 	mov.w	r0, r2, lsl #28
- 8000686:	bf1f      	itttt	ne
- 8000688:	f012 437f 	andsne.w	r3, r2, #4278190080	@ 0xff000000
- 800068c:	f093 4f7f 	teqne	r3, #4278190080	@ 0xff000000
- 8000690:	f081 5160 	eorne.w	r1, r1, #939524096	@ 0x38000000
- 8000694:	4770      	bxne	lr
- 8000696:	f032 427f 	bics.w	r2, r2, #4278190080	@ 0xff000000
- 800069a:	bf08      	it	eq
- 800069c:	4770      	bxeq	lr
- 800069e:	f093 4f7f 	teq	r3, #4278190080	@ 0xff000000
- 80006a2:	bf04      	itt	eq
- 80006a4:	f441 2100 	orreq.w	r1, r1, #524288	@ 0x80000
- 80006a8:	4770      	bxeq	lr
- 80006aa:	b530      	push	{r4, r5, lr}
- 80006ac:	f44f 7460 	mov.w	r4, #896	@ 0x380
- 80006b0:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
- 80006b4:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
- 80006b8:	e71c      	b.n	80004f4 <__adddf3+0x138>
- 80006ba:	bf00      	nop
+0800046c <__aeabi_ul2d>:
+ 800046c:	ea50 0201 	orrs.w	r2, r0, r1
+ 8000470:	bf08      	it	eq
+ 8000472:	4770      	bxeq	lr
+ 8000474:	b530      	push	{r4, r5, lr}
+ 8000476:	f04f 0500 	mov.w	r5, #0
+ 800047a:	e00a      	b.n	8000492 <__aeabi_l2d+0x16>
 
-080006bc <__aeabi_ul2d>:
- 80006bc:	ea50 0201 	orrs.w	r2, r0, r1
- 80006c0:	bf08      	it	eq
- 80006c2:	4770      	bxeq	lr
- 80006c4:	b530      	push	{r4, r5, lr}
- 80006c6:	f04f 0500 	mov.w	r5, #0
- 80006ca:	e00a      	b.n	80006e2 <__aeabi_l2d+0x16>
+0800047c <__aeabi_l2d>:
+ 800047c:	ea50 0201 	orrs.w	r2, r0, r1
+ 8000480:	bf08      	it	eq
+ 8000482:	4770      	bxeq	lr
+ 8000484:	b530      	push	{r4, r5, lr}
+ 8000486:	f011 4500 	ands.w	r5, r1, #2147483648	@ 0x80000000
+ 800048a:	d502      	bpl.n	8000492 <__aeabi_l2d+0x16>
+ 800048c:	4240      	negs	r0, r0
+ 800048e:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
+ 8000492:	f44f 6480 	mov.w	r4, #1024	@ 0x400
+ 8000496:	f104 0432 	add.w	r4, r4, #50	@ 0x32
+ 800049a:	ea5f 5c91 	movs.w	ip, r1, lsr #22
+ 800049e:	f43f aed8 	beq.w	8000252 <__adddf3+0xe6>
+ 80004a2:	f04f 0203 	mov.w	r2, #3
+ 80004a6:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
+ 80004aa:	bf18      	it	ne
+ 80004ac:	3203      	addne	r2, #3
+ 80004ae:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
+ 80004b2:	bf18      	it	ne
+ 80004b4:	3203      	addne	r2, #3
+ 80004b6:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
+ 80004ba:	f1c2 0320 	rsb	r3, r2, #32
+ 80004be:	fa00 fc03 	lsl.w	ip, r0, r3
+ 80004c2:	fa20 f002 	lsr.w	r0, r0, r2
+ 80004c6:	fa01 fe03 	lsl.w	lr, r1, r3
+ 80004ca:	ea40 000e 	orr.w	r0, r0, lr
+ 80004ce:	fa21 f102 	lsr.w	r1, r1, r2
+ 80004d2:	4414      	add	r4, r2
+ 80004d4:	e6bd      	b.n	8000252 <__adddf3+0xe6>
+ 80004d6:	bf00      	nop
 
-080006cc <__aeabi_l2d>:
- 80006cc:	ea50 0201 	orrs.w	r2, r0, r1
- 80006d0:	bf08      	it	eq
- 80006d2:	4770      	bxeq	lr
- 80006d4:	b530      	push	{r4, r5, lr}
- 80006d6:	f011 4500 	ands.w	r5, r1, #2147483648	@ 0x80000000
- 80006da:	d502      	bpl.n	80006e2 <__aeabi_l2d+0x16>
- 80006dc:	4240      	negs	r0, r0
- 80006de:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
- 80006e2:	f44f 6480 	mov.w	r4, #1024	@ 0x400
- 80006e6:	f104 0432 	add.w	r4, r4, #50	@ 0x32
- 80006ea:	ea5f 5c91 	movs.w	ip, r1, lsr #22
- 80006ee:	f43f aed8 	beq.w	80004a2 <__adddf3+0xe6>
- 80006f2:	f04f 0203 	mov.w	r2, #3
- 80006f6:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
- 80006fa:	bf18      	it	ne
- 80006fc:	3203      	addne	r2, #3
- 80006fe:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
- 8000702:	bf18      	it	ne
- 8000704:	3203      	addne	r2, #3
- 8000706:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
- 800070a:	f1c2 0320 	rsb	r3, r2, #32
- 800070e:	fa00 fc03 	lsl.w	ip, r0, r3
- 8000712:	fa20 f002 	lsr.w	r0, r0, r2
- 8000716:	fa01 fe03 	lsl.w	lr, r1, r3
- 800071a:	ea40 000e 	orr.w	r0, r0, lr
- 800071e:	fa21 f102 	lsr.w	r1, r1, r2
- 8000722:	4414      	add	r4, r2
- 8000724:	e6bd      	b.n	80004a2 <__adddf3+0xe6>
- 8000726:	bf00      	nop
+080004d8 <__aeabi_dmul>:
+ 80004d8:	b570      	push	{r4, r5, r6, lr}
+ 80004da:	f04f 0cff 	mov.w	ip, #255	@ 0xff
+ 80004de:	f44c 6ce0 	orr.w	ip, ip, #1792	@ 0x700
+ 80004e2:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
+ 80004e6:	bf1d      	ittte	ne
+ 80004e8:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
+ 80004ec:	ea94 0f0c 	teqne	r4, ip
+ 80004f0:	ea95 0f0c 	teqne	r5, ip
+ 80004f4:	f000 f8de 	bleq	80006b4 <__aeabi_dmul+0x1dc>
+ 80004f8:	442c      	add	r4, r5
+ 80004fa:	ea81 0603 	eor.w	r6, r1, r3
+ 80004fe:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
+ 8000502:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
+ 8000506:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
+ 800050a:	bf18      	it	ne
+ 800050c:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
+ 8000510:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
+ 8000514:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
+ 8000518:	d038      	beq.n	800058c <__aeabi_dmul+0xb4>
+ 800051a:	fba0 ce02 	umull	ip, lr, r0, r2
+ 800051e:	f04f 0500 	mov.w	r5, #0
+ 8000522:	fbe1 e502 	umlal	lr, r5, r1, r2
+ 8000526:	f006 4200 	and.w	r2, r6, #2147483648	@ 0x80000000
+ 800052a:	fbe0 e503 	umlal	lr, r5, r0, r3
+ 800052e:	f04f 0600 	mov.w	r6, #0
+ 8000532:	fbe1 5603 	umlal	r5, r6, r1, r3
+ 8000536:	f09c 0f00 	teq	ip, #0
+ 800053a:	bf18      	it	ne
+ 800053c:	f04e 0e01 	orrne.w	lr, lr, #1
+ 8000540:	f1a4 04ff 	sub.w	r4, r4, #255	@ 0xff
+ 8000544:	f5b6 7f00 	cmp.w	r6, #512	@ 0x200
+ 8000548:	f564 7440 	sbc.w	r4, r4, #768	@ 0x300
+ 800054c:	d204      	bcs.n	8000558 <__aeabi_dmul+0x80>
+ 800054e:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
+ 8000552:	416d      	adcs	r5, r5
+ 8000554:	eb46 0606 	adc.w	r6, r6, r6
+ 8000558:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
+ 800055c:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
+ 8000560:	ea4f 20c5 	mov.w	r0, r5, lsl #11
+ 8000564:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
+ 8000568:	ea4f 2ece 	mov.w	lr, lr, lsl #11
+ 800056c:	f1b4 0cfd 	subs.w	ip, r4, #253	@ 0xfd
+ 8000570:	bf88      	it	hi
+ 8000572:	f5bc 6fe0 	cmphi.w	ip, #1792	@ 0x700
+ 8000576:	d81e      	bhi.n	80005b6 <__aeabi_dmul+0xde>
+ 8000578:	f1be 4f00 	cmp.w	lr, #2147483648	@ 0x80000000
+ 800057c:	bf08      	it	eq
+ 800057e:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
+ 8000582:	f150 0000 	adcs.w	r0, r0, #0
+ 8000586:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
+ 800058a:	bd70      	pop	{r4, r5, r6, pc}
+ 800058c:	f006 4600 	and.w	r6, r6, #2147483648	@ 0x80000000
+ 8000590:	ea46 0101 	orr.w	r1, r6, r1
+ 8000594:	ea40 0002 	orr.w	r0, r0, r2
+ 8000598:	ea81 0103 	eor.w	r1, r1, r3
+ 800059c:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
+ 80005a0:	bfc2      	ittt	gt
+ 80005a2:	ebd4 050c 	rsbsgt	r5, r4, ip
+ 80005a6:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
+ 80005aa:	bd70      	popgt	{r4, r5, r6, pc}
+ 80005ac:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
+ 80005b0:	f04f 0e00 	mov.w	lr, #0
+ 80005b4:	3c01      	subs	r4, #1
+ 80005b6:	f300 80ab 	bgt.w	8000710 <__aeabi_dmul+0x238>
+ 80005ba:	f114 0f36 	cmn.w	r4, #54	@ 0x36
+ 80005be:	bfde      	ittt	le
+ 80005c0:	2000      	movle	r0, #0
+ 80005c2:	f001 4100 	andle.w	r1, r1, #2147483648	@ 0x80000000
+ 80005c6:	bd70      	pople	{r4, r5, r6, pc}
+ 80005c8:	f1c4 0400 	rsb	r4, r4, #0
+ 80005cc:	3c20      	subs	r4, #32
+ 80005ce:	da35      	bge.n	800063c <__aeabi_dmul+0x164>
+ 80005d0:	340c      	adds	r4, #12
+ 80005d2:	dc1b      	bgt.n	800060c <__aeabi_dmul+0x134>
+ 80005d4:	f104 0414 	add.w	r4, r4, #20
+ 80005d8:	f1c4 0520 	rsb	r5, r4, #32
+ 80005dc:	fa00 f305 	lsl.w	r3, r0, r5
+ 80005e0:	fa20 f004 	lsr.w	r0, r0, r4
+ 80005e4:	fa01 f205 	lsl.w	r2, r1, r5
+ 80005e8:	ea40 0002 	orr.w	r0, r0, r2
+ 80005ec:	f001 4200 	and.w	r2, r1, #2147483648	@ 0x80000000
+ 80005f0:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
+ 80005f4:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
+ 80005f8:	fa21 f604 	lsr.w	r6, r1, r4
+ 80005fc:	eb42 0106 	adc.w	r1, r2, r6
+ 8000600:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
+ 8000604:	bf08      	it	eq
+ 8000606:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
+ 800060a:	bd70      	pop	{r4, r5, r6, pc}
+ 800060c:	f1c4 040c 	rsb	r4, r4, #12
+ 8000610:	f1c4 0520 	rsb	r5, r4, #32
+ 8000614:	fa00 f304 	lsl.w	r3, r0, r4
+ 8000618:	fa20 f005 	lsr.w	r0, r0, r5
+ 800061c:	fa01 f204 	lsl.w	r2, r1, r4
+ 8000620:	ea40 0002 	orr.w	r0, r0, r2
+ 8000624:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
+ 8000628:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
+ 800062c:	f141 0100 	adc.w	r1, r1, #0
+ 8000630:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
+ 8000634:	bf08      	it	eq
+ 8000636:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
+ 800063a:	bd70      	pop	{r4, r5, r6, pc}
+ 800063c:	f1c4 0520 	rsb	r5, r4, #32
+ 8000640:	fa00 f205 	lsl.w	r2, r0, r5
+ 8000644:	ea4e 0e02 	orr.w	lr, lr, r2
+ 8000648:	fa20 f304 	lsr.w	r3, r0, r4
+ 800064c:	fa01 f205 	lsl.w	r2, r1, r5
+ 8000650:	ea43 0302 	orr.w	r3, r3, r2
+ 8000654:	fa21 f004 	lsr.w	r0, r1, r4
+ 8000658:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
+ 800065c:	fa21 f204 	lsr.w	r2, r1, r4
+ 8000660:	ea20 0002 	bic.w	r0, r0, r2
+ 8000664:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
+ 8000668:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
+ 800066c:	bf08      	it	eq
+ 800066e:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
+ 8000672:	bd70      	pop	{r4, r5, r6, pc}
+ 8000674:	f094 0f00 	teq	r4, #0
+ 8000678:	d10f      	bne.n	800069a <__aeabi_dmul+0x1c2>
+ 800067a:	f001 4600 	and.w	r6, r1, #2147483648	@ 0x80000000
+ 800067e:	0040      	lsls	r0, r0, #1
+ 8000680:	eb41 0101 	adc.w	r1, r1, r1
+ 8000684:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
+ 8000688:	bf08      	it	eq
+ 800068a:	3c01      	subeq	r4, #1
+ 800068c:	d0f7      	beq.n	800067e <__aeabi_dmul+0x1a6>
+ 800068e:	ea41 0106 	orr.w	r1, r1, r6
+ 8000692:	f095 0f00 	teq	r5, #0
+ 8000696:	bf18      	it	ne
+ 8000698:	4770      	bxne	lr
+ 800069a:	f003 4600 	and.w	r6, r3, #2147483648	@ 0x80000000
+ 800069e:	0052      	lsls	r2, r2, #1
+ 80006a0:	eb43 0303 	adc.w	r3, r3, r3
+ 80006a4:	f413 1f80 	tst.w	r3, #1048576	@ 0x100000
+ 80006a8:	bf08      	it	eq
+ 80006aa:	3d01      	subeq	r5, #1
+ 80006ac:	d0f7      	beq.n	800069e <__aeabi_dmul+0x1c6>
+ 80006ae:	ea43 0306 	orr.w	r3, r3, r6
+ 80006b2:	4770      	bx	lr
+ 80006b4:	ea94 0f0c 	teq	r4, ip
+ 80006b8:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
+ 80006bc:	bf18      	it	ne
+ 80006be:	ea95 0f0c 	teqne	r5, ip
+ 80006c2:	d00c      	beq.n	80006de <__aeabi_dmul+0x206>
+ 80006c4:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
+ 80006c8:	bf18      	it	ne
+ 80006ca:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
+ 80006ce:	d1d1      	bne.n	8000674 <__aeabi_dmul+0x19c>
+ 80006d0:	ea81 0103 	eor.w	r1, r1, r3
+ 80006d4:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
+ 80006d8:	f04f 0000 	mov.w	r0, #0
+ 80006dc:	bd70      	pop	{r4, r5, r6, pc}
+ 80006de:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
+ 80006e2:	bf06      	itte	eq
+ 80006e4:	4610      	moveq	r0, r2
+ 80006e6:	4619      	moveq	r1, r3
+ 80006e8:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
+ 80006ec:	d019      	beq.n	8000722 <__aeabi_dmul+0x24a>
+ 80006ee:	ea94 0f0c 	teq	r4, ip
+ 80006f2:	d102      	bne.n	80006fa <__aeabi_dmul+0x222>
+ 80006f4:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
+ 80006f8:	d113      	bne.n	8000722 <__aeabi_dmul+0x24a>
+ 80006fa:	ea95 0f0c 	teq	r5, ip
+ 80006fe:	d105      	bne.n	800070c <__aeabi_dmul+0x234>
+ 8000700:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
+ 8000704:	bf1c      	itt	ne
+ 8000706:	4610      	movne	r0, r2
+ 8000708:	4619      	movne	r1, r3
+ 800070a:	d10a      	bne.n	8000722 <__aeabi_dmul+0x24a>
+ 800070c:	ea81 0103 	eor.w	r1, r1, r3
+ 8000710:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
+ 8000714:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
+ 8000718:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
+ 800071c:	f04f 0000 	mov.w	r0, #0
+ 8000720:	bd70      	pop	{r4, r5, r6, pc}
+ 8000722:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
+ 8000726:	f441 0178 	orr.w	r1, r1, #16252928	@ 0xf80000
+ 800072a:	bd70      	pop	{r4, r5, r6, pc}
 
-08000728 <__aeabi_d2iz>:
- 8000728:	ea4f 0241 	mov.w	r2, r1, lsl #1
- 800072c:	f512 1200 	adds.w	r2, r2, #2097152	@ 0x200000
- 8000730:	d215      	bcs.n	800075e <__aeabi_d2iz+0x36>
- 8000732:	d511      	bpl.n	8000758 <__aeabi_d2iz+0x30>
- 8000734:	f46f 7378 	mvn.w	r3, #992	@ 0x3e0
- 8000738:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
- 800073c:	d912      	bls.n	8000764 <__aeabi_d2iz+0x3c>
- 800073e:	ea4f 23c1 	mov.w	r3, r1, lsl #11
- 8000742:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
- 8000746:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
- 800074a:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
- 800074e:	fa23 f002 	lsr.w	r0, r3, r2
- 8000752:	bf18      	it	ne
- 8000754:	4240      	negne	r0, r0
- 8000756:	4770      	bx	lr
- 8000758:	f04f 0000 	mov.w	r0, #0
- 800075c:	4770      	bx	lr
- 800075e:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
- 8000762:	d105      	bne.n	8000770 <__aeabi_d2iz+0x48>
- 8000764:	f011 4000 	ands.w	r0, r1, #2147483648	@ 0x80000000
- 8000768:	bf08      	it	eq
- 800076a:	f06f 4000 	mvneq.w	r0, #2147483648	@ 0x80000000
- 800076e:	4770      	bx	lr
- 8000770:	f04f 0000 	mov.w	r0, #0
- 8000774:	4770      	bx	lr
- 8000776:	bf00      	nop
+0800072c <__aeabi_ddiv>:
+ 800072c:	b570      	push	{r4, r5, r6, lr}
+ 800072e:	f04f 0cff 	mov.w	ip, #255	@ 0xff
+ 8000732:	f44c 6ce0 	orr.w	ip, ip, #1792	@ 0x700
+ 8000736:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
+ 800073a:	bf1d      	ittte	ne
+ 800073c:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
+ 8000740:	ea94 0f0c 	teqne	r4, ip
+ 8000744:	ea95 0f0c 	teqne	r5, ip
+ 8000748:	f000 f8a7 	bleq	800089a <__aeabi_ddiv+0x16e>
+ 800074c:	eba4 0405 	sub.w	r4, r4, r5
+ 8000750:	ea81 0e03 	eor.w	lr, r1, r3
+ 8000754:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
+ 8000758:	ea4f 3101 	mov.w	r1, r1, lsl #12
+ 800075c:	f000 8088 	beq.w	8000870 <__aeabi_ddiv+0x144>
+ 8000760:	ea4f 3303 	mov.w	r3, r3, lsl #12
+ 8000764:	f04f 5580 	mov.w	r5, #268435456	@ 0x10000000
+ 8000768:	ea45 1313 	orr.w	r3, r5, r3, lsr #4
+ 800076c:	ea43 6312 	orr.w	r3, r3, r2, lsr #24
+ 8000770:	ea4f 2202 	mov.w	r2, r2, lsl #8
+ 8000774:	ea45 1511 	orr.w	r5, r5, r1, lsr #4
+ 8000778:	ea45 6510 	orr.w	r5, r5, r0, lsr #24
+ 800077c:	ea4f 2600 	mov.w	r6, r0, lsl #8
+ 8000780:	f00e 4100 	and.w	r1, lr, #2147483648	@ 0x80000000
+ 8000784:	429d      	cmp	r5, r3
+ 8000786:	bf08      	it	eq
+ 8000788:	4296      	cmpeq	r6, r2
+ 800078a:	f144 04fd 	adc.w	r4, r4, #253	@ 0xfd
+ 800078e:	f504 7440 	add.w	r4, r4, #768	@ 0x300
+ 8000792:	d202      	bcs.n	800079a <__aeabi_ddiv+0x6e>
+ 8000794:	085b      	lsrs	r3, r3, #1
+ 8000796:	ea4f 0232 	mov.w	r2, r2, rrx
+ 800079a:	1ab6      	subs	r6, r6, r2
+ 800079c:	eb65 0503 	sbc.w	r5, r5, r3
+ 80007a0:	085b      	lsrs	r3, r3, #1
+ 80007a2:	ea4f 0232 	mov.w	r2, r2, rrx
+ 80007a6:	f44f 1080 	mov.w	r0, #1048576	@ 0x100000
+ 80007aa:	f44f 2c00 	mov.w	ip, #524288	@ 0x80000
+ 80007ae:	ebb6 0e02 	subs.w	lr, r6, r2
+ 80007b2:	eb75 0e03 	sbcs.w	lr, r5, r3
+ 80007b6:	bf22      	ittt	cs
+ 80007b8:	1ab6      	subcs	r6, r6, r2
+ 80007ba:	4675      	movcs	r5, lr
+ 80007bc:	ea40 000c 	orrcs.w	r0, r0, ip
+ 80007c0:	085b      	lsrs	r3, r3, #1
+ 80007c2:	ea4f 0232 	mov.w	r2, r2, rrx
+ 80007c6:	ebb6 0e02 	subs.w	lr, r6, r2
+ 80007ca:	eb75 0e03 	sbcs.w	lr, r5, r3
+ 80007ce:	bf22      	ittt	cs
+ 80007d0:	1ab6      	subcs	r6, r6, r2
+ 80007d2:	4675      	movcs	r5, lr
+ 80007d4:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
+ 80007d8:	085b      	lsrs	r3, r3, #1
+ 80007da:	ea4f 0232 	mov.w	r2, r2, rrx
+ 80007de:	ebb6 0e02 	subs.w	lr, r6, r2
+ 80007e2:	eb75 0e03 	sbcs.w	lr, r5, r3
+ 80007e6:	bf22      	ittt	cs
+ 80007e8:	1ab6      	subcs	r6, r6, r2
+ 80007ea:	4675      	movcs	r5, lr
+ 80007ec:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
+ 80007f0:	085b      	lsrs	r3, r3, #1
+ 80007f2:	ea4f 0232 	mov.w	r2, r2, rrx
+ 80007f6:	ebb6 0e02 	subs.w	lr, r6, r2
+ 80007fa:	eb75 0e03 	sbcs.w	lr, r5, r3
+ 80007fe:	bf22      	ittt	cs
+ 8000800:	1ab6      	subcs	r6, r6, r2
+ 8000802:	4675      	movcs	r5, lr
+ 8000804:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
+ 8000808:	ea55 0e06 	orrs.w	lr, r5, r6
+ 800080c:	d018      	beq.n	8000840 <__aeabi_ddiv+0x114>
+ 800080e:	ea4f 1505 	mov.w	r5, r5, lsl #4
+ 8000812:	ea45 7516 	orr.w	r5, r5, r6, lsr #28
+ 8000816:	ea4f 1606 	mov.w	r6, r6, lsl #4
+ 800081a:	ea4f 03c3 	mov.w	r3, r3, lsl #3
+ 800081e:	ea43 7352 	orr.w	r3, r3, r2, lsr #29
+ 8000822:	ea4f 02c2 	mov.w	r2, r2, lsl #3
+ 8000826:	ea5f 1c1c 	movs.w	ip, ip, lsr #4
+ 800082a:	d1c0      	bne.n	80007ae <__aeabi_ddiv+0x82>
+ 800082c:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
+ 8000830:	d10b      	bne.n	800084a <__aeabi_ddiv+0x11e>
+ 8000832:	ea41 0100 	orr.w	r1, r1, r0
+ 8000836:	f04f 0000 	mov.w	r0, #0
+ 800083a:	f04f 4c00 	mov.w	ip, #2147483648	@ 0x80000000
+ 800083e:	e7b6      	b.n	80007ae <__aeabi_ddiv+0x82>
+ 8000840:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
+ 8000844:	bf04      	itt	eq
+ 8000846:	4301      	orreq	r1, r0
+ 8000848:	2000      	moveq	r0, #0
+ 800084a:	f1b4 0cfd 	subs.w	ip, r4, #253	@ 0xfd
+ 800084e:	bf88      	it	hi
+ 8000850:	f5bc 6fe0 	cmphi.w	ip, #1792	@ 0x700
+ 8000854:	f63f aeaf 	bhi.w	80005b6 <__aeabi_dmul+0xde>
+ 8000858:	ebb5 0c03 	subs.w	ip, r5, r3
+ 800085c:	bf04      	itt	eq
+ 800085e:	ebb6 0c02 	subseq.w	ip, r6, r2
+ 8000862:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
+ 8000866:	f150 0000 	adcs.w	r0, r0, #0
+ 800086a:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
+ 800086e:	bd70      	pop	{r4, r5, r6, pc}
+ 8000870:	f00e 4e00 	and.w	lr, lr, #2147483648	@ 0x80000000
+ 8000874:	ea4e 3111 	orr.w	r1, lr, r1, lsr #12
+ 8000878:	eb14 045c 	adds.w	r4, r4, ip, lsr #1
+ 800087c:	bfc2      	ittt	gt
+ 800087e:	ebd4 050c 	rsbsgt	r5, r4, ip
+ 8000882:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
+ 8000886:	bd70      	popgt	{r4, r5, r6, pc}
+ 8000888:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
+ 800088c:	f04f 0e00 	mov.w	lr, #0
+ 8000890:	3c01      	subs	r4, #1
+ 8000892:	e690      	b.n	80005b6 <__aeabi_dmul+0xde>
+ 8000894:	ea45 0e06 	orr.w	lr, r5, r6
+ 8000898:	e68d      	b.n	80005b6 <__aeabi_dmul+0xde>
+ 800089a:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
+ 800089e:	ea94 0f0c 	teq	r4, ip
+ 80008a2:	bf08      	it	eq
+ 80008a4:	ea95 0f0c 	teqeq	r5, ip
+ 80008a8:	f43f af3b 	beq.w	8000722 <__aeabi_dmul+0x24a>
+ 80008ac:	ea94 0f0c 	teq	r4, ip
+ 80008b0:	d10a      	bne.n	80008c8 <__aeabi_ddiv+0x19c>
+ 80008b2:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
+ 80008b6:	f47f af34 	bne.w	8000722 <__aeabi_dmul+0x24a>
+ 80008ba:	ea95 0f0c 	teq	r5, ip
+ 80008be:	f47f af25 	bne.w	800070c <__aeabi_dmul+0x234>
+ 80008c2:	4610      	mov	r0, r2
+ 80008c4:	4619      	mov	r1, r3
+ 80008c6:	e72c      	b.n	8000722 <__aeabi_dmul+0x24a>
+ 80008c8:	ea95 0f0c 	teq	r5, ip
+ 80008cc:	d106      	bne.n	80008dc <__aeabi_ddiv+0x1b0>
+ 80008ce:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
+ 80008d2:	f43f aefd 	beq.w	80006d0 <__aeabi_dmul+0x1f8>
+ 80008d6:	4610      	mov	r0, r2
+ 80008d8:	4619      	mov	r1, r3
+ 80008da:	e722      	b.n	8000722 <__aeabi_dmul+0x24a>
+ 80008dc:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
+ 80008e0:	bf18      	it	ne
+ 80008e2:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
+ 80008e6:	f47f aec5 	bne.w	8000674 <__aeabi_dmul+0x19c>
+ 80008ea:	ea50 0441 	orrs.w	r4, r0, r1, lsl #1
+ 80008ee:	f47f af0d 	bne.w	800070c <__aeabi_dmul+0x234>
+ 80008f2:	ea52 0543 	orrs.w	r5, r2, r3, lsl #1
+ 80008f6:	f47f aeeb 	bne.w	80006d0 <__aeabi_dmul+0x1f8>
+ 80008fa:	e712      	b.n	8000722 <__aeabi_dmul+0x24a>
 
-08000778 <__aeabi_frsub>:
- 8000778:	f080 4000 	eor.w	r0, r0, #2147483648	@ 0x80000000
- 800077c:	e002      	b.n	8000784 <__addsf3>
- 800077e:	bf00      	nop
+080008fc <__gedf2>:
+ 80008fc:	f04f 3cff 	mov.w	ip, #4294967295
+ 8000900:	e006      	b.n	8000910 <__cmpdf2+0x4>
+ 8000902:	bf00      	nop
 
-08000780 <__aeabi_fsub>:
- 8000780:	f081 4100 	eor.w	r1, r1, #2147483648	@ 0x80000000
+08000904 <__ledf2>:
+ 8000904:	f04f 0c01 	mov.w	ip, #1
+ 8000908:	e002      	b.n	8000910 <__cmpdf2+0x4>
+ 800090a:	bf00      	nop
 
-08000784 <__addsf3>:
- 8000784:	0042      	lsls	r2, r0, #1
- 8000786:	bf1f      	itttt	ne
- 8000788:	ea5f 0341 	movsne.w	r3, r1, lsl #1
- 800078c:	ea92 0f03 	teqne	r2, r3
- 8000790:	ea7f 6c22 	mvnsne.w	ip, r2, asr #24
- 8000794:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
- 8000798:	d06a      	beq.n	8000870 <__addsf3+0xec>
- 800079a:	ea4f 6212 	mov.w	r2, r2, lsr #24
- 800079e:	ebd2 6313 	rsbs	r3, r2, r3, lsr #24
- 80007a2:	bfc1      	itttt	gt
- 80007a4:	18d2      	addgt	r2, r2, r3
- 80007a6:	4041      	eorgt	r1, r0
- 80007a8:	4048      	eorgt	r0, r1
- 80007aa:	4041      	eorgt	r1, r0
- 80007ac:	bfb8      	it	lt
- 80007ae:	425b      	neglt	r3, r3
- 80007b0:	2b19      	cmp	r3, #25
- 80007b2:	bf88      	it	hi
- 80007b4:	4770      	bxhi	lr
- 80007b6:	f010 4f00 	tst.w	r0, #2147483648	@ 0x80000000
- 80007ba:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
- 80007be:	f020 407f 	bic.w	r0, r0, #4278190080	@ 0xff000000
- 80007c2:	bf18      	it	ne
- 80007c4:	4240      	negne	r0, r0
- 80007c6:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
- 80007ca:	f441 0100 	orr.w	r1, r1, #8388608	@ 0x800000
- 80007ce:	f021 417f 	bic.w	r1, r1, #4278190080	@ 0xff000000
- 80007d2:	bf18      	it	ne
- 80007d4:	4249      	negne	r1, r1
- 80007d6:	ea92 0f03 	teq	r2, r3
- 80007da:	d03f      	beq.n	800085c <__addsf3+0xd8>
- 80007dc:	f1a2 0201 	sub.w	r2, r2, #1
- 80007e0:	fa41 fc03 	asr.w	ip, r1, r3
- 80007e4:	eb10 000c 	adds.w	r0, r0, ip
- 80007e8:	f1c3 0320 	rsb	r3, r3, #32
- 80007ec:	fa01 f103 	lsl.w	r1, r1, r3
- 80007f0:	f000 4300 	and.w	r3, r0, #2147483648	@ 0x80000000
- 80007f4:	d502      	bpl.n	80007fc <__addsf3+0x78>
- 80007f6:	4249      	negs	r1, r1
- 80007f8:	eb60 0040 	sbc.w	r0, r0, r0, lsl #1
- 80007fc:	f5b0 0f00 	cmp.w	r0, #8388608	@ 0x800000
- 8000800:	d313      	bcc.n	800082a <__addsf3+0xa6>
- 8000802:	f1b0 7f80 	cmp.w	r0, #16777216	@ 0x1000000
- 8000806:	d306      	bcc.n	8000816 <__addsf3+0x92>
- 8000808:	0840      	lsrs	r0, r0, #1
- 800080a:	ea4f 0131 	mov.w	r1, r1, rrx
- 800080e:	f102 0201 	add.w	r2, r2, #1
- 8000812:	2afe      	cmp	r2, #254	@ 0xfe
- 8000814:	d251      	bcs.n	80008ba <__addsf3+0x136>
- 8000816:	f1b1 4f00 	cmp.w	r1, #2147483648	@ 0x80000000
- 800081a:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
- 800081e:	bf08      	it	eq
- 8000820:	f020 0001 	biceq.w	r0, r0, #1
- 8000824:	ea40 0003 	orr.w	r0, r0, r3
- 8000828:	4770      	bx	lr
- 800082a:	0049      	lsls	r1, r1, #1
- 800082c:	eb40 0000 	adc.w	r0, r0, r0
- 8000830:	3a01      	subs	r2, #1
- 8000832:	bf28      	it	cs
- 8000834:	f5b0 0f00 	cmpcs.w	r0, #8388608	@ 0x800000
- 8000838:	d2ed      	bcs.n	8000816 <__addsf3+0x92>
- 800083a:	fab0 fc80 	clz	ip, r0
- 800083e:	f1ac 0c08 	sub.w	ip, ip, #8
- 8000842:	ebb2 020c 	subs.w	r2, r2, ip
- 8000846:	fa00 f00c 	lsl.w	r0, r0, ip
- 800084a:	bfaa      	itet	ge
- 800084c:	eb00 50c2 	addge.w	r0, r0, r2, lsl #23
- 8000850:	4252      	neglt	r2, r2
- 8000852:	4318      	orrge	r0, r3
- 8000854:	bfbc      	itt	lt
- 8000856:	40d0      	lsrlt	r0, r2
- 8000858:	4318      	orrlt	r0, r3
- 800085a:	4770      	bx	lr
- 800085c:	f092 0f00 	teq	r2, #0
- 8000860:	f481 0100 	eor.w	r1, r1, #8388608	@ 0x800000
- 8000864:	bf06      	itte	eq
- 8000866:	f480 0000 	eoreq.w	r0, r0, #8388608	@ 0x800000
- 800086a:	3201      	addeq	r2, #1
- 800086c:	3b01      	subne	r3, #1
- 800086e:	e7b5      	b.n	80007dc <__addsf3+0x58>
- 8000870:	ea4f 0341 	mov.w	r3, r1, lsl #1
- 8000874:	ea7f 6c22 	mvns.w	ip, r2, asr #24
- 8000878:	bf18      	it	ne
- 800087a:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
- 800087e:	d021      	beq.n	80008c4 <__addsf3+0x140>
- 8000880:	ea92 0f03 	teq	r2, r3
- 8000884:	d004      	beq.n	8000890 <__addsf3+0x10c>
- 8000886:	f092 0f00 	teq	r2, #0
- 800088a:	bf08      	it	eq
- 800088c:	4608      	moveq	r0, r1
- 800088e:	4770      	bx	lr
- 8000890:	ea90 0f01 	teq	r0, r1
- 8000894:	bf1c      	itt	ne
- 8000896:	2000      	movne	r0, #0
- 8000898:	4770      	bxne	lr
- 800089a:	f012 4f7f 	tst.w	r2, #4278190080	@ 0xff000000
- 800089e:	d104      	bne.n	80008aa <__addsf3+0x126>
- 80008a0:	0040      	lsls	r0, r0, #1
- 80008a2:	bf28      	it	cs
- 80008a4:	f040 4000 	orrcs.w	r0, r0, #2147483648	@ 0x80000000
- 80008a8:	4770      	bx	lr
- 80008aa:	f112 7200 	adds.w	r2, r2, #33554432	@ 0x2000000
- 80008ae:	bf3c      	itt	cc
- 80008b0:	f500 0000 	addcc.w	r0, r0, #8388608	@ 0x800000
- 80008b4:	4770      	bxcc	lr
- 80008b6:	f000 4300 	and.w	r3, r0, #2147483648	@ 0x80000000
- 80008ba:	f043 40fe 	orr.w	r0, r3, #2130706432	@ 0x7f000000
- 80008be:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
- 80008c2:	4770      	bx	lr
- 80008c4:	ea7f 6222 	mvns.w	r2, r2, asr #24
- 80008c8:	bf16      	itet	ne
- 80008ca:	4608      	movne	r0, r1
- 80008cc:	ea7f 6323 	mvnseq.w	r3, r3, asr #24
- 80008d0:	4601      	movne	r1, r0
- 80008d2:	0242      	lsls	r2, r0, #9
- 80008d4:	bf06      	itte	eq
- 80008d6:	ea5f 2341 	movseq.w	r3, r1, lsl #9
- 80008da:	ea90 0f01 	teqeq	r0, r1
- 80008de:	f440 0080 	orrne.w	r0, r0, #4194304	@ 0x400000
- 80008e2:	4770      	bx	lr
+0800090c <__cmpdf2>:
+ 800090c:	f04f 0c01 	mov.w	ip, #1
+ 8000910:	f84d cd04 	str.w	ip, [sp, #-4]!
+ 8000914:	ea4f 0c41 	mov.w	ip, r1, lsl #1
+ 8000918:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
+ 800091c:	ea4f 0c43 	mov.w	ip, r3, lsl #1
+ 8000920:	bf18      	it	ne
+ 8000922:	ea7f 5c6c 	mvnsne.w	ip, ip, asr #21
+ 8000926:	d01b      	beq.n	8000960 <__cmpdf2+0x54>
+ 8000928:	b001      	add	sp, #4
+ 800092a:	ea50 0c41 	orrs.w	ip, r0, r1, lsl #1
+ 800092e:	bf0c      	ite	eq
+ 8000930:	ea52 0c43 	orrseq.w	ip, r2, r3, lsl #1
+ 8000934:	ea91 0f03 	teqne	r1, r3
+ 8000938:	bf02      	ittt	eq
+ 800093a:	ea90 0f02 	teqeq	r0, r2
+ 800093e:	2000      	moveq	r0, #0
+ 8000940:	4770      	bxeq	lr
+ 8000942:	f110 0f00 	cmn.w	r0, #0
+ 8000946:	ea91 0f03 	teq	r1, r3
+ 800094a:	bf58      	it	pl
+ 800094c:	4299      	cmppl	r1, r3
+ 800094e:	bf08      	it	eq
+ 8000950:	4290      	cmpeq	r0, r2
+ 8000952:	bf2c      	ite	cs
+ 8000954:	17d8      	asrcs	r0, r3, #31
+ 8000956:	ea6f 70e3 	mvncc.w	r0, r3, asr #31
+ 800095a:	f040 0001 	orr.w	r0, r0, #1
+ 800095e:	4770      	bx	lr
+ 8000960:	ea4f 0c41 	mov.w	ip, r1, lsl #1
+ 8000964:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
+ 8000968:	d102      	bne.n	8000970 <__cmpdf2+0x64>
+ 800096a:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
+ 800096e:	d107      	bne.n	8000980 <__cmpdf2+0x74>
+ 8000970:	ea4f 0c43 	mov.w	ip, r3, lsl #1
+ 8000974:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
+ 8000978:	d1d6      	bne.n	8000928 <__cmpdf2+0x1c>
+ 800097a:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
+ 800097e:	d0d3      	beq.n	8000928 <__cmpdf2+0x1c>
+ 8000980:	f85d 0b04 	ldr.w	r0, [sp], #4
+ 8000984:	4770      	bx	lr
+ 8000986:	bf00      	nop
 
-080008e4 <__aeabi_ui2f>:
- 80008e4:	f04f 0300 	mov.w	r3, #0
- 80008e8:	e004      	b.n	80008f4 <__aeabi_i2f+0x8>
- 80008ea:	bf00      	nop
+08000988 <__aeabi_cdrcmple>:
+ 8000988:	4684      	mov	ip, r0
+ 800098a:	4610      	mov	r0, r2
+ 800098c:	4662      	mov	r2, ip
+ 800098e:	468c      	mov	ip, r1
+ 8000990:	4619      	mov	r1, r3
+ 8000992:	4663      	mov	r3, ip
+ 8000994:	e000      	b.n	8000998 <__aeabi_cdcmpeq>
+ 8000996:	bf00      	nop
 
-080008ec <__aeabi_i2f>:
- 80008ec:	f010 4300 	ands.w	r3, r0, #2147483648	@ 0x80000000
- 80008f0:	bf48      	it	mi
- 80008f2:	4240      	negmi	r0, r0
- 80008f4:	ea5f 0c00 	movs.w	ip, r0
- 80008f8:	bf08      	it	eq
- 80008fa:	4770      	bxeq	lr
- 80008fc:	f043 4396 	orr.w	r3, r3, #1258291200	@ 0x4b000000
- 8000900:	4601      	mov	r1, r0
- 8000902:	f04f 0000 	mov.w	r0, #0
- 8000906:	e01c      	b.n	8000942 <__aeabi_l2f+0x2a>
+08000998 <__aeabi_cdcmpeq>:
+ 8000998:	b501      	push	{r0, lr}
+ 800099a:	f7ff ffb7 	bl	800090c <__cmpdf2>
+ 800099e:	2800      	cmp	r0, #0
+ 80009a0:	bf48      	it	mi
+ 80009a2:	f110 0f00 	cmnmi.w	r0, #0
+ 80009a6:	bd01      	pop	{r0, pc}
 
-08000908 <__aeabi_ul2f>:
- 8000908:	ea50 0201 	orrs.w	r2, r0, r1
- 800090c:	bf08      	it	eq
- 800090e:	4770      	bxeq	lr
- 8000910:	f04f 0300 	mov.w	r3, #0
- 8000914:	e00a      	b.n	800092c <__aeabi_l2f+0x14>
- 8000916:	bf00      	nop
+080009a8 <__aeabi_dcmpeq>:
+ 80009a8:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 80009ac:	f7ff fff4 	bl	8000998 <__aeabi_cdcmpeq>
+ 80009b0:	bf0c      	ite	eq
+ 80009b2:	2001      	moveq	r0, #1
+ 80009b4:	2000      	movne	r0, #0
+ 80009b6:	f85d fb08 	ldr.w	pc, [sp], #8
+ 80009ba:	bf00      	nop
 
-08000918 <__aeabi_l2f>:
- 8000918:	ea50 0201 	orrs.w	r2, r0, r1
- 800091c:	bf08      	it	eq
- 800091e:	4770      	bxeq	lr
- 8000920:	f011 4300 	ands.w	r3, r1, #2147483648	@ 0x80000000
- 8000924:	d502      	bpl.n	800092c <__aeabi_l2f+0x14>
- 8000926:	4240      	negs	r0, r0
- 8000928:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
- 800092c:	ea5f 0c01 	movs.w	ip, r1
- 8000930:	bf02      	ittt	eq
- 8000932:	4684      	moveq	ip, r0
- 8000934:	4601      	moveq	r1, r0
- 8000936:	2000      	moveq	r0, #0
- 8000938:	f043 43b6 	orr.w	r3, r3, #1526726656	@ 0x5b000000
- 800093c:	bf08      	it	eq
- 800093e:	f1a3 5380 	subeq.w	r3, r3, #268435456	@ 0x10000000
- 8000942:	f5a3 0300 	sub.w	r3, r3, #8388608	@ 0x800000
- 8000946:	fabc f28c 	clz	r2, ip
- 800094a:	3a08      	subs	r2, #8
- 800094c:	eba3 53c2 	sub.w	r3, r3, r2, lsl #23
- 8000950:	db10      	blt.n	8000974 <__aeabi_l2f+0x5c>
- 8000952:	fa01 fc02 	lsl.w	ip, r1, r2
- 8000956:	4463      	add	r3, ip
- 8000958:	fa00 fc02 	lsl.w	ip, r0, r2
- 800095c:	f1c2 0220 	rsb	r2, r2, #32
- 8000960:	f1bc 4f00 	cmp.w	ip, #2147483648	@ 0x80000000
- 8000964:	fa20 f202 	lsr.w	r2, r0, r2
- 8000968:	eb43 0002 	adc.w	r0, r3, r2
- 800096c:	bf08      	it	eq
- 800096e:	f020 0001 	biceq.w	r0, r0, #1
- 8000972:	4770      	bx	lr
- 8000974:	f102 0220 	add.w	r2, r2, #32
- 8000978:	fa01 fc02 	lsl.w	ip, r1, r2
- 800097c:	f1c2 0220 	rsb	r2, r2, #32
- 8000980:	ea50 004c 	orrs.w	r0, r0, ip, lsl #1
- 8000984:	fa21 f202 	lsr.w	r2, r1, r2
- 8000988:	eb43 0002 	adc.w	r0, r3, r2
- 800098c:	bf08      	it	eq
- 800098e:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
- 8000992:	4770      	bx	lr
+080009bc <__aeabi_dcmplt>:
+ 80009bc:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 80009c0:	f7ff ffea 	bl	8000998 <__aeabi_cdcmpeq>
+ 80009c4:	bf34      	ite	cc
+ 80009c6:	2001      	movcc	r0, #1
+ 80009c8:	2000      	movcs	r0, #0
+ 80009ca:	f85d fb08 	ldr.w	pc, [sp], #8
+ 80009ce:	bf00      	nop
 
-08000994 <__aeabi_fmul>:
- 8000994:	f04f 0cff 	mov.w	ip, #255	@ 0xff
- 8000998:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
- 800099c:	bf1e      	ittt	ne
- 800099e:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
- 80009a2:	ea92 0f0c 	teqne	r2, ip
- 80009a6:	ea93 0f0c 	teqne	r3, ip
- 80009aa:	d06f      	beq.n	8000a8c <__aeabi_fmul+0xf8>
- 80009ac:	441a      	add	r2, r3
- 80009ae:	ea80 0c01 	eor.w	ip, r0, r1
- 80009b2:	0240      	lsls	r0, r0, #9
- 80009b4:	bf18      	it	ne
- 80009b6:	ea5f 2141 	movsne.w	r1, r1, lsl #9
- 80009ba:	d01e      	beq.n	80009fa <__aeabi_fmul+0x66>
- 80009bc:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
- 80009c0:	ea43 1050 	orr.w	r0, r3, r0, lsr #5
- 80009c4:	ea43 1151 	orr.w	r1, r3, r1, lsr #5
- 80009c8:	fba0 3101 	umull	r3, r1, r0, r1
- 80009cc:	f00c 4000 	and.w	r0, ip, #2147483648	@ 0x80000000
- 80009d0:	f5b1 0f00 	cmp.w	r1, #8388608	@ 0x800000
- 80009d4:	bf3e      	ittt	cc
- 80009d6:	0049      	lslcc	r1, r1, #1
- 80009d8:	ea41 71d3 	orrcc.w	r1, r1, r3, lsr #31
- 80009dc:	005b      	lslcc	r3, r3, #1
- 80009de:	ea40 0001 	orr.w	r0, r0, r1
- 80009e2:	f162 027f 	sbc.w	r2, r2, #127	@ 0x7f
- 80009e6:	2afd      	cmp	r2, #253	@ 0xfd
- 80009e8:	d81d      	bhi.n	8000a26 <__aeabi_fmul+0x92>
- 80009ea:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
- 80009ee:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
- 80009f2:	bf08      	it	eq
- 80009f4:	f020 0001 	biceq.w	r0, r0, #1
- 80009f8:	4770      	bx	lr
- 80009fa:	f090 0f00 	teq	r0, #0
- 80009fe:	f00c 4c00 	and.w	ip, ip, #2147483648	@ 0x80000000
- 8000a02:	bf08      	it	eq
- 8000a04:	0249      	lsleq	r1, r1, #9
- 8000a06:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
- 8000a0a:	ea40 2051 	orr.w	r0, r0, r1, lsr #9
- 8000a0e:	3a7f      	subs	r2, #127	@ 0x7f
- 8000a10:	bfc2      	ittt	gt
- 8000a12:	f1d2 03ff 	rsbsgt	r3, r2, #255	@ 0xff
- 8000a16:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
- 8000a1a:	4770      	bxgt	lr
- 8000a1c:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
- 8000a20:	f04f 0300 	mov.w	r3, #0
- 8000a24:	3a01      	subs	r2, #1
- 8000a26:	dc5d      	bgt.n	8000ae4 <__aeabi_fmul+0x150>
- 8000a28:	f112 0f19 	cmn.w	r2, #25
- 8000a2c:	bfdc      	itt	le
- 8000a2e:	f000 4000 	andle.w	r0, r0, #2147483648	@ 0x80000000
- 8000a32:	4770      	bxle	lr
- 8000a34:	f1c2 0200 	rsb	r2, r2, #0
- 8000a38:	0041      	lsls	r1, r0, #1
- 8000a3a:	fa21 f102 	lsr.w	r1, r1, r2
- 8000a3e:	f1c2 0220 	rsb	r2, r2, #32
- 8000a42:	fa00 fc02 	lsl.w	ip, r0, r2
- 8000a46:	ea5f 0031 	movs.w	r0, r1, rrx
- 8000a4a:	f140 0000 	adc.w	r0, r0, #0
- 8000a4e:	ea53 034c 	orrs.w	r3, r3, ip, lsl #1
- 8000a52:	bf08      	it	eq
- 8000a54:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
+080009d0 <__aeabi_dcmple>:
+ 80009d0:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 80009d4:	f7ff ffe0 	bl	8000998 <__aeabi_cdcmpeq>
+ 80009d8:	bf94      	ite	ls
+ 80009da:	2001      	movls	r0, #1
+ 80009dc:	2000      	movhi	r0, #0
+ 80009de:	f85d fb08 	ldr.w	pc, [sp], #8
+ 80009e2:	bf00      	nop
+
+080009e4 <__aeabi_dcmpge>:
+ 80009e4:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 80009e8:	f7ff ffce 	bl	8000988 <__aeabi_cdrcmple>
+ 80009ec:	bf94      	ite	ls
+ 80009ee:	2001      	movls	r0, #1
+ 80009f0:	2000      	movhi	r0, #0
+ 80009f2:	f85d fb08 	ldr.w	pc, [sp], #8
+ 80009f6:	bf00      	nop
+
+080009f8 <__aeabi_dcmpgt>:
+ 80009f8:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 80009fc:	f7ff ffc4 	bl	8000988 <__aeabi_cdrcmple>
+ 8000a00:	bf34      	ite	cc
+ 8000a02:	2001      	movcc	r0, #1
+ 8000a04:	2000      	movcs	r0, #0
+ 8000a06:	f85d fb08 	ldr.w	pc, [sp], #8
+ 8000a0a:	bf00      	nop
+
+08000a0c <__aeabi_d2iz>:
+ 8000a0c:	ea4f 0241 	mov.w	r2, r1, lsl #1
+ 8000a10:	f512 1200 	adds.w	r2, r2, #2097152	@ 0x200000
+ 8000a14:	d215      	bcs.n	8000a42 <__aeabi_d2iz+0x36>
+ 8000a16:	d511      	bpl.n	8000a3c <__aeabi_d2iz+0x30>
+ 8000a18:	f46f 7378 	mvn.w	r3, #992	@ 0x3e0
+ 8000a1c:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
+ 8000a20:	d912      	bls.n	8000a48 <__aeabi_d2iz+0x3c>
+ 8000a22:	ea4f 23c1 	mov.w	r3, r1, lsl #11
+ 8000a26:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
+ 8000a2a:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
+ 8000a2e:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
+ 8000a32:	fa23 f002 	lsr.w	r0, r3, r2
+ 8000a36:	bf18      	it	ne
+ 8000a38:	4240      	negne	r0, r0
+ 8000a3a:	4770      	bx	lr
+ 8000a3c:	f04f 0000 	mov.w	r0, #0
+ 8000a40:	4770      	bx	lr
+ 8000a42:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
+ 8000a46:	d105      	bne.n	8000a54 <__aeabi_d2iz+0x48>
+ 8000a48:	f011 4000 	ands.w	r0, r1, #2147483648	@ 0x80000000
+ 8000a4c:	bf08      	it	eq
+ 8000a4e:	f06f 4000 	mvneq.w	r0, #2147483648	@ 0x80000000
+ 8000a52:	4770      	bx	lr
+ 8000a54:	f04f 0000 	mov.w	r0, #0
  8000a58:	4770      	bx	lr
- 8000a5a:	f092 0f00 	teq	r2, #0
- 8000a5e:	f000 4c00 	and.w	ip, r0, #2147483648	@ 0x80000000
- 8000a62:	bf02      	ittt	eq
- 8000a64:	0040      	lsleq	r0, r0, #1
- 8000a66:	f410 0f00 	tsteq.w	r0, #8388608	@ 0x800000
- 8000a6a:	3a01      	subeq	r2, #1
- 8000a6c:	d0f9      	beq.n	8000a62 <__aeabi_fmul+0xce>
- 8000a6e:	ea40 000c 	orr.w	r0, r0, ip
- 8000a72:	f093 0f00 	teq	r3, #0
- 8000a76:	f001 4c00 	and.w	ip, r1, #2147483648	@ 0x80000000
- 8000a7a:	bf02      	ittt	eq
- 8000a7c:	0049      	lsleq	r1, r1, #1
- 8000a7e:	f411 0f00 	tsteq.w	r1, #8388608	@ 0x800000
- 8000a82:	3b01      	subeq	r3, #1
- 8000a84:	d0f9      	beq.n	8000a7a <__aeabi_fmul+0xe6>
- 8000a86:	ea41 010c 	orr.w	r1, r1, ip
- 8000a8a:	e78f      	b.n	80009ac <__aeabi_fmul+0x18>
- 8000a8c:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
- 8000a90:	ea92 0f0c 	teq	r2, ip
- 8000a94:	bf18      	it	ne
- 8000a96:	ea93 0f0c 	teqne	r3, ip
- 8000a9a:	d00a      	beq.n	8000ab2 <__aeabi_fmul+0x11e>
- 8000a9c:	f030 4c00 	bics.w	ip, r0, #2147483648	@ 0x80000000
- 8000aa0:	bf18      	it	ne
- 8000aa2:	f031 4c00 	bicsne.w	ip, r1, #2147483648	@ 0x80000000
- 8000aa6:	d1d8      	bne.n	8000a5a <__aeabi_fmul+0xc6>
- 8000aa8:	ea80 0001 	eor.w	r0, r0, r1
- 8000aac:	f000 4000 	and.w	r0, r0, #2147483648	@ 0x80000000
- 8000ab0:	4770      	bx	lr
- 8000ab2:	f090 0f00 	teq	r0, #0
- 8000ab6:	bf17      	itett	ne
- 8000ab8:	f090 4f00 	teqne	r0, #2147483648	@ 0x80000000
- 8000abc:	4608      	moveq	r0, r1
- 8000abe:	f091 0f00 	teqne	r1, #0
- 8000ac2:	f091 4f00 	teqne	r1, #2147483648	@ 0x80000000
- 8000ac6:	d014      	beq.n	8000af2 <__aeabi_fmul+0x15e>
- 8000ac8:	ea92 0f0c 	teq	r2, ip
- 8000acc:	d101      	bne.n	8000ad2 <__aeabi_fmul+0x13e>
- 8000ace:	0242      	lsls	r2, r0, #9
- 8000ad0:	d10f      	bne.n	8000af2 <__aeabi_fmul+0x15e>
- 8000ad2:	ea93 0f0c 	teq	r3, ip
- 8000ad6:	d103      	bne.n	8000ae0 <__aeabi_fmul+0x14c>
- 8000ad8:	024b      	lsls	r3, r1, #9
- 8000ada:	bf18      	it	ne
- 8000adc:	4608      	movne	r0, r1
- 8000ade:	d108      	bne.n	8000af2 <__aeabi_fmul+0x15e>
- 8000ae0:	ea80 0001 	eor.w	r0, r0, r1
- 8000ae4:	f000 4000 	and.w	r0, r0, #2147483648	@ 0x80000000
- 8000ae8:	f040 40fe 	orr.w	r0, r0, #2130706432	@ 0x7f000000
- 8000aec:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
- 8000af0:	4770      	bx	lr
- 8000af2:	f040 40fe 	orr.w	r0, r0, #2130706432	@ 0x7f000000
- 8000af6:	f440 0040 	orr.w	r0, r0, #12582912	@ 0xc00000
- 8000afa:	4770      	bx	lr
+ 8000a5a:	bf00      	nop
 
-08000afc <__aeabi_fdiv>:
- 8000afc:	f04f 0cff 	mov.w	ip, #255	@ 0xff
- 8000b00:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
- 8000b04:	bf1e      	ittt	ne
- 8000b06:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
- 8000b0a:	ea92 0f0c 	teqne	r2, ip
- 8000b0e:	ea93 0f0c 	teqne	r3, ip
- 8000b12:	d069      	beq.n	8000be8 <__aeabi_fdiv+0xec>
- 8000b14:	eba2 0203 	sub.w	r2, r2, r3
- 8000b18:	ea80 0c01 	eor.w	ip, r0, r1
- 8000b1c:	0249      	lsls	r1, r1, #9
- 8000b1e:	ea4f 2040 	mov.w	r0, r0, lsl #9
- 8000b22:	d037      	beq.n	8000b94 <__aeabi_fdiv+0x98>
- 8000b24:	f04f 5380 	mov.w	r3, #268435456	@ 0x10000000
- 8000b28:	ea43 1111 	orr.w	r1, r3, r1, lsr #4
- 8000b2c:	ea43 1310 	orr.w	r3, r3, r0, lsr #4
- 8000b30:	f00c 4000 	and.w	r0, ip, #2147483648	@ 0x80000000
- 8000b34:	428b      	cmp	r3, r1
- 8000b36:	bf38      	it	cc
- 8000b38:	005b      	lslcc	r3, r3, #1
- 8000b3a:	f142 027d 	adc.w	r2, r2, #125	@ 0x7d
- 8000b3e:	f44f 0c00 	mov.w	ip, #8388608	@ 0x800000
- 8000b42:	428b      	cmp	r3, r1
- 8000b44:	bf24      	itt	cs
- 8000b46:	1a5b      	subcs	r3, r3, r1
- 8000b48:	ea40 000c 	orrcs.w	r0, r0, ip
- 8000b4c:	ebb3 0f51 	cmp.w	r3, r1, lsr #1
- 8000b50:	bf24      	itt	cs
- 8000b52:	eba3 0351 	subcs.w	r3, r3, r1, lsr #1
- 8000b56:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
- 8000b5a:	ebb3 0f91 	cmp.w	r3, r1, lsr #2
- 8000b5e:	bf24      	itt	cs
- 8000b60:	eba3 0391 	subcs.w	r3, r3, r1, lsr #2
- 8000b64:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
- 8000b68:	ebb3 0fd1 	cmp.w	r3, r1, lsr #3
- 8000b6c:	bf24      	itt	cs
- 8000b6e:	eba3 03d1 	subcs.w	r3, r3, r1, lsr #3
- 8000b72:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
- 8000b76:	011b      	lsls	r3, r3, #4
- 8000b78:	bf18      	it	ne
- 8000b7a:	ea5f 1c1c 	movsne.w	ip, ip, lsr #4
- 8000b7e:	d1e0      	bne.n	8000b42 <__aeabi_fdiv+0x46>
- 8000b80:	2afd      	cmp	r2, #253	@ 0xfd
- 8000b82:	f63f af50 	bhi.w	8000a26 <__aeabi_fmul+0x92>
- 8000b86:	428b      	cmp	r3, r1
- 8000b88:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
- 8000b8c:	bf08      	it	eq
- 8000b8e:	f020 0001 	biceq.w	r0, r0, #1
- 8000b92:	4770      	bx	lr
- 8000b94:	f00c 4c00 	and.w	ip, ip, #2147483648	@ 0x80000000
- 8000b98:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
- 8000b9c:	327f      	adds	r2, #127	@ 0x7f
- 8000b9e:	bfc2      	ittt	gt
- 8000ba0:	f1d2 03ff 	rsbsgt	r3, r2, #255	@ 0xff
- 8000ba4:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
- 8000ba8:	4770      	bxgt	lr
- 8000baa:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
- 8000bae:	f04f 0300 	mov.w	r3, #0
- 8000bb2:	3a01      	subs	r2, #1
- 8000bb4:	e737      	b.n	8000a26 <__aeabi_fmul+0x92>
- 8000bb6:	f092 0f00 	teq	r2, #0
- 8000bba:	f000 4c00 	and.w	ip, r0, #2147483648	@ 0x80000000
- 8000bbe:	bf02      	ittt	eq
- 8000bc0:	0040      	lsleq	r0, r0, #1
- 8000bc2:	f410 0f00 	tsteq.w	r0, #8388608	@ 0x800000
- 8000bc6:	3a01      	subeq	r2, #1
- 8000bc8:	d0f9      	beq.n	8000bbe <__aeabi_fdiv+0xc2>
- 8000bca:	ea40 000c 	orr.w	r0, r0, ip
- 8000bce:	f093 0f00 	teq	r3, #0
- 8000bd2:	f001 4c00 	and.w	ip, r1, #2147483648	@ 0x80000000
- 8000bd6:	bf02      	ittt	eq
- 8000bd8:	0049      	lsleq	r1, r1, #1
- 8000bda:	f411 0f00 	tsteq.w	r1, #8388608	@ 0x800000
- 8000bde:	3b01      	subeq	r3, #1
- 8000be0:	d0f9      	beq.n	8000bd6 <__aeabi_fdiv+0xda>
- 8000be2:	ea41 010c 	orr.w	r1, r1, ip
- 8000be6:	e795      	b.n	8000b14 <__aeabi_fdiv+0x18>
- 8000be8:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
- 8000bec:	ea92 0f0c 	teq	r2, ip
- 8000bf0:	d108      	bne.n	8000c04 <__aeabi_fdiv+0x108>
- 8000bf2:	0242      	lsls	r2, r0, #9
- 8000bf4:	f47f af7d 	bne.w	8000af2 <__aeabi_fmul+0x15e>
- 8000bf8:	ea93 0f0c 	teq	r3, ip
- 8000bfc:	f47f af70 	bne.w	8000ae0 <__aeabi_fmul+0x14c>
- 8000c00:	4608      	mov	r0, r1
- 8000c02:	e776      	b.n	8000af2 <__aeabi_fmul+0x15e>
- 8000c04:	ea93 0f0c 	teq	r3, ip
- 8000c08:	d104      	bne.n	8000c14 <__aeabi_fdiv+0x118>
- 8000c0a:	024b      	lsls	r3, r1, #9
- 8000c0c:	f43f af4c 	beq.w	8000aa8 <__aeabi_fmul+0x114>
- 8000c10:	4608      	mov	r0, r1
- 8000c12:	e76e      	b.n	8000af2 <__aeabi_fmul+0x15e>
- 8000c14:	f030 4c00 	bics.w	ip, r0, #2147483648	@ 0x80000000
- 8000c18:	bf18      	it	ne
- 8000c1a:	f031 4c00 	bicsne.w	ip, r1, #2147483648	@ 0x80000000
- 8000c1e:	d1ca      	bne.n	8000bb6 <__aeabi_fdiv+0xba>
- 8000c20:	f030 4200 	bics.w	r2, r0, #2147483648	@ 0x80000000
- 8000c24:	f47f af5c 	bne.w	8000ae0 <__aeabi_fmul+0x14c>
- 8000c28:	f031 4300 	bics.w	r3, r1, #2147483648	@ 0x80000000
- 8000c2c:	f47f af3c 	bne.w	8000aa8 <__aeabi_fmul+0x114>
- 8000c30:	e75f      	b.n	8000af2 <__aeabi_fmul+0x15e>
- 8000c32:	bf00      	nop
+08000a5c <__aeabi_d2f>:
+ 8000a5c:	ea4f 0241 	mov.w	r2, r1, lsl #1
+ 8000a60:	f1b2 43e0 	subs.w	r3, r2, #1879048192	@ 0x70000000
+ 8000a64:	bf24      	itt	cs
+ 8000a66:	f5b3 1c00 	subscs.w	ip, r3, #2097152	@ 0x200000
+ 8000a6a:	f1dc 5cfe 	rsbscs	ip, ip, #532676608	@ 0x1fc00000
+ 8000a6e:	d90d      	bls.n	8000a8c <__aeabi_d2f+0x30>
+ 8000a70:	f001 4c00 	and.w	ip, r1, #2147483648	@ 0x80000000
+ 8000a74:	ea4f 02c0 	mov.w	r2, r0, lsl #3
+ 8000a78:	ea4c 7050 	orr.w	r0, ip, r0, lsr #29
+ 8000a7c:	f1b2 4f00 	cmp.w	r2, #2147483648	@ 0x80000000
+ 8000a80:	eb40 0083 	adc.w	r0, r0, r3, lsl #2
+ 8000a84:	bf08      	it	eq
+ 8000a86:	f020 0001 	biceq.w	r0, r0, #1
+ 8000a8a:	4770      	bx	lr
+ 8000a8c:	f011 4f80 	tst.w	r1, #1073741824	@ 0x40000000
+ 8000a90:	d121      	bne.n	8000ad6 <__aeabi_d2f+0x7a>
+ 8000a92:	f113 7238 	adds.w	r2, r3, #48234496	@ 0x2e00000
+ 8000a96:	bfbc      	itt	lt
+ 8000a98:	f001 4000 	andlt.w	r0, r1, #2147483648	@ 0x80000000
+ 8000a9c:	4770      	bxlt	lr
+ 8000a9e:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
+ 8000aa2:	ea4f 5252 	mov.w	r2, r2, lsr #21
+ 8000aa6:	f1c2 0218 	rsb	r2, r2, #24
+ 8000aaa:	f1c2 0c20 	rsb	ip, r2, #32
+ 8000aae:	fa10 f30c 	lsls.w	r3, r0, ip
+ 8000ab2:	fa20 f002 	lsr.w	r0, r0, r2
+ 8000ab6:	bf18      	it	ne
+ 8000ab8:	f040 0001 	orrne.w	r0, r0, #1
+ 8000abc:	ea4f 23c1 	mov.w	r3, r1, lsl #11
+ 8000ac0:	ea4f 23d3 	mov.w	r3, r3, lsr #11
+ 8000ac4:	fa03 fc0c 	lsl.w	ip, r3, ip
+ 8000ac8:	ea40 000c 	orr.w	r0, r0, ip
+ 8000acc:	fa23 f302 	lsr.w	r3, r3, r2
+ 8000ad0:	ea4f 0343 	mov.w	r3, r3, lsl #1
+ 8000ad4:	e7cc      	b.n	8000a70 <__aeabi_d2f+0x14>
+ 8000ad6:	ea7f 5362 	mvns.w	r3, r2, asr #21
+ 8000ada:	d107      	bne.n	8000aec <__aeabi_d2f+0x90>
+ 8000adc:	ea50 3301 	orrs.w	r3, r0, r1, lsl #12
+ 8000ae0:	bf1e      	ittt	ne
+ 8000ae2:	f04f 40fe 	movne.w	r0, #2130706432	@ 0x7f000000
+ 8000ae6:	f440 0040 	orrne.w	r0, r0, #12582912	@ 0xc00000
+ 8000aea:	4770      	bxne	lr
+ 8000aec:	f001 4000 	and.w	r0, r1, #2147483648	@ 0x80000000
+ 8000af0:	f040 40fe 	orr.w	r0, r0, #2130706432	@ 0x7f000000
+ 8000af4:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000af8:	4770      	bx	lr
+ 8000afa:	bf00      	nop
 
-08000c34 <__gesf2>:
- 8000c34:	f04f 3cff 	mov.w	ip, #4294967295
- 8000c38:	e006      	b.n	8000c48 <__cmpsf2+0x4>
- 8000c3a:	bf00      	nop
+08000afc <__aeabi_frsub>:
+ 8000afc:	f080 4000 	eor.w	r0, r0, #2147483648	@ 0x80000000
+ 8000b00:	e002      	b.n	8000b08 <__addsf3>
+ 8000b02:	bf00      	nop
 
-08000c3c <__lesf2>:
- 8000c3c:	f04f 0c01 	mov.w	ip, #1
- 8000c40:	e002      	b.n	8000c48 <__cmpsf2+0x4>
- 8000c42:	bf00      	nop
+08000b04 <__aeabi_fsub>:
+ 8000b04:	f081 4100 	eor.w	r1, r1, #2147483648	@ 0x80000000
 
-08000c44 <__cmpsf2>:
- 8000c44:	f04f 0c01 	mov.w	ip, #1
- 8000c48:	f84d cd04 	str.w	ip, [sp, #-4]!
- 8000c4c:	ea4f 0240 	mov.w	r2, r0, lsl #1
- 8000c50:	ea4f 0341 	mov.w	r3, r1, lsl #1
- 8000c54:	ea7f 6c22 	mvns.w	ip, r2, asr #24
- 8000c58:	bf18      	it	ne
- 8000c5a:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
- 8000c5e:	d011      	beq.n	8000c84 <__cmpsf2+0x40>
- 8000c60:	b001      	add	sp, #4
- 8000c62:	ea52 0c53 	orrs.w	ip, r2, r3, lsr #1
- 8000c66:	bf18      	it	ne
- 8000c68:	ea90 0f01 	teqne	r0, r1
- 8000c6c:	bf58      	it	pl
- 8000c6e:	ebb2 0003 	subspl.w	r0, r2, r3
- 8000c72:	bf88      	it	hi
- 8000c74:	17c8      	asrhi	r0, r1, #31
- 8000c76:	bf38      	it	cc
- 8000c78:	ea6f 70e1 	mvncc.w	r0, r1, asr #31
- 8000c7c:	bf18      	it	ne
- 8000c7e:	f040 0001 	orrne.w	r0, r0, #1
- 8000c82:	4770      	bx	lr
- 8000c84:	ea7f 6c22 	mvns.w	ip, r2, asr #24
- 8000c88:	d102      	bne.n	8000c90 <__cmpsf2+0x4c>
- 8000c8a:	ea5f 2c40 	movs.w	ip, r0, lsl #9
- 8000c8e:	d105      	bne.n	8000c9c <__cmpsf2+0x58>
- 8000c90:	ea7f 6c23 	mvns.w	ip, r3, asr #24
- 8000c94:	d1e4      	bne.n	8000c60 <__cmpsf2+0x1c>
- 8000c96:	ea5f 2c41 	movs.w	ip, r1, lsl #9
- 8000c9a:	d0e1      	beq.n	8000c60 <__cmpsf2+0x1c>
- 8000c9c:	f85d 0b04 	ldr.w	r0, [sp], #4
- 8000ca0:	4770      	bx	lr
- 8000ca2:	bf00      	nop
+08000b08 <__addsf3>:
+ 8000b08:	0042      	lsls	r2, r0, #1
+ 8000b0a:	bf1f      	itttt	ne
+ 8000b0c:	ea5f 0341 	movsne.w	r3, r1, lsl #1
+ 8000b10:	ea92 0f03 	teqne	r2, r3
+ 8000b14:	ea7f 6c22 	mvnsne.w	ip, r2, asr #24
+ 8000b18:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
+ 8000b1c:	d06a      	beq.n	8000bf4 <__addsf3+0xec>
+ 8000b1e:	ea4f 6212 	mov.w	r2, r2, lsr #24
+ 8000b22:	ebd2 6313 	rsbs	r3, r2, r3, lsr #24
+ 8000b26:	bfc1      	itttt	gt
+ 8000b28:	18d2      	addgt	r2, r2, r3
+ 8000b2a:	4041      	eorgt	r1, r0
+ 8000b2c:	4048      	eorgt	r0, r1
+ 8000b2e:	4041      	eorgt	r1, r0
+ 8000b30:	bfb8      	it	lt
+ 8000b32:	425b      	neglt	r3, r3
+ 8000b34:	2b19      	cmp	r3, #25
+ 8000b36:	bf88      	it	hi
+ 8000b38:	4770      	bxhi	lr
+ 8000b3a:	f010 4f00 	tst.w	r0, #2147483648	@ 0x80000000
+ 8000b3e:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000b42:	f020 407f 	bic.w	r0, r0, #4278190080	@ 0xff000000
+ 8000b46:	bf18      	it	ne
+ 8000b48:	4240      	negne	r0, r0
+ 8000b4a:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
+ 8000b4e:	f441 0100 	orr.w	r1, r1, #8388608	@ 0x800000
+ 8000b52:	f021 417f 	bic.w	r1, r1, #4278190080	@ 0xff000000
+ 8000b56:	bf18      	it	ne
+ 8000b58:	4249      	negne	r1, r1
+ 8000b5a:	ea92 0f03 	teq	r2, r3
+ 8000b5e:	d03f      	beq.n	8000be0 <__addsf3+0xd8>
+ 8000b60:	f1a2 0201 	sub.w	r2, r2, #1
+ 8000b64:	fa41 fc03 	asr.w	ip, r1, r3
+ 8000b68:	eb10 000c 	adds.w	r0, r0, ip
+ 8000b6c:	f1c3 0320 	rsb	r3, r3, #32
+ 8000b70:	fa01 f103 	lsl.w	r1, r1, r3
+ 8000b74:	f000 4300 	and.w	r3, r0, #2147483648	@ 0x80000000
+ 8000b78:	d502      	bpl.n	8000b80 <__addsf3+0x78>
+ 8000b7a:	4249      	negs	r1, r1
+ 8000b7c:	eb60 0040 	sbc.w	r0, r0, r0, lsl #1
+ 8000b80:	f5b0 0f00 	cmp.w	r0, #8388608	@ 0x800000
+ 8000b84:	d313      	bcc.n	8000bae <__addsf3+0xa6>
+ 8000b86:	f1b0 7f80 	cmp.w	r0, #16777216	@ 0x1000000
+ 8000b8a:	d306      	bcc.n	8000b9a <__addsf3+0x92>
+ 8000b8c:	0840      	lsrs	r0, r0, #1
+ 8000b8e:	ea4f 0131 	mov.w	r1, r1, rrx
+ 8000b92:	f102 0201 	add.w	r2, r2, #1
+ 8000b96:	2afe      	cmp	r2, #254	@ 0xfe
+ 8000b98:	d251      	bcs.n	8000c3e <__addsf3+0x136>
+ 8000b9a:	f1b1 4f00 	cmp.w	r1, #2147483648	@ 0x80000000
+ 8000b9e:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
+ 8000ba2:	bf08      	it	eq
+ 8000ba4:	f020 0001 	biceq.w	r0, r0, #1
+ 8000ba8:	ea40 0003 	orr.w	r0, r0, r3
+ 8000bac:	4770      	bx	lr
+ 8000bae:	0049      	lsls	r1, r1, #1
+ 8000bb0:	eb40 0000 	adc.w	r0, r0, r0
+ 8000bb4:	3a01      	subs	r2, #1
+ 8000bb6:	bf28      	it	cs
+ 8000bb8:	f5b0 0f00 	cmpcs.w	r0, #8388608	@ 0x800000
+ 8000bbc:	d2ed      	bcs.n	8000b9a <__addsf3+0x92>
+ 8000bbe:	fab0 fc80 	clz	ip, r0
+ 8000bc2:	f1ac 0c08 	sub.w	ip, ip, #8
+ 8000bc6:	ebb2 020c 	subs.w	r2, r2, ip
+ 8000bca:	fa00 f00c 	lsl.w	r0, r0, ip
+ 8000bce:	bfaa      	itet	ge
+ 8000bd0:	eb00 50c2 	addge.w	r0, r0, r2, lsl #23
+ 8000bd4:	4252      	neglt	r2, r2
+ 8000bd6:	4318      	orrge	r0, r3
+ 8000bd8:	bfbc      	itt	lt
+ 8000bda:	40d0      	lsrlt	r0, r2
+ 8000bdc:	4318      	orrlt	r0, r3
+ 8000bde:	4770      	bx	lr
+ 8000be0:	f092 0f00 	teq	r2, #0
+ 8000be4:	f481 0100 	eor.w	r1, r1, #8388608	@ 0x800000
+ 8000be8:	bf06      	itte	eq
+ 8000bea:	f480 0000 	eoreq.w	r0, r0, #8388608	@ 0x800000
+ 8000bee:	3201      	addeq	r2, #1
+ 8000bf0:	3b01      	subne	r3, #1
+ 8000bf2:	e7b5      	b.n	8000b60 <__addsf3+0x58>
+ 8000bf4:	ea4f 0341 	mov.w	r3, r1, lsl #1
+ 8000bf8:	ea7f 6c22 	mvns.w	ip, r2, asr #24
+ 8000bfc:	bf18      	it	ne
+ 8000bfe:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
+ 8000c02:	d021      	beq.n	8000c48 <__addsf3+0x140>
+ 8000c04:	ea92 0f03 	teq	r2, r3
+ 8000c08:	d004      	beq.n	8000c14 <__addsf3+0x10c>
+ 8000c0a:	f092 0f00 	teq	r2, #0
+ 8000c0e:	bf08      	it	eq
+ 8000c10:	4608      	moveq	r0, r1
+ 8000c12:	4770      	bx	lr
+ 8000c14:	ea90 0f01 	teq	r0, r1
+ 8000c18:	bf1c      	itt	ne
+ 8000c1a:	2000      	movne	r0, #0
+ 8000c1c:	4770      	bxne	lr
+ 8000c1e:	f012 4f7f 	tst.w	r2, #4278190080	@ 0xff000000
+ 8000c22:	d104      	bne.n	8000c2e <__addsf3+0x126>
+ 8000c24:	0040      	lsls	r0, r0, #1
+ 8000c26:	bf28      	it	cs
+ 8000c28:	f040 4000 	orrcs.w	r0, r0, #2147483648	@ 0x80000000
+ 8000c2c:	4770      	bx	lr
+ 8000c2e:	f112 7200 	adds.w	r2, r2, #33554432	@ 0x2000000
+ 8000c32:	bf3c      	itt	cc
+ 8000c34:	f500 0000 	addcc.w	r0, r0, #8388608	@ 0x800000
+ 8000c38:	4770      	bxcc	lr
+ 8000c3a:	f000 4300 	and.w	r3, r0, #2147483648	@ 0x80000000
+ 8000c3e:	f043 40fe 	orr.w	r0, r3, #2130706432	@ 0x7f000000
+ 8000c42:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000c46:	4770      	bx	lr
+ 8000c48:	ea7f 6222 	mvns.w	r2, r2, asr #24
+ 8000c4c:	bf16      	itet	ne
+ 8000c4e:	4608      	movne	r0, r1
+ 8000c50:	ea7f 6323 	mvnseq.w	r3, r3, asr #24
+ 8000c54:	4601      	movne	r1, r0
+ 8000c56:	0242      	lsls	r2, r0, #9
+ 8000c58:	bf06      	itte	eq
+ 8000c5a:	ea5f 2341 	movseq.w	r3, r1, lsl #9
+ 8000c5e:	ea90 0f01 	teqeq	r0, r1
+ 8000c62:	f440 0080 	orrne.w	r0, r0, #4194304	@ 0x400000
+ 8000c66:	4770      	bx	lr
 
-08000ca4 <__aeabi_cfrcmple>:
- 8000ca4:	4684      	mov	ip, r0
- 8000ca6:	4608      	mov	r0, r1
- 8000ca8:	4661      	mov	r1, ip
- 8000caa:	e7ff      	b.n	8000cac <__aeabi_cfcmpeq>
+08000c68 <__aeabi_ui2f>:
+ 8000c68:	f04f 0300 	mov.w	r3, #0
+ 8000c6c:	e004      	b.n	8000c78 <__aeabi_i2f+0x8>
+ 8000c6e:	bf00      	nop
 
-08000cac <__aeabi_cfcmpeq>:
- 8000cac:	b50f      	push	{r0, r1, r2, r3, lr}
- 8000cae:	f7ff ffc9 	bl	8000c44 <__cmpsf2>
- 8000cb2:	2800      	cmp	r0, #0
- 8000cb4:	bf48      	it	mi
- 8000cb6:	f110 0f00 	cmnmi.w	r0, #0
- 8000cba:	bd0f      	pop	{r0, r1, r2, r3, pc}
+08000c70 <__aeabi_i2f>:
+ 8000c70:	f010 4300 	ands.w	r3, r0, #2147483648	@ 0x80000000
+ 8000c74:	bf48      	it	mi
+ 8000c76:	4240      	negmi	r0, r0
+ 8000c78:	ea5f 0c00 	movs.w	ip, r0
+ 8000c7c:	bf08      	it	eq
+ 8000c7e:	4770      	bxeq	lr
+ 8000c80:	f043 4396 	orr.w	r3, r3, #1258291200	@ 0x4b000000
+ 8000c84:	4601      	mov	r1, r0
+ 8000c86:	f04f 0000 	mov.w	r0, #0
+ 8000c8a:	e01c      	b.n	8000cc6 <__aeabi_l2f+0x2a>
 
-08000cbc <__aeabi_fcmpeq>:
- 8000cbc:	f84d ed08 	str.w	lr, [sp, #-8]!
- 8000cc0:	f7ff fff4 	bl	8000cac <__aeabi_cfcmpeq>
- 8000cc4:	bf0c      	ite	eq
- 8000cc6:	2001      	moveq	r0, #1
- 8000cc8:	2000      	movne	r0, #0
- 8000cca:	f85d fb08 	ldr.w	pc, [sp], #8
- 8000cce:	bf00      	nop
+08000c8c <__aeabi_ul2f>:
+ 8000c8c:	ea50 0201 	orrs.w	r2, r0, r1
+ 8000c90:	bf08      	it	eq
+ 8000c92:	4770      	bxeq	lr
+ 8000c94:	f04f 0300 	mov.w	r3, #0
+ 8000c98:	e00a      	b.n	8000cb0 <__aeabi_l2f+0x14>
+ 8000c9a:	bf00      	nop
 
-08000cd0 <__aeabi_fcmplt>:
- 8000cd0:	f84d ed08 	str.w	lr, [sp, #-8]!
- 8000cd4:	f7ff ffea 	bl	8000cac <__aeabi_cfcmpeq>
- 8000cd8:	bf34      	ite	cc
- 8000cda:	2001      	movcc	r0, #1
- 8000cdc:	2000      	movcs	r0, #0
- 8000cde:	f85d fb08 	ldr.w	pc, [sp], #8
- 8000ce2:	bf00      	nop
+08000c9c <__aeabi_l2f>:
+ 8000c9c:	ea50 0201 	orrs.w	r2, r0, r1
+ 8000ca0:	bf08      	it	eq
+ 8000ca2:	4770      	bxeq	lr
+ 8000ca4:	f011 4300 	ands.w	r3, r1, #2147483648	@ 0x80000000
+ 8000ca8:	d502      	bpl.n	8000cb0 <__aeabi_l2f+0x14>
+ 8000caa:	4240      	negs	r0, r0
+ 8000cac:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
+ 8000cb0:	ea5f 0c01 	movs.w	ip, r1
+ 8000cb4:	bf02      	ittt	eq
+ 8000cb6:	4684      	moveq	ip, r0
+ 8000cb8:	4601      	moveq	r1, r0
+ 8000cba:	2000      	moveq	r0, #0
+ 8000cbc:	f043 43b6 	orr.w	r3, r3, #1526726656	@ 0x5b000000
+ 8000cc0:	bf08      	it	eq
+ 8000cc2:	f1a3 5380 	subeq.w	r3, r3, #268435456	@ 0x10000000
+ 8000cc6:	f5a3 0300 	sub.w	r3, r3, #8388608	@ 0x800000
+ 8000cca:	fabc f28c 	clz	r2, ip
+ 8000cce:	3a08      	subs	r2, #8
+ 8000cd0:	eba3 53c2 	sub.w	r3, r3, r2, lsl #23
+ 8000cd4:	db10      	blt.n	8000cf8 <__aeabi_l2f+0x5c>
+ 8000cd6:	fa01 fc02 	lsl.w	ip, r1, r2
+ 8000cda:	4463      	add	r3, ip
+ 8000cdc:	fa00 fc02 	lsl.w	ip, r0, r2
+ 8000ce0:	f1c2 0220 	rsb	r2, r2, #32
+ 8000ce4:	f1bc 4f00 	cmp.w	ip, #2147483648	@ 0x80000000
+ 8000ce8:	fa20 f202 	lsr.w	r2, r0, r2
+ 8000cec:	eb43 0002 	adc.w	r0, r3, r2
+ 8000cf0:	bf08      	it	eq
+ 8000cf2:	f020 0001 	biceq.w	r0, r0, #1
+ 8000cf6:	4770      	bx	lr
+ 8000cf8:	f102 0220 	add.w	r2, r2, #32
+ 8000cfc:	fa01 fc02 	lsl.w	ip, r1, r2
+ 8000d00:	f1c2 0220 	rsb	r2, r2, #32
+ 8000d04:	ea50 004c 	orrs.w	r0, r0, ip, lsl #1
+ 8000d08:	fa21 f202 	lsr.w	r2, r1, r2
+ 8000d0c:	eb43 0002 	adc.w	r0, r3, r2
+ 8000d10:	bf08      	it	eq
+ 8000d12:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
+ 8000d16:	4770      	bx	lr
 
-08000ce4 <__aeabi_fcmple>:
- 8000ce4:	f84d ed08 	str.w	lr, [sp, #-8]!
- 8000ce8:	f7ff ffe0 	bl	8000cac <__aeabi_cfcmpeq>
- 8000cec:	bf94      	ite	ls
- 8000cee:	2001      	movls	r0, #1
- 8000cf0:	2000      	movhi	r0, #0
- 8000cf2:	f85d fb08 	ldr.w	pc, [sp], #8
- 8000cf6:	bf00      	nop
+08000d18 <__aeabi_fmul>:
+ 8000d18:	f04f 0cff 	mov.w	ip, #255	@ 0xff
+ 8000d1c:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
+ 8000d20:	bf1e      	ittt	ne
+ 8000d22:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
+ 8000d26:	ea92 0f0c 	teqne	r2, ip
+ 8000d2a:	ea93 0f0c 	teqne	r3, ip
+ 8000d2e:	d06f      	beq.n	8000e10 <__aeabi_fmul+0xf8>
+ 8000d30:	441a      	add	r2, r3
+ 8000d32:	ea80 0c01 	eor.w	ip, r0, r1
+ 8000d36:	0240      	lsls	r0, r0, #9
+ 8000d38:	bf18      	it	ne
+ 8000d3a:	ea5f 2141 	movsne.w	r1, r1, lsl #9
+ 8000d3e:	d01e      	beq.n	8000d7e <__aeabi_fmul+0x66>
+ 8000d40:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
+ 8000d44:	ea43 1050 	orr.w	r0, r3, r0, lsr #5
+ 8000d48:	ea43 1151 	orr.w	r1, r3, r1, lsr #5
+ 8000d4c:	fba0 3101 	umull	r3, r1, r0, r1
+ 8000d50:	f00c 4000 	and.w	r0, ip, #2147483648	@ 0x80000000
+ 8000d54:	f5b1 0f00 	cmp.w	r1, #8388608	@ 0x800000
+ 8000d58:	bf3e      	ittt	cc
+ 8000d5a:	0049      	lslcc	r1, r1, #1
+ 8000d5c:	ea41 71d3 	orrcc.w	r1, r1, r3, lsr #31
+ 8000d60:	005b      	lslcc	r3, r3, #1
+ 8000d62:	ea40 0001 	orr.w	r0, r0, r1
+ 8000d66:	f162 027f 	sbc.w	r2, r2, #127	@ 0x7f
+ 8000d6a:	2afd      	cmp	r2, #253	@ 0xfd
+ 8000d6c:	d81d      	bhi.n	8000daa <__aeabi_fmul+0x92>
+ 8000d6e:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
+ 8000d72:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
+ 8000d76:	bf08      	it	eq
+ 8000d78:	f020 0001 	biceq.w	r0, r0, #1
+ 8000d7c:	4770      	bx	lr
+ 8000d7e:	f090 0f00 	teq	r0, #0
+ 8000d82:	f00c 4c00 	and.w	ip, ip, #2147483648	@ 0x80000000
+ 8000d86:	bf08      	it	eq
+ 8000d88:	0249      	lsleq	r1, r1, #9
+ 8000d8a:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
+ 8000d8e:	ea40 2051 	orr.w	r0, r0, r1, lsr #9
+ 8000d92:	3a7f      	subs	r2, #127	@ 0x7f
+ 8000d94:	bfc2      	ittt	gt
+ 8000d96:	f1d2 03ff 	rsbsgt	r3, r2, #255	@ 0xff
+ 8000d9a:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
+ 8000d9e:	4770      	bxgt	lr
+ 8000da0:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000da4:	f04f 0300 	mov.w	r3, #0
+ 8000da8:	3a01      	subs	r2, #1
+ 8000daa:	dc5d      	bgt.n	8000e68 <__aeabi_fmul+0x150>
+ 8000dac:	f112 0f19 	cmn.w	r2, #25
+ 8000db0:	bfdc      	itt	le
+ 8000db2:	f000 4000 	andle.w	r0, r0, #2147483648	@ 0x80000000
+ 8000db6:	4770      	bxle	lr
+ 8000db8:	f1c2 0200 	rsb	r2, r2, #0
+ 8000dbc:	0041      	lsls	r1, r0, #1
+ 8000dbe:	fa21 f102 	lsr.w	r1, r1, r2
+ 8000dc2:	f1c2 0220 	rsb	r2, r2, #32
+ 8000dc6:	fa00 fc02 	lsl.w	ip, r0, r2
+ 8000dca:	ea5f 0031 	movs.w	r0, r1, rrx
+ 8000dce:	f140 0000 	adc.w	r0, r0, #0
+ 8000dd2:	ea53 034c 	orrs.w	r3, r3, ip, lsl #1
+ 8000dd6:	bf08      	it	eq
+ 8000dd8:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
+ 8000ddc:	4770      	bx	lr
+ 8000dde:	f092 0f00 	teq	r2, #0
+ 8000de2:	f000 4c00 	and.w	ip, r0, #2147483648	@ 0x80000000
+ 8000de6:	bf02      	ittt	eq
+ 8000de8:	0040      	lsleq	r0, r0, #1
+ 8000dea:	f410 0f00 	tsteq.w	r0, #8388608	@ 0x800000
+ 8000dee:	3a01      	subeq	r2, #1
+ 8000df0:	d0f9      	beq.n	8000de6 <__aeabi_fmul+0xce>
+ 8000df2:	ea40 000c 	orr.w	r0, r0, ip
+ 8000df6:	f093 0f00 	teq	r3, #0
+ 8000dfa:	f001 4c00 	and.w	ip, r1, #2147483648	@ 0x80000000
+ 8000dfe:	bf02      	ittt	eq
+ 8000e00:	0049      	lsleq	r1, r1, #1
+ 8000e02:	f411 0f00 	tsteq.w	r1, #8388608	@ 0x800000
+ 8000e06:	3b01      	subeq	r3, #1
+ 8000e08:	d0f9      	beq.n	8000dfe <__aeabi_fmul+0xe6>
+ 8000e0a:	ea41 010c 	orr.w	r1, r1, ip
+ 8000e0e:	e78f      	b.n	8000d30 <__aeabi_fmul+0x18>
+ 8000e10:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
+ 8000e14:	ea92 0f0c 	teq	r2, ip
+ 8000e18:	bf18      	it	ne
+ 8000e1a:	ea93 0f0c 	teqne	r3, ip
+ 8000e1e:	d00a      	beq.n	8000e36 <__aeabi_fmul+0x11e>
+ 8000e20:	f030 4c00 	bics.w	ip, r0, #2147483648	@ 0x80000000
+ 8000e24:	bf18      	it	ne
+ 8000e26:	f031 4c00 	bicsne.w	ip, r1, #2147483648	@ 0x80000000
+ 8000e2a:	d1d8      	bne.n	8000dde <__aeabi_fmul+0xc6>
+ 8000e2c:	ea80 0001 	eor.w	r0, r0, r1
+ 8000e30:	f000 4000 	and.w	r0, r0, #2147483648	@ 0x80000000
+ 8000e34:	4770      	bx	lr
+ 8000e36:	f090 0f00 	teq	r0, #0
+ 8000e3a:	bf17      	itett	ne
+ 8000e3c:	f090 4f00 	teqne	r0, #2147483648	@ 0x80000000
+ 8000e40:	4608      	moveq	r0, r1
+ 8000e42:	f091 0f00 	teqne	r1, #0
+ 8000e46:	f091 4f00 	teqne	r1, #2147483648	@ 0x80000000
+ 8000e4a:	d014      	beq.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000e4c:	ea92 0f0c 	teq	r2, ip
+ 8000e50:	d101      	bne.n	8000e56 <__aeabi_fmul+0x13e>
+ 8000e52:	0242      	lsls	r2, r0, #9
+ 8000e54:	d10f      	bne.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000e56:	ea93 0f0c 	teq	r3, ip
+ 8000e5a:	d103      	bne.n	8000e64 <__aeabi_fmul+0x14c>
+ 8000e5c:	024b      	lsls	r3, r1, #9
+ 8000e5e:	bf18      	it	ne
+ 8000e60:	4608      	movne	r0, r1
+ 8000e62:	d108      	bne.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000e64:	ea80 0001 	eor.w	r0, r0, r1
+ 8000e68:	f000 4000 	and.w	r0, r0, #2147483648	@ 0x80000000
+ 8000e6c:	f040 40fe 	orr.w	r0, r0, #2130706432	@ 0x7f000000
+ 8000e70:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000e74:	4770      	bx	lr
+ 8000e76:	f040 40fe 	orr.w	r0, r0, #2130706432	@ 0x7f000000
+ 8000e7a:	f440 0040 	orr.w	r0, r0, #12582912	@ 0xc00000
+ 8000e7e:	4770      	bx	lr
 
-08000cf8 <__aeabi_fcmpge>:
- 8000cf8:	f84d ed08 	str.w	lr, [sp, #-8]!
- 8000cfc:	f7ff ffd2 	bl	8000ca4 <__aeabi_cfrcmple>
- 8000d00:	bf94      	ite	ls
- 8000d02:	2001      	movls	r0, #1
- 8000d04:	2000      	movhi	r0, #0
- 8000d06:	f85d fb08 	ldr.w	pc, [sp], #8
- 8000d0a:	bf00      	nop
+08000e80 <__aeabi_fdiv>:
+ 8000e80:	f04f 0cff 	mov.w	ip, #255	@ 0xff
+ 8000e84:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
+ 8000e88:	bf1e      	ittt	ne
+ 8000e8a:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
+ 8000e8e:	ea92 0f0c 	teqne	r2, ip
+ 8000e92:	ea93 0f0c 	teqne	r3, ip
+ 8000e96:	d069      	beq.n	8000f6c <__aeabi_fdiv+0xec>
+ 8000e98:	eba2 0203 	sub.w	r2, r2, r3
+ 8000e9c:	ea80 0c01 	eor.w	ip, r0, r1
+ 8000ea0:	0249      	lsls	r1, r1, #9
+ 8000ea2:	ea4f 2040 	mov.w	r0, r0, lsl #9
+ 8000ea6:	d037      	beq.n	8000f18 <__aeabi_fdiv+0x98>
+ 8000ea8:	f04f 5380 	mov.w	r3, #268435456	@ 0x10000000
+ 8000eac:	ea43 1111 	orr.w	r1, r3, r1, lsr #4
+ 8000eb0:	ea43 1310 	orr.w	r3, r3, r0, lsr #4
+ 8000eb4:	f00c 4000 	and.w	r0, ip, #2147483648	@ 0x80000000
+ 8000eb8:	428b      	cmp	r3, r1
+ 8000eba:	bf38      	it	cc
+ 8000ebc:	005b      	lslcc	r3, r3, #1
+ 8000ebe:	f142 027d 	adc.w	r2, r2, #125	@ 0x7d
+ 8000ec2:	f44f 0c00 	mov.w	ip, #8388608	@ 0x800000
+ 8000ec6:	428b      	cmp	r3, r1
+ 8000ec8:	bf24      	itt	cs
+ 8000eca:	1a5b      	subcs	r3, r3, r1
+ 8000ecc:	ea40 000c 	orrcs.w	r0, r0, ip
+ 8000ed0:	ebb3 0f51 	cmp.w	r3, r1, lsr #1
+ 8000ed4:	bf24      	itt	cs
+ 8000ed6:	eba3 0351 	subcs.w	r3, r3, r1, lsr #1
+ 8000eda:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
+ 8000ede:	ebb3 0f91 	cmp.w	r3, r1, lsr #2
+ 8000ee2:	bf24      	itt	cs
+ 8000ee4:	eba3 0391 	subcs.w	r3, r3, r1, lsr #2
+ 8000ee8:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
+ 8000eec:	ebb3 0fd1 	cmp.w	r3, r1, lsr #3
+ 8000ef0:	bf24      	itt	cs
+ 8000ef2:	eba3 03d1 	subcs.w	r3, r3, r1, lsr #3
+ 8000ef6:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
+ 8000efa:	011b      	lsls	r3, r3, #4
+ 8000efc:	bf18      	it	ne
+ 8000efe:	ea5f 1c1c 	movsne.w	ip, ip, lsr #4
+ 8000f02:	d1e0      	bne.n	8000ec6 <__aeabi_fdiv+0x46>
+ 8000f04:	2afd      	cmp	r2, #253	@ 0xfd
+ 8000f06:	f63f af50 	bhi.w	8000daa <__aeabi_fmul+0x92>
+ 8000f0a:	428b      	cmp	r3, r1
+ 8000f0c:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
+ 8000f10:	bf08      	it	eq
+ 8000f12:	f020 0001 	biceq.w	r0, r0, #1
+ 8000f16:	4770      	bx	lr
+ 8000f18:	f00c 4c00 	and.w	ip, ip, #2147483648	@ 0x80000000
+ 8000f1c:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
+ 8000f20:	327f      	adds	r2, #127	@ 0x7f
+ 8000f22:	bfc2      	ittt	gt
+ 8000f24:	f1d2 03ff 	rsbsgt	r3, r2, #255	@ 0xff
+ 8000f28:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
+ 8000f2c:	4770      	bxgt	lr
+ 8000f2e:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
+ 8000f32:	f04f 0300 	mov.w	r3, #0
+ 8000f36:	3a01      	subs	r2, #1
+ 8000f38:	e737      	b.n	8000daa <__aeabi_fmul+0x92>
+ 8000f3a:	f092 0f00 	teq	r2, #0
+ 8000f3e:	f000 4c00 	and.w	ip, r0, #2147483648	@ 0x80000000
+ 8000f42:	bf02      	ittt	eq
+ 8000f44:	0040      	lsleq	r0, r0, #1
+ 8000f46:	f410 0f00 	tsteq.w	r0, #8388608	@ 0x800000
+ 8000f4a:	3a01      	subeq	r2, #1
+ 8000f4c:	d0f9      	beq.n	8000f42 <__aeabi_fdiv+0xc2>
+ 8000f4e:	ea40 000c 	orr.w	r0, r0, ip
+ 8000f52:	f093 0f00 	teq	r3, #0
+ 8000f56:	f001 4c00 	and.w	ip, r1, #2147483648	@ 0x80000000
+ 8000f5a:	bf02      	ittt	eq
+ 8000f5c:	0049      	lsleq	r1, r1, #1
+ 8000f5e:	f411 0f00 	tsteq.w	r1, #8388608	@ 0x800000
+ 8000f62:	3b01      	subeq	r3, #1
+ 8000f64:	d0f9      	beq.n	8000f5a <__aeabi_fdiv+0xda>
+ 8000f66:	ea41 010c 	orr.w	r1, r1, ip
+ 8000f6a:	e795      	b.n	8000e98 <__aeabi_fdiv+0x18>
+ 8000f6c:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
+ 8000f70:	ea92 0f0c 	teq	r2, ip
+ 8000f74:	d108      	bne.n	8000f88 <__aeabi_fdiv+0x108>
+ 8000f76:	0242      	lsls	r2, r0, #9
+ 8000f78:	f47f af7d 	bne.w	8000e76 <__aeabi_fmul+0x15e>
+ 8000f7c:	ea93 0f0c 	teq	r3, ip
+ 8000f80:	f47f af70 	bne.w	8000e64 <__aeabi_fmul+0x14c>
+ 8000f84:	4608      	mov	r0, r1
+ 8000f86:	e776      	b.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000f88:	ea93 0f0c 	teq	r3, ip
+ 8000f8c:	d104      	bne.n	8000f98 <__aeabi_fdiv+0x118>
+ 8000f8e:	024b      	lsls	r3, r1, #9
+ 8000f90:	f43f af4c 	beq.w	8000e2c <__aeabi_fmul+0x114>
+ 8000f94:	4608      	mov	r0, r1
+ 8000f96:	e76e      	b.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000f98:	f030 4c00 	bics.w	ip, r0, #2147483648	@ 0x80000000
+ 8000f9c:	bf18      	it	ne
+ 8000f9e:	f031 4c00 	bicsne.w	ip, r1, #2147483648	@ 0x80000000
+ 8000fa2:	d1ca      	bne.n	8000f3a <__aeabi_fdiv+0xba>
+ 8000fa4:	f030 4200 	bics.w	r2, r0, #2147483648	@ 0x80000000
+ 8000fa8:	f47f af5c 	bne.w	8000e64 <__aeabi_fmul+0x14c>
+ 8000fac:	f031 4300 	bics.w	r3, r1, #2147483648	@ 0x80000000
+ 8000fb0:	f47f af3c 	bne.w	8000e2c <__aeabi_fmul+0x114>
+ 8000fb4:	e75f      	b.n	8000e76 <__aeabi_fmul+0x15e>
+ 8000fb6:	bf00      	nop
 
-08000d0c <__aeabi_fcmpgt>:
- 8000d0c:	f84d ed08 	str.w	lr, [sp, #-8]!
- 8000d10:	f7ff ffc8 	bl	8000ca4 <__aeabi_cfrcmple>
- 8000d14:	bf34      	ite	cc
- 8000d16:	2001      	movcc	r0, #1
- 8000d18:	2000      	movcs	r0, #0
- 8000d1a:	f85d fb08 	ldr.w	pc, [sp], #8
- 8000d1e:	bf00      	nop
+08000fb8 <__gesf2>:
+ 8000fb8:	f04f 3cff 	mov.w	ip, #4294967295
+ 8000fbc:	e006      	b.n	8000fcc <__cmpsf2+0x4>
+ 8000fbe:	bf00      	nop
 
-08000d20 <__aeabi_fcmpun>:
- 8000d20:	ea4f 0240 	mov.w	r2, r0, lsl #1
- 8000d24:	ea4f 0341 	mov.w	r3, r1, lsl #1
- 8000d28:	ea7f 6c22 	mvns.w	ip, r2, asr #24
- 8000d2c:	d102      	bne.n	8000d34 <__aeabi_fcmpun+0x14>
- 8000d2e:	ea5f 2c40 	movs.w	ip, r0, lsl #9
- 8000d32:	d108      	bne.n	8000d46 <__aeabi_fcmpun+0x26>
- 8000d34:	ea7f 6c23 	mvns.w	ip, r3, asr #24
- 8000d38:	d102      	bne.n	8000d40 <__aeabi_fcmpun+0x20>
- 8000d3a:	ea5f 2c41 	movs.w	ip, r1, lsl #9
- 8000d3e:	d102      	bne.n	8000d46 <__aeabi_fcmpun+0x26>
- 8000d40:	f04f 0000 	mov.w	r0, #0
- 8000d44:	4770      	bx	lr
- 8000d46:	f04f 0001 	mov.w	r0, #1
- 8000d4a:	4770      	bx	lr
+08000fc0 <__lesf2>:
+ 8000fc0:	f04f 0c01 	mov.w	ip, #1
+ 8000fc4:	e002      	b.n	8000fcc <__cmpsf2+0x4>
+ 8000fc6:	bf00      	nop
 
-08000d4c <__aeabi_f2iz>:
- 8000d4c:	ea4f 0240 	mov.w	r2, r0, lsl #1
- 8000d50:	f1b2 4ffe 	cmp.w	r2, #2130706432	@ 0x7f000000
- 8000d54:	d30f      	bcc.n	8000d76 <__aeabi_f2iz+0x2a>
- 8000d56:	f04f 039e 	mov.w	r3, #158	@ 0x9e
- 8000d5a:	ebb3 6212 	subs.w	r2, r3, r2, lsr #24
- 8000d5e:	d90d      	bls.n	8000d7c <__aeabi_f2iz+0x30>
- 8000d60:	ea4f 2300 	mov.w	r3, r0, lsl #8
- 8000d64:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
- 8000d68:	f010 4f00 	tst.w	r0, #2147483648	@ 0x80000000
- 8000d6c:	fa23 f002 	lsr.w	r0, r3, r2
- 8000d70:	bf18      	it	ne
- 8000d72:	4240      	negne	r0, r0
- 8000d74:	4770      	bx	lr
- 8000d76:	f04f 0000 	mov.w	r0, #0
- 8000d7a:	4770      	bx	lr
- 8000d7c:	f112 0f61 	cmn.w	r2, #97	@ 0x61
- 8000d80:	d101      	bne.n	8000d86 <__aeabi_f2iz+0x3a>
- 8000d82:	0242      	lsls	r2, r0, #9
- 8000d84:	d105      	bne.n	8000d92 <__aeabi_f2iz+0x46>
- 8000d86:	f010 4000 	ands.w	r0, r0, #2147483648	@ 0x80000000
- 8000d8a:	bf08      	it	eq
- 8000d8c:	f06f 4000 	mvneq.w	r0, #2147483648	@ 0x80000000
- 8000d90:	4770      	bx	lr
- 8000d92:	f04f 0000 	mov.w	r0, #0
- 8000d96:	4770      	bx	lr
+08000fc8 <__cmpsf2>:
+ 8000fc8:	f04f 0c01 	mov.w	ip, #1
+ 8000fcc:	f84d cd04 	str.w	ip, [sp, #-4]!
+ 8000fd0:	ea4f 0240 	mov.w	r2, r0, lsl #1
+ 8000fd4:	ea4f 0341 	mov.w	r3, r1, lsl #1
+ 8000fd8:	ea7f 6c22 	mvns.w	ip, r2, asr #24
+ 8000fdc:	bf18      	it	ne
+ 8000fde:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
+ 8000fe2:	d011      	beq.n	8001008 <__cmpsf2+0x40>
+ 8000fe4:	b001      	add	sp, #4
+ 8000fe6:	ea52 0c53 	orrs.w	ip, r2, r3, lsr #1
+ 8000fea:	bf18      	it	ne
+ 8000fec:	ea90 0f01 	teqne	r0, r1
+ 8000ff0:	bf58      	it	pl
+ 8000ff2:	ebb2 0003 	subspl.w	r0, r2, r3
+ 8000ff6:	bf88      	it	hi
+ 8000ff8:	17c8      	asrhi	r0, r1, #31
+ 8000ffa:	bf38      	it	cc
+ 8000ffc:	ea6f 70e1 	mvncc.w	r0, r1, asr #31
+ 8001000:	bf18      	it	ne
+ 8001002:	f040 0001 	orrne.w	r0, r0, #1
+ 8001006:	4770      	bx	lr
+ 8001008:	ea7f 6c22 	mvns.w	ip, r2, asr #24
+ 800100c:	d102      	bne.n	8001014 <__cmpsf2+0x4c>
+ 800100e:	ea5f 2c40 	movs.w	ip, r0, lsl #9
+ 8001012:	d105      	bne.n	8001020 <__cmpsf2+0x58>
+ 8001014:	ea7f 6c23 	mvns.w	ip, r3, asr #24
+ 8001018:	d1e4      	bne.n	8000fe4 <__cmpsf2+0x1c>
+ 800101a:	ea5f 2c41 	movs.w	ip, r1, lsl #9
+ 800101e:	d0e1      	beq.n	8000fe4 <__cmpsf2+0x1c>
+ 8001020:	f85d 0b04 	ldr.w	r0, [sp], #4
+ 8001024:	4770      	bx	lr
+ 8001026:	bf00      	nop
 
-08000d98 <AD5934_SetRegisterValue>:
+08001028 <__aeabi_cfrcmple>:
+ 8001028:	4684      	mov	ip, r0
+ 800102a:	4608      	mov	r0, r1
+ 800102c:	4661      	mov	r1, ip
+ 800102e:	e7ff      	b.n	8001030 <__aeabi_cfcmpeq>
+
+08001030 <__aeabi_cfcmpeq>:
+ 8001030:	b50f      	push	{r0, r1, r2, r3, lr}
+ 8001032:	f7ff ffc9 	bl	8000fc8 <__cmpsf2>
+ 8001036:	2800      	cmp	r0, #0
+ 8001038:	bf48      	it	mi
+ 800103a:	f110 0f00 	cmnmi.w	r0, #0
+ 800103e:	bd0f      	pop	{r0, r1, r2, r3, pc}
+
+08001040 <__aeabi_fcmpeq>:
+ 8001040:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 8001044:	f7ff fff4 	bl	8001030 <__aeabi_cfcmpeq>
+ 8001048:	bf0c      	ite	eq
+ 800104a:	2001      	moveq	r0, #1
+ 800104c:	2000      	movne	r0, #0
+ 800104e:	f85d fb08 	ldr.w	pc, [sp], #8
+ 8001052:	bf00      	nop
+
+08001054 <__aeabi_fcmplt>:
+ 8001054:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 8001058:	f7ff ffea 	bl	8001030 <__aeabi_cfcmpeq>
+ 800105c:	bf34      	ite	cc
+ 800105e:	2001      	movcc	r0, #1
+ 8001060:	2000      	movcs	r0, #0
+ 8001062:	f85d fb08 	ldr.w	pc, [sp], #8
+ 8001066:	bf00      	nop
+
+08001068 <__aeabi_fcmple>:
+ 8001068:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 800106c:	f7ff ffe0 	bl	8001030 <__aeabi_cfcmpeq>
+ 8001070:	bf94      	ite	ls
+ 8001072:	2001      	movls	r0, #1
+ 8001074:	2000      	movhi	r0, #0
+ 8001076:	f85d fb08 	ldr.w	pc, [sp], #8
+ 800107a:	bf00      	nop
+
+0800107c <__aeabi_fcmpge>:
+ 800107c:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 8001080:	f7ff ffd2 	bl	8001028 <__aeabi_cfrcmple>
+ 8001084:	bf94      	ite	ls
+ 8001086:	2001      	movls	r0, #1
+ 8001088:	2000      	movhi	r0, #0
+ 800108a:	f85d fb08 	ldr.w	pc, [sp], #8
+ 800108e:	bf00      	nop
+
+08001090 <__aeabi_fcmpgt>:
+ 8001090:	f84d ed08 	str.w	lr, [sp, #-8]!
+ 8001094:	f7ff ffc8 	bl	8001028 <__aeabi_cfrcmple>
+ 8001098:	bf34      	ite	cc
+ 800109a:	2001      	movcc	r0, #1
+ 800109c:	2000      	movcs	r0, #0
+ 800109e:	f85d fb08 	ldr.w	pc, [sp], #8
+ 80010a2:	bf00      	nop
+
+080010a4 <__aeabi_fcmpun>:
+ 80010a4:	ea4f 0240 	mov.w	r2, r0, lsl #1
+ 80010a8:	ea4f 0341 	mov.w	r3, r1, lsl #1
+ 80010ac:	ea7f 6c22 	mvns.w	ip, r2, asr #24
+ 80010b0:	d102      	bne.n	80010b8 <__aeabi_fcmpun+0x14>
+ 80010b2:	ea5f 2c40 	movs.w	ip, r0, lsl #9
+ 80010b6:	d108      	bne.n	80010ca <__aeabi_fcmpun+0x26>
+ 80010b8:	ea7f 6c23 	mvns.w	ip, r3, asr #24
+ 80010bc:	d102      	bne.n	80010c4 <__aeabi_fcmpun+0x20>
+ 80010be:	ea5f 2c41 	movs.w	ip, r1, lsl #9
+ 80010c2:	d102      	bne.n	80010ca <__aeabi_fcmpun+0x26>
+ 80010c4:	f04f 0000 	mov.w	r0, #0
+ 80010c8:	4770      	bx	lr
+ 80010ca:	f04f 0001 	mov.w	r0, #1
+ 80010ce:	4770      	bx	lr
+
+080010d0 <__aeabi_f2iz>:
+ 80010d0:	ea4f 0240 	mov.w	r2, r0, lsl #1
+ 80010d4:	f1b2 4ffe 	cmp.w	r2, #2130706432	@ 0x7f000000
+ 80010d8:	d30f      	bcc.n	80010fa <__aeabi_f2iz+0x2a>
+ 80010da:	f04f 039e 	mov.w	r3, #158	@ 0x9e
+ 80010de:	ebb3 6212 	subs.w	r2, r3, r2, lsr #24
+ 80010e2:	d90d      	bls.n	8001100 <__aeabi_f2iz+0x30>
+ 80010e4:	ea4f 2300 	mov.w	r3, r0, lsl #8
+ 80010e8:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
+ 80010ec:	f010 4f00 	tst.w	r0, #2147483648	@ 0x80000000
+ 80010f0:	fa23 f002 	lsr.w	r0, r3, r2
+ 80010f4:	bf18      	it	ne
+ 80010f6:	4240      	negne	r0, r0
+ 80010f8:	4770      	bx	lr
+ 80010fa:	f04f 0000 	mov.w	r0, #0
+ 80010fe:	4770      	bx	lr
+ 8001100:	f112 0f61 	cmn.w	r2, #97	@ 0x61
+ 8001104:	d101      	bne.n	800110a <__aeabi_f2iz+0x3a>
+ 8001106:	0242      	lsls	r2, r0, #9
+ 8001108:	d105      	bne.n	8001116 <__aeabi_f2iz+0x46>
+ 800110a:	f010 4000 	ands.w	r0, r0, #2147483648	@ 0x80000000
+ 800110e:	bf08      	it	eq
+ 8001110:	f06f 4000 	mvneq.w	r0, #2147483648	@ 0x80000000
+ 8001114:	4770      	bx	lr
+ 8001116:	f04f 0000 	mov.w	r0, #0
+ 800111a:	4770      	bx	lr
+
+0800111c <AD5934_SetRegisterValue>:
 * @param numberOfBytes - Number of bytes to be written in the register
 *
 * @return None.
 ******************************************************************************/
 void AD5934_SetRegisterValue(uint8_t registerAddress, uint32_t registerValue, uint8_t numberOfBytes)
 {
- 8000d98:	b580      	push	{r7, lr}
- 8000d9a:	b086      	sub	sp, #24
- 8000d9c:	af02      	add	r7, sp, #8
- 8000d9e:	4603      	mov	r3, r0
- 8000da0:	6039      	str	r1, [r7, #0]
- 8000da2:	71fb      	strb	r3, [r7, #7]
- 8000da4:	4613      	mov	r3, r2
- 8000da6:	71bb      	strb	r3, [r7, #6]
+ 800111c:	b580      	push	{r7, lr}
+ 800111e:	b086      	sub	sp, #24
+ 8001120:	af02      	add	r7, sp, #8
+ 8001122:	4603      	mov	r3, r0
+ 8001124:	6039      	str	r1, [r7, #0]
+ 8001126:	71fb      	strb	r3, [r7, #7]
+ 8001128:	4613      	mov	r3, r2
+ 800112a:	71bb      	strb	r3, [r7, #6]
 	uint8_t writeData[2] = {0, 0};
- 8000da8:	2300      	movs	r3, #0
- 8000daa:	81bb      	strh	r3, [r7, #12]
+ 800112c:	2300      	movs	r3, #0
+ 800112e:	81bb      	strh	r3, [r7, #12]
 	HAL_StatusTypeDef status;
 	union Bytes2Long AD5934_reg;
 
 	AD5934_reg.number = registerValue;
- 8000dac:	683b      	ldr	r3, [r7, #0]
- 8000dae:	60bb      	str	r3, [r7, #8]
+ 8001130:	683b      	ldr	r3, [r7, #0]
+ 8001132:	60bb      	str	r3, [r7, #8]
 
 	for (uint8_t i = 0; i < numberOfBytes; i++)
- 8000db0:	2300      	movs	r3, #0
- 8000db2:	73fb      	strb	r3, [r7, #15]
- 8000db4:	e018      	b.n	8000de8 <AD5934_SetRegisterValue+0x50>
+ 8001134:	2300      	movs	r3, #0
+ 8001136:	73fb      	strb	r3, [r7, #15]
+ 8001138:	e018      	b.n	800116c <AD5934_SetRegisterValue+0x50>
 	{
 		writeData[0] = registerAddress - i;
- 8000db6:	79fa      	ldrb	r2, [r7, #7]
- 8000db8:	7bfb      	ldrb	r3, [r7, #15]
- 8000dba:	1ad3      	subs	r3, r2, r3
- 8000dbc:	b2db      	uxtb	r3, r3
- 8000dbe:	733b      	strb	r3, [r7, #12]
+ 800113a:	79fa      	ldrb	r2, [r7, #7]
+ 800113c:	7bfb      	ldrb	r3, [r7, #15]
+ 800113e:	1ad3      	subs	r3, r2, r3
+ 8001140:	b2db      	uxtb	r3, r3
+ 8001142:	733b      	strb	r3, [r7, #12]
 		writeData[1] = AD5934_reg.bytes[i];
- 8000dc0:	7bfb      	ldrb	r3, [r7, #15]
- 8000dc2:	3310      	adds	r3, #16
- 8000dc4:	443b      	add	r3, r7
- 8000dc6:	f813 3c08 	ldrb.w	r3, [r3, #-8]
- 8000dca:	737b      	strb	r3, [r7, #13]
+ 8001144:	7bfb      	ldrb	r3, [r7, #15]
+ 8001146:	3310      	adds	r3, #16
+ 8001148:	443b      	add	r3, r7
+ 800114a:	f813 3c08 	ldrb.w	r3, [r3, #-8]
+ 800114e:	737b      	strb	r3, [r7, #13]
 		status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
- 8000dcc:	f107 020c 	add.w	r2, r7, #12
- 8000dd0:	2305      	movs	r3, #5
- 8000dd2:	9300      	str	r3, [sp, #0]
- 8000dd4:	2302      	movs	r3, #2
- 8000dd6:	211a      	movs	r1, #26
- 8000dd8:	4807      	ldr	r0, [pc, #28]	@ (8000df8 <AD5934_SetRegisterValue+0x60>)
- 8000dda:	f002 fdc5 	bl	8003968 <HAL_I2C_Master_Transmit>
- 8000dde:	4603      	mov	r3, r0
- 8000de0:	73bb      	strb	r3, [r7, #14]
+ 8001150:	f107 020c 	add.w	r2, r7, #12
+ 8001154:	2305      	movs	r3, #5
+ 8001156:	9300      	str	r3, [sp, #0]
+ 8001158:	2302      	movs	r3, #2
+ 800115a:	211a      	movs	r1, #26
+ 800115c:	4807      	ldr	r0, [pc, #28]	@ (800117c <AD5934_SetRegisterValue+0x60>)
+ 800115e:	f003 fe17 	bl	8004d90 <HAL_I2C_Master_Transmit>
+ 8001162:	4603      	mov	r3, r0
+ 8001164:	73bb      	strb	r3, [r7, #14]
 	for (uint8_t i = 0; i < numberOfBytes; i++)
- 8000de2:	7bfb      	ldrb	r3, [r7, #15]
- 8000de4:	3301      	adds	r3, #1
- 8000de6:	73fb      	strb	r3, [r7, #15]
- 8000de8:	7bfa      	ldrb	r2, [r7, #15]
- 8000dea:	79bb      	ldrb	r3, [r7, #6]
- 8000dec:	429a      	cmp	r2, r3
- 8000dee:	d3e2      	bcc.n	8000db6 <AD5934_SetRegisterValue+0x1e>
+ 8001166:	7bfb      	ldrb	r3, [r7, #15]
+ 8001168:	3301      	adds	r3, #1
+ 800116a:	73fb      	strb	r3, [r7, #15]
+ 800116c:	7bfa      	ldrb	r2, [r7, #15]
+ 800116e:	79bb      	ldrb	r3, [r7, #6]
+ 8001170:	429a      	cmp	r2, r3
+ 8001172:	d3e2      	bcc.n	800113a <AD5934_SetRegisterValue+0x1e>
 	}
 
 	return;
- 8000df0:	bf00      	nop
+ 8001174:	bf00      	nop
 
 }
- 8000df2:	3710      	adds	r7, #16
- 8000df4:	46bd      	mov	sp, r7
- 8000df6:	bd80      	pop	{r7, pc}
- 8000df8:	20000228 	.word	0x20000228
+ 8001176:	3710      	adds	r7, #16
+ 8001178:	46bd      	mov	sp, r7
+ 800117a:	bd80      	pop	{r7, pc}
+ 800117c:	20000654 	.word	0x20000654
 
-08000dfc <AD5934_GetRegisterValue>:
+08001180 <AD5934_GetRegisterValue>:
 * @param numberOfBytes - Number of bytes to be read from the register.
 *
 * @return Register value.
 ******************************************************************************/
 uint32_t AD5934_GetRegisterValue(uint8_t registerAddress, uint8_t numberOfBytes)
 {
- 8000dfc:	b580      	push	{r7, lr}
- 8000dfe:	b088      	sub	sp, #32
- 8000e00:	af02      	add	r7, sp, #8
- 8000e02:	4603      	mov	r3, r0
- 8000e04:	460a      	mov	r2, r1
- 8000e06:	71fb      	strb	r3, [r7, #7]
- 8000e08:	4613      	mov	r3, r2
- 8000e0a:	71bb      	strb	r3, [r7, #6]
+ 8001180:	b580      	push	{r7, lr}
+ 8001182:	b088      	sub	sp, #32
+ 8001184:	af02      	add	r7, sp, #8
+ 8001186:	4603      	mov	r3, r0
+ 8001188:	460a      	mov	r2, r1
+ 800118a:	71fb      	strb	r3, [r7, #7]
+ 800118c:	4613      	mov	r3, r2
+ 800118e:	71bb      	strb	r3, [r7, #6]
     uint8_t readData[1]   = {0};
- 8000e0c:	2300      	movs	r3, #0
- 8000e0e:	753b      	strb	r3, [r7, #20]
+ 8001190:	2300      	movs	r3, #0
+ 8001192:	753b      	strb	r3, [r7, #20]
     uint8_t writeData[2]; //= {AD5934_ADDR_POINTER, registerAddress};
     union Bytes2Long AD5934_reg;
     HAL_StatusTypeDef status;
 
     if(numberOfBytes > 4)
- 8000e10:	79bb      	ldrb	r3, [r7, #6]
- 8000e12:	2b04      	cmp	r3, #4
- 8000e14:	d902      	bls.n	8000e1c <AD5934_GetRegisterValue+0x20>
+ 8001194:	79bb      	ldrb	r3, [r7, #6]
+ 8001196:	2b04      	cmp	r3, #4
+ 8001198:	d902      	bls.n	80011a0 <AD5934_GetRegisterValue+0x20>
     	return 0xFFFFFFFF; //Overflow
- 8000e16:	f04f 33ff 	mov.w	r3, #4294967295
- 8000e1a:	e031      	b.n	8000e80 <AD5934_GetRegisterValue+0x84>
+ 800119a:	f04f 33ff 	mov.w	r3, #4294967295
+ 800119e:	e031      	b.n	8001204 <AD5934_GetRegisterValue+0x84>
 
     AD5934_reg.number = 0;
- 8000e1c:	2300      	movs	r3, #0
- 8000e1e:	60fb      	str	r3, [r7, #12]
+ 80011a0:	2300      	movs	r3, #0
+ 80011a2:	60fb      	str	r3, [r7, #12]
     for (uint8_t i = 0; i < numberOfBytes; i++)
- 8000e20:	2300      	movs	r3, #0
- 8000e22:	75fb      	strb	r3, [r7, #23]
- 8000e24:	e027      	b.n	8000e76 <AD5934_GetRegisterValue+0x7a>
+ 80011a4:	2300      	movs	r3, #0
+ 80011a6:	75fb      	strb	r3, [r7, #23]
+ 80011a8:	e027      	b.n	80011fa <AD5934_GetRegisterValue+0x7a>
     {
     	writeData[0] = AD5934_ADDR_POINTER;
- 8000e26:	23b0      	movs	r3, #176	@ 0xb0
- 8000e28:	743b      	strb	r3, [r7, #16]
+ 80011aa:	23b0      	movs	r3, #176	@ 0xb0
+ 80011ac:	743b      	strb	r3, [r7, #16]
     	writeData[1] = registerAddress - i;
- 8000e2a:	79fa      	ldrb	r2, [r7, #7]
- 8000e2c:	7dfb      	ldrb	r3, [r7, #23]
- 8000e2e:	1ad3      	subs	r3, r2, r3
- 8000e30:	b2db      	uxtb	r3, r3
- 8000e32:	747b      	strb	r3, [r7, #17]
+ 80011ae:	79fa      	ldrb	r2, [r7, #7]
+ 80011b0:	7dfb      	ldrb	r3, [r7, #23]
+ 80011b2:	1ad3      	subs	r3, r2, r3
+ 80011b4:	b2db      	uxtb	r3, r3
+ 80011b6:	747b      	strb	r3, [r7, #17]
     	status = HAL_I2C_Master_Transmit(&hi2c2, AD5934_I2C_ADDRESS, writeData, 2, 5);
- 8000e34:	f107 0210 	add.w	r2, r7, #16
- 8000e38:	2305      	movs	r3, #5
- 8000e3a:	9300      	str	r3, [sp, #0]
- 8000e3c:	2302      	movs	r3, #2
- 8000e3e:	211a      	movs	r1, #26
- 8000e40:	4811      	ldr	r0, [pc, #68]	@ (8000e88 <AD5934_GetRegisterValue+0x8c>)
- 8000e42:	f002 fd91 	bl	8003968 <HAL_I2C_Master_Transmit>
- 8000e46:	4603      	mov	r3, r0
- 8000e48:	75bb      	strb	r3, [r7, #22]
+ 80011b8:	f107 0210 	add.w	r2, r7, #16
+ 80011bc:	2305      	movs	r3, #5
+ 80011be:	9300      	str	r3, [sp, #0]
+ 80011c0:	2302      	movs	r3, #2
+ 80011c2:	211a      	movs	r1, #26
+ 80011c4:	4811      	ldr	r0, [pc, #68]	@ (800120c <AD5934_GetRegisterValue+0x8c>)
+ 80011c6:	f003 fde3 	bl	8004d90 <HAL_I2C_Master_Transmit>
+ 80011ca:	4603      	mov	r3, r0
+ 80011cc:	75bb      	strb	r3, [r7, #22]
 
     	//HAL_Delay(1);
     	readData[0] = 0;
- 8000e4a:	2300      	movs	r3, #0
- 8000e4c:	753b      	strb	r3, [r7, #20]
+ 80011ce:	2300      	movs	r3, #0
+ 80011d0:	753b      	strb	r3, [r7, #20]
     	status = HAL_I2C_Master_Receive(&hi2c2, AD5934_I2C_ADDRESS, readData, 1, 5);
- 8000e4e:	f107 0214 	add.w	r2, r7, #20
- 8000e52:	2305      	movs	r3, #5
- 8000e54:	9300      	str	r3, [sp, #0]
- 8000e56:	2301      	movs	r3, #1
- 8000e58:	211a      	movs	r1, #26
- 8000e5a:	480b      	ldr	r0, [pc, #44]	@ (8000e88 <AD5934_GetRegisterValue+0x8c>)
- 8000e5c:	f002 fe82 	bl	8003b64 <HAL_I2C_Master_Receive>
- 8000e60:	4603      	mov	r3, r0
- 8000e62:	75bb      	strb	r3, [r7, #22]
+ 80011d2:	f107 0214 	add.w	r2, r7, #20
+ 80011d6:	2305      	movs	r3, #5
+ 80011d8:	9300      	str	r3, [sp, #0]
+ 80011da:	2301      	movs	r3, #1
+ 80011dc:	211a      	movs	r1, #26
+ 80011de:	480b      	ldr	r0, [pc, #44]	@ (800120c <AD5934_GetRegisterValue+0x8c>)
+ 80011e0:	f003 fed4 	bl	8004f8c <HAL_I2C_Master_Receive>
+ 80011e4:	4603      	mov	r3, r0
+ 80011e6:	75bb      	strb	r3, [r7, #22]
     	AD5934_reg.bytes[i]=readData[0];
- 8000e64:	7dfb      	ldrb	r3, [r7, #23]
- 8000e66:	7d3a      	ldrb	r2, [r7, #20]
- 8000e68:	3318      	adds	r3, #24
- 8000e6a:	443b      	add	r3, r7
- 8000e6c:	f803 2c0c 	strb.w	r2, [r3, #-12]
+ 80011e8:	7dfb      	ldrb	r3, [r7, #23]
+ 80011ea:	7d3a      	ldrb	r2, [r7, #20]
+ 80011ec:	3318      	adds	r3, #24
+ 80011ee:	443b      	add	r3, r7
+ 80011f0:	f803 2c0c 	strb.w	r2, [r3, #-12]
     for (uint8_t i = 0; i < numberOfBytes; i++)
- 8000e70:	7dfb      	ldrb	r3, [r7, #23]
- 8000e72:	3301      	adds	r3, #1
- 8000e74:	75fb      	strb	r3, [r7, #23]
- 8000e76:	7dfa      	ldrb	r2, [r7, #23]
- 8000e78:	79bb      	ldrb	r3, [r7, #6]
- 8000e7a:	429a      	cmp	r2, r3
- 8000e7c:	d3d3      	bcc.n	8000e26 <AD5934_GetRegisterValue+0x2a>
+ 80011f4:	7dfb      	ldrb	r3, [r7, #23]
+ 80011f6:	3301      	adds	r3, #1
+ 80011f8:	75fb      	strb	r3, [r7, #23]
+ 80011fa:	7dfa      	ldrb	r2, [r7, #23]
+ 80011fc:	79bb      	ldrb	r3, [r7, #6]
+ 80011fe:	429a      	cmp	r2, r3
+ 8001200:	d3d3      	bcc.n	80011aa <AD5934_GetRegisterValue+0x2a>
     /*
     AD5934_value.byte[0] = (uint16_t)(AD5934_reg.number & 0x0000FFFF) + 2048;
     AD5934_value.ints[1] = (uint16_t)((AD5934_reg.number & 0xFFFF0000)>>16) + 2048;
 	*/
 
     return AD5934_reg.number;
- 8000e7e:	68fb      	ldr	r3, [r7, #12]
+ 8001202:	68fb      	ldr	r3, [r7, #12]
 }
- 8000e80:	4618      	mov	r0, r3
- 8000e82:	3718      	adds	r7, #24
- 8000e84:	46bd      	mov	sp, r7
- 8000e86:	bd80      	pop	{r7, pc}
- 8000e88:	20000228 	.word	0x20000228
+ 8001204:	4618      	mov	r0, r3
+ 8001206:	3718      	adds	r7, #24
+ 8001208:	46bd      	mov	sp, r7
+ 800120a:	bd80      	pop	{r7, pc}
+ 800120c:	20000654 	.word	0x20000654
 
-08000e8c <AD5934_Init>:
+08001210 <AD5934_Init>:
 * @param None.
 *
 * @return None.
 ******************************************************************************/
 void AD5934_Init(void)
 {
- 8000e8c:	b580      	push	{r7, lr}
- 8000e8e:	af00      	add	r7, sp, #0
+ 8001210:	b580      	push	{r7, lr}
+ 8001212:	af00      	add	r7, sp, #0
 	/************ Config Sweep******************/
 
 	// Place AD5934 in reset
 	AD5934_SetRegisterValue(AD5934_CONTROL_REG_LB, (AD5934_CONTROL_FUNCTION(AD5934_RESET)), 1);
- 8000e90:	2201      	movs	r2, #1
- 8000e92:	f44f 7180 	mov.w	r1, #256	@ 0x100
- 8000e96:	2081      	movs	r0, #129	@ 0x81
- 8000e98:	f7ff ff7e 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001214:	2201      	movs	r2, #1
+ 8001216:	f44f 7180 	mov.w	r1, #256	@ 0x100
+ 800121a:	2081      	movs	r0, #129	@ 0x81
+ 800121c:	f7ff ff7e 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Configure starting frequency
 	AD5934_SetRegisterValue(AD5934_START_FREQ_REG_LB, AD5934_FREQ_1K590HZ, 3);
- 8000e9c:	2203      	movs	r2, #3
- 8000e9e:	490a      	ldr	r1, [pc, #40]	@ (8000ec8 <AD5934_Init+0x3c>)
- 8000ea0:	2084      	movs	r0, #132	@ 0x84
- 8000ea2:	f7ff ff79 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001220:	2203      	movs	r2, #3
+ 8001222:	490a      	ldr	r1, [pc, #40]	@ (800124c <AD5934_Init+0x3c>)
+ 8001224:	2084      	movs	r0, #132	@ 0x84
+ 8001226:	f7ff ff79 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Configure frequency increment step
 	AD5934_SetRegisterValue(AD5934_FREQ_INCR_REG_LB, AD5934_FREQ_0HZ, 3);
- 8000ea6:	2203      	movs	r2, #3
- 8000ea8:	2100      	movs	r1, #0
- 8000eaa:	2087      	movs	r0, #135	@ 0x87
- 8000eac:	f7ff ff74 	bl	8000d98 <AD5934_SetRegisterValue>
+ 800122a:	2203      	movs	r2, #3
+ 800122c:	2100      	movs	r1, #0
+ 800122e:	2087      	movs	r0, #135	@ 0x87
+ 8001230:	f7ff ff74 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Configure number of steps
 	AD5934_SetRegisterValue(AD5934_NR_INCR_REG_LB, AD5934_STEP_FREQ_0, 2);
- 8000eb0:	2202      	movs	r2, #2
- 8000eb2:	2100      	movs	r1, #0
- 8000eb4:	2089      	movs	r0, #137	@ 0x89
- 8000eb6:	f7ff ff6f 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001234:	2202      	movs	r2, #2
+ 8001236:	2100      	movs	r1, #0
+ 8001238:	2089      	movs	r0, #137	@ 0x89
+ 800123a:	f7ff ff6f 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Set 128 Settling Time
 	AD5934_SetRegisterValue(AD5934_NR_SETTLE_REG_LB, AD5934_SETTLING_TIME_0S01,  2);
- 8000eba:	2202      	movs	r2, #2
- 8000ebc:	210c      	movs	r1, #12
- 8000ebe:	208b      	movs	r0, #139	@ 0x8b
- 8000ec0:	f7ff ff6a 	bl	8000d98 <AD5934_SetRegisterValue>
+ 800123e:	2202      	movs	r2, #2
+ 8001240:	210c      	movs	r1, #12
+ 8001242:	208b      	movs	r0, #139	@ 0x8b
+ 8001244:	f7ff ff6a 	bl	800111c <AD5934_SetRegisterValue>
 
 }
- 8000ec4:	bf00      	nop
- 8000ec6:	bd80      	pop	{r7, pc}
- 8000ec8:	003419e3 	.word	0x003419e3
+ 8001248:	bf00      	nop
+ 800124a:	bd80      	pop	{r7, pc}
+ 800124c:	003419e3 	.word	0x003419e3
 
-08000ecc <AD5934_RestartSweep>:
+08001250 <AD5934_RestartSweep>:
 * @param None.
 *
 * @return None.
 ******************************************************************************/
 void AD5934_RestartSweep(void)
 {
- 8000ecc:	b580      	push	{r7, lr}
- 8000ece:	af00      	add	r7, sp, #0
+ 8001250:	b580      	push	{r7, lr}
+ 8001252:	af00      	add	r7, sp, #0
 	// Place AD5934 in standby
 	AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_STANDBY) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) |  AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
- 8000ed0:	2201      	movs	r2, #1
- 8000ed2:	21b4      	movs	r1, #180	@ 0xb4
- 8000ed4:	2080      	movs	r0, #128	@ 0x80
- 8000ed6:	f7ff ff5f 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001254:	2201      	movs	r2, #1
+ 8001256:	21b4      	movs	r1, #180	@ 0xb4
+ 8001258:	2080      	movs	r0, #128	@ 0x80
+ 800125a:	f7ff ff5f 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Initialize starting frequency, Start frequency sweep, standby
 	AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, ((AD5934_CONTROL_FUNCTION(AD5934_INIT_START_FREQ)) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) |  AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
- 8000eda:	2201      	movs	r2, #1
- 8000edc:	2114      	movs	r1, #20
- 8000ede:	2080      	movs	r0, #128	@ 0x80
- 8000ee0:	f7ff ff5a 	bl	8000d98 <AD5934_SetRegisterValue>
+ 800125e:	2201      	movs	r2, #1
+ 8001260:	2114      	movs	r1, #20
+ 8001262:	2080      	movs	r0, #128	@ 0x80
+ 8001264:	f7ff ff5a 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Configure Range Output, PGA gain andPlace AD5934 in sweep
 	AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_START_FREQ_SWEEP) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) |  AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
- 8000ee4:	2201      	movs	r2, #1
- 8000ee6:	2124      	movs	r1, #36	@ 0x24
- 8000ee8:	2080      	movs	r0, #128	@ 0x80
- 8000eea:	f7ff ff55 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001268:	2201      	movs	r2, #1
+ 800126a:	2124      	movs	r1, #36	@ 0x24
+ 800126c:	2080      	movs	r0, #128	@ 0x80
+ 800126e:	f7ff ff55 	bl	800111c <AD5934_SetRegisterValue>
 
 	// Wait for data to be valid
 	AD5934_Wait_For_Data_Valid();
- 8000eee:	f000 fc37 	bl	8001760 <AD5934_Wait_For_Data_Valid>
+ 8001272:	f000 faef 	bl	8001854 <AD5934_Wait_For_Data_Valid>
 
 	// Power Down
 	AD5934_SetRegisterValue(AD5934_CONTROL_REG_HB, (AD5934_CONTROL_FUNCTION(AD5934_POWER_DOWN) | AD5934_CONTROL_RANGE(AD5934_400mVpp_RANGE) |  AD5934_PGA_GAIN(AD5934_PGA_GAIN_X5)), 1);
- 8000ef2:	2201      	movs	r2, #1
- 8000ef4:	21a4      	movs	r1, #164	@ 0xa4
- 8000ef6:	2080      	movs	r0, #128	@ 0x80
- 8000ef8:	f7ff ff4e 	bl	8000d98 <AD5934_SetRegisterValue>
+ 8001276:	2201      	movs	r2, #1
+ 8001278:	21a4      	movs	r1, #164	@ 0xa4
+ 800127a:	2080      	movs	r0, #128	@ 0x80
+ 800127c:	f7ff ff4e 	bl	800111c <AD5934_SetRegisterValue>
 
 }
- 8000efc:	bf00      	nop
- 8000efe:	bd80      	pop	{r7, pc}
+ 8001280:	bf00      	nop
+ 8001282:	bd80      	pop	{r7, pc}
 
-08000f00 <AD5934_Sweep>:
+08001284 <AD5934_Sweep>:
 * @param:   channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC
 *
 * @return Real(int16) and Imaginary(int16) numbers into a int32.
 ******************************************************************************/
 uint32_t AD5934_Sweep(void)
 {
- 8000f00:	b580      	push	{r7, lr}
- 8000f02:	b082      	sub	sp, #8
- 8000f04:	af00      	add	r7, sp, #0
+ 8001284:	b580      	push	{r7, lr}
+ 8001286:	b082      	sub	sp, #8
+ 8001288:	af00      	add	r7, sp, #0
 	int16_t real_value, imag_value;
 	uint32_t value=0;
- 8000f06:	2300      	movs	r3, #0
- 8000f08:	607b      	str	r3, [r7, #4]
+ 800128a:	2300      	movs	r3, #0
+ 800128c:	607b      	str	r3, [r7, #4]
 
 	// Restart Sweeping
 	AD5934_RestartSweep();
- 8000f0a:	f7ff ffdf 	bl	8000ecc <AD5934_RestartSweep>
+ 800128e:	f7ff ffdf 	bl	8001250 <AD5934_RestartSweep>
 
 	real_value = ((AD5934_GetRegisterValue(AD5934_REAL_REG_LB,2)));
- 8000f0e:	2102      	movs	r1, #2
- 8000f10:	2095      	movs	r0, #149	@ 0x95
- 8000f12:	f7ff ff73 	bl	8000dfc <AD5934_GetRegisterValue>
- 8000f16:	4603      	mov	r3, r0
- 8000f18:	807b      	strh	r3, [r7, #2]
+ 8001292:	2102      	movs	r1, #2
+ 8001294:	2095      	movs	r0, #149	@ 0x95
+ 8001296:	f7ff ff73 	bl	8001180 <AD5934_GetRegisterValue>
+ 800129a:	4603      	mov	r3, r0
+ 800129c:	807b      	strh	r3, [r7, #2]
 	imag_value = ((AD5934_GetRegisterValue(AD5934_IMG_REG_LB,2)));
- 8000f1a:	2102      	movs	r1, #2
- 8000f1c:	2097      	movs	r0, #151	@ 0x97
- 8000f1e:	f7ff ff6d 	bl	8000dfc <AD5934_GetRegisterValue>
- 8000f22:	4603      	mov	r3, r0
- 8000f24:	803b      	strh	r3, [r7, #0]
+ 800129e:	2102      	movs	r1, #2
+ 80012a0:	2097      	movs	r0, #151	@ 0x97
+ 80012a2:	f7ff ff6d 	bl	8001180 <AD5934_GetRegisterValue>
+ 80012a6:	4603      	mov	r3, r0
+ 80012a8:	803b      	strh	r3, [r7, #0]
 
 	// Get Real (16-bit)  and Imaginary (16-bit) values into an unsigned 32-bit
 	value = ((((uint16_t)(imag_value))<<16) | ((uint16_t)(real_value)));
- 8000f26:	883b      	ldrh	r3, [r7, #0]
- 8000f28:	041b      	lsls	r3, r3, #16
- 8000f2a:	887a      	ldrh	r2, [r7, #2]
- 8000f2c:	4313      	orrs	r3, r2
- 8000f2e:	607b      	str	r3, [r7, #4]
+ 80012aa:	883b      	ldrh	r3, [r7, #0]
+ 80012ac:	041b      	lsls	r3, r3, #16
+ 80012ae:	887a      	ldrh	r2, [r7, #2]
+ 80012b0:	4313      	orrs	r3, r2
+ 80012b2:	607b      	str	r3, [r7, #4]
 
 	return value;
- 8000f30:	687b      	ldr	r3, [r7, #4]
+ 80012b4:	687b      	ldr	r3, [r7, #4]
 }
- 8000f32:	4618      	mov	r0, r3
- 8000f34:	3708      	adds	r7, #8
- 8000f36:	46bd      	mov	sp, r7
- 8000f38:	bd80      	pop	{r7, pc}
+ 80012b6:	4618      	mov	r0, r3
+ 80012b8:	3708      	adds	r7, #8
+ 80012ba:	46bd      	mov	sp, r7
+ 80012bc:	bd80      	pop	{r7, pc}
 	...
 
-08000f3c <AD5934_GetTemperature>:
+080012c0 <AD5934_GetTemperature>:
 * @param channel - AD5934_CH_PT100 or AD5934_CH_PT1000.
 *
 * @return impedance.
 ******************************************************************************/
 float AD5934_GetTemperature(void)
 {
- 8000f3c:	b590      	push	{r4, r7, lr}
- 8000f3e:	b093      	sub	sp, #76	@ 0x4c
- 8000f40:	af00      	add	r7, sp, #0
-	uint8_t i, channel;
+ 80012c0:	b590      	push	{r4, r7, lr}
+ 80012c2:	b093      	sub	sp, #76	@ 0x4c
+ 80012c4:	af00      	add	r7, sp, #0
+	uint8_t i, ch_dut, ch_ref;
 	uint32_t sample;
 	int32_t ref_sum[2], dut_sum[2];
-	float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum;
+	float real_ref,imag_ref, real_dut, imag_dut, ratio, discriminant, mag_dut, mag_ref, ratio_mag, impedance_dut, temperature_sum, gain_factor;
 
 	if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_7) == GPIO_PIN_SET) // OFF = PT1000, ON = PT100, PA7 has internal pull-up and switch connects to GND
- 8000f42:	2180      	movs	r1, #128	@ 0x80
- 8000f44:	48aa      	ldr	r0, [pc, #680]	@ (80011f0 <AD5934_GetTemperature+0x2b4>)
- 8000f46:	f002 fb83 	bl	8003650 <HAL_GPIO_ReadPin>
- 8000f4a:	4603      	mov	r3, r0
- 8000f4c:	2b01      	cmp	r3, #1
- 8000f4e:	d103      	bne.n	8000f58 <AD5934_GetTemperature+0x1c>
-		channel = AD5934_CH_PT100;
- 8000f50:	2300      	movs	r3, #0
- 8000f52:	f887 3046 	strb.w	r3, [r7, #70]	@ 0x46
- 8000f56:	e002      	b.n	8000f5e <AD5934_GetTemperature+0x22>
+ 80012c6:	2180      	movs	r1, #128	@ 0x80
+ 80012c8:	48ab      	ldr	r0, [pc, #684]	@ (8001578 <AD5934_GetTemperature+0x2b8>)
+ 80012ca:	f003 fbd5 	bl	8004a78 <HAL_GPIO_ReadPin>
+ 80012ce:	4603      	mov	r3, r0
+ 80012d0:	2b01      	cmp	r3, #1
+ 80012d2:	d108      	bne.n	80012e6 <AD5934_GetTemperature+0x26>
+	{
+		ch_ref = AD5934_CH_REF100R_LOW_GAIN;
+ 80012d4:	2309      	movs	r3, #9
+ 80012d6:	f887 3045 	strb.w	r3, [r7, #69]	@ 0x45
+		ch_dut = AD5934_CH_RTD_LOW_GAIN; //PT100
+ 80012da:	2341      	movs	r3, #65	@ 0x41
+ 80012dc:	f887 3046 	strb.w	r3, [r7, #70]	@ 0x46
+		gain_factor = 100.0f;
+ 80012e0:	4ba6      	ldr	r3, [pc, #664]	@ (800157c <AD5934_GetTemperature+0x2bc>)
+ 80012e2:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 80012e4:	e007      	b.n	80012f6 <AD5934_GetTemperature+0x36>
+	}
 	else
-		channel = AD5934_CH_PT1000;
- 8000f58:	2301      	movs	r3, #1
- 8000f5a:	f887 3046 	strb.w	r3, [r7, #70]	@ 0x46
+	{
+		ch_ref = AD5934_CH_REF1K_MID_GAIN;
+ 80012e6:	2312      	movs	r3, #18
+ 80012e8:	f887 3045 	strb.w	r3, [r7, #69]	@ 0x45
+		ch_dut = AD5934_CH_RTD_MID_GAIN; //PT1000
+ 80012ec:	2342      	movs	r3, #66	@ 0x42
+ 80012ee:	f887 3046 	strb.w	r3, [r7, #70]	@ 0x46
+		gain_factor = 1000.0f;
+ 80012f2:	4ba3      	ldr	r3, [pc, #652]	@ (8001580 <AD5934_GetTemperature+0x2c0>)
+ 80012f4:	63bb      	str	r3, [r7, #56]	@ 0x38
+	}
 
-	ADG715_Update(channel + AD5934_CH_DELTA); // Set the Reference Resistor on board in the Analog Mux
- 8000f5e:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 8000f62:	3310      	adds	r3, #16
- 8000f64:	b2db      	uxtb	r3, r3
- 8000f66:	4618      	mov	r0, r3
- 8000f68:	f000 fc9a 	bl	80018a0 <ADG715_Update>
+	ADG715_Update(ch_ref); // Set the Reference Resistor on board in the Analog Mux
+ 80012f6:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 80012fa:	4618      	mov	r0, r3
+ 80012fc:	f000 fb4a 	bl	8001994 <ADG715_Update>
 	HAL_Delay(2); //Wait a little
- 8000f6c:	2002      	movs	r0, #2
- 8000f6e:	f001 fdf5 	bl	8002b5c <HAL_Delay>
+ 8001300:	2002      	movs	r0, #2
+ 8001302:	f001 fff1 	bl	80032e8 <HAL_Delay>
 
 	sample = AD5934_Sweep(); // Get Reference Resistor Values from ADC
- 8000f72:	f7ff ffc5 	bl	8000f00 <AD5934_Sweep>
- 8000f76:	63b8      	str	r0, [r7, #56]	@ 0x38
+ 8001306:	f7ff ffbd 	bl	8001284 <AD5934_Sweep>
+ 800130a:	6378      	str	r0, [r7, #52]	@ 0x34
 
 	// Move values in the vectors
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 8000f78:	2307      	movs	r3, #7
- 8000f7a:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8000f7e:	e01e      	b.n	8000fbe <AD5934_GetTemperature+0x82>
+ 800130c:	2307      	movs	r3, #7
+ 800130e:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001312:	e01e      	b.n	8001352 <AD5934_GetTemperature+0x92>
 	{
 		temperature_ref_samples[i][0] = temperature_ref_samples[i-1][0]; //real
- 8000f80:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000f84:	1e5a      	subs	r2, r3, #1
- 8000f86:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000f8a:	499a      	ldr	r1, [pc, #616]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000f8c:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
- 8000f90:	4a98      	ldr	r2, [pc, #608]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000f92:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
+ 8001314:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001318:	1e5a      	subs	r2, r3, #1
+ 800131a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800131e:	4999      	ldr	r1, [pc, #612]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001320:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
+ 8001324:	4a97      	ldr	r2, [pc, #604]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001326:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
 		temperature_ref_samples[i][1] = temperature_ref_samples[i-1][1]; //imag
- 8000f96:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000f9a:	3b01      	subs	r3, #1
- 8000f9c:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
- 8000fa0:	4994      	ldr	r1, [pc, #592]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000fa2:	009b      	lsls	r3, r3, #2
- 8000fa4:	440b      	add	r3, r1
- 8000fa6:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
- 8000faa:	4992      	ldr	r1, [pc, #584]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000fac:	0093      	lsls	r3, r2, #2
- 8000fae:	440b      	add	r3, r1
- 8000fb0:	4602      	mov	r2, r0
- 8000fb2:	805a      	strh	r2, [r3, #2]
+ 800132a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800132e:	3b01      	subs	r3, #1
+ 8001330:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
+ 8001334:	4993      	ldr	r1, [pc, #588]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001336:	009b      	lsls	r3, r3, #2
+ 8001338:	440b      	add	r3, r1
+ 800133a:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
+ 800133e:	4991      	ldr	r1, [pc, #580]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001340:	0093      	lsls	r3, r2, #2
+ 8001342:	440b      	add	r3, r1
+ 8001344:	4602      	mov	r2, r0
+ 8001346:	805a      	strh	r2, [r3, #2]
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 8000fb4:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000fb8:	3b01      	subs	r3, #1
- 8000fba:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8000fbe:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000fc2:	2b00      	cmp	r3, #0
- 8000fc4:	d1dc      	bne.n	8000f80 <AD5934_GetTemperature+0x44>
+ 8001348:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800134c:	3b01      	subs	r3, #1
+ 800134e:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001352:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001356:	2b00      	cmp	r3, #0
+ 8001358:	d1dc      	bne.n	8001314 <AD5934_GetTemperature+0x54>
 	}
 
 	// Read real and imaginary data
 	temperature_ref_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
- 8000fc6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8000fc8:	b21a      	sxth	r2, r3
- 8000fca:	4b8a      	ldr	r3, [pc, #552]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000fcc:	801a      	strh	r2, [r3, #0]
+ 800135a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 800135c:	b21a      	sxth	r2, r3
+ 800135e:	4b89      	ldr	r3, [pc, #548]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001360:	801a      	strh	r2, [r3, #0]
 	//temperature_ref_samples[0][1]  = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
 	temperature_ref_samples[0][1]  = (int16_t)((sample & 0xFFFF0000)>>16); //imag
- 8000fce:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8000fd0:	0c1b      	lsrs	r3, r3, #16
- 8000fd2:	b21a      	sxth	r2, r3
- 8000fd4:	4b87      	ldr	r3, [pc, #540]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000fd6:	805a      	strh	r2, [r3, #2]
+ 8001362:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8001364:	0c1b      	lsrs	r3, r3, #16
+ 8001366:	b21a      	sxth	r2, r3
+ 8001368:	4b86      	ldr	r3, [pc, #536]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 800136a:	805a      	strh	r2, [r3, #2]
 
 	// Sum values in the vectors
 	for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
- 8000fd8:	2300      	movs	r3, #0
- 8000fda:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8000fde:	2300      	movs	r3, #0
- 8000fe0:	60fb      	str	r3, [r7, #12]
- 8000fe2:	2300      	movs	r3, #0
- 8000fe4:	613b      	str	r3, [r7, #16]
- 8000fe6:	e016      	b.n	8001016 <AD5934_GetTemperature+0xda>
+ 800136c:	2300      	movs	r3, #0
+ 800136e:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001372:	2300      	movs	r3, #0
+ 8001374:	60bb      	str	r3, [r7, #8]
+ 8001376:	2300      	movs	r3, #0
+ 8001378:	60fb      	str	r3, [r7, #12]
+ 800137a:	e016      	b.n	80013aa <AD5934_GetTemperature+0xea>
 	{
 		ref_sum[0] += (int32_t)temperature_ref_samples[i][0]; //real
- 8000fe8:	68fb      	ldr	r3, [r7, #12]
- 8000fea:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
- 8000fee:	4981      	ldr	r1, [pc, #516]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8000ff0:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
- 8000ff4:	4413      	add	r3, r2
- 8000ff6:	60fb      	str	r3, [r7, #12]
+ 800137c:	68bb      	ldr	r3, [r7, #8]
+ 800137e:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
+ 8001382:	4980      	ldr	r1, [pc, #512]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001384:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
+ 8001388:	4413      	add	r3, r2
+ 800138a:	60bb      	str	r3, [r7, #8]
 		ref_sum[1] += (int32_t)temperature_ref_samples[i][1]; //imag
- 8000ff8:	693a      	ldr	r2, [r7, #16]
- 8000ffa:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8000ffe:	497d      	ldr	r1, [pc, #500]	@ (80011f4 <AD5934_GetTemperature+0x2b8>)
- 8001000:	009b      	lsls	r3, r3, #2
- 8001002:	440b      	add	r3, r1
- 8001004:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
- 8001008:	4413      	add	r3, r2
- 800100a:	613b      	str	r3, [r7, #16]
+ 800138c:	68fa      	ldr	r2, [r7, #12]
+ 800138e:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001392:	497c      	ldr	r1, [pc, #496]	@ (8001584 <AD5934_GetTemperature+0x2c4>)
+ 8001394:	009b      	lsls	r3, r3, #2
+ 8001396:	440b      	add	r3, r1
+ 8001398:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
+ 800139c:	4413      	add	r3, r2
+ 800139e:	60fb      	str	r3, [r7, #12]
 	for (i = 0, ref_sum[0]=0, ref_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
- 800100c:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8001010:	3301      	adds	r3, #1
- 8001012:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8001016:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 800101a:	2b07      	cmp	r3, #7
- 800101c:	d9e4      	bls.n	8000fe8 <AD5934_GetTemperature+0xac>
+ 80013a0:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80013a4:	3301      	adds	r3, #1
+ 80013a6:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 80013aa:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80013ae:	2b07      	cmp	r3, #7
+ 80013b0:	d9e4      	bls.n	800137c <AD5934_GetTemperature+0xbc>
 	}
 
 	real_ref = ((float)ref_sum[0])/((float)AD5934_TEMP_AVERAGES);
- 800101e:	68fb      	ldr	r3, [r7, #12]
- 8001020:	4618      	mov	r0, r3
- 8001022:	f7ff fc63 	bl	80008ec <__aeabi_i2f>
- 8001026:	4603      	mov	r3, r0
- 8001028:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 800102c:	4618      	mov	r0, r3
- 800102e:	f7ff fd65 	bl	8000afc <__aeabi_fdiv>
- 8001032:	4603      	mov	r3, r0
- 8001034:	637b      	str	r3, [r7, #52]	@ 0x34
+ 80013b2:	68bb      	ldr	r3, [r7, #8]
+ 80013b4:	4618      	mov	r0, r3
+ 80013b6:	f7ff fc5b 	bl	8000c70 <__aeabi_i2f>
+ 80013ba:	4603      	mov	r3, r0
+ 80013bc:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 80013c0:	4618      	mov	r0, r3
+ 80013c2:	f7ff fd5d 	bl	8000e80 <__aeabi_fdiv>
+ 80013c6:	4603      	mov	r3, r0
+ 80013c8:	633b      	str	r3, [r7, #48]	@ 0x30
 	imag_ref = ((float)ref_sum[1])/((float)AD5934_TEMP_AVERAGES);
- 8001036:	693b      	ldr	r3, [r7, #16]
- 8001038:	4618      	mov	r0, r3
- 800103a:	f7ff fc57 	bl	80008ec <__aeabi_i2f>
- 800103e:	4603      	mov	r3, r0
- 8001040:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 8001044:	4618      	mov	r0, r3
- 8001046:	f7ff fd59 	bl	8000afc <__aeabi_fdiv>
- 800104a:	4603      	mov	r3, r0
- 800104c:	633b      	str	r3, [r7, #48]	@ 0x30
+ 80013ca:	68fb      	ldr	r3, [r7, #12]
+ 80013cc:	4618      	mov	r0, r3
+ 80013ce:	f7ff fc4f 	bl	8000c70 <__aeabi_i2f>
+ 80013d2:	4603      	mov	r3, r0
+ 80013d4:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 80013d8:	4618      	mov	r0, r3
+ 80013da:	f7ff fd51 	bl	8000e80 <__aeabi_fdiv>
+ 80013de:	4603      	mov	r3, r0
+ 80013e0:	62fb      	str	r3, [r7, #44]	@ 0x2c
 
 	// Calculate gain factor impedance
 	mag_ref = sqrtf((real_ref * real_ref) + (imag_ref * imag_ref));
- 800104e:	6b79      	ldr	r1, [r7, #52]	@ 0x34
- 8001050:	6b78      	ldr	r0, [r7, #52]	@ 0x34
- 8001052:	f7ff fc9f 	bl	8000994 <__aeabi_fmul>
- 8001056:	4603      	mov	r3, r0
- 8001058:	461c      	mov	r4, r3
- 800105a:	6b39      	ldr	r1, [r7, #48]	@ 0x30
- 800105c:	6b38      	ldr	r0, [r7, #48]	@ 0x30
- 800105e:	f7ff fc99 	bl	8000994 <__aeabi_fmul>
- 8001062:	4603      	mov	r3, r0
- 8001064:	4619      	mov	r1, r3
- 8001066:	4620      	mov	r0, r4
- 8001068:	f7ff fb8c 	bl	8000784 <__addsf3>
- 800106c:	4603      	mov	r3, r0
- 800106e:	4618      	mov	r0, r3
- 8001070:	f004 fe7a 	bl	8005d68 <sqrtf>
- 8001074:	62f8      	str	r0, [r7, #44]	@ 0x2c
+ 80013e2:	6b39      	ldr	r1, [r7, #48]	@ 0x30
+ 80013e4:	6b38      	ldr	r0, [r7, #48]	@ 0x30
+ 80013e6:	f7ff fc97 	bl	8000d18 <__aeabi_fmul>
+ 80013ea:	4603      	mov	r3, r0
+ 80013ec:	461c      	mov	r4, r3
+ 80013ee:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 80013f0:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
+ 80013f2:	f7ff fc91 	bl	8000d18 <__aeabi_fmul>
+ 80013f6:	4603      	mov	r3, r0
+ 80013f8:	4619      	mov	r1, r3
+ 80013fa:	4620      	mov	r0, r4
+ 80013fc:	f7ff fb84 	bl	8000b08 <__addsf3>
+ 8001400:	4603      	mov	r3, r0
+ 8001402:	4618      	mov	r0, r3
+ 8001404:	f006 fa4c 	bl	80078a0 <sqrtf>
+ 8001408:	62b8      	str	r0, [r7, #40]	@ 0x28
 
-	ADG715_Update(channel);
- 8001076:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 800107a:	4618      	mov	r0, r3
- 800107c:	f000 fc10 	bl	80018a0 <ADG715_Update>
+	ADG715_Update(ch_dut);
+ 800140a:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
+ 800140e:	4618      	mov	r0, r3
+ 8001410:	f000 fac0 	bl	8001994 <ADG715_Update>
 	HAL_Delay(2);
- 8001080:	2002      	movs	r0, #2
- 8001082:	f001 fd6b 	bl	8002b5c <HAL_Delay>
+ 8001414:	2002      	movs	r0, #2
+ 8001416:	f001 ff67 	bl	80032e8 <HAL_Delay>
 
 	sample = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
- 8001086:	f7ff ff3b 	bl	8000f00 <AD5934_Sweep>
- 800108a:	63b8      	str	r0, [r7, #56]	@ 0x38
+ 800141a:	f7ff ff33 	bl	8001284 <AD5934_Sweep>
+ 800141e:	6378      	str	r0, [r7, #52]	@ 0x34
 
 
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 800108c:	2307      	movs	r3, #7
- 800108e:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8001092:	e01e      	b.n	80010d2 <AD5934_GetTemperature+0x196>
+ 8001420:	2307      	movs	r3, #7
+ 8001422:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001426:	e01e      	b.n	8001466 <AD5934_GetTemperature+0x1a6>
 	{
 		temperature_dut_samples[i][0] = temperature_dut_samples[i-1][0]; //real
- 8001094:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8001098:	1e5a      	subs	r2, r3, #1
- 800109a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 800109e:	4956      	ldr	r1, [pc, #344]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010a0:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
- 80010a4:	4a54      	ldr	r2, [pc, #336]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010a6:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
+ 8001428:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800142c:	1e5a      	subs	r2, r3, #1
+ 800142e:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001432:	4955      	ldr	r1, [pc, #340]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 8001434:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
+ 8001438:	4a53      	ldr	r2, [pc, #332]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 800143a:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
 		temperature_dut_samples[i][1] = temperature_dut_samples[i-1][1]; //imag
- 80010aa:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80010ae:	3b01      	subs	r3, #1
- 80010b0:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
- 80010b4:	4950      	ldr	r1, [pc, #320]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010b6:	009b      	lsls	r3, r3, #2
- 80010b8:	440b      	add	r3, r1
- 80010ba:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
- 80010be:	494e      	ldr	r1, [pc, #312]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010c0:	0093      	lsls	r3, r2, #2
- 80010c2:	440b      	add	r3, r1
- 80010c4:	4602      	mov	r2, r0
- 80010c6:	805a      	strh	r2, [r3, #2]
+ 800143e:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001442:	3b01      	subs	r3, #1
+ 8001444:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
+ 8001448:	494f      	ldr	r1, [pc, #316]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 800144a:	009b      	lsls	r3, r3, #2
+ 800144c:	440b      	add	r3, r1
+ 800144e:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
+ 8001452:	494d      	ldr	r1, [pc, #308]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 8001454:	0093      	lsls	r3, r2, #2
+ 8001456:	440b      	add	r3, r1
+ 8001458:	4602      	mov	r2, r0
+ 800145a:	805a      	strh	r2, [r3, #2]
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 80010c8:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80010cc:	3b01      	subs	r3, #1
- 80010ce:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 80010d2:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80010d6:	2b00      	cmp	r3, #0
- 80010d8:	d1dc      	bne.n	8001094 <AD5934_GetTemperature+0x158>
+ 800145c:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001460:	3b01      	subs	r3, #1
+ 8001462:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001466:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800146a:	2b00      	cmp	r3, #0
+ 800146c:	d1dc      	bne.n	8001428 <AD5934_GetTemperature+0x168>
 	}
 
 	// Read real and imaginary data
 	temperature_dut_samples[0][0] = (int16_t)(sample & 0x0000FFFF); //real
- 80010da:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80010dc:	b21a      	sxth	r2, r3
- 80010de:	4b46      	ldr	r3, [pc, #280]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010e0:	801a      	strh	r2, [r3, #0]
+ 800146e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8001470:	b21a      	sxth	r2, r3
+ 8001472:	4b45      	ldr	r3, [pc, #276]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 8001474:	801a      	strh	r2, [r3, #0]
 	//temperature_dut_samples[0][1]  = 0xFFFF-(((sample & 0xFFFF0000)>>16)); //imag
 	temperature_dut_samples[0][1]  = (int16_t)((sample & 0xFFFF0000)>>16); //imag
- 80010e2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80010e4:	0c1b      	lsrs	r3, r3, #16
- 80010e6:	b21a      	sxth	r2, r3
- 80010e8:	4b43      	ldr	r3, [pc, #268]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 80010ea:	805a      	strh	r2, [r3, #2]
+ 8001476:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8001478:	0c1b      	lsrs	r3, r3, #16
+ 800147a:	b21a      	sxth	r2, r3
+ 800147c:	4b42      	ldr	r3, [pc, #264]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 800147e:	805a      	strh	r2, [r3, #2]
 
 	for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
- 80010ec:	2300      	movs	r3, #0
- 80010ee:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 80010f2:	2300      	movs	r3, #0
- 80010f4:	607b      	str	r3, [r7, #4]
- 80010f6:	2300      	movs	r3, #0
- 80010f8:	60bb      	str	r3, [r7, #8]
- 80010fa:	e016      	b.n	800112a <AD5934_GetTemperature+0x1ee>
+ 8001480:	2300      	movs	r3, #0
+ 8001482:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001486:	2300      	movs	r3, #0
+ 8001488:	603b      	str	r3, [r7, #0]
+ 800148a:	2300      	movs	r3, #0
+ 800148c:	607b      	str	r3, [r7, #4]
+ 800148e:	e016      	b.n	80014be <AD5934_GetTemperature+0x1fe>
 	{
 		dut_sum[0] += (int32_t)temperature_dut_samples[i][0]; //real
- 80010fc:	687b      	ldr	r3, [r7, #4]
- 80010fe:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
- 8001102:	493d      	ldr	r1, [pc, #244]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 8001104:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
- 8001108:	4413      	add	r3, r2
- 800110a:	607b      	str	r3, [r7, #4]
+ 8001490:	683b      	ldr	r3, [r7, #0]
+ 8001492:	f897 2047 	ldrb.w	r2, [r7, #71]	@ 0x47
+ 8001496:	493c      	ldr	r1, [pc, #240]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 8001498:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
+ 800149c:	4413      	add	r3, r2
+ 800149e:	603b      	str	r3, [r7, #0]
 		dut_sum[1] += (int32_t)temperature_dut_samples[i][1]; //imag
- 800110c:	68ba      	ldr	r2, [r7, #8]
- 800110e:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8001112:	4939      	ldr	r1, [pc, #228]	@ (80011f8 <AD5934_GetTemperature+0x2bc>)
- 8001114:	009b      	lsls	r3, r3, #2
- 8001116:	440b      	add	r3, r1
- 8001118:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
- 800111c:	4413      	add	r3, r2
- 800111e:	60bb      	str	r3, [r7, #8]
+ 80014a0:	687a      	ldr	r2, [r7, #4]
+ 80014a2:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80014a6:	4938      	ldr	r1, [pc, #224]	@ (8001588 <AD5934_GetTemperature+0x2c8>)
+ 80014a8:	009b      	lsls	r3, r3, #2
+ 80014aa:	440b      	add	r3, r1
+ 80014ac:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
+ 80014b0:	4413      	add	r3, r2
+ 80014b2:	607b      	str	r3, [r7, #4]
 	for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_TEMP_AVERAGES; i++)
- 8001120:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8001124:	3301      	adds	r3, #1
- 8001126:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 800112a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 800112e:	2b07      	cmp	r3, #7
- 8001130:	d9e4      	bls.n	80010fc <AD5934_GetTemperature+0x1c0>
+ 80014b4:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80014b8:	3301      	adds	r3, #1
+ 80014ba:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 80014be:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80014c2:	2b07      	cmp	r3, #7
+ 80014c4:	d9e4      	bls.n	8001490 <AD5934_GetTemperature+0x1d0>
 	}
 
 	real_dut = ((float)dut_sum[0])/((float)AD5934_TEMP_AVERAGES);
- 8001132:	687b      	ldr	r3, [r7, #4]
- 8001134:	4618      	mov	r0, r3
- 8001136:	f7ff fbd9 	bl	80008ec <__aeabi_i2f>
- 800113a:	4603      	mov	r3, r0
- 800113c:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 8001140:	4618      	mov	r0, r3
- 8001142:	f7ff fcdb 	bl	8000afc <__aeabi_fdiv>
- 8001146:	4603      	mov	r3, r0
- 8001148:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 80014c6:	683b      	ldr	r3, [r7, #0]
+ 80014c8:	4618      	mov	r0, r3
+ 80014ca:	f7ff fbd1 	bl	8000c70 <__aeabi_i2f>
+ 80014ce:	4603      	mov	r3, r0
+ 80014d0:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 80014d4:	4618      	mov	r0, r3
+ 80014d6:	f7ff fcd3 	bl	8000e80 <__aeabi_fdiv>
+ 80014da:	4603      	mov	r3, r0
+ 80014dc:	627b      	str	r3, [r7, #36]	@ 0x24
 	imag_dut = ((float)dut_sum[1])/((float)AD5934_TEMP_AVERAGES);
- 800114a:	68bb      	ldr	r3, [r7, #8]
- 800114c:	4618      	mov	r0, r3
- 800114e:	f7ff fbcd 	bl	80008ec <__aeabi_i2f>
- 8001152:	4603      	mov	r3, r0
- 8001154:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 8001158:	4618      	mov	r0, r3
- 800115a:	f7ff fccf 	bl	8000afc <__aeabi_fdiv>
- 800115e:	4603      	mov	r3, r0
- 8001160:	627b      	str	r3, [r7, #36]	@ 0x24
+ 80014de:	687b      	ldr	r3, [r7, #4]
+ 80014e0:	4618      	mov	r0, r3
+ 80014e2:	f7ff fbc5 	bl	8000c70 <__aeabi_i2f>
+ 80014e6:	4603      	mov	r3, r0
+ 80014e8:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 80014ec:	4618      	mov	r0, r3
+ 80014ee:	f7ff fcc7 	bl	8000e80 <__aeabi_fdiv>
+ 80014f2:	4603      	mov	r3, r0
+ 80014f4:	623b      	str	r3, [r7, #32]
 
 	// Calculate magnitude
 	mag_dut = sqrtf((real_dut * real_dut) + (imag_dut * imag_dut));
- 8001162:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
- 8001164:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
- 8001166:	f7ff fc15 	bl	8000994 <__aeabi_fmul>
- 800116a:	4603      	mov	r3, r0
- 800116c:	461c      	mov	r4, r3
- 800116e:	6a79      	ldr	r1, [r7, #36]	@ 0x24
- 8001170:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 8001172:	f7ff fc0f 	bl	8000994 <__aeabi_fmul>
- 8001176:	4603      	mov	r3, r0
- 8001178:	4619      	mov	r1, r3
- 800117a:	4620      	mov	r0, r4
- 800117c:	f7ff fb02 	bl	8000784 <__addsf3>
- 8001180:	4603      	mov	r3, r0
- 8001182:	4618      	mov	r0, r3
- 8001184:	f004 fdf0 	bl	8005d68 <sqrtf>
- 8001188:	6238      	str	r0, [r7, #32]
+ 80014f6:	6a79      	ldr	r1, [r7, #36]	@ 0x24
+ 80014f8:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 80014fa:	f7ff fc0d 	bl	8000d18 <__aeabi_fmul>
+ 80014fe:	4603      	mov	r3, r0
+ 8001500:	461c      	mov	r4, r3
+ 8001502:	6a39      	ldr	r1, [r7, #32]
+ 8001504:	6a38      	ldr	r0, [r7, #32]
+ 8001506:	f7ff fc07 	bl	8000d18 <__aeabi_fmul>
+ 800150a:	4603      	mov	r3, r0
+ 800150c:	4619      	mov	r1, r3
+ 800150e:	4620      	mov	r0, r4
+ 8001510:	f7ff fafa 	bl	8000b08 <__addsf3>
+ 8001514:	4603      	mov	r3, r0
+ 8001516:	4618      	mov	r0, r3
+ 8001518:	f006 f9c2 	bl	80078a0 <sqrtf>
+ 800151c:	61f8      	str	r0, [r7, #28]
 
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 800118a:	2307      	movs	r3, #7
- 800118c:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8001190:	e00f      	b.n	80011b2 <AD5934_GetTemperature+0x276>
+ 800151e:	2307      	movs	r3, #7
+ 8001520:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001524:	e00f      	b.n	8001546 <AD5934_GetTemperature+0x286>
 		temperature_display[i] = temperature_display[i-1];
- 8001192:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 8001196:	1e5a      	subs	r2, r3, #1
- 8001198:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 800119c:	4917      	ldr	r1, [pc, #92]	@ (80011fc <AD5934_GetTemperature+0x2c0>)
- 800119e:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
- 80011a2:	4916      	ldr	r1, [pc, #88]	@ (80011fc <AD5934_GetTemperature+0x2c0>)
- 80011a4:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+ 8001526:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800152a:	1e5a      	subs	r2, r3, #1
+ 800152c:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001530:	4916      	ldr	r1, [pc, #88]	@ (800158c <AD5934_GetTemperature+0x2cc>)
+ 8001532:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
+ 8001536:	4915      	ldr	r1, [pc, #84]	@ (800158c <AD5934_GetTemperature+0x2cc>)
+ 8001538:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
 	for (i = (AD5934_TEMP_AVERAGES-1); i > 0; i--)
- 80011a8:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80011ac:	3b01      	subs	r3, #1
- 80011ae:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 80011b2:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80011b6:	2b00      	cmp	r3, #0
- 80011b8:	d1eb      	bne.n	8001192 <AD5934_GetTemperature+0x256>
+ 800153c:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001540:	3b01      	subs	r3, #1
+ 8001542:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 8001546:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800154a:	2b00      	cmp	r3, #0
+ 800154c:	d1eb      	bne.n	8001526 <AD5934_GetTemperature+0x266>
 
 	ratio_mag = mag_ref / mag_dut;
- 80011ba:	6a39      	ldr	r1, [r7, #32]
- 80011bc:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
- 80011be:	f7ff fc9d 	bl	8000afc <__aeabi_fdiv>
- 80011c2:	4603      	mov	r3, r0
- 80011c4:	61fb      	str	r3, [r7, #28]
+ 800154e:	69f9      	ldr	r1, [r7, #28]
+ 8001550:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
+ 8001552:	f7ff fc95 	bl	8000e80 <__aeabi_fdiv>
+ 8001556:	4603      	mov	r3, r0
+ 8001558:	61bb      	str	r3, [r7, #24]
 
-	if(channel==AD5934_CH_PT100)
- 80011c6:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 80011ca:	2b00      	cmp	r3, #0
- 80011cc:	d11a      	bne.n	8001204 <AD5934_GetTemperature+0x2c8>
-		impedance_dut = AD5934_Linear_Correction((calibrationResistance[channel & 0x0F]) * ratio_mag);
- 80011ce:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 80011d2:	f003 030f 	and.w	r3, r3, #15
- 80011d6:	4a0a      	ldr	r2, [pc, #40]	@ (8001200 <AD5934_GetTemperature+0x2c4>)
- 80011d8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 80011dc:	69f9      	ldr	r1, [r7, #28]
- 80011de:	4618      	mov	r0, r3
- 80011e0:	f7ff fbd8 	bl	8000994 <__aeabi_fmul>
- 80011e4:	4603      	mov	r3, r0
- 80011e6:	4618      	mov	r0, r3
- 80011e8:	f000 fb0e 	bl	8001808 <AD5934_Linear_Correction>
- 80011ec:	6438      	str	r0, [r7, #64]	@ 0x40
- 80011ee:	e016      	b.n	800121e <AD5934_GetTemperature+0x2e2>
- 80011f0:	40010800 	.word	0x40010800
- 80011f4:	200000b4 	.word	0x200000b4
- 80011f8:	20000094 	.word	0x20000094
- 80011fc:	200000d4 	.word	0x200000d4
- 8001200:	08005ee8 	.word	0x08005ee8
+	if(ch_ref==AD5934_CH_REF100R_LOW_GAIN) // only for PT100
+ 800155a:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 800155e:	2b09      	cmp	r3, #9
+ 8001560:	d116      	bne.n	8001590 <AD5934_GetTemperature+0x2d0>
+		impedance_dut = AD5934_Linear_Correction(gain_factor * ratio_mag);
+ 8001562:	69b9      	ldr	r1, [r7, #24]
+ 8001564:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
+ 8001566:	f7ff fbd7 	bl	8000d18 <__aeabi_fmul>
+ 800156a:	4603      	mov	r3, r0
+ 800156c:	4618      	mov	r0, r3
+ 800156e:	f000 f9c5 	bl	80018fc <AD5934_Linear_Correction>
+ 8001572:	6438      	str	r0, [r7, #64]	@ 0x40
+ 8001574:	e012      	b.n	800159c <AD5934_GetTemperature+0x2dc>
+ 8001576:	bf00      	nop
+ 8001578:	40010800 	.word	0x40010800
+ 800157c:	42c80000 	.word	0x42c80000
+ 8001580:	447a0000 	.word	0x447a0000
+ 8001584:	200000bc 	.word	0x200000bc
+ 8001588:	2000009c 	.word	0x2000009c
+ 800158c:	200000dc 	.word	0x200000dc
 	else
-		impedance_dut = (calibrationResistance[channel & 0x0F]) * ratio_mag;
- 8001204:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 8001208:	f003 030f 	and.w	r3, r3, #15
- 800120c:	4a48      	ldr	r2, [pc, #288]	@ (8001330 <AD5934_GetTemperature+0x3f4>)
- 800120e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8001212:	4619      	mov	r1, r3
- 8001214:	69f8      	ldr	r0, [r7, #28]
- 8001216:	f7ff fbbd 	bl	8000994 <__aeabi_fmul>
- 800121a:	4603      	mov	r3, r0
- 800121c:	643b      	str	r3, [r7, #64]	@ 0x40
+		impedance_dut = gain_factor * ratio_mag;
+ 8001590:	69b9      	ldr	r1, [r7, #24]
+ 8001592:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
+ 8001594:	f7ff fbc0 	bl	8000d18 <__aeabi_fmul>
+ 8001598:	4603      	mov	r3, r0
+ 800159a:	643b      	str	r3, [r7, #64]	@ 0x40
 
 	// Calculate impedance ratio with the Reference Resistor
-	ratio = impedance_dut / (calibrationResistance[channel & 0x0F]);
- 800121e:	f897 3046 	ldrb.w	r3, [r7, #70]	@ 0x46
- 8001222:	f003 030f 	and.w	r3, r3, #15
- 8001226:	4a42      	ldr	r2, [pc, #264]	@ (8001330 <AD5934_GetTemperature+0x3f4>)
- 8001228:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 800122c:	4619      	mov	r1, r3
- 800122e:	6c38      	ldr	r0, [r7, #64]	@ 0x40
- 8001230:	f7ff fc64 	bl	8000afc <__aeabi_fdiv>
- 8001234:	4603      	mov	r3, r0
- 8001236:	61bb      	str	r3, [r7, #24]
+	ratio = impedance_dut / gain_factor;
+ 800159c:	6bb9      	ldr	r1, [r7, #56]	@ 0x38
+ 800159e:	6c38      	ldr	r0, [r7, #64]	@ 0x40
+ 80015a0:	f7ff fc6e 	bl	8000e80 <__aeabi_fdiv>
+ 80015a4:	4603      	mov	r3, r0
+ 80015a6:	617b      	str	r3, [r7, #20]
 
 	// Calculate impedance discriminant with the ratio
 	discriminant = (AD5934_RTD_A*AD5934_RTD_A)-(4.0f * AD5934_RTD_B * (1.0f - ratio));
- 8001238:	69b9      	ldr	r1, [r7, #24]
- 800123a:	f04f 507e 	mov.w	r0, #1065353216	@ 0x3f800000
- 800123e:	f7ff fa9f 	bl	8000780 <__aeabi_fsub>
- 8001242:	4603      	mov	r3, r0
- 8001244:	493b      	ldr	r1, [pc, #236]	@ (8001334 <AD5934_GetTemperature+0x3f8>)
- 8001246:	4618      	mov	r0, r3
- 8001248:	f7ff fba4 	bl	8000994 <__aeabi_fmul>
- 800124c:	4603      	mov	r3, r0
- 800124e:	493a      	ldr	r1, [pc, #232]	@ (8001338 <AD5934_GetTemperature+0x3fc>)
- 8001250:	4618      	mov	r0, r3
- 8001252:	f7ff fa97 	bl	8000784 <__addsf3>
- 8001256:	4603      	mov	r3, r0
- 8001258:	617b      	str	r3, [r7, #20]
+ 80015a8:	6979      	ldr	r1, [r7, #20]
+ 80015aa:	f04f 507e 	mov.w	r0, #1065353216	@ 0x3f800000
+ 80015ae:	f7ff faa9 	bl	8000b04 <__aeabi_fsub>
+ 80015b2:	4603      	mov	r3, r0
+ 80015b4:	493a      	ldr	r1, [pc, #232]	@ (80016a0 <AD5934_GetTemperature+0x3e0>)
+ 80015b6:	4618      	mov	r0, r3
+ 80015b8:	f7ff fbae 	bl	8000d18 <__aeabi_fmul>
+ 80015bc:	4603      	mov	r3, r0
+ 80015be:	4939      	ldr	r1, [pc, #228]	@ (80016a4 <AD5934_GetTemperature+0x3e4>)
+ 80015c0:	4618      	mov	r0, r3
+ 80015c2:	f7ff faa1 	bl	8000b08 <__addsf3>
+ 80015c6:	4603      	mov	r3, r0
+ 80015c8:	613b      	str	r3, [r7, #16]
 
 	// Calculate new temperature with the discriminant
 	temperature_display[0] = (-AD5934_RTD_A + sqrtf(discriminant))/(2.0f * AD5934_RTD_B);
- 800125a:	6978      	ldr	r0, [r7, #20]
- 800125c:	f004 fd84 	bl	8005d68 <sqrtf>
- 8001260:	4603      	mov	r3, r0
- 8001262:	4936      	ldr	r1, [pc, #216]	@ (800133c <AD5934_GetTemperature+0x400>)
- 8001264:	4618      	mov	r0, r3
- 8001266:	f7ff fa8b 	bl	8000780 <__aeabi_fsub>
- 800126a:	4603      	mov	r3, r0
- 800126c:	4934      	ldr	r1, [pc, #208]	@ (8001340 <AD5934_GetTemperature+0x404>)
- 800126e:	4618      	mov	r0, r3
- 8001270:	f7ff fc44 	bl	8000afc <__aeabi_fdiv>
- 8001274:	4603      	mov	r3, r0
- 8001276:	461a      	mov	r2, r3
- 8001278:	4b32      	ldr	r3, [pc, #200]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 800127a:	601a      	str	r2, [r3, #0]
+ 80015ca:	6938      	ldr	r0, [r7, #16]
+ 80015cc:	f006 f968 	bl	80078a0 <sqrtf>
+ 80015d0:	4603      	mov	r3, r0
+ 80015d2:	4935      	ldr	r1, [pc, #212]	@ (80016a8 <AD5934_GetTemperature+0x3e8>)
+ 80015d4:	4618      	mov	r0, r3
+ 80015d6:	f7ff fa95 	bl	8000b04 <__aeabi_fsub>
+ 80015da:	4603      	mov	r3, r0
+ 80015dc:	4933      	ldr	r1, [pc, #204]	@ (80016ac <AD5934_GetTemperature+0x3ec>)
+ 80015de:	4618      	mov	r0, r3
+ 80015e0:	f7ff fc4e 	bl	8000e80 <__aeabi_fdiv>
+ 80015e4:	4603      	mov	r3, r0
+ 80015e6:	461a      	mov	r2, r3
+ 80015e8:	4b31      	ldr	r3, [pc, #196]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 80015ea:	601a      	str	r2, [r3, #0]
 
 	// Sum of all temperatures
 	for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++)
- 800127c:	2300      	movs	r3, #0
- 800127e:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 8001282:	f04f 0300 	mov.w	r3, #0
- 8001286:	63fb      	str	r3, [r7, #60]	@ 0x3c
- 8001288:	e00f      	b.n	80012aa <AD5934_GetTemperature+0x36e>
+ 80015ec:	2300      	movs	r3, #0
+ 80015ee:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 80015f2:	f04f 0300 	mov.w	r3, #0
+ 80015f6:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 80015f8:	e00f      	b.n	800161a <AD5934_GetTemperature+0x35a>
 		temperature_sum += temperature_display[i];
- 800128a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 800128e:	4a2d      	ldr	r2, [pc, #180]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 8001290:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8001294:	4619      	mov	r1, r3
- 8001296:	6bf8      	ldr	r0, [r7, #60]	@ 0x3c
- 8001298:	f7ff fa74 	bl	8000784 <__addsf3>
- 800129c:	4603      	mov	r3, r0
- 800129e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 80015fa:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 80015fe:	4a2c      	ldr	r2, [pc, #176]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 8001600:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8001604:	4619      	mov	r1, r3
+ 8001606:	6bf8      	ldr	r0, [r7, #60]	@ 0x3c
+ 8001608:	f7ff fa7e 	bl	8000b08 <__addsf3>
+ 800160c:	4603      	mov	r3, r0
+ 800160e:	63fb      	str	r3, [r7, #60]	@ 0x3c
 	for (i = 0, temperature_sum=0.0f; i < AD5934_TEMP_AVERAGES; i++)
- 80012a0:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80012a4:	3301      	adds	r3, #1
- 80012a6:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
- 80012aa:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
- 80012ae:	2b07      	cmp	r3, #7
- 80012b0:	d9eb      	bls.n	800128a <AD5934_GetTemperature+0x34e>
+ 8001610:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 8001614:	3301      	adds	r3, #1
+ 8001616:	f887 3047 	strb.w	r3, [r7, #71]	@ 0x47
+ 800161a:	f897 3047 	ldrb.w	r3, [r7, #71]	@ 0x47
+ 800161e:	2b07      	cmp	r3, #7
+ 8001620:	d9eb      	bls.n	80015fa <AD5934_GetTemperature+0x33a>
 
 	// Is the temperature stable?
 	if(temperature_display[0]>0.0f && (abs(temperature_display[0]-temperature_display[AD5934_TEMP_AVERAGES-1])/temperature_display[0])<0.1f)
- 80012b2:	4b24      	ldr	r3, [pc, #144]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 80012b4:	681b      	ldr	r3, [r3, #0]
- 80012b6:	f04f 0100 	mov.w	r1, #0
- 80012ba:	4618      	mov	r0, r3
- 80012bc:	f7ff fd26 	bl	8000d0c <__aeabi_fcmpgt>
- 80012c0:	4603      	mov	r3, r0
- 80012c2:	2b00      	cmp	r3, #0
- 80012c4:	d02d      	beq.n	8001322 <AD5934_GetTemperature+0x3e6>
- 80012c6:	4b1f      	ldr	r3, [pc, #124]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 80012c8:	681b      	ldr	r3, [r3, #0]
- 80012ca:	4a1e      	ldr	r2, [pc, #120]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 80012cc:	69d2      	ldr	r2, [r2, #28]
- 80012ce:	4611      	mov	r1, r2
- 80012d0:	4618      	mov	r0, r3
- 80012d2:	f7ff fa55 	bl	8000780 <__aeabi_fsub>
- 80012d6:	4603      	mov	r3, r0
- 80012d8:	4618      	mov	r0, r3
- 80012da:	f7ff fd37 	bl	8000d4c <__aeabi_f2iz>
- 80012de:	4603      	mov	r3, r0
- 80012e0:	2b00      	cmp	r3, #0
- 80012e2:	bfb8      	it	lt
- 80012e4:	425b      	neglt	r3, r3
- 80012e6:	4618      	mov	r0, r3
- 80012e8:	f7ff fb00 	bl	80008ec <__aeabi_i2f>
- 80012ec:	4602      	mov	r2, r0
- 80012ee:	4b15      	ldr	r3, [pc, #84]	@ (8001344 <AD5934_GetTemperature+0x408>)
- 80012f0:	681b      	ldr	r3, [r3, #0]
- 80012f2:	4619      	mov	r1, r3
- 80012f4:	4610      	mov	r0, r2
- 80012f6:	f7ff fc01 	bl	8000afc <__aeabi_fdiv>
- 80012fa:	4603      	mov	r3, r0
- 80012fc:	4912      	ldr	r1, [pc, #72]	@ (8001348 <AD5934_GetTemperature+0x40c>)
- 80012fe:	4618      	mov	r0, r3
- 8001300:	f7ff fce6 	bl	8000cd0 <__aeabi_fcmplt>
- 8001304:	4603      	mov	r3, r0
- 8001306:	2b00      	cmp	r3, #0
- 8001308:	d00b      	beq.n	8001322 <AD5934_GetTemperature+0x3e6>
+ 8001622:	4b23      	ldr	r3, [pc, #140]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 8001624:	681b      	ldr	r3, [r3, #0]
+ 8001626:	f04f 0100 	mov.w	r1, #0
+ 800162a:	4618      	mov	r0, r3
+ 800162c:	f7ff fd30 	bl	8001090 <__aeabi_fcmpgt>
+ 8001630:	4603      	mov	r3, r0
+ 8001632:	2b00      	cmp	r3, #0
+ 8001634:	d02d      	beq.n	8001692 <AD5934_GetTemperature+0x3d2>
+ 8001636:	4b1e      	ldr	r3, [pc, #120]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 8001638:	681b      	ldr	r3, [r3, #0]
+ 800163a:	4a1d      	ldr	r2, [pc, #116]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 800163c:	69d2      	ldr	r2, [r2, #28]
+ 800163e:	4611      	mov	r1, r2
+ 8001640:	4618      	mov	r0, r3
+ 8001642:	f7ff fa5f 	bl	8000b04 <__aeabi_fsub>
+ 8001646:	4603      	mov	r3, r0
+ 8001648:	4618      	mov	r0, r3
+ 800164a:	f7ff fd41 	bl	80010d0 <__aeabi_f2iz>
+ 800164e:	4603      	mov	r3, r0
+ 8001650:	2b00      	cmp	r3, #0
+ 8001652:	bfb8      	it	lt
+ 8001654:	425b      	neglt	r3, r3
+ 8001656:	4618      	mov	r0, r3
+ 8001658:	f7ff fb0a 	bl	8000c70 <__aeabi_i2f>
+ 800165c:	4602      	mov	r2, r0
+ 800165e:	4b14      	ldr	r3, [pc, #80]	@ (80016b0 <AD5934_GetTemperature+0x3f0>)
+ 8001660:	681b      	ldr	r3, [r3, #0]
+ 8001662:	4619      	mov	r1, r3
+ 8001664:	4610      	mov	r0, r2
+ 8001666:	f7ff fc0b 	bl	8000e80 <__aeabi_fdiv>
+ 800166a:	4603      	mov	r3, r0
+ 800166c:	4911      	ldr	r1, [pc, #68]	@ (80016b4 <AD5934_GetTemperature+0x3f4>)
+ 800166e:	4618      	mov	r0, r3
+ 8001670:	f7ff fcf0 	bl	8001054 <__aeabi_fcmplt>
+ 8001674:	4603      	mov	r3, r0
+ 8001676:	2b00      	cmp	r3, #0
+ 8001678:	d00b      	beq.n	8001692 <AD5934_GetTemperature+0x3d2>
 		return(AD5934_Round_Float_Precision(temperature_sum/((float)AD5934_TEMP_AVERAGES),1)); // Sum / number of averages
- 800130a:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 800130e:	6bf8      	ldr	r0, [r7, #60]	@ 0x3c
- 8001310:	f7ff fbf4 	bl	8000afc <__aeabi_fdiv>
- 8001314:	4603      	mov	r3, r0
- 8001316:	2101      	movs	r1, #1
- 8001318:	4618      	mov	r0, r3
- 800131a:	f000 fa47 	bl	80017ac <AD5934_Round_Float_Precision>
- 800131e:	4603      	mov	r3, r0
- 8001320:	e001      	b.n	8001326 <AD5934_GetTemperature+0x3ea>
+ 800167a:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 800167e:	6bf8      	ldr	r0, [r7, #60]	@ 0x3c
+ 8001680:	f7ff fbfe 	bl	8000e80 <__aeabi_fdiv>
+ 8001684:	4603      	mov	r3, r0
+ 8001686:	2101      	movs	r1, #1
+ 8001688:	4618      	mov	r0, r3
+ 800168a:	f000 f909 	bl	80018a0 <AD5934_Round_Float_Precision>
+ 800168e:	4603      	mov	r3, r0
+ 8001690:	e001      	b.n	8001696 <AD5934_GetTemperature+0x3d6>
 	else
 		return 0.0f;	//instable values return always 0
- 8001322:	f04f 0300 	mov.w	r3, #0
+ 8001692:	f04f 0300 	mov.w	r3, #0
 }
- 8001326:	4618      	mov	r0, r3
- 8001328:	374c      	adds	r7, #76	@ 0x4c
- 800132a:	46bd      	mov	sp, r7
- 800132c:	bd90      	pop	{r4, r7, pc}
- 800132e:	bf00      	nop
- 8001330:	08005ee8 	.word	0x08005ee8
- 8001334:	361b057f 	.word	0x361b057f
- 8001338:	37802266 	.word	0x37802266
- 800133c:	3b801132 	.word	0x3b801132
- 8001340:	b59b057f 	.word	0xb59b057f
- 8001344:	200000d4 	.word	0x200000d4
- 8001348:	3dcccccd 	.word	0x3dcccccd
+ 8001696:	4618      	mov	r0, r3
+ 8001698:	374c      	adds	r7, #76	@ 0x4c
+ 800169a:	46bd      	mov	sp, r7
+ 800169c:	bd90      	pop	{r4, r7, pc}
+ 800169e:	bf00      	nop
+ 80016a0:	361b057f 	.word	0x361b057f
+ 80016a4:	37802266 	.word	0x37802266
+ 80016a8:	3b801132 	.word	0x3b801132
+ 80016ac:	b59b057f 	.word	0xb59b057f
+ 80016b0:	200000dc 	.word	0x200000dc
+ 80016b4:	3dcccccd 	.word	0x3dcccccd
 
-0800134c <AD5934_GetImpedance>:
+080016b8 <AD5934_GetImpedance>:
 * @param none.
 *
 * @return impedance.
 ******************************************************************************/
 float AD5934_GetImpedance(void)
 {
- 800134c:	b590      	push	{r4, r7, lr}
- 800134e:	b095      	sub	sp, #84	@ 0x54
- 8001350:	af00      	add	r7, sp, #0
-	int32_t ref_sum_H[2], ref_sum_L[2], dut_sum[2];
-	float real_number, imag_number, mag_dut, mag_ref_H, mag_ref_L, gain_factor_H, gain_factor_L, gain_factor_dut, slope, admittance;
-
-	/* STEP 1: Two points reference curve  */
-
-	ADG715_Update(AD5934_CH_REF_1K); // Set the Reference for High Resistor on board in the Analog Mux
- 8001352:	2011      	movs	r0, #17
- 8001354:	f000 faa4 	bl	80018a0 <ADG715_Update>
-	HAL_Delay(2); //Wait a little
- 8001358:	2002      	movs	r0, #2
- 800135a:	f001 fbff 	bl	8002b5c <HAL_Delay>
-
-	sample_H = AD5934_Sweep(); // Get Reference Resistor 1 from ADC
- 800135e:	f7ff fdcf 	bl	8000f00 <AD5934_Sweep>
- 8001362:	6438      	str	r0, [r7, #64]	@ 0x40
-
-	ADG715_Update(AD5934_CH_REF_100R); // Set the Reference for Low Resistor on board in the Analog Mux
- 8001364:	2010      	movs	r0, #16
- 8001366:	f000 fa9b 	bl	80018a0 <ADG715_Update>
-	HAL_Delay(2); //Wait a little
- 800136a:	2002      	movs	r0, #2
- 800136c:	f001 fbf6 	bl	8002b5c <HAL_Delay>
-
-	sample_L = AD5934_Sweep(); // Get Reference Resistor 2 from ADC
- 8001370:	f7ff fdc6 	bl	8000f00 <AD5934_Sweep>
- 8001374:	63f8      	str	r0, [r7, #60]	@ 0x3c
-
-
-	// Move values in the vectors
-	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
- 8001376:	2307      	movs	r3, #7
- 8001378:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 800137c:	e038      	b.n	80013f0 <AD5934_GetImpedance+0xa4>
-	{
-		ec_ref_samples_H[i][0] = ec_ref_samples_H[i-1][0]; //real
- 800137e:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001382:	1e5a      	subs	r2, r3, #1
- 8001384:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001388:	49ad      	ldr	r1, [pc, #692]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 800138a:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
- 800138e:	4aac      	ldr	r2, [pc, #688]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 8001390:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
-		ec_ref_samples_H[i][1] = ec_ref_samples_H[i-1][1]; //imag
- 8001394:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001398:	3b01      	subs	r3, #1
- 800139a:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 800139e:	49a8      	ldr	r1, [pc, #672]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 80013a0:	009b      	lsls	r3, r3, #2
- 80013a2:	440b      	add	r3, r1
- 80013a4:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
- 80013a8:	49a5      	ldr	r1, [pc, #660]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 80013aa:	0093      	lsls	r3, r2, #2
- 80013ac:	440b      	add	r3, r1
- 80013ae:	4602      	mov	r2, r0
- 80013b0:	805a      	strh	r2, [r3, #2]
-
-		ec_ref_samples_L[i][0] = ec_ref_samples_L[i-1][0]; //real
- 80013b2:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80013b6:	1e5a      	subs	r2, r3, #1
- 80013b8:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80013bc:	49a1      	ldr	r1, [pc, #644]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 80013be:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
- 80013c2:	4aa0      	ldr	r2, [pc, #640]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 80013c4:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
-		ec_ref_samples_L[i][1] = ec_ref_samples_L[i-1][1]; //imag
- 80013c8:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80013cc:	3b01      	subs	r3, #1
- 80013ce:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 80013d2:	499c      	ldr	r1, [pc, #624]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 80013d4:	009b      	lsls	r3, r3, #2
- 80013d6:	440b      	add	r3, r1
- 80013d8:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
- 80013dc:	4999      	ldr	r1, [pc, #612]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 80013de:	0093      	lsls	r3, r2, #2
- 80013e0:	440b      	add	r3, r1
- 80013e2:	4602      	mov	r2, r0
- 80013e4:	805a      	strh	r2, [r3, #2]
-	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
- 80013e6:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80013ea:	3b01      	subs	r3, #1
- 80013ec:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 80013f0:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80013f4:	2b00      	cmp	r3, #0
- 80013f6:	d1c2      	bne.n	800137e <AD5934_GetImpedance+0x32>
-
-	}
-
-	// Read real and imaginary data
-	ec_ref_samples_H[0][0] = (int16_t)(sample_H & 0x0000FFFF); //real
- 80013f8:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
- 80013fa:	b21a      	sxth	r2, r3
- 80013fc:	4b90      	ldr	r3, [pc, #576]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 80013fe:	801a      	strh	r2, [r3, #0]
-	ec_ref_samples_H[0][1]  = (int16_t)((sample_H & 0xFFFF0000)>>16); //imag
- 8001400:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
- 8001402:	0c1b      	lsrs	r3, r3, #16
- 8001404:	b21a      	sxth	r2, r3
- 8001406:	4b8e      	ldr	r3, [pc, #568]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 8001408:	805a      	strh	r2, [r3, #2]
-	//ec_ref_samples_H[0][1]  = (int16_t)((0xFFFF - (sample_H & 0xFFFF0000)>>16)); //imag
-
-	// Read real and imaginary data
-	ec_ref_samples_L[0][0] = (int16_t)(sample_L & 0x0000FFFF); //real
- 800140a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 800140c:	b21a      	sxth	r2, r3
- 800140e:	4b8d      	ldr	r3, [pc, #564]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 8001410:	801a      	strh	r2, [r3, #0]
-	ec_ref_samples_L[0][1]  = (int16_t)((sample_L & 0xFFFF0000)>>16); //imag
- 8001412:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001414:	0c1b      	lsrs	r3, r3, #16
- 8001416:	b21a      	sxth	r2, r3
- 8001418:	4b8a      	ldr	r3, [pc, #552]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 800141a:	805a      	strh	r2, [r3, #2]
-	//ec_ref_samples_L[0][1]  = (int16_t)((0xFFFF - (sample_L & 0xFFFF0000)>>16)); //imag
-
-
-	// Sum values in the vectors
-	for (i = 0, ref_sum_H[0]=0, ref_sum_H[1]=0, ref_sum_L[0]=0, ref_sum_L[1]=0; i < AD5934_EC_AVERAGES; i++)
- 800141c:	2300      	movs	r3, #0
- 800141e:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 8001422:	2300      	movs	r3, #0
- 8001424:	617b      	str	r3, [r7, #20]
- 8001426:	2300      	movs	r3, #0
- 8001428:	61bb      	str	r3, [r7, #24]
- 800142a:	2300      	movs	r3, #0
- 800142c:	60fb      	str	r3, [r7, #12]
- 800142e:	2300      	movs	r3, #0
- 8001430:	613b      	str	r3, [r7, #16]
- 8001432:	e028      	b.n	8001486 <AD5934_GetImpedance+0x13a>
-	{
-		ref_sum_H[0] += (int32_t)ec_ref_samples_H[i][0]; //real
- 8001434:	697b      	ldr	r3, [r7, #20]
- 8001436:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 800143a:	4981      	ldr	r1, [pc, #516]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 800143c:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
- 8001440:	4413      	add	r3, r2
- 8001442:	617b      	str	r3, [r7, #20]
-		ref_sum_H[1] += (int32_t)ec_ref_samples_H[i][1]; //imag
- 8001444:	69ba      	ldr	r2, [r7, #24]
- 8001446:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800144a:	497d      	ldr	r1, [pc, #500]	@ (8001640 <AD5934_GetImpedance+0x2f4>)
- 800144c:	009b      	lsls	r3, r3, #2
- 800144e:	440b      	add	r3, r1
- 8001450:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
- 8001454:	4413      	add	r3, r2
- 8001456:	61bb      	str	r3, [r7, #24]
-
-		ref_sum_L[0] += (int32_t)ec_ref_samples_L[i][0]; //real
- 8001458:	68fb      	ldr	r3, [r7, #12]
- 800145a:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 800145e:	4979      	ldr	r1, [pc, #484]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 8001460:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
- 8001464:	4413      	add	r3, r2
- 8001466:	60fb      	str	r3, [r7, #12]
-		ref_sum_L[1] += (int32_t)ec_ref_samples_L[i][1]; //imag
- 8001468:	693a      	ldr	r2, [r7, #16]
- 800146a:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800146e:	4975      	ldr	r1, [pc, #468]	@ (8001644 <AD5934_GetImpedance+0x2f8>)
- 8001470:	009b      	lsls	r3, r3, #2
- 8001472:	440b      	add	r3, r1
- 8001474:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
- 8001478:	4413      	add	r3, r2
- 800147a:	613b      	str	r3, [r7, #16]
-	for (i = 0, ref_sum_H[0]=0, ref_sum_H[1]=0, ref_sum_L[0]=0, ref_sum_L[1]=0; i < AD5934_EC_AVERAGES; i++)
- 800147c:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001480:	3301      	adds	r3, #1
- 8001482:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 8001486:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800148a:	2b07      	cmp	r3, #7
- 800148c:	d9d2      	bls.n	8001434 <AD5934_GetImpedance+0xe8>
-	}
-
-	real_number = ((float)ref_sum_H[0])/((float)AD5934_EC_AVERAGES);
- 800148e:	697b      	ldr	r3, [r7, #20]
- 8001490:	4618      	mov	r0, r3
- 8001492:	f7ff fa2b 	bl	80008ec <__aeabi_i2f>
- 8001496:	4603      	mov	r3, r0
- 8001498:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 800149c:	4618      	mov	r0, r3
- 800149e:	f7ff fb2d 	bl	8000afc <__aeabi_fdiv>
- 80014a2:	4603      	mov	r3, r0
- 80014a4:	63bb      	str	r3, [r7, #56]	@ 0x38
-	imag_number = ((float)ref_sum_H[1])/((float)AD5934_EC_AVERAGES);
- 80014a6:	69bb      	ldr	r3, [r7, #24]
- 80014a8:	4618      	mov	r0, r3
- 80014aa:	f7ff fa1f 	bl	80008ec <__aeabi_i2f>
- 80014ae:	4603      	mov	r3, r0
- 80014b0:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 80014b4:	4618      	mov	r0, r3
- 80014b6:	f7ff fb21 	bl	8000afc <__aeabi_fdiv>
- 80014ba:	4603      	mov	r3, r0
- 80014bc:	637b      	str	r3, [r7, #52]	@ 0x34
-
-	// Calculate gain factor impedance
-	mag_ref_H = sqrtf((real_number * real_number) + (imag_number * imag_number));
- 80014be:	6bb9      	ldr	r1, [r7, #56]	@ 0x38
- 80014c0:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
- 80014c2:	f7ff fa67 	bl	8000994 <__aeabi_fmul>
- 80014c6:	4603      	mov	r3, r0
- 80014c8:	461c      	mov	r4, r3
- 80014ca:	6b79      	ldr	r1, [r7, #52]	@ 0x34
- 80014cc:	6b78      	ldr	r0, [r7, #52]	@ 0x34
- 80014ce:	f7ff fa61 	bl	8000994 <__aeabi_fmul>
- 80014d2:	4603      	mov	r3, r0
- 80014d4:	4619      	mov	r1, r3
- 80014d6:	4620      	mov	r0, r4
- 80014d8:	f7ff f954 	bl	8000784 <__addsf3>
- 80014dc:	4603      	mov	r3, r0
- 80014de:	4618      	mov	r0, r3
- 80014e0:	f004 fc42 	bl	8005d68 <sqrtf>
- 80014e4:	6338      	str	r0, [r7, #48]	@ 0x30
-
-	if(mag_ref_H > 0.0f)
- 80014e6:	f04f 0100 	mov.w	r1, #0
- 80014ea:	6b38      	ldr	r0, [r7, #48]	@ 0x30
- 80014ec:	f7ff fc0e 	bl	8000d0c <__aeabi_fcmpgt>
- 80014f0:	4603      	mov	r3, r0
- 80014f2:	2b00      	cmp	r3, #0
- 80014f4:	d00c      	beq.n	8001510 <AD5934_GetImpedance+0x1c4>
-		gain_factor_H = 1.0f / (1000.0f * mag_ref_H);
- 80014f6:	4954      	ldr	r1, [pc, #336]	@ (8001648 <AD5934_GetImpedance+0x2fc>)
- 80014f8:	6b38      	ldr	r0, [r7, #48]	@ 0x30
- 80014fa:	f7ff fa4b 	bl	8000994 <__aeabi_fmul>
- 80014fe:	4603      	mov	r3, r0
- 8001500:	4619      	mov	r1, r3
- 8001502:	f04f 507e 	mov.w	r0, #1065353216	@ 0x3f800000
- 8001506:	f7ff faf9 	bl	8000afc <__aeabi_fdiv>
- 800150a:	4603      	mov	r3, r0
- 800150c:	64bb      	str	r3, [r7, #72]	@ 0x48
- 800150e:	e002      	b.n	8001516 <AD5934_GetImpedance+0x1ca>
-	else
-		gain_factor_H = 0.0f;
- 8001510:	f04f 0300 	mov.w	r3, #0
- 8001514:	64bb      	str	r3, [r7, #72]	@ 0x48
-
-	real_number = ((float)ref_sum_L[0])/((float)AD5934_EC_AVERAGES);
- 8001516:	68fb      	ldr	r3, [r7, #12]
- 8001518:	4618      	mov	r0, r3
- 800151a:	f7ff f9e7 	bl	80008ec <__aeabi_i2f>
- 800151e:	4603      	mov	r3, r0
- 8001520:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 8001524:	4618      	mov	r0, r3
- 8001526:	f7ff fae9 	bl	8000afc <__aeabi_fdiv>
- 800152a:	4603      	mov	r3, r0
- 800152c:	63bb      	str	r3, [r7, #56]	@ 0x38
-	imag_number = ((float)ref_sum_L[1])/((float)AD5934_EC_AVERAGES);
- 800152e:	693b      	ldr	r3, [r7, #16]
- 8001530:	4618      	mov	r0, r3
- 8001532:	f7ff f9db 	bl	80008ec <__aeabi_i2f>
- 8001536:	4603      	mov	r3, r0
- 8001538:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 800153c:	4618      	mov	r0, r3
- 800153e:	f7ff fadd 	bl	8000afc <__aeabi_fdiv>
- 8001542:	4603      	mov	r3, r0
- 8001544:	637b      	str	r3, [r7, #52]	@ 0x34
-
-		// Calculate gain factor impedance
-	mag_ref_L = sqrtf((real_number * real_number) + (imag_number * imag_number));
- 8001546:	6bb9      	ldr	r1, [r7, #56]	@ 0x38
- 8001548:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
- 800154a:	f7ff fa23 	bl	8000994 <__aeabi_fmul>
- 800154e:	4603      	mov	r3, r0
- 8001550:	461c      	mov	r4, r3
- 8001552:	6b79      	ldr	r1, [r7, #52]	@ 0x34
- 8001554:	6b78      	ldr	r0, [r7, #52]	@ 0x34
- 8001556:	f7ff fa1d 	bl	8000994 <__aeabi_fmul>
- 800155a:	4603      	mov	r3, r0
- 800155c:	4619      	mov	r1, r3
- 800155e:	4620      	mov	r0, r4
- 8001560:	f7ff f910 	bl	8000784 <__addsf3>
- 8001564:	4603      	mov	r3, r0
- 8001566:	4618      	mov	r0, r3
- 8001568:	f004 fbfe 	bl	8005d68 <sqrtf>
- 800156c:	62f8      	str	r0, [r7, #44]	@ 0x2c
-
-	if(mag_ref_L > 0.0f)
- 800156e:	f04f 0100 	mov.w	r1, #0
- 8001572:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
- 8001574:	f7ff fbca 	bl	8000d0c <__aeabi_fcmpgt>
- 8001578:	4603      	mov	r3, r0
- 800157a:	2b00      	cmp	r3, #0
- 800157c:	d00c      	beq.n	8001598 <AD5934_GetImpedance+0x24c>
-		gain_factor_L = 1.0f / (100.0f * mag_ref_L);
- 800157e:	4933      	ldr	r1, [pc, #204]	@ (800164c <AD5934_GetImpedance+0x300>)
- 8001580:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
- 8001582:	f7ff fa07 	bl	8000994 <__aeabi_fmul>
- 8001586:	4603      	mov	r3, r0
- 8001588:	4619      	mov	r1, r3
- 800158a:	f04f 507e 	mov.w	r0, #1065353216	@ 0x3f800000
- 800158e:	f7ff fab5 	bl	8000afc <__aeabi_fdiv>
- 8001592:	4603      	mov	r3, r0
- 8001594:	647b      	str	r3, [r7, #68]	@ 0x44
- 8001596:	e002      	b.n	800159e <AD5934_GetImpedance+0x252>
-	else
-		gain_factor_L = 0.0f;
- 8001598:	f04f 0300 	mov.w	r3, #0
- 800159c:	647b      	str	r3, [r7, #68]	@ 0x44
+ 80016b8:	b590      	push	{r4, r7, lr}
+ 80016ba:	b089      	sub	sp, #36	@ 0x24
+ 80016bc:	af00      	add	r7, sp, #0
+	float real_number, imag_number, mag_dut, slope;
 
 
 	/* STEP 2: Set the Amplification related to the maximum set value  */
 
 	if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6) == GPIO_PIN_SET) // PA6 has internal pull-up and the Switch connects to GND
- 800159e:	2140      	movs	r1, #64	@ 0x40
- 80015a0:	482b      	ldr	r0, [pc, #172]	@ (8001650 <AD5934_GetImpedance+0x304>)
- 80015a2:	f002 f855 	bl	8003650 <HAL_GPIO_ReadPin>
- 80015a6:	4603      	mov	r3, r0
- 80015a8:	2b01      	cmp	r3, #1
- 80015aa:	d103      	bne.n	80015b4 <AD5934_GetImpedance+0x268>
-		channel = AD5934_CH_EC_5MS;		// Switch OFF = 5 mS/cm
- 80015ac:	2322      	movs	r3, #34	@ 0x22
- 80015ae:	f887 304e 	strb.w	r3, [r7, #78]	@ 0x4e
- 80015b2:	e002      	b.n	80015ba <AD5934_GetImpedance+0x26e>
+ 80016be:	2140      	movs	r1, #64	@ 0x40
+ 80016c0:	485e      	ldr	r0, [pc, #376]	@ (800183c <AD5934_GetImpedance+0x184>)
+ 80016c2:	f003 f9d9 	bl	8004a78 <HAL_GPIO_ReadPin>
+ 80016c6:	4603      	mov	r3, r0
+ 80016c8:	2b01      	cmp	r3, #1
+ 80016ca:	d102      	bne.n	80016d2 <AD5934_GetImpedance+0x1a>
+		ec_gain = AD5934_CH_EC_HIGH_GAIN;		// Switch OFF = 5 mS/cm, HIGH GAIN,
+ 80016cc:	2384      	movs	r3, #132	@ 0x84
+ 80016ce:	77bb      	strb	r3, [r7, #30]
+ 80016d0:	e001      	b.n	80016d6 <AD5934_GetImpedance+0x1e>
 	else
-		channel = AD5934_CH_EC_10MS;	// Switch ON = 10 mS/cm
- 80015b4:	2321      	movs	r3, #33	@ 0x21
- 80015b6:	f887 304e 	strb.w	r3, [r7, #78]	@ 0x4e
+		ec_gain = AD5934_CH_EC_MID_GAIN;		// Switch ON = 10 mS/cm, MID GAIN,
+ 80016d2:	2382      	movs	r3, #130	@ 0x82
+ 80016d4:	77bb      	strb	r3, [r7, #30]
 
-	ADG715_Update(channel);
- 80015ba:	f897 304e 	ldrb.w	r3, [r7, #78]	@ 0x4e
- 80015be:	4618      	mov	r0, r3
- 80015c0:	f000 f96e 	bl	80018a0 <ADG715_Update>
+	ADG715_Update(ec_gain);
+ 80016d6:	7fbb      	ldrb	r3, [r7, #30]
+ 80016d8:	4618      	mov	r0, r3
+ 80016da:	f000 f95b 	bl	8001994 <ADG715_Update>
 	HAL_Delay(2);
- 80015c4:	2002      	movs	r0, #2
- 80015c6:	f001 fac9 	bl	8002b5c <HAL_Delay>
+ 80016de:	2002      	movs	r0, #2
+ 80016e0:	f001 fe02 	bl	80032e8 <HAL_Delay>
 
 	sample_dut = AD5934_Sweep(); // Get PT100/PT1000 Values from ADC
- 80015ca:	f7ff fc99 	bl	8000f00 <AD5934_Sweep>
- 80015ce:	62b8      	str	r0, [r7, #40]	@ 0x28
-
+ 80016e4:	f7ff fdce 	bl	8001284 <AD5934_Sweep>
+ 80016e8:	61b8      	str	r0, [r7, #24]
 
 	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
- 80015d0:	2307      	movs	r3, #7
- 80015d2:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 80015d6:	e01e      	b.n	8001616 <AD5934_GetImpedance+0x2ca>
+ 80016ea:	2307      	movs	r3, #7
+ 80016ec:	77fb      	strb	r3, [r7, #31]
+ 80016ee:	e018      	b.n	8001722 <AD5934_GetImpedance+0x6a>
 	{
 		ec_dut_samples[i][0] = ec_dut_samples[i-1][0]; //real
- 80015d8:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80015dc:	1e5a      	subs	r2, r3, #1
- 80015de:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80015e2:	491c      	ldr	r1, [pc, #112]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 80015e4:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
- 80015e8:	4a1a      	ldr	r2, [pc, #104]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 80015ea:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
+ 80016f0:	7ffb      	ldrb	r3, [r7, #31]
+ 80016f2:	1e5a      	subs	r2, r3, #1
+ 80016f4:	7ffb      	ldrb	r3, [r7, #31]
+ 80016f6:	4952      	ldr	r1, [pc, #328]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 80016f8:	f931 1022 	ldrsh.w	r1, [r1, r2, lsl #2]
+ 80016fc:	4a50      	ldr	r2, [pc, #320]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 80016fe:	f822 1023 	strh.w	r1, [r2, r3, lsl #2]
 		ec_dut_samples[i][1] = ec_dut_samples[i-1][1]; //imag
- 80015ee:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 80015f2:	3b01      	subs	r3, #1
- 80015f4:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 80015f8:	4916      	ldr	r1, [pc, #88]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 80015fa:	009b      	lsls	r3, r3, #2
- 80015fc:	440b      	add	r3, r1
- 80015fe:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
- 8001602:	4914      	ldr	r1, [pc, #80]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 8001604:	0093      	lsls	r3, r2, #2
- 8001606:	440b      	add	r3, r1
- 8001608:	4602      	mov	r2, r0
- 800160a:	805a      	strh	r2, [r3, #2]
+ 8001702:	7ffb      	ldrb	r3, [r7, #31]
+ 8001704:	3b01      	subs	r3, #1
+ 8001706:	7ffa      	ldrb	r2, [r7, #31]
+ 8001708:	494d      	ldr	r1, [pc, #308]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 800170a:	009b      	lsls	r3, r3, #2
+ 800170c:	440b      	add	r3, r1
+ 800170e:	f9b3 0002 	ldrsh.w	r0, [r3, #2]
+ 8001712:	494b      	ldr	r1, [pc, #300]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 8001714:	0093      	lsls	r3, r2, #2
+ 8001716:	440b      	add	r3, r1
+ 8001718:	4602      	mov	r2, r0
+ 800171a:	805a      	strh	r2, [r3, #2]
 	for (i = (AD5934_EC_AVERAGES-1); i > 0; i--)
- 800160c:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001610:	3b01      	subs	r3, #1
- 8001612:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 8001616:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800161a:	2b00      	cmp	r3, #0
- 800161c:	d1dc      	bne.n	80015d8 <AD5934_GetImpedance+0x28c>
+ 800171c:	7ffb      	ldrb	r3, [r7, #31]
+ 800171e:	3b01      	subs	r3, #1
+ 8001720:	77fb      	strb	r3, [r7, #31]
+ 8001722:	7ffb      	ldrb	r3, [r7, #31]
+ 8001724:	2b00      	cmp	r3, #0
+ 8001726:	d1e3      	bne.n	80016f0 <AD5934_GetImpedance+0x38>
 	}
 
 	// Read real and imaginary data
 	ec_dut_samples[0][0] = (int16_t)(sample_dut & 0x0000FFFF); //real
- 800161e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 8001620:	b21a      	sxth	r2, r3
- 8001622:	4b0c      	ldr	r3, [pc, #48]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 8001624:	801a      	strh	r2, [r3, #0]
+ 8001728:	69bb      	ldr	r3, [r7, #24]
+ 800172a:	b21a      	sxth	r2, r3
+ 800172c:	4b44      	ldr	r3, [pc, #272]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 800172e:	801a      	strh	r2, [r3, #0]
 	ec_dut_samples[0][1] = (int16_t)((sample_dut & 0xFFFF0000)>>16); //imag
- 8001626:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 8001628:	0c1b      	lsrs	r3, r3, #16
- 800162a:	b21a      	sxth	r2, r3
- 800162c:	4b09      	ldr	r3, [pc, #36]	@ (8001654 <AD5934_GetImpedance+0x308>)
- 800162e:	805a      	strh	r2, [r3, #2]
-	//ec_dut_samples[0][1] = (int16_t)((0xFFFF - (sample_dut & 0xFFFF0000)>>16)); //imag
+ 8001730:	69bb      	ldr	r3, [r7, #24]
+ 8001732:	0c1b      	lsrs	r3, r3, #16
+ 8001734:	b21a      	sxth	r2, r3
+ 8001736:	4b42      	ldr	r3, [pc, #264]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 8001738:	805a      	strh	r2, [r3, #2]
 
 	for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_EC_AVERAGES; i++)
- 8001630:	2300      	movs	r3, #0
- 8001632:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 8001636:	2300      	movs	r3, #0
- 8001638:	607b      	str	r3, [r7, #4]
- 800163a:	2300      	movs	r3, #0
- 800163c:	60bb      	str	r3, [r7, #8]
- 800163e:	e022      	b.n	8001686 <AD5934_GetImpedance+0x33a>
- 8001640:	20000114 	.word	0x20000114
- 8001644:	20000134 	.word	0x20000134
- 8001648:	447a0000 	.word	0x447a0000
- 800164c:	42c80000 	.word	0x42c80000
- 8001650:	40010800 	.word	0x40010800
- 8001654:	200000f4 	.word	0x200000f4
+ 800173a:	2300      	movs	r3, #0
+ 800173c:	77fb      	strb	r3, [r7, #31]
+ 800173e:	2300      	movs	r3, #0
+ 8001740:	603b      	str	r3, [r7, #0]
+ 8001742:	2300      	movs	r3, #0
+ 8001744:	607b      	str	r3, [r7, #4]
+ 8001746:	e012      	b.n	800176e <AD5934_GetImpedance+0xb6>
 	{
 		dut_sum[0] += (int32_t)ec_dut_samples[i][0]; //real
- 8001658:	687b      	ldr	r3, [r7, #4]
- 800165a:	f897 204f 	ldrb.w	r2, [r7, #79]	@ 0x4f
- 800165e:	493e      	ldr	r1, [pc, #248]	@ (8001758 <AD5934_GetImpedance+0x40c>)
- 8001660:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
- 8001664:	4413      	add	r3, r2
- 8001666:	607b      	str	r3, [r7, #4]
+ 8001748:	683b      	ldr	r3, [r7, #0]
+ 800174a:	7ffa      	ldrb	r2, [r7, #31]
+ 800174c:	493c      	ldr	r1, [pc, #240]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 800174e:	f931 2022 	ldrsh.w	r2, [r1, r2, lsl #2]
+ 8001752:	4413      	add	r3, r2
+ 8001754:	603b      	str	r3, [r7, #0]
 		dut_sum[1] += (int32_t)ec_dut_samples[i][1]; //imag
- 8001668:	68ba      	ldr	r2, [r7, #8]
- 800166a:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800166e:	493a      	ldr	r1, [pc, #232]	@ (8001758 <AD5934_GetImpedance+0x40c>)
- 8001670:	009b      	lsls	r3, r3, #2
- 8001672:	440b      	add	r3, r1
- 8001674:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
- 8001678:	4413      	add	r3, r2
- 800167a:	60bb      	str	r3, [r7, #8]
+ 8001756:	687a      	ldr	r2, [r7, #4]
+ 8001758:	7ffb      	ldrb	r3, [r7, #31]
+ 800175a:	4939      	ldr	r1, [pc, #228]	@ (8001840 <AD5934_GetImpedance+0x188>)
+ 800175c:	009b      	lsls	r3, r3, #2
+ 800175e:	440b      	add	r3, r1
+ 8001760:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
+ 8001764:	4413      	add	r3, r2
+ 8001766:	607b      	str	r3, [r7, #4]
 	for (i = 0, dut_sum[0]=0, dut_sum[1]=0; i < AD5934_EC_AVERAGES; i++)
- 800167c:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 8001680:	3301      	adds	r3, #1
- 8001682:	f887 304f 	strb.w	r3, [r7, #79]	@ 0x4f
- 8001686:	f897 304f 	ldrb.w	r3, [r7, #79]	@ 0x4f
- 800168a:	2b07      	cmp	r3, #7
- 800168c:	d9e4      	bls.n	8001658 <AD5934_GetImpedance+0x30c>
+ 8001768:	7ffb      	ldrb	r3, [r7, #31]
+ 800176a:	3301      	adds	r3, #1
+ 800176c:	77fb      	strb	r3, [r7, #31]
+ 800176e:	7ffb      	ldrb	r3, [r7, #31]
+ 8001770:	2b07      	cmp	r3, #7
+ 8001772:	d9e9      	bls.n	8001748 <AD5934_GetImpedance+0x90>
 	}
 
 	real_number = ((float)dut_sum[0])/((float)AD5934_EC_AVERAGES);
- 800168e:	687b      	ldr	r3, [r7, #4]
- 8001690:	4618      	mov	r0, r3
- 8001692:	f7ff f92b 	bl	80008ec <__aeabi_i2f>
- 8001696:	4603      	mov	r3, r0
- 8001698:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 800169c:	4618      	mov	r0, r3
- 800169e:	f7ff fa2d 	bl	8000afc <__aeabi_fdiv>
- 80016a2:	4603      	mov	r3, r0
- 80016a4:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 8001774:	683b      	ldr	r3, [r7, #0]
+ 8001776:	4618      	mov	r0, r3
+ 8001778:	f7ff fa7a 	bl	8000c70 <__aeabi_i2f>
+ 800177c:	4603      	mov	r3, r0
+ 800177e:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 8001782:	4618      	mov	r0, r3
+ 8001784:	f7ff fb7c 	bl	8000e80 <__aeabi_fdiv>
+ 8001788:	4603      	mov	r3, r0
+ 800178a:	617b      	str	r3, [r7, #20]
 	imag_number = ((float)dut_sum[1])/((float)AD5934_EC_AVERAGES);
- 80016a6:	68bb      	ldr	r3, [r7, #8]
- 80016a8:	4618      	mov	r0, r3
- 80016aa:	f7ff f91f 	bl	80008ec <__aeabi_i2f>
- 80016ae:	4603      	mov	r3, r0
- 80016b0:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
- 80016b4:	4618      	mov	r0, r3
- 80016b6:	f7ff fa21 	bl	8000afc <__aeabi_fdiv>
- 80016ba:	4603      	mov	r3, r0
- 80016bc:	637b      	str	r3, [r7, #52]	@ 0x34
+ 800178c:	687b      	ldr	r3, [r7, #4]
+ 800178e:	4618      	mov	r0, r3
+ 8001790:	f7ff fa6e 	bl	8000c70 <__aeabi_i2f>
+ 8001794:	4603      	mov	r3, r0
+ 8001796:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 800179a:	4618      	mov	r0, r3
+ 800179c:	f7ff fb70 	bl	8000e80 <__aeabi_fdiv>
+ 80017a0:	4603      	mov	r3, r0
+ 80017a2:	613b      	str	r3, [r7, #16]
 
 	// Calculate unknown magnitude
 	mag_dut = sqrtf((real_number * real_number) + (imag_number * imag_number));
- 80016be:	6bb9      	ldr	r1, [r7, #56]	@ 0x38
- 80016c0:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
- 80016c2:	f7ff f967 	bl	8000994 <__aeabi_fmul>
- 80016c6:	4603      	mov	r3, r0
- 80016c8:	461c      	mov	r4, r3
- 80016ca:	6b79      	ldr	r1, [r7, #52]	@ 0x34
- 80016cc:	6b78      	ldr	r0, [r7, #52]	@ 0x34
- 80016ce:	f7ff f961 	bl	8000994 <__aeabi_fmul>
- 80016d2:	4603      	mov	r3, r0
- 80016d4:	4619      	mov	r1, r3
- 80016d6:	4620      	mov	r0, r4
- 80016d8:	f7ff f854 	bl	8000784 <__addsf3>
- 80016dc:	4603      	mov	r3, r0
- 80016de:	4618      	mov	r0, r3
- 80016e0:	f004 fb42 	bl	8005d68 <sqrtf>
- 80016e4:	6278      	str	r0, [r7, #36]	@ 0x24
+ 80017a4:	6979      	ldr	r1, [r7, #20]
+ 80017a6:	6978      	ldr	r0, [r7, #20]
+ 80017a8:	f7ff fab6 	bl	8000d18 <__aeabi_fmul>
+ 80017ac:	4603      	mov	r3, r0
+ 80017ae:	461c      	mov	r4, r3
+ 80017b0:	6939      	ldr	r1, [r7, #16]
+ 80017b2:	6938      	ldr	r0, [r7, #16]
+ 80017b4:	f7ff fab0 	bl	8000d18 <__aeabi_fmul>
+ 80017b8:	4603      	mov	r3, r0
+ 80017ba:	4619      	mov	r1, r3
+ 80017bc:	4620      	mov	r0, r4
+ 80017be:	f7ff f9a3 	bl	8000b08 <__addsf3>
+ 80017c2:	4603      	mov	r3, r0
+ 80017c4:	4618      	mov	r0, r3
+ 80017c6:	f006 f86b 	bl	80078a0 <sqrtf>
+ 80017ca:	60f8      	str	r0, [r7, #12]
+
 
 	// Calculate gain factor for the unknown magnitude
 
-	if(mag_ref_H != mag_ref_L)
- 80016e6:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
- 80016e8:	6b38      	ldr	r0, [r7, #48]	@ 0x30
- 80016ea:	f7ff fae7 	bl	8000cbc <__aeabi_fcmpeq>
- 80016ee:	4603      	mov	r3, r0
- 80016f0:	2b00      	cmp	r3, #0
- 80016f2:	d12b      	bne.n	800174c <AD5934_GetImpedance+0x400>
-		slope = ((gain_factor_H - gain_factor_L)/(mag_ref_H - mag_ref_L));
- 80016f4:	6c79      	ldr	r1, [r7, #68]	@ 0x44
- 80016f6:	6cb8      	ldr	r0, [r7, #72]	@ 0x48
- 80016f8:	f7ff f842 	bl	8000780 <__aeabi_fsub>
- 80016fc:	4603      	mov	r3, r0
- 80016fe:	461c      	mov	r4, r3
- 8001700:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
- 8001702:	6b38      	ldr	r0, [r7, #48]	@ 0x30
- 8001704:	f7ff f83c 	bl	8000780 <__aeabi_fsub>
- 8001708:	4603      	mov	r3, r0
- 800170a:	4619      	mov	r1, r3
- 800170c:	4620      	mov	r0, r4
- 800170e:	f7ff f9f5 	bl	8000afc <__aeabi_fdiv>
- 8001712:	4603      	mov	r3, r0
- 8001714:	623b      	str	r3, [r7, #32]
-		//slope = ((gain_factor_H - gain_factor_L)/(log10f(mag_ref_H) - log10f(mag_ref_L)));
+	if(main_state == STATE_SETUP_CALIBRATION)
+ 80017cc:	4b1d      	ldr	r3, [pc, #116]	@ (8001844 <AD5934_GetImpedance+0x18c>)
+ 80017ce:	781b      	ldrb	r3, [r3, #0]
+ 80017d0:	2b01      	cmp	r3, #1
+ 80017d2:	d101      	bne.n	80017d8 <AD5934_GetImpedance+0x120>
+		return(mag_dut);
+ 80017d4:	68fb      	ldr	r3, [r7, #12]
+ 80017d6:	e02d      	b.n	8001834 <AD5934_GetImpedance+0x17c>
+	else if(flash_data.ec12880_value != flash_data.ec1413_value)
+ 80017d8:	4b1b      	ldr	r3, [pc, #108]	@ (8001848 <AD5934_GetImpedance+0x190>)
+ 80017da:	691b      	ldr	r3, [r3, #16]
+ 80017dc:	4a1a      	ldr	r2, [pc, #104]	@ (8001848 <AD5934_GetImpedance+0x190>)
+ 80017de:	68d2      	ldr	r2, [r2, #12]
+ 80017e0:	4611      	mov	r1, r2
+ 80017e2:	4618      	mov	r0, r3
+ 80017e4:	f7ff fc2c 	bl	8001040 <__aeabi_fcmpeq>
+ 80017e8:	4603      	mov	r3, r0
+ 80017ea:	2b00      	cmp	r3, #0
+ 80017ec:	d120      	bne.n	8001830 <AD5934_GetImpedance+0x178>
+	{
+		slope = ((AD5934_GAIN_FACTOR_12880US - AD5934_GAIN_FACTOR_1413US)/(flash_data.ec12880_value - flash_data.ec1413_value));
+ 80017ee:	4b16      	ldr	r3, [pc, #88]	@ (8001848 <AD5934_GetImpedance+0x190>)
+ 80017f0:	691b      	ldr	r3, [r3, #16]
+ 80017f2:	4a15      	ldr	r2, [pc, #84]	@ (8001848 <AD5934_GetImpedance+0x190>)
+ 80017f4:	68d2      	ldr	r2, [r2, #12]
+ 80017f6:	4611      	mov	r1, r2
+ 80017f8:	4618      	mov	r0, r3
+ 80017fa:	f7ff f983 	bl	8000b04 <__aeabi_fsub>
+ 80017fe:	4603      	mov	r3, r0
+ 8001800:	4619      	mov	r1, r3
+ 8001802:	4812      	ldr	r0, [pc, #72]	@ (800184c <AD5934_GetImpedance+0x194>)
+ 8001804:	f7ff fb3c 	bl	8000e80 <__aeabi_fdiv>
+ 8001808:	4603      	mov	r3, r0
+ 800180a:	60bb      	str	r3, [r7, #8]
+
+		return(AD5934_GAIN_FACTOR_1413US + (mag_dut - flash_data.ec1413_value) * slope);
+ 800180c:	4b0e      	ldr	r3, [pc, #56]	@ (8001848 <AD5934_GetImpedance+0x190>)
+ 800180e:	68db      	ldr	r3, [r3, #12]
+ 8001810:	4619      	mov	r1, r3
+ 8001812:	68f8      	ldr	r0, [r7, #12]
+ 8001814:	f7ff f976 	bl	8000b04 <__aeabi_fsub>
+ 8001818:	4603      	mov	r3, r0
+ 800181a:	68b9      	ldr	r1, [r7, #8]
+ 800181c:	4618      	mov	r0, r3
+ 800181e:	f7ff fa7b 	bl	8000d18 <__aeabi_fmul>
+ 8001822:	4603      	mov	r3, r0
+ 8001824:	490a      	ldr	r1, [pc, #40]	@ (8001850 <AD5934_GetImpedance+0x198>)
+ 8001826:	4618      	mov	r0, r3
+ 8001828:	f7ff f96e 	bl	8000b08 <__addsf3>
+ 800182c:	4603      	mov	r3, r0
+ 800182e:	e001      	b.n	8001834 <AD5934_GetImpedance+0x17c>
+	}
 	else
 		return 0.0f;
-
-	//gain_factor_dut = gain_factor_L + (log10f(mag_dut) - log10f(mag_ref_L)) * slope;
-	gain_factor_dut = gain_factor_L + (mag_dut - mag_ref_L) * slope;
- 8001716:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
- 8001718:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 800171a:	f7ff f831 	bl	8000780 <__aeabi_fsub>
- 800171e:	4603      	mov	r3, r0
- 8001720:	6a39      	ldr	r1, [r7, #32]
- 8001722:	4618      	mov	r0, r3
- 8001724:	f7ff f936 	bl	8000994 <__aeabi_fmul>
- 8001728:	4603      	mov	r3, r0
- 800172a:	4619      	mov	r1, r3
- 800172c:	6c78      	ldr	r0, [r7, #68]	@ 0x44
- 800172e:	f7ff f829 	bl	8000784 <__addsf3>
- 8001732:	4603      	mov	r3, r0
- 8001734:	61fb      	str	r3, [r7, #28]
-
-	// Calculate and return admittance in mS
-	return(10.0f * mag_dut * gain_factor_dut);
- 8001736:	4909      	ldr	r1, [pc, #36]	@ (800175c <AD5934_GetImpedance+0x410>)
- 8001738:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 800173a:	f7ff f92b 	bl	8000994 <__aeabi_fmul>
- 800173e:	4603      	mov	r3, r0
- 8001740:	69f9      	ldr	r1, [r7, #28]
- 8001742:	4618      	mov	r0, r3
- 8001744:	f7ff f926 	bl	8000994 <__aeabi_fmul>
- 8001748:	4603      	mov	r3, r0
- 800174a:	e001      	b.n	8001750 <AD5934_GetImpedance+0x404>
-		return 0.0f;
- 800174c:	f04f 0300 	mov.w	r3, #0
-
+ 8001830:	f04f 0300 	mov.w	r3, #0
 }
- 8001750:	4618      	mov	r0, r3
- 8001752:	3754      	adds	r7, #84	@ 0x54
- 8001754:	46bd      	mov	sp, r7
- 8001756:	bd90      	pop	{r4, r7, pc}
- 8001758:	200000f4 	.word	0x200000f4
- 800175c:	41200000 	.word	0x41200000
+ 8001834:	4618      	mov	r0, r3
+ 8001836:	3724      	adds	r7, #36	@ 0x24
+ 8001838:	46bd      	mov	sp, r7
+ 800183a:	bd90      	pop	{r4, r7, pc}
+ 800183c:	40010800 	.word	0x40010800
+ 8001840:	200000fc 	.word	0x200000fc
+ 8001844:	200006a8 	.word	0x200006a8
+ 8001848:	200001f8 	.word	0x200001f8
+ 800184c:	46332c00 	.word	0x46332c00
+ 8001850:	44b0a000 	.word	0x44b0a000
 
-08001760 <AD5934_Wait_For_Data_Valid>:
+08001854 <AD5934_Wait_For_Data_Valid>:
 
 /**
  * @brief Monitora o status com TIMEOUT para evitar travamento do sistema.
  */
 void AD5934_Wait_For_Data_Valid(void)
 {
- 8001760:	b580      	push	{r7, lr}
- 8001762:	b084      	sub	sp, #16
- 8001764:	af00      	add	r7, sp, #0
+ 8001854:	b580      	push	{r7, lr}
+ 8001856:	b084      	sub	sp, #16
+ 8001858:	af00      	add	r7, sp, #0
     uint32_t  timeout_counter = 0;
- 8001766:	2300      	movs	r3, #0
- 8001768:	60fb      	str	r3, [r7, #12]
+ 800185a:	2300      	movs	r3, #0
+ 800185c:	60fb      	str	r3, [r7, #12]
     const uint32_t MAX_TIMEOUT = 10000; // Limite de tentativas
- 800176a:	f242 7310 	movw	r3, #10000	@ 0x2710
- 800176e:	60bb      	str	r3, [r7, #8]
+ 800185e:	f242 7310 	movw	r3, #10000	@ 0x2710
+ 8001862:	60bb      	str	r3, [r7, #8]
     uint8_t status;
 
     while (1)
     {
         status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
- 8001770:	2101      	movs	r1, #1
- 8001772:	208f      	movs	r0, #143	@ 0x8f
- 8001774:	f7ff fb42 	bl	8000dfc <AD5934_GetRegisterValue>
- 8001778:	4603      	mov	r3, r0
- 800177a:	71fb      	strb	r3, [r7, #7]
+ 8001864:	2101      	movs	r1, #1
+ 8001866:	208f      	movs	r0, #143	@ 0x8f
+ 8001868:	f7ff fc8a 	bl	8001180 <AD5934_GetRegisterValue>
+ 800186c:	4603      	mov	r3, r0
+ 800186e:	71fb      	strb	r3, [r7, #7]
 
         if ((status & AD5934_STATUS_DATA_VALID) != 0)
- 800177c:	79fb      	ldrb	r3, [r7, #7]
- 800177e:	f003 0302 	and.w	r3, r3, #2
- 8001782:	2b00      	cmp	r3, #0
- 8001784:	d10a      	bne.n	800179c <AD5934_Wait_For_Data_Valid+0x3c>
+ 8001870:	79fb      	ldrb	r3, [r7, #7]
+ 8001872:	f003 0302 	and.w	r3, r3, #2
+ 8001876:	2b00      	cmp	r3, #0
+ 8001878:	d10a      	bne.n	8001890 <AD5934_Wait_For_Data_Valid+0x3c>
         {
             break; // Sucesso!
         }
 
         timeout_counter++;
- 8001786:	68fb      	ldr	r3, [r7, #12]
- 8001788:	3301      	adds	r3, #1
- 800178a:	60fb      	str	r3, [r7, #12]
+ 800187a:	68fb      	ldr	r3, [r7, #12]
+ 800187c:	3301      	adds	r3, #1
+ 800187e:	60fb      	str	r3, [r7, #12]
         if (timeout_counter >= MAX_TIMEOUT)
- 800178c:	68fa      	ldr	r2, [r7, #12]
- 800178e:	68bb      	ldr	r3, [r7, #8]
- 8001790:	429a      	cmp	r2, r3
- 8001792:	d205      	bcs.n	80017a0 <AD5934_Wait_For_Data_Valid+0x40>
+ 8001880:	68fa      	ldr	r2, [r7, #12]
+ 8001882:	68bb      	ldr	r3, [r7, #8]
+ 8001884:	429a      	cmp	r2, r3
+ 8001886:	d205      	bcs.n	8001894 <AD5934_Wait_For_Data_Valid+0x40>
         {
             // TRATAMENTO DE ERRO: O sistema não travou, mas o chip falhou.
             break;
         }
 
         HAL_Delay(1); // Pequeno delay para não sobrecarregar o barramento I2C
- 8001794:	2001      	movs	r0, #1
- 8001796:	f001 f9e1 	bl	8002b5c <HAL_Delay>
+ 8001888:	2001      	movs	r0, #1
+ 800188a:	f001 fd2d 	bl	80032e8 <HAL_Delay>
         status = (uint8_t)AD5934_GetRegisterValue(AD5934_STATUS_REG, 1);
- 800179a:	e7e9      	b.n	8001770 <AD5934_Wait_For_Data_Valid+0x10>
+ 800188e:	e7e9      	b.n	8001864 <AD5934_Wait_For_Data_Valid+0x10>
             break; // Sucesso!
- 800179c:	bf00      	nop
- 800179e:	e000      	b.n	80017a2 <AD5934_Wait_For_Data_Valid+0x42>
+ 8001890:	bf00      	nop
+ 8001892:	e000      	b.n	8001896 <AD5934_Wait_For_Data_Valid+0x42>
             break;
- 80017a0:	bf00      	nop
+ 8001894:	bf00      	nop
     }
 }
- 80017a2:	bf00      	nop
- 80017a4:	3710      	adds	r7, #16
- 80017a6:	46bd      	mov	sp, r7
- 80017a8:	bd80      	pop	{r7, pc}
+ 8001896:	bf00      	nop
+ 8001898:	3710      	adds	r7, #16
+ 800189a:	46bd      	mov	sp, r7
+ 800189c:	bd80      	pop	{r7, pc}
 	...
 
-080017ac <AD5934_Round_Float_Precision>:
+080018a0 <AD5934_Round_Float_Precision>:
  * @param valor O valor float original.
  * @param casas_decimais Quantidade de casas que devem permanecer após a vírgula.
  * @return float O valor com as casas decimais excedentes removidas.
  */
 float AD5934_Round_Float_Precision(float value, uint8_t number_of_decimals)
 {
- 80017ac:	b580      	push	{r7, lr}
- 80017ae:	b084      	sub	sp, #16
- 80017b0:	af00      	add	r7, sp, #0
- 80017b2:	6078      	str	r0, [r7, #4]
- 80017b4:	460b      	mov	r3, r1
- 80017b6:	70fb      	strb	r3, [r7, #3]
+ 80018a0:	b580      	push	{r7, lr}
+ 80018a2:	b084      	sub	sp, #16
+ 80018a4:	af00      	add	r7, sp, #0
+ 80018a6:	6078      	str	r0, [r7, #4]
+ 80018a8:	460b      	mov	r3, r1
+ 80018aa:	70fb      	strb	r3, [r7, #3]
     float multiply = 1.0f;
- 80017b8:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
- 80017bc:	60fb      	str	r3, [r7, #12]
+ 80018ac:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
+ 80018b0:	60fb      	str	r3, [r7, #12]
 
     for (uint8_t i = 0; i < number_of_decimals; i++)
- 80017be:	2300      	movs	r3, #0
- 80017c0:	72fb      	strb	r3, [r7, #11]
- 80017c2:	e008      	b.n	80017d6 <AD5934_Round_Float_Precision+0x2a>
+ 80018b2:	2300      	movs	r3, #0
+ 80018b4:	72fb      	strb	r3, [r7, #11]
+ 80018b6:	e008      	b.n	80018ca <AD5934_Round_Float_Precision+0x2a>
     	multiply *= 10.0f;
- 80017c4:	490f      	ldr	r1, [pc, #60]	@ (8001804 <AD5934_Round_Float_Precision+0x58>)
- 80017c6:	68f8      	ldr	r0, [r7, #12]
- 80017c8:	f7ff f8e4 	bl	8000994 <__aeabi_fmul>
- 80017cc:	4603      	mov	r3, r0
- 80017ce:	60fb      	str	r3, [r7, #12]
+ 80018b8:	490f      	ldr	r1, [pc, #60]	@ (80018f8 <AD5934_Round_Float_Precision+0x58>)
+ 80018ba:	68f8      	ldr	r0, [r7, #12]
+ 80018bc:	f7ff fa2c 	bl	8000d18 <__aeabi_fmul>
+ 80018c0:	4603      	mov	r3, r0
+ 80018c2:	60fb      	str	r3, [r7, #12]
     for (uint8_t i = 0; i < number_of_decimals; i++)
- 80017d0:	7afb      	ldrb	r3, [r7, #11]
- 80017d2:	3301      	adds	r3, #1
- 80017d4:	72fb      	strb	r3, [r7, #11]
- 80017d6:	7afa      	ldrb	r2, [r7, #11]
- 80017d8:	78fb      	ldrb	r3, [r7, #3]
- 80017da:	429a      	cmp	r2, r3
- 80017dc:	d3f2      	bcc.n	80017c4 <AD5934_Round_Float_Precision+0x18>
+ 80018c4:	7afb      	ldrb	r3, [r7, #11]
+ 80018c6:	3301      	adds	r3, #1
+ 80018c8:	72fb      	strb	r3, [r7, #11]
+ 80018ca:	7afa      	ldrb	r2, [r7, #11]
+ 80018cc:	78fb      	ldrb	r3, [r7, #3]
+ 80018ce:	429a      	cmp	r2, r3
+ 80018d0:	d3f2      	bcc.n	80018b8 <AD5934_Round_Float_Precision+0x18>
 
     return roundf(value * multiply) / multiply;
- 80017de:	68f9      	ldr	r1, [r7, #12]
- 80017e0:	6878      	ldr	r0, [r7, #4]
- 80017e2:	f7ff f8d7 	bl	8000994 <__aeabi_fmul>
- 80017e6:	4603      	mov	r3, r0
- 80017e8:	4618      	mov	r0, r3
- 80017ea:	f004 fb4d 	bl	8005e88 <roundf>
- 80017ee:	4603      	mov	r3, r0
- 80017f0:	68f9      	ldr	r1, [r7, #12]
- 80017f2:	4618      	mov	r0, r3
- 80017f4:	f7ff f982 	bl	8000afc <__aeabi_fdiv>
- 80017f8:	4603      	mov	r3, r0
+ 80018d2:	68f9      	ldr	r1, [r7, #12]
+ 80018d4:	6878      	ldr	r0, [r7, #4]
+ 80018d6:	f7ff fa1f 	bl	8000d18 <__aeabi_fmul>
+ 80018da:	4603      	mov	r3, r0
+ 80018dc:	4618      	mov	r0, r3
+ 80018de:	f006 f86f 	bl	80079c0 <roundf>
+ 80018e2:	4603      	mov	r3, r0
+ 80018e4:	68f9      	ldr	r1, [r7, #12]
+ 80018e6:	4618      	mov	r0, r3
+ 80018e8:	f7ff faca 	bl	8000e80 <__aeabi_fdiv>
+ 80018ec:	4603      	mov	r3, r0
 }
- 80017fa:	4618      	mov	r0, r3
- 80017fc:	3710      	adds	r7, #16
- 80017fe:	46bd      	mov	sp, r7
- 8001800:	bd80      	pop	{r7, pc}
- 8001802:	bf00      	nop
- 8001804:	41200000 	.word	0x41200000
+ 80018ee:	4618      	mov	r0, r3
+ 80018f0:	3710      	adds	r7, #16
+ 80018f2:	46bd      	mov	sp, r7
+ 80018f4:	bd80      	pop	{r7, pc}
+ 80018f6:	bf00      	nop
+ 80018f8:	41200000 	.word	0x41200000
 
-08001808 <AD5934_Linear_Correction>:
+080018fc <AD5934_Linear_Correction>:
  *
  * @param input_val The raw float value from sensor/ADC.
  * @return float The transformed value following the requested trend.
  */
 float AD5934_Linear_Correction(float raw_value)
 {
- 8001808:	b580      	push	{r7, lr}
- 800180a:	b084      	sub	sp, #16
- 800180c:	af00      	add	r7, sp, #0
- 800180e:	6078      	str	r0, [r7, #4]
+ 80018fc:	b580      	push	{r7, lr}
+ 80018fe:	b084      	sub	sp, #16
+ 8001900:	af00      	add	r7, sp, #0
+ 8001902:	6078      	str	r0, [r7, #4]
     /* Pre-calculated constants from regression analysis */
     const float slope = 1.02281f;
- 8001810:	4b08      	ldr	r3, [pc, #32]	@ (8001834 <AD5934_Linear_Correction+0x2c>)
- 8001812:	60fb      	str	r3, [r7, #12]
+ 8001904:	4b08      	ldr	r3, [pc, #32]	@ (8001928 <AD5934_Linear_Correction+0x2c>)
+ 8001906:	60fb      	str	r3, [r7, #12]
     const float offset = (-2.1409f);
- 8001814:	4b08      	ldr	r3, [pc, #32]	@ (8001838 <AD5934_Linear_Correction+0x30>)
- 8001816:	60bb      	str	r3, [r7, #8]
+ 8001908:	4b08      	ldr	r3, [pc, #32]	@ (800192c <AD5934_Linear_Correction+0x30>)
+ 800190a:	60bb      	str	r3, [r7, #8]
 
     /* Single FPU instruction (if FPU available) or optimized software float mul/add */
     return (raw_value * slope) + offset;
- 8001818:	68f9      	ldr	r1, [r7, #12]
- 800181a:	6878      	ldr	r0, [r7, #4]
- 800181c:	f7ff f8ba 	bl	8000994 <__aeabi_fmul>
- 8001820:	4603      	mov	r3, r0
- 8001822:	68b9      	ldr	r1, [r7, #8]
- 8001824:	4618      	mov	r0, r3
- 8001826:	f7fe ffad 	bl	8000784 <__addsf3>
- 800182a:	4603      	mov	r3, r0
+ 800190c:	68f9      	ldr	r1, [r7, #12]
+ 800190e:	6878      	ldr	r0, [r7, #4]
+ 8001910:	f7ff fa02 	bl	8000d18 <__aeabi_fmul>
+ 8001914:	4603      	mov	r3, r0
+ 8001916:	68b9      	ldr	r1, [r7, #8]
+ 8001918:	4618      	mov	r0, r3
+ 800191a:	f7ff f8f5 	bl	8000b08 <__addsf3>
+ 800191e:	4603      	mov	r3, r0
 }
- 800182c:	4618      	mov	r0, r3
- 800182e:	3710      	adds	r7, #16
- 8001830:	46bd      	mov	sp, r7
- 8001832:	bd80      	pop	{r7, pc}
- 8001834:	3f82eb70 	.word	0x3f82eb70
- 8001838:	c0090481 	.word	0xc0090481
+ 8001920:	4618      	mov	r0, r3
+ 8001922:	3710      	adds	r7, #16
+ 8001924:	46bd      	mov	sp, r7
+ 8001926:	bd80      	pop	{r7, pc}
+ 8001928:	3f82eb70 	.word	0x3f82eb70
+ 800192c:	c0090481 	.word	0xc0090481
 
-0800183c <ADG715_SetRegisterValue>:
+08001930 <ADG715_SetRegisterValue>:
  *
  * @return None.
 *******************************************************************************/
 
 void ADG715_SetRegisterValue(char value)
 {
- 800183c:	b580      	push	{r7, lr}
- 800183e:	b086      	sub	sp, #24
- 8001840:	af02      	add	r7, sp, #8
- 8001842:	4603      	mov	r3, r0
- 8001844:	71fb      	strb	r3, [r7, #7]
+ 8001930:	b580      	push	{r7, lr}
+ 8001932:	b086      	sub	sp, #24
+ 8001934:	af02      	add	r7, sp, #8
+ 8001936:	4603      	mov	r3, r0
+ 8001938:	71fb      	strb	r3, [r7, #7]
 	uint8_t  writeData[1]	= {value};
- 8001846:	79fb      	ldrb	r3, [r7, #7]
- 8001848:	733b      	strb	r3, [r7, #12]
+ 800193a:	79fb      	ldrb	r3, [r7, #7]
+ 800193c:	733b      	strb	r3, [r7, #12]
 	HAL_StatusTypeDef status;
 
 	status = HAL_I2C_Master_Transmit(&hi2c2, ADG715_I2C_ADDRESS, writeData, 1, 1);
- 800184a:	f107 020c 	add.w	r2, r7, #12
- 800184e:	2301      	movs	r3, #1
- 8001850:	9300      	str	r3, [sp, #0]
- 8001852:	2301      	movs	r3, #1
- 8001854:	2190      	movs	r1, #144	@ 0x90
- 8001856:	4804      	ldr	r0, [pc, #16]	@ (8001868 <ADG715_SetRegisterValue+0x2c>)
- 8001858:	f002 f886 	bl	8003968 <HAL_I2C_Master_Transmit>
- 800185c:	4603      	mov	r3, r0
- 800185e:	73fb      	strb	r3, [r7, #15]
+ 800193e:	f107 020c 	add.w	r2, r7, #12
+ 8001942:	2301      	movs	r3, #1
+ 8001944:	9300      	str	r3, [sp, #0]
+ 8001946:	2301      	movs	r3, #1
+ 8001948:	2190      	movs	r1, #144	@ 0x90
+ 800194a:	4804      	ldr	r0, [pc, #16]	@ (800195c <ADG715_SetRegisterValue+0x2c>)
+ 800194c:	f003 fa20 	bl	8004d90 <HAL_I2C_Master_Transmit>
+ 8001950:	4603      	mov	r3, r0
+ 8001952:	73fb      	strb	r3, [r7, #15]
 
 	return;
- 8001860:	bf00      	nop
+ 8001954:	bf00      	nop
 }
- 8001862:	3710      	adds	r7, #16
- 8001864:	46bd      	mov	sp, r7
- 8001866:	bd80      	pop	{r7, pc}
- 8001868:	20000228 	.word	0x20000228
+ 8001956:	3710      	adds	r7, #16
+ 8001958:	46bd      	mov	sp, r7
+ 800195a:	bd80      	pop	{r7, pc}
+ 800195c:	20000654 	.word	0x20000654
 
-0800186c <ADG715_SetChannels>:
+08001960 <ADG715_SetChannels>:
 
 void ADG715_SetChannels(uint8_t ch1, uint8_t ch2)
 {
- 800186c:	b580      	push	{r7, lr}
- 800186e:	b082      	sub	sp, #8
- 8001870:	af00      	add	r7, sp, #0
- 8001872:	4603      	mov	r3, r0
- 8001874:	460a      	mov	r2, r1
- 8001876:	71fb      	strb	r3, [r7, #7]
- 8001878:	4613      	mov	r3, r2
- 800187a:	71bb      	strb	r3, [r7, #6]
+ 8001960:	b580      	push	{r7, lr}
+ 8001962:	b082      	sub	sp, #8
+ 8001964:	af00      	add	r7, sp, #0
+ 8001966:	4603      	mov	r3, r0
+ 8001968:	460a      	mov	r2, r1
+ 800196a:	71fb      	strb	r3, [r7, #7]
+ 800196c:	4613      	mov	r3, r2
+ 800196e:	71bb      	strb	r3, [r7, #6]
 	ADG715_SetRegisterValue(ch1+ch2);
- 800187c:	79fa      	ldrb	r2, [r7, #7]
- 800187e:	79bb      	ldrb	r3, [r7, #6]
- 8001880:	4413      	add	r3, r2
- 8001882:	b2db      	uxtb	r3, r3
- 8001884:	4618      	mov	r0, r3
- 8001886:	f7ff ffd9 	bl	800183c <ADG715_SetRegisterValue>
+ 8001970:	79fa      	ldrb	r2, [r7, #7]
+ 8001972:	79bb      	ldrb	r3, [r7, #6]
+ 8001974:	4413      	add	r3, r2
+ 8001976:	b2db      	uxtb	r3, r3
+ 8001978:	4618      	mov	r0, r3
+ 800197a:	f7ff ffd9 	bl	8001930 <ADG715_SetRegisterValue>
 }
- 800188a:	bf00      	nop
- 800188c:	3708      	adds	r7, #8
- 800188e:	46bd      	mov	sp, r7
- 8001890:	bd80      	pop	{r7, pc}
+ 800197e:	bf00      	nop
+ 8001980:	3708      	adds	r7, #8
+ 8001982:	46bd      	mov	sp, r7
+ 8001984:	bd80      	pop	{r7, pc}
 
-08001892 <ADG715_ResetChannels>:
+08001986 <ADG715_ResetChannels>:
 
 void ADG715_ResetChannels(void)
 {
- 8001892:	b580      	push	{r7, lr}
- 8001894:	af00      	add	r7, sp, #0
+ 8001986:	b580      	push	{r7, lr}
+ 8001988:	af00      	add	r7, sp, #0
 	ADG715_SetRegisterValue(0);
- 8001896:	2000      	movs	r0, #0
- 8001898:	f7ff ffd0 	bl	800183c <ADG715_SetRegisterValue>
+ 800198a:	2000      	movs	r0, #0
+ 800198c:	f7ff ffd0 	bl	8001930 <ADG715_SetRegisterValue>
 }
- 800189c:	bf00      	nop
- 800189e:	bd80      	pop	{r7, pc}
+ 8001990:	bf00      	nop
+ 8001992:	bd80      	pop	{r7, pc}
 
-080018a0 <ADG715_Update>:
+08001994 <ADG715_Update>:
 * @param: channel = AD5934_CH_REF_100R, AD5934_CH_REF_1K, AD5934_CH_REF_10K, AD5934_CH_PT100, AD5934_CH_PT1000 or AD5934_CH_EC
 *
 * @return none.
 ******************************************************************************/
 void ADG715_Update(uint8_t channel)
 {
- 80018a0:	b580      	push	{r7, lr}
- 80018a2:	b082      	sub	sp, #8
- 80018a4:	af00      	add	r7, sp, #0
- 80018a6:	4603      	mov	r3, r0
- 80018a8:	71fb      	strb	r3, [r7, #7]
+ 8001994:	b580      	push	{r7, lr}
+ 8001996:	b082      	sub	sp, #8
+ 8001998:	af00      	add	r7, sp, #0
+ 800199a:	4603      	mov	r3, r0
+ 800199c:	71fb      	strb	r3, [r7, #7]
 	HAL_StatusTypeDef status;
 
 	// Disconnect all Analog Switches
 	ADG715_ResetChannels();
- 80018aa:	f7ff fff2 	bl	8001892 <ADG715_ResetChannels>
+ 800199e:	f7ff fff2 	bl	8001986 <ADG715_ResetChannels>
 
 	// Set the pair of connections
-	if(channel == AD5934_CH_REF_100R)
- 80018ae:	79fb      	ldrb	r3, [r7, #7]
- 80018b0:	2b10      	cmp	r3, #16
- 80018b2:	d104      	bne.n	80018be <ADG715_Update+0x1e>
+	if(channel == AD5934_CH_REF100R_LOW_GAIN)
+ 80019a2:	79fb      	ldrb	r3, [r7, #7]
+ 80019a4:	2b09      	cmp	r3, #9
+ 80019a6:	d104      	bne.n	80019b2 <ADG715_Update+0x1e>
 	{
 		ADG715_SetChannels(ADG715_SW1, ADG715_SW4); // Rf = 150R, Ch = Ref_100R
- 80018b4:	2108      	movs	r1, #8
- 80018b6:	2001      	movs	r0, #1
- 80018b8:	f7ff ffd8 	bl	800186c <ADG715_SetChannels>
-	else if(channel == AD5934_CH_EC_5MS)
+ 80019a8:	2108      	movs	r1, #8
+ 80019aa:	2001      	movs	r0, #1
+ 80019ac:	f7ff ffd8 	bl	8001960 <ADG715_SetChannels>
+	else if(channel == AD5934_CH_EC_HIGH_GAIN)
 	{
-		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC 5 mS/cm Max
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC
 	}
 
 }
- 80018bc:	e02e      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_REF_1K)
- 80018be:	79fb      	ldrb	r3, [r7, #7]
- 80018c0:	2b11      	cmp	r3, #17
- 80018c2:	d104      	bne.n	80018ce <ADG715_Update+0x2e>
+ 80019b0:	e06e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF100R_MID_GAIN)
+ 80019b2:	79fb      	ldrb	r3, [r7, #7]
+ 80019b4:	2b0a      	cmp	r3, #10
+ 80019b6:	d104      	bne.n	80019c2 <ADG715_Update+0x2e>
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW4); // Rf = 1k5, Ch = Ref_100R
+ 80019b8:	2108      	movs	r1, #8
+ 80019ba:	2002      	movs	r0, #2
+ 80019bc:	f7ff ffd0 	bl	8001960 <ADG715_SetChannels>
+}
+ 80019c0:	e066      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF100R_HIGH_GAIN)
+ 80019c2:	79fb      	ldrb	r3, [r7, #7]
+ 80019c4:	2b0c      	cmp	r3, #12
+ 80019c6:	d104      	bne.n	80019d2 <ADG715_Update+0x3e>
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW4); // Rf = 6k2, Ch = Ref_100R
+ 80019c8:	2108      	movs	r1, #8
+ 80019ca:	2004      	movs	r0, #4
+ 80019cc:	f7ff ffc8 	bl	8001960 <ADG715_SetChannels>
+}
+ 80019d0:	e05e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF1K_LOW_GAIN)
+ 80019d2:	79fb      	ldrb	r3, [r7, #7]
+ 80019d4:	2b11      	cmp	r3, #17
+ 80019d6:	d104      	bne.n	80019e2 <ADG715_Update+0x4e>
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW5); // Rf = 150R, Ch = Ref_1k
+ 80019d8:	2110      	movs	r1, #16
+ 80019da:	2001      	movs	r0, #1
+ 80019dc:	f7ff ffc0 	bl	8001960 <ADG715_SetChannels>
+}
+ 80019e0:	e056      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF1K_MID_GAIN)
+ 80019e2:	79fb      	ldrb	r3, [r7, #7]
+ 80019e4:	2b12      	cmp	r3, #18
+ 80019e6:	d104      	bne.n	80019f2 <ADG715_Update+0x5e>
 		ADG715_SetChannels(ADG715_SW2, ADG715_SW5); // Rf = 1k5, Ch = Ref_1k
- 80018c4:	2110      	movs	r1, #16
- 80018c6:	2002      	movs	r0, #2
- 80018c8:	f7ff ffd0 	bl	800186c <ADG715_SetChannels>
+ 80019e8:	2110      	movs	r1, #16
+ 80019ea:	2002      	movs	r0, #2
+ 80019ec:	f7ff ffb8 	bl	8001960 <ADG715_SetChannels>
 }
- 80018cc:	e026      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_REF_10K)
- 80018ce:	79fb      	ldrb	r3, [r7, #7]
- 80018d0:	2b12      	cmp	r3, #18
- 80018d2:	d104      	bne.n	80018de <ADG715_Update+0x3e>
+ 80019f0:	e04e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF1K_HIGH_GAIN)
+ 80019f2:	79fb      	ldrb	r3, [r7, #7]
+ 80019f4:	2b14      	cmp	r3, #20
+ 80019f6:	d104      	bne.n	8001a02 <ADG715_Update+0x6e>
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW5); // Rf = 6k2, Ch = Ref_1k
+ 80019f8:	2110      	movs	r1, #16
+ 80019fa:	2004      	movs	r0, #4
+ 80019fc:	f7ff ffb0 	bl	8001960 <ADG715_SetChannels>
+}
+ 8001a00:	e046      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF10K_LOW_GAIN)
+ 8001a02:	79fb      	ldrb	r3, [r7, #7]
+ 8001a04:	2b21      	cmp	r3, #33	@ 0x21
+ 8001a06:	d104      	bne.n	8001a12 <ADG715_Update+0x7e>
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW6); // Rf = 150R, Ch = Ref_10k
+ 8001a08:	2120      	movs	r1, #32
+ 8001a0a:	2001      	movs	r0, #1
+ 8001a0c:	f7ff ffa8 	bl	8001960 <ADG715_SetChannels>
+}
+ 8001a10:	e03e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF10K_MID_GAIN)
+ 8001a12:	79fb      	ldrb	r3, [r7, #7]
+ 8001a14:	2b22      	cmp	r3, #34	@ 0x22
+ 8001a16:	d104      	bne.n	8001a22 <ADG715_Update+0x8e>
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW6); // Rf = 1k5, Ch = Ref_10k
+ 8001a18:	2120      	movs	r1, #32
+ 8001a1a:	2002      	movs	r0, #2
+ 8001a1c:	f7ff ffa0 	bl	8001960 <ADG715_SetChannels>
+}
+ 8001a20:	e036      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_REF10K_HIGH_GAIN)
+ 8001a22:	79fb      	ldrb	r3, [r7, #7]
+ 8001a24:	2b24      	cmp	r3, #36	@ 0x24
+ 8001a26:	d104      	bne.n	8001a32 <ADG715_Update+0x9e>
 		ADG715_SetChannels(ADG715_SW3, ADG715_SW6); // Rf = 6k2, Ch = Ref_10k
- 80018d4:	2120      	movs	r1, #32
- 80018d6:	2004      	movs	r0, #4
- 80018d8:	f7ff ffc8 	bl	800186c <ADG715_SetChannels>
+ 8001a28:	2120      	movs	r1, #32
+ 8001a2a:	2004      	movs	r0, #4
+ 8001a2c:	f7ff ff98 	bl	8001960 <ADG715_SetChannels>
 }
- 80018dc:	e01e      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_PT100)
- 80018de:	79fb      	ldrb	r3, [r7, #7]
- 80018e0:	2b00      	cmp	r3, #0
- 80018e2:	d104      	bne.n	80018ee <ADG715_Update+0x4e>
-		ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = PT100
- 80018e4:	2140      	movs	r1, #64	@ 0x40
- 80018e6:	2001      	movs	r0, #1
- 80018e8:	f7ff ffc0 	bl	800186c <ADG715_SetChannels>
+ 8001a30:	e02e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_RTD_LOW_GAIN)
+ 8001a32:	79fb      	ldrb	r3, [r7, #7]
+ 8001a34:	2b41      	cmp	r3, #65	@ 0x41
+ 8001a36:	d104      	bne.n	8001a42 <ADG715_Update+0xae>
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW7); // Rf = 150R, Ch = RTD
+ 8001a38:	2140      	movs	r1, #64	@ 0x40
+ 8001a3a:	2001      	movs	r0, #1
+ 8001a3c:	f7ff ff90 	bl	8001960 <ADG715_SetChannels>
 }
- 80018ec:	e016      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_PT1000)
- 80018ee:	79fb      	ldrb	r3, [r7, #7]
- 80018f0:	2b01      	cmp	r3, #1
- 80018f2:	d104      	bne.n	80018fe <ADG715_Update+0x5e>
-		ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = PT1000
- 80018f4:	2140      	movs	r1, #64	@ 0x40
- 80018f6:	2002      	movs	r0, #2
- 80018f8:	f7ff ffb8 	bl	800186c <ADG715_SetChannels>
+ 8001a40:	e026      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_RTD_MID_GAIN)
+ 8001a42:	79fb      	ldrb	r3, [r7, #7]
+ 8001a44:	2b42      	cmp	r3, #66	@ 0x42
+ 8001a46:	d104      	bne.n	8001a52 <ADG715_Update+0xbe>
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW7); // Rf = 1k5, Ch = RTD
+ 8001a48:	2140      	movs	r1, #64	@ 0x40
+ 8001a4a:	2002      	movs	r0, #2
+ 8001a4c:	f7ff ff88 	bl	8001960 <ADG715_SetChannels>
 }
- 80018fc:	e00e      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_EC_10MS)
- 80018fe:	79fb      	ldrb	r3, [r7, #7]
- 8001900:	2b21      	cmp	r3, #33	@ 0x21
- 8001902:	d104      	bne.n	800190e <ADG715_Update+0x6e>
-		ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC 10 mS/cm Max
- 8001904:	2180      	movs	r1, #128	@ 0x80
- 8001906:	2002      	movs	r0, #2
- 8001908:	f7ff ffb0 	bl	800186c <ADG715_SetChannels>
+ 8001a50:	e01e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_RTD_HIGH_GAIN)
+ 8001a52:	79fb      	ldrb	r3, [r7, #7]
+ 8001a54:	2b44      	cmp	r3, #68	@ 0x44
+ 8001a56:	d104      	bne.n	8001a62 <ADG715_Update+0xce>
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW7); // Rf = 6k2, Ch = RTD
+ 8001a58:	2140      	movs	r1, #64	@ 0x40
+ 8001a5a:	2004      	movs	r0, #4
+ 8001a5c:	f7ff ff80 	bl	8001960 <ADG715_SetChannels>
 }
- 800190c:	e006      	b.n	800191c <ADG715_Update+0x7c>
-	else if(channel == AD5934_CH_EC_5MS)
- 800190e:	79fb      	ldrb	r3, [r7, #7]
- 8001910:	2b22      	cmp	r3, #34	@ 0x22
- 8001912:	d103      	bne.n	800191c <ADG715_Update+0x7c>
-		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC 5 mS/cm Max
- 8001914:	2180      	movs	r1, #128	@ 0x80
- 8001916:	2004      	movs	r0, #4
- 8001918:	f7ff ffa8 	bl	800186c <ADG715_SetChannels>
+ 8001a60:	e016      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_EC_LOW_GAIN)
+ 8001a62:	79fb      	ldrb	r3, [r7, #7]
+ 8001a64:	2b81      	cmp	r3, #129	@ 0x81
+ 8001a66:	d104      	bne.n	8001a72 <ADG715_Update+0xde>
+		ADG715_SetChannels(ADG715_SW1, ADG715_SW8); // Rf = 150R, Ch = EC
+ 8001a68:	2180      	movs	r1, #128	@ 0x80
+ 8001a6a:	2001      	movs	r0, #1
+ 8001a6c:	f7ff ff78 	bl	8001960 <ADG715_SetChannels>
 }
- 800191c:	bf00      	nop
- 800191e:	3708      	adds	r7, #8
- 8001920:	46bd      	mov	sp, r7
- 8001922:	bd80      	pop	{r7, pc}
+ 8001a70:	e00e      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_EC_MID_GAIN)
+ 8001a72:	79fb      	ldrb	r3, [r7, #7]
+ 8001a74:	2b82      	cmp	r3, #130	@ 0x82
+ 8001a76:	d104      	bne.n	8001a82 <ADG715_Update+0xee>
+		ADG715_SetChannels(ADG715_SW2, ADG715_SW8); // Rf = 1k5, Ch = EC
+ 8001a78:	2180      	movs	r1, #128	@ 0x80
+ 8001a7a:	2002      	movs	r0, #2
+ 8001a7c:	f7ff ff70 	bl	8001960 <ADG715_SetChannels>
+}
+ 8001a80:	e006      	b.n	8001a90 <ADG715_Update+0xfc>
+	else if(channel == AD5934_CH_EC_HIGH_GAIN)
+ 8001a82:	79fb      	ldrb	r3, [r7, #7]
+ 8001a84:	2b84      	cmp	r3, #132	@ 0x84
+ 8001a86:	d103      	bne.n	8001a90 <ADG715_Update+0xfc>
+		ADG715_SetChannels(ADG715_SW3, ADG715_SW8); // Rf = 6k2, Ch = EC
+ 8001a88:	2180      	movs	r1, #128	@ 0x80
+ 8001a8a:	2004      	movs	r0, #4
+ 8001a8c:	f7ff ff68 	bl	8001960 <ADG715_SetChannels>
+}
+ 8001a90:	bf00      	nop
+ 8001a92:	3708      	adds	r7, #8
+ 8001a94:	46bd      	mov	sp, r7
+ 8001a96:	bd80      	pop	{r7, pc}
 
-08001924 <MX_ADC1_Init>:
-ADC_HandleTypeDef hadc1;
+08001a98 <MX_ADC1_Init>:
 ADC_HandleTypeDef hadc2;
+DMA_HandleTypeDef hdma_adc1;
 
 /* ADC1 init function */
 void MX_ADC1_Init(void)
 {
- 8001924:	b580      	push	{r7, lr}
- 8001926:	b084      	sub	sp, #16
- 8001928:	af00      	add	r7, sp, #0
+ 8001a98:	b580      	push	{r7, lr}
+ 8001a9a:	b084      	sub	sp, #16
+ 8001a9c:	af00      	add	r7, sp, #0
 
   /* USER CODE BEGIN ADC1_Init 0 */
 
   /* USER CODE END ADC1_Init 0 */
 
   ADC_ChannelConfTypeDef sConfig = {0};
- 800192a:	1d3b      	adds	r3, r7, #4
- 800192c:	2200      	movs	r2, #0
- 800192e:	601a      	str	r2, [r3, #0]
- 8001930:	605a      	str	r2, [r3, #4]
- 8001932:	609a      	str	r2, [r3, #8]
+ 8001a9e:	1d3b      	adds	r3, r7, #4
+ 8001aa0:	2200      	movs	r2, #0
+ 8001aa2:	601a      	str	r2, [r3, #0]
+ 8001aa4:	605a      	str	r2, [r3, #4]
+ 8001aa6:	609a      	str	r2, [r3, #8]
 
   /* USER CODE END ADC1_Init 1 */
 
   /** Common config
   */
   hadc1.Instance = ADC1;
- 8001934:	4b18      	ldr	r3, [pc, #96]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001936:	4a19      	ldr	r2, [pc, #100]	@ (800199c <MX_ADC1_Init+0x78>)
- 8001938:	601a      	str	r2, [r3, #0]
-  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
- 800193a:	4b17      	ldr	r3, [pc, #92]	@ (8001998 <MX_ADC1_Init+0x74>)
- 800193c:	2200      	movs	r2, #0
- 800193e:	609a      	str	r2, [r3, #8]
+ 8001aa8:	4b20      	ldr	r3, [pc, #128]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001aaa:	4a21      	ldr	r2, [pc, #132]	@ (8001b30 <MX_ADC1_Init+0x98>)
+ 8001aac:	601a      	str	r2, [r3, #0]
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 8001aae:	4b1f      	ldr	r3, [pc, #124]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001ab0:	f44f 7280 	mov.w	r2, #256	@ 0x100
+ 8001ab4:	609a      	str	r2, [r3, #8]
   hadc1.Init.ContinuousConvMode = DISABLE;
- 8001940:	4b15      	ldr	r3, [pc, #84]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001942:	2200      	movs	r2, #0
- 8001944:	731a      	strb	r2, [r3, #12]
+ 8001ab6:	4b1d      	ldr	r3, [pc, #116]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001ab8:	2200      	movs	r2, #0
+ 8001aba:	731a      	strb	r2, [r3, #12]
   hadc1.Init.DiscontinuousConvMode = DISABLE;
- 8001946:	4b14      	ldr	r3, [pc, #80]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001948:	2200      	movs	r2, #0
- 800194a:	751a      	strb	r2, [r3, #20]
-  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
- 800194c:	4b12      	ldr	r3, [pc, #72]	@ (8001998 <MX_ADC1_Init+0x74>)
- 800194e:	f44f 2260 	mov.w	r2, #917504	@ 0xe0000
- 8001952:	61da      	str	r2, [r3, #28]
+ 8001abc:	4b1b      	ldr	r3, [pc, #108]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001abe:	2200      	movs	r2, #0
+ 8001ac0:	751a      	strb	r2, [r3, #20]
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO;
+ 8001ac2:	4b1a      	ldr	r3, [pc, #104]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001ac4:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
+ 8001ac8:	61da      	str	r2, [r3, #28]
   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- 8001954:	4b10      	ldr	r3, [pc, #64]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001956:	2200      	movs	r2, #0
- 8001958:	605a      	str	r2, [r3, #4]
-  hadc1.Init.NbrOfConversion = 1;
- 800195a:	4b0f      	ldr	r3, [pc, #60]	@ (8001998 <MX_ADC1_Init+0x74>)
- 800195c:	2201      	movs	r2, #1
- 800195e:	611a      	str	r2, [r3, #16]
+ 8001aca:	4b18      	ldr	r3, [pc, #96]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001acc:	2200      	movs	r2, #0
+ 8001ace:	605a      	str	r2, [r3, #4]
+  hadc1.Init.NbrOfConversion = 2;
+ 8001ad0:	4b16      	ldr	r3, [pc, #88]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001ad2:	2202      	movs	r2, #2
+ 8001ad4:	611a      	str	r2, [r3, #16]
   if (HAL_ADC_Init(&hadc1) != HAL_OK)
- 8001960:	480d      	ldr	r0, [pc, #52]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001962:	f001 f91f 	bl	8002ba4 <HAL_ADC_Init>
- 8001966:	4603      	mov	r3, r0
- 8001968:	2b00      	cmp	r3, #0
- 800196a:	d001      	beq.n	8001970 <MX_ADC1_Init+0x4c>
+ 8001ad6:	4815      	ldr	r0, [pc, #84]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001ad8:	f001 fc2a 	bl	8003330 <HAL_ADC_Init>
+ 8001adc:	4603      	mov	r3, r0
+ 8001ade:	2b00      	cmp	r3, #0
+ 8001ae0:	d001      	beq.n	8001ae6 <MX_ADC1_Init+0x4e>
   {
     Error_Handler();
- 800196c:	f000 fe80 	bl	8002670 <Error_Handler>
+ 8001ae2:	f001 f915 	bl	8002d10 <Error_Handler>
   }
 
   /** Configure Regular Channel
   */
-  sConfig.Channel = ADC_CHANNEL_0;
- 8001970:	2300      	movs	r3, #0
- 8001972:	607b      	str	r3, [r7, #4]
+  sConfig.Channel = ADC_CHANNEL_VREFINT;
+ 8001ae6:	2311      	movs	r3, #17
+ 8001ae8:	607b      	str	r3, [r7, #4]
   sConfig.Rank = ADC_REGULAR_RANK_1;
- 8001974:	2301      	movs	r3, #1
- 8001976:	60bb      	str	r3, [r7, #8]
-  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
- 8001978:	2300      	movs	r3, #0
- 800197a:	60fb      	str	r3, [r7, #12]
+ 8001aea:	2301      	movs	r3, #1
+ 8001aec:	60bb      	str	r3, [r7, #8]
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
+ 8001aee:	2307      	movs	r3, #7
+ 8001af0:	60fb      	str	r3, [r7, #12]
   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
- 800197c:	1d3b      	adds	r3, r7, #4
- 800197e:	4619      	mov	r1, r3
- 8001980:	4805      	ldr	r0, [pc, #20]	@ (8001998 <MX_ADC1_Init+0x74>)
- 8001982:	f001 f9e7 	bl	8002d54 <HAL_ADC_ConfigChannel>
- 8001986:	4603      	mov	r3, r0
- 8001988:	2b00      	cmp	r3, #0
- 800198a:	d001      	beq.n	8001990 <MX_ADC1_Init+0x6c>
+ 8001af2:	1d3b      	adds	r3, r7, #4
+ 8001af4:	4619      	mov	r1, r3
+ 8001af6:	480d      	ldr	r0, [pc, #52]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001af8:	f001 fde2 	bl	80036c0 <HAL_ADC_ConfigChannel>
+ 8001afc:	4603      	mov	r3, r0
+ 8001afe:	2b00      	cmp	r3, #0
+ 8001b00:	d001      	beq.n	8001b06 <MX_ADC1_Init+0x6e>
   {
     Error_Handler();
- 800198c:	f000 fe70 	bl	8002670 <Error_Handler>
+ 8001b02:	f001 f905 	bl	8002d10 <Error_Handler>
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+ 8001b06:	2310      	movs	r3, #16
+ 8001b08:	607b      	str	r3, [r7, #4]
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+ 8001b0a:	2302      	movs	r3, #2
+ 8001b0c:	60bb      	str	r3, [r7, #8]
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001b0e:	1d3b      	adds	r3, r7, #4
+ 8001b10:	4619      	mov	r1, r3
+ 8001b12:	4806      	ldr	r0, [pc, #24]	@ (8001b2c <MX_ADC1_Init+0x94>)
+ 8001b14:	f001 fdd4 	bl	80036c0 <HAL_ADC_ConfigChannel>
+ 8001b18:	4603      	mov	r3, r0
+ 8001b1a:	2b00      	cmp	r3, #0
+ 8001b1c:	d001      	beq.n	8001b22 <MX_ADC1_Init+0x8a>
+  {
+    Error_Handler();
+ 8001b1e:	f001 f8f7 	bl	8002d10 <Error_Handler>
   }
   /* USER CODE BEGIN ADC1_Init 2 */
 
   /* USER CODE END ADC1_Init 2 */
 
 }
- 8001990:	bf00      	nop
- 8001992:	3710      	adds	r7, #16
- 8001994:	46bd      	mov	sp, r7
- 8001996:	bd80      	pop	{r7, pc}
- 8001998:	20000154 	.word	0x20000154
- 800199c:	40012400 	.word	0x40012400
+ 8001b22:	bf00      	nop
+ 8001b24:	3710      	adds	r7, #16
+ 8001b26:	46bd      	mov	sp, r7
+ 8001b28:	bd80      	pop	{r7, pc}
+ 8001b2a:	bf00      	nop
+ 8001b2c:	2000011c 	.word	0x2000011c
+ 8001b30:	40012400 	.word	0x40012400
 
-080019a0 <MX_ADC2_Init>:
+08001b34 <MX_ADC2_Init>:
 /* ADC2 init function */
 void MX_ADC2_Init(void)
 {
- 80019a0:	b580      	push	{r7, lr}
- 80019a2:	b084      	sub	sp, #16
- 80019a4:	af00      	add	r7, sp, #0
+ 8001b34:	b580      	push	{r7, lr}
+ 8001b36:	b084      	sub	sp, #16
+ 8001b38:	af00      	add	r7, sp, #0
 
   /* USER CODE BEGIN ADC2_Init 0 */
 
   /* USER CODE END ADC2_Init 0 */
 
   ADC_ChannelConfTypeDef sConfig = {0};
- 80019a6:	1d3b      	adds	r3, r7, #4
- 80019a8:	2200      	movs	r2, #0
- 80019aa:	601a      	str	r2, [r3, #0]
- 80019ac:	605a      	str	r2, [r3, #4]
- 80019ae:	609a      	str	r2, [r3, #8]
+ 8001b3a:	1d3b      	adds	r3, r7, #4
+ 8001b3c:	2200      	movs	r2, #0
+ 8001b3e:	601a      	str	r2, [r3, #0]
+ 8001b40:	605a      	str	r2, [r3, #4]
+ 8001b42:	609a      	str	r2, [r3, #8]
 
   /* USER CODE END ADC2_Init 1 */
 
   /** Common config
   */
   hadc2.Instance = ADC2;
- 80019b0:	4b18      	ldr	r3, [pc, #96]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019b2:	4a19      	ldr	r2, [pc, #100]	@ (8001a18 <MX_ADC2_Init+0x78>)
- 80019b4:	601a      	str	r2, [r3, #0]
+ 8001b44:	4b18      	ldr	r3, [pc, #96]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b46:	4a19      	ldr	r2, [pc, #100]	@ (8001bac <MX_ADC2_Init+0x78>)
+ 8001b48:	601a      	str	r2, [r3, #0]
   hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
- 80019b6:	4b17      	ldr	r3, [pc, #92]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019b8:	2200      	movs	r2, #0
- 80019ba:	609a      	str	r2, [r3, #8]
+ 8001b4a:	4b17      	ldr	r3, [pc, #92]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b4c:	2200      	movs	r2, #0
+ 8001b4e:	609a      	str	r2, [r3, #8]
   hadc2.Init.ContinuousConvMode = DISABLE;
- 80019bc:	4b15      	ldr	r3, [pc, #84]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019be:	2200      	movs	r2, #0
- 80019c0:	731a      	strb	r2, [r3, #12]
+ 8001b50:	4b15      	ldr	r3, [pc, #84]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b52:	2200      	movs	r2, #0
+ 8001b54:	731a      	strb	r2, [r3, #12]
   hadc2.Init.DiscontinuousConvMode = DISABLE;
- 80019c2:	4b14      	ldr	r3, [pc, #80]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019c4:	2200      	movs	r2, #0
- 80019c6:	751a      	strb	r2, [r3, #20]
+ 8001b56:	4b14      	ldr	r3, [pc, #80]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b58:	2200      	movs	r2, #0
+ 8001b5a:	751a      	strb	r2, [r3, #20]
   hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
- 80019c8:	4b12      	ldr	r3, [pc, #72]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019ca:	f44f 2260 	mov.w	r2, #917504	@ 0xe0000
- 80019ce:	61da      	str	r2, [r3, #28]
+ 8001b5c:	4b12      	ldr	r3, [pc, #72]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b5e:	f44f 2260 	mov.w	r2, #917504	@ 0xe0000
+ 8001b62:	61da      	str	r2, [r3, #28]
   hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- 80019d0:	4b10      	ldr	r3, [pc, #64]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019d2:	2200      	movs	r2, #0
- 80019d4:	605a      	str	r2, [r3, #4]
+ 8001b64:	4b10      	ldr	r3, [pc, #64]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b66:	2200      	movs	r2, #0
+ 8001b68:	605a      	str	r2, [r3, #4]
   hadc2.Init.NbrOfConversion = 1;
- 80019d6:	4b0f      	ldr	r3, [pc, #60]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019d8:	2201      	movs	r2, #1
- 80019da:	611a      	str	r2, [r3, #16]
+ 8001b6a:	4b0f      	ldr	r3, [pc, #60]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b6c:	2201      	movs	r2, #1
+ 8001b6e:	611a      	str	r2, [r3, #16]
   if (HAL_ADC_Init(&hadc2) != HAL_OK)
- 80019dc:	480d      	ldr	r0, [pc, #52]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019de:	f001 f8e1 	bl	8002ba4 <HAL_ADC_Init>
- 80019e2:	4603      	mov	r3, r0
- 80019e4:	2b00      	cmp	r3, #0
- 80019e6:	d001      	beq.n	80019ec <MX_ADC2_Init+0x4c>
+ 8001b70:	480d      	ldr	r0, [pc, #52]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b72:	f001 fbdd 	bl	8003330 <HAL_ADC_Init>
+ 8001b76:	4603      	mov	r3, r0
+ 8001b78:	2b00      	cmp	r3, #0
+ 8001b7a:	d001      	beq.n	8001b80 <MX_ADC2_Init+0x4c>
   {
     Error_Handler();
- 80019e8:	f000 fe42 	bl	8002670 <Error_Handler>
+ 8001b7c:	f001 f8c8 	bl	8002d10 <Error_Handler>
   }
 
   /** Configure Regular Channel
   */
   sConfig.Channel = ADC_CHANNEL_1;
- 80019ec:	2301      	movs	r3, #1
- 80019ee:	607b      	str	r3, [r7, #4]
+ 8001b80:	2301      	movs	r3, #1
+ 8001b82:	607b      	str	r3, [r7, #4]
   sConfig.Rank = ADC_REGULAR_RANK_1;
- 80019f0:	2301      	movs	r3, #1
- 80019f2:	60bb      	str	r3, [r7, #8]
+ 8001b84:	2301      	movs	r3, #1
+ 8001b86:	60bb      	str	r3, [r7, #8]
   sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
- 80019f4:	2300      	movs	r3, #0
- 80019f6:	60fb      	str	r3, [r7, #12]
+ 8001b88:	2300      	movs	r3, #0
+ 8001b8a:	60fb      	str	r3, [r7, #12]
   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
- 80019f8:	1d3b      	adds	r3, r7, #4
- 80019fa:	4619      	mov	r1, r3
- 80019fc:	4805      	ldr	r0, [pc, #20]	@ (8001a14 <MX_ADC2_Init+0x74>)
- 80019fe:	f001 f9a9 	bl	8002d54 <HAL_ADC_ConfigChannel>
- 8001a02:	4603      	mov	r3, r0
- 8001a04:	2b00      	cmp	r3, #0
- 8001a06:	d001      	beq.n	8001a0c <MX_ADC2_Init+0x6c>
+ 8001b8c:	1d3b      	adds	r3, r7, #4
+ 8001b8e:	4619      	mov	r1, r3
+ 8001b90:	4805      	ldr	r0, [pc, #20]	@ (8001ba8 <MX_ADC2_Init+0x74>)
+ 8001b92:	f001 fd95 	bl	80036c0 <HAL_ADC_ConfigChannel>
+ 8001b96:	4603      	mov	r3, r0
+ 8001b98:	2b00      	cmp	r3, #0
+ 8001b9a:	d001      	beq.n	8001ba0 <MX_ADC2_Init+0x6c>
   {
     Error_Handler();
- 8001a08:	f000 fe32 	bl	8002670 <Error_Handler>
+ 8001b9c:	f001 f8b8 	bl	8002d10 <Error_Handler>
   }
   /* USER CODE BEGIN ADC2_Init 2 */
 
   /* USER CODE END ADC2_Init 2 */
 
 }
- 8001a0c:	bf00      	nop
- 8001a0e:	3710      	adds	r7, #16
- 8001a10:	46bd      	mov	sp, r7
- 8001a12:	bd80      	pop	{r7, pc}
- 8001a14:	20000184 	.word	0x20000184
- 8001a18:	40012800 	.word	0x40012800
+ 8001ba0:	bf00      	nop
+ 8001ba2:	3710      	adds	r7, #16
+ 8001ba4:	46bd      	mov	sp, r7
+ 8001ba6:	bd80      	pop	{r7, pc}
+ 8001ba8:	2000014c 	.word	0x2000014c
+ 8001bac:	40012800 	.word	0x40012800
 
-08001a1c <HAL_ADC_MspInit>:
+08001bb0 <HAL_ADC_MspInit>:
 
 void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
 {
- 8001a1c:	b580      	push	{r7, lr}
- 8001a1e:	b08a      	sub	sp, #40	@ 0x28
- 8001a20:	af00      	add	r7, sp, #0
- 8001a22:	6078      	str	r0, [r7, #4]
+ 8001bb0:	b580      	push	{r7, lr}
+ 8001bb2:	b08a      	sub	sp, #40	@ 0x28
+ 8001bb4:	af00      	add	r7, sp, #0
+ 8001bb6:	6078      	str	r0, [r7, #4]
 
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001a24:	f107 0318 	add.w	r3, r7, #24
- 8001a28:	2200      	movs	r2, #0
- 8001a2a:	601a      	str	r2, [r3, #0]
- 8001a2c:	605a      	str	r2, [r3, #4]
- 8001a2e:	609a      	str	r2, [r3, #8]
- 8001a30:	60da      	str	r2, [r3, #12]
+ 8001bb8:	f107 0318 	add.w	r3, r7, #24
+ 8001bbc:	2200      	movs	r2, #0
+ 8001bbe:	601a      	str	r2, [r3, #0]
+ 8001bc0:	605a      	str	r2, [r3, #4]
+ 8001bc2:	609a      	str	r2, [r3, #8]
+ 8001bc4:	60da      	str	r2, [r3, #12]
   if(adcHandle->Instance==ADC1)
- 8001a32:	687b      	ldr	r3, [r7, #4]
- 8001a34:	681b      	ldr	r3, [r3, #0]
- 8001a36:	4a28      	ldr	r2, [pc, #160]	@ (8001ad8 <HAL_ADC_MspInit+0xbc>)
- 8001a38:	4293      	cmp	r3, r2
- 8001a3a:	d122      	bne.n	8001a82 <HAL_ADC_MspInit+0x66>
+ 8001bc6:	687b      	ldr	r3, [r7, #4]
+ 8001bc8:	681b      	ldr	r3, [r3, #0]
+ 8001bca:	4a3c      	ldr	r2, [pc, #240]	@ (8001cbc <HAL_ADC_MspInit+0x10c>)
+ 8001bcc:	4293      	cmp	r3, r2
+ 8001bce:	d14a      	bne.n	8001c66 <HAL_ADC_MspInit+0xb6>
   {
   /* USER CODE BEGIN ADC1_MspInit 0 */
 
   /* USER CODE END ADC1_MspInit 0 */
     /* ADC1 clock enable */
     __HAL_RCC_ADC1_CLK_ENABLE();
- 8001a3c:	4b27      	ldr	r3, [pc, #156]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a3e:	699b      	ldr	r3, [r3, #24]
- 8001a40:	4a26      	ldr	r2, [pc, #152]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a42:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
- 8001a46:	6193      	str	r3, [r2, #24]
- 8001a48:	4b24      	ldr	r3, [pc, #144]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a4a:	699b      	ldr	r3, [r3, #24]
- 8001a4c:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 8001a50:	617b      	str	r3, [r7, #20]
- 8001a52:	697b      	ldr	r3, [r7, #20]
+ 8001bd0:	4b3b      	ldr	r3, [pc, #236]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bd2:	699b      	ldr	r3, [r3, #24]
+ 8001bd4:	4a3a      	ldr	r2, [pc, #232]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bd6:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
+ 8001bda:	6193      	str	r3, [r2, #24]
+ 8001bdc:	4b38      	ldr	r3, [pc, #224]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bde:	699b      	ldr	r3, [r3, #24]
+ 8001be0:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8001be4:	617b      	str	r3, [r7, #20]
+ 8001be6:	697b      	ldr	r3, [r7, #20]
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001a54:	4b21      	ldr	r3, [pc, #132]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a56:	699b      	ldr	r3, [r3, #24]
- 8001a58:	4a20      	ldr	r2, [pc, #128]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a5a:	f043 0304 	orr.w	r3, r3, #4
- 8001a5e:	6193      	str	r3, [r2, #24]
- 8001a60:	4b1e      	ldr	r3, [pc, #120]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a62:	699b      	ldr	r3, [r3, #24]
- 8001a64:	f003 0304 	and.w	r3, r3, #4
- 8001a68:	613b      	str	r3, [r7, #16]
- 8001a6a:	693b      	ldr	r3, [r7, #16]
+ 8001be8:	4b35      	ldr	r3, [pc, #212]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bea:	699b      	ldr	r3, [r3, #24]
+ 8001bec:	4a34      	ldr	r2, [pc, #208]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bee:	f043 0304 	orr.w	r3, r3, #4
+ 8001bf2:	6193      	str	r3, [r2, #24]
+ 8001bf4:	4b32      	ldr	r3, [pc, #200]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001bf6:	699b      	ldr	r3, [r3, #24]
+ 8001bf8:	f003 0304 	and.w	r3, r3, #4
+ 8001bfc:	613b      	str	r3, [r7, #16]
+ 8001bfe:	693b      	ldr	r3, [r7, #16]
     /**ADC1 GPIO Configuration
     PA0-WKUP     ------> ADC1_IN0
     PA1     ------> ADC1_IN1
     */
     GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
- 8001a6c:	2303      	movs	r3, #3
- 8001a6e:	61bb      	str	r3, [r7, #24]
+ 8001c00:	2303      	movs	r3, #3
+ 8001c02:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 8001a70:	2303      	movs	r3, #3
- 8001a72:	61fb      	str	r3, [r7, #28]
+ 8001c04:	2303      	movs	r3, #3
+ 8001c06:	61fb      	str	r3, [r7, #28]
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8001a74:	f107 0318 	add.w	r3, r7, #24
- 8001a78:	4619      	mov	r1, r3
- 8001a7a:	4819      	ldr	r0, [pc, #100]	@ (8001ae0 <HAL_ADC_MspInit+0xc4>)
- 8001a7c:	f001 fc64 	bl	8003348 <HAL_GPIO_Init>
+ 8001c08:	f107 0318 	add.w	r3, r7, #24
+ 8001c0c:	4619      	mov	r1, r3
+ 8001c0e:	482d      	ldr	r0, [pc, #180]	@ (8001cc4 <HAL_ADC_MspInit+0x114>)
+ 8001c10:	f002 fdae 	bl	8004770 <HAL_GPIO_Init>
+
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance = DMA1_Channel1;
+ 8001c14:	4b2c      	ldr	r3, [pc, #176]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c16:	4a2d      	ldr	r2, [pc, #180]	@ (8001ccc <HAL_ADC_MspInit+0x11c>)
+ 8001c18:	601a      	str	r2, [r3, #0]
+    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ 8001c1a:	4b2b      	ldr	r3, [pc, #172]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c1c:	2200      	movs	r2, #0
+ 8001c1e:	605a      	str	r2, [r3, #4]
+    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8001c20:	4b29      	ldr	r3, [pc, #164]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c22:	2200      	movs	r2, #0
+ 8001c24:	609a      	str	r2, [r3, #8]
+    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+ 8001c26:	4b28      	ldr	r3, [pc, #160]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c28:	2280      	movs	r2, #128	@ 0x80
+ 8001c2a:	60da      	str	r2, [r3, #12]
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+ 8001c2c:	4b26      	ldr	r3, [pc, #152]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c2e:	f44f 7280 	mov.w	r2, #256	@ 0x100
+ 8001c32:	611a      	str	r2, [r3, #16]
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+ 8001c34:	4b24      	ldr	r3, [pc, #144]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c36:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8001c3a:	615a      	str	r2, [r3, #20]
+    hdma_adc1.Init.Mode = DMA_CIRCULAR;
+ 8001c3c:	4b22      	ldr	r3, [pc, #136]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c3e:	2220      	movs	r2, #32
+ 8001c40:	619a      	str	r2, [r3, #24]
+    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
+ 8001c42:	4b21      	ldr	r3, [pc, #132]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c44:	2200      	movs	r2, #0
+ 8001c46:	61da      	str	r2, [r3, #28]
+    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+ 8001c48:	481f      	ldr	r0, [pc, #124]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c4a:	f002 f8ef 	bl	8003e2c <HAL_DMA_Init>
+ 8001c4e:	4603      	mov	r3, r0
+ 8001c50:	2b00      	cmp	r3, #0
+ 8001c52:	d001      	beq.n	8001c58 <HAL_ADC_MspInit+0xa8>
+    {
+      Error_Handler();
+ 8001c54:	f001 f85c 	bl	8002d10 <Error_Handler>
+    }
+
+    __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1);
+ 8001c58:	687b      	ldr	r3, [r7, #4]
+ 8001c5a:	4a1b      	ldr	r2, [pc, #108]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c5c:	621a      	str	r2, [r3, #32]
+ 8001c5e:	4a1a      	ldr	r2, [pc, #104]	@ (8001cc8 <HAL_ADC_MspInit+0x118>)
+ 8001c60:	687b      	ldr	r3, [r7, #4]
+ 8001c62:	6253      	str	r3, [r2, #36]	@ 0x24
 
   /* USER CODE BEGIN ADC2_MspInit 1 */
 
   /* USER CODE END ADC2_MspInit 1 */
   }
 }
- 8001a80:	e026      	b.n	8001ad0 <HAL_ADC_MspInit+0xb4>
+ 8001c64:	e026      	b.n	8001cb4 <HAL_ADC_MspInit+0x104>
   else if(adcHandle->Instance==ADC2)
- 8001a82:	687b      	ldr	r3, [r7, #4]
- 8001a84:	681b      	ldr	r3, [r3, #0]
- 8001a86:	4a17      	ldr	r2, [pc, #92]	@ (8001ae4 <HAL_ADC_MspInit+0xc8>)
- 8001a88:	4293      	cmp	r3, r2
- 8001a8a:	d121      	bne.n	8001ad0 <HAL_ADC_MspInit+0xb4>
+ 8001c66:	687b      	ldr	r3, [r7, #4]
+ 8001c68:	681b      	ldr	r3, [r3, #0]
+ 8001c6a:	4a19      	ldr	r2, [pc, #100]	@ (8001cd0 <HAL_ADC_MspInit+0x120>)
+ 8001c6c:	4293      	cmp	r3, r2
+ 8001c6e:	d121      	bne.n	8001cb4 <HAL_ADC_MspInit+0x104>
     __HAL_RCC_ADC2_CLK_ENABLE();
- 8001a8c:	4b13      	ldr	r3, [pc, #76]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a8e:	699b      	ldr	r3, [r3, #24]
- 8001a90:	4a12      	ldr	r2, [pc, #72]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a92:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
- 8001a96:	6193      	str	r3, [r2, #24]
- 8001a98:	4b10      	ldr	r3, [pc, #64]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001a9a:	699b      	ldr	r3, [r3, #24]
- 8001a9c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
- 8001aa0:	60fb      	str	r3, [r7, #12]
- 8001aa2:	68fb      	ldr	r3, [r7, #12]
+ 8001c70:	4b13      	ldr	r3, [pc, #76]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c72:	699b      	ldr	r3, [r3, #24]
+ 8001c74:	4a12      	ldr	r2, [pc, #72]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c76:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
+ 8001c7a:	6193      	str	r3, [r2, #24]
+ 8001c7c:	4b10      	ldr	r3, [pc, #64]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c7e:	699b      	ldr	r3, [r3, #24]
+ 8001c80:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8001c84:	60fb      	str	r3, [r7, #12]
+ 8001c86:	68fb      	ldr	r3, [r7, #12]
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001aa4:	4b0d      	ldr	r3, [pc, #52]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001aa6:	699b      	ldr	r3, [r3, #24]
- 8001aa8:	4a0c      	ldr	r2, [pc, #48]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001aaa:	f043 0304 	orr.w	r3, r3, #4
- 8001aae:	6193      	str	r3, [r2, #24]
- 8001ab0:	4b0a      	ldr	r3, [pc, #40]	@ (8001adc <HAL_ADC_MspInit+0xc0>)
- 8001ab2:	699b      	ldr	r3, [r3, #24]
- 8001ab4:	f003 0304 	and.w	r3, r3, #4
- 8001ab8:	60bb      	str	r3, [r7, #8]
- 8001aba:	68bb      	ldr	r3, [r7, #8]
-    GPIO_InitStruct.Pin = AIN2_Pin;
- 8001abc:	2302      	movs	r3, #2
- 8001abe:	61bb      	str	r3, [r7, #24]
+ 8001c88:	4b0d      	ldr	r3, [pc, #52]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c8a:	699b      	ldr	r3, [r3, #24]
+ 8001c8c:	4a0c      	ldr	r2, [pc, #48]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c8e:	f043 0304 	orr.w	r3, r3, #4
+ 8001c92:	6193      	str	r3, [r2, #24]
+ 8001c94:	4b0a      	ldr	r3, [pc, #40]	@ (8001cc0 <HAL_ADC_MspInit+0x110>)
+ 8001c96:	699b      	ldr	r3, [r3, #24]
+ 8001c98:	f003 0304 	and.w	r3, r3, #4
+ 8001c9c:	60bb      	str	r3, [r7, #8]
+ 8001c9e:	68bb      	ldr	r3, [r7, #8]
+    GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin;
+ 8001ca0:	2303      	movs	r3, #3
+ 8001ca2:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 8001ac0:	2303      	movs	r3, #3
- 8001ac2:	61fb      	str	r3, [r7, #28]
-    HAL_GPIO_Init(AIN2_GPIO_Port, &GPIO_InitStruct);
- 8001ac4:	f107 0318 	add.w	r3, r7, #24
- 8001ac8:	4619      	mov	r1, r3
- 8001aca:	4805      	ldr	r0, [pc, #20]	@ (8001ae0 <HAL_ADC_MspInit+0xc4>)
- 8001acc:	f001 fc3c 	bl	8003348 <HAL_GPIO_Init>
+ 8001ca4:	2303      	movs	r3, #3
+ 8001ca6:	61fb      	str	r3, [r7, #28]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8001ca8:	f107 0318 	add.w	r3, r7, #24
+ 8001cac:	4619      	mov	r1, r3
+ 8001cae:	4805      	ldr	r0, [pc, #20]	@ (8001cc4 <HAL_ADC_MspInit+0x114>)
+ 8001cb0:	f002 fd5e 	bl	8004770 <HAL_GPIO_Init>
 }
- 8001ad0:	bf00      	nop
- 8001ad2:	3728      	adds	r7, #40	@ 0x28
- 8001ad4:	46bd      	mov	sp, r7
- 8001ad6:	bd80      	pop	{r7, pc}
- 8001ad8:	40012400 	.word	0x40012400
- 8001adc:	40021000 	.word	0x40021000
- 8001ae0:	40010800 	.word	0x40010800
- 8001ae4:	40012800 	.word	0x40012800
+ 8001cb4:	bf00      	nop
+ 8001cb6:	3728      	adds	r7, #40	@ 0x28
+ 8001cb8:	46bd      	mov	sp, r7
+ 8001cba:	bd80      	pop	{r7, pc}
+ 8001cbc:	40012400 	.word	0x40012400
+ 8001cc0:	40021000 	.word	0x40021000
+ 8001cc4:	40010800 	.word	0x40010800
+ 8001cc8:	2000017c 	.word	0x2000017c
+ 8001ccc:	40020008 	.word	0x40020008
+ 8001cd0:	40012800 	.word	0x40012800
 
-08001ae8 <writeRegister>:
-#include "main.h" // Assuming HAL is included via main.h
+08001cd4 <writeRegister>:
 
-float temp_calib, ph_compensated, v_ph4=0, v_ph7=0;
+ADS1015_I2C i2c;
+float ph_dut_samples[ADS1015_PH_AVERAGES]={0};
 
 // Write the register
 static void writeRegister(ADS1015_I2C *i2c, uint8_t reg, uint16_t value) {
- 8001ae8:	b580      	push	{r7, lr}
- 8001aea:	b086      	sub	sp, #24
- 8001aec:	af02      	add	r7, sp, #8
- 8001aee:	6078      	str	r0, [r7, #4]
- 8001af0:	460b      	mov	r3, r1
- 8001af2:	70fb      	strb	r3, [r7, #3]
- 8001af4:	4613      	mov	r3, r2
- 8001af6:	803b      	strh	r3, [r7, #0]
+ 8001cd4:	b580      	push	{r7, lr}
+ 8001cd6:	b086      	sub	sp, #24
+ 8001cd8:	af02      	add	r7, sp, #8
+ 8001cda:	6078      	str	r0, [r7, #4]
+ 8001cdc:	460b      	mov	r3, r1
+ 8001cde:	70fb      	strb	r3, [r7, #3]
+ 8001ce0:	4613      	mov	r3, r2
+ 8001ce2:	803b      	strh	r3, [r7, #0]
 	uint8_t pData[3] = { reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF) };
- 8001af8:	78fb      	ldrb	r3, [r7, #3]
- 8001afa:	733b      	strb	r3, [r7, #12]
- 8001afc:	883b      	ldrh	r3, [r7, #0]
- 8001afe:	0a1b      	lsrs	r3, r3, #8
- 8001b00:	b29b      	uxth	r3, r3
- 8001b02:	b2db      	uxtb	r3, r3
- 8001b04:	737b      	strb	r3, [r7, #13]
- 8001b06:	883b      	ldrh	r3, [r7, #0]
- 8001b08:	b2db      	uxtb	r3, r3
- 8001b0a:	73bb      	strb	r3, [r7, #14]
+ 8001ce4:	78fb      	ldrb	r3, [r7, #3]
+ 8001ce6:	733b      	strb	r3, [r7, #12]
+ 8001ce8:	883b      	ldrh	r3, [r7, #0]
+ 8001cea:	0a1b      	lsrs	r3, r3, #8
+ 8001cec:	b29b      	uxth	r3, r3
+ 8001cee:	b2db      	uxtb	r3, r3
+ 8001cf0:	737b      	strb	r3, [r7, #13]
+ 8001cf2:	883b      	ldrh	r3, [r7, #0]
+ 8001cf4:	b2db      	uxtb	r3, r3
+ 8001cf6:	73bb      	strb	r3, [r7, #14]
 	HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, pData, 3, 10);
- 8001b0c:	687b      	ldr	r3, [r7, #4]
- 8001b0e:	68d8      	ldr	r0, [r3, #12]
- 8001b10:	687b      	ldr	r3, [r7, #4]
- 8001b12:	8819      	ldrh	r1, [r3, #0]
- 8001b14:	f107 020c 	add.w	r2, r7, #12
- 8001b18:	230a      	movs	r3, #10
- 8001b1a:	9300      	str	r3, [sp, #0]
- 8001b1c:	2303      	movs	r3, #3
- 8001b1e:	f001 ff23 	bl	8003968 <HAL_I2C_Master_Transmit>
+ 8001cf8:	687b      	ldr	r3, [r7, #4]
+ 8001cfa:	68d8      	ldr	r0, [r3, #12]
+ 8001cfc:	687b      	ldr	r3, [r7, #4]
+ 8001cfe:	8819      	ldrh	r1, [r3, #0]
+ 8001d00:	f107 020c 	add.w	r2, r7, #12
+ 8001d04:	230a      	movs	r3, #10
+ 8001d06:	9300      	str	r3, [sp, #0]
+ 8001d08:	2303      	movs	r3, #3
+ 8001d0a:	f003 f841 	bl	8004d90 <HAL_I2C_Master_Transmit>
 }
- 8001b22:	bf00      	nop
- 8001b24:	3710      	adds	r7, #16
- 8001b26:	46bd      	mov	sp, r7
- 8001b28:	bd80      	pop	{r7, pc}
+ 8001d0e:	bf00      	nop
+ 8001d10:	3710      	adds	r7, #16
+ 8001d12:	46bd      	mov	sp, r7
+ 8001d14:	bd80      	pop	{r7, pc}
 
-08001b2a <readRegister>:
+08001d16 <readRegister>:
 
 // Read the register
 static uint16_t readRegister(ADS1015_I2C *i2c, uint8_t reg) {
- 8001b2a:	b580      	push	{r7, lr}
- 8001b2c:	b086      	sub	sp, #24
- 8001b2e:	af02      	add	r7, sp, #8
- 8001b30:	6078      	str	r0, [r7, #4]
- 8001b32:	460b      	mov	r3, r1
- 8001b34:	70fb      	strb	r3, [r7, #3]
+ 8001d16:	b580      	push	{r7, lr}
+ 8001d18:	b086      	sub	sp, #24
+ 8001d1a:	af02      	add	r7, sp, #8
+ 8001d1c:	6078      	str	r0, [r7, #4]
+ 8001d1e:	460b      	mov	r3, r1
+ 8001d20:	70fb      	strb	r3, [r7, #3]
 	HAL_I2C_Master_Transmit(i2c->hi2c, i2c->m_i2cAddress, &reg, 1, 10);
- 8001b36:	687b      	ldr	r3, [r7, #4]
- 8001b38:	68d8      	ldr	r0, [r3, #12]
- 8001b3a:	687b      	ldr	r3, [r7, #4]
- 8001b3c:	8819      	ldrh	r1, [r3, #0]
- 8001b3e:	1cfa      	adds	r2, r7, #3
- 8001b40:	230a      	movs	r3, #10
- 8001b42:	9300      	str	r3, [sp, #0]
- 8001b44:	2301      	movs	r3, #1
- 8001b46:	f001 ff0f 	bl	8003968 <HAL_I2C_Master_Transmit>
+ 8001d22:	687b      	ldr	r3, [r7, #4]
+ 8001d24:	68d8      	ldr	r0, [r3, #12]
+ 8001d26:	687b      	ldr	r3, [r7, #4]
+ 8001d28:	8819      	ldrh	r1, [r3, #0]
+ 8001d2a:	1cfa      	adds	r2, r7, #3
+ 8001d2c:	230a      	movs	r3, #10
+ 8001d2e:	9300      	str	r3, [sp, #0]
+ 8001d30:	2301      	movs	r3, #1
+ 8001d32:	f003 f82d 	bl	8004d90 <HAL_I2C_Master_Transmit>
 	uint8_t pData[2] = { 0, 0 };
- 8001b4a:	2300      	movs	r3, #0
- 8001b4c:	81bb      	strh	r3, [r7, #12]
+ 8001d36:	2300      	movs	r3, #0
+ 8001d38:	81bb      	strh	r3, [r7, #12]
 	HAL_I2C_Master_Receive(i2c->hi2c, i2c->m_i2cAddress, pData, 2, 10);
- 8001b4e:	687b      	ldr	r3, [r7, #4]
- 8001b50:	68d8      	ldr	r0, [r3, #12]
- 8001b52:	687b      	ldr	r3, [r7, #4]
- 8001b54:	8819      	ldrh	r1, [r3, #0]
- 8001b56:	f107 020c 	add.w	r2, r7, #12
- 8001b5a:	230a      	movs	r3, #10
- 8001b5c:	9300      	str	r3, [sp, #0]
- 8001b5e:	2302      	movs	r3, #2
- 8001b60:	f002 f800 	bl	8003b64 <HAL_I2C_Master_Receive>
+ 8001d3a:	687b      	ldr	r3, [r7, #4]
+ 8001d3c:	68d8      	ldr	r0, [r3, #12]
+ 8001d3e:	687b      	ldr	r3, [r7, #4]
+ 8001d40:	8819      	ldrh	r1, [r3, #0]
+ 8001d42:	f107 020c 	add.w	r2, r7, #12
+ 8001d46:	230a      	movs	r3, #10
+ 8001d48:	9300      	str	r3, [sp, #0]
+ 8001d4a:	2302      	movs	r3, #2
+ 8001d4c:	f003 f91e 	bl	8004f8c <HAL_I2C_Master_Receive>
 	return ((pData[0] << 8) | pData[1]);
- 8001b64:	7b3b      	ldrb	r3, [r7, #12]
- 8001b66:	b21b      	sxth	r3, r3
- 8001b68:	021b      	lsls	r3, r3, #8
- 8001b6a:	b21a      	sxth	r2, r3
- 8001b6c:	7b7b      	ldrb	r3, [r7, #13]
- 8001b6e:	b21b      	sxth	r3, r3
- 8001b70:	4313      	orrs	r3, r2
- 8001b72:	b21b      	sxth	r3, r3
- 8001b74:	b29b      	uxth	r3, r3
+ 8001d50:	7b3b      	ldrb	r3, [r7, #12]
+ 8001d52:	b21b      	sxth	r3, r3
+ 8001d54:	021b      	lsls	r3, r3, #8
+ 8001d56:	b21a      	sxth	r2, r3
+ 8001d58:	7b7b      	ldrb	r3, [r7, #13]
+ 8001d5a:	b21b      	sxth	r3, r3
+ 8001d5c:	4313      	orrs	r3, r2
+ 8001d5e:	b21b      	sxth	r3, r3
+ 8001d60:	b29b      	uxth	r3, r3
 }
- 8001b76:	4618      	mov	r0, r3
- 8001b78:	3710      	adds	r7, #16
- 8001b7a:	46bd      	mov	sp, r7
- 8001b7c:	bd80      	pop	{r7, pc}
+ 8001d62:	4618      	mov	r0, r3
+ 8001d64:	3710      	adds	r7, #16
+ 8001d66:	46bd      	mov	sp, r7
+ 8001d68:	bd80      	pop	{r7, pc}
 
-08001b7e <ADS1015>:
+08001d6a <ADS1015>:
 		HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); // This MUST have GPIO PA5 ready to use - ERROR I2C - Wrong address
 
 }
 
 // Declare an ADS1015 structure
 void ADS1015(ADS1015_I2C *i2c, I2C_HandleTypeDef *hi2c, uint8_t i2cAddress) {
- 8001b7e:	b480      	push	{r7}
- 8001b80:	b085      	sub	sp, #20
- 8001b82:	af00      	add	r7, sp, #0
- 8001b84:	60f8      	str	r0, [r7, #12]
- 8001b86:	60b9      	str	r1, [r7, #8]
- 8001b88:	4613      	mov	r3, r2
- 8001b8a:	71fb      	strb	r3, [r7, #7]
+ 8001d6a:	b480      	push	{r7}
+ 8001d6c:	b085      	sub	sp, #20
+ 8001d6e:	af00      	add	r7, sp, #0
+ 8001d70:	60f8      	str	r0, [r7, #12]
+ 8001d72:	60b9      	str	r1, [r7, #8]
+ 8001d74:	4613      	mov	r3, r2
+ 8001d76:	71fb      	strb	r3, [r7, #7]
 	i2c->hi2c = hi2c;
- 8001b8c:	68fb      	ldr	r3, [r7, #12]
- 8001b8e:	68ba      	ldr	r2, [r7, #8]
- 8001b90:	60da      	str	r2, [r3, #12]
+ 8001d78:	68fb      	ldr	r3, [r7, #12]
+ 8001d7a:	68ba      	ldr	r2, [r7, #8]
+ 8001d7c:	60da      	str	r2, [r3, #12]
 	i2c->m_i2cAddress = i2cAddress << 1; //  It's Important to shift the address << 1
- 8001b92:	79fb      	ldrb	r3, [r7, #7]
- 8001b94:	b29b      	uxth	r3, r3
- 8001b96:	005b      	lsls	r3, r3, #1
- 8001b98:	b29a      	uxth	r2, r3
- 8001b9a:	68fb      	ldr	r3, [r7, #12]
- 8001b9c:	801a      	strh	r2, [r3, #0]
+ 8001d7e:	79fb      	ldrb	r3, [r7, #7]
+ 8001d80:	b29b      	uxth	r3, r3
+ 8001d82:	005b      	lsls	r3, r3, #1
+ 8001d84:	b29a      	uxth	r2, r3
+ 8001d86:	68fb      	ldr	r3, [r7, #12]
+ 8001d88:	801a      	strh	r2, [r3, #0]
 	i2c->m_conversionDelay = ADS1015_CONVERSIONDELAY;
- 8001b9e:	68fb      	ldr	r3, [r7, #12]
- 8001ba0:	2204      	movs	r2, #4
- 8001ba2:	605a      	str	r2, [r3, #4]
+ 8001d8a:	68fb      	ldr	r3, [r7, #12]
+ 8001d8c:	2204      	movs	r2, #4
+ 8001d8e:	605a      	str	r2, [r3, #4]
 	i2c->m_bitShift = 4;
- 8001ba4:	68fb      	ldr	r3, [r7, #12]
- 8001ba6:	2204      	movs	r2, #4
- 8001ba8:	721a      	strb	r2, [r3, #8]
+ 8001d90:	68fb      	ldr	r3, [r7, #12]
+ 8001d92:	2204      	movs	r2, #4
+ 8001d94:	721a      	strb	r2, [r3, #8]
 	i2c->m_gain = GAIN_TWOTHIRDS; /* +/- 6.144V range (limited to VDD +0.3V max!) */
- 8001baa:	68fb      	ldr	r3, [r7, #12]
- 8001bac:	2200      	movs	r2, #0
- 8001bae:	815a      	strh	r2, [r3, #10]
+ 8001d96:	68fb      	ldr	r3, [r7, #12]
+ 8001d98:	2200      	movs	r2, #0
+ 8001d9a:	815a      	strh	r2, [r3, #10]
 	//ADSbegin(i2c); //Ready is not used
 }
- 8001bb0:	bf00      	nop
- 8001bb2:	3714      	adds	r7, #20
- 8001bb4:	46bd      	mov	sp, r7
- 8001bb6:	bc80      	pop	{r7}
- 8001bb8:	4770      	bx	lr
+ 8001d9c:	bf00      	nop
+ 8001d9e:	3714      	adds	r7, #20
+ 8001da0:	46bd      	mov	sp, r7
+ 8001da2:	bc80      	pop	{r7}
+ 8001da4:	4770      	bx	lr
 
-08001bba <ADSsetGain>:
+08001da6 <ADSsetGain>:
  // ADSsetGain(GAIN_TWO);        // 2x gain   +/- 2.048V  1 bit = 1mV      0.0625mV
  // ADSsetGain(GAIN_FOUR);       // 4x gain   +/- 1.024V  1 bit = 0.5mV    0.03125mV
  // ADSsetGain(GAIN_EIGHT);      // 8x gain   +/- 0.512V  1 bit = 0.25mV   0.015625mV
  // ADSsetGain(GAIN_SIXTEEN);    // 16x gain  +/- 0.256V  1 bit = 0.125mV  0.0078125mV
  */
 void ADSsetGain(ADS1015_I2C *i2c, adsGain_t gain) {
- 8001bba:	b480      	push	{r7}
- 8001bbc:	b083      	sub	sp, #12
- 8001bbe:	af00      	add	r7, sp, #0
- 8001bc0:	6078      	str	r0, [r7, #4]
- 8001bc2:	460b      	mov	r3, r1
- 8001bc4:	807b      	strh	r3, [r7, #2]
+ 8001da6:	b480      	push	{r7}
+ 8001da8:	b083      	sub	sp, #12
+ 8001daa:	af00      	add	r7, sp, #0
+ 8001dac:	6078      	str	r0, [r7, #4]
+ 8001dae:	460b      	mov	r3, r1
+ 8001db0:	807b      	strh	r3, [r7, #2]
 	i2c->m_gain = gain;
- 8001bc6:	687b      	ldr	r3, [r7, #4]
- 8001bc8:	887a      	ldrh	r2, [r7, #2]
- 8001bca:	815a      	strh	r2, [r3, #10]
+ 8001db2:	687b      	ldr	r3, [r7, #4]
+ 8001db4:	887a      	ldrh	r2, [r7, #2]
+ 8001db6:	815a      	strh	r2, [r3, #10]
 }
- 8001bcc:	bf00      	nop
- 8001bce:	370c      	adds	r7, #12
- 8001bd0:	46bd      	mov	sp, r7
- 8001bd2:	bc80      	pop	{r7}
- 8001bd4:	4770      	bx	lr
+ 8001db8:	bf00      	nop
+ 8001dba:	370c      	adds	r7, #12
+ 8001dbc:	46bd      	mov	sp, r7
+ 8001dbe:	bc80      	pop	{r7}
+ 8001dc0:	4770      	bx	lr
 
-08001bd6 <ADSreadADC_Differential_0_1>:
+08001dc2 <ADSreadADC_Differential_0_1>:
 /*
  * Reads the conversion results, measuring the voltage
  * difference between the P (AIN0) and N (AIN1) input.  Generates
  * a signed value since the difference can be either positive or negative.
  */
 int16_t ADSreadADC_Differential_0_1(ADS1015_I2C *i2c) {
- 8001bd6:	b580      	push	{r7, lr}
- 8001bd8:	b084      	sub	sp, #16
- 8001bda:	af00      	add	r7, sp, #0
- 8001bdc:	6078      	str	r0, [r7, #4]
+ 8001dc2:	b580      	push	{r7, lr}
+ 8001dc4:	b084      	sub	sp, #16
+ 8001dc6:	af00      	add	r7, sp, #0
+ 8001dc8:	6078      	str	r0, [r7, #4]
 	// Start with default values
 	uint16_t config =
- 8001bde:	f240 1303 	movw	r3, #259	@ 0x103
- 8001be2:	81bb      	strh	r3, [r7, #12]
+ 8001dca:	f240 1303 	movw	r3, #259	@ 0x103
+ 8001dce:	81bb      	strh	r3, [r7, #12]
 	ADS1015_REG_CONFIG_CMODE_TRAD 	| 	// Traditional comparator (default val)
 	ADS1015_REG_CONFIG_DR_128SPS 	| 	// 128 samples per second (default)
 	ADS1015_REG_CONFIG_MODE_SINGLE;   	// Single-shot mode (default)
 
 	// Set PGA/voltage range
 	config |= i2c->m_gain;
- 8001be4:	687b      	ldr	r3, [r7, #4]
- 8001be6:	895a      	ldrh	r2, [r3, #10]
- 8001be8:	89bb      	ldrh	r3, [r7, #12]
- 8001bea:	4313      	orrs	r3, r2
- 8001bec:	81bb      	strh	r3, [r7, #12]
+ 8001dd0:	687b      	ldr	r3, [r7, #4]
+ 8001dd2:	895a      	ldrh	r2, [r3, #10]
+ 8001dd4:	89bb      	ldrh	r3, [r7, #12]
+ 8001dd6:	4313      	orrs	r3, r2
+ 8001dd8:	81bb      	strh	r3, [r7, #12]
 
 	// Set channels
 	config |= ADS1015_REG_CONFIG_MUX_DIFF_0_1; // AIN0 = P, AIN1 = N
 
 	// Set 'start single-conversion' bit
 	config |= ADS1015_REG_CONFIG_OS_SINGLE;
- 8001bee:	89bb      	ldrh	r3, [r7, #12]
- 8001bf0:	ea6f 4343 	mvn.w	r3, r3, lsl #17
- 8001bf4:	ea6f 4353 	mvn.w	r3, r3, lsr #17
- 8001bf8:	81bb      	strh	r3, [r7, #12]
+ 8001dda:	89bb      	ldrh	r3, [r7, #12]
+ 8001ddc:	ea6f 4343 	mvn.w	r3, r3, lsl #17
+ 8001de0:	ea6f 4353 	mvn.w	r3, r3, lsr #17
+ 8001de4:	81bb      	strh	r3, [r7, #12]
 
 	// Write config register to the ADC
 	writeRegister(i2c, ADS1015_REG_POINTER_CONFIG, config);
- 8001bfa:	89bb      	ldrh	r3, [r7, #12]
- 8001bfc:	461a      	mov	r2, r3
- 8001bfe:	2101      	movs	r1, #1
- 8001c00:	6878      	ldr	r0, [r7, #4]
- 8001c02:	f7ff ff71 	bl	8001ae8 <writeRegister>
+ 8001de6:	89bb      	ldrh	r3, [r7, #12]
+ 8001de8:	461a      	mov	r2, r3
+ 8001dea:	2101      	movs	r1, #1
+ 8001dec:	6878      	ldr	r0, [r7, #4]
+ 8001dee:	f7ff ff71 	bl	8001cd4 <writeRegister>
 
 	// Wait for the conversion to complete
 	HAL_Delay(i2c->m_conversionDelay);
- 8001c06:	687b      	ldr	r3, [r7, #4]
- 8001c08:	685b      	ldr	r3, [r3, #4]
- 8001c0a:	4618      	mov	r0, r3
- 8001c0c:	f000 ffa6 	bl	8002b5c <HAL_Delay>
+ 8001df2:	687b      	ldr	r3, [r7, #4]
+ 8001df4:	685b      	ldr	r3, [r3, #4]
+ 8001df6:	4618      	mov	r0, r3
+ 8001df8:	f001 fa76 	bl	80032e8 <HAL_Delay>
 
 	// Read the conversion results
 	uint16_t res = readRegister(i2c, ADS1015_REG_POINTER_CONVERT) >> i2c->m_bitShift;
- 8001c10:	2100      	movs	r1, #0
- 8001c12:	6878      	ldr	r0, [r7, #4]
- 8001c14:	f7ff ff89 	bl	8001b2a <readRegister>
- 8001c18:	4603      	mov	r3, r0
- 8001c1a:	461a      	mov	r2, r3
- 8001c1c:	687b      	ldr	r3, [r7, #4]
- 8001c1e:	7a1b      	ldrb	r3, [r3, #8]
- 8001c20:	fa42 f303 	asr.w	r3, r2, r3
- 8001c24:	81fb      	strh	r3, [r7, #14]
+ 8001dfc:	2100      	movs	r1, #0
+ 8001dfe:	6878      	ldr	r0, [r7, #4]
+ 8001e00:	f7ff ff89 	bl	8001d16 <readRegister>
+ 8001e04:	4603      	mov	r3, r0
+ 8001e06:	461a      	mov	r2, r3
+ 8001e08:	687b      	ldr	r3, [r7, #4]
+ 8001e0a:	7a1b      	ldrb	r3, [r3, #8]
+ 8001e0c:	fa42 f303 	asr.w	r3, r2, r3
+ 8001e10:	81fb      	strh	r3, [r7, #14]
 	if (i2c->m_bitShift == 0) {
- 8001c26:	687b      	ldr	r3, [r7, #4]
- 8001c28:	7a1b      	ldrb	r3, [r3, #8]
- 8001c2a:	2b00      	cmp	r3, #0
- 8001c2c:	d102      	bne.n	8001c34 <ADSreadADC_Differential_0_1+0x5e>
+ 8001e12:	687b      	ldr	r3, [r7, #4]
+ 8001e14:	7a1b      	ldrb	r3, [r3, #8]
+ 8001e16:	2b00      	cmp	r3, #0
+ 8001e18:	d102      	bne.n	8001e20 <ADSreadADC_Differential_0_1+0x5e>
 		return (int16_t) res;
- 8001c2e:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
- 8001c32:	e00b      	b.n	8001c4c <ADSreadADC_Differential_0_1+0x76>
+ 8001e1a:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
+ 8001e1e:	e00b      	b.n	8001e38 <ADSreadADC_Differential_0_1+0x76>
 	} else {
 		// Shift 12-bit results right 4 bits for the ADS1015,
 		// making sure we keep the sign bit intact
 		if (res > 0x07FF) {
- 8001c34:	89fb      	ldrh	r3, [r7, #14]
- 8001c36:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
- 8001c3a:	d305      	bcc.n	8001c48 <ADSreadADC_Differential_0_1+0x72>
+ 8001e20:	89fb      	ldrh	r3, [r7, #14]
+ 8001e22:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
+ 8001e26:	d305      	bcc.n	8001e34 <ADSreadADC_Differential_0_1+0x72>
 			// negative number - extend the sign to 16th bit
 			res |= 0xF000;
- 8001c3c:	89fb      	ldrh	r3, [r7, #14]
- 8001c3e:	ea6f 5303 	mvn.w	r3, r3, lsl #20
- 8001c42:	ea6f 5313 	mvn.w	r3, r3, lsr #20
- 8001c46:	81fb      	strh	r3, [r7, #14]
+ 8001e28:	89fb      	ldrh	r3, [r7, #14]
+ 8001e2a:	ea6f 5303 	mvn.w	r3, r3, lsl #20
+ 8001e2e:	ea6f 5313 	mvn.w	r3, r3, lsr #20
+ 8001e32:	81fb      	strh	r3, [r7, #14]
 		}
 		return (int16_t) res;
- 8001c48:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
+ 8001e34:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
 	}
 }
- 8001c4c:	4618      	mov	r0, r3
- 8001c4e:	3710      	adds	r7, #16
- 8001c50:	46bd      	mov	sp, r7
- 8001c52:	bd80      	pop	{r7, pc}
+ 8001e38:	4618      	mov	r0, r3
+ 8001e3a:	3710      	adds	r7, #16
+ 8001e3c:	46bd      	mov	sp, r7
+ 8001e3e:	bd80      	pop	{r7, pc}
 
-08001c54 <ADSCalculate_ph_Volts>:
+08001e40 <ADSCalculate_ph_Volts>:
 		return (int16_t) res;
 	}
 }
 
-float ADSCalculate_ph_Volts(int16_t adc_raw)
+float ADSCalculate_ph_Volts(void)
 {
- 8001c54:	b580      	push	{r7, lr}
- 8001c56:	b082      	sub	sp, #8
- 8001c58:	af00      	add	r7, sp, #0
- 8001c5a:	4603      	mov	r3, r0
- 8001c5c:	80fb      	strh	r3, [r7, #6]
-    // 1. Converter leitura bruta do ADC para tensão real (Volts)
-    return ((float)adc_raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX;
- 8001c5e:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 8001c62:	4618      	mov	r0, r3
- 8001c64:	f7fe fe42 	bl	80008ec <__aeabi_i2f>
- 8001c68:	4603      	mov	r3, r0
- 8001c6a:	4907      	ldr	r1, [pc, #28]	@ (8001c88 <ADSCalculate_ph_Volts+0x34>)
- 8001c6c:	4618      	mov	r0, r3
- 8001c6e:	f7fe fe91 	bl	8000994 <__aeabi_fmul>
- 8001c72:	4603      	mov	r3, r0
- 8001c74:	4905      	ldr	r1, [pc, #20]	@ (8001c8c <ADSCalculate_ph_Volts+0x38>)
- 8001c76:	4618      	mov	r0, r3
- 8001c78:	f7fe ff40 	bl	8000afc <__aeabi_fdiv>
- 8001c7c:	4603      	mov	r3, r0
-}
- 8001c7e:	4618      	mov	r0, r3
- 8001c80:	3708      	adds	r7, #8
- 8001c82:	46bd      	mov	sp, r7
- 8001c84:	bd80      	pop	{r7, pc}
- 8001c86:	bf00      	nop
- 8001c88:	40533333 	.word	0x40533333
- 8001c8c:	457ff000 	.word	0x457ff000
+ 8001e40:	b580      	push	{r7, lr}
+ 8001e42:	b082      	sub	sp, #8
+ 8001e44:	af00      	add	r7, sp, #0
+	float ph_dut_sum;
+	uint8_t i;
 
-08001c90 <ADSCalculate_ph_Compensated>:
+	for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
+ 8001e46:	2307      	movs	r3, #7
+ 8001e48:	70fb      	strb	r3, [r7, #3]
+ 8001e4a:	e00b      	b.n	8001e64 <ADSCalculate_ph_Volts+0x24>
+		ph_dut_samples[i] = ph_dut_samples[i-1];
+ 8001e4c:	78fb      	ldrb	r3, [r7, #3]
+ 8001e4e:	1e5a      	subs	r2, r3, #1
+ 8001e50:	78fb      	ldrb	r3, [r7, #3]
+ 8001e52:	4922      	ldr	r1, [pc, #136]	@ (8001edc <ADSCalculate_ph_Volts+0x9c>)
+ 8001e54:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
+ 8001e58:	4920      	ldr	r1, [pc, #128]	@ (8001edc <ADSCalculate_ph_Volts+0x9c>)
+ 8001e5a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+	for (i = (ADS1015_PH_AVERAGES-1); i > 0; i--)
+ 8001e5e:	78fb      	ldrb	r3, [r7, #3]
+ 8001e60:	3b01      	subs	r3, #1
+ 8001e62:	70fb      	strb	r3, [r7, #3]
+ 8001e64:	78fb      	ldrb	r3, [r7, #3]
+ 8001e66:	2b00      	cmp	r3, #0
+ 8001e68:	d1f0      	bne.n	8001e4c <ADSCalculate_ph_Volts+0xc>
+
+	ph_dut_samples[0] = (((float)(2048 - ADSreadADC_Differential_0_1(&i2c)) * ADS1015_ADC_VREF) / ADS1015_ADC_MAX); 	// 1. Converter leitura bruta do ADC para tensão real (Volts)
+ 8001e6a:	481d      	ldr	r0, [pc, #116]	@ (8001ee0 <ADSCalculate_ph_Volts+0xa0>)
+ 8001e6c:	f7ff ffa9 	bl	8001dc2 <ADSreadADC_Differential_0_1>
+ 8001e70:	4603      	mov	r3, r0
+ 8001e72:	f5c3 6300 	rsb	r3, r3, #2048	@ 0x800
+ 8001e76:	4618      	mov	r0, r3
+ 8001e78:	f7fe fefa 	bl	8000c70 <__aeabi_i2f>
+ 8001e7c:	4603      	mov	r3, r0
+ 8001e7e:	4919      	ldr	r1, [pc, #100]	@ (8001ee4 <ADSCalculate_ph_Volts+0xa4>)
+ 8001e80:	4618      	mov	r0, r3
+ 8001e82:	f7fe ff49 	bl	8000d18 <__aeabi_fmul>
+ 8001e86:	4603      	mov	r3, r0
+ 8001e88:	4917      	ldr	r1, [pc, #92]	@ (8001ee8 <ADSCalculate_ph_Volts+0xa8>)
+ 8001e8a:	4618      	mov	r0, r3
+ 8001e8c:	f7fe fff8 	bl	8000e80 <__aeabi_fdiv>
+ 8001e90:	4603      	mov	r3, r0
+ 8001e92:	461a      	mov	r2, r3
+ 8001e94:	4b11      	ldr	r3, [pc, #68]	@ (8001edc <ADSCalculate_ph_Volts+0x9c>)
+ 8001e96:	601a      	str	r2, [r3, #0]
+
+	for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
+ 8001e98:	2300      	movs	r3, #0
+ 8001e9a:	70fb      	strb	r3, [r7, #3]
+ 8001e9c:	f04f 0300 	mov.w	r3, #0
+ 8001ea0:	607b      	str	r3, [r7, #4]
+ 8001ea2:	e00c      	b.n	8001ebe <ADSCalculate_ph_Volts+0x7e>
+		ph_dut_sum += ph_dut_samples[i];
+ 8001ea4:	78fb      	ldrb	r3, [r7, #3]
+ 8001ea6:	4a0d      	ldr	r2, [pc, #52]	@ (8001edc <ADSCalculate_ph_Volts+0x9c>)
+ 8001ea8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8001eac:	4619      	mov	r1, r3
+ 8001eae:	6878      	ldr	r0, [r7, #4]
+ 8001eb0:	f7fe fe2a 	bl	8000b08 <__addsf3>
+ 8001eb4:	4603      	mov	r3, r0
+ 8001eb6:	607b      	str	r3, [r7, #4]
+	for (i = 0, ph_dut_sum=0; i < ADS1015_PH_AVERAGES; i++)
+ 8001eb8:	78fb      	ldrb	r3, [r7, #3]
+ 8001eba:	3301      	adds	r3, #1
+ 8001ebc:	70fb      	strb	r3, [r7, #3]
+ 8001ebe:	78fb      	ldrb	r3, [r7, #3]
+ 8001ec0:	2b07      	cmp	r3, #7
+ 8001ec2:	d9ef      	bls.n	8001ea4 <ADSCalculate_ph_Volts+0x64>
+
+	ph_dut_sum /= ADS1015_PH_AVERAGES;
+ 8001ec4:	f04f 4182 	mov.w	r1, #1090519040	@ 0x41000000
+ 8001ec8:	6878      	ldr	r0, [r7, #4]
+ 8001eca:	f7fe ffd9 	bl	8000e80 <__aeabi_fdiv>
+ 8001ece:	4603      	mov	r3, r0
+ 8001ed0:	607b      	str	r3, [r7, #4]
+
+    return (ph_dut_sum);
+ 8001ed2:	687b      	ldr	r3, [r7, #4]
+}
+ 8001ed4:	4618      	mov	r0, r3
+ 8001ed6:	3708      	adds	r7, #8
+ 8001ed8:	46bd      	mov	sp, r7
+ 8001eda:	bd80      	pop	{r7, pc}
+ 8001edc:	200001d0 	.word	0x200001d0
+ 8001ee0:	200001c0 	.word	0x200001c0
+ 8001ee4:	40533333 	.word	0x40533333
+ 8001ee8:	457ff000 	.word	0x457ff000
+
+08001eec <ADSCalculate_ph_Compensated>:
  * @param temp_dut      Temperatura atual medida em Celsius.
  *
  * @return float        Valor de pH calculado (0.0 a 14.0).
  */
 float ADSCalculate_ph_Compensated(int16_t adc_raw, float temp_dut)
 {
- 8001c90:	b590      	push	{r4, r7, lr}
- 8001c92:	b08b      	sub	sp, #44	@ 0x2c
- 8001c94:	af00      	add	r7, sp, #0
- 8001c96:	4603      	mov	r3, r0
- 8001c98:	6039      	str	r1, [r7, #0]
- 8001c9a:	80fb      	strh	r3, [r7, #6]
+ 8001eec:	b590      	push	{r4, r7, lr}
+ 8001eee:	b08b      	sub	sp, #44	@ 0x2c
+ 8001ef0:	af00      	add	r7, sp, #0
+ 8001ef2:	4603      	mov	r3, r0
+ 8001ef4:	6039      	str	r1, [r7, #0]
+ 8001ef6:	80fb      	strh	r3, [r7, #6]
 
 
     // 1. Converter leitura bruta do ADC para tensão real (Volts)
     float v_measured = ((float)adc_raw * ADS1015_ADC_VREF) / ADS1015_ADC_MAX;
- 8001c9c:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
- 8001ca0:	4618      	mov	r0, r3
- 8001ca2:	f7fe fe23 	bl	80008ec <__aeabi_i2f>
- 8001ca6:	4603      	mov	r3, r0
- 8001ca8:	4935      	ldr	r1, [pc, #212]	@ (8001d80 <ADSCalculate_ph_Compensated+0xf0>)
- 8001caa:	4618      	mov	r0, r3
- 8001cac:	f7fe fe72 	bl	8000994 <__aeabi_fmul>
- 8001cb0:	4603      	mov	r3, r0
- 8001cb2:	4934      	ldr	r1, [pc, #208]	@ (8001d84 <ADSCalculate_ph_Compensated+0xf4>)
- 8001cb4:	4618      	mov	r0, r3
- 8001cb6:	f7fe ff21 	bl	8000afc <__aeabi_fdiv>
- 8001cba:	4603      	mov	r3, r0
- 8001cbc:	623b      	str	r3, [r7, #32]
+ 8001ef8:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 8001efc:	4618      	mov	r0, r3
+ 8001efe:	f7fe feb7 	bl	8000c70 <__aeabi_i2f>
+ 8001f02:	4603      	mov	r3, r0
+ 8001f04:	4935      	ldr	r1, [pc, #212]	@ (8001fdc <ADSCalculate_ph_Compensated+0xf0>)
+ 8001f06:	4618      	mov	r0, r3
+ 8001f08:	f7fe ff06 	bl	8000d18 <__aeabi_fmul>
+ 8001f0c:	4603      	mov	r3, r0
+ 8001f0e:	4934      	ldr	r1, [pc, #208]	@ (8001fe0 <ADSCalculate_ph_Compensated+0xf4>)
+ 8001f10:	4618      	mov	r0, r3
+ 8001f12:	f7fe ffb5 	bl	8000e80 <__aeabi_fdiv>
+ 8001f16:	4603      	mov	r3, r0
+ 8001f18:	623b      	str	r3, [r7, #32]
 
     // 2. Calcular o Slope original (medido na temperatura da calibração)
     // Delta pH é fixo em 3.0 (de pH 7 para pH 4)
-    float delta_v_calib = v_ph7 - v_ph4;
- 8001cbe:	4b32      	ldr	r3, [pc, #200]	@ (8001d88 <ADSCalculate_ph_Compensated+0xf8>)
- 8001cc0:	681b      	ldr	r3, [r3, #0]
- 8001cc2:	4a32      	ldr	r2, [pc, #200]	@ (8001d8c <ADSCalculate_ph_Compensated+0xfc>)
- 8001cc4:	6812      	ldr	r2, [r2, #0]
- 8001cc6:	4611      	mov	r1, r2
- 8001cc8:	4618      	mov	r0, r3
- 8001cca:	f7fe fd59 	bl	8000780 <__aeabi_fsub>
- 8001cce:	4603      	mov	r3, r0
- 8001cd0:	61fb      	str	r3, [r7, #28]
+    float delta_v_calib = flash_data.ph7_value - flash_data.ph4_value;
+ 8001f1a:	4b32      	ldr	r3, [pc, #200]	@ (8001fe4 <ADSCalculate_ph_Compensated+0xf8>)
+ 8001f1c:	689b      	ldr	r3, [r3, #8]
+ 8001f1e:	4a31      	ldr	r2, [pc, #196]	@ (8001fe4 <ADSCalculate_ph_Compensated+0xf8>)
+ 8001f20:	6852      	ldr	r2, [r2, #4]
+ 8001f22:	4611      	mov	r1, r2
+ 8001f24:	4618      	mov	r0, r3
+ 8001f26:	f7fe fded 	bl	8000b04 <__aeabi_fsub>
+ 8001f2a:	4603      	mov	r3, r0
+ 8001f2c:	61fb      	str	r3, [r7, #28]
 
     if (delta_v_calib == 0.0f)
- 8001cd2:	f04f 0100 	mov.w	r1, #0
- 8001cd6:	69f8      	ldr	r0, [r7, #28]
- 8001cd8:	f7fe fff0 	bl	8000cbc <__aeabi_fcmpeq>
- 8001cdc:	4603      	mov	r3, r0
- 8001cde:	2b00      	cmp	r3, #0
- 8001ce0:	d002      	beq.n	8001ce8 <ADSCalculate_ph_Compensated+0x58>
+ 8001f2e:	f04f 0100 	mov.w	r1, #0
+ 8001f32:	69f8      	ldr	r0, [r7, #28]
+ 8001f34:	f7ff f884 	bl	8001040 <__aeabi_fcmpeq>
+ 8001f38:	4603      	mov	r3, r0
+ 8001f3a:	2b00      	cmp	r3, #0
+ 8001f3c:	d002      	beq.n	8001f44 <ADSCalculate_ph_Compensated+0x58>
     {
         return 0.0f; // Proteção contra erro de calibração/divisão por zero
- 8001ce2:	f04f 0300 	mov.w	r3, #0
- 8001ce6:	e046      	b.n	8001d76 <ADSCalculate_ph_Compensated+0xe6>
+ 8001f3e:	f04f 0300 	mov.w	r3, #0
+ 8001f42:	e046      	b.n	8001fd2 <ADSCalculate_ph_Compensated+0xe6>
     }
 
     float slope_at_calib = 3.0f / delta_v_calib;
- 8001ce8:	69f9      	ldr	r1, [r7, #28]
- 8001cea:	4829      	ldr	r0, [pc, #164]	@ (8001d90 <ADSCalculate_ph_Compensated+0x100>)
- 8001cec:	f7fe ff06 	bl	8000afc <__aeabi_fdiv>
- 8001cf0:	4603      	mov	r3, r0
- 8001cf2:	61bb      	str	r3, [r7, #24]
+ 8001f44:	69f9      	ldr	r1, [r7, #28]
+ 8001f46:	4828      	ldr	r0, [pc, #160]	@ (8001fe8 <ADSCalculate_ph_Compensated+0xfc>)
+ 8001f48:	f7fe ff9a 	bl	8000e80 <__aeabi_fdiv>
+ 8001f4c:	4603      	mov	r3, r0
+ 8001f4e:	61bb      	str	r3, [r7, #24]
 
     // 3. Calcular o Fator de Correção Térmica (Equação de Nernst)
     float temp_k_now = temp_dut + ADS1015_KELVIN_OFFSET;
- 8001cf4:	4927      	ldr	r1, [pc, #156]	@ (8001d94 <ADSCalculate_ph_Compensated+0x104>)
- 8001cf6:	6838      	ldr	r0, [r7, #0]
- 8001cf8:	f7fe fd44 	bl	8000784 <__addsf3>
- 8001cfc:	4603      	mov	r3, r0
- 8001cfe:	617b      	str	r3, [r7, #20]
-	float temp_k_ref = temp_calib + ADS1015_KELVIN_OFFSET;
- 8001d00:	4b25      	ldr	r3, [pc, #148]	@ (8001d98 <ADSCalculate_ph_Compensated+0x108>)
- 8001d02:	681b      	ldr	r3, [r3, #0]
- 8001d04:	4923      	ldr	r1, [pc, #140]	@ (8001d94 <ADSCalculate_ph_Compensated+0x104>)
- 8001d06:	4618      	mov	r0, r3
- 8001d08:	f7fe fd3c 	bl	8000784 <__addsf3>
- 8001d0c:	4603      	mov	r3, r0
- 8001d0e:	613b      	str	r3, [r7, #16]
+ 8001f50:	4926      	ldr	r1, [pc, #152]	@ (8001fec <ADSCalculate_ph_Compensated+0x100>)
+ 8001f52:	6838      	ldr	r0, [r7, #0]
+ 8001f54:	f7fe fdd8 	bl	8000b08 <__addsf3>
+ 8001f58:	4603      	mov	r3, r0
+ 8001f5a:	617b      	str	r3, [r7, #20]
+	float temp_k_ref = flash_data.temperature_value + ADS1015_KELVIN_OFFSET;
+ 8001f5c:	4b21      	ldr	r3, [pc, #132]	@ (8001fe4 <ADSCalculate_ph_Compensated+0xf8>)
+ 8001f5e:	695b      	ldr	r3, [r3, #20]
+ 8001f60:	4922      	ldr	r1, [pc, #136]	@ (8001fec <ADSCalculate_ph_Compensated+0x100>)
+ 8001f62:	4618      	mov	r0, r3
+ 8001f64:	f7fe fdd0 	bl	8000b08 <__addsf3>
+ 8001f68:	4603      	mov	r3, r0
+ 8001f6a:	613b      	str	r3, [r7, #16]
 
 	// Fator: (T_atual / T_referencia)
 	float thermal_factor = temp_k_now / temp_k_ref;
- 8001d10:	6939      	ldr	r1, [r7, #16]
- 8001d12:	6978      	ldr	r0, [r7, #20]
- 8001d14:	f7fe fef2 	bl	8000afc <__aeabi_fdiv>
- 8001d18:	4603      	mov	r3, r0
- 8001d1a:	60fb      	str	r3, [r7, #12]
+ 8001f6c:	6939      	ldr	r1, [r7, #16]
+ 8001f6e:	6978      	ldr	r0, [r7, #20]
+ 8001f70:	f7fe ff86 	bl	8000e80 <__aeabi_fdiv>
+ 8001f74:	4603      	mov	r3, r0
+ 8001f76:	60fb      	str	r3, [r7, #12]
 	/*
 	 * 4. Cálculo Final do pH
 	 * O Slope ajustado para a temperatura atual é: slope_at_calib / thermal_factor
 	 * Fórmula: pH = pH_ref + (V_medido - V_ref_7) * Slope_ajustado
 	 */
-	float ph_result = 7.0f + ((v_measured - v_ph7) * (slope_at_calib / thermal_factor));
- 8001d1c:	4b1a      	ldr	r3, [pc, #104]	@ (8001d88 <ADSCalculate_ph_Compensated+0xf8>)
- 8001d1e:	681b      	ldr	r3, [r3, #0]
- 8001d20:	4619      	mov	r1, r3
- 8001d22:	6a38      	ldr	r0, [r7, #32]
- 8001d24:	f7fe fd2c 	bl	8000780 <__aeabi_fsub>
- 8001d28:	4603      	mov	r3, r0
- 8001d2a:	461c      	mov	r4, r3
- 8001d2c:	68f9      	ldr	r1, [r7, #12]
- 8001d2e:	69b8      	ldr	r0, [r7, #24]
- 8001d30:	f7fe fee4 	bl	8000afc <__aeabi_fdiv>
- 8001d34:	4603      	mov	r3, r0
- 8001d36:	4619      	mov	r1, r3
- 8001d38:	4620      	mov	r0, r4
- 8001d3a:	f7fe fe2b 	bl	8000994 <__aeabi_fmul>
- 8001d3e:	4603      	mov	r3, r0
- 8001d40:	4916      	ldr	r1, [pc, #88]	@ (8001d9c <ADSCalculate_ph_Compensated+0x10c>)
- 8001d42:	4618      	mov	r0, r3
- 8001d44:	f7fe fd1e 	bl	8000784 <__addsf3>
- 8001d48:	4603      	mov	r3, r0
- 8001d4a:	627b      	str	r3, [r7, #36]	@ 0x24
+	float ph_result = 7.0f + ((v_measured - flash_data.ph7_value) * (slope_at_calib / thermal_factor));
+ 8001f78:	4b1a      	ldr	r3, [pc, #104]	@ (8001fe4 <ADSCalculate_ph_Compensated+0xf8>)
+ 8001f7a:	689b      	ldr	r3, [r3, #8]
+ 8001f7c:	4619      	mov	r1, r3
+ 8001f7e:	6a38      	ldr	r0, [r7, #32]
+ 8001f80:	f7fe fdc0 	bl	8000b04 <__aeabi_fsub>
+ 8001f84:	4603      	mov	r3, r0
+ 8001f86:	461c      	mov	r4, r3
+ 8001f88:	68f9      	ldr	r1, [r7, #12]
+ 8001f8a:	69b8      	ldr	r0, [r7, #24]
+ 8001f8c:	f7fe ff78 	bl	8000e80 <__aeabi_fdiv>
+ 8001f90:	4603      	mov	r3, r0
+ 8001f92:	4619      	mov	r1, r3
+ 8001f94:	4620      	mov	r0, r4
+ 8001f96:	f7fe febf 	bl	8000d18 <__aeabi_fmul>
+ 8001f9a:	4603      	mov	r3, r0
+ 8001f9c:	4914      	ldr	r1, [pc, #80]	@ (8001ff0 <ADSCalculate_ph_Compensated+0x104>)
+ 8001f9e:	4618      	mov	r0, r3
+ 8001fa0:	f7fe fdb2 	bl	8000b08 <__addsf3>
+ 8001fa4:	4603      	mov	r3, r0
+ 8001fa6:	627b      	str	r3, [r7, #36]	@ 0x24
 
 	// 5. Clamping (Garantir limites físicos)
 	if (ph_result < 0.0f) ph_result = 0.0f;
- 8001d4c:	f04f 0100 	mov.w	r1, #0
- 8001d50:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 8001d52:	f7fe ffbd 	bl	8000cd0 <__aeabi_fcmplt>
- 8001d56:	4603      	mov	r3, r0
- 8001d58:	2b00      	cmp	r3, #0
- 8001d5a:	d002      	beq.n	8001d62 <ADSCalculate_ph_Compensated+0xd2>
- 8001d5c:	f04f 0300 	mov.w	r3, #0
- 8001d60:	627b      	str	r3, [r7, #36]	@ 0x24
+ 8001fa8:	f04f 0100 	mov.w	r1, #0
+ 8001fac:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 8001fae:	f7ff f851 	bl	8001054 <__aeabi_fcmplt>
+ 8001fb2:	4603      	mov	r3, r0
+ 8001fb4:	2b00      	cmp	r3, #0
+ 8001fb6:	d002      	beq.n	8001fbe <ADSCalculate_ph_Compensated+0xd2>
+ 8001fb8:	f04f 0300 	mov.w	r3, #0
+ 8001fbc:	627b      	str	r3, [r7, #36]	@ 0x24
 	if (ph_result > 14.0f) ph_result = 14.0f;
- 8001d62:	490f      	ldr	r1, [pc, #60]	@ (8001da0 <ADSCalculate_ph_Compensated+0x110>)
- 8001d64:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 8001d66:	f7fe ffd1 	bl	8000d0c <__aeabi_fcmpgt>
- 8001d6a:	4603      	mov	r3, r0
- 8001d6c:	2b00      	cmp	r3, #0
- 8001d6e:	d001      	beq.n	8001d74 <ADSCalculate_ph_Compensated+0xe4>
- 8001d70:	4b0b      	ldr	r3, [pc, #44]	@ (8001da0 <ADSCalculate_ph_Compensated+0x110>)
- 8001d72:	627b      	str	r3, [r7, #36]	@ 0x24
+ 8001fbe:	490d      	ldr	r1, [pc, #52]	@ (8001ff4 <ADSCalculate_ph_Compensated+0x108>)
+ 8001fc0:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 8001fc2:	f7ff f865 	bl	8001090 <__aeabi_fcmpgt>
+ 8001fc6:	4603      	mov	r3, r0
+ 8001fc8:	2b00      	cmp	r3, #0
+ 8001fca:	d001      	beq.n	8001fd0 <ADSCalculate_ph_Compensated+0xe4>
+ 8001fcc:	4b09      	ldr	r3, [pc, #36]	@ (8001ff4 <ADSCalculate_ph_Compensated+0x108>)
+ 8001fce:	627b      	str	r3, [r7, #36]	@ 0x24
 
 	return ph_result;
- 8001d74:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8001fd0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 }
- 8001d76:	4618      	mov	r0, r3
- 8001d78:	372c      	adds	r7, #44	@ 0x2c
- 8001d7a:	46bd      	mov	sp, r7
- 8001d7c:	bd90      	pop	{r4, r7, pc}
- 8001d7e:	bf00      	nop
- 8001d80:	40533333 	.word	0x40533333
- 8001d84:	457ff000 	.word	0x457ff000
- 8001d88:	200001c0 	.word	0x200001c0
- 8001d8c:	200001bc 	.word	0x200001bc
- 8001d90:	40400000 	.word	0x40400000
- 8001d94:	43889333 	.word	0x43889333
- 8001d98:	200001b4 	.word	0x200001b4
- 8001d9c:	40e00000 	.word	0x40e00000
- 8001da0:	41600000 	.word	0x41600000
+ 8001fd2:	4618      	mov	r0, r3
+ 8001fd4:	372c      	adds	r7, #44	@ 0x2c
+ 8001fd6:	46bd      	mov	sp, r7
+ 8001fd8:	bd90      	pop	{r4, r7, pc}
+ 8001fda:	bf00      	nop
+ 8001fdc:	40533333 	.word	0x40533333
+ 8001fe0:	457ff000 	.word	0x457ff000
+ 8001fe4:	200001f8 	.word	0x200001f8
+ 8001fe8:	40400000 	.word	0x40400000
+ 8001fec:	43889333 	.word	0x43889333
+ 8001ff0:	40e00000 	.word	0x40e00000
+ 8001ff4:	41600000 	.word	0x41600000
 
-08001da4 <digital_outputs_init>:
+08001ff8 <digital_outputs_init>:
  * @brief Initializes the GPIO hardware and sets initial states.
  * @note This function replaces the handle-based init.
  * @retval None
  */
 void digital_outputs_init(void)
 {
- 8001da4:	b580      	push	{r7, lr}
- 8001da6:	b086      	sub	sp, #24
- 8001da8:	af00      	add	r7, sp, #0
+ 8001ff8:	b580      	push	{r7, lr}
+ 8001ffa:	b086      	sub	sp, #24
+ 8001ffc:	af00      	add	r7, sp, #0
     GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001daa:	1d3b      	adds	r3, r7, #4
- 8001dac:	2200      	movs	r2, #0
- 8001dae:	601a      	str	r2, [r3, #0]
- 8001db0:	605a      	str	r2, [r3, #4]
- 8001db2:	609a      	str	r2, [r3, #8]
- 8001db4:	60da      	str	r2, [r3, #12]
+ 8001ffe:	1d3b      	adds	r3, r7, #4
+ 8002000:	2200      	movs	r2, #0
+ 8002002:	601a      	str	r2, [r3, #0]
+ 8002004:	605a      	str	r2, [r3, #4]
+ 8002006:	609a      	str	r2, [r3, #8]
+ 8002008:	60da      	str	r2, [r3, #12]
 
     for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
- 8001db6:	2300      	movs	r3, #0
- 8001db8:	617b      	str	r3, [r7, #20]
- 8001dba:	e029      	b.n	8001e10 <digital_outputs_init+0x6c>
+ 800200a:	2300      	movs	r3, #0
+ 800200c:	617b      	str	r3, [r7, #20]
+ 800200e:	e029      	b.n	8002064 <digital_outputs_init+0x6c>
         GPIO_InitStruct.Pin   = output_pins[i].pin;
- 8001dbc:	4a18      	ldr	r2, [pc, #96]	@ (8001e20 <digital_outputs_init+0x7c>)
- 8001dbe:	697b      	ldr	r3, [r7, #20]
- 8001dc0:	00db      	lsls	r3, r3, #3
- 8001dc2:	4413      	add	r3, r2
- 8001dc4:	889b      	ldrh	r3, [r3, #4]
- 8001dc6:	607b      	str	r3, [r7, #4]
+ 8002010:	4a18      	ldr	r2, [pc, #96]	@ (8002074 <digital_outputs_init+0x7c>)
+ 8002012:	697b      	ldr	r3, [r7, #20]
+ 8002014:	00db      	lsls	r3, r3, #3
+ 8002016:	4413      	add	r3, r2
+ 8002018:	889b      	ldrh	r3, [r3, #4]
+ 800201a:	607b      	str	r3, [r7, #4]
         GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD; // Open-drain
- 8001dc8:	2311      	movs	r3, #17
- 8001dca:	60bb      	str	r3, [r7, #8]
+ 800201c:	2311      	movs	r3, #17
+ 800201e:	60bb      	str	r3, [r7, #8]
         GPIO_InitStruct.Pull  = GPIO_NOPULL;
- 8001dcc:	2300      	movs	r3, #0
- 8001dce:	60fb      	str	r3, [r7, #12]
+ 8002020:	2300      	movs	r3, #0
+ 8002022:	60fb      	str	r3, [r7, #12]
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001dd0:	2302      	movs	r3, #2
- 8001dd2:	613b      	str	r3, [r7, #16]
+ 8002024:	2302      	movs	r3, #2
+ 8002026:	613b      	str	r3, [r7, #16]
 
         HAL_GPIO_Init(output_pins[i].port, &GPIO_InitStruct);
- 8001dd4:	4a12      	ldr	r2, [pc, #72]	@ (8001e20 <digital_outputs_init+0x7c>)
- 8001dd6:	697b      	ldr	r3, [r7, #20]
- 8001dd8:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
- 8001ddc:	1d3a      	adds	r2, r7, #4
- 8001dde:	4611      	mov	r1, r2
- 8001de0:	4618      	mov	r0, r3
- 8001de2:	f001 fab1 	bl	8003348 <HAL_GPIO_Init>
+ 8002028:	4a12      	ldr	r2, [pc, #72]	@ (8002074 <digital_outputs_init+0x7c>)
+ 800202a:	697b      	ldr	r3, [r7, #20]
+ 800202c:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
+ 8002030:	1d3a      	adds	r2, r7, #4
+ 8002032:	4611      	mov	r1, r2
+ 8002034:	4618      	mov	r0, r3
+ 8002036:	f002 fb9b 	bl	8004770 <HAL_GPIO_Init>
 
         // Force initial state to LOW (Reset)
         HAL_GPIO_WritePin(output_pins[i].port, output_pins[i].pin, GPIO_PIN_RESET);
- 8001de6:	4a0e      	ldr	r2, [pc, #56]	@ (8001e20 <digital_outputs_init+0x7c>)
- 8001de8:	697b      	ldr	r3, [r7, #20]
- 8001dea:	f852 0033 	ldr.w	r0, [r2, r3, lsl #3]
- 8001dee:	4a0c      	ldr	r2, [pc, #48]	@ (8001e20 <digital_outputs_init+0x7c>)
- 8001df0:	697b      	ldr	r3, [r7, #20]
- 8001df2:	00db      	lsls	r3, r3, #3
- 8001df4:	4413      	add	r3, r2
- 8001df6:	889b      	ldrh	r3, [r3, #4]
- 8001df8:	2200      	movs	r2, #0
- 8001dfa:	4619      	mov	r1, r3
- 8001dfc:	f001 fc3f 	bl	800367e <HAL_GPIO_WritePin>
+ 800203a:	4a0e      	ldr	r2, [pc, #56]	@ (8002074 <digital_outputs_init+0x7c>)
+ 800203c:	697b      	ldr	r3, [r7, #20]
+ 800203e:	f852 0033 	ldr.w	r0, [r2, r3, lsl #3]
+ 8002042:	4a0c      	ldr	r2, [pc, #48]	@ (8002074 <digital_outputs_init+0x7c>)
+ 8002044:	697b      	ldr	r3, [r7, #20]
+ 8002046:	00db      	lsls	r3, r3, #3
+ 8002048:	4413      	add	r3, r2
+ 800204a:	889b      	ldrh	r3, [r3, #4]
+ 800204c:	2200      	movs	r2, #0
+ 800204e:	4619      	mov	r1, r3
+ 8002050:	f002 fd29 	bl	8004aa6 <HAL_GPIO_WritePin>
         pin_states[i] = 0;
- 8001e00:	4a08      	ldr	r2, [pc, #32]	@ (8001e24 <digital_outputs_init+0x80>)
- 8001e02:	697b      	ldr	r3, [r7, #20]
- 8001e04:	4413      	add	r3, r2
- 8001e06:	2200      	movs	r2, #0
- 8001e08:	701a      	strb	r2, [r3, #0]
+ 8002054:	4a08      	ldr	r2, [pc, #32]	@ (8002078 <digital_outputs_init+0x80>)
+ 8002056:	697b      	ldr	r3, [r7, #20]
+ 8002058:	4413      	add	r3, r2
+ 800205a:	2200      	movs	r2, #0
+ 800205c:	701a      	strb	r2, [r3, #0]
     for (int i = 0; i < OUTPUT_PINS_COUNT; i++) {
- 8001e0a:	697b      	ldr	r3, [r7, #20]
- 8001e0c:	3301      	adds	r3, #1
- 8001e0e:	617b      	str	r3, [r7, #20]
- 8001e10:	697b      	ldr	r3, [r7, #20]
- 8001e12:	2b07      	cmp	r3, #7
- 8001e14:	ddd2      	ble.n	8001dbc <digital_outputs_init+0x18>
+ 800205e:	697b      	ldr	r3, [r7, #20]
+ 8002060:	3301      	adds	r3, #1
+ 8002062:	617b      	str	r3, [r7, #20]
+ 8002064:	697b      	ldr	r3, [r7, #20]
+ 8002066:	2b07      	cmp	r3, #7
+ 8002068:	ddd2      	ble.n	8002010 <digital_outputs_init+0x18>
     }
 }
- 8001e16:	bf00      	nop
- 8001e18:	bf00      	nop
- 8001e1a:	3718      	adds	r7, #24
- 8001e1c:	46bd      	mov	sp, r7
- 8001e1e:	bd80      	pop	{r7, pc}
- 8001e20:	08005ef4 	.word	0x08005ef4
- 8001e24:	200001c4 	.word	0x200001c4
+ 800206a:	bf00      	nop
+ 800206c:	bf00      	nop
+ 800206e:	3718      	adds	r7, #24
+ 8002070:	46bd      	mov	sp, r7
+ 8002072:	bd80      	pop	{r7, pc}
+ 8002074:	08007a20 	.word	0x08007a20
+ 8002078:	200001f0 	.word	0x200001f0
 
-08001e28 <MX_GPIO_Init>:
+0800207c <MX_DMA_Init>:
+
+/**
+  * Enable DMA controller clock
+  */
+void MX_DMA_Init(void)
+{
+ 800207c:	b580      	push	{r7, lr}
+ 800207e:	b082      	sub	sp, #8
+ 8002080:	af00      	add	r7, sp, #0
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8002082:	4b0c      	ldr	r3, [pc, #48]	@ (80020b4 <MX_DMA_Init+0x38>)
+ 8002084:	695b      	ldr	r3, [r3, #20]
+ 8002086:	4a0b      	ldr	r2, [pc, #44]	@ (80020b4 <MX_DMA_Init+0x38>)
+ 8002088:	f043 0301 	orr.w	r3, r3, #1
+ 800208c:	6153      	str	r3, [r2, #20]
+ 800208e:	4b09      	ldr	r3, [pc, #36]	@ (80020b4 <MX_DMA_Init+0x38>)
+ 8002090:	695b      	ldr	r3, [r3, #20]
+ 8002092:	f003 0301 	and.w	r3, r3, #1
+ 8002096:	607b      	str	r3, [r7, #4]
+ 8002098:	687b      	ldr	r3, [r7, #4]
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+ 800209a:	2200      	movs	r2, #0
+ 800209c:	2100      	movs	r1, #0
+ 800209e:	200b      	movs	r0, #11
+ 80020a0:	f001 fe8d 	bl	8003dbe <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+ 80020a4:	200b      	movs	r0, #11
+ 80020a6:	f001 fea6 	bl	8003df6 <HAL_NVIC_EnableIRQ>
+
+}
+ 80020aa:	bf00      	nop
+ 80020ac:	3708      	adds	r7, #8
+ 80020ae:	46bd      	mov	sp, r7
+ 80020b0:	bd80      	pop	{r7, pc}
+ 80020b2:	bf00      	nop
+ 80020b4:	40021000 	.word	0x40021000
+
+080020b8 <Flash_Save_Page>:
+ * @return HAL_OK em caso de sucesso.
+ */
+
+FlashPage_t flash_data;
+
+HAL_StatusTypeDef Flash_Save_Page(FlashPage_t *pPage) {
+ 80020b8:	b5b0      	push	{r4, r5, r7, lr}
+ 80020ba:	b08c      	sub	sp, #48	@ 0x30
+ 80020bc:	af00      	add	r7, sp, #0
+ 80020be:	6078      	str	r0, [r7, #4]
+    if (pPage == NULL) return HAL_ERROR;
+ 80020c0:	687b      	ldr	r3, [r7, #4]
+ 80020c2:	2b00      	cmp	r3, #0
+ 80020c4:	d101      	bne.n	80020ca <Flash_Save_Page+0x12>
+ 80020c6:	2301      	movs	r3, #1
+ 80020c8:	e04a      	b.n	8002160 <Flash_Save_Page+0xa8>
+
+    HAL_StatusTypeDef status = HAL_OK;
+ 80020ca:	2300      	movs	r3, #0
+ 80020cc:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
+
+    HAL_FLASH_Unlock();
+ 80020d0:	f002 f9be 	bl	8004450 <HAL_FLASH_Unlock>
+
+    // 1. Apagar a página inteira (limpa os 1024 bytes)
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    uint32_t PageError = 0;
+ 80020d4:	2300      	movs	r3, #0
+ 80020d6:	60bb      	str	r3, [r7, #8]
+
+    EraseInitStruct.TypeErase     = FLASH_TYPEERASE_PAGES;
+ 80020d8:	2300      	movs	r3, #0
+ 80020da:	60fb      	str	r3, [r7, #12]
+    EraseInitStruct.PageAddress   = FLASH_PAGE_ADDR;
+ 80020dc:	4b22      	ldr	r3, [pc, #136]	@ (8002168 <Flash_Save_Page+0xb0>)
+ 80020de:	617b      	str	r3, [r7, #20]
+    EraseInitStruct.NbPages       = 1;
+ 80020e0:	2301      	movs	r3, #1
+ 80020e2:	61bb      	str	r3, [r7, #24]
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) {
+ 80020e4:	f107 0208 	add.w	r2, r7, #8
+ 80020e8:	f107 030c 	add.w	r3, r7, #12
+ 80020ec:	4611      	mov	r1, r2
+ 80020ee:	4618      	mov	r0, r3
+ 80020f0:	f002 fa96 	bl	8004620 <HAL_FLASHEx_Erase>
+ 80020f4:	4603      	mov	r3, r0
+ 80020f6:	2b00      	cmp	r3, #0
+ 80020f8:	d003      	beq.n	8002102 <Flash_Save_Page+0x4a>
+        status = HAL_ERROR;
+ 80020fa:	2301      	movs	r3, #1
+ 80020fc:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
+        goto Exit;
+ 8002100:	e02a      	b.n	8002158 <Flash_Save_Page+0xa0>
+
+    // 2. Gravar o bloco de 1KB
+    // Como a estrutura é exatamente 1KB e alinhada, podemos tratar como um array de uint32_t.
+    // O STM32F1 grava preferencialmente em DoubleWord (64-bit), mas HalfWord (16-bit)
+    // funciona de forma segura para qualquer tamanho múltiplo de 2.
+    uint32_t *pSrc = (uint32_t *)pPage;
+ 8002102:	687b      	ldr	r3, [r7, #4]
+ 8002104:	627b      	str	r3, [r7, #36]	@ 0x24
+    uint32_t *pDest = (uint32_t *)FLASH_PAGE_ADDR;
+ 8002106:	4b18      	ldr	r3, [pc, #96]	@ (8002168 <Flash_Save_Page+0xb0>)
+ 8002108:	623b      	str	r3, [r7, #32]
+    uint32_t iterations = FLASH_PAGE_SIZE / sizeof(uint32_t); // 1024 / 4 = 256 iterações
+ 800210a:	f44f 7380 	mov.w	r3, #256	@ 0x100
+ 800210e:	61fb      	str	r3, [r7, #28]
+
+    for (uint32_t i = 0; i < iterations; i++) {
+ 8002110:	2300      	movs	r3, #0
+ 8002112:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8002114:	e01b      	b.n	800214e <Flash_Save_Page+0x96>
+        // Usamos o modo de gravação de 32-bit (Word) se disponível,
+        // ou simulamos com duas gravações de 16-bit para máxima compatuidade no F1.
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, (uint32_t)&pDest[i], pSrc[i]) != HAL_OK) {
+ 8002116:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8002118:	009b      	lsls	r3, r3, #2
+ 800211a:	6a3a      	ldr	r2, [r7, #32]
+ 800211c:	4413      	add	r3, r2
+ 800211e:	4619      	mov	r1, r3
+ 8002120:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8002122:	009b      	lsls	r3, r3, #2
+ 8002124:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8002126:	4413      	add	r3, r2
+ 8002128:	681b      	ldr	r3, [r3, #0]
+ 800212a:	2200      	movs	r2, #0
+ 800212c:	461c      	mov	r4, r3
+ 800212e:	4615      	mov	r5, r2
+ 8002130:	4622      	mov	r2, r4
+ 8002132:	462b      	mov	r3, r5
+ 8002134:	2002      	movs	r0, #2
+ 8002136:	f002 f91b 	bl	8004370 <HAL_FLASH_Program>
+ 800213a:	4603      	mov	r3, r0
+ 800213c:	2b00      	cmp	r3, #0
+ 800213e:	d003      	beq.n	8002148 <Flash_Save_Page+0x90>
+            status = HAL_ERROR;
+ 8002140:	2301      	movs	r3, #1
+ 8002142:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
+            break;
+ 8002146:	e007      	b.n	8002158 <Flash_Save_Page+0xa0>
+    for (uint32_t i = 0; i < iterations; i++) {
+ 8002148:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 800214a:	3301      	adds	r3, #1
+ 800214c:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 800214e:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 8002150:	69fb      	ldr	r3, [r7, #28]
+ 8002152:	429a      	cmp	r2, r3
+ 8002154:	d3df      	bcc.n	8002116 <Flash_Save_Page+0x5e>
+        }
+    }
+
+Exit:
+ 8002156:	bf00      	nop
+    HAL_FLASH_Lock();
+ 8002158:	f002 f9a0 	bl	800449c <HAL_FLASH_Lock>
+    return status;
+ 800215c:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
+}
+ 8002160:	4618      	mov	r0, r3
+ 8002162:	3730      	adds	r7, #48	@ 0x30
+ 8002164:	46bd      	mov	sp, r7
+ 8002166:	bdb0      	pop	{r4, r5, r7, pc}
+ 8002168:	0800fc00 	.word	0x0800fc00
+
+0800216c <Flash_Load_Page>:
+
+/**
+ * @brief Lê a página da Flash para a RAM.
+ */
+HAL_StatusTypeDef Flash_Load_Page(FlashPage_t *pDest) {
+ 800216c:	b580      	push	{r7, lr}
+ 800216e:	b082      	sub	sp, #8
+ 8002170:	af00      	add	r7, sp, #0
+ 8002172:	6078      	str	r0, [r7, #4]
+    if (pDest == NULL) return HAL_ERROR;
+ 8002174:	687b      	ldr	r3, [r7, #4]
+ 8002176:	2b00      	cmp	r3, #0
+ 8002178:	d101      	bne.n	800217e <Flash_Load_Page+0x12>
+ 800217a:	2301      	movs	r3, #1
+ 800217c:	e00d      	b.n	800219a <Flash_Load_Page+0x2e>
+
+    // Leitura direta por memcpy (A Flash é mapeada no espaço de endereçamento comum)
+    memcpy(pDest, (void *)FLASH_PAGE_ADDR, FLASH_PAGE_SIZE);
+ 800217e:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8002182:	4908      	ldr	r1, [pc, #32]	@ (80021a4 <Flash_Load_Page+0x38>)
+ 8002184:	6878      	ldr	r0, [r7, #4]
+ 8002186:	f005 fb7d 	bl	8007884 <memcpy>
+
+    // Validação da integridade através do Magic Number
+    if (pDest->magic_number != 0xDEADBEEF) {
+ 800218a:	687b      	ldr	r3, [r7, #4]
+ 800218c:	681b      	ldr	r3, [r3, #0]
+ 800218e:	4a06      	ldr	r2, [pc, #24]	@ (80021a8 <Flash_Load_Page+0x3c>)
+ 8002190:	4293      	cmp	r3, r2
+ 8002192:	d001      	beq.n	8002198 <Flash_Load_Page+0x2c>
+        return HAL_ERROR;
+ 8002194:	2301      	movs	r3, #1
+ 8002196:	e000      	b.n	800219a <Flash_Load_Page+0x2e>
+    }
+
+    return HAL_OK;
+ 8002198:	2300      	movs	r3, #0
+}
+ 800219a:	4618      	mov	r0, r3
+ 800219c:	3708      	adds	r7, #8
+ 800219e:	46bd      	mov	sp, r7
+ 80021a0:	bd80      	pop	{r7, pc}
+ 80021a2:	bf00      	nop
+ 80021a4:	0800fc00 	.word	0x0800fc00
+ 80021a8:	deadbeef 	.word	0xdeadbeef
+
+080021ac <MX_GPIO_Init>:
         * EXTI
         * Free pins are configured automatically as Analog (this feature is enabled through
         * the Code Generation settings)
 */
 void MX_GPIO_Init(void)
 {
- 8001e28:	b580      	push	{r7, lr}
- 8001e2a:	b088      	sub	sp, #32
- 8001e2c:	af00      	add	r7, sp, #0
+ 80021ac:	b580      	push	{r7, lr}
+ 80021ae:	b088      	sub	sp, #32
+ 80021b0:	af00      	add	r7, sp, #0
 
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001e2e:	f107 0310 	add.w	r3, r7, #16
- 8001e32:	2200      	movs	r2, #0
- 8001e34:	601a      	str	r2, [r3, #0]
- 8001e36:	605a      	str	r2, [r3, #4]
- 8001e38:	609a      	str	r2, [r3, #8]
- 8001e3a:	60da      	str	r2, [r3, #12]
+ 80021b2:	f107 0310 	add.w	r3, r7, #16
+ 80021b6:	2200      	movs	r2, #0
+ 80021b8:	601a      	str	r2, [r3, #0]
+ 80021ba:	605a      	str	r2, [r3, #4]
+ 80021bc:	609a      	str	r2, [r3, #8]
+ 80021be:	60da      	str	r2, [r3, #12]
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOC_CLK_ENABLE();
- 8001e3c:	4b50      	ldr	r3, [pc, #320]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e3e:	699b      	ldr	r3, [r3, #24]
- 8001e40:	4a4f      	ldr	r2, [pc, #316]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e42:	f043 0310 	orr.w	r3, r3, #16
- 8001e46:	6193      	str	r3, [r2, #24]
- 8001e48:	4b4d      	ldr	r3, [pc, #308]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e4a:	699b      	ldr	r3, [r3, #24]
- 8001e4c:	f003 0310 	and.w	r3, r3, #16
- 8001e50:	60fb      	str	r3, [r7, #12]
- 8001e52:	68fb      	ldr	r3, [r7, #12]
+ 80021c0:	4b50      	ldr	r3, [pc, #320]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021c2:	699b      	ldr	r3, [r3, #24]
+ 80021c4:	4a4f      	ldr	r2, [pc, #316]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021c6:	f043 0310 	orr.w	r3, r3, #16
+ 80021ca:	6193      	str	r3, [r2, #24]
+ 80021cc:	4b4d      	ldr	r3, [pc, #308]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021ce:	699b      	ldr	r3, [r3, #24]
+ 80021d0:	f003 0310 	and.w	r3, r3, #16
+ 80021d4:	60fb      	str	r3, [r7, #12]
+ 80021d6:	68fb      	ldr	r3, [r7, #12]
   __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001e54:	4b4a      	ldr	r3, [pc, #296]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e56:	699b      	ldr	r3, [r3, #24]
- 8001e58:	4a49      	ldr	r2, [pc, #292]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e5a:	f043 0320 	orr.w	r3, r3, #32
- 8001e5e:	6193      	str	r3, [r2, #24]
- 8001e60:	4b47      	ldr	r3, [pc, #284]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e62:	699b      	ldr	r3, [r3, #24]
- 8001e64:	f003 0320 	and.w	r3, r3, #32
- 8001e68:	60bb      	str	r3, [r7, #8]
- 8001e6a:	68bb      	ldr	r3, [r7, #8]
+ 80021d8:	4b4a      	ldr	r3, [pc, #296]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021da:	699b      	ldr	r3, [r3, #24]
+ 80021dc:	4a49      	ldr	r2, [pc, #292]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021de:	f043 0320 	orr.w	r3, r3, #32
+ 80021e2:	6193      	str	r3, [r2, #24]
+ 80021e4:	4b47      	ldr	r3, [pc, #284]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021e6:	699b      	ldr	r3, [r3, #24]
+ 80021e8:	f003 0320 	and.w	r3, r3, #32
+ 80021ec:	60bb      	str	r3, [r7, #8]
+ 80021ee:	68bb      	ldr	r3, [r7, #8]
   __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001e6c:	4b44      	ldr	r3, [pc, #272]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e6e:	699b      	ldr	r3, [r3, #24]
- 8001e70:	4a43      	ldr	r2, [pc, #268]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e72:	f043 0304 	orr.w	r3, r3, #4
- 8001e76:	6193      	str	r3, [r2, #24]
- 8001e78:	4b41      	ldr	r3, [pc, #260]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e7a:	699b      	ldr	r3, [r3, #24]
- 8001e7c:	f003 0304 	and.w	r3, r3, #4
- 8001e80:	607b      	str	r3, [r7, #4]
- 8001e82:	687b      	ldr	r3, [r7, #4]
+ 80021f0:	4b44      	ldr	r3, [pc, #272]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021f2:	699b      	ldr	r3, [r3, #24]
+ 80021f4:	4a43      	ldr	r2, [pc, #268]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021f6:	f043 0304 	orr.w	r3, r3, #4
+ 80021fa:	6193      	str	r3, [r2, #24]
+ 80021fc:	4b41      	ldr	r3, [pc, #260]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 80021fe:	699b      	ldr	r3, [r3, #24]
+ 8002200:	f003 0304 	and.w	r3, r3, #4
+ 8002204:	607b      	str	r3, [r7, #4]
+ 8002206:	687b      	ldr	r3, [r7, #4]
   __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001e84:	4b3e      	ldr	r3, [pc, #248]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e86:	699b      	ldr	r3, [r3, #24]
- 8001e88:	4a3d      	ldr	r2, [pc, #244]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e8a:	f043 0308 	orr.w	r3, r3, #8
- 8001e8e:	6193      	str	r3, [r2, #24]
- 8001e90:	4b3b      	ldr	r3, [pc, #236]	@ (8001f80 <MX_GPIO_Init+0x158>)
- 8001e92:	699b      	ldr	r3, [r3, #24]
- 8001e94:	f003 0308 	and.w	r3, r3, #8
- 8001e98:	603b      	str	r3, [r7, #0]
- 8001e9a:	683b      	ldr	r3, [r7, #0]
+ 8002208:	4b3e      	ldr	r3, [pc, #248]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 800220a:	699b      	ldr	r3, [r3, #24]
+ 800220c:	4a3d      	ldr	r2, [pc, #244]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 800220e:	f043 0308 	orr.w	r3, r3, #8
+ 8002212:	6193      	str	r3, [r2, #24]
+ 8002214:	4b3b      	ldr	r3, [pc, #236]	@ (8002304 <MX_GPIO_Init+0x158>)
+ 8002216:	699b      	ldr	r3, [r3, #24]
+ 8002218:	f003 0308 	and.w	r3, r3, #8
+ 800221c:	603b      	str	r3, [r7, #0]
+ 800221e:	683b      	ldr	r3, [r7, #0]
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOC, DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin, GPIO_PIN_RESET);
- 8001e9c:	2200      	movs	r2, #0
- 8001e9e:	f44f 4160 	mov.w	r1, #57344	@ 0xe000
- 8001ea2:	4838      	ldr	r0, [pc, #224]	@ (8001f84 <MX_GPIO_Init+0x15c>)
- 8001ea4:	f001 fbeb 	bl	800367e <HAL_GPIO_WritePin>
+ 8002220:	2200      	movs	r2, #0
+ 8002222:	f44f 4160 	mov.w	r1, #57344	@ 0xe000
+ 8002226:	4838      	ldr	r0, [pc, #224]	@ (8002308 <MX_GPIO_Init+0x15c>)
+ 8002228:	f002 fc3d 	bl	8004aa6 <HAL_GPIO_WritePin>
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOB, DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
- 8001ea8:	2200      	movs	r2, #0
- 8001eaa:	f240 3137 	movw	r1, #823	@ 0x337
- 8001eae:	4836      	ldr	r0, [pc, #216]	@ (8001f88 <MX_GPIO_Init+0x160>)
- 8001eb0:	f001 fbe5 	bl	800367e <HAL_GPIO_WritePin>
+ 800222c:	2200      	movs	r2, #0
+ 800222e:	f240 3137 	movw	r1, #823	@ 0x337
+ 8002232:	4836      	ldr	r0, [pc, #216]	@ (800230c <MX_GPIO_Init+0x160>)
+ 8002234:	f002 fc37 	bl	8004aa6 <HAL_GPIO_WritePin>
                           |LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(TX_EN_RS485_GPIO_Port, TX_EN_RS485_Pin, GPIO_PIN_RESET);
- 8001eb4:	2200      	movs	r2, #0
- 8001eb6:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
- 8001eba:	4834      	ldr	r0, [pc, #208]	@ (8001f8c <MX_GPIO_Init+0x164>)
- 8001ebc:	f001 fbdf 	bl	800367e <HAL_GPIO_WritePin>
+ 8002238:	2200      	movs	r2, #0
+ 800223a:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
+ 800223e:	4834      	ldr	r0, [pc, #208]	@ (8002310 <MX_GPIO_Init+0x164>)
+ 8002240:	f002 fc31 	bl	8004aa6 <HAL_GPIO_WritePin>
 
   /*Configure GPIO pins : DIGI_OUT5_Pin DIGI_OUT6_Pin DIGI_OUT7_Pin */
   GPIO_InitStruct.Pin = DIGI_OUT5_Pin|DIGI_OUT6_Pin|DIGI_OUT7_Pin;
- 8001ec0:	f44f 4360 	mov.w	r3, #57344	@ 0xe000
- 8001ec4:	613b      	str	r3, [r7, #16]
+ 8002244:	f44f 4360 	mov.w	r3, #57344	@ 0xe000
+ 8002248:	613b      	str	r3, [r7, #16]
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
- 8001ec6:	2311      	movs	r3, #17
- 8001ec8:	617b      	str	r3, [r7, #20]
+ 800224a:	2311      	movs	r3, #17
+ 800224c:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001eca:	2300      	movs	r3, #0
- 8001ecc:	61bb      	str	r3, [r7, #24]
+ 800224e:	2300      	movs	r3, #0
+ 8002250:	61bb      	str	r3, [r7, #24]
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001ece:	2302      	movs	r3, #2
- 8001ed0:	61fb      	str	r3, [r7, #28]
+ 8002252:	2302      	movs	r3, #2
+ 8002254:	61fb      	str	r3, [r7, #28]
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8001ed2:	f107 0310 	add.w	r3, r7, #16
- 8001ed6:	4619      	mov	r1, r3
- 8001ed8:	482a      	ldr	r0, [pc, #168]	@ (8001f84 <MX_GPIO_Init+0x15c>)
- 8001eda:	f001 fa35 	bl	8003348 <HAL_GPIO_Init>
+ 8002256:	f107 0310 	add.w	r3, r7, #16
+ 800225a:	4619      	mov	r1, r3
+ 800225c:	482a      	ldr	r0, [pc, #168]	@ (8002308 <MX_GPIO_Init+0x15c>)
+ 800225e:	f002 fa87 	bl	8004770 <HAL_GPIO_Init>
 
   /*Configure GPIO pins : RS485_Addr0_Pin RS485_Addr1_Pin RS485_Addr2_Pin RS485_Addr3_Pin
                            SYS_CFG0_Pin SYS_CFG1_Pin PG_RS485_Pin PG_CE_Pin
                            PG_PH_Pin */
   GPIO_InitStruct.Pin = RS485_Addr0_Pin|RS485_Addr1_Pin|RS485_Addr2_Pin|RS485_Addr3_Pin
- 8001ede:	f648 13fc 	movw	r3, #35324	@ 0x89fc
- 8001ee2:	613b      	str	r3, [r7, #16]
+ 8002262:	f648 13fc 	movw	r3, #35324	@ 0x89fc
+ 8002266:	613b      	str	r3, [r7, #16]
                           |SYS_CFG0_Pin|SYS_CFG1_Pin|PG_RS485_Pin|PG_CE_Pin
                           |PG_PH_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001ee4:	2300      	movs	r3, #0
- 8001ee6:	617b      	str	r3, [r7, #20]
+ 8002268:	2300      	movs	r3, #0
+ 800226a:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8001ee8:	2301      	movs	r3, #1
- 8001eea:	61bb      	str	r3, [r7, #24]
+ 800226c:	2301      	movs	r3, #1
+ 800226e:	61bb      	str	r3, [r7, #24]
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8001eec:	f107 0310 	add.w	r3, r7, #16
- 8001ef0:	4619      	mov	r1, r3
- 8001ef2:	4826      	ldr	r0, [pc, #152]	@ (8001f8c <MX_GPIO_Init+0x164>)
- 8001ef4:	f001 fa28 	bl	8003348 <HAL_GPIO_Init>
+ 8002270:	f107 0310 	add.w	r3, r7, #16
+ 8002274:	4619      	mov	r1, r3
+ 8002276:	4826      	ldr	r0, [pc, #152]	@ (8002310 <MX_GPIO_Init+0x164>)
+ 8002278:	f002 fa7a 	bl	8004770 <HAL_GPIO_Init>
 
   /*Configure GPIO pins : DIGI_OUT0_Pin DIGI_OUT1_Pin DIGI_OUT2_Pin LED_Red_Pin
                            LED_Green_Pin DIGI_OUT3_Pin DIGI_OUT4_Pin */
   GPIO_InitStruct.Pin = DIGI_OUT0_Pin|DIGI_OUT1_Pin|DIGI_OUT2_Pin|LED_Red_Pin
- 8001ef8:	f240 3337 	movw	r3, #823	@ 0x337
- 8001efc:	613b      	str	r3, [r7, #16]
+ 800227c:	f240 3337 	movw	r3, #823	@ 0x337
+ 8002280:	613b      	str	r3, [r7, #16]
                           |LED_Green_Pin|DIGI_OUT3_Pin|DIGI_OUT4_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
- 8001efe:	2311      	movs	r3, #17
- 8001f00:	617b      	str	r3, [r7, #20]
+ 8002282:	2311      	movs	r3, #17
+ 8002284:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001f02:	2300      	movs	r3, #0
- 8001f04:	61bb      	str	r3, [r7, #24]
+ 8002286:	2300      	movs	r3, #0
+ 8002288:	61bb      	str	r3, [r7, #24]
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001f06:	2302      	movs	r3, #2
- 8001f08:	61fb      	str	r3, [r7, #28]
+ 800228a:	2302      	movs	r3, #2
+ 800228c:	61fb      	str	r3, [r7, #28]
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8001f0a:	f107 0310 	add.w	r3, r7, #16
- 8001f0e:	4619      	mov	r1, r3
- 8001f10:	481d      	ldr	r0, [pc, #116]	@ (8001f88 <MX_GPIO_Init+0x160>)
- 8001f12:	f001 fa19 	bl	8003348 <HAL_GPIO_Init>
+ 800228e:	f107 0310 	add.w	r3, r7, #16
+ 8002292:	4619      	mov	r1, r3
+ 8002294:	481d      	ldr	r0, [pc, #116]	@ (800230c <MX_GPIO_Init+0x160>)
+ 8002296:	f002 fa6b 	bl	8004770 <HAL_GPIO_Init>
 
   /*Configure GPIO pins : RS485_Addr4_Pin RS485_Addr5_Pin RS485_Addr6_Pin RS485_Addr7_Pin */
   GPIO_InitStruct.Pin = RS485_Addr4_Pin|RS485_Addr5_Pin|RS485_Addr6_Pin|RS485_Addr7_Pin;
- 8001f16:	f44f 4370 	mov.w	r3, #61440	@ 0xf000
- 8001f1a:	613b      	str	r3, [r7, #16]
+ 800229a:	f44f 4370 	mov.w	r3, #61440	@ 0xf000
+ 800229e:	613b      	str	r3, [r7, #16]
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001f1c:	2300      	movs	r3, #0
- 8001f1e:	617b      	str	r3, [r7, #20]
+ 80022a0:	2300      	movs	r3, #0
+ 80022a2:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8001f20:	2301      	movs	r3, #1
- 8001f22:	61bb      	str	r3, [r7, #24]
+ 80022a4:	2301      	movs	r3, #1
+ 80022a6:	61bb      	str	r3, [r7, #24]
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8001f24:	f107 0310 	add.w	r3, r7, #16
- 8001f28:	4619      	mov	r1, r3
- 8001f2a:	4817      	ldr	r0, [pc, #92]	@ (8001f88 <MX_GPIO_Init+0x160>)
- 8001f2c:	f001 fa0c 	bl	8003348 <HAL_GPIO_Init>
+ 80022a8:	f107 0310 	add.w	r3, r7, #16
+ 80022ac:	4619      	mov	r1, r3
+ 80022ae:	4817      	ldr	r0, [pc, #92]	@ (800230c <MX_GPIO_Init+0x160>)
+ 80022b0:	f002 fa5e 	bl	8004770 <HAL_GPIO_Init>
 
   /*Configure GPIO pin : TX_EN_RS485_Pin */
   GPIO_InitStruct.Pin = TX_EN_RS485_Pin;
- 8001f30:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
- 8001f34:	613b      	str	r3, [r7, #16]
+ 80022b4:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 80022b8:	613b      	str	r3, [r7, #16]
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001f36:	2301      	movs	r3, #1
- 8001f38:	617b      	str	r3, [r7, #20]
+ 80022ba:	2301      	movs	r3, #1
+ 80022bc:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001f3a:	2300      	movs	r3, #0
- 8001f3c:	61bb      	str	r3, [r7, #24]
+ 80022be:	2300      	movs	r3, #0
+ 80022c0:	61bb      	str	r3, [r7, #24]
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001f3e:	2302      	movs	r3, #2
- 8001f40:	61fb      	str	r3, [r7, #28]
+ 80022c2:	2302      	movs	r3, #2
+ 80022c4:	61fb      	str	r3, [r7, #28]
   HAL_GPIO_Init(TX_EN_RS485_GPIO_Port, &GPIO_InitStruct);
- 8001f42:	f107 0310 	add.w	r3, r7, #16
- 8001f46:	4619      	mov	r1, r3
- 8001f48:	4810      	ldr	r0, [pc, #64]	@ (8001f8c <MX_GPIO_Init+0x164>)
- 8001f4a:	f001 f9fd 	bl	8003348 <HAL_GPIO_Init>
+ 80022c6:	f107 0310 	add.w	r3, r7, #16
+ 80022ca:	4619      	mov	r1, r3
+ 80022cc:	4810      	ldr	r0, [pc, #64]	@ (8002310 <MX_GPIO_Init+0x164>)
+ 80022ce:	f002 fa4f 	bl	8004770 <HAL_GPIO_Init>
 
   /*Configure GPIO pin : Calib_PH_Pin */
   GPIO_InitStruct.Pin = Calib_PH_Pin;
- 8001f4e:	2308      	movs	r3, #8
- 8001f50:	613b      	str	r3, [r7, #16]
+ 80022d2:	2308      	movs	r3, #8
+ 80022d4:	613b      	str	r3, [r7, #16]
   GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
- 8001f52:	4b0f      	ldr	r3, [pc, #60]	@ (8001f90 <MX_GPIO_Init+0x168>)
- 8001f54:	617b      	str	r3, [r7, #20]
+ 80022d6:	4b0f      	ldr	r3, [pc, #60]	@ (8002314 <MX_GPIO_Init+0x168>)
+ 80022d8:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8001f56:	2301      	movs	r3, #1
- 8001f58:	61bb      	str	r3, [r7, #24]
+ 80022da:	2301      	movs	r3, #1
+ 80022dc:	61bb      	str	r3, [r7, #24]
   HAL_GPIO_Init(Calib_PH_GPIO_Port, &GPIO_InitStruct);
- 8001f5a:	f107 0310 	add.w	r3, r7, #16
- 8001f5e:	4619      	mov	r1, r3
- 8001f60:	4809      	ldr	r0, [pc, #36]	@ (8001f88 <MX_GPIO_Init+0x160>)
- 8001f62:	f001 f9f1 	bl	8003348 <HAL_GPIO_Init>
+ 80022de:	f107 0310 	add.w	r3, r7, #16
+ 80022e2:	4619      	mov	r1, r3
+ 80022e4:	4809      	ldr	r0, [pc, #36]	@ (800230c <MX_GPIO_Init+0x160>)
+ 80022e6:	f002 fa43 	bl	8004770 <HAL_GPIO_Init>
 
   /* EXTI interrupt init*/
   HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0);
- 8001f66:	2200      	movs	r2, #0
- 8001f68:	2100      	movs	r1, #0
- 8001f6a:	2009      	movs	r0, #9
- 8001f6c:	f001 f903 	bl	8003176 <HAL_NVIC_SetPriority>
+ 80022ea:	2200      	movs	r2, #0
+ 80022ec:	2100      	movs	r1, #0
+ 80022ee:	2009      	movs	r0, #9
+ 80022f0:	f001 fd65 	bl	8003dbe <HAL_NVIC_SetPriority>
   HAL_NVIC_EnableIRQ(EXTI3_IRQn);
- 8001f70:	2009      	movs	r0, #9
- 8001f72:	f001 f91c 	bl	80031ae <HAL_NVIC_EnableIRQ>
+ 80022f4:	2009      	movs	r0, #9
+ 80022f6:	f001 fd7e 	bl	8003df6 <HAL_NVIC_EnableIRQ>
 
 }
- 8001f76:	bf00      	nop
- 8001f78:	3720      	adds	r7, #32
- 8001f7a:	46bd      	mov	sp, r7
- 8001f7c:	bd80      	pop	{r7, pc}
- 8001f7e:	bf00      	nop
- 8001f80:	40021000 	.word	0x40021000
- 8001f84:	40011000 	.word	0x40011000
- 8001f88:	40010c00 	.word	0x40010c00
- 8001f8c:	40010800 	.word	0x40010800
- 8001f90:	10310000 	.word	0x10310000
+ 80022fa:	bf00      	nop
+ 80022fc:	3720      	adds	r7, #32
+ 80022fe:	46bd      	mov	sp, r7
+ 8002300:	bd80      	pop	{r7, pc}
+ 8002302:	bf00      	nop
+ 8002304:	40021000 	.word	0x40021000
+ 8002308:	40011000 	.word	0x40011000
+ 800230c:	40010c00 	.word	0x40010c00
+ 8002310:	40010800 	.word	0x40010800
+ 8002314:	10310000 	.word	0x10310000
 
-08001f94 <HAL_GPIO_EXTI_Callback>:
+08002318 <HAL_GPIO_EXTI_Callback>:
  *          It distinguishes between rising and falling edges by reading the pin state.
  * @param  GPIO_Pin: Specifies the pins connected to the EXTI line.
  * @retval None
  */
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
- 8001f94:	b580      	push	{r7, lr}
- 8001f96:	b084      	sub	sp, #16
- 8001f98:	af00      	add	r7, sp, #0
- 8001f9a:	4603      	mov	r3, r0
- 8001f9c:	80fb      	strh	r3, [r7, #6]
-    if (GPIO_Pin == Calib_PH_Pin)
- 8001f9e:	88fb      	ldrh	r3, [r7, #6]
- 8001fa0:	2b08      	cmp	r3, #8
- 8001fa2:	d13b      	bne.n	800201c <HAL_GPIO_EXTI_Callback+0x88>
+ 8002318:	b580      	push	{r7, lr}
+ 800231a:	b084      	sub	sp, #16
+ 800231c:	af00      	add	r7, sp, #0
+ 800231e:	4603      	mov	r3, r0
+ 8002320:	80fb      	strh	r3, [r7, #6]
+    if ((GPIO_Pin == Calib_PH_Pin) && (main_state == STATE_RUNNING_OK))
+ 8002322:	88fb      	ldrh	r3, [r7, #6]
+ 8002324:	2b08      	cmp	r3, #8
+ 8002326:	d13f      	bne.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
+ 8002328:	4b21      	ldr	r3, [pc, #132]	@ (80023b0 <HAL_GPIO_EXTI_Callback+0x98>)
+ 800232a:	781b      	ldrb	r3, [r3, #0]
+ 800232c:	2b00      	cmp	r3, #0
+ 800232e:	d13b      	bne.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
     {
     	uint32_t current_time = HAL_GetTick();
- 8001fa4:	f000 fdd0 	bl	8002b48 <HAL_GetTick>
- 8001fa8:	60f8      	str	r0, [r7, #12]
+ 8002330:	f000 ffd0 	bl	80032d4 <HAL_GetTick>
+ 8002334:	60f8      	str	r0, [r7, #12]
     	GPIO_PinState pin_state = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3);
- 8001faa:	2108      	movs	r1, #8
- 8001fac:	481d      	ldr	r0, [pc, #116]	@ (8002024 <HAL_GPIO_EXTI_Callback+0x90>)
- 8001fae:	f001 fb4f 	bl	8003650 <HAL_GPIO_ReadPin>
- 8001fb2:	4603      	mov	r3, r0
- 8001fb4:	72fb      	strb	r3, [r7, #11]
+ 8002336:	2108      	movs	r1, #8
+ 8002338:	481e      	ldr	r0, [pc, #120]	@ (80023b4 <HAL_GPIO_EXTI_Callback+0x9c>)
+ 800233a:	f002 fb9d 	bl	8004a78 <HAL_GPIO_ReadPin>
+ 800233e:	4603      	mov	r3, r0
+ 8002340:	72fb      	strb	r3, [r7, #11]
 
     	if(pin_state != last_original_pin)
- 8001fb6:	4b1c      	ldr	r3, [pc, #112]	@ (8002028 <HAL_GPIO_EXTI_Callback+0x94>)
- 8001fb8:	781b      	ldrb	r3, [r3, #0]
- 8001fba:	b2db      	uxtb	r3, r3
- 8001fbc:	7afa      	ldrb	r2, [r7, #11]
- 8001fbe:	429a      	cmp	r2, r3
- 8001fc0:	d02c      	beq.n	800201c <HAL_GPIO_EXTI_Callback+0x88>
+ 8002342:	4b1d      	ldr	r3, [pc, #116]	@ (80023b8 <HAL_GPIO_EXTI_Callback+0xa0>)
+ 8002344:	781b      	ldrb	r3, [r3, #0]
+ 8002346:	b2db      	uxtb	r3, r3
+ 8002348:	7afa      	ldrb	r2, [r7, #11]
+ 800234a:	429a      	cmp	r2, r3
+ 800234c:	d02c      	beq.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
     	{
 			if(first_time_state == 1)
- 8001fc2:	4b1a      	ldr	r3, [pc, #104]	@ (800202c <HAL_GPIO_EXTI_Callback+0x98>)
- 8001fc4:	781b      	ldrb	r3, [r3, #0]
- 8001fc6:	b2db      	uxtb	r3, r3
- 8001fc8:	2b01      	cmp	r3, #1
- 8001fca:	d106      	bne.n	8001fda <HAL_GPIO_EXTI_Callback+0x46>
+ 800234e:	4b1b      	ldr	r3, [pc, #108]	@ (80023bc <HAL_GPIO_EXTI_Callback+0xa4>)
+ 8002350:	781b      	ldrb	r3, [r3, #0]
+ 8002352:	b2db      	uxtb	r3, r3
+ 8002354:	2b01      	cmp	r3, #1
+ 8002356:	d106      	bne.n	8002366 <HAL_GPIO_EXTI_Callback+0x4e>
 			{
 				original_pin_state = pin_state;
- 8001fcc:	4a18      	ldr	r2, [pc, #96]	@ (8002030 <HAL_GPIO_EXTI_Callback+0x9c>)
- 8001fce:	7afb      	ldrb	r3, [r7, #11]
- 8001fd0:	7013      	strb	r3, [r2, #0]
+ 8002358:	4a19      	ldr	r2, [pc, #100]	@ (80023c0 <HAL_GPIO_EXTI_Callback+0xa8>)
+ 800235a:	7afb      	ldrb	r3, [r7, #11]
+ 800235c:	7013      	strb	r3, [r2, #0]
 				first_time_state = 0;
- 8001fd2:	4b16      	ldr	r3, [pc, #88]	@ (800202c <HAL_GPIO_EXTI_Callback+0x98>)
- 8001fd4:	2200      	movs	r2, #0
- 8001fd6:	701a      	strb	r2, [r3, #0]
+ 800235e:	4b17      	ldr	r3, [pc, #92]	@ (80023bc <HAL_GPIO_EXTI_Callback+0xa4>)
+ 8002360:	2200      	movs	r2, #0
+ 8002362:	701a      	strb	r2, [r3, #0]
 				last_original_pin = original_pin_state;
 				first_time_state = 1;
 			}
     	}
     }
 }
- 8001fd8:	e020      	b.n	800201c <HAL_GPIO_EXTI_Callback+0x88>
+ 8002364:	e020      	b.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
 			else if(((current_time - last_interrupt_time) > 70U) && (pin_state == original_pin_state))
- 8001fda:	4b16      	ldr	r3, [pc, #88]	@ (8002034 <HAL_GPIO_EXTI_Callback+0xa0>)
- 8001fdc:	681b      	ldr	r3, [r3, #0]
- 8001fde:	68fa      	ldr	r2, [r7, #12]
- 8001fe0:	1ad3      	subs	r3, r2, r3
- 8001fe2:	2b46      	cmp	r3, #70	@ 0x46
- 8001fe4:	d91a      	bls.n	800201c <HAL_GPIO_EXTI_Callback+0x88>
- 8001fe6:	4b12      	ldr	r3, [pc, #72]	@ (8002030 <HAL_GPIO_EXTI_Callback+0x9c>)
- 8001fe8:	781b      	ldrb	r3, [r3, #0]
- 8001fea:	b2db      	uxtb	r3, r3
- 8001fec:	7afa      	ldrb	r2, [r7, #11]
- 8001fee:	429a      	cmp	r2, r3
- 8001ff0:	d114      	bne.n	800201c <HAL_GPIO_EXTI_Callback+0x88>
+ 8002366:	4b17      	ldr	r3, [pc, #92]	@ (80023c4 <HAL_GPIO_EXTI_Callback+0xac>)
+ 8002368:	681b      	ldr	r3, [r3, #0]
+ 800236a:	68fa      	ldr	r2, [r7, #12]
+ 800236c:	1ad3      	subs	r3, r2, r3
+ 800236e:	2b46      	cmp	r3, #70	@ 0x46
+ 8002370:	d91a      	bls.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
+ 8002372:	4b13      	ldr	r3, [pc, #76]	@ (80023c0 <HAL_GPIO_EXTI_Callback+0xa8>)
+ 8002374:	781b      	ldrb	r3, [r3, #0]
+ 8002376:	b2db      	uxtb	r3, r3
+ 8002378:	7afa      	ldrb	r2, [r7, #11]
+ 800237a:	429a      	cmp	r2, r3
+ 800237c:	d114      	bne.n	80023a8 <HAL_GPIO_EXTI_Callback+0x90>
 				if(pin_state == GPIO_PIN_RESET)
- 8001ff2:	7afb      	ldrb	r3, [r7, #11]
- 8001ff4:	2b00      	cmp	r3, #0
- 8001ff6:	d103      	bne.n	8002000 <HAL_GPIO_EXTI_Callback+0x6c>
+ 800237e:	7afb      	ldrb	r3, [r7, #11]
+ 8002380:	2b00      	cmp	r3, #0
+ 8002382:	d103      	bne.n	800238c <HAL_GPIO_EXTI_Callback+0x74>
 					edge_state = FALLING_EDGE;
- 8001ff8:	4b0f      	ldr	r3, [pc, #60]	@ (8002038 <HAL_GPIO_EXTI_Callback+0xa4>)
- 8001ffa:	22ff      	movs	r2, #255	@ 0xff
- 8001ffc:	701a      	strb	r2, [r3, #0]
- 8001ffe:	e002      	b.n	8002006 <HAL_GPIO_EXTI_Callback+0x72>
+ 8002384:	4b10      	ldr	r3, [pc, #64]	@ (80023c8 <HAL_GPIO_EXTI_Callback+0xb0>)
+ 8002386:	22ff      	movs	r2, #255	@ 0xff
+ 8002388:	701a      	strb	r2, [r3, #0]
+ 800238a:	e002      	b.n	8002392 <HAL_GPIO_EXTI_Callback+0x7a>
 					edge_state = RISING_EDGE;
- 8002000:	4b0d      	ldr	r3, [pc, #52]	@ (8002038 <HAL_GPIO_EXTI_Callback+0xa4>)
- 8002002:	2201      	movs	r2, #1
- 8002004:	701a      	strb	r2, [r3, #0]
+ 800238c:	4b0e      	ldr	r3, [pc, #56]	@ (80023c8 <HAL_GPIO_EXTI_Callback+0xb0>)
+ 800238e:	2201      	movs	r2, #1
+ 8002390:	701a      	strb	r2, [r3, #0]
 				last_interrupt_time = current_time;
- 8002006:	4a0b      	ldr	r2, [pc, #44]	@ (8002034 <HAL_GPIO_EXTI_Callback+0xa0>)
- 8002008:	68fb      	ldr	r3, [r7, #12]
- 800200a:	6013      	str	r3, [r2, #0]
+ 8002392:	4a0c      	ldr	r2, [pc, #48]	@ (80023c4 <HAL_GPIO_EXTI_Callback+0xac>)
+ 8002394:	68fb      	ldr	r3, [r7, #12]
+ 8002396:	6013      	str	r3, [r2, #0]
 				last_original_pin = original_pin_state;
- 800200c:	4b08      	ldr	r3, [pc, #32]	@ (8002030 <HAL_GPIO_EXTI_Callback+0x9c>)
- 800200e:	781b      	ldrb	r3, [r3, #0]
- 8002010:	b2da      	uxtb	r2, r3
- 8002012:	4b05      	ldr	r3, [pc, #20]	@ (8002028 <HAL_GPIO_EXTI_Callback+0x94>)
- 8002014:	701a      	strb	r2, [r3, #0]
+ 8002398:	4b09      	ldr	r3, [pc, #36]	@ (80023c0 <HAL_GPIO_EXTI_Callback+0xa8>)
+ 800239a:	781b      	ldrb	r3, [r3, #0]
+ 800239c:	b2da      	uxtb	r2, r3
+ 800239e:	4b06      	ldr	r3, [pc, #24]	@ (80023b8 <HAL_GPIO_EXTI_Callback+0xa0>)
+ 80023a0:	701a      	strb	r2, [r3, #0]
 				first_time_state = 1;
- 8002016:	4b05      	ldr	r3, [pc, #20]	@ (800202c <HAL_GPIO_EXTI_Callback+0x98>)
- 8002018:	2201      	movs	r2, #1
- 800201a:	701a      	strb	r2, [r3, #0]
+ 80023a2:	4b06      	ldr	r3, [pc, #24]	@ (80023bc <HAL_GPIO_EXTI_Callback+0xa4>)
+ 80023a4:	2201      	movs	r2, #1
+ 80023a6:	701a      	strb	r2, [r3, #0]
 }
- 800201c:	bf00      	nop
- 800201e:	3710      	adds	r7, #16
- 8002020:	46bd      	mov	sp, r7
- 8002022:	bd80      	pop	{r7, pc}
- 8002024:	40010c00 	.word	0x40010c00
- 8002028:	20000001 	.word	0x20000001
- 800202c:	20000000 	.word	0x20000000
- 8002030:	200001d0 	.word	0x200001d0
- 8002034:	200001cc 	.word	0x200001cc
- 8002038:	200001d1 	.word	0x200001d1
+ 80023a8:	bf00      	nop
+ 80023aa:	3710      	adds	r7, #16
+ 80023ac:	46bd      	mov	sp, r7
+ 80023ae:	bd80      	pop	{r7, pc}
+ 80023b0:	200006a8 	.word	0x200006a8
+ 80023b4:	40010c00 	.word	0x40010c00
+ 80023b8:	20000001 	.word	0x20000001
+ 80023bc:	20000000 	.word	0x20000000
+ 80023c0:	200005fc 	.word	0x200005fc
+ 80023c4:	200005f8 	.word	0x200005f8
+ 80023c8:	200005fd 	.word	0x200005fd
 
-0800203c <MX_I2C1_Init>:
+080023cc <MX_I2C1_Init>:
 I2C_HandleTypeDef hi2c1;
 I2C_HandleTypeDef hi2c2;
 
 /* I2C1 init function */
 void MX_I2C1_Init(void)
 {
- 800203c:	b580      	push	{r7, lr}
- 800203e:	af00      	add	r7, sp, #0
+ 80023cc:	b580      	push	{r7, lr}
+ 80023ce:	af00      	add	r7, sp, #0
   /* USER CODE END I2C1_Init 0 */
 
   /* USER CODE BEGIN I2C1_Init 1 */
 
   /* USER CODE END I2C1_Init 1 */
   hi2c1.Instance = I2C1;
- 8002040:	4b12      	ldr	r3, [pc, #72]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002042:	4a13      	ldr	r2, [pc, #76]	@ (8002090 <MX_I2C1_Init+0x54>)
- 8002044:	601a      	str	r2, [r3, #0]
+ 80023d0:	4b12      	ldr	r3, [pc, #72]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023d2:	4a13      	ldr	r2, [pc, #76]	@ (8002420 <MX_I2C1_Init+0x54>)
+ 80023d4:	601a      	str	r2, [r3, #0]
   hi2c1.Init.ClockSpeed = 100000;
- 8002046:	4b11      	ldr	r3, [pc, #68]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002048:	4a12      	ldr	r2, [pc, #72]	@ (8002094 <MX_I2C1_Init+0x58>)
- 800204a:	605a      	str	r2, [r3, #4]
+ 80023d6:	4b11      	ldr	r3, [pc, #68]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023d8:	4a12      	ldr	r2, [pc, #72]	@ (8002424 <MX_I2C1_Init+0x58>)
+ 80023da:	605a      	str	r2, [r3, #4]
   hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
- 800204c:	4b0f      	ldr	r3, [pc, #60]	@ (800208c <MX_I2C1_Init+0x50>)
- 800204e:	2200      	movs	r2, #0
- 8002050:	609a      	str	r2, [r3, #8]
+ 80023dc:	4b0f      	ldr	r3, [pc, #60]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023de:	2200      	movs	r2, #0
+ 80023e0:	609a      	str	r2, [r3, #8]
   hi2c1.Init.OwnAddress1 = 0;
- 8002052:	4b0e      	ldr	r3, [pc, #56]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002054:	2200      	movs	r2, #0
- 8002056:	60da      	str	r2, [r3, #12]
+ 80023e2:	4b0e      	ldr	r3, [pc, #56]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023e4:	2200      	movs	r2, #0
+ 80023e6:	60da      	str	r2, [r3, #12]
   hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
- 8002058:	4b0c      	ldr	r3, [pc, #48]	@ (800208c <MX_I2C1_Init+0x50>)
- 800205a:	f44f 4280 	mov.w	r2, #16384	@ 0x4000
- 800205e:	611a      	str	r2, [r3, #16]
+ 80023e8:	4b0c      	ldr	r3, [pc, #48]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023ea:	f44f 4280 	mov.w	r2, #16384	@ 0x4000
+ 80023ee:	611a      	str	r2, [r3, #16]
   hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
- 8002060:	4b0a      	ldr	r3, [pc, #40]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002062:	2200      	movs	r2, #0
- 8002064:	615a      	str	r2, [r3, #20]
+ 80023f0:	4b0a      	ldr	r3, [pc, #40]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023f2:	2200      	movs	r2, #0
+ 80023f4:	615a      	str	r2, [r3, #20]
   hi2c1.Init.OwnAddress2 = 0;
- 8002066:	4b09      	ldr	r3, [pc, #36]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002068:	2200      	movs	r2, #0
- 800206a:	619a      	str	r2, [r3, #24]
+ 80023f6:	4b09      	ldr	r3, [pc, #36]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023f8:	2200      	movs	r2, #0
+ 80023fa:	619a      	str	r2, [r3, #24]
   hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
- 800206c:	4b07      	ldr	r3, [pc, #28]	@ (800208c <MX_I2C1_Init+0x50>)
- 800206e:	2200      	movs	r2, #0
- 8002070:	61da      	str	r2, [r3, #28]
+ 80023fc:	4b07      	ldr	r3, [pc, #28]	@ (800241c <MX_I2C1_Init+0x50>)
+ 80023fe:	2200      	movs	r2, #0
+ 8002400:	61da      	str	r2, [r3, #28]
   hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
- 8002072:	4b06      	ldr	r3, [pc, #24]	@ (800208c <MX_I2C1_Init+0x50>)
- 8002074:	2200      	movs	r2, #0
- 8002076:	621a      	str	r2, [r3, #32]
+ 8002402:	4b06      	ldr	r3, [pc, #24]	@ (800241c <MX_I2C1_Init+0x50>)
+ 8002404:	2200      	movs	r2, #0
+ 8002406:	621a      	str	r2, [r3, #32]
   if (HAL_I2C_Init(&hi2c1) != HAL_OK)
- 8002078:	4804      	ldr	r0, [pc, #16]	@ (800208c <MX_I2C1_Init+0x50>)
- 800207a:	f001 fb31 	bl	80036e0 <HAL_I2C_Init>
- 800207e:	4603      	mov	r3, r0
- 8002080:	2b00      	cmp	r3, #0
- 8002082:	d001      	beq.n	8002088 <MX_I2C1_Init+0x4c>
+ 8002408:	4804      	ldr	r0, [pc, #16]	@ (800241c <MX_I2C1_Init+0x50>)
+ 800240a:	f002 fb7d 	bl	8004b08 <HAL_I2C_Init>
+ 800240e:	4603      	mov	r3, r0
+ 8002410:	2b00      	cmp	r3, #0
+ 8002412:	d001      	beq.n	8002418 <MX_I2C1_Init+0x4c>
   {
     Error_Handler();
- 8002084:	f000 faf4 	bl	8002670 <Error_Handler>
+ 8002414:	f000 fc7c 	bl	8002d10 <Error_Handler>
   }
   /* USER CODE BEGIN I2C1_Init 2 */
 
   /* USER CODE END I2C1_Init 2 */
 
 }
- 8002088:	bf00      	nop
- 800208a:	bd80      	pop	{r7, pc}
- 800208c:	200001d4 	.word	0x200001d4
- 8002090:	40005400 	.word	0x40005400
- 8002094:	000186a0 	.word	0x000186a0
+ 8002418:	bf00      	nop
+ 800241a:	bd80      	pop	{r7, pc}
+ 800241c:	20000600 	.word	0x20000600
+ 8002420:	40005400 	.word	0x40005400
+ 8002424:	000186a0 	.word	0x000186a0
 
-08002098 <MX_I2C2_Init>:
+08002428 <MX_I2C2_Init>:
 /* I2C2 init function */
 void MX_I2C2_Init(void)
 {
- 8002098:	b580      	push	{r7, lr}
- 800209a:	af00      	add	r7, sp, #0
+ 8002428:	b580      	push	{r7, lr}
+ 800242a:	af00      	add	r7, sp, #0
   /* USER CODE END I2C2_Init 0 */
 
   /* USER CODE BEGIN I2C2_Init 1 */
 
   /* USER CODE END I2C2_Init 1 */
   hi2c2.Instance = I2C2;
- 800209c:	4b12      	ldr	r3, [pc, #72]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 800209e:	4a13      	ldr	r2, [pc, #76]	@ (80020ec <MX_I2C2_Init+0x54>)
- 80020a0:	601a      	str	r2, [r3, #0]
+ 800242c:	4b12      	ldr	r3, [pc, #72]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 800242e:	4a13      	ldr	r2, [pc, #76]	@ (800247c <MX_I2C2_Init+0x54>)
+ 8002430:	601a      	str	r2, [r3, #0]
   hi2c2.Init.ClockSpeed = 100000;
- 80020a2:	4b11      	ldr	r3, [pc, #68]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020a4:	4a12      	ldr	r2, [pc, #72]	@ (80020f0 <MX_I2C2_Init+0x58>)
- 80020a6:	605a      	str	r2, [r3, #4]
+ 8002432:	4b11      	ldr	r3, [pc, #68]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002434:	4a12      	ldr	r2, [pc, #72]	@ (8002480 <MX_I2C2_Init+0x58>)
+ 8002436:	605a      	str	r2, [r3, #4]
   hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
- 80020a8:	4b0f      	ldr	r3, [pc, #60]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020aa:	2200      	movs	r2, #0
- 80020ac:	609a      	str	r2, [r3, #8]
+ 8002438:	4b0f      	ldr	r3, [pc, #60]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 800243a:	2200      	movs	r2, #0
+ 800243c:	609a      	str	r2, [r3, #8]
   hi2c2.Init.OwnAddress1 = 0;
- 80020ae:	4b0e      	ldr	r3, [pc, #56]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020b0:	2200      	movs	r2, #0
- 80020b2:	60da      	str	r2, [r3, #12]
+ 800243e:	4b0e      	ldr	r3, [pc, #56]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002440:	2200      	movs	r2, #0
+ 8002442:	60da      	str	r2, [r3, #12]
   hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
- 80020b4:	4b0c      	ldr	r3, [pc, #48]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020b6:	f44f 4280 	mov.w	r2, #16384	@ 0x4000
- 80020ba:	611a      	str	r2, [r3, #16]
+ 8002444:	4b0c      	ldr	r3, [pc, #48]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002446:	f44f 4280 	mov.w	r2, #16384	@ 0x4000
+ 800244a:	611a      	str	r2, [r3, #16]
   hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
- 80020bc:	4b0a      	ldr	r3, [pc, #40]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020be:	2200      	movs	r2, #0
- 80020c0:	615a      	str	r2, [r3, #20]
+ 800244c:	4b0a      	ldr	r3, [pc, #40]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 800244e:	2200      	movs	r2, #0
+ 8002450:	615a      	str	r2, [r3, #20]
   hi2c2.Init.OwnAddress2 = 0;
- 80020c2:	4b09      	ldr	r3, [pc, #36]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020c4:	2200      	movs	r2, #0
- 80020c6:	619a      	str	r2, [r3, #24]
+ 8002452:	4b09      	ldr	r3, [pc, #36]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002454:	2200      	movs	r2, #0
+ 8002456:	619a      	str	r2, [r3, #24]
   hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
- 80020c8:	4b07      	ldr	r3, [pc, #28]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020ca:	2200      	movs	r2, #0
- 80020cc:	61da      	str	r2, [r3, #28]
+ 8002458:	4b07      	ldr	r3, [pc, #28]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 800245a:	2200      	movs	r2, #0
+ 800245c:	61da      	str	r2, [r3, #28]
   hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
- 80020ce:	4b06      	ldr	r3, [pc, #24]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020d0:	2200      	movs	r2, #0
- 80020d2:	621a      	str	r2, [r3, #32]
+ 800245e:	4b06      	ldr	r3, [pc, #24]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002460:	2200      	movs	r2, #0
+ 8002462:	621a      	str	r2, [r3, #32]
   if (HAL_I2C_Init(&hi2c2) != HAL_OK)
- 80020d4:	4804      	ldr	r0, [pc, #16]	@ (80020e8 <MX_I2C2_Init+0x50>)
- 80020d6:	f001 fb03 	bl	80036e0 <HAL_I2C_Init>
- 80020da:	4603      	mov	r3, r0
- 80020dc:	2b00      	cmp	r3, #0
- 80020de:	d001      	beq.n	80020e4 <MX_I2C2_Init+0x4c>
+ 8002464:	4804      	ldr	r0, [pc, #16]	@ (8002478 <MX_I2C2_Init+0x50>)
+ 8002466:	f002 fb4f 	bl	8004b08 <HAL_I2C_Init>
+ 800246a:	4603      	mov	r3, r0
+ 800246c:	2b00      	cmp	r3, #0
+ 800246e:	d001      	beq.n	8002474 <MX_I2C2_Init+0x4c>
   {
     Error_Handler();
- 80020e0:	f000 fac6 	bl	8002670 <Error_Handler>
+ 8002470:	f000 fc4e 	bl	8002d10 <Error_Handler>
   }
   /* USER CODE BEGIN I2C2_Init 2 */
 
   /* USER CODE END I2C2_Init 2 */
 
 }
- 80020e4:	bf00      	nop
- 80020e6:	bd80      	pop	{r7, pc}
- 80020e8:	20000228 	.word	0x20000228
- 80020ec:	40005800 	.word	0x40005800
- 80020f0:	000186a0 	.word	0x000186a0
+ 8002474:	bf00      	nop
+ 8002476:	bd80      	pop	{r7, pc}
+ 8002478:	20000654 	.word	0x20000654
+ 800247c:	40005800 	.word	0x40005800
+ 8002480:	000186a0 	.word	0x000186a0
 
-080020f4 <HAL_I2C_MspInit>:
+08002484 <HAL_I2C_MspInit>:
 
 void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
 {
- 80020f4:	b580      	push	{r7, lr}
- 80020f6:	b08a      	sub	sp, #40	@ 0x28
- 80020f8:	af00      	add	r7, sp, #0
- 80020fa:	6078      	str	r0, [r7, #4]
+ 8002484:	b580      	push	{r7, lr}
+ 8002486:	b08a      	sub	sp, #40	@ 0x28
+ 8002488:	af00      	add	r7, sp, #0
+ 800248a:	6078      	str	r0, [r7, #4]
 
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80020fc:	f107 0318 	add.w	r3, r7, #24
- 8002100:	2200      	movs	r2, #0
- 8002102:	601a      	str	r2, [r3, #0]
- 8002104:	605a      	str	r2, [r3, #4]
- 8002106:	609a      	str	r2, [r3, #8]
- 8002108:	60da      	str	r2, [r3, #12]
+ 800248c:	f107 0318 	add.w	r3, r7, #24
+ 8002490:	2200      	movs	r2, #0
+ 8002492:	601a      	str	r2, [r3, #0]
+ 8002494:	605a      	str	r2, [r3, #4]
+ 8002496:	609a      	str	r2, [r3, #8]
+ 8002498:	60da      	str	r2, [r3, #12]
   if(i2cHandle->Instance==I2C1)
- 800210a:	687b      	ldr	r3, [r7, #4]
- 800210c:	681b      	ldr	r3, [r3, #0]
- 800210e:	4a2b      	ldr	r2, [pc, #172]	@ (80021bc <HAL_I2C_MspInit+0xc8>)
- 8002110:	4293      	cmp	r3, r2
- 8002112:	d124      	bne.n	800215e <HAL_I2C_MspInit+0x6a>
+ 800249a:	687b      	ldr	r3, [r7, #4]
+ 800249c:	681b      	ldr	r3, [r3, #0]
+ 800249e:	4a2b      	ldr	r2, [pc, #172]	@ (800254c <HAL_I2C_MspInit+0xc8>)
+ 80024a0:	4293      	cmp	r3, r2
+ 80024a2:	d124      	bne.n	80024ee <HAL_I2C_MspInit+0x6a>
   {
   /* USER CODE BEGIN I2C1_MspInit 0 */
 
   /* USER CODE END I2C1_MspInit 0 */
 
     __HAL_RCC_GPIOB_CLK_ENABLE();
- 8002114:	4b2a      	ldr	r3, [pc, #168]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 8002116:	699b      	ldr	r3, [r3, #24]
- 8002118:	4a29      	ldr	r2, [pc, #164]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 800211a:	f043 0308 	orr.w	r3, r3, #8
- 800211e:	6193      	str	r3, [r2, #24]
- 8002120:	4b27      	ldr	r3, [pc, #156]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 8002122:	699b      	ldr	r3, [r3, #24]
- 8002124:	f003 0308 	and.w	r3, r3, #8
- 8002128:	617b      	str	r3, [r7, #20]
- 800212a:	697b      	ldr	r3, [r7, #20]
+ 80024a4:	4b2a      	ldr	r3, [pc, #168]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024a6:	699b      	ldr	r3, [r3, #24]
+ 80024a8:	4a29      	ldr	r2, [pc, #164]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024aa:	f043 0308 	orr.w	r3, r3, #8
+ 80024ae:	6193      	str	r3, [r2, #24]
+ 80024b0:	4b27      	ldr	r3, [pc, #156]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024b2:	699b      	ldr	r3, [r3, #24]
+ 80024b4:	f003 0308 	and.w	r3, r3, #8
+ 80024b8:	617b      	str	r3, [r7, #20]
+ 80024ba:	697b      	ldr	r3, [r7, #20]
     /**I2C1 GPIO Configuration
     PB6     ------> I2C1_SCL
     PB7     ------> I2C1_SDA
     */
     GPIO_InitStruct.Pin = I2C1_SCL_PH_Pin|I2C1_SDA_PH_Pin;
- 800212c:	23c0      	movs	r3, #192	@ 0xc0
- 800212e:	61bb      	str	r3, [r7, #24]
+ 80024bc:	23c0      	movs	r3, #192	@ 0xc0
+ 80024be:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
- 8002130:	2312      	movs	r3, #18
- 8002132:	61fb      	str	r3, [r7, #28]
+ 80024c0:	2312      	movs	r3, #18
+ 80024c2:	61fb      	str	r3, [r7, #28]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8002134:	2302      	movs	r3, #2
- 8002136:	627b      	str	r3, [r7, #36]	@ 0x24
+ 80024c4:	2302      	movs	r3, #2
+ 80024c6:	627b      	str	r3, [r7, #36]	@ 0x24
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8002138:	f107 0318 	add.w	r3, r7, #24
- 800213c:	4619      	mov	r1, r3
- 800213e:	4821      	ldr	r0, [pc, #132]	@ (80021c4 <HAL_I2C_MspInit+0xd0>)
- 8002140:	f001 f902 	bl	8003348 <HAL_GPIO_Init>
+ 80024c8:	f107 0318 	add.w	r3, r7, #24
+ 80024cc:	4619      	mov	r1, r3
+ 80024ce:	4821      	ldr	r0, [pc, #132]	@ (8002554 <HAL_I2C_MspInit+0xd0>)
+ 80024d0:	f002 f94e 	bl	8004770 <HAL_GPIO_Init>
 
     /* I2C1 clock enable */
     __HAL_RCC_I2C1_CLK_ENABLE();
- 8002144:	4b1e      	ldr	r3, [pc, #120]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 8002146:	69db      	ldr	r3, [r3, #28]
- 8002148:	4a1d      	ldr	r2, [pc, #116]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 800214a:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
- 800214e:	61d3      	str	r3, [r2, #28]
- 8002150:	4b1b      	ldr	r3, [pc, #108]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 8002152:	69db      	ldr	r3, [r3, #28]
- 8002154:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
- 8002158:	613b      	str	r3, [r7, #16]
- 800215a:	693b      	ldr	r3, [r7, #16]
+ 80024d4:	4b1e      	ldr	r3, [pc, #120]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024d6:	69db      	ldr	r3, [r3, #28]
+ 80024d8:	4a1d      	ldr	r2, [pc, #116]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024da:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
+ 80024de:	61d3      	str	r3, [r2, #28]
+ 80024e0:	4b1b      	ldr	r3, [pc, #108]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024e2:	69db      	ldr	r3, [r3, #28]
+ 80024e4:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
+ 80024e8:	613b      	str	r3, [r7, #16]
+ 80024ea:	693b      	ldr	r3, [r7, #16]
     __HAL_RCC_I2C2_CLK_ENABLE();
   /* USER CODE BEGIN I2C2_MspInit 1 */
 
   /* USER CODE END I2C2_MspInit 1 */
   }
 }
- 800215c:	e029      	b.n	80021b2 <HAL_I2C_MspInit+0xbe>
+ 80024ec:	e029      	b.n	8002542 <HAL_I2C_MspInit+0xbe>
   else if(i2cHandle->Instance==I2C2)
- 800215e:	687b      	ldr	r3, [r7, #4]
- 8002160:	681b      	ldr	r3, [r3, #0]
- 8002162:	4a19      	ldr	r2, [pc, #100]	@ (80021c8 <HAL_I2C_MspInit+0xd4>)
- 8002164:	4293      	cmp	r3, r2
- 8002166:	d124      	bne.n	80021b2 <HAL_I2C_MspInit+0xbe>
+ 80024ee:	687b      	ldr	r3, [r7, #4]
+ 80024f0:	681b      	ldr	r3, [r3, #0]
+ 80024f2:	4a19      	ldr	r2, [pc, #100]	@ (8002558 <HAL_I2C_MspInit+0xd4>)
+ 80024f4:	4293      	cmp	r3, r2
+ 80024f6:	d124      	bne.n	8002542 <HAL_I2C_MspInit+0xbe>
     __HAL_RCC_GPIOB_CLK_ENABLE();
- 8002168:	4b15      	ldr	r3, [pc, #84]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 800216a:	699b      	ldr	r3, [r3, #24]
- 800216c:	4a14      	ldr	r2, [pc, #80]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 800216e:	f043 0308 	orr.w	r3, r3, #8
- 8002172:	6193      	str	r3, [r2, #24]
- 8002174:	4b12      	ldr	r3, [pc, #72]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 8002176:	699b      	ldr	r3, [r3, #24]
- 8002178:	f003 0308 	and.w	r3, r3, #8
- 800217c:	60fb      	str	r3, [r7, #12]
- 800217e:	68fb      	ldr	r3, [r7, #12]
+ 80024f8:	4b15      	ldr	r3, [pc, #84]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024fa:	699b      	ldr	r3, [r3, #24]
+ 80024fc:	4a14      	ldr	r2, [pc, #80]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 80024fe:	f043 0308 	orr.w	r3, r3, #8
+ 8002502:	6193      	str	r3, [r2, #24]
+ 8002504:	4b12      	ldr	r3, [pc, #72]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 8002506:	699b      	ldr	r3, [r3, #24]
+ 8002508:	f003 0308 	and.w	r3, r3, #8
+ 800250c:	60fb      	str	r3, [r7, #12]
+ 800250e:	68fb      	ldr	r3, [r7, #12]
     GPIO_InitStruct.Pin = I2C2_SCL_CE_Pin|I2C2_SDA_CE_Pin;
- 8002180:	f44f 6340 	mov.w	r3, #3072	@ 0xc00
- 8002184:	61bb      	str	r3, [r7, #24]
+ 8002510:	f44f 6340 	mov.w	r3, #3072	@ 0xc00
+ 8002514:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
- 8002186:	2312      	movs	r3, #18
- 8002188:	61fb      	str	r3, [r7, #28]
+ 8002516:	2312      	movs	r3, #18
+ 8002518:	61fb      	str	r3, [r7, #28]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800218a:	2302      	movs	r3, #2
- 800218c:	627b      	str	r3, [r7, #36]	@ 0x24
+ 800251a:	2302      	movs	r3, #2
+ 800251c:	627b      	str	r3, [r7, #36]	@ 0x24
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 800218e:	f107 0318 	add.w	r3, r7, #24
- 8002192:	4619      	mov	r1, r3
- 8002194:	480b      	ldr	r0, [pc, #44]	@ (80021c4 <HAL_I2C_MspInit+0xd0>)
- 8002196:	f001 f8d7 	bl	8003348 <HAL_GPIO_Init>
+ 800251e:	f107 0318 	add.w	r3, r7, #24
+ 8002522:	4619      	mov	r1, r3
+ 8002524:	480b      	ldr	r0, [pc, #44]	@ (8002554 <HAL_I2C_MspInit+0xd0>)
+ 8002526:	f002 f923 	bl	8004770 <HAL_GPIO_Init>
     __HAL_RCC_I2C2_CLK_ENABLE();
- 800219a:	4b09      	ldr	r3, [pc, #36]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 800219c:	69db      	ldr	r3, [r3, #28]
- 800219e:	4a08      	ldr	r2, [pc, #32]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 80021a0:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
- 80021a4:	61d3      	str	r3, [r2, #28]
- 80021a6:	4b06      	ldr	r3, [pc, #24]	@ (80021c0 <HAL_I2C_MspInit+0xcc>)
- 80021a8:	69db      	ldr	r3, [r3, #28]
- 80021aa:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
- 80021ae:	60bb      	str	r3, [r7, #8]
- 80021b0:	68bb      	ldr	r3, [r7, #8]
+ 800252a:	4b09      	ldr	r3, [pc, #36]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 800252c:	69db      	ldr	r3, [r3, #28]
+ 800252e:	4a08      	ldr	r2, [pc, #32]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 8002530:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
+ 8002534:	61d3      	str	r3, [r2, #28]
+ 8002536:	4b06      	ldr	r3, [pc, #24]	@ (8002550 <HAL_I2C_MspInit+0xcc>)
+ 8002538:	69db      	ldr	r3, [r3, #28]
+ 800253a:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 800253e:	60bb      	str	r3, [r7, #8]
+ 8002540:	68bb      	ldr	r3, [r7, #8]
 }
- 80021b2:	bf00      	nop
- 80021b4:	3728      	adds	r7, #40	@ 0x28
- 80021b6:	46bd      	mov	sp, r7
- 80021b8:	bd80      	pop	{r7, pc}
- 80021ba:	bf00      	nop
- 80021bc:	40005400 	.word	0x40005400
- 80021c0:	40021000 	.word	0x40021000
- 80021c4:	40010c00 	.word	0x40010c00
- 80021c8:	40005800 	.word	0x40005800
+ 8002542:	bf00      	nop
+ 8002544:	3728      	adds	r7, #40	@ 0x28
+ 8002546:	46bd      	mov	sp, r7
+ 8002548:	bd80      	pop	{r7, pc}
+ 800254a:	bf00      	nop
+ 800254c:	40005400 	.word	0x40005400
+ 8002550:	40021000 	.word	0x40021000
+ 8002554:	40010c00 	.word	0x40010c00
+ 8002558:	40005800 	.word	0x40005800
+ 800255c:	00000000 	.word	0x00000000
 
-080021cc <main>:
+08002560 <main>:
 /**
   * @brief  The application entry point.
   * @retval int
   */
 int main(void)
 {
- 80021cc:	b580      	push	{r7, lr}
- 80021ce:	b08e      	sub	sp, #56	@ 0x38
- 80021d0:	af00      	add	r7, sp, #0
+ 8002560:	b580      	push	{r7, lr}
+ 8002562:	b08c      	sub	sp, #48	@ 0x30
+ 8002564:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN 1 */
 	HAL_StatusTypeDef status0,status1;
 
 
 	   // Variables to store previous LED states
 	   uint8_t previous_green_state = 0;
- 80021d2:	2300      	movs	r3, #0
- 80021d4:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+ 8002566:	2300      	movs	r3, #0
+ 8002568:	f887 302a 	strb.w	r3, [r7, #42]	@ 0x2a
 	   uint8_t previous_red_state = 0;
- 80021d8:	2300      	movs	r3, #0
- 80021da:	f887 3032 	strb.w	r3, [r7, #50]	@ 0x32
+ 800256c:	2300      	movs	r3, #0
+ 800256e:	f887 3029 	strb.w	r3, [r7, #41]	@ 0x29
 
 	   // Variables for timing
 	   uint32_t previous_millis_green = 0;
- 80021de:	2300      	movs	r3, #0
- 80021e0:	637b      	str	r3, [r7, #52]	@ 0x34
+ 8002572:	2300      	movs	r3, #0
+ 8002574:	62fb      	str	r3, [r7, #44]	@ 0x2c
 	   uint32_t previous_millis_red = 0;
- 80021e2:	2300      	movs	r3, #0
- 80021e4:	62fb      	str	r3, [r7, #44]	@ 0x2c
-	   uint32_t current_millis;
+ 8002576:	2300      	movs	r3, #0
+ 8002578:	627b      	str	r3, [r7, #36]	@ 0x24
+
+
 
-	float temperature_RTD, admittance_EC;
 
 	/*! Temporary variables */
-	char  tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
- 80021e6:	1d3b      	adds	r3, r7, #4
- 80021e8:	2200      	movs	r2, #0
- 80021ea:	601a      	str	r2, [r3, #0]
- 80021ec:	605a      	str	r2, [r3, #4]
- 80021ee:	811a      	strh	r2, [r3, #8]
-	long double         tempValue = 0;
- 80021f0:	f04f 0200 	mov.w	r2, #0
- 80021f4:	f04f 0300 	mov.w	r3, #0
- 80021f8:	e9c7 2308 	strd	r2, r3, [r7, #32]
+	uint8_t  tempString[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ 800257a:	1d3b      	adds	r3, r7, #4
+ 800257c:	2200      	movs	r2, #0
+ 800257e:	601a      	str	r2, [r3, #0]
+ 8002580:	605a      	str	r2, [r3, #4]
+ 8002582:	811a      	strh	r2, [r3, #8]
   /* USER CODE END 1 */
 
   /* MCU Configuration--------------------------------------------------------*/
 
   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
- 80021fc:	f000 fc4c 	bl	8002a98 <HAL_Init>
+ 8002584:	f000 fe4e 	bl	8003224 <HAL_Init>
   /* USER CODE BEGIN Init */
 
   /* USER CODE END Init */
 
   /* Configure the system clock */
   SystemClock_Config();
- 8002200:	f000 f910 	bl	8002424 <SystemClock_Config>
+ 8002588:	f000 fa44 	bl	8002a14 <SystemClock_Config>
   /* USER CODE BEGIN SysInit */
 
   /* USER CODE END SysInit */
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
- 8002204:	f7ff fe10 	bl	8001e28 <MX_GPIO_Init>
+ 800258c:	f7ff fe0e 	bl	80021ac <MX_GPIO_Init>
+  MX_DMA_Init();
+ 8002590:	f7ff fd74 	bl	800207c <MX_DMA_Init>
   MX_ADC1_Init();
- 8002208:	f7ff fb8c 	bl	8001924 <MX_ADC1_Init>
+ 8002594:	f7ff fa80 	bl	8001a98 <MX_ADC1_Init>
   MX_ADC2_Init();
- 800220c:	f7ff fbc8 	bl	80019a0 <MX_ADC2_Init>
+ 8002598:	f7ff facc 	bl	8001b34 <MX_ADC2_Init>
   MX_I2C1_Init();
- 8002210:	f7ff ff14 	bl	800203c <MX_I2C1_Init>
+ 800259c:	f7ff ff16 	bl	80023cc <MX_I2C1_Init>
   MX_I2C2_Init();
- 8002214:	f7ff ff40 	bl	8002098 <MX_I2C2_Init>
+ 80025a0:	f7ff ff42 	bl	8002428 <MX_I2C2_Init>
   MX_USART1_UART_Init();
- 8002218:	f000 fb9a 	bl	8002950 <MX_USART1_UART_Init>
+ 80025a4:	f000 fd9a 	bl	80030dc <MX_USART1_UART_Init>
+  MX_TIM3_Init();
+ 80025a8:	f000 fd2c 	bl	8003004 <MX_TIM3_Init>
   /* USER CODE BEGIN 2 */
 
+  Flash_Load_Page(&flash_data);
+ 80025ac:	48c2      	ldr	r0, [pc, #776]	@ (80028b8 <main+0x358>)
+ 80025ae:	f7ff fddd 	bl	800216c <Flash_Load_Page>
+
+  //TempSensor_Init(&hadc1);
+
+
+  HAL_TIM_Base_Start(&htim3);
+ 80025b2:	48c2      	ldr	r0, [pc, #776]	@ (80028bc <main+0x35c>)
+ 80025b4:	f004 f8aa 	bl	800670c <HAL_TIM_Base_Start>
+  HAL_ADCEx_Calibration_Start(&hadc1);
+ 80025b8:	48c1      	ldr	r0, [pc, #772]	@ (80028c0 <main+0x360>)
+ 80025ba:	f001 fa7b 	bl	8003ab4 <HAL_ADCEx_Calibration_Start>
+  HAL_ADC_Start_DMA(&hadc1, (uint32_t*)AD_RES, 2);   // Start ADC Conversion
+ 80025be:	2202      	movs	r2, #2
+ 80025c0:	49c0      	ldr	r1, [pc, #768]	@ (80028c4 <main+0x364>)
+ 80025c2:	48bf      	ldr	r0, [pc, #764]	@ (80028c0 <main+0x360>)
+ 80025c4:	f000 ff8c 	bl	80034e0 <HAL_ADC_Start_DMA>
+
   digital_outputs_init();
- 800221c:	f7ff fdc2 	bl	8001da4 <digital_outputs_init>
+ 80025c8:	f7ff fd16 	bl	8001ff8 <digital_outputs_init>
 
   // Initialize RS-485 driver
    rs485_init();
- 8002220:	f000 fa38 	bl	8002694 <rs485_init>
+ 80025cc:	f000 fbb2 	bl	8002d34 <rs485_init>
 
    ADS1015(&i2c, &hi2c1, ADS_ADDR_GND);
- 8002224:	2248      	movs	r2, #72	@ 0x48
- 8002226:	4974      	ldr	r1, [pc, #464]	@ (80023f8 <main+0x22c>)
- 8002228:	4874      	ldr	r0, [pc, #464]	@ (80023fc <main+0x230>)
- 800222a:	f7ff fca8 	bl	8001b7e <ADS1015>
+ 80025d0:	2248      	movs	r2, #72	@ 0x48
+ 80025d2:	49bd      	ldr	r1, [pc, #756]	@ (80028c8 <main+0x368>)
+ 80025d4:	48bd      	ldr	r0, [pc, #756]	@ (80028cc <main+0x36c>)
+ 80025d6:	f7ff fbc8 	bl	8001d6a <ADS1015>
    ADSsetGain(&i2c, GAIN_SIXTEEN);
- 800222e:	f44f 6120 	mov.w	r1, #2560	@ 0xa00
- 8002232:	4872      	ldr	r0, [pc, #456]	@ (80023fc <main+0x230>)
- 8002234:	f7ff fcc1 	bl	8001bba <ADSsetGain>
+ 80025da:	f44f 6120 	mov.w	r1, #2560	@ 0xa00
+ 80025de:	48bb      	ldr	r0, [pc, #748]	@ (80028cc <main+0x36c>)
+ 80025e0:	f7ff fbe1 	bl	8001da6 <ADSsetGain>
 
 	// Start CE and RTD Measurement
 	AD5934_Init();
- 8002238:	f7fe fe28 	bl	8000e8c <AD5934_Init>
-   while (1)
-   {
+ 80025e4:	f7fe fe14 	bl	8001210 <AD5934_Init>
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+
+	if(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET)
+ 80025e8:	2108      	movs	r1, #8
+ 80025ea:	48b9      	ldr	r0, [pc, #740]	@ (80028d0 <main+0x370>)
+ 80025ec:	f002 fa44 	bl	8004a78 <HAL_GPIO_ReadPin>
+ 80025f0:	4603      	mov	r3, r0
+ 80025f2:	2b00      	cmp	r3, #0
+ 80025f4:	d167      	bne.n	80026c6 <main+0x166>
+	{
+		main_state = STATE_SETUP_CALIBRATION;
+ 80025f6:	4bb7      	ldr	r3, [pc, #732]	@ (80028d4 <main+0x374>)
+ 80025f8:	2201      	movs	r2, #1
+ 80025fa:	701a      	strb	r2, [r3, #0]
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
+ 80025fc:	2201      	movs	r2, #1
+ 80025fe:	2110      	movs	r1, #16
+ 8002600:	48b3      	ldr	r0, [pc, #716]	@ (80028d0 <main+0x370>)
+ 8002602:	f002 fa50 	bl	8004aa6 <HAL_GPIO_WritePin>
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
+ 8002606:	2200      	movs	r2, #0
+ 8002608:	2120      	movs	r1, #32
+ 800260a:	48b1      	ldr	r0, [pc, #708]	@ (80028d0 <main+0x370>)
+ 800260c:	f002 fa4b 	bl	8004aa6 <HAL_GPIO_WritePin>
+
+		for(i=0;i<32;i++)
+ 8002610:	2300      	movs	r3, #0
+ 8002612:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 8002616:	e011      	b.n	800263c <main+0xdc>
+		{
+			flash_data.temperature_value = temperature_RTD;
+ 8002618:	4aa7      	ldr	r2, [pc, #668]	@ (80028b8 <main+0x358>)
+ 800261a:	6a3b      	ldr	r3, [r7, #32]
+ 800261c:	6153      	str	r3, [r2, #20]
+			flash_data.ph4_value = ADSCalculate_ph_Volts();
+ 800261e:	f7ff fc0f 	bl	8001e40 <ADSCalculate_ph_Volts>
+ 8002622:	4603      	mov	r3, r0
+ 8002624:	4aa4      	ldr	r2, [pc, #656]	@ (80028b8 <main+0x358>)
+ 8002626:	6053      	str	r3, [r2, #4]
+			flash_data.ec1413_value = AD5934_GetImpedance();
+ 8002628:	f7ff f846 	bl	80016b8 <AD5934_GetImpedance>
+ 800262c:	4603      	mov	r3, r0
+ 800262e:	4aa2      	ldr	r2, [pc, #648]	@ (80028b8 <main+0x358>)
+ 8002630:	60d3      	str	r3, [r2, #12]
+		for(i=0;i<32;i++)
+ 8002632:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002636:	3301      	adds	r3, #1
+ 8002638:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 800263c:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002640:	2b1f      	cmp	r3, #31
+ 8002642:	d9e9      	bls.n	8002618 <main+0xb8>
+		}
+
+
+		while(HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_3) == GPIO_PIN_RESET);
+ 8002644:	bf00      	nop
+ 8002646:	2108      	movs	r1, #8
+ 8002648:	48a1      	ldr	r0, [pc, #644]	@ (80028d0 <main+0x370>)
+ 800264a:	f002 fa15 	bl	8004a78 <HAL_GPIO_ReadPin>
+ 800264e:	4603      	mov	r3, r0
+ 8002650:	2b00      	cmp	r3, #0
+ 8002652:	d0f8      	beq.n	8002646 <main+0xe6>
+		HAL_Delay(500);
+ 8002654:	f44f 70fa 	mov.w	r0, #500	@ 0x1f4
+ 8002658:	f000 fe46 	bl	80032e8 <HAL_Delay>
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
+ 800265c:	2200      	movs	r2, #0
+ 800265e:	2110      	movs	r1, #16
+ 8002660:	489b      	ldr	r0, [pc, #620]	@ (80028d0 <main+0x370>)
+ 8002662:	f002 fa20 	bl	8004aa6 <HAL_GPIO_WritePin>
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
+ 8002666:	2201      	movs	r2, #1
+ 8002668:	2120      	movs	r1, #32
+ 800266a:	4899      	ldr	r0, [pc, #612]	@ (80028d0 <main+0x370>)
+ 800266c:	f002 fa1b 	bl	8004aa6 <HAL_GPIO_WritePin>
+
+		for(i=0;i<32;i++)
+ 8002670:	2300      	movs	r3, #0
+ 8002672:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 8002676:	e011      	b.n	800269c <main+0x13c>
+		{
+			flash_data.ph7_value = ADSCalculate_ph_Volts();
+ 8002678:	f7ff fbe2 	bl	8001e40 <ADSCalculate_ph_Volts>
+ 800267c:	4603      	mov	r3, r0
+ 800267e:	4a8e      	ldr	r2, [pc, #568]	@ (80028b8 <main+0x358>)
+ 8002680:	6093      	str	r3, [r2, #8]
+			flash_data.ec12880_value = AD5934_GetImpedance();
+ 8002682:	f7ff f819 	bl	80016b8 <AD5934_GetImpedance>
+ 8002686:	4603      	mov	r3, r0
+ 8002688:	4a8b      	ldr	r2, [pc, #556]	@ (80028b8 <main+0x358>)
+ 800268a:	6113      	str	r3, [r2, #16]
+			Flash_Save_Page(&flash_data);
+ 800268c:	488a      	ldr	r0, [pc, #552]	@ (80028b8 <main+0x358>)
+ 800268e:	f7ff fd13 	bl	80020b8 <Flash_Save_Page>
+		for(i=0;i<32;i++)
+ 8002692:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002696:	3301      	adds	r3, #1
+ 8002698:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 800269c:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 80026a0:	2b1f      	cmp	r3, #31
+ 80026a2:	d9e9      	bls.n	8002678 <main+0x118>
+		}
+
+		HAL_Delay(500);
+ 80026a4:	f44f 70fa 	mov.w	r0, #500	@ 0x1f4
+ 80026a8:	f000 fe1e 	bl	80032e8 <HAL_Delay>
+
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Green LED On
+ 80026ac:	2200      	movs	r2, #0
+ 80026ae:	2110      	movs	r1, #16
+ 80026b0:	4887      	ldr	r0, [pc, #540]	@ (80028d0 <main+0x370>)
+ 80026b2:	f002 f9f8 	bl	8004aa6 <HAL_GPIO_WritePin>
+		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); // Red LED On
+ 80026b6:	2200      	movs	r2, #0
+ 80026b8:	2120      	movs	r1, #32
+ 80026ba:	4885      	ldr	r0, [pc, #532]	@ (80028d0 <main+0x370>)
+ 80026bc:	f002 f9f3 	bl	8004aa6 <HAL_GPIO_WritePin>
+
+		main_state = STATE_RUNNING_OK;
+ 80026c0:	4b84      	ldr	r3, [pc, #528]	@ (80028d4 <main+0x374>)
+ 80026c2:	2200      	movs	r2, #0
+ 80026c4:	701a      	strb	r2, [r3, #0]
+	while (1)
+	{
     /* USER CODE END WHILE */
 
     /* USER CODE BEGIN 3 */
      current_millis = HAL_GetTick();
- 800223c:	f000 fc84 	bl	8002b48 <HAL_GetTick>
- 8002240:	61f8      	str	r0, [r7, #28]
+ 80026c6:	f000 fe05 	bl	80032d4 <HAL_GetTick>
+ 80026ca:	61f8      	str	r0, [r7, #28]
+
+
 
 
      // Piscar LED verde em PB5 a cada 0,5 segundos
-     if ((current_millis - previous_millis_green) >= 800)
- 8002242:	69fa      	ldr	r2, [r7, #28]
- 8002244:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 8002246:	1ad3      	subs	r3, r2, r3
- 8002248:	f5b3 7f48 	cmp.w	r3, #800	@ 0x320
- 800224c:	d3f6      	bcc.n	800223c <main+0x70>
+     if ((current_millis - previous_millis_green) >= 500)
+ 80026cc:	69fa      	ldr	r2, [r7, #28]
+ 80026ce:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80026d0:	1ad3      	subs	r3, r2, r3
+ 80026d2:	f5b3 7ffa 	cmp.w	r3, #500	@ 0x1f4
+ 80026d6:	f0c0 80a7 	bcc.w	8002828 <main+0x2c8>
      {
        previous_millis_green = current_millis;
- 800224e:	69fb      	ldr	r3, [r7, #28]
- 8002250:	637b      	str	r3, [r7, #52]	@ 0x34
+ 80026da:	69fb      	ldr	r3, [r7, #28]
+ 80026dc:	62fb      	str	r3, [r7, #44]	@ 0x2c
+         previous_green_state = current_green_state;
          uint8_t led_data[2] = {0x01, current_green_state}; // Command 0x01 for green LED
 
        }*/
 
+       FloatToString(tempString, Temperature);
+ 80026de:	4b7e      	ldr	r3, [pc, #504]	@ (80028d8 <main+0x378>)
+ 80026e0:	681b      	ldr	r3, [r3, #0]
+ 80026e2:	4618      	mov	r0, r3
+ 80026e4:	f7fd fea0 	bl	8000428 <__aeabi_f2d>
+ 80026e8:	4602      	mov	r2, r0
+ 80026ea:	460b      	mov	r3, r1
+ 80026ec:	1d39      	adds	r1, r7, #4
+ 80026ee:	4608      	mov	r0, r1
+ 80026f0:	f000 f9ec 	bl	8002acc <FloatToString>
+       status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
+ 80026f4:	1d3b      	adds	r3, r7, #4
+ 80026f6:	4618      	mov	r0, r3
+ 80026f8:	f7fd fd2a 	bl	8000150 <strlen>
+ 80026fc:	4603      	mov	r3, r0
+ 80026fe:	b29b      	uxth	r3, r3
+ 8002700:	3b01      	subs	r3, #1
+ 8002702:	b29a      	uxth	r2, r3
+ 8002704:	1d3b      	adds	r3, r7, #4
+ 8002706:	4611      	mov	r1, r2
+ 8002708:	4618      	mov	r0, r3
+ 800270a:	f000 fb3f 	bl	8002d8c <rs485_send_broadcast>
+ 800270e:	4603      	mov	r3, r0
+ 8002710:	76fb      	strb	r3, [r7, #27]
+       status1 = rs485_send_broadcast(newline_temp, strlen((char*)newline_temp));
+ 8002712:	4872      	ldr	r0, [pc, #456]	@ (80028dc <main+0x37c>)
+ 8002714:	f7fd fd1c 	bl	8000150 <strlen>
+ 8002718:	4603      	mov	r3, r0
+ 800271a:	b29b      	uxth	r3, r3
+ 800271c:	4619      	mov	r1, r3
+ 800271e:	486f      	ldr	r0, [pc, #444]	@ (80028dc <main+0x37c>)
+ 8002720:	f000 fb34 	bl	8002d8c <rs485_send_broadcast>
+ 8002724:	4603      	mov	r3, r0
+ 8002726:	76bb      	strb	r3, [r7, #26]
+
 
   	 temperature_RTD = AD5934_GetTemperature();
- 8002252:	f7fe fe73 	bl	8000f3c <AD5934_GetTemperature>
- 8002256:	61b8      	str	r0, [r7, #24]
+ 8002728:	f7fe fdca 	bl	80012c0 <AD5934_GetTemperature>
+ 800272c:	6238      	str	r0, [r7, #32]
   	 FloatToString(tempString, temperature_RTD);
- 8002258:	69b8      	ldr	r0, [r7, #24]
- 800225a:	f7fe fa0d 	bl	8000678 <__aeabi_f2d>
- 800225e:	4602      	mov	r2, r0
- 8002260:	460b      	mov	r3, r1
- 8002262:	1d39      	adds	r1, r7, #4
- 8002264:	4608      	mov	r0, r1
- 8002266:	f000 f939 	bl	80024dc <FloatToString>
+ 800272e:	6a38      	ldr	r0, [r7, #32]
+ 8002730:	f7fd fe7a 	bl	8000428 <__aeabi_f2d>
+ 8002734:	4602      	mov	r2, r0
+ 8002736:	460b      	mov	r3, r1
+ 8002738:	1d39      	adds	r1, r7, #4
+ 800273a:	4608      	mov	r0, r1
+ 800273c:	f000 f9c6 	bl	8002acc <FloatToString>
   	 status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
- 800226a:	1d3b      	adds	r3, r7, #4
- 800226c:	4618      	mov	r0, r3
- 800226e:	f7fd ff6d 	bl	800014c <strlen>
- 8002272:	4603      	mov	r3, r0
- 8002274:	b29b      	uxth	r3, r3
- 8002276:	3b01      	subs	r3, #1
- 8002278:	b29a      	uxth	r2, r3
- 800227a:	1d3b      	adds	r3, r7, #4
- 800227c:	4611      	mov	r1, r2
- 800227e:	4618      	mov	r0, r3
- 8002280:	f000 fa34 	bl	80026ec <rs485_send_broadcast>
- 8002284:	4603      	mov	r3, r0
- 8002286:	75fb      	strb	r3, [r7, #23]
+ 8002740:	1d3b      	adds	r3, r7, #4
+ 8002742:	4618      	mov	r0, r3
+ 8002744:	f7fd fd04 	bl	8000150 <strlen>
+ 8002748:	4603      	mov	r3, r0
+ 800274a:	b29b      	uxth	r3, r3
+ 800274c:	3b01      	subs	r3, #1
+ 800274e:	b29a      	uxth	r2, r3
+ 8002750:	1d3b      	adds	r3, r7, #4
+ 8002752:	4611      	mov	r1, r2
+ 8002754:	4618      	mov	r0, r3
+ 8002756:	f000 fb19 	bl	8002d8c <rs485_send_broadcast>
+ 800275a:	4603      	mov	r3, r0
+ 800275c:	76fb      	strb	r3, [r7, #27]
   	 status1 = rs485_send_broadcast(newline_real, strlen((char*)newline_real));
- 8002288:	485d      	ldr	r0, [pc, #372]	@ (8002400 <main+0x234>)
- 800228a:	f7fd ff5f 	bl	800014c <strlen>
- 800228e:	4603      	mov	r3, r0
- 8002290:	b29b      	uxth	r3, r3
- 8002292:	4619      	mov	r1, r3
- 8002294:	485a      	ldr	r0, [pc, #360]	@ (8002400 <main+0x234>)
- 8002296:	f000 fa29 	bl	80026ec <rs485_send_broadcast>
- 800229a:	4603      	mov	r3, r0
- 800229c:	75bb      	strb	r3, [r7, #22]
+ 800275e:	4860      	ldr	r0, [pc, #384]	@ (80028e0 <main+0x380>)
+ 8002760:	f7fd fcf6 	bl	8000150 <strlen>
+ 8002764:	4603      	mov	r3, r0
+ 8002766:	b29b      	uxth	r3, r3
+ 8002768:	4619      	mov	r1, r3
+ 800276a:	485d      	ldr	r0, [pc, #372]	@ (80028e0 <main+0x380>)
+ 800276c:	f000 fb0e 	bl	8002d8c <rs485_send_broadcast>
+ 8002770:	4603      	mov	r3, r0
+ 8002772:	76bb      	strb	r3, [r7, #26]
 
 
-  	if(edge_state == FALLING_EDGE)
- 800229e:	4b59      	ldr	r3, [pc, #356]	@ (8002404 <main+0x238>)
- 80022a0:	781b      	ldrb	r3, [r3, #0]
- 80022a2:	b25b      	sxtb	r3, r3
- 80022a4:	f1b3 3fff 	cmp.w	r3, #4294967295
- 80022a8:	d123      	bne.n	80022f2 <main+0x126>
-  	     {
-  			HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_SET);
- 80022aa:	2201      	movs	r2, #1
- 80022ac:	2110      	movs	r1, #16
- 80022ae:	4856      	ldr	r0, [pc, #344]	@ (8002408 <main+0x23c>)
- 80022b0:	f001 f9e5 	bl	800367e <HAL_GPIO_WritePin>
-  			HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET);
- 80022b4:	2200      	movs	r2, #0
- 80022b6:	2120      	movs	r1, #32
- 80022b8:	4853      	ldr	r0, [pc, #332]	@ (8002408 <main+0x23c>)
- 80022ba:	f001 f9e0 	bl	800367e <HAL_GPIO_WritePin>
-  			temp_calib = temperature_RTD;
- 80022be:	4a53      	ldr	r2, [pc, #332]	@ (800240c <main+0x240>)
- 80022c0:	69bb      	ldr	r3, [r7, #24]
- 80022c2:	6013      	str	r3, [r2, #0]
-  	    	 v_ph4 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c));
- 80022c4:	484d      	ldr	r0, [pc, #308]	@ (80023fc <main+0x230>)
- 80022c6:	f7ff fc86 	bl	8001bd6 <ADSreadADC_Differential_0_1>
- 80022ca:	4603      	mov	r3, r0
- 80022cc:	b29b      	uxth	r3, r3
- 80022ce:	f5c3 6300 	rsb	r3, r3, #2048	@ 0x800
- 80022d2:	b29b      	uxth	r3, r3
- 80022d4:	b21b      	sxth	r3, r3
- 80022d6:	4618      	mov	r0, r3
- 80022d8:	f7ff fcbc 	bl	8001c54 <ADSCalculate_ph_Volts>
- 80022dc:	4603      	mov	r3, r0
- 80022de:	4a4c      	ldr	r2, [pc, #304]	@ (8002410 <main+0x244>)
- 80022e0:	6013      	str	r3, [r2, #0]
-  	    	 edge_state = NO_EDGE;
- 80022e2:	4b48      	ldr	r3, [pc, #288]	@ (8002404 <main+0x238>)
- 80022e4:	2200      	movs	r2, #0
- 80022e6:	701a      	strb	r2, [r3, #0]
-  	    	 HAL_Delay(500);
- 80022e8:	f44f 70fa 	mov.w	r0, #500	@ 0x1f4
- 80022ec:	f000 fc36 	bl	8002b5c <HAL_Delay>
- 80022f0:	e024      	b.n	800233c <main+0x170>
-  	     }else if(edge_state == RISING_EDGE)
- 80022f2:	4b44      	ldr	r3, [pc, #272]	@ (8002404 <main+0x238>)
- 80022f4:	781b      	ldrb	r3, [r3, #0]
- 80022f6:	b25b      	sxtb	r3, r3
- 80022f8:	2b01      	cmp	r3, #1
- 80022fa:	d11f      	bne.n	800233c <main+0x170>
-  	     {
-  	    	HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET);
- 80022fc:	2200      	movs	r2, #0
- 80022fe:	2110      	movs	r1, #16
- 8002300:	4841      	ldr	r0, [pc, #260]	@ (8002408 <main+0x23c>)
- 8002302:	f001 f9bc 	bl	800367e <HAL_GPIO_WritePin>
-  	    	HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET);
- 8002306:	2201      	movs	r2, #1
- 8002308:	2120      	movs	r1, #32
- 800230a:	483f      	ldr	r0, [pc, #252]	@ (8002408 <main+0x23c>)
- 800230c:	f001 f9b7 	bl	800367e <HAL_GPIO_WritePin>
-  	    	v_ph7 = ADSCalculate_ph_Volts(2048 - ADSreadADC_Differential_0_1(&i2c));
- 8002310:	483a      	ldr	r0, [pc, #232]	@ (80023fc <main+0x230>)
- 8002312:	f7ff fc60 	bl	8001bd6 <ADSreadADC_Differential_0_1>
- 8002316:	4603      	mov	r3, r0
- 8002318:	b29b      	uxth	r3, r3
- 800231a:	f5c3 6300 	rsb	r3, r3, #2048	@ 0x800
- 800231e:	b29b      	uxth	r3, r3
- 8002320:	b21b      	sxth	r3, r3
- 8002322:	4618      	mov	r0, r3
- 8002324:	f7ff fc96 	bl	8001c54 <ADSCalculate_ph_Volts>
- 8002328:	4603      	mov	r3, r0
- 800232a:	4a3a      	ldr	r2, [pc, #232]	@ (8002414 <main+0x248>)
- 800232c:	6013      	str	r3, [r2, #0]
-  	    	 edge_state = NO_EDGE;
- 800232e:	4b35      	ldr	r3, [pc, #212]	@ (8002404 <main+0x238>)
- 8002330:	2200      	movs	r2, #0
- 8002332:	701a      	strb	r2, [r3, #0]
-  	    	HAL_Delay(500);
- 8002334:	f44f 70fa 	mov.w	r0, #500	@ 0x1f4
- 8002338:	f000 fc10 	bl	8002b5c <HAL_Delay>
-  	     }
 
-  	     ph_compensated = ADSCalculate_ph_Compensated((2048 - ADSreadADC_Differential_0_1(&i2c)),temp_calib);
- 800233c:	482f      	ldr	r0, [pc, #188]	@ (80023fc <main+0x230>)
- 800233e:	f7ff fc4a 	bl	8001bd6 <ADSreadADC_Differential_0_1>
- 8002342:	4603      	mov	r3, r0
- 8002344:	b29b      	uxth	r3, r3
- 8002346:	f5c3 6300 	rsb	r3, r3, #2048	@ 0x800
- 800234a:	b29b      	uxth	r3, r3
- 800234c:	b21b      	sxth	r3, r3
- 800234e:	4a2f      	ldr	r2, [pc, #188]	@ (800240c <main+0x240>)
- 8002350:	6812      	ldr	r2, [r2, #0]
- 8002352:	4611      	mov	r1, r2
- 8002354:	4618      	mov	r0, r3
- 8002356:	f7ff fc9b 	bl	8001c90 <ADSCalculate_ph_Compensated>
- 800235a:	4603      	mov	r3, r0
- 800235c:	4a2e      	ldr	r2, [pc, #184]	@ (8002418 <main+0x24c>)
- 800235e:	6013      	str	r3, [r2, #0]
+  	     ph_compensated = ADSCalculate_ph_Compensated((2048 - ADSreadADC_Differential_0_1(&i2c)),flash_data.temperature_value);
+ 8002774:	4855      	ldr	r0, [pc, #340]	@ (80028cc <main+0x36c>)
+ 8002776:	f7ff fb24 	bl	8001dc2 <ADSreadADC_Differential_0_1>
+ 800277a:	4603      	mov	r3, r0
+ 800277c:	b29b      	uxth	r3, r3
+ 800277e:	f5c3 6300 	rsb	r3, r3, #2048	@ 0x800
+ 8002782:	b29b      	uxth	r3, r3
+ 8002784:	b21b      	sxth	r3, r3
+ 8002786:	4a4c      	ldr	r2, [pc, #304]	@ (80028b8 <main+0x358>)
+ 8002788:	6952      	ldr	r2, [r2, #20]
+ 800278a:	4611      	mov	r1, r2
+ 800278c:	4618      	mov	r0, r3
+ 800278e:	f7ff fbad 	bl	8001eec <ADSCalculate_ph_Compensated>
+ 8002792:	6178      	str	r0, [r7, #20]
   	     FloatToString(tempString, ph_compensated);
- 8002360:	4b2d      	ldr	r3, [pc, #180]	@ (8002418 <main+0x24c>)
- 8002362:	681b      	ldr	r3, [r3, #0]
- 8002364:	4618      	mov	r0, r3
- 8002366:	f7fe f987 	bl	8000678 <__aeabi_f2d>
- 800236a:	4602      	mov	r2, r0
- 800236c:	460b      	mov	r3, r1
- 800236e:	1d39      	adds	r1, r7, #4
- 8002370:	4608      	mov	r0, r1
- 8002372:	f000 f8b3 	bl	80024dc <FloatToString>
+ 8002794:	6978      	ldr	r0, [r7, #20]
+ 8002796:	f7fd fe47 	bl	8000428 <__aeabi_f2d>
+ 800279a:	4602      	mov	r2, r0
+ 800279c:	460b      	mov	r3, r1
+ 800279e:	1d39      	adds	r1, r7, #4
+ 80027a0:	4608      	mov	r0, r1
+ 80027a2:	f000 f993 	bl	8002acc <FloatToString>
   	     status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
- 8002376:	1d3b      	adds	r3, r7, #4
- 8002378:	4618      	mov	r0, r3
- 800237a:	f7fd fee7 	bl	800014c <strlen>
- 800237e:	4603      	mov	r3, r0
- 8002380:	b29b      	uxth	r3, r3
- 8002382:	3b01      	subs	r3, #1
- 8002384:	b29a      	uxth	r2, r3
- 8002386:	1d3b      	adds	r3, r7, #4
- 8002388:	4611      	mov	r1, r2
- 800238a:	4618      	mov	r0, r3
- 800238c:	f000 f9ae 	bl	80026ec <rs485_send_broadcast>
- 8002390:	4603      	mov	r3, r0
- 8002392:	75fb      	strb	r3, [r7, #23]
+ 80027a6:	1d3b      	adds	r3, r7, #4
+ 80027a8:	4618      	mov	r0, r3
+ 80027aa:	f7fd fcd1 	bl	8000150 <strlen>
+ 80027ae:	4603      	mov	r3, r0
+ 80027b0:	b29b      	uxth	r3, r3
+ 80027b2:	3b01      	subs	r3, #1
+ 80027b4:	b29a      	uxth	r2, r3
+ 80027b6:	1d3b      	adds	r3, r7, #4
+ 80027b8:	4611      	mov	r1, r2
+ 80027ba:	4618      	mov	r0, r3
+ 80027bc:	f000 fae6 	bl	8002d8c <rs485_send_broadcast>
+ 80027c0:	4603      	mov	r3, r0
+ 80027c2:	76fb      	strb	r3, [r7, #27]
   	     status1 = rs485_send_broadcast(newline_ph, strlen((char*)newline_ph));
- 8002394:	4821      	ldr	r0, [pc, #132]	@ (800241c <main+0x250>)
- 8002396:	f7fd fed9 	bl	800014c <strlen>
- 800239a:	4603      	mov	r3, r0
- 800239c:	b29b      	uxth	r3, r3
- 800239e:	4619      	mov	r1, r3
- 80023a0:	481e      	ldr	r0, [pc, #120]	@ (800241c <main+0x250>)
- 80023a2:	f000 f9a3 	bl	80026ec <rs485_send_broadcast>
- 80023a6:	4603      	mov	r3, r0
- 80023a8:	75bb      	strb	r3, [r7, #22]
+ 80027c4:	4847      	ldr	r0, [pc, #284]	@ (80028e4 <main+0x384>)
+ 80027c6:	f7fd fcc3 	bl	8000150 <strlen>
+ 80027ca:	4603      	mov	r3, r0
+ 80027cc:	b29b      	uxth	r3, r3
+ 80027ce:	4619      	mov	r1, r3
+ 80027d0:	4844      	ldr	r0, [pc, #272]	@ (80028e4 <main+0x384>)
+ 80027d2:	f000 fadb 	bl	8002d8c <rs485_send_broadcast>
+ 80027d6:	4603      	mov	r3, r0
+ 80027d8:	76bb      	strb	r3, [r7, #26]
 
 
   	   admittance_EC = AD5934_GetImpedance();
- 80023aa:	f7fe ffcf 	bl	800134c <AD5934_GetImpedance>
- 80023ae:	6138      	str	r0, [r7, #16]
+ 80027da:	f7fe ff6d 	bl	80016b8 <AD5934_GetImpedance>
+ 80027de:	6138      	str	r0, [r7, #16]
   	   FloatToString(tempString, admittance_EC);
- 80023b0:	6938      	ldr	r0, [r7, #16]
- 80023b2:	f7fe f961 	bl	8000678 <__aeabi_f2d>
- 80023b6:	4602      	mov	r2, r0
- 80023b8:	460b      	mov	r3, r1
- 80023ba:	1d39      	adds	r1, r7, #4
- 80023bc:	4608      	mov	r0, r1
- 80023be:	f000 f88d 	bl	80024dc <FloatToString>
+ 80027e0:	6938      	ldr	r0, [r7, #16]
+ 80027e2:	f7fd fe21 	bl	8000428 <__aeabi_f2d>
+ 80027e6:	4602      	mov	r2, r0
+ 80027e8:	460b      	mov	r3, r1
+ 80027ea:	1d39      	adds	r1, r7, #4
+ 80027ec:	4608      	mov	r0, r1
+ 80027ee:	f000 f96d 	bl	8002acc <FloatToString>
   	   status0 = rs485_send_broadcast(tempString, (strlen((char*)tempString)-1));
- 80023c2:	1d3b      	adds	r3, r7, #4
- 80023c4:	4618      	mov	r0, r3
- 80023c6:	f7fd fec1 	bl	800014c <strlen>
- 80023ca:	4603      	mov	r3, r0
- 80023cc:	b29b      	uxth	r3, r3
- 80023ce:	3b01      	subs	r3, #1
- 80023d0:	b29a      	uxth	r2, r3
- 80023d2:	1d3b      	adds	r3, r7, #4
- 80023d4:	4611      	mov	r1, r2
- 80023d6:	4618      	mov	r0, r3
- 80023d8:	f000 f988 	bl	80026ec <rs485_send_broadcast>
- 80023dc:	4603      	mov	r3, r0
- 80023de:	75fb      	strb	r3, [r7, #23]
+ 80027f2:	1d3b      	adds	r3, r7, #4
+ 80027f4:	4618      	mov	r0, r3
+ 80027f6:	f7fd fcab 	bl	8000150 <strlen>
+ 80027fa:	4603      	mov	r3, r0
+ 80027fc:	b29b      	uxth	r3, r3
+ 80027fe:	3b01      	subs	r3, #1
+ 8002800:	b29a      	uxth	r2, r3
+ 8002802:	1d3b      	adds	r3, r7, #4
+ 8002804:	4611      	mov	r1, r2
+ 8002806:	4618      	mov	r0, r3
+ 8002808:	f000 fac0 	bl	8002d8c <rs485_send_broadcast>
+ 800280c:	4603      	mov	r3, r0
+ 800280e:	76fb      	strb	r3, [r7, #27]
   	   status1 = rs485_send_broadcast(newline_admi, strlen((char*)newline_admi));
- 80023e0:	480f      	ldr	r0, [pc, #60]	@ (8002420 <main+0x254>)
- 80023e2:	f7fd feb3 	bl	800014c <strlen>
- 80023e6:	4603      	mov	r3, r0
- 80023e8:	b29b      	uxth	r3, r3
- 80023ea:	4619      	mov	r1, r3
- 80023ec:	480c      	ldr	r0, [pc, #48]	@ (8002420 <main+0x254>)
- 80023ee:	f000 f97d 	bl	80026ec <rs485_send_broadcast>
- 80023f2:	4603      	mov	r3, r0
- 80023f4:	75bb      	strb	r3, [r7, #22]
-     current_millis = HAL_GetTick();
- 80023f6:	e721      	b.n	800223c <main+0x70>
- 80023f8:	200001d4 	.word	0x200001d4
- 80023fc:	2000027c 	.word	0x2000027c
- 8002400:	20000014 	.word	0x20000014
- 8002404:	200001d1 	.word	0x200001d1
- 8002408:	40010c00 	.word	0x40010c00
- 800240c:	200001b4 	.word	0x200001b4
- 8002410:	200001bc 	.word	0x200001bc
- 8002414:	200001c0 	.word	0x200001c0
- 8002418:	200001b8 	.word	0x200001b8
- 800241c:	20000004 	.word	0x20000004
- 8002420:	2000000c 	.word	0x2000000c
+ 8002810:	4835      	ldr	r0, [pc, #212]	@ (80028e8 <main+0x388>)
+ 8002812:	f7fd fc9d 	bl	8000150 <strlen>
+ 8002816:	4603      	mov	r3, r0
+ 8002818:	b29b      	uxth	r3, r3
+ 800281a:	4619      	mov	r1, r3
+ 800281c:	4832      	ldr	r0, [pc, #200]	@ (80028e8 <main+0x388>)
+ 800281e:	f000 fab5 	bl	8002d8c <rs485_send_broadcast>
+ 8002822:	4603      	mov	r3, r0
+ 8002824:	76bb      	strb	r3, [r7, #26]
+ 8002826:	e74e      	b.n	80026c6 <main+0x166>
 
-08002424 <SystemClock_Config>:
+     }
+     else if(UpdateEvent)
+ 8002828:	4b30      	ldr	r3, [pc, #192]	@ (80028ec <main+0x38c>)
+ 800282a:	781b      	ldrb	r3, [r3, #0]
+ 800282c:	2b00      	cmp	r3, #0
+ 800282e:	f43f af4a 	beq.w	80026c6 <main+0x166>
+     {
+
+		 for (i = (STM32_TEMPERATURE_AVERAGES-1); i > 0; i--)
+ 8002832:	2303      	movs	r3, #3
+ 8002834:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 8002838:	e00f      	b.n	800285a <main+0x2fa>
+		 	 Temp_Samples[i] = Temp_Samples[i-1];
+ 800283a:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 800283e:	1e5a      	subs	r2, r3, #1
+ 8002840:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002844:	492a      	ldr	r1, [pc, #168]	@ (80028f0 <main+0x390>)
+ 8002846:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
+ 800284a:	4929      	ldr	r1, [pc, #164]	@ (80028f0 <main+0x390>)
+ 800284c:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+		 for (i = (STM32_TEMPERATURE_AVERAGES-1); i > 0; i--)
+ 8002850:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002854:	3b01      	subs	r3, #1
+ 8002856:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 800285a:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 800285e:	2b00      	cmp	r3, #0
+ 8002860:	d1eb      	bne.n	800283a <main+0x2da>
+
+
+		 	// Read real and imaginary data
+		 	 if(AD_RES[0]>0.0f)
+ 8002862:	4b18      	ldr	r3, [pc, #96]	@ (80028c4 <main+0x364>)
+ 8002864:	881b      	ldrh	r3, [r3, #0]
+ 8002866:	4618      	mov	r0, r3
+ 8002868:	f7fe fa02 	bl	8000c70 <__aeabi_i2f>
+ 800286c:	4603      	mov	r3, r0
+ 800286e:	f04f 0100 	mov.w	r1, #0
+ 8002872:	4618      	mov	r0, r3
+ 8002874:	f7fe fc0c 	bl	8001090 <__aeabi_fcmpgt>
+ 8002878:	4603      	mov	r3, r0
+ 800287a:	2b00      	cmp	r3, #0
+ 800287c:	d03c      	beq.n	80028f8 <main+0x398>
+		 		 V_Ref = (float)((V_REF_INT * 4095.0)/AD_RES[0]);
+ 800287e:	4b11      	ldr	r3, [pc, #68]	@ (80028c4 <main+0x364>)
+ 8002880:	881b      	ldrh	r3, [r3, #0]
+ 8002882:	4618      	mov	r0, r3
+ 8002884:	f7fd fdbe 	bl	8000404 <__aeabi_i2d>
+ 8002888:	4602      	mov	r2, r0
+ 800288a:	460b      	mov	r3, r1
+ 800288c:	a108      	add	r1, pc, #32	@ (adr r1, 80028b0 <main+0x350>)
+ 800288e:	e9d1 0100 	ldrd	r0, r1, [r1]
+ 8002892:	f7fd ff4b 	bl	800072c <__aeabi_ddiv>
+ 8002896:	4602      	mov	r2, r0
+ 8002898:	460b      	mov	r3, r1
+ 800289a:	4610      	mov	r0, r2
+ 800289c:	4619      	mov	r1, r3
+ 800289e:	f7fe f8dd 	bl	8000a5c <__aeabi_d2f>
+ 80028a2:	4603      	mov	r3, r0
+ 80028a4:	4a13      	ldr	r2, [pc, #76]	@ (80028f4 <main+0x394>)
+ 80028a6:	6013      	str	r3, [r2, #0]
+ 80028a8:	e02a      	b.n	8002900 <main+0x3a0>
+ 80028aa:	bf00      	nop
+ 80028ac:	f3af 8000 	nop.w
+ 80028b0:	0ccc0000 	.word	0x0ccc0000
+ 80028b4:	40b33200 	.word	0x40b33200
+ 80028b8:	200001f8 	.word	0x200001f8
+ 80028bc:	20000720 	.word	0x20000720
+ 80028c0:	2000011c 	.word	0x2000011c
+ 80028c4:	200006ac 	.word	0x200006ac
+ 80028c8:	20000600 	.word	0x20000600
+ 80028cc:	200001c0 	.word	0x200001c0
+ 80028d0:	40010c00 	.word	0x40010c00
+ 80028d4:	200006a8 	.word	0x200006a8
+ 80028d8:	200006b4 	.word	0x200006b4
+ 80028dc:	20000014 	.word	0x20000014
+ 80028e0:	2000001c 	.word	0x2000001c
+ 80028e4:	20000004 	.word	0x20000004
+ 80028e8:	2000000c 	.word	0x2000000c
+ 80028ec:	200006b0 	.word	0x200006b0
+ 80028f0:	200006c4 	.word	0x200006c4
+ 80028f4:	200006c0 	.word	0x200006c0
+		 	 else
+		 		V_Ref = 0.0f;
+ 80028f8:	4b3b      	ldr	r3, [pc, #236]	@ (80029e8 <main+0x488>)
+ 80028fa:	f04f 0200 	mov.w	r2, #0
+ 80028fe:	601a      	str	r2, [r3, #0]
+		 	 V_Sense = (float)(AD_RES[1] * V_Ref) / 4095.0;
+ 8002900:	4b3a      	ldr	r3, [pc, #232]	@ (80029ec <main+0x48c>)
+ 8002902:	885b      	ldrh	r3, [r3, #2]
+ 8002904:	4618      	mov	r0, r3
+ 8002906:	f7fe f9b3 	bl	8000c70 <__aeabi_i2f>
+ 800290a:	4602      	mov	r2, r0
+ 800290c:	4b36      	ldr	r3, [pc, #216]	@ (80029e8 <main+0x488>)
+ 800290e:	681b      	ldr	r3, [r3, #0]
+ 8002910:	4619      	mov	r1, r3
+ 8002912:	4610      	mov	r0, r2
+ 8002914:	f7fe fa00 	bl	8000d18 <__aeabi_fmul>
+ 8002918:	4603      	mov	r3, r0
+ 800291a:	4935      	ldr	r1, [pc, #212]	@ (80029f0 <main+0x490>)
+ 800291c:	4618      	mov	r0, r3
+ 800291e:	f7fe faaf 	bl	8000e80 <__aeabi_fdiv>
+ 8002922:	4603      	mov	r3, r0
+ 8002924:	461a      	mov	r2, r3
+ 8002926:	4b33      	ldr	r3, [pc, #204]	@ (80029f4 <main+0x494>)
+ 8002928:	601a      	str	r2, [r3, #0]
+		 	Temp_Samples[0] = (((V_AT_25C - V_Sense) * 1000.0) /AVG_SLOPE) + 25.0;
+ 800292a:	4b32      	ldr	r3, [pc, #200]	@ (80029f4 <main+0x494>)
+ 800292c:	681b      	ldr	r3, [r3, #0]
+ 800292e:	4619      	mov	r1, r3
+ 8002930:	4831      	ldr	r0, [pc, #196]	@ (80029f8 <main+0x498>)
+ 8002932:	f7fe f8e7 	bl	8000b04 <__aeabi_fsub>
+ 8002936:	4603      	mov	r3, r0
+ 8002938:	4618      	mov	r0, r3
+ 800293a:	f7fd fd75 	bl	8000428 <__aeabi_f2d>
+ 800293e:	f04f 0200 	mov.w	r2, #0
+ 8002942:	4b2e      	ldr	r3, [pc, #184]	@ (80029fc <main+0x49c>)
+ 8002944:	f7fd fdc8 	bl	80004d8 <__aeabi_dmul>
+ 8002948:	4602      	mov	r2, r0
+ 800294a:	460b      	mov	r3, r1
+ 800294c:	4610      	mov	r0, r2
+ 800294e:	4619      	mov	r1, r3
+ 8002950:	a323      	add	r3, pc, #140	@ (adr r3, 80029e0 <main+0x480>)
+ 8002952:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8002956:	f7fd fee9 	bl	800072c <__aeabi_ddiv>
+ 800295a:	4602      	mov	r2, r0
+ 800295c:	460b      	mov	r3, r1
+ 800295e:	4610      	mov	r0, r2
+ 8002960:	4619      	mov	r1, r3
+ 8002962:	f04f 0200 	mov.w	r2, #0
+ 8002966:	4b26      	ldr	r3, [pc, #152]	@ (8002a00 <main+0x4a0>)
+ 8002968:	f7fd fc00 	bl	800016c <__adddf3>
+ 800296c:	4602      	mov	r2, r0
+ 800296e:	460b      	mov	r3, r1
+ 8002970:	4610      	mov	r0, r2
+ 8002972:	4619      	mov	r1, r3
+ 8002974:	f7fe f872 	bl	8000a5c <__aeabi_d2f>
+ 8002978:	4603      	mov	r3, r0
+ 800297a:	4a22      	ldr	r2, [pc, #136]	@ (8002a04 <main+0x4a4>)
+ 800297c:	6013      	str	r3, [r2, #0]
+
+		 	for (i = 0, Temp_Sum=0; i < STM32_TEMPERATURE_AVERAGES; i++)
+ 800297e:	2300      	movs	r3, #0
+ 8002980:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 8002984:	4b20      	ldr	r3, [pc, #128]	@ (8002a08 <main+0x4a8>)
+ 8002986:	f04f 0200 	mov.w	r2, #0
+ 800298a:	601a      	str	r2, [r3, #0]
+ 800298c:	e013      	b.n	80029b6 <main+0x456>
+		 		Temp_Sum += Temp_Samples[i];
+ 800298e:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 8002992:	4a1c      	ldr	r2, [pc, #112]	@ (8002a04 <main+0x4a4>)
+ 8002994:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8002998:	4a1b      	ldr	r2, [pc, #108]	@ (8002a08 <main+0x4a8>)
+ 800299a:	6812      	ldr	r2, [r2, #0]
+ 800299c:	4611      	mov	r1, r2
+ 800299e:	4618      	mov	r0, r3
+ 80029a0:	f7fe f8b2 	bl	8000b08 <__addsf3>
+ 80029a4:	4603      	mov	r3, r0
+ 80029a6:	461a      	mov	r2, r3
+ 80029a8:	4b17      	ldr	r3, [pc, #92]	@ (8002a08 <main+0x4a8>)
+ 80029aa:	601a      	str	r2, [r3, #0]
+		 	for (i = 0, Temp_Sum=0; i < STM32_TEMPERATURE_AVERAGES; i++)
+ 80029ac:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 80029b0:	3301      	adds	r3, #1
+ 80029b2:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+ 80029b6:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+ 80029ba:	2b03      	cmp	r3, #3
+ 80029bc:	d9e7      	bls.n	800298e <main+0x42e>
+
+		 	Temperature = Temp_Sum/((float)STM32_TEMPERATURE_AVERAGES);
+ 80029be:	4b12      	ldr	r3, [pc, #72]	@ (8002a08 <main+0x4a8>)
+ 80029c0:	681b      	ldr	r3, [r3, #0]
+ 80029c2:	f04f 4181 	mov.w	r1, #1082130432	@ 0x40800000
+ 80029c6:	4618      	mov	r0, r3
+ 80029c8:	f7fe fa5a 	bl	8000e80 <__aeabi_fdiv>
+ 80029cc:	4603      	mov	r3, r0
+ 80029ce:	461a      	mov	r2, r3
+ 80029d0:	4b0e      	ldr	r3, [pc, #56]	@ (8002a0c <main+0x4ac>)
+ 80029d2:	601a      	str	r2, [r3, #0]
+
+		 	UpdateEvent = 0;
+ 80029d4:	4b0e      	ldr	r3, [pc, #56]	@ (8002a10 <main+0x4b0>)
+ 80029d6:	2200      	movs	r2, #0
+ 80029d8:	701a      	strb	r2, [r3, #0]
+     current_millis = HAL_GetTick();
+ 80029da:	e674      	b.n	80026c6 <main+0x166>
+ 80029dc:	f3af 8000 	nop.w
+ 80029e0:	40000000 	.word	0x40000000
+ 80029e4:	40113333 	.word	0x40113333
+ 80029e8:	200006c0 	.word	0x200006c0
+ 80029ec:	200006ac 	.word	0x200006ac
+ 80029f0:	457ff000 	.word	0x457ff000
+ 80029f4:	200006bc 	.word	0x200006bc
+ 80029f8:	3fb70a3d 	.word	0x3fb70a3d
+ 80029fc:	408f4000 	.word	0x408f4000
+ 8002a00:	40390000 	.word	0x40390000
+ 8002a04:	200006c4 	.word	0x200006c4
+ 8002a08:	200006b8 	.word	0x200006b8
+ 8002a0c:	200006b4 	.word	0x200006b4
+ 8002a10:	200006b0 	.word	0x200006b0
+
+08002a14 <SystemClock_Config>:
 /**
   * @brief System Clock Configuration
   * @retval None
   */
 void SystemClock_Config(void)
 {
- 8002424:	b580      	push	{r7, lr}
- 8002426:	b094      	sub	sp, #80	@ 0x50
- 8002428:	af00      	add	r7, sp, #0
+ 8002a14:	b580      	push	{r7, lr}
+ 8002a16:	b094      	sub	sp, #80	@ 0x50
+ 8002a18:	af00      	add	r7, sp, #0
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 800242a:	f107 0328 	add.w	r3, r7, #40	@ 0x28
- 800242e:	2228      	movs	r2, #40	@ 0x28
- 8002430:	2100      	movs	r1, #0
- 8002432:	4618      	mov	r0, r3
- 8002434:	f003 fc66 	bl	8005d04 <memset>
+ 8002a1a:	f107 0328 	add.w	r3, r7, #40	@ 0x28
+ 8002a1e:	2228      	movs	r2, #40	@ 0x28
+ 8002a20:	2100      	movs	r1, #0
+ 8002a22:	4618      	mov	r0, r3
+ 8002a24:	f004 fefc 	bl	8007820 <memset>
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8002438:	f107 0314 	add.w	r3, r7, #20
- 800243c:	2200      	movs	r2, #0
- 800243e:	601a      	str	r2, [r3, #0]
- 8002440:	605a      	str	r2, [r3, #4]
- 8002442:	609a      	str	r2, [r3, #8]
- 8002444:	60da      	str	r2, [r3, #12]
- 8002446:	611a      	str	r2, [r3, #16]
+ 8002a28:	f107 0314 	add.w	r3, r7, #20
+ 8002a2c:	2200      	movs	r2, #0
+ 8002a2e:	601a      	str	r2, [r3, #0]
+ 8002a30:	605a      	str	r2, [r3, #4]
+ 8002a32:	609a      	str	r2, [r3, #8]
+ 8002a34:	60da      	str	r2, [r3, #12]
+ 8002a36:	611a      	str	r2, [r3, #16]
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
- 8002448:	1d3b      	adds	r3, r7, #4
- 800244a:	2200      	movs	r2, #0
- 800244c:	601a      	str	r2, [r3, #0]
- 800244e:	605a      	str	r2, [r3, #4]
- 8002450:	609a      	str	r2, [r3, #8]
- 8002452:	60da      	str	r2, [r3, #12]
+ 8002a38:	1d3b      	adds	r3, r7, #4
+ 8002a3a:	2200      	movs	r2, #0
+ 8002a3c:	601a      	str	r2, [r3, #0]
+ 8002a3e:	605a      	str	r2, [r3, #4]
+ 8002a40:	609a      	str	r2, [r3, #8]
+ 8002a42:	60da      	str	r2, [r3, #12]
 
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- 8002454:	2301      	movs	r3, #1
- 8002456:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8002a44:	2301      	movs	r3, #1
+ 8002a46:	62bb      	str	r3, [r7, #40]	@ 0x28
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- 8002458:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
- 800245c:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 8002a48:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
+ 8002a4c:	62fb      	str	r3, [r7, #44]	@ 0x2c
   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
- 800245e:	2300      	movs	r3, #0
- 8002460:	633b      	str	r3, [r7, #48]	@ 0x30
+ 8002a4e:	2300      	movs	r3, #0
+ 8002a50:	633b      	str	r3, [r7, #48]	@ 0x30
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8002462:	2301      	movs	r3, #1
- 8002464:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 8002a52:	2301      	movs	r3, #1
+ 8002a54:	63bb      	str	r3, [r7, #56]	@ 0x38
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- 8002466:	2302      	movs	r3, #2
- 8002468:	647b      	str	r3, [r7, #68]	@ 0x44
+ 8002a56:	2302      	movs	r3, #2
+ 8002a58:	647b      	str	r3, [r7, #68]	@ 0x44
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- 800246a:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
- 800246e:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8002a5a:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
+ 8002a5e:	64bb      	str	r3, [r7, #72]	@ 0x48
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
- 8002470:	2300      	movs	r3, #0
- 8002472:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 8002a60:	2300      	movs	r3, #0
+ 8002a62:	64fb      	str	r3, [r7, #76]	@ 0x4c
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8002474:	f107 0328 	add.w	r3, r7, #40	@ 0x28
- 8002478:	4618      	mov	r0, r3
- 800247a:	f002 f965 	bl	8004748 <HAL_RCC_OscConfig>
- 800247e:	4603      	mov	r3, r0
- 8002480:	2b00      	cmp	r3, #0
- 8002482:	d001      	beq.n	8002488 <SystemClock_Config+0x64>
+ 8002a64:	f107 0328 	add.w	r3, r7, #40	@ 0x28
+ 8002a68:	4618      	mov	r0, r3
+ 8002a6a:	f003 f881 	bl	8005b70 <HAL_RCC_OscConfig>
+ 8002a6e:	4603      	mov	r3, r0
+ 8002a70:	2b00      	cmp	r3, #0
+ 8002a72:	d001      	beq.n	8002a78 <SystemClock_Config+0x64>
   {
     Error_Handler();
- 8002484:	f000 f8f4 	bl	8002670 <Error_Handler>
+ 8002a74:	f000 f94c 	bl	8002d10 <Error_Handler>
   }
 
   /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8002488:	230f      	movs	r3, #15
- 800248a:	617b      	str	r3, [r7, #20]
+ 8002a78:	230f      	movs	r3, #15
+ 8002a7a:	617b      	str	r3, [r7, #20]
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- 800248c:	2302      	movs	r3, #2
- 800248e:	61bb      	str	r3, [r7, #24]
+ 8002a7c:	2302      	movs	r3, #2
+ 8002a7e:	61bb      	str	r3, [r7, #24]
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8002490:	2300      	movs	r3, #0
- 8002492:	61fb      	str	r3, [r7, #28]
+ 8002a80:	2300      	movs	r3, #0
+ 8002a82:	61fb      	str	r3, [r7, #28]
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
- 8002494:	f44f 6380 	mov.w	r3, #1024	@ 0x400
- 8002498:	623b      	str	r3, [r7, #32]
+ 8002a84:	f44f 6380 	mov.w	r3, #1024	@ 0x400
+ 8002a88:	623b      	str	r3, [r7, #32]
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
- 800249a:	f44f 6380 	mov.w	r3, #1024	@ 0x400
- 800249e:	627b      	str	r3, [r7, #36]	@ 0x24
+ 8002a8a:	f44f 6380 	mov.w	r3, #1024	@ 0x400
+ 8002a8e:	627b      	str	r3, [r7, #36]	@ 0x24
 
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 80024a0:	f107 0314 	add.w	r3, r7, #20
- 80024a4:	2100      	movs	r1, #0
- 80024a6:	4618      	mov	r0, r3
- 80024a8:	f002 fbd0 	bl	8004c4c <HAL_RCC_ClockConfig>
- 80024ac:	4603      	mov	r3, r0
- 80024ae:	2b00      	cmp	r3, #0
- 80024b0:	d001      	beq.n	80024b6 <SystemClock_Config+0x92>
+ 8002a90:	f107 0314 	add.w	r3, r7, #20
+ 8002a94:	2100      	movs	r1, #0
+ 8002a96:	4618      	mov	r0, r3
+ 8002a98:	f003 faec 	bl	8006074 <HAL_RCC_ClockConfig>
+ 8002a9c:	4603      	mov	r3, r0
+ 8002a9e:	2b00      	cmp	r3, #0
+ 8002aa0:	d001      	beq.n	8002aa6 <SystemClock_Config+0x92>
   {
     Error_Handler();
- 80024b2:	f000 f8dd 	bl	8002670 <Error_Handler>
+ 8002aa2:	f000 f935 	bl	8002d10 <Error_Handler>
   }
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
- 80024b6:	2302      	movs	r3, #2
- 80024b8:	607b      	str	r3, [r7, #4]
+ 8002aa6:	2302      	movs	r3, #2
+ 8002aa8:	607b      	str	r3, [r7, #4]
   PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8;
- 80024ba:	f44f 4340 	mov.w	r3, #49152	@ 0xc000
- 80024be:	60fb      	str	r3, [r7, #12]
+ 8002aaa:	f44f 4340 	mov.w	r3, #49152	@ 0xc000
+ 8002aae:	60fb      	str	r3, [r7, #12]
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
- 80024c0:	1d3b      	adds	r3, r7, #4
- 80024c2:	4618      	mov	r0, r3
- 80024c4:	f002 fd52 	bl	8004f6c <HAL_RCCEx_PeriphCLKConfig>
- 80024c8:	4603      	mov	r3, r0
- 80024ca:	2b00      	cmp	r3, #0
- 80024cc:	d001      	beq.n	80024d2 <SystemClock_Config+0xae>
+ 8002ab0:	1d3b      	adds	r3, r7, #4
+ 8002ab2:	4618      	mov	r0, r3
+ 8002ab4:	f003 fc6e 	bl	8006394 <HAL_RCCEx_PeriphCLKConfig>
+ 8002ab8:	4603      	mov	r3, r0
+ 8002aba:	2b00      	cmp	r3, #0
+ 8002abc:	d001      	beq.n	8002ac2 <SystemClock_Config+0xae>
   {
     Error_Handler();
- 80024ce:	f000 f8cf 	bl	8002670 <Error_Handler>
+ 8002abe:	f000 f927 	bl	8002d10 <Error_Handler>
   }
 }
- 80024d2:	bf00      	nop
- 80024d4:	3750      	adds	r7, #80	@ 0x50
- 80024d6:	46bd      	mov	sp, r7
- 80024d8:	bd80      	pop	{r7, pc}
+ 8002ac2:	bf00      	nop
+ 8002ac4:	3750      	adds	r7, #80	@ 0x50
+ 8002ac6:	46bd      	mov	sp, r7
+ 8002ac8:	bd80      	pop	{r7, pc}
 	...
 
-080024dc <FloatToString>:
+08002acc <FloatToString>:
  * @param val - value to be converted
  *
  * @return None.
 *******************************************************************************/
-void FloatToString(char * buf, double val)
+void FloatToString(char *buf, double val)
 {
- 80024dc:	b580      	push	{r7, lr}
- 80024de:	b08a      	sub	sp, #40	@ 0x28
- 80024e0:	af00      	add	r7, sp, #0
- 80024e2:	60f8      	str	r0, [r7, #12]
- 80024e4:	e9c7 2300 	strd	r2, r3, [r7]
-    long  intPart  = 0;
- 80024e8:	2300      	movs	r3, #0
- 80024ea:	627b      	str	r3, [r7, #36]	@ 0x24
-    short fracPart = 0;
- 80024ec:	2300      	movs	r3, #0
- 80024ee:	847b      	strh	r3, [r7, #34]	@ 0x22
-    short  charPos  = 0;
- 80024f0:	2300      	movs	r3, #0
- 80024f2:	843b      	strh	r3, [r7, #32]
-    char  localBuf[12] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
- 80024f4:	f107 0310 	add.w	r3, r7, #16
- 80024f8:	2200      	movs	r2, #0
- 80024fa:	601a      	str	r2, [r3, #0]
- 80024fc:	605a      	str	r2, [r3, #4]
- 80024fe:	609a      	str	r2, [r3, #8]
-    short  i = sizeof(localBuf) - 1;
- 8002500:	230b      	movs	r3, #11
- 8002502:	83fb      	strh	r3, [r7, #30]
+ 8002acc:	b5b0      	push	{r4, r5, r7, lr}
+ 8002ace:	b096      	sub	sp, #88	@ 0x58
+ 8002ad0:	af00      	add	r7, sp, #0
+ 8002ad2:	60f8      	str	r0, [r7, #12]
+ 8002ad4:	e9c7 2300 	strd	r2, r3, [r7]
+    char temp[20]; // Buffer auxiliar para construção segura
+    int i = 0;
+ 8002ad8:	2300      	movs	r3, #0
+ 8002ada:	657b      	str	r3, [r7, #84]	@ 0x54
 
-    intPart = (long)val;
- 8002504:	e9d7 0100 	ldrd	r0, r1, [r7]
- 8002508:	f7fe f90e 	bl	8000728 <__aeabi_d2iz>
- 800250c:	4603      	mov	r3, r0
- 800250e:	627b      	str	r3, [r7, #36]	@ 0x24
-    fracPart = (short)((val - intPart) * 1000 + 0.5);
- 8002510:	6a78      	ldr	r0, [r7, #36]	@ 0x24
- 8002512:	f7fe f89f 	bl	8000654 <__aeabi_i2d>
- 8002516:	4602      	mov	r2, r0
- 8002518:	460b      	mov	r3, r1
- 800251a:	e9d7 0100 	ldrd	r0, r1, [r7]
- 800251e:	f7fd ff4b 	bl	80003b8 <__aeabi_dsub>
- 8002522:	4602      	mov	r2, r0
- 8002524:	460b      	mov	r3, r1
- 8002526:	4610      	mov	r0, r2
- 8002528:	4619      	mov	r1, r3
- 800252a:	f04f 0200 	mov.w	r2, #0
- 800252e:	4b4d      	ldr	r3, [pc, #308]	@ (8002664 <FloatToString+0x188>)
- 8002530:	f7fd fe14 	bl	800015c <__aeabi_dmul>
- 8002534:	4602      	mov	r2, r0
- 8002536:	460b      	mov	r3, r1
- 8002538:	4610      	mov	r0, r2
- 800253a:	4619      	mov	r1, r3
- 800253c:	f04f 0200 	mov.w	r2, #0
- 8002540:	4b49      	ldr	r3, [pc, #292]	@ (8002668 <FloatToString+0x18c>)
- 8002542:	f7fd ff3b 	bl	80003bc <__adddf3>
- 8002546:	4602      	mov	r2, r0
- 8002548:	460b      	mov	r3, r1
- 800254a:	4610      	mov	r0, r2
- 800254c:	4619      	mov	r1, r3
- 800254e:	f7fe f8eb 	bl	8000728 <__aeabi_d2iz>
- 8002552:	4603      	mov	r3, r0
- 8002554:	847b      	strh	r3, [r7, #34]	@ 0x22
-    while(i > sizeof(localBuf) - 4)
- 8002556:	e025      	b.n	80025a4 <FloatToString+0xc8>
-    {
-        localBuf[i] = (fracPart % 10) + 0x30;
- 8002558:	f9b7 2022 	ldrsh.w	r2, [r7, #34]	@ 0x22
- 800255c:	4b43      	ldr	r3, [pc, #268]	@ (800266c <FloatToString+0x190>)
- 800255e:	fb83 1302 	smull	r1, r3, r3, r2
- 8002562:	1099      	asrs	r1, r3, #2
- 8002564:	17d3      	asrs	r3, r2, #31
- 8002566:	1ac9      	subs	r1, r1, r3
- 8002568:	460b      	mov	r3, r1
- 800256a:	009b      	lsls	r3, r3, #2
- 800256c:	440b      	add	r3, r1
- 800256e:	005b      	lsls	r3, r3, #1
- 8002570:	1ad3      	subs	r3, r2, r3
- 8002572:	b21b      	sxth	r3, r3
- 8002574:	b2da      	uxtb	r2, r3
- 8002576:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 800257a:	3230      	adds	r2, #48	@ 0x30
- 800257c:	b2d2      	uxtb	r2, r2
- 800257e:	3328      	adds	r3, #40	@ 0x28
- 8002580:	443b      	add	r3, r7
- 8002582:	f803 2c18 	strb.w	r2, [r3, #-24]
-        fracPart /= 10;
- 8002586:	f9b7 3022 	ldrsh.w	r3, [r7, #34]	@ 0x22
- 800258a:	4a38      	ldr	r2, [pc, #224]	@ (800266c <FloatToString+0x190>)
- 800258c:	fb82 1203 	smull	r1, r2, r2, r3
- 8002590:	1092      	asrs	r2, r2, #2
- 8002592:	17db      	asrs	r3, r3, #31
- 8002594:	1ad3      	subs	r3, r2, r3
- 8002596:	847b      	strh	r3, [r7, #34]	@ 0x22
-        i--;
- 8002598:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 800259c:	b29b      	uxth	r3, r3
- 800259e:	3b01      	subs	r3, #1
- 80025a0:	b29b      	uxth	r3, r3
- 80025a2:	83fb      	strh	r3, [r7, #30]
-    while(i > sizeof(localBuf) - 4)
- 80025a4:	8bfb      	ldrh	r3, [r7, #30]
- 80025a6:	2b08      	cmp	r3, #8
- 80025a8:	d8d6      	bhi.n	8002558 <FloatToString+0x7c>
+    // 1. Tratar sinal negativo
+    if (val < 0) {
+ 8002adc:	f04f 0200 	mov.w	r2, #0
+ 8002ae0:	f04f 0300 	mov.w	r3, #0
+ 8002ae4:	e9d7 0100 	ldrd	r0, r1, [r7]
+ 8002ae8:	f7fd ff68 	bl	80009bc <__aeabi_dcmplt>
+ 8002aec:	4603      	mov	r3, r0
+ 8002aee:	2b00      	cmp	r3, #0
+ 8002af0:	d00d      	beq.n	8002b0e <FloatToString+0x42>
+        temp[i++] = '-';
+ 8002af2:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8002af4:	1c5a      	adds	r2, r3, #1
+ 8002af6:	657a      	str	r2, [r7, #84]	@ 0x54
+ 8002af8:	3358      	adds	r3, #88	@ 0x58
+ 8002afa:	443b      	add	r3, r7
+ 8002afc:	222d      	movs	r2, #45	@ 0x2d
+ 8002afe:	f803 2c30 	strb.w	r2, [r3, #-48]
+        val = -val;
+ 8002b02:	683c      	ldr	r4, [r7, #0]
+ 8002b04:	687b      	ldr	r3, [r7, #4]
+ 8002b06:	f083 4500 	eor.w	r5, r3, #2147483648	@ 0x80000000
+ 8002b0a:	e9c7 4500 	strd	r4, r5, [r7]
     }
-    localBuf[i] = '.';
- 80025aa:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 80025ae:	3328      	adds	r3, #40	@ 0x28
- 80025b0:	443b      	add	r3, r7
- 80025b2:	222e      	movs	r2, #46	@ 0x2e
- 80025b4:	f803 2c18 	strb.w	r2, [r3, #-24]
-    if(intPart == 0)
- 80025b8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80025ba:	2b00      	cmp	r3, #0
- 80025bc:	d130      	bne.n	8002620 <FloatToString+0x144>
-    {
-        i --;
- 80025be:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 80025c2:	b29b      	uxth	r3, r3
- 80025c4:	3b01      	subs	r3, #1
- 80025c6:	b29b      	uxth	r3, r3
- 80025c8:	83fb      	strh	r3, [r7, #30]
-        localBuf[i] = '0';
- 80025ca:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 80025ce:	3328      	adds	r3, #40	@ 0x28
- 80025d0:	443b      	add	r3, r7
- 80025d2:	2230      	movs	r2, #48	@ 0x30
- 80025d4:	f803 2c18 	strb.w	r2, [r3, #-24]
+
+    // 2. Separar parte inteira e fracionária
+    long intPart = (long)val;
+ 8002b0e:	e9d7 0100 	ldrd	r0, r1, [r7]
+ 8002b12:	f7fd ff7b 	bl	8000a0c <__aeabi_d2iz>
+ 8002b16:	4603      	mov	r3, r0
+ 8002b18:	653b      	str	r3, [r7, #80]	@ 0x50
+    // Multiplicamos por 1000 para obter 3 casas decimais fixas
+    int fracPart = (int)((val - (double)intPart) * 1000.0 + 0.5);
+ 8002b1a:	6d38      	ldr	r0, [r7, #80]	@ 0x50
+ 8002b1c:	f7fd fc72 	bl	8000404 <__aeabi_i2d>
+ 8002b20:	4602      	mov	r2, r0
+ 8002b22:	460b      	mov	r3, r1
+ 8002b24:	e9d7 0100 	ldrd	r0, r1, [r7]
+ 8002b28:	f7fd fb1e 	bl	8000168 <__aeabi_dsub>
+ 8002b2c:	4602      	mov	r2, r0
+ 8002b2e:	460b      	mov	r3, r1
+ 8002b30:	4610      	mov	r0, r2
+ 8002b32:	4619      	mov	r1, r3
+ 8002b34:	f04f 0200 	mov.w	r2, #0
+ 8002b38:	4b6a      	ldr	r3, [pc, #424]	@ (8002ce4 <FloatToString+0x218>)
+ 8002b3a:	f7fd fccd 	bl	80004d8 <__aeabi_dmul>
+ 8002b3e:	4602      	mov	r2, r0
+ 8002b40:	460b      	mov	r3, r1
+ 8002b42:	4610      	mov	r0, r2
+ 8002b44:	4619      	mov	r1, r3
+ 8002b46:	f04f 0200 	mov.w	r2, #0
+ 8002b4a:	4b67      	ldr	r3, [pc, #412]	@ (8002ce8 <FloatToString+0x21c>)
+ 8002b4c:	f7fd fb0e 	bl	800016c <__adddf3>
+ 8002b50:	4602      	mov	r2, r0
+ 8002b52:	460b      	mov	r3, r1
+ 8002b54:	4610      	mov	r0, r2
+ 8002b56:	4619      	mov	r1, r3
+ 8002b58:	f7fd ff58 	bl	8000a0c <__aeabi_d2iz>
+ 8002b5c:	4603      	mov	r3, r0
+ 8002b5e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+
+    // 3. Converter a parte inteira para o buffer temp
+    // Usamos um buffer temporário de inversão para não precisar de lógica complexa de ponteiro
+    char intRev[12];
+    int j = 0;
+ 8002b60:	2300      	movs	r3, #0
+ 8002b62:	64fb      	str	r3, [r7, #76]	@ 0x4c
+
+    if (intPart == 0) {
+ 8002b64:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8002b66:	2b00      	cmp	r3, #0
+ 8002b68:	d126      	bne.n	8002bb8 <FloatToString+0xec>
+        intRev[j++] = '0';
+ 8002b6a:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8002b6c:	1c5a      	adds	r2, r3, #1
+ 8002b6e:	64fa      	str	r2, [r7, #76]	@ 0x4c
+ 8002b70:	3358      	adds	r3, #88	@ 0x58
+ 8002b72:	443b      	add	r3, r7
+ 8002b74:	2230      	movs	r2, #48	@ 0x30
+ 8002b76:	f803 2c3c 	strb.w	r2, [r3, #-60]
+ 8002b7a:	e020      	b.n	8002bbe <FloatToString+0xf2>
+    } else {
+        while (intPart > 0) {
+            intRev[j++] = (intPart % 10) + '0';
+ 8002b7c:	6d3a      	ldr	r2, [r7, #80]	@ 0x50
+ 8002b7e:	4b5b      	ldr	r3, [pc, #364]	@ (8002cec <FloatToString+0x220>)
+ 8002b80:	fb83 1302 	smull	r1, r3, r3, r2
+ 8002b84:	1099      	asrs	r1, r3, #2
+ 8002b86:	17d3      	asrs	r3, r2, #31
+ 8002b88:	1ac9      	subs	r1, r1, r3
+ 8002b8a:	460b      	mov	r3, r1
+ 8002b8c:	009b      	lsls	r3, r3, #2
+ 8002b8e:	440b      	add	r3, r1
+ 8002b90:	005b      	lsls	r3, r3, #1
+ 8002b92:	1ad1      	subs	r1, r2, r3
+ 8002b94:	b2ca      	uxtb	r2, r1
+ 8002b96:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8002b98:	1c59      	adds	r1, r3, #1
+ 8002b9a:	64f9      	str	r1, [r7, #76]	@ 0x4c
+ 8002b9c:	3230      	adds	r2, #48	@ 0x30
+ 8002b9e:	b2d2      	uxtb	r2, r2
+ 8002ba0:	3358      	adds	r3, #88	@ 0x58
+ 8002ba2:	443b      	add	r3, r7
+ 8002ba4:	f803 2c3c 	strb.w	r2, [r3, #-60]
+            intPart /= 10;
+ 8002ba8:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8002baa:	4a50      	ldr	r2, [pc, #320]	@ (8002cec <FloatToString+0x220>)
+ 8002bac:	fb82 1203 	smull	r1, r2, r2, r3
+ 8002bb0:	1092      	asrs	r2, r2, #2
+ 8002bb2:	17db      	asrs	r3, r3, #31
+ 8002bb4:	1ad3      	subs	r3, r2, r3
+ 8002bb6:	653b      	str	r3, [r7, #80]	@ 0x50
+        while (intPart > 0) {
+ 8002bb8:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8002bba:	2b00      	cmp	r3, #0
+ 8002bbc:	dcde      	bgt.n	8002b7c <FloatToString+0xb0>
+        }
     }
-    while(intPart)
- 80025d8:	e022      	b.n	8002620 <FloatToString+0x144>
-    {
-        i --;
- 80025da:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 80025de:	b29b      	uxth	r3, r3
- 80025e0:	3b01      	subs	r3, #1
- 80025e2:	b29b      	uxth	r3, r3
- 80025e4:	83fb      	strh	r3, [r7, #30]
-        localBuf[i] =(intPart % 10)  + 0x30;
- 80025e6:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 80025e8:	4b20      	ldr	r3, [pc, #128]	@ (800266c <FloatToString+0x190>)
- 80025ea:	fb83 1302 	smull	r1, r3, r3, r2
- 80025ee:	1099      	asrs	r1, r3, #2
- 80025f0:	17d3      	asrs	r3, r2, #31
- 80025f2:	1ac9      	subs	r1, r1, r3
- 80025f4:	460b      	mov	r3, r1
- 80025f6:	009b      	lsls	r3, r3, #2
- 80025f8:	440b      	add	r3, r1
- 80025fa:	005b      	lsls	r3, r3, #1
- 80025fc:	1ad1      	subs	r1, r2, r3
- 80025fe:	b2ca      	uxtb	r2, r1
- 8002600:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
- 8002604:	3230      	adds	r2, #48	@ 0x30
- 8002606:	b2d2      	uxtb	r2, r2
- 8002608:	3328      	adds	r3, #40	@ 0x28
- 800260a:	443b      	add	r3, r7
- 800260c:	f803 2c18 	strb.w	r2, [r3, #-24]
-        intPart /= 10;
- 8002610:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8002612:	4a16      	ldr	r2, [pc, #88]	@ (800266c <FloatToString+0x190>)
- 8002614:	fb82 1203 	smull	r1, r2, r2, r3
- 8002618:	1092      	asrs	r2, r2, #2
- 800261a:	17db      	asrs	r3, r3, #31
- 800261c:	1ad3      	subs	r3, r2, r3
- 800261e:	627b      	str	r3, [r7, #36]	@ 0x24
-    while(intPart)
- 8002620:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8002622:	2b00      	cmp	r3, #0
- 8002624:	d1d9      	bne.n	80025da <FloatToString+0xfe>
+
+    // Inverter a parte inteira de volta para o buffer principal
+    for (int k = j - 1; k >= 0; k--) {
+ 8002bbe:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8002bc0:	3b01      	subs	r3, #1
+ 8002bc2:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8002bc4:	e00e      	b.n	8002be4 <FloatToString+0x118>
+        temp[i++] = intRev[k];
+ 8002bc6:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8002bc8:	1c5a      	adds	r2, r3, #1
+ 8002bca:	657a      	str	r2, [r7, #84]	@ 0x54
+ 8002bcc:	f107 011c 	add.w	r1, r7, #28
+ 8002bd0:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 8002bd2:	440a      	add	r2, r1
+ 8002bd4:	7812      	ldrb	r2, [r2, #0]
+ 8002bd6:	3358      	adds	r3, #88	@ 0x58
+ 8002bd8:	443b      	add	r3, r7
+ 8002bda:	f803 2c30 	strb.w	r2, [r3, #-48]
+    for (int k = j - 1; k >= 0; k--) {
+ 8002bde:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 8002be0:	3b01      	subs	r3, #1
+ 8002be2:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8002be4:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 8002be6:	2b00      	cmp	r3, #0
+ 8002be8:	daed      	bge.n	8002bc6 <FloatToString+0xfa>
     }
-    for(charPos = i; charPos < sizeof(localBuf); charPos ++)
- 8002626:	8bfb      	ldrh	r3, [r7, #30]
- 8002628:	843b      	strh	r3, [r7, #32]
- 800262a:	e010      	b.n	800264e <FloatToString+0x172>
-    {
-        *buf = localBuf[charPos];
- 800262c:	f9b7 3020 	ldrsh.w	r3, [r7, #32]
- 8002630:	3328      	adds	r3, #40	@ 0x28
- 8002632:	443b      	add	r3, r7
- 8002634:	f813 2c18 	ldrb.w	r2, [r3, #-24]
- 8002638:	68fb      	ldr	r3, [r7, #12]
- 800263a:	701a      	strb	r2, [r3, #0]
-        buf ++;
- 800263c:	68fb      	ldr	r3, [r7, #12]
- 800263e:	3301      	adds	r3, #1
- 8002640:	60fb      	str	r3, [r7, #12]
-    for(charPos = i; charPos < sizeof(localBuf); charPos ++)
- 8002642:	f9b7 3020 	ldrsh.w	r3, [r7, #32]
- 8002646:	b29b      	uxth	r3, r3
- 8002648:	3301      	adds	r3, #1
- 800264a:	b29b      	uxth	r3, r3
- 800264c:	843b      	strh	r3, [r7, #32]
- 800264e:	8c3b      	ldrh	r3, [r7, #32]
- 8002650:	2b0b      	cmp	r3, #11
- 8002652:	d9eb      	bls.n	800262c <FloatToString+0x150>
+
+    // 4. Adicionar o ponto decimal e a parte fracionária (sempre 3 casas)
+    temp[i++] = '.';
+ 8002bea:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8002bec:	1c5a      	adds	r2, r3, #1
+ 8002bee:	657a      	str	r2, [r7, #84]	@ 0x54
+ 8002bf0:	3358      	adds	r3, #88	@ 0x58
+ 8002bf2:	443b      	add	r3, r7
+ 8002bf4:	222e      	movs	r2, #46	@ 0x2e
+ 8002bf6:	f803 2c30 	strb.w	r2, [r3, #-48]
+
+    // Garantir que a parte fracionária tenha sempre 3 dígitos (ex: .005 em vez de .5)
+    int fracBuffer[3];
+    fracBuffer[2] = fracPart % 10;          // Unidade
+ 8002bfa:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
+ 8002bfc:	4b3b      	ldr	r3, [pc, #236]	@ (8002cec <FloatToString+0x220>)
+ 8002bfe:	fb83 2301 	smull	r2, r3, r3, r1
+ 8002c02:	109a      	asrs	r2, r3, #2
+ 8002c04:	17cb      	asrs	r3, r1, #31
+ 8002c06:	1ad2      	subs	r2, r2, r3
+ 8002c08:	4613      	mov	r3, r2
+ 8002c0a:	009b      	lsls	r3, r3, #2
+ 8002c0c:	4413      	add	r3, r2
+ 8002c0e:	005b      	lsls	r3, r3, #1
+ 8002c10:	1aca      	subs	r2, r1, r3
+ 8002c12:	61ba      	str	r2, [r7, #24]
+    fracBuffer[1] = (fracPart / 10) % 10;   // Dezena
+ 8002c14:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8002c16:	4a35      	ldr	r2, [pc, #212]	@ (8002cec <FloatToString+0x220>)
+ 8002c18:	fb82 1203 	smull	r1, r2, r2, r3
+ 8002c1c:	1092      	asrs	r2, r2, #2
+ 8002c1e:	17db      	asrs	r3, r3, #31
+ 8002c20:	1ad1      	subs	r1, r2, r3
+ 8002c22:	4b32      	ldr	r3, [pc, #200]	@ (8002cec <FloatToString+0x220>)
+ 8002c24:	fb83 2301 	smull	r2, r3, r3, r1
+ 8002c28:	109a      	asrs	r2, r3, #2
+ 8002c2a:	17cb      	asrs	r3, r1, #31
+ 8002c2c:	1ad2      	subs	r2, r2, r3
+ 8002c2e:	4613      	mov	r3, r2
+ 8002c30:	009b      	lsls	r3, r3, #2
+ 8002c32:	4413      	add	r3, r2
+ 8002c34:	005b      	lsls	r3, r3, #1
+ 8002c36:	1aca      	subs	r2, r1, r3
+ 8002c38:	617a      	str	r2, [r7, #20]
+    fracBuffer[0] = (fracPart / 100) % 10;  // Centena
+ 8002c3a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8002c3c:	4a2c      	ldr	r2, [pc, #176]	@ (8002cf0 <FloatToString+0x224>)
+ 8002c3e:	fb82 1203 	smull	r1, r2, r2, r3
+ 8002c42:	1152      	asrs	r2, r2, #5
+ 8002c44:	17db      	asrs	r3, r3, #31
+ 8002c46:	1ad1      	subs	r1, r2, r3
+ 8002c48:	4b28      	ldr	r3, [pc, #160]	@ (8002cec <FloatToString+0x220>)
+ 8002c4a:	fb83 2301 	smull	r2, r3, r3, r1
+ 8002c4e:	109a      	asrs	r2, r3, #2
+ 8002c50:	17cb      	asrs	r3, r1, #31
+ 8002c52:	1ad2      	subs	r2, r2, r3
+ 8002c54:	4613      	mov	r3, r2
+ 8002c56:	009b      	lsls	r3, r3, #2
+ 8002c58:	4413      	add	r3, r2
+ 8002c5a:	005b      	lsls	r3, r3, #1
+ 8002c5c:	1aca      	subs	r2, r1, r3
+ 8002c5e:	613a      	str	r2, [r7, #16]
+
+    for (int k = 2; k >= 0; k--) {
+ 8002c60:	2302      	movs	r3, #2
+ 8002c62:	647b      	str	r3, [r7, #68]	@ 0x44
+ 8002c64:	e012      	b.n	8002c8c <FloatToString+0x1c0>
+        temp[i++] = fracBuffer[k] + '0';
+ 8002c66:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8002c68:	009b      	lsls	r3, r3, #2
+ 8002c6a:	3358      	adds	r3, #88	@ 0x58
+ 8002c6c:	443b      	add	r3, r7
+ 8002c6e:	f853 3c48 	ldr.w	r3, [r3, #-72]
+ 8002c72:	b2da      	uxtb	r2, r3
+ 8002c74:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8002c76:	1c59      	adds	r1, r3, #1
+ 8002c78:	6579      	str	r1, [r7, #84]	@ 0x54
+ 8002c7a:	3230      	adds	r2, #48	@ 0x30
+ 8002c7c:	b2d2      	uxtb	r2, r2
+ 8002c7e:	3358      	adds	r3, #88	@ 0x58
+ 8002c80:	443b      	add	r3, r7
+ 8002c82:	f803 2c30 	strb.w	r2, [r3, #-48]
+    for (int k = 2; k >= 0; k--) {
+ 8002c86:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8002c88:	3b01      	subs	r3, #1
+ 8002c8a:	647b      	str	r3, [r7, #68]	@ 0x44
+ 8002c8c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8002c8e:	2b00      	cmp	r3, #0
+ 8002c90:	dae9      	bge.n	8002c66 <FloatToString+0x19a>
     }
-	*buf = 0;
- 8002654:	68fb      	ldr	r3, [r7, #12]
- 8002656:	2200      	movs	r2, #0
- 8002658:	701a      	strb	r2, [r3, #0]
+
+    // 5. Finalizar a string com o caractere nulo
+    temp[i] = '\0';
+ 8002c92:	f107 0228 	add.w	r2, r7, #40	@ 0x28
+ 8002c96:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8002c98:	4413      	add	r3, r2
+ 8002c9a:	2200      	movs	r2, #0
+ 8002c9c:	701a      	strb	r2, [r3, #0]
+
+    // 6. Copiar para o buffer de destino final (sem risco de lixo)
+    int destIdx = 0;
+ 8002c9e:	2300      	movs	r3, #0
+ 8002ca0:	643b      	str	r3, [r7, #64]	@ 0x40
+    while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
+ 8002ca2:	e00b      	b.n	8002cbc <FloatToString+0x1f0>
+        buf[destIdx] = temp[destIdx];
+ 8002ca4:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8002ca6:	68fa      	ldr	r2, [r7, #12]
+ 8002ca8:	4413      	add	r3, r2
+ 8002caa:	f107 0128 	add.w	r1, r7, #40	@ 0x28
+ 8002cae:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 8002cb0:	440a      	add	r2, r1
+ 8002cb2:	7812      	ldrb	r2, [r2, #0]
+ 8002cb4:	701a      	strb	r2, [r3, #0]
+        destIdx++;
+ 8002cb6:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8002cb8:	3301      	adds	r3, #1
+ 8002cba:	643b      	str	r3, [r7, #64]	@ 0x40
+    while (temp[destIdx] != '\0' && destIdx < 15) { // Limite de segurança
+ 8002cbc:	f107 0228 	add.w	r2, r7, #40	@ 0x28
+ 8002cc0:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8002cc2:	4413      	add	r3, r2
+ 8002cc4:	781b      	ldrb	r3, [r3, #0]
+ 8002cc6:	2b00      	cmp	r3, #0
+ 8002cc8:	d002      	beq.n	8002cd0 <FloatToString+0x204>
+ 8002cca:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8002ccc:	2b0e      	cmp	r3, #14
+ 8002cce:	dde9      	ble.n	8002ca4 <FloatToString+0x1d8>
+    }
+    buf[destIdx] = '\0';
+ 8002cd0:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8002cd2:	68fa      	ldr	r2, [r7, #12]
+ 8002cd4:	4413      	add	r3, r2
+ 8002cd6:	2200      	movs	r2, #0
+ 8002cd8:	701a      	strb	r2, [r3, #0]
 }
- 800265a:	bf00      	nop
- 800265c:	3728      	adds	r7, #40	@ 0x28
- 800265e:	46bd      	mov	sp, r7
- 8002660:	bd80      	pop	{r7, pc}
- 8002662:	bf00      	nop
- 8002664:	408f4000 	.word	0x408f4000
- 8002668:	3fe00000 	.word	0x3fe00000
- 800266c:	66666667 	.word	0x66666667
+ 8002cda:	bf00      	nop
+ 8002cdc:	3758      	adds	r7, #88	@ 0x58
+ 8002cde:	46bd      	mov	sp, r7
+ 8002ce0:	bdb0      	pop	{r4, r5, r7, pc}
+ 8002ce2:	bf00      	nop
+ 8002ce4:	408f4000 	.word	0x408f4000
+ 8002ce8:	3fe00000 	.word	0x3fe00000
+ 8002cec:	66666667 	.word	0x66666667
+ 8002cf0:	51eb851f 	.word	0x51eb851f
 
-08002670 <Error_Handler>:
+08002cf4 <HAL_ADC_ConvCpltCallback>:
+    }
+}
+
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ 8002cf4:	b480      	push	{r7}
+ 8002cf6:	b083      	sub	sp, #12
+ 8002cf8:	af00      	add	r7, sp, #0
+ 8002cfa:	6078      	str	r0, [r7, #4]
+     UpdateEvent = 1;
+ 8002cfc:	4b03      	ldr	r3, [pc, #12]	@ (8002d0c <HAL_ADC_ConvCpltCallback+0x18>)
+ 8002cfe:	2201      	movs	r2, #1
+ 8002d00:	701a      	strb	r2, [r3, #0]
+}
+ 8002d02:	bf00      	nop
+ 8002d04:	370c      	adds	r7, #12
+ 8002d06:	46bd      	mov	sp, r7
+ 8002d08:	bc80      	pop	{r7}
+ 8002d0a:	4770      	bx	lr
+ 8002d0c:	200006b0 	.word	0x200006b0
+
+08002d10 <Error_Handler>:
 /**
   * @brief  This function is executed in case of error occurrence.
   * @retval None
   */
 void Error_Handler(void)
 {
- 8002670:	b480      	push	{r7}
- 8002672:	af00      	add	r7, sp, #0
+ 8002d10:	b480      	push	{r7}
+ 8002d12:	af00      	add	r7, sp, #0
   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_irq(void)
 {
   __ASM volatile ("cpsid i" : : : "memory");
- 8002674:	b672      	cpsid	i
+ 8002d14:	b672      	cpsid	i
 }
- 8002676:	bf00      	nop
+ 8002d16:	bf00      	nop
   /* USER CODE BEGIN Error_Handler_Debug */
   /* User can add his own implementation to report the HAL error return state */
   __disable_irq();
   while (1)
- 8002678:	bf00      	nop
- 800267a:	e7fd      	b.n	8002678 <Error_Handler+0x8>
+ 8002d18:	bf00      	nop
+ 8002d1a:	e7fd      	b.n	8002d18 <Error_Handler+0x8>
 
-0800267c <LL_GPIO_ReadInputPort>:
+08002d1c <LL_GPIO_ReadInputPort>:
   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
   * @param  GPIOx GPIO Port
   * @retval Input data register value of port
   */
 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
 {
- 800267c:	b480      	push	{r7}
- 800267e:	b083      	sub	sp, #12
- 8002680:	af00      	add	r7, sp, #0
- 8002682:	6078      	str	r0, [r7, #4]
+ 8002d1c:	b480      	push	{r7}
+ 8002d1e:	b083      	sub	sp, #12
+ 8002d20:	af00      	add	r7, sp, #0
+ 8002d22:	6078      	str	r0, [r7, #4]
   return (READ_REG(GPIOx->IDR));
- 8002684:	687b      	ldr	r3, [r7, #4]
- 8002686:	689b      	ldr	r3, [r3, #8]
+ 8002d24:	687b      	ldr	r3, [r7, #4]
+ 8002d26:	689b      	ldr	r3, [r3, #8]
 }
- 8002688:	4618      	mov	r0, r3
- 800268a:	370c      	adds	r7, #12
- 800268c:	46bd      	mov	sp, r7
- 800268e:	bc80      	pop	{r7}
- 8002690:	4770      	bx	lr
+ 8002d28:	4618      	mov	r0, r3
+ 8002d2a:	370c      	adds	r7, #12
+ 8002d2c:	46bd      	mov	sp, r7
+ 8002d2e:	bc80      	pop	{r7}
+ 8002d30:	4770      	bx	lr
 	...
 
-08002694 <rs485_init>:
+08002d34 <rs485_init>:
 /**
  * @brief Initializes the RS-485 driver.
  * @note This function configures GPIOs for address detection and USART1 for communication.
  */
 void rs485_init(void)
 {
- 8002694:	b580      	push	{r7, lr}
- 8002696:	af00      	add	r7, sp, #0
+ 8002d34:	b580      	push	{r7, lr}
+ 8002d36:	af00      	add	r7, sp, #0
     /* Configure GPIOs for address detection */
     rs485_configure_gpio_address();
- 8002698:	f000 f864 	bl	8002764 <rs485_configure_gpio_address>
+ 8002d38:	f000 f864 	bl	8002e04 <rs485_configure_gpio_address>
 
     /* Configure USART1 for RS-485 communication */
     rs485_configure_usart1();
- 800269c:	f000 f8a8 	bl	80027f0 <rs485_configure_usart1>
+ 8002d3c:	f000 f8a8 	bl	8002e90 <rs485_configure_usart1>
 
     /* Get the current device address from GPIOs */
     device_address.full_address = rs485_get_address();
- 80026a0:	f000 f808 	bl	80026b4 <rs485_get_address>
- 80026a4:	4603      	mov	r3, r0
- 80026a6:	461a      	mov	r2, r3
- 80026a8:	4b01      	ldr	r3, [pc, #4]	@ (80026b0 <rs485_init+0x1c>)
- 80026aa:	709a      	strb	r2, [r3, #2]
+ 8002d40:	f000 f808 	bl	8002d54 <rs485_get_address>
+ 8002d44:	4603      	mov	r3, r0
+ 8002d46:	461a      	mov	r2, r3
+ 8002d48:	4b01      	ldr	r3, [pc, #4]	@ (8002d50 <rs485_init+0x1c>)
+ 8002d4a:	709a      	strb	r2, [r3, #2]
 }
- 80026ac:	bf00      	nop
- 80026ae:	bd80      	pop	{r7, pc}
- 80026b0:	2000028c 	.word	0x2000028c
+ 8002d4c:	bf00      	nop
+ 8002d4e:	bd80      	pop	{r7, pc}
+ 8002d50:	200006d4 	.word	0x200006d4
 
-080026b4 <rs485_get_address>:
+08002d54 <rs485_get_address>:
 /**
  * @brief Gets the current device address from GPIOs.
  * @return The 8-bit device address.
  */
 uint8_t rs485_get_address(void)
 {
- 80026b4:	b598      	push	{r3, r4, r7, lr}
- 80026b6:	af00      	add	r7, sp, #0
+ 8002d54:	b598      	push	{r3, r4, r7, lr}
+ 8002d56:	af00      	add	r7, sp, #0
     return ((uint8_t) ((((LL_GPIO_ReadInputPort(GPIOB) & RS485_ADDR_MASK_HIGH)>>RS485_ADDR_BIT_SET_HIGH) | (LL_GPIO_ReadInputPort(GPIOA) & RS485_ADDR_MASK_LOW)>>RS485_ADDR_BIT_SET_LOW)));
- 80026b8:	480a      	ldr	r0, [pc, #40]	@ (80026e4 <rs485_get_address+0x30>)
- 80026ba:	f7ff ffdf 	bl	800267c <LL_GPIO_ReadInputPort>
- 80026be:	4603      	mov	r3, r0
- 80026c0:	0a1b      	lsrs	r3, r3, #8
- 80026c2:	b2db      	uxtb	r3, r3
- 80026c4:	f023 030f 	bic.w	r3, r3, #15
- 80026c8:	b2dc      	uxtb	r4, r3
- 80026ca:	4807      	ldr	r0, [pc, #28]	@ (80026e8 <rs485_get_address+0x34>)
- 80026cc:	f7ff ffd6 	bl	800267c <LL_GPIO_ReadInputPort>
- 80026d0:	4603      	mov	r3, r0
- 80026d2:	089b      	lsrs	r3, r3, #2
- 80026d4:	b2db      	uxtb	r3, r3
- 80026d6:	f003 030f 	and.w	r3, r3, #15
- 80026da:	b2db      	uxtb	r3, r3
- 80026dc:	4323      	orrs	r3, r4
- 80026de:	b2db      	uxtb	r3, r3
+ 8002d58:	480a      	ldr	r0, [pc, #40]	@ (8002d84 <rs485_get_address+0x30>)
+ 8002d5a:	f7ff ffdf 	bl	8002d1c <LL_GPIO_ReadInputPort>
+ 8002d5e:	4603      	mov	r3, r0
+ 8002d60:	0a1b      	lsrs	r3, r3, #8
+ 8002d62:	b2db      	uxtb	r3, r3
+ 8002d64:	f023 030f 	bic.w	r3, r3, #15
+ 8002d68:	b2dc      	uxtb	r4, r3
+ 8002d6a:	4807      	ldr	r0, [pc, #28]	@ (8002d88 <rs485_get_address+0x34>)
+ 8002d6c:	f7ff ffd6 	bl	8002d1c <LL_GPIO_ReadInputPort>
+ 8002d70:	4603      	mov	r3, r0
+ 8002d72:	089b      	lsrs	r3, r3, #2
+ 8002d74:	b2db      	uxtb	r3, r3
+ 8002d76:	f003 030f 	and.w	r3, r3, #15
+ 8002d7a:	b2db      	uxtb	r3, r3
+ 8002d7c:	4323      	orrs	r3, r4
+ 8002d7e:	b2db      	uxtb	r3, r3
 }
- 80026e0:	4618      	mov	r0, r3
- 80026e2:	bd98      	pop	{r3, r4, r7, pc}
- 80026e4:	40010c00 	.word	0x40010c00
- 80026e8:	40010800 	.word	0x40010800
+ 8002d80:	4618      	mov	r0, r3
+ 8002d82:	bd98      	pop	{r3, r4, r7, pc}
+ 8002d84:	40010c00 	.word	0x40010c00
+ 8002d88:	40010800 	.word	0x40010800
 
-080026ec <rs485_send_broadcast>:
+08002d8c <rs485_send_broadcast>:
  * @param data Pointer to the data buffer.
  * @param length Number of bytes to send.
  * @retval HAL_OK on success, otherwise error code.
  */
 HAL_StatusTypeDef rs485_send_broadcast(uint8_t* data, uint16_t length)
 {
- 80026ec:	b580      	push	{r7, lr}
- 80026ee:	b084      	sub	sp, #16
- 80026f0:	af00      	add	r7, sp, #0
- 80026f2:	6078      	str	r0, [r7, #4]
- 80026f4:	460b      	mov	r3, r1
- 80026f6:	807b      	strh	r3, [r7, #2]
+ 8002d8c:	b580      	push	{r7, lr}
+ 8002d8e:	b084      	sub	sp, #16
+ 8002d90:	af00      	add	r7, sp, #0
+ 8002d92:	6078      	str	r0, [r7, #4]
+ 8002d94:	460b      	mov	r3, r1
+ 8002d96:	807b      	strh	r3, [r7, #2]
     /* Enable transmission mode */
     rs485_enable_tx();
- 80026f8:	f000 f81c 	bl	8002734 <rs485_enable_tx>
+ 8002d98:	f000 f81c 	bl	8002dd4 <rs485_enable_tx>
 
     /* Send the broadcast address (0x00) first */
     uint8_t broadcast_address = 0x00;
- 80026fc:	2300      	movs	r3, #0
- 80026fe:	73bb      	strb	r3, [r7, #14]
+ 8002d9c:	2300      	movs	r3, #0
+ 8002d9e:	73bb      	strb	r3, [r7, #14]
     HAL_UART_Transmit(&huart1, &broadcast_address, 1, HAL_MAX_DELAY);
- 8002700:	f107 010e 	add.w	r1, r7, #14
- 8002704:	f04f 33ff 	mov.w	r3, #4294967295
- 8002708:	2201      	movs	r2, #1
- 800270a:	4809      	ldr	r0, [pc, #36]	@ (8002730 <rs485_send_broadcast+0x44>)
- 800270c:	f002 fd34 	bl	8005178 <HAL_UART_Transmit>
+ 8002da0:	f107 010e 	add.w	r1, r7, #14
+ 8002da4:	f04f 33ff 	mov.w	r3, #4294967295
+ 8002da8:	2201      	movs	r2, #1
+ 8002daa:	4809      	ldr	r0, [pc, #36]	@ (8002dd0 <rs485_send_broadcast+0x44>)
+ 8002dac:	f003 ff72 	bl	8006c94 <HAL_UART_Transmit>
 
     /* Send the data */
     HAL_StatusTypeDef status = HAL_UART_Transmit(&huart1, data, length, HAL_MAX_DELAY);
- 8002710:	887a      	ldrh	r2, [r7, #2]
- 8002712:	f04f 33ff 	mov.w	r3, #4294967295
- 8002716:	6879      	ldr	r1, [r7, #4]
- 8002718:	4805      	ldr	r0, [pc, #20]	@ (8002730 <rs485_send_broadcast+0x44>)
- 800271a:	f002 fd2d 	bl	8005178 <HAL_UART_Transmit>
- 800271e:	4603      	mov	r3, r0
- 8002720:	73fb      	strb	r3, [r7, #15]
+ 8002db0:	887a      	ldrh	r2, [r7, #2]
+ 8002db2:	f04f 33ff 	mov.w	r3, #4294967295
+ 8002db6:	6879      	ldr	r1, [r7, #4]
+ 8002db8:	4805      	ldr	r0, [pc, #20]	@ (8002dd0 <rs485_send_broadcast+0x44>)
+ 8002dba:	f003 ff6b 	bl	8006c94 <HAL_UART_Transmit>
+ 8002dbe:	4603      	mov	r3, r0
+ 8002dc0:	73fb      	strb	r3, [r7, #15]
 
     /* Disable transmission mode after sending */
     rs485_disable_tx();
- 8002722:	f000 f813 	bl	800274c <rs485_disable_tx>
+ 8002dc2:	f000 f813 	bl	8002dec <rs485_disable_tx>
 
     return status;
- 8002726:	7bfb      	ldrb	r3, [r7, #15]
+ 8002dc6:	7bfb      	ldrb	r3, [r7, #15]
 }
- 8002728:	4618      	mov	r0, r3
- 800272a:	3710      	adds	r7, #16
- 800272c:	46bd      	mov	sp, r7
- 800272e:	bd80      	pop	{r7, pc}
- 8002730:	20000290 	.word	0x20000290
+ 8002dc8:	4618      	mov	r0, r3
+ 8002dca:	3710      	adds	r7, #16
+ 8002dcc:	46bd      	mov	sp, r7
+ 8002dce:	bd80      	pop	{r7, pc}
+ 8002dd0:	200006d8 	.word	0x200006d8
 
-08002734 <rs485_enable_tx>:
+08002dd4 <rs485_enable_tx>:
 
 /**
  * @brief Enables transmission mode on RS-485 transceiver.
  */
 void rs485_enable_tx(void)
 {
- 8002734:	b580      	push	{r7, lr}
- 8002736:	af00      	add	r7, sp, #0
+ 8002dd4:	b580      	push	{r7, lr}
+ 8002dd6:	af00      	add	r7, sp, #0
     /* Set TX EN pin high to enable transmitter */
     HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_SET);
- 8002738:	2201      	movs	r2, #1
- 800273a:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
- 800273e:	4802      	ldr	r0, [pc, #8]	@ (8002748 <rs485_enable_tx+0x14>)
- 8002740:	f000 ff9d 	bl	800367e <HAL_GPIO_WritePin>
+ 8002dd8:	2201      	movs	r2, #1
+ 8002dda:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
+ 8002dde:	4802      	ldr	r0, [pc, #8]	@ (8002de8 <rs485_enable_tx+0x14>)
+ 8002de0:	f001 fe61 	bl	8004aa6 <HAL_GPIO_WritePin>
 }
- 8002744:	bf00      	nop
- 8002746:	bd80      	pop	{r7, pc}
- 8002748:	40010800 	.word	0x40010800
+ 8002de4:	bf00      	nop
+ 8002de6:	bd80      	pop	{r7, pc}
+ 8002de8:	40010800 	.word	0x40010800
 
-0800274c <rs485_disable_tx>:
+08002dec <rs485_disable_tx>:
 
 /**
  * @brief Disables transmission mode on RS-485 transceiver.
  */
 void rs485_disable_tx(void)
 {
- 800274c:	b580      	push	{r7, lr}
- 800274e:	af00      	add	r7, sp, #0
+ 8002dec:	b580      	push	{r7, lr}
+ 8002dee:	af00      	add	r7, sp, #0
     /* Set TX EN pin low to disable transmitter */
     HAL_GPIO_WritePin(RS485_TX_EN_PORT, RS485_TX_EN_PIN, GPIO_PIN_RESET);
- 8002750:	2200      	movs	r2, #0
- 8002752:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
- 8002756:	4802      	ldr	r0, [pc, #8]	@ (8002760 <rs485_disable_tx+0x14>)
- 8002758:	f000 ff91 	bl	800367e <HAL_GPIO_WritePin>
+ 8002df0:	2200      	movs	r2, #0
+ 8002df2:	f44f 5180 	mov.w	r1, #4096	@ 0x1000
+ 8002df6:	4802      	ldr	r0, [pc, #8]	@ (8002e00 <rs485_disable_tx+0x14>)
+ 8002df8:	f001 fe55 	bl	8004aa6 <HAL_GPIO_WritePin>
 }
- 800275c:	bf00      	nop
- 800275e:	bd80      	pop	{r7, pc}
- 8002760:	40010800 	.word	0x40010800
+ 8002dfc:	bf00      	nop
+ 8002dfe:	bd80      	pop	{r7, pc}
+ 8002e00:	40010800 	.word	0x40010800
 
-08002764 <rs485_configure_gpio_address>:
+08002e04 <rs485_configure_gpio_address>:
 
 /**
  * @brief Configures GPIOs for address detection.
  */
 static void rs485_configure_gpio_address(void)
 {
- 8002764:	b580      	push	{r7, lr}
- 8002766:	b086      	sub	sp, #24
- 8002768:	af00      	add	r7, sp, #0
+ 8002e04:	b580      	push	{r7, lr}
+ 8002e06:	b086      	sub	sp, #24
+ 8002e08:	af00      	add	r7, sp, #0
     GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800276a:	f107 0308 	add.w	r3, r7, #8
- 800276e:	2200      	movs	r2, #0
- 8002770:	601a      	str	r2, [r3, #0]
- 8002772:	605a      	str	r2, [r3, #4]
- 8002774:	609a      	str	r2, [r3, #8]
- 8002776:	60da      	str	r2, [r3, #12]
+ 8002e0a:	f107 0308 	add.w	r3, r7, #8
+ 8002e0e:	2200      	movs	r2, #0
+ 8002e10:	601a      	str	r2, [r3, #0]
+ 8002e12:	605a      	str	r2, [r3, #4]
+ 8002e14:	609a      	str	r2, [r3, #8]
+ 8002e16:	60da      	str	r2, [r3, #12]
 
     /* Enable clock for GPIOA and GPIOB */
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 8002778:	4b1a      	ldr	r3, [pc, #104]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 800277a:	699b      	ldr	r3, [r3, #24]
- 800277c:	4a19      	ldr	r2, [pc, #100]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 800277e:	f043 0304 	orr.w	r3, r3, #4
- 8002782:	6193      	str	r3, [r2, #24]
- 8002784:	4b17      	ldr	r3, [pc, #92]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 8002786:	699b      	ldr	r3, [r3, #24]
- 8002788:	f003 0304 	and.w	r3, r3, #4
- 800278c:	607b      	str	r3, [r7, #4]
- 800278e:	687b      	ldr	r3, [r7, #4]
+ 8002e18:	4b1a      	ldr	r3, [pc, #104]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e1a:	699b      	ldr	r3, [r3, #24]
+ 8002e1c:	4a19      	ldr	r2, [pc, #100]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e1e:	f043 0304 	orr.w	r3, r3, #4
+ 8002e22:	6193      	str	r3, [r2, #24]
+ 8002e24:	4b17      	ldr	r3, [pc, #92]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e26:	699b      	ldr	r3, [r3, #24]
+ 8002e28:	f003 0304 	and.w	r3, r3, #4
+ 8002e2c:	607b      	str	r3, [r7, #4]
+ 8002e2e:	687b      	ldr	r3, [r7, #4]
     __HAL_RCC_GPIOB_CLK_ENABLE();
- 8002790:	4b14      	ldr	r3, [pc, #80]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 8002792:	699b      	ldr	r3, [r3, #24]
- 8002794:	4a13      	ldr	r2, [pc, #76]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 8002796:	f043 0308 	orr.w	r3, r3, #8
- 800279a:	6193      	str	r3, [r2, #24]
- 800279c:	4b11      	ldr	r3, [pc, #68]	@ (80027e4 <rs485_configure_gpio_address+0x80>)
- 800279e:	699b      	ldr	r3, [r3, #24]
- 80027a0:	f003 0308 	and.w	r3, r3, #8
- 80027a4:	603b      	str	r3, [r7, #0]
- 80027a6:	683b      	ldr	r3, [r7, #0]
+ 8002e30:	4b14      	ldr	r3, [pc, #80]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e32:	699b      	ldr	r3, [r3, #24]
+ 8002e34:	4a13      	ldr	r2, [pc, #76]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e36:	f043 0308 	orr.w	r3, r3, #8
+ 8002e3a:	6193      	str	r3, [r2, #24]
+ 8002e3c:	4b11      	ldr	r3, [pc, #68]	@ (8002e84 <rs485_configure_gpio_address+0x80>)
+ 8002e3e:	699b      	ldr	r3, [r3, #24]
+ 8002e40:	f003 0308 	and.w	r3, r3, #8
+ 8002e44:	603b      	str	r3, [r7, #0]
+ 8002e46:	683b      	ldr	r3, [r7, #0]
 
     /* Configure PA2-PA5 as input with pull-up */
     GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
- 80027a8:	233c      	movs	r3, #60	@ 0x3c
- 80027aa:	60bb      	str	r3, [r7, #8]
+ 8002e48:	233c      	movs	r3, #60	@ 0x3c
+ 8002e4a:	60bb      	str	r3, [r7, #8]
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 80027ac:	2300      	movs	r3, #0
- 80027ae:	60fb      	str	r3, [r7, #12]
+ 8002e4c:	2300      	movs	r3, #0
+ 8002e4e:	60fb      	str	r3, [r7, #12]
     GPIO_InitStruct.Pull = GPIO_PULLUP;
- 80027b0:	2301      	movs	r3, #1
- 80027b2:	613b      	str	r3, [r7, #16]
+ 8002e50:	2301      	movs	r3, #1
+ 8002e52:	613b      	str	r3, [r7, #16]
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 80027b4:	f107 0308 	add.w	r3, r7, #8
- 80027b8:	4619      	mov	r1, r3
- 80027ba:	480b      	ldr	r0, [pc, #44]	@ (80027e8 <rs485_configure_gpio_address+0x84>)
- 80027bc:	f000 fdc4 	bl	8003348 <HAL_GPIO_Init>
+ 8002e54:	f107 0308 	add.w	r3, r7, #8
+ 8002e58:	4619      	mov	r1, r3
+ 8002e5a:	480b      	ldr	r0, [pc, #44]	@ (8002e88 <rs485_configure_gpio_address+0x84>)
+ 8002e5c:	f001 fc88 	bl	8004770 <HAL_GPIO_Init>
 
     /* Configure PB12-PB15 as input with pull-up */
     GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
- 80027c0:	f44f 4370 	mov.w	r3, #61440	@ 0xf000
- 80027c4:	60bb      	str	r3, [r7, #8]
+ 8002e60:	f44f 4370 	mov.w	r3, #61440	@ 0xf000
+ 8002e64:	60bb      	str	r3, [r7, #8]
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 80027c6:	2300      	movs	r3, #0
- 80027c8:	60fb      	str	r3, [r7, #12]
+ 8002e66:	2300      	movs	r3, #0
+ 8002e68:	60fb      	str	r3, [r7, #12]
     GPIO_InitStruct.Pull = GPIO_PULLUP;
- 80027ca:	2301      	movs	r3, #1
- 80027cc:	613b      	str	r3, [r7, #16]
+ 8002e6a:	2301      	movs	r3, #1
+ 8002e6c:	613b      	str	r3, [r7, #16]
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 80027ce:	f107 0308 	add.w	r3, r7, #8
- 80027d2:	4619      	mov	r1, r3
- 80027d4:	4805      	ldr	r0, [pc, #20]	@ (80027ec <rs485_configure_gpio_address+0x88>)
- 80027d6:	f000 fdb7 	bl	8003348 <HAL_GPIO_Init>
+ 8002e6e:	f107 0308 	add.w	r3, r7, #8
+ 8002e72:	4619      	mov	r1, r3
+ 8002e74:	4805      	ldr	r0, [pc, #20]	@ (8002e8c <rs485_configure_gpio_address+0x88>)
+ 8002e76:	f001 fc7b 	bl	8004770 <HAL_GPIO_Init>
 }
- 80027da:	bf00      	nop
- 80027dc:	3718      	adds	r7, #24
- 80027de:	46bd      	mov	sp, r7
- 80027e0:	bd80      	pop	{r7, pc}
- 80027e2:	bf00      	nop
- 80027e4:	40021000 	.word	0x40021000
- 80027e8:	40010800 	.word	0x40010800
- 80027ec:	40010c00 	.word	0x40010c00
+ 8002e7a:	bf00      	nop
+ 8002e7c:	3718      	adds	r7, #24
+ 8002e7e:	46bd      	mov	sp, r7
+ 8002e80:	bd80      	pop	{r7, pc}
+ 8002e82:	bf00      	nop
+ 8002e84:	40021000 	.word	0x40021000
+ 8002e88:	40010800 	.word	0x40010800
+ 8002e8c:	40010c00 	.word	0x40010c00
 
-080027f0 <rs485_configure_usart1>:
+08002e90 <rs485_configure_usart1>:
 
 /**
  * @brief Configures USART1 for RS-485 communication.
  */
 static void rs485_configure_usart1(void)
 {
- 80027f0:	b580      	push	{r7, lr}
- 80027f2:	b082      	sub	sp, #8
- 80027f4:	af00      	add	r7, sp, #0
+ 8002e90:	b580      	push	{r7, lr}
+ 8002e92:	b082      	sub	sp, #8
+ 8002e94:	af00      	add	r7, sp, #0
     /* Enable clock for USART1 */
     __HAL_RCC_USART1_CLK_ENABLE();
- 80027f6:	4b18      	ldr	r3, [pc, #96]	@ (8002858 <rs485_configure_usart1+0x68>)
- 80027f8:	699b      	ldr	r3, [r3, #24]
- 80027fa:	4a17      	ldr	r2, [pc, #92]	@ (8002858 <rs485_configure_usart1+0x68>)
- 80027fc:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
- 8002800:	6193      	str	r3, [r2, #24]
- 8002802:	4b15      	ldr	r3, [pc, #84]	@ (8002858 <rs485_configure_usart1+0x68>)
- 8002804:	699b      	ldr	r3, [r3, #24]
- 8002806:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
- 800280a:	607b      	str	r3, [r7, #4]
- 800280c:	687b      	ldr	r3, [r7, #4]
+ 8002e96:	4b18      	ldr	r3, [pc, #96]	@ (8002ef8 <rs485_configure_usart1+0x68>)
+ 8002e98:	699b      	ldr	r3, [r3, #24]
+ 8002e9a:	4a17      	ldr	r2, [pc, #92]	@ (8002ef8 <rs485_configure_usart1+0x68>)
+ 8002e9c:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
+ 8002ea0:	6193      	str	r3, [r2, #24]
+ 8002ea2:	4b15      	ldr	r3, [pc, #84]	@ (8002ef8 <rs485_configure_usart1+0x68>)
+ 8002ea4:	699b      	ldr	r3, [r3, #24]
+ 8002ea6:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8002eaa:	607b      	str	r3, [r7, #4]
+ 8002eac:	687b      	ldr	r3, [r7, #4]
 
     huart1.Instance = USART1;
- 800280e:	4b13      	ldr	r3, [pc, #76]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002810:	4a13      	ldr	r2, [pc, #76]	@ (8002860 <rs485_configure_usart1+0x70>)
- 8002812:	601a      	str	r2, [r3, #0]
+ 8002eae:	4b13      	ldr	r3, [pc, #76]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002eb0:	4a13      	ldr	r2, [pc, #76]	@ (8002f00 <rs485_configure_usart1+0x70>)
+ 8002eb2:	601a      	str	r2, [r3, #0]
     huart1.Init.BaudRate = 9600;           /*!< Default baud rate for RS-485 */
- 8002814:	4b11      	ldr	r3, [pc, #68]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002816:	f44f 5216 	mov.w	r2, #9600	@ 0x2580
- 800281a:	605a      	str	r2, [r3, #4]
+ 8002eb4:	4b11      	ldr	r3, [pc, #68]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002eb6:	f44f 5216 	mov.w	r2, #9600	@ 0x2580
+ 8002eba:	605a      	str	r2, [r3, #4]
     huart1.Init.WordLength = UART_WORDLENGTH_8B;
- 800281c:	4b0f      	ldr	r3, [pc, #60]	@ (800285c <rs485_configure_usart1+0x6c>)
- 800281e:	2200      	movs	r2, #0
- 8002820:	609a      	str	r2, [r3, #8]
+ 8002ebc:	4b0f      	ldr	r3, [pc, #60]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002ebe:	2200      	movs	r2, #0
+ 8002ec0:	609a      	str	r2, [r3, #8]
     huart1.Init.StopBits = UART_STOPBITS_1;
- 8002822:	4b0e      	ldr	r3, [pc, #56]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002824:	2200      	movs	r2, #0
- 8002826:	60da      	str	r2, [r3, #12]
+ 8002ec2:	4b0e      	ldr	r3, [pc, #56]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002ec4:	2200      	movs	r2, #0
+ 8002ec6:	60da      	str	r2, [r3, #12]
     huart1.Init.Parity = UART_PARITY_NONE;
- 8002828:	4b0c      	ldr	r3, [pc, #48]	@ (800285c <rs485_configure_usart1+0x6c>)
- 800282a:	2200      	movs	r2, #0
- 800282c:	611a      	str	r2, [r3, #16]
+ 8002ec8:	4b0c      	ldr	r3, [pc, #48]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002eca:	2200      	movs	r2, #0
+ 8002ecc:	611a      	str	r2, [r3, #16]
     huart1.Init.Mode = UART_MODE_TX_RX;
- 800282e:	4b0b      	ldr	r3, [pc, #44]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002830:	220c      	movs	r2, #12
- 8002832:	615a      	str	r2, [r3, #20]
+ 8002ece:	4b0b      	ldr	r3, [pc, #44]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002ed0:	220c      	movs	r2, #12
+ 8002ed2:	615a      	str	r2, [r3, #20]
     huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; /*!< Use NONE as TX enable */
- 8002834:	4b09      	ldr	r3, [pc, #36]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002836:	2200      	movs	r2, #0
- 8002838:	619a      	str	r2, [r3, #24]
+ 8002ed4:	4b09      	ldr	r3, [pc, #36]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002ed6:	2200      	movs	r2, #0
+ 8002ed8:	619a      	str	r2, [r3, #24]
     huart1.Init.OverSampling = UART_OVERSAMPLING_16;
- 800283a:	4b08      	ldr	r3, [pc, #32]	@ (800285c <rs485_configure_usart1+0x6c>)
- 800283c:	2200      	movs	r2, #0
- 800283e:	61da      	str	r2, [r3, #28]
+ 8002eda:	4b08      	ldr	r3, [pc, #32]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002edc:	2200      	movs	r2, #0
+ 8002ede:	61da      	str	r2, [r3, #28]
 
     if (HAL_UART_Init(&huart1) != HAL_OK)
- 8002840:	4806      	ldr	r0, [pc, #24]	@ (800285c <rs485_configure_usart1+0x6c>)
- 8002842:	f002 fc49 	bl	80050d8 <HAL_UART_Init>
- 8002846:	4603      	mov	r3, r0
- 8002848:	2b00      	cmp	r3, #0
- 800284a:	d001      	beq.n	8002850 <rs485_configure_usart1+0x60>
+ 8002ee0:	4806      	ldr	r0, [pc, #24]	@ (8002efc <rs485_configure_usart1+0x6c>)
+ 8002ee2:	f003 fe87 	bl	8006bf4 <HAL_UART_Init>
+ 8002ee6:	4603      	mov	r3, r0
+ 8002ee8:	2b00      	cmp	r3, #0
+ 8002eea:	d001      	beq.n	8002ef0 <rs485_configure_usart1+0x60>
     {
         /* Initialization Error */
         while(1);
- 800284c:	bf00      	nop
- 800284e:	e7fd      	b.n	800284c <rs485_configure_usart1+0x5c>
+ 8002eec:	bf00      	nop
+ 8002eee:	e7fd      	b.n	8002eec <rs485_configure_usart1+0x5c>
     }
 }
- 8002850:	bf00      	nop
- 8002852:	3708      	adds	r7, #8
- 8002854:	46bd      	mov	sp, r7
- 8002856:	bd80      	pop	{r7, pc}
- 8002858:	40021000 	.word	0x40021000
- 800285c:	20000290 	.word	0x20000290
- 8002860:	40013800 	.word	0x40013800
+ 8002ef0:	bf00      	nop
+ 8002ef2:	3708      	adds	r7, #8
+ 8002ef4:	46bd      	mov	sp, r7
+ 8002ef6:	bd80      	pop	{r7, pc}
+ 8002ef8:	40021000 	.word	0x40021000
+ 8002efc:	200006d8 	.word	0x200006d8
+ 8002f00:	40013800 	.word	0x40013800
 
-08002864 <HAL_MspInit>:
+08002f04 <HAL_MspInit>:
 /* USER CODE END 0 */
 /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
 {
- 8002864:	b480      	push	{r7}
- 8002866:	b085      	sub	sp, #20
- 8002868:	af00      	add	r7, sp, #0
+ 8002f04:	b480      	push	{r7}
+ 8002f06:	b085      	sub	sp, #20
+ 8002f08:	af00      	add	r7, sp, #0
 
   /* USER CODE BEGIN MspInit 0 */
 
   /* USER CODE END MspInit 0 */
 
   __HAL_RCC_AFIO_CLK_ENABLE();
- 800286a:	4b15      	ldr	r3, [pc, #84]	@ (80028c0 <HAL_MspInit+0x5c>)
- 800286c:	699b      	ldr	r3, [r3, #24]
- 800286e:	4a14      	ldr	r2, [pc, #80]	@ (80028c0 <HAL_MspInit+0x5c>)
- 8002870:	f043 0301 	orr.w	r3, r3, #1
- 8002874:	6193      	str	r3, [r2, #24]
- 8002876:	4b12      	ldr	r3, [pc, #72]	@ (80028c0 <HAL_MspInit+0x5c>)
- 8002878:	699b      	ldr	r3, [r3, #24]
- 800287a:	f003 0301 	and.w	r3, r3, #1
- 800287e:	60bb      	str	r3, [r7, #8]
- 8002880:	68bb      	ldr	r3, [r7, #8]
+ 8002f0a:	4b15      	ldr	r3, [pc, #84]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f0c:	699b      	ldr	r3, [r3, #24]
+ 8002f0e:	4a14      	ldr	r2, [pc, #80]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f10:	f043 0301 	orr.w	r3, r3, #1
+ 8002f14:	6193      	str	r3, [r2, #24]
+ 8002f16:	4b12      	ldr	r3, [pc, #72]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f18:	699b      	ldr	r3, [r3, #24]
+ 8002f1a:	f003 0301 	and.w	r3, r3, #1
+ 8002f1e:	60bb      	str	r3, [r7, #8]
+ 8002f20:	68bb      	ldr	r3, [r7, #8]
   __HAL_RCC_PWR_CLK_ENABLE();
- 8002882:	4b0f      	ldr	r3, [pc, #60]	@ (80028c0 <HAL_MspInit+0x5c>)
- 8002884:	69db      	ldr	r3, [r3, #28]
- 8002886:	4a0e      	ldr	r2, [pc, #56]	@ (80028c0 <HAL_MspInit+0x5c>)
- 8002888:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 800288c:	61d3      	str	r3, [r2, #28]
- 800288e:	4b0c      	ldr	r3, [pc, #48]	@ (80028c0 <HAL_MspInit+0x5c>)
- 8002890:	69db      	ldr	r3, [r3, #28]
- 8002892:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 8002896:	607b      	str	r3, [r7, #4]
- 8002898:	687b      	ldr	r3, [r7, #4]
+ 8002f22:	4b0f      	ldr	r3, [pc, #60]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f24:	69db      	ldr	r3, [r3, #28]
+ 8002f26:	4a0e      	ldr	r2, [pc, #56]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f28:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 8002f2c:	61d3      	str	r3, [r2, #28]
+ 8002f2e:	4b0c      	ldr	r3, [pc, #48]	@ (8002f60 <HAL_MspInit+0x5c>)
+ 8002f30:	69db      	ldr	r3, [r3, #28]
+ 8002f32:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8002f36:	607b      	str	r3, [r7, #4]
+ 8002f38:	687b      	ldr	r3, [r7, #4]
 
   /* System interrupt init*/
 
   /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
   */
   __HAL_AFIO_REMAP_SWJ_NOJTAG();
- 800289a:	4b0a      	ldr	r3, [pc, #40]	@ (80028c4 <HAL_MspInit+0x60>)
- 800289c:	685b      	ldr	r3, [r3, #4]
- 800289e:	60fb      	str	r3, [r7, #12]
- 80028a0:	68fb      	ldr	r3, [r7, #12]
- 80028a2:	f023 63e0 	bic.w	r3, r3, #117440512	@ 0x7000000
- 80028a6:	60fb      	str	r3, [r7, #12]
- 80028a8:	68fb      	ldr	r3, [r7, #12]
- 80028aa:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
- 80028ae:	60fb      	str	r3, [r7, #12]
- 80028b0:	4a04      	ldr	r2, [pc, #16]	@ (80028c4 <HAL_MspInit+0x60>)
- 80028b2:	68fb      	ldr	r3, [r7, #12]
- 80028b4:	6053      	str	r3, [r2, #4]
+ 8002f3a:	4b0a      	ldr	r3, [pc, #40]	@ (8002f64 <HAL_MspInit+0x60>)
+ 8002f3c:	685b      	ldr	r3, [r3, #4]
+ 8002f3e:	60fb      	str	r3, [r7, #12]
+ 8002f40:	68fb      	ldr	r3, [r7, #12]
+ 8002f42:	f023 63e0 	bic.w	r3, r3, #117440512	@ 0x7000000
+ 8002f46:	60fb      	str	r3, [r7, #12]
+ 8002f48:	68fb      	ldr	r3, [r7, #12]
+ 8002f4a:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
+ 8002f4e:	60fb      	str	r3, [r7, #12]
+ 8002f50:	4a04      	ldr	r2, [pc, #16]	@ (8002f64 <HAL_MspInit+0x60>)
+ 8002f52:	68fb      	ldr	r3, [r7, #12]
+ 8002f54:	6053      	str	r3, [r2, #4]
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
- 80028b6:	bf00      	nop
- 80028b8:	3714      	adds	r7, #20
- 80028ba:	46bd      	mov	sp, r7
- 80028bc:	bc80      	pop	{r7}
- 80028be:	4770      	bx	lr
- 80028c0:	40021000 	.word	0x40021000
- 80028c4:	40010000 	.word	0x40010000
+ 8002f56:	bf00      	nop
+ 8002f58:	3714      	adds	r7, #20
+ 8002f5a:	46bd      	mov	sp, r7
+ 8002f5c:	bc80      	pop	{r7}
+ 8002f5e:	4770      	bx	lr
+ 8002f60:	40021000 	.word	0x40021000
+ 8002f64:	40010000 	.word	0x40010000
 
-080028c8 <NMI_Handler>:
+08002f68 <NMI_Handler>:
 /******************************************************************************/
 /**
   * @brief This function handles Non maskable interrupt.
   */
 void NMI_Handler(void)
 {
- 80028c8:	b480      	push	{r7}
- 80028ca:	af00      	add	r7, sp, #0
+ 8002f68:	b480      	push	{r7}
+ 8002f6a:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
 
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
    while (1)
- 80028cc:	bf00      	nop
- 80028ce:	e7fd      	b.n	80028cc <NMI_Handler+0x4>
+ 8002f6c:	bf00      	nop
+ 8002f6e:	e7fd      	b.n	8002f6c <NMI_Handler+0x4>
 
-080028d0 <HardFault_Handler>:
+08002f70 <HardFault_Handler>:
 
 /**
   * @brief This function handles Hard fault interrupt.
   */
 void HardFault_Handler(void)
 {
- 80028d0:	b480      	push	{r7}
- 80028d2:	af00      	add	r7, sp, #0
+ 8002f70:	b480      	push	{r7}
+ 8002f72:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN HardFault_IRQn 0 */
 
   /* USER CODE END HardFault_IRQn 0 */
   while (1)
- 80028d4:	bf00      	nop
- 80028d6:	e7fd      	b.n	80028d4 <HardFault_Handler+0x4>
+ 8002f74:	bf00      	nop
+ 8002f76:	e7fd      	b.n	8002f74 <HardFault_Handler+0x4>
 
-080028d8 <MemManage_Handler>:
+08002f78 <MemManage_Handler>:
 
 /**
   * @brief This function handles Memory management fault.
   */
 void MemManage_Handler(void)
 {
- 80028d8:	b480      	push	{r7}
- 80028da:	af00      	add	r7, sp, #0
+ 8002f78:	b480      	push	{r7}
+ 8002f7a:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
 
   /* USER CODE END MemoryManagement_IRQn 0 */
   while (1)
- 80028dc:	bf00      	nop
- 80028de:	e7fd      	b.n	80028dc <MemManage_Handler+0x4>
+ 8002f7c:	bf00      	nop
+ 8002f7e:	e7fd      	b.n	8002f7c <MemManage_Handler+0x4>
 
-080028e0 <BusFault_Handler>:
+08002f80 <BusFault_Handler>:
 
 /**
   * @brief This function handles Prefetch fault, memory access fault.
   */
 void BusFault_Handler(void)
 {
- 80028e0:	b480      	push	{r7}
- 80028e2:	af00      	add	r7, sp, #0
+ 8002f80:	b480      	push	{r7}
+ 8002f82:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN BusFault_IRQn 0 */
 
   /* USER CODE END BusFault_IRQn 0 */
   while (1)
- 80028e4:	bf00      	nop
- 80028e6:	e7fd      	b.n	80028e4 <BusFault_Handler+0x4>
+ 8002f84:	bf00      	nop
+ 8002f86:	e7fd      	b.n	8002f84 <BusFault_Handler+0x4>
 
-080028e8 <UsageFault_Handler>:
+08002f88 <UsageFault_Handler>:
 
 /**
   * @brief This function handles Undefined instruction or illegal state.
   */
 void UsageFault_Handler(void)
 {
- 80028e8:	b480      	push	{r7}
- 80028ea:	af00      	add	r7, sp, #0
+ 8002f88:	b480      	push	{r7}
+ 8002f8a:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN UsageFault_IRQn 0 */
 
   /* USER CODE END UsageFault_IRQn 0 */
   while (1)
- 80028ec:	bf00      	nop
- 80028ee:	e7fd      	b.n	80028ec <UsageFault_Handler+0x4>
+ 8002f8c:	bf00      	nop
+ 8002f8e:	e7fd      	b.n	8002f8c <UsageFault_Handler+0x4>
 
-080028f0 <SVC_Handler>:
+08002f90 <SVC_Handler>:
 
 /**
   * @brief This function handles System service call via SWI instruction.
   */
 void SVC_Handler(void)
 {
- 80028f0:	b480      	push	{r7}
- 80028f2:	af00      	add	r7, sp, #0
+ 8002f90:	b480      	push	{r7}
+ 8002f92:	af00      	add	r7, sp, #0
 
   /* USER CODE END SVCall_IRQn 0 */
   /* USER CODE BEGIN SVCall_IRQn 1 */
 
   /* USER CODE END SVCall_IRQn 1 */
 }
- 80028f4:	bf00      	nop
- 80028f6:	46bd      	mov	sp, r7
- 80028f8:	bc80      	pop	{r7}
- 80028fa:	4770      	bx	lr
+ 8002f94:	bf00      	nop
+ 8002f96:	46bd      	mov	sp, r7
+ 8002f98:	bc80      	pop	{r7}
+ 8002f9a:	4770      	bx	lr
 
-080028fc <DebugMon_Handler>:
+08002f9c <DebugMon_Handler>:
 
 /**
   * @brief This function handles Debug monitor.
   */
 void DebugMon_Handler(void)
 {
- 80028fc:	b480      	push	{r7}
- 80028fe:	af00      	add	r7, sp, #0
+ 8002f9c:	b480      	push	{r7}
+ 8002f9e:	af00      	add	r7, sp, #0
 
   /* USER CODE END DebugMonitor_IRQn 0 */
   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
 
   /* USER CODE END DebugMonitor_IRQn 1 */
 }
- 8002900:	bf00      	nop
- 8002902:	46bd      	mov	sp, r7
- 8002904:	bc80      	pop	{r7}
- 8002906:	4770      	bx	lr
+ 8002fa0:	bf00      	nop
+ 8002fa2:	46bd      	mov	sp, r7
+ 8002fa4:	bc80      	pop	{r7}
+ 8002fa6:	4770      	bx	lr
 
-08002908 <PendSV_Handler>:
+08002fa8 <PendSV_Handler>:
 
 /**
   * @brief This function handles Pendable request for system service.
   */
 void PendSV_Handler(void)
 {
- 8002908:	b480      	push	{r7}
- 800290a:	af00      	add	r7, sp, #0
+ 8002fa8:	b480      	push	{r7}
+ 8002faa:	af00      	add	r7, sp, #0
 
   /* USER CODE END PendSV_IRQn 0 */
   /* USER CODE BEGIN PendSV_IRQn 1 */
 
   /* USER CODE END PendSV_IRQn 1 */
 }
- 800290c:	bf00      	nop
- 800290e:	46bd      	mov	sp, r7
- 8002910:	bc80      	pop	{r7}
- 8002912:	4770      	bx	lr
+ 8002fac:	bf00      	nop
+ 8002fae:	46bd      	mov	sp, r7
+ 8002fb0:	bc80      	pop	{r7}
+ 8002fb2:	4770      	bx	lr
 
-08002914 <SysTick_Handler>:
+08002fb4 <SysTick_Handler>:
 
 /**
   * @brief This function handles System tick timer.
   */
 void SysTick_Handler(void)
 {
- 8002914:	b580      	push	{r7, lr}
- 8002916:	af00      	add	r7, sp, #0
+ 8002fb4:	b580      	push	{r7, lr}
+ 8002fb6:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN SysTick_IRQn 0 */
 
   /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
- 8002918:	f000 f904 	bl	8002b24 <HAL_IncTick>
+ 8002fb8:	f000 f97a 	bl	80032b0 <HAL_IncTick>
   /* USER CODE BEGIN SysTick_IRQn 1 */
 
   /* USER CODE END SysTick_IRQn 1 */
 }
- 800291c:	bf00      	nop
- 800291e:	bd80      	pop	{r7, pc}
+ 8002fbc:	bf00      	nop
+ 8002fbe:	bd80      	pop	{r7, pc}
 
-08002920 <EXTI3_IRQHandler>:
+08002fc0 <EXTI3_IRQHandler>:
 
 /**
   * @brief This function handles EXTI line3 interrupt.
   */
 void EXTI3_IRQHandler(void)
 {
- 8002920:	b580      	push	{r7, lr}
- 8002922:	af00      	add	r7, sp, #0
+ 8002fc0:	b580      	push	{r7, lr}
+ 8002fc2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN EXTI3_IRQn 0 */
 
   /* USER CODE END EXTI3_IRQn 0 */
   HAL_GPIO_EXTI_IRQHandler(Calib_PH_Pin);
- 8002924:	2008      	movs	r0, #8
- 8002926:	f000 fec3 	bl	80036b0 <HAL_GPIO_EXTI_IRQHandler>
+ 8002fc4:	2008      	movs	r0, #8
+ 8002fc6:	f001 fd87 	bl	8004ad8 <HAL_GPIO_EXTI_IRQHandler>
   /* USER CODE BEGIN EXTI3_IRQn 1 */
 
   /* USER CODE END EXTI3_IRQn 1 */
 }
- 800292a:	bf00      	nop
- 800292c:	bd80      	pop	{r7, pc}
+ 8002fca:	bf00      	nop
+ 8002fcc:	bd80      	pop	{r7, pc}
 	...
 
-08002930 <USART1_IRQHandler>:
+08002fd0 <DMA1_Channel1_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+ 8002fd0:	b580      	push	{r7, lr}
+ 8002fd2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_adc1);
+ 8002fd4:	4802      	ldr	r0, [pc, #8]	@ (8002fe0 <DMA1_Channel1_IRQHandler+0x10>)
+ 8002fd6:	f001 f897 	bl	8004108 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+ 8002fda:	bf00      	nop
+ 8002fdc:	bd80      	pop	{r7, pc}
+ 8002fde:	bf00      	nop
+ 8002fe0:	2000017c 	.word	0x2000017c
+
+08002fe4 <USART1_IRQHandler>:
 
 /**
   * @brief This function handles USART1 global interrupt.
   */
 void USART1_IRQHandler(void)
 {
- 8002930:	b580      	push	{r7, lr}
- 8002932:	af00      	add	r7, sp, #0
+ 8002fe4:	b580      	push	{r7, lr}
+ 8002fe6:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN USART1_IRQn 0 */
 
   /* USER CODE END USART1_IRQn 0 */
   HAL_UART_IRQHandler(&huart1);
- 8002934:	4802      	ldr	r0, [pc, #8]	@ (8002940 <USART1_IRQHandler+0x10>)
- 8002936:	f002 fcab 	bl	8005290 <HAL_UART_IRQHandler>
+ 8002fe8:	4802      	ldr	r0, [pc, #8]	@ (8002ff4 <USART1_IRQHandler+0x10>)
+ 8002fea:	f003 fedf 	bl	8006dac <HAL_UART_IRQHandler>
   /* USER CODE BEGIN USART1_IRQn 1 */
 
   /* USER CODE END USART1_IRQn 1 */
 }
- 800293a:	bf00      	nop
- 800293c:	bd80      	pop	{r7, pc}
- 800293e:	bf00      	nop
- 8002940:	200002d8 	.word	0x200002d8
+ 8002fee:	bf00      	nop
+ 8002ff0:	bd80      	pop	{r7, pc}
+ 8002ff2:	bf00      	nop
+ 8002ff4:	20000768 	.word	0x20000768
 
-08002944 <SystemInit>:
+08002ff8 <SystemInit>:
   * @note   This function should be used only after reset.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
 {
- 8002944:	b480      	push	{r7}
- 8002946:	af00      	add	r7, sp, #0
+ 8002ff8:	b480      	push	{r7}
+ 8002ffa:	af00      	add	r7, sp, #0
 
   /* Configure the Vector Table location -------------------------------------*/
 #if defined(USER_VECT_TAB_ADDRESS)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #endif /* USER_VECT_TAB_ADDRESS */
 }
- 8002948:	bf00      	nop
- 800294a:	46bd      	mov	sp, r7
- 800294c:	bc80      	pop	{r7}
- 800294e:	4770      	bx	lr
+ 8002ffc:	bf00      	nop
+ 8002ffe:	46bd      	mov	sp, r7
+ 8003000:	bc80      	pop	{r7}
+ 8003002:	4770      	bx	lr
 
-08002950 <MX_USART1_UART_Init>:
+08003004 <MX_TIM3_Init>:
+
+TIM_HandleTypeDef htim3;
+
+/* TIM3 init function */
+void MX_TIM3_Init(void)
+{
+ 8003004:	b580      	push	{r7, lr}
+ 8003006:	b086      	sub	sp, #24
+ 8003008:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 800300a:	f107 0308 	add.w	r3, r7, #8
+ 800300e:	2200      	movs	r2, #0
+ 8003010:	601a      	str	r2, [r3, #0]
+ 8003012:	605a      	str	r2, [r3, #4]
+ 8003014:	609a      	str	r2, [r3, #8]
+ 8003016:	60da      	str	r2, [r3, #12]
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8003018:	463b      	mov	r3, r7
+ 800301a:	2200      	movs	r2, #0
+ 800301c:	601a      	str	r2, [r3, #0]
+ 800301e:	605a      	str	r2, [r3, #4]
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+ 8003020:	4b1d      	ldr	r3, [pc, #116]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003022:	4a1e      	ldr	r2, [pc, #120]	@ (800309c <MX_TIM3_Init+0x98>)
+ 8003024:	601a      	str	r2, [r3, #0]
+  htim3.Init.Prescaler = 3;
+ 8003026:	4b1c      	ldr	r3, [pc, #112]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003028:	2203      	movs	r2, #3
+ 800302a:	605a      	str	r2, [r3, #4]
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 800302c:	4b1a      	ldr	r3, [pc, #104]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 800302e:	2200      	movs	r2, #0
+ 8003030:	609a      	str	r2, [r3, #8]
+  htim3.Init.Period = 59999;
+ 8003032:	4b19      	ldr	r3, [pc, #100]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003034:	f64e 225f 	movw	r2, #59999	@ 0xea5f
+ 8003038:	60da      	str	r2, [r3, #12]
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 800303a:	4b17      	ldr	r3, [pc, #92]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 800303c:	2200      	movs	r2, #0
+ 800303e:	611a      	str	r2, [r3, #16]
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
+ 8003040:	4b15      	ldr	r3, [pc, #84]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003042:	2280      	movs	r2, #128	@ 0x80
+ 8003044:	619a      	str	r2, [r3, #24]
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 8003046:	4814      	ldr	r0, [pc, #80]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003048:	f003 fb10 	bl	800666c <HAL_TIM_Base_Init>
+ 800304c:	4603      	mov	r3, r0
+ 800304e:	2b00      	cmp	r3, #0
+ 8003050:	d001      	beq.n	8003056 <MX_TIM3_Init+0x52>
+  {
+    Error_Handler();
+ 8003052:	f7ff fe5d 	bl	8002d10 <Error_Handler>
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8003056:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 800305a:	60bb      	str	r3, [r7, #8]
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 800305c:	f107 0308 	add.w	r3, r7, #8
+ 8003060:	4619      	mov	r1, r3
+ 8003062:	480d      	ldr	r0, [pc, #52]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003064:	f003 fb9c 	bl	80067a0 <HAL_TIM_ConfigClockSource>
+ 8003068:	4603      	mov	r3, r0
+ 800306a:	2b00      	cmp	r3, #0
+ 800306c:	d001      	beq.n	8003072 <MX_TIM3_Init+0x6e>
+  {
+    Error_Handler();
+ 800306e:	f7ff fe4f 	bl	8002d10 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
+ 8003072:	2320      	movs	r3, #32
+ 8003074:	603b      	str	r3, [r7, #0]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8003076:	2300      	movs	r3, #0
+ 8003078:	607b      	str	r3, [r7, #4]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 800307a:	463b      	mov	r3, r7
+ 800307c:	4619      	mov	r1, r3
+ 800307e:	4806      	ldr	r0, [pc, #24]	@ (8003098 <MX_TIM3_Init+0x94>)
+ 8003080:	f003 fd5a 	bl	8006b38 <HAL_TIMEx_MasterConfigSynchronization>
+ 8003084:	4603      	mov	r3, r0
+ 8003086:	2b00      	cmp	r3, #0
+ 8003088:	d001      	beq.n	800308e <MX_TIM3_Init+0x8a>
+  {
+    Error_Handler();
+ 800308a:	f7ff fe41 	bl	8002d10 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+
+}
+ 800308e:	bf00      	nop
+ 8003090:	3718      	adds	r7, #24
+ 8003092:	46bd      	mov	sp, r7
+ 8003094:	bd80      	pop	{r7, pc}
+ 8003096:	bf00      	nop
+ 8003098:	20000720 	.word	0x20000720
+ 800309c:	40000400 	.word	0x40000400
+
+080030a0 <HAL_TIM_Base_MspInit>:
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+ 80030a0:	b480      	push	{r7}
+ 80030a2:	b085      	sub	sp, #20
+ 80030a4:	af00      	add	r7, sp, #0
+ 80030a6:	6078      	str	r0, [r7, #4]
+
+  if(tim_baseHandle->Instance==TIM3)
+ 80030a8:	687b      	ldr	r3, [r7, #4]
+ 80030aa:	681b      	ldr	r3, [r3, #0]
+ 80030ac:	4a09      	ldr	r2, [pc, #36]	@ (80030d4 <HAL_TIM_Base_MspInit+0x34>)
+ 80030ae:	4293      	cmp	r3, r2
+ 80030b0:	d10b      	bne.n	80030ca <HAL_TIM_Base_MspInit+0x2a>
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* TIM3 clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+ 80030b2:	4b09      	ldr	r3, [pc, #36]	@ (80030d8 <HAL_TIM_Base_MspInit+0x38>)
+ 80030b4:	69db      	ldr	r3, [r3, #28]
+ 80030b6:	4a08      	ldr	r2, [pc, #32]	@ (80030d8 <HAL_TIM_Base_MspInit+0x38>)
+ 80030b8:	f043 0302 	orr.w	r3, r3, #2
+ 80030bc:	61d3      	str	r3, [r2, #28]
+ 80030be:	4b06      	ldr	r3, [pc, #24]	@ (80030d8 <HAL_TIM_Base_MspInit+0x38>)
+ 80030c0:	69db      	ldr	r3, [r3, #28]
+ 80030c2:	f003 0302 	and.w	r3, r3, #2
+ 80030c6:	60fb      	str	r3, [r7, #12]
+ 80030c8:	68fb      	ldr	r3, [r7, #12]
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+}
+ 80030ca:	bf00      	nop
+ 80030cc:	3714      	adds	r7, #20
+ 80030ce:	46bd      	mov	sp, r7
+ 80030d0:	bc80      	pop	{r7}
+ 80030d2:	4770      	bx	lr
+ 80030d4:	40000400 	.word	0x40000400
+ 80030d8:	40021000 	.word	0x40021000
+
+080030dc <MX_USART1_UART_Init>:
 UART_HandleTypeDef huart1;
 
 /* USART1 init function */
 
 void MX_USART1_UART_Init(void)
 {
- 8002950:	b580      	push	{r7, lr}
- 8002952:	af00      	add	r7, sp, #0
+ 80030dc:	b580      	push	{r7, lr}
+ 80030de:	af00      	add	r7, sp, #0
   /* USER CODE END USART1_Init 0 */
 
   /* USER CODE BEGIN USART1_Init 1 */
 
   /* USER CODE END USART1_Init 1 */
   huart1.Instance = USART1;
- 8002954:	4b11      	ldr	r3, [pc, #68]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002956:	4a12      	ldr	r2, [pc, #72]	@ (80029a0 <MX_USART1_UART_Init+0x50>)
- 8002958:	601a      	str	r2, [r3, #0]
+ 80030e0:	4b11      	ldr	r3, [pc, #68]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 80030e2:	4a12      	ldr	r2, [pc, #72]	@ (800312c <MX_USART1_UART_Init+0x50>)
+ 80030e4:	601a      	str	r2, [r3, #0]
   huart1.Init.BaudRate = 115200;
- 800295a:	4b10      	ldr	r3, [pc, #64]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 800295c:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
- 8002960:	605a      	str	r2, [r3, #4]
+ 80030e6:	4b10      	ldr	r3, [pc, #64]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 80030e8:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
+ 80030ec:	605a      	str	r2, [r3, #4]
   huart1.Init.WordLength = UART_WORDLENGTH_8B;
- 8002962:	4b0e      	ldr	r3, [pc, #56]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002964:	2200      	movs	r2, #0
- 8002966:	609a      	str	r2, [r3, #8]
+ 80030ee:	4b0e      	ldr	r3, [pc, #56]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 80030f0:	2200      	movs	r2, #0
+ 80030f2:	609a      	str	r2, [r3, #8]
   huart1.Init.StopBits = UART_STOPBITS_1;
- 8002968:	4b0c      	ldr	r3, [pc, #48]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 800296a:	2200      	movs	r2, #0
- 800296c:	60da      	str	r2, [r3, #12]
+ 80030f4:	4b0c      	ldr	r3, [pc, #48]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 80030f6:	2200      	movs	r2, #0
+ 80030f8:	60da      	str	r2, [r3, #12]
   huart1.Init.Parity = UART_PARITY_NONE;
- 800296e:	4b0b      	ldr	r3, [pc, #44]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002970:	2200      	movs	r2, #0
- 8002972:	611a      	str	r2, [r3, #16]
+ 80030fa:	4b0b      	ldr	r3, [pc, #44]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 80030fc:	2200      	movs	r2, #0
+ 80030fe:	611a      	str	r2, [r3, #16]
   huart1.Init.Mode = UART_MODE_TX_RX;
- 8002974:	4b09      	ldr	r3, [pc, #36]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002976:	220c      	movs	r2, #12
- 8002978:	615a      	str	r2, [r3, #20]
+ 8003100:	4b09      	ldr	r3, [pc, #36]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 8003102:	220c      	movs	r2, #12
+ 8003104:	615a      	str	r2, [r3, #20]
   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 800297a:	4b08      	ldr	r3, [pc, #32]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 800297c:	2200      	movs	r2, #0
- 800297e:	619a      	str	r2, [r3, #24]
+ 8003106:	4b08      	ldr	r3, [pc, #32]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 8003108:	2200      	movs	r2, #0
+ 800310a:	619a      	str	r2, [r3, #24]
   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
- 8002980:	4b06      	ldr	r3, [pc, #24]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002982:	2200      	movs	r2, #0
- 8002984:	61da      	str	r2, [r3, #28]
+ 800310c:	4b06      	ldr	r3, [pc, #24]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 800310e:	2200      	movs	r2, #0
+ 8003110:	61da      	str	r2, [r3, #28]
   if (HAL_UART_Init(&huart1) != HAL_OK)
- 8002986:	4805      	ldr	r0, [pc, #20]	@ (800299c <MX_USART1_UART_Init+0x4c>)
- 8002988:	f002 fba6 	bl	80050d8 <HAL_UART_Init>
- 800298c:	4603      	mov	r3, r0
- 800298e:	2b00      	cmp	r3, #0
- 8002990:	d001      	beq.n	8002996 <MX_USART1_UART_Init+0x46>
+ 8003112:	4805      	ldr	r0, [pc, #20]	@ (8003128 <MX_USART1_UART_Init+0x4c>)
+ 8003114:	f003 fd6e 	bl	8006bf4 <HAL_UART_Init>
+ 8003118:	4603      	mov	r3, r0
+ 800311a:	2b00      	cmp	r3, #0
+ 800311c:	d001      	beq.n	8003122 <MX_USART1_UART_Init+0x46>
   {
     Error_Handler();
- 8002992:	f7ff fe6d 	bl	8002670 <Error_Handler>
+ 800311e:	f7ff fdf7 	bl	8002d10 <Error_Handler>
   }
   /* USER CODE BEGIN USART1_Init 2 */
 
   /* USER CODE END USART1_Init 2 */
 
 }
- 8002996:	bf00      	nop
- 8002998:	bd80      	pop	{r7, pc}
- 800299a:	bf00      	nop
- 800299c:	200002d8 	.word	0x200002d8
- 80029a0:	40013800 	.word	0x40013800
+ 8003122:	bf00      	nop
+ 8003124:	bd80      	pop	{r7, pc}
+ 8003126:	bf00      	nop
+ 8003128:	20000768 	.word	0x20000768
+ 800312c:	40013800 	.word	0x40013800
 
-080029a4 <HAL_UART_MspInit>:
+08003130 <HAL_UART_MspInit>:
 
 void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 {
- 80029a4:	b580      	push	{r7, lr}
- 80029a6:	b088      	sub	sp, #32
- 80029a8:	af00      	add	r7, sp, #0
- 80029aa:	6078      	str	r0, [r7, #4]
+ 8003130:	b580      	push	{r7, lr}
+ 8003132:	b088      	sub	sp, #32
+ 8003134:	af00      	add	r7, sp, #0
+ 8003136:	6078      	str	r0, [r7, #4]
 
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80029ac:	f107 0310 	add.w	r3, r7, #16
- 80029b0:	2200      	movs	r2, #0
- 80029b2:	601a      	str	r2, [r3, #0]
- 80029b4:	605a      	str	r2, [r3, #4]
- 80029b6:	609a      	str	r2, [r3, #8]
- 80029b8:	60da      	str	r2, [r3, #12]
+ 8003138:	f107 0310 	add.w	r3, r7, #16
+ 800313c:	2200      	movs	r2, #0
+ 800313e:	601a      	str	r2, [r3, #0]
+ 8003140:	605a      	str	r2, [r3, #4]
+ 8003142:	609a      	str	r2, [r3, #8]
+ 8003144:	60da      	str	r2, [r3, #12]
   if(uartHandle->Instance==USART1)
- 80029ba:	687b      	ldr	r3, [r7, #4]
- 80029bc:	681b      	ldr	r3, [r3, #0]
- 80029be:	4a20      	ldr	r2, [pc, #128]	@ (8002a40 <HAL_UART_MspInit+0x9c>)
- 80029c0:	4293      	cmp	r3, r2
- 80029c2:	d139      	bne.n	8002a38 <HAL_UART_MspInit+0x94>
+ 8003146:	687b      	ldr	r3, [r7, #4]
+ 8003148:	681b      	ldr	r3, [r3, #0]
+ 800314a:	4a20      	ldr	r2, [pc, #128]	@ (80031cc <HAL_UART_MspInit+0x9c>)
+ 800314c:	4293      	cmp	r3, r2
+ 800314e:	d139      	bne.n	80031c4 <HAL_UART_MspInit+0x94>
   {
   /* USER CODE BEGIN USART1_MspInit 0 */
 
   /* USER CODE END USART1_MspInit 0 */
     /* USART1 clock enable */
     __HAL_RCC_USART1_CLK_ENABLE();
- 80029c4:	4b1f      	ldr	r3, [pc, #124]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029c6:	699b      	ldr	r3, [r3, #24]
- 80029c8:	4a1e      	ldr	r2, [pc, #120]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029ca:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
- 80029ce:	6193      	str	r3, [r2, #24]
- 80029d0:	4b1c      	ldr	r3, [pc, #112]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029d2:	699b      	ldr	r3, [r3, #24]
- 80029d4:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
- 80029d8:	60fb      	str	r3, [r7, #12]
- 80029da:	68fb      	ldr	r3, [r7, #12]
+ 8003150:	4b1f      	ldr	r3, [pc, #124]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 8003152:	699b      	ldr	r3, [r3, #24]
+ 8003154:	4a1e      	ldr	r2, [pc, #120]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 8003156:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
+ 800315a:	6193      	str	r3, [r2, #24]
+ 800315c:	4b1c      	ldr	r3, [pc, #112]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 800315e:	699b      	ldr	r3, [r3, #24]
+ 8003160:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8003164:	60fb      	str	r3, [r7, #12]
+ 8003166:	68fb      	ldr	r3, [r7, #12]
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 80029dc:	4b19      	ldr	r3, [pc, #100]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029de:	699b      	ldr	r3, [r3, #24]
- 80029e0:	4a18      	ldr	r2, [pc, #96]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029e2:	f043 0304 	orr.w	r3, r3, #4
- 80029e6:	6193      	str	r3, [r2, #24]
- 80029e8:	4b16      	ldr	r3, [pc, #88]	@ (8002a44 <HAL_UART_MspInit+0xa0>)
- 80029ea:	699b      	ldr	r3, [r3, #24]
- 80029ec:	f003 0304 	and.w	r3, r3, #4
- 80029f0:	60bb      	str	r3, [r7, #8]
- 80029f2:	68bb      	ldr	r3, [r7, #8]
+ 8003168:	4b19      	ldr	r3, [pc, #100]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 800316a:	699b      	ldr	r3, [r3, #24]
+ 800316c:	4a18      	ldr	r2, [pc, #96]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 800316e:	f043 0304 	orr.w	r3, r3, #4
+ 8003172:	6193      	str	r3, [r2, #24]
+ 8003174:	4b16      	ldr	r3, [pc, #88]	@ (80031d0 <HAL_UART_MspInit+0xa0>)
+ 8003176:	699b      	ldr	r3, [r3, #24]
+ 8003178:	f003 0304 	and.w	r3, r3, #4
+ 800317c:	60bb      	str	r3, [r7, #8]
+ 800317e:	68bb      	ldr	r3, [r7, #8]
     /**USART1 GPIO Configuration
     PA9     ------> USART1_TX
     PA10     ------> USART1_RX
     */
     GPIO_InitStruct.Pin = TX_RS485_Pin;
- 80029f4:	f44f 7300 	mov.w	r3, #512	@ 0x200
- 80029f8:	613b      	str	r3, [r7, #16]
+ 8003180:	f44f 7300 	mov.w	r3, #512	@ 0x200
+ 8003184:	613b      	str	r3, [r7, #16]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80029fa:	2302      	movs	r3, #2
- 80029fc:	617b      	str	r3, [r7, #20]
+ 8003186:	2302      	movs	r3, #2
+ 8003188:	617b      	str	r3, [r7, #20]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
- 80029fe:	2301      	movs	r3, #1
- 8002a00:	61fb      	str	r3, [r7, #28]
+ 800318a:	2301      	movs	r3, #1
+ 800318c:	61fb      	str	r3, [r7, #28]
     HAL_GPIO_Init(TX_RS485_GPIO_Port, &GPIO_InitStruct);
- 8002a02:	f107 0310 	add.w	r3, r7, #16
- 8002a06:	4619      	mov	r1, r3
- 8002a08:	480f      	ldr	r0, [pc, #60]	@ (8002a48 <HAL_UART_MspInit+0xa4>)
- 8002a0a:	f000 fc9d 	bl	8003348 <HAL_GPIO_Init>
+ 800318e:	f107 0310 	add.w	r3, r7, #16
+ 8003192:	4619      	mov	r1, r3
+ 8003194:	480f      	ldr	r0, [pc, #60]	@ (80031d4 <HAL_UART_MspInit+0xa4>)
+ 8003196:	f001 faeb 	bl	8004770 <HAL_GPIO_Init>
 
     GPIO_InitStruct.Pin = RX_RS485_Pin;
- 8002a0e:	f44f 6380 	mov.w	r3, #1024	@ 0x400
- 8002a12:	613b      	str	r3, [r7, #16]
+ 800319a:	f44f 6380 	mov.w	r3, #1024	@ 0x400
+ 800319e:	613b      	str	r3, [r7, #16]
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8002a14:	2300      	movs	r3, #0
- 8002a16:	617b      	str	r3, [r7, #20]
+ 80031a0:	2300      	movs	r3, #0
+ 80031a2:	617b      	str	r3, [r7, #20]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8002a18:	2300      	movs	r3, #0
- 8002a1a:	61bb      	str	r3, [r7, #24]
+ 80031a4:	2300      	movs	r3, #0
+ 80031a6:	61bb      	str	r3, [r7, #24]
     HAL_GPIO_Init(RX_RS485_GPIO_Port, &GPIO_InitStruct);
- 8002a1c:	f107 0310 	add.w	r3, r7, #16
- 8002a20:	4619      	mov	r1, r3
- 8002a22:	4809      	ldr	r0, [pc, #36]	@ (8002a48 <HAL_UART_MspInit+0xa4>)
- 8002a24:	f000 fc90 	bl	8003348 <HAL_GPIO_Init>
+ 80031a8:	f107 0310 	add.w	r3, r7, #16
+ 80031ac:	4619      	mov	r1, r3
+ 80031ae:	4809      	ldr	r0, [pc, #36]	@ (80031d4 <HAL_UART_MspInit+0xa4>)
+ 80031b0:	f001 fade 	bl	8004770 <HAL_GPIO_Init>
 
     /* USART1 interrupt Init */
     HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
- 8002a28:	2200      	movs	r2, #0
- 8002a2a:	2100      	movs	r1, #0
- 8002a2c:	2025      	movs	r0, #37	@ 0x25
- 8002a2e:	f000 fba2 	bl	8003176 <HAL_NVIC_SetPriority>
+ 80031b4:	2200      	movs	r2, #0
+ 80031b6:	2100      	movs	r1, #0
+ 80031b8:	2025      	movs	r0, #37	@ 0x25
+ 80031ba:	f000 fe00 	bl	8003dbe <HAL_NVIC_SetPriority>
     HAL_NVIC_EnableIRQ(USART1_IRQn);
- 8002a32:	2025      	movs	r0, #37	@ 0x25
- 8002a34:	f000 fbbb 	bl	80031ae <HAL_NVIC_EnableIRQ>
+ 80031be:	2025      	movs	r0, #37	@ 0x25
+ 80031c0:	f000 fe19 	bl	8003df6 <HAL_NVIC_EnableIRQ>
   /* USER CODE BEGIN USART1_MspInit 1 */
 
   /* USER CODE END USART1_MspInit 1 */
   }
 }
- 8002a38:	bf00      	nop
- 8002a3a:	3720      	adds	r7, #32
- 8002a3c:	46bd      	mov	sp, r7
- 8002a3e:	bd80      	pop	{r7, pc}
- 8002a40:	40013800 	.word	0x40013800
- 8002a44:	40021000 	.word	0x40021000
- 8002a48:	40010800 	.word	0x40010800
+ 80031c4:	bf00      	nop
+ 80031c6:	3720      	adds	r7, #32
+ 80031c8:	46bd      	mov	sp, r7
+ 80031ca:	bd80      	pop	{r7, pc}
+ 80031cc:	40013800 	.word	0x40013800
+ 80031d0:	40021000 	.word	0x40021000
+ 80031d4:	40010800 	.word	0x40010800
 
-08002a4c <Reset_Handler>:
+080031d8 <Reset_Handler>:
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
 
 /* Call the clock system initialization function.*/
-    bl  SystemInit
- 8002a4c:	f7ff ff7a 	bl	8002944 <SystemInit>
+     bl  SystemInit
+ 80031d8:	f7ff ff0e 	bl	8002ff8 <SystemInit>
 
 /* Copy the data segment initializers from flash to SRAM */
   ldr r0, =_sdata
- 8002a50:	480b      	ldr	r0, [pc, #44]	@ (8002a80 <LoopFillZerobss+0xe>)
+ 80031dc:	480b      	ldr	r0, [pc, #44]	@ (800320c <LoopFillZerobss+0xe>)
   ldr r1, =_edata
- 8002a52:	490c      	ldr	r1, [pc, #48]	@ (8002a84 <LoopFillZerobss+0x12>)
+ 80031de:	490c      	ldr	r1, [pc, #48]	@ (8003210 <LoopFillZerobss+0x12>)
   ldr r2, =_sidata
- 8002a54:	4a0c      	ldr	r2, [pc, #48]	@ (8002a88 <LoopFillZerobss+0x16>)
+ 80031e0:	4a0c      	ldr	r2, [pc, #48]	@ (8003214 <LoopFillZerobss+0x16>)
   movs r3, #0
- 8002a56:	2300      	movs	r3, #0
+ 80031e2:	2300      	movs	r3, #0
   b LoopCopyDataInit
- 8002a58:	e002      	b.n	8002a60 <LoopCopyDataInit>
+ 80031e4:	e002      	b.n	80031ec <LoopCopyDataInit>
 
-08002a5a <CopyDataInit>:
+080031e6 <CopyDataInit>:
 
 CopyDataInit:
   ldr r4, [r2, r3]
- 8002a5a:	58d4      	ldr	r4, [r2, r3]
+ 80031e6:	58d4      	ldr	r4, [r2, r3]
   str r4, [r0, r3]
- 8002a5c:	50c4      	str	r4, [r0, r3]
+ 80031e8:	50c4      	str	r4, [r0, r3]
   adds r3, r3, #4
- 8002a5e:	3304      	adds	r3, #4
+ 80031ea:	3304      	adds	r3, #4
 
-08002a60 <LoopCopyDataInit>:
+080031ec <LoopCopyDataInit>:
 
 LoopCopyDataInit:
   adds r4, r0, r3
- 8002a60:	18c4      	adds	r4, r0, r3
+ 80031ec:	18c4      	adds	r4, r0, r3
   cmp r4, r1
- 8002a62:	428c      	cmp	r4, r1
+ 80031ee:	428c      	cmp	r4, r1
   bcc CopyDataInit
- 8002a64:	d3f9      	bcc.n	8002a5a <CopyDataInit>
+ 80031f0:	d3f9      	bcc.n	80031e6 <CopyDataInit>
   
 /* Zero fill the bss segment. */
   ldr r2, =_sbss
- 8002a66:	4a09      	ldr	r2, [pc, #36]	@ (8002a8c <LoopFillZerobss+0x1a>)
+ 80031f2:	4a09      	ldr	r2, [pc, #36]	@ (8003218 <LoopFillZerobss+0x1a>)
   ldr r4, =_ebss
- 8002a68:	4c09      	ldr	r4, [pc, #36]	@ (8002a90 <LoopFillZerobss+0x1e>)
+ 80031f4:	4c09      	ldr	r4, [pc, #36]	@ (800321c <LoopFillZerobss+0x1e>)
   movs r3, #0
- 8002a6a:	2300      	movs	r3, #0
+ 80031f6:	2300      	movs	r3, #0
   b LoopFillZerobss
- 8002a6c:	e001      	b.n	8002a72 <LoopFillZerobss>
+ 80031f8:	e001      	b.n	80031fe <LoopFillZerobss>
 
-08002a6e <FillZerobss>:
+080031fa <FillZerobss>:
 
 FillZerobss:
   str  r3, [r2]
- 8002a6e:	6013      	str	r3, [r2, #0]
+ 80031fa:	6013      	str	r3, [r2, #0]
   adds r2, r2, #4
- 8002a70:	3204      	adds	r2, #4
+ 80031fc:	3204      	adds	r2, #4
 
-08002a72 <LoopFillZerobss>:
+080031fe <LoopFillZerobss>:
 
 LoopFillZerobss:
   cmp r2, r4
- 8002a72:	42a2      	cmp	r2, r4
+ 80031fe:	42a2      	cmp	r2, r4
   bcc FillZerobss
- 8002a74:	d3fb      	bcc.n	8002a6e <FillZerobss>
+ 8003200:	d3fb      	bcc.n	80031fa <FillZerobss>
 
 /* Call static constructors */
     bl __libc_init_array
- 8002a76:	f003 f953 	bl	8005d20 <__libc_init_array>
+ 8003202:	f004 fb1b 	bl	800783c <__libc_init_array>
 /* Call the application's entry point.*/
   bl main
- 8002a7a:	f7ff fba7 	bl	80021cc <main>
+ 8003206:	f7ff f9ab 	bl	8002560 <main>
   bx lr
- 8002a7e:	4770      	bx	lr
+ 800320a:	4770      	bx	lr
   ldr r0, =_sdata
- 8002a80:	20000000 	.word	0x20000000
+ 800320c:	20000000 	.word	0x20000000
   ldr r1, =_edata
- 8002a84:	20000078 	.word	0x20000078
+ 8003210:	20000080 	.word	0x20000080
   ldr r2, =_sidata
- 8002a88:	08005f78 	.word	0x08005f78
+ 8003214:	08007ab8 	.word	0x08007ab8
   ldr r2, =_sbss
- 8002a8c:	20000078 	.word	0x20000078
+ 8003218:	20000080 	.word	0x20000080
   ldr r4, =_ebss
- 8002a90:	2000045c 	.word	0x2000045c
+ 800321c:	20000910 	.word	0x20000910
 
-08002a94 <ADC1_2_IRQHandler>:
+08003220 <ADC1_2_IRQHandler>:
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
- 8002a94:	e7fe      	b.n	8002a94 <ADC1_2_IRQHandler>
+ 8003220:	e7fe      	b.n	8003220 <ADC1_2_IRQHandler>
 	...
 
-08002a98 <HAL_Init>:
+08003224 <HAL_Init>:
   *         need to ensure that the SysTick time base is always set to 1 millisecond
   *         to have correct HAL operation.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_Init(void)
 {
- 8002a98:	b580      	push	{r7, lr}
- 8002a9a:	af00      	add	r7, sp, #0
+ 8003224:	b580      	push	{r7, lr}
+ 8003226:	af00      	add	r7, sp, #0
     defined(STM32F102x6) || defined(STM32F102xB) || \
     defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
     defined(STM32F105xC) || defined(STM32F107xC)
 
   /* Prefetch buffer is not available on value line devices */
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
- 8002a9c:	4b08      	ldr	r3, [pc, #32]	@ (8002ac0 <HAL_Init+0x28>)
- 8002a9e:	681b      	ldr	r3, [r3, #0]
- 8002aa0:	4a07      	ldr	r2, [pc, #28]	@ (8002ac0 <HAL_Init+0x28>)
- 8002aa2:	f043 0310 	orr.w	r3, r3, #16
- 8002aa6:	6013      	str	r3, [r2, #0]
+ 8003228:	4b08      	ldr	r3, [pc, #32]	@ (800324c <HAL_Init+0x28>)
+ 800322a:	681b      	ldr	r3, [r3, #0]
+ 800322c:	4a07      	ldr	r2, [pc, #28]	@ (800324c <HAL_Init+0x28>)
+ 800322e:	f043 0310 	orr.w	r3, r3, #16
+ 8003232:	6013      	str	r3, [r2, #0]
 #endif
 #endif /* PREFETCH_ENABLE */
 
   /* Set Interrupt Group Priority */
   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8002aa8:	2003      	movs	r0, #3
- 8002aaa:	f000 fb59 	bl	8003160 <HAL_NVIC_SetPriorityGrouping>
+ 8003234:	2003      	movs	r0, #3
+ 8003236:	f000 fdb7 	bl	8003da8 <HAL_NVIC_SetPriorityGrouping>
 
   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
   HAL_InitTick(TICK_INT_PRIORITY);
- 8002aae:	200f      	movs	r0, #15
- 8002ab0:	f000 f808 	bl	8002ac4 <HAL_InitTick>
+ 800323a:	200f      	movs	r0, #15
+ 800323c:	f000 f808 	bl	8003250 <HAL_InitTick>
 
   /* Init the low level hardware */
   HAL_MspInit();
- 8002ab4:	f7ff fed6 	bl	8002864 <HAL_MspInit>
+ 8003240:	f7ff fe60 	bl	8002f04 <HAL_MspInit>
 
   /* Return function status */
   return HAL_OK;
- 8002ab8:	2300      	movs	r3, #0
+ 8003244:	2300      	movs	r3, #0
 }
- 8002aba:	4618      	mov	r0, r3
- 8002abc:	bd80      	pop	{r7, pc}
- 8002abe:	bf00      	nop
- 8002ac0:	40022000 	.word	0x40022000
+ 8003246:	4618      	mov	r0, r3
+ 8003248:	bd80      	pop	{r7, pc}
+ 800324a:	bf00      	nop
+ 800324c:	40022000 	.word	0x40022000
 
-08002ac4 <HAL_InitTick>:
+08003250 <HAL_InitTick>:
   *       implementation  in user file.
   * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
- 8002ac4:	b580      	push	{r7, lr}
- 8002ac6:	b082      	sub	sp, #8
- 8002ac8:	af00      	add	r7, sp, #0
- 8002aca:	6078      	str	r0, [r7, #4]
+ 8003250:	b580      	push	{r7, lr}
+ 8003252:	b082      	sub	sp, #8
+ 8003254:	af00      	add	r7, sp, #0
+ 8003256:	6078      	str	r0, [r7, #4]
   /* Configure the SysTick to have interrupt in 1ms time basis*/
   if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8002acc:	4b12      	ldr	r3, [pc, #72]	@ (8002b18 <HAL_InitTick+0x54>)
- 8002ace:	681a      	ldr	r2, [r3, #0]
- 8002ad0:	4b12      	ldr	r3, [pc, #72]	@ (8002b1c <HAL_InitTick+0x58>)
- 8002ad2:	781b      	ldrb	r3, [r3, #0]
- 8002ad4:	4619      	mov	r1, r3
- 8002ad6:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
- 8002ada:	fbb3 f3f1 	udiv	r3, r3, r1
- 8002ade:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002ae2:	4618      	mov	r0, r3
- 8002ae4:	f000 fb71 	bl	80031ca <HAL_SYSTICK_Config>
- 8002ae8:	4603      	mov	r3, r0
- 8002aea:	2b00      	cmp	r3, #0
- 8002aec:	d001      	beq.n	8002af2 <HAL_InitTick+0x2e>
+ 8003258:	4b12      	ldr	r3, [pc, #72]	@ (80032a4 <HAL_InitTick+0x54>)
+ 800325a:	681a      	ldr	r2, [r3, #0]
+ 800325c:	4b12      	ldr	r3, [pc, #72]	@ (80032a8 <HAL_InitTick+0x58>)
+ 800325e:	781b      	ldrb	r3, [r3, #0]
+ 8003260:	4619      	mov	r1, r3
+ 8003262:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
+ 8003266:	fbb3 f3f1 	udiv	r3, r3, r1
+ 800326a:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800326e:	4618      	mov	r0, r3
+ 8003270:	f000 fdcf 	bl	8003e12 <HAL_SYSTICK_Config>
+ 8003274:	4603      	mov	r3, r0
+ 8003276:	2b00      	cmp	r3, #0
+ 8003278:	d001      	beq.n	800327e <HAL_InitTick+0x2e>
   {
     return HAL_ERROR;
- 8002aee:	2301      	movs	r3, #1
- 8002af0:	e00e      	b.n	8002b10 <HAL_InitTick+0x4c>
+ 800327a:	2301      	movs	r3, #1
+ 800327c:	e00e      	b.n	800329c <HAL_InitTick+0x4c>
   }
 
   /* Configure the SysTick IRQ priority */
   if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8002af2:	687b      	ldr	r3, [r7, #4]
- 8002af4:	2b0f      	cmp	r3, #15
- 8002af6:	d80a      	bhi.n	8002b0e <HAL_InitTick+0x4a>
+ 800327e:	687b      	ldr	r3, [r7, #4]
+ 8003280:	2b0f      	cmp	r3, #15
+ 8003282:	d80a      	bhi.n	800329a <HAL_InitTick+0x4a>
   {
     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8002af8:	2200      	movs	r2, #0
- 8002afa:	6879      	ldr	r1, [r7, #4]
- 8002afc:	f04f 30ff 	mov.w	r0, #4294967295
- 8002b00:	f000 fb39 	bl	8003176 <HAL_NVIC_SetPriority>
+ 8003284:	2200      	movs	r2, #0
+ 8003286:	6879      	ldr	r1, [r7, #4]
+ 8003288:	f04f 30ff 	mov.w	r0, #4294967295
+ 800328c:	f000 fd97 	bl	8003dbe <HAL_NVIC_SetPriority>
     uwTickPrio = TickPriority;
- 8002b04:	4a06      	ldr	r2, [pc, #24]	@ (8002b20 <HAL_InitTick+0x5c>)
- 8002b06:	687b      	ldr	r3, [r7, #4]
- 8002b08:	6013      	str	r3, [r2, #0]
+ 8003290:	4a06      	ldr	r2, [pc, #24]	@ (80032ac <HAL_InitTick+0x5c>)
+ 8003292:	687b      	ldr	r3, [r7, #4]
+ 8003294:	6013      	str	r3, [r2, #0]
   {
     return HAL_ERROR;
   }
 
   /* Return function status */
   return HAL_OK;
- 8002b0a:	2300      	movs	r3, #0
- 8002b0c:	e000      	b.n	8002b10 <HAL_InitTick+0x4c>
+ 8003296:	2300      	movs	r3, #0
+ 8003298:	e000      	b.n	800329c <HAL_InitTick+0x4c>
     return HAL_ERROR;
- 8002b0e:	2301      	movs	r3, #1
+ 800329a:	2301      	movs	r3, #1
 }
- 8002b10:	4618      	mov	r0, r3
- 8002b12:	3708      	adds	r7, #8
- 8002b14:	46bd      	mov	sp, r7
- 8002b16:	bd80      	pop	{r7, pc}
- 8002b18:	2000001c 	.word	0x2000001c
- 8002b1c:	20000024 	.word	0x20000024
- 8002b20:	20000020 	.word	0x20000020
+ 800329c:	4618      	mov	r0, r3
+ 800329e:	3708      	adds	r7, #8
+ 80032a0:	46bd      	mov	sp, r7
+ 80032a2:	bd80      	pop	{r7, pc}
+ 80032a4:	20000024 	.word	0x20000024
+ 80032a8:	2000002c 	.word	0x2000002c
+ 80032ac:	20000028 	.word	0x20000028
 
-08002b24 <HAL_IncTick>:
+080032b0 <HAL_IncTick>:
   * @note This function is declared as __weak to be overwritten in case of other
   *      implementations in user file.
   * @retval None
   */
 __weak void HAL_IncTick(void)
 {
- 8002b24:	b480      	push	{r7}
- 8002b26:	af00      	add	r7, sp, #0
+ 80032b0:	b480      	push	{r7}
+ 80032b2:	af00      	add	r7, sp, #0
   uwTick += uwTickFreq;
- 8002b28:	4b05      	ldr	r3, [pc, #20]	@ (8002b40 <HAL_IncTick+0x1c>)
- 8002b2a:	781b      	ldrb	r3, [r3, #0]
- 8002b2c:	461a      	mov	r2, r3
- 8002b2e:	4b05      	ldr	r3, [pc, #20]	@ (8002b44 <HAL_IncTick+0x20>)
- 8002b30:	681b      	ldr	r3, [r3, #0]
- 8002b32:	4413      	add	r3, r2
- 8002b34:	4a03      	ldr	r2, [pc, #12]	@ (8002b44 <HAL_IncTick+0x20>)
- 8002b36:	6013      	str	r3, [r2, #0]
+ 80032b4:	4b05      	ldr	r3, [pc, #20]	@ (80032cc <HAL_IncTick+0x1c>)
+ 80032b6:	781b      	ldrb	r3, [r3, #0]
+ 80032b8:	461a      	mov	r2, r3
+ 80032ba:	4b05      	ldr	r3, [pc, #20]	@ (80032d0 <HAL_IncTick+0x20>)
+ 80032bc:	681b      	ldr	r3, [r3, #0]
+ 80032be:	4413      	add	r3, r2
+ 80032c0:	4a03      	ldr	r2, [pc, #12]	@ (80032d0 <HAL_IncTick+0x20>)
+ 80032c2:	6013      	str	r3, [r2, #0]
 }
- 8002b38:	bf00      	nop
- 8002b3a:	46bd      	mov	sp, r7
- 8002b3c:	bc80      	pop	{r7}
- 8002b3e:	4770      	bx	lr
- 8002b40:	20000024 	.word	0x20000024
- 8002b44:	20000320 	.word	0x20000320
+ 80032c4:	bf00      	nop
+ 80032c6:	46bd      	mov	sp, r7
+ 80032c8:	bc80      	pop	{r7}
+ 80032ca:	4770      	bx	lr
+ 80032cc:	2000002c 	.word	0x2000002c
+ 80032d0:	200007b0 	.word	0x200007b0
 
-08002b48 <HAL_GetTick>:
+080032d4 <HAL_GetTick>:
   * @note  This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
   * @retval tick value
   */
 __weak uint32_t HAL_GetTick(void)
 {
- 8002b48:	b480      	push	{r7}
- 8002b4a:	af00      	add	r7, sp, #0
+ 80032d4:	b480      	push	{r7}
+ 80032d6:	af00      	add	r7, sp, #0
   return uwTick;
- 8002b4c:	4b02      	ldr	r3, [pc, #8]	@ (8002b58 <HAL_GetTick+0x10>)
- 8002b4e:	681b      	ldr	r3, [r3, #0]
+ 80032d8:	4b02      	ldr	r3, [pc, #8]	@ (80032e4 <HAL_GetTick+0x10>)
+ 80032da:	681b      	ldr	r3, [r3, #0]
 }
- 8002b50:	4618      	mov	r0, r3
- 8002b52:	46bd      	mov	sp, r7
- 8002b54:	bc80      	pop	{r7}
- 8002b56:	4770      	bx	lr
- 8002b58:	20000320 	.word	0x20000320
+ 80032dc:	4618      	mov	r0, r3
+ 80032de:	46bd      	mov	sp, r7
+ 80032e0:	bc80      	pop	{r7}
+ 80032e2:	4770      	bx	lr
+ 80032e4:	200007b0 	.word	0x200007b0
 
-08002b5c <HAL_Delay>:
+080032e8 <HAL_Delay>:
   *       implementations in user file.
   * @param Delay specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(uint32_t Delay)
 {
- 8002b5c:	b580      	push	{r7, lr}
- 8002b5e:	b084      	sub	sp, #16
- 8002b60:	af00      	add	r7, sp, #0
- 8002b62:	6078      	str	r0, [r7, #4]
+ 80032e8:	b580      	push	{r7, lr}
+ 80032ea:	b084      	sub	sp, #16
+ 80032ec:	af00      	add	r7, sp, #0
+ 80032ee:	6078      	str	r0, [r7, #4]
   uint32_t tickstart = HAL_GetTick();
- 8002b64:	f7ff fff0 	bl	8002b48 <HAL_GetTick>
- 8002b68:	60b8      	str	r0, [r7, #8]
+ 80032f0:	f7ff fff0 	bl	80032d4 <HAL_GetTick>
+ 80032f4:	60b8      	str	r0, [r7, #8]
   uint32_t wait = Delay;
- 8002b6a:	687b      	ldr	r3, [r7, #4]
- 8002b6c:	60fb      	str	r3, [r7, #12]
+ 80032f6:	687b      	ldr	r3, [r7, #4]
+ 80032f8:	60fb      	str	r3, [r7, #12]
 
   /* Add a freq to guarantee minimum wait */
   if (wait < HAL_MAX_DELAY)
- 8002b6e:	68fb      	ldr	r3, [r7, #12]
- 8002b70:	f1b3 3fff 	cmp.w	r3, #4294967295
- 8002b74:	d005      	beq.n	8002b82 <HAL_Delay+0x26>
+ 80032fa:	68fb      	ldr	r3, [r7, #12]
+ 80032fc:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8003300:	d005      	beq.n	800330e <HAL_Delay+0x26>
   {
     wait += (uint32_t)(uwTickFreq);
- 8002b76:	4b0a      	ldr	r3, [pc, #40]	@ (8002ba0 <HAL_Delay+0x44>)
- 8002b78:	781b      	ldrb	r3, [r3, #0]
- 8002b7a:	461a      	mov	r2, r3
- 8002b7c:	68fb      	ldr	r3, [r7, #12]
- 8002b7e:	4413      	add	r3, r2
- 8002b80:	60fb      	str	r3, [r7, #12]
+ 8003302:	4b0a      	ldr	r3, [pc, #40]	@ (800332c <HAL_Delay+0x44>)
+ 8003304:	781b      	ldrb	r3, [r3, #0]
+ 8003306:	461a      	mov	r2, r3
+ 8003308:	68fb      	ldr	r3, [r7, #12]
+ 800330a:	4413      	add	r3, r2
+ 800330c:	60fb      	str	r3, [r7, #12]
   }
 
   while ((HAL_GetTick() - tickstart) < wait)
- 8002b82:	bf00      	nop
- 8002b84:	f7ff ffe0 	bl	8002b48 <HAL_GetTick>
- 8002b88:	4602      	mov	r2, r0
- 8002b8a:	68bb      	ldr	r3, [r7, #8]
- 8002b8c:	1ad3      	subs	r3, r2, r3
- 8002b8e:	68fa      	ldr	r2, [r7, #12]
- 8002b90:	429a      	cmp	r2, r3
- 8002b92:	d8f7      	bhi.n	8002b84 <HAL_Delay+0x28>
+ 800330e:	bf00      	nop
+ 8003310:	f7ff ffe0 	bl	80032d4 <HAL_GetTick>
+ 8003314:	4602      	mov	r2, r0
+ 8003316:	68bb      	ldr	r3, [r7, #8]
+ 8003318:	1ad3      	subs	r3, r2, r3
+ 800331a:	68fa      	ldr	r2, [r7, #12]
+ 800331c:	429a      	cmp	r2, r3
+ 800331e:	d8f7      	bhi.n	8003310 <HAL_Delay+0x28>
   {
   }
 }
- 8002b94:	bf00      	nop
- 8002b96:	bf00      	nop
- 8002b98:	3710      	adds	r7, #16
- 8002b9a:	46bd      	mov	sp, r7
- 8002b9c:	bd80      	pop	{r7, pc}
- 8002b9e:	bf00      	nop
- 8002ba0:	20000024 	.word	0x20000024
+ 8003320:	bf00      	nop
+ 8003322:	bf00      	nop
+ 8003324:	3710      	adds	r7, #16
+ 8003326:	46bd      	mov	sp, r7
+ 8003328:	bd80      	pop	{r7, pc}
+ 800332a:	bf00      	nop
+ 800332c:	2000002c 	.word	0x2000002c
 
-08002ba4 <HAL_ADC_Init>:
+08003330 <HAL_ADC_Init>:
   *         of structure "ADC_InitTypeDef".
   * @param  hadc: ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 {
- 8002ba4:	b580      	push	{r7, lr}
- 8002ba6:	b086      	sub	sp, #24
- 8002ba8:	af00      	add	r7, sp, #0
- 8002baa:	6078      	str	r0, [r7, #4]
+ 8003330:	b580      	push	{r7, lr}
+ 8003332:	b086      	sub	sp, #24
+ 8003334:	af00      	add	r7, sp, #0
+ 8003336:	6078      	str	r0, [r7, #4]
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- 8002bac:	2300      	movs	r3, #0
- 8002bae:	75fb      	strb	r3, [r7, #23]
+ 8003338:	2300      	movs	r3, #0
+ 800333a:	75fb      	strb	r3, [r7, #23]
   uint32_t tmp_cr1 = 0U;
- 8002bb0:	2300      	movs	r3, #0
- 8002bb2:	613b      	str	r3, [r7, #16]
+ 800333c:	2300      	movs	r3, #0
+ 800333e:	613b      	str	r3, [r7, #16]
   uint32_t tmp_cr2 = 0U;
- 8002bb4:	2300      	movs	r3, #0
- 8002bb6:	60bb      	str	r3, [r7, #8]
+ 8003340:	2300      	movs	r3, #0
+ 8003342:	60bb      	str	r3, [r7, #8]
   uint32_t tmp_sqr1 = 0U;
- 8002bb8:	2300      	movs	r3, #0
- 8002bba:	60fb      	str	r3, [r7, #12]
+ 8003344:	2300      	movs	r3, #0
+ 8003346:	60fb      	str	r3, [r7, #12]
   
   /* Check ADC handle */
   if(hadc == NULL)
- 8002bbc:	687b      	ldr	r3, [r7, #4]
- 8002bbe:	2b00      	cmp	r3, #0
- 8002bc0:	d101      	bne.n	8002bc6 <HAL_ADC_Init+0x22>
+ 8003348:	687b      	ldr	r3, [r7, #4]
+ 800334a:	2b00      	cmp	r3, #0
+ 800334c:	d101      	bne.n	8003352 <HAL_ADC_Init+0x22>
   {
     return HAL_ERROR;
- 8002bc2:	2301      	movs	r3, #1
- 8002bc4:	e0be      	b.n	8002d44 <HAL_ADC_Init+0x1a0>
+ 800334e:	2301      	movs	r3, #1
+ 8003350:	e0be      	b.n	80034d0 <HAL_ADC_Init+0x1a0>
   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
   
   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- 8002bc6:	687b      	ldr	r3, [r7, #4]
- 8002bc8:	689b      	ldr	r3, [r3, #8]
- 8002bca:	2b00      	cmp	r3, #0
+ 8003352:	687b      	ldr	r3, [r7, #4]
+ 8003354:	689b      	ldr	r3, [r3, #8]
+ 8003356:	2b00      	cmp	r3, #0
   /* Refer to header of this file for more details on clock enabling          */
   /* procedure.                                                               */
 
   /* Actions performed only if ADC is coming from state reset:                */
   /* - Initialization of ADC MSP                                              */
   if (hadc->State == HAL_ADC_STATE_RESET)
- 8002bcc:	687b      	ldr	r3, [r7, #4]
- 8002bce:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002bd0:	2b00      	cmp	r3, #0
- 8002bd2:	d109      	bne.n	8002be8 <HAL_ADC_Init+0x44>
+ 8003358:	687b      	ldr	r3, [r7, #4]
+ 800335a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 800335c:	2b00      	cmp	r3, #0
+ 800335e:	d109      	bne.n	8003374 <HAL_ADC_Init+0x44>
   {
     /* Initialize ADC error code */
     ADC_CLEAR_ERRORCODE(hadc);
- 8002bd4:	687b      	ldr	r3, [r7, #4]
- 8002bd6:	2200      	movs	r2, #0
- 8002bd8:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8003360:	687b      	ldr	r3, [r7, #4]
+ 8003362:	2200      	movs	r2, #0
+ 8003364:	62da      	str	r2, [r3, #44]	@ 0x2c
     
     /* Allocate lock resource and initialize it */
     hadc->Lock = HAL_UNLOCKED;
- 8002bda:	687b      	ldr	r3, [r7, #4]
- 8002bdc:	2200      	movs	r2, #0
- 8002bde:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+ 8003366:	687b      	ldr	r3, [r7, #4]
+ 8003368:	2200      	movs	r2, #0
+ 800336a:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
     
     /* Init the low level hardware */
     hadc->MspInitCallback(hadc);
 #else
     /* Init the low level hardware */
     HAL_ADC_MspInit(hadc);
- 8002be2:	6878      	ldr	r0, [r7, #4]
- 8002be4:	f7fe ff1a 	bl	8001a1c <HAL_ADC_MspInit>
+ 800336e:	6878      	ldr	r0, [r7, #4]
+ 8003370:	f7fe fc1e 	bl	8001bb0 <HAL_ADC_MspInit>
   /* Stop potential conversion on going, on regular and injected groups */
   /* Disable ADC peripheral */
   /* Note: In case of ADC already enabled, precaution to not launch an        */
   /*       unwanted conversion while modifying register CR2 by writing 1 to   */
   /*       bit ADON.                                                          */
   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
- 8002be8:	6878      	ldr	r0, [r7, #4]
- 8002bea:	f000 f9ab 	bl	8002f44 <ADC_ConversionStop_Disable>
- 8002bee:	4603      	mov	r3, r0
- 8002bf0:	75fb      	strb	r3, [r7, #23]
+ 8003374:	6878      	ldr	r0, [r7, #4]
+ 8003376:	f000 faf5 	bl	8003964 <ADC_ConversionStop_Disable>
+ 800337a:	4603      	mov	r3, r0
+ 800337c:	75fb      	strb	r3, [r7, #23]
   
   
   /* Configuration of ADC parameters if previous preliminary actions are      */ 
   /* correctly completed.                                                     */
   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- 8002bf2:	687b      	ldr	r3, [r7, #4]
- 8002bf4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002bf6:	f003 0310 	and.w	r3, r3, #16
- 8002bfa:	2b00      	cmp	r3, #0
- 8002bfc:	f040 8099 	bne.w	8002d32 <HAL_ADC_Init+0x18e>
- 8002c00:	7dfb      	ldrb	r3, [r7, #23]
- 8002c02:	2b00      	cmp	r3, #0
- 8002c04:	f040 8095 	bne.w	8002d32 <HAL_ADC_Init+0x18e>
+ 800337e:	687b      	ldr	r3, [r7, #4]
+ 8003380:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003382:	f003 0310 	and.w	r3, r3, #16
+ 8003386:	2b00      	cmp	r3, #0
+ 8003388:	f040 8099 	bne.w	80034be <HAL_ADC_Init+0x18e>
+ 800338c:	7dfb      	ldrb	r3, [r7, #23]
+ 800338e:	2b00      	cmp	r3, #0
+ 8003390:	f040 8095 	bne.w	80034be <HAL_ADC_Init+0x18e>
       (tmp_hal_status == HAL_OK)                                  )
   {
     /* Set ADC state */
     ADC_STATE_CLR_SET(hadc->State,
- 8002c08:	687b      	ldr	r3, [r7, #4]
- 8002c0a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002c0c:	f423 5388 	bic.w	r3, r3, #4352	@ 0x1100
- 8002c10:	f023 0302 	bic.w	r3, r3, #2
- 8002c14:	f043 0202 	orr.w	r2, r3, #2
- 8002c18:	687b      	ldr	r3, [r7, #4]
- 8002c1a:	629a      	str	r2, [r3, #40]	@ 0x28
+ 8003394:	687b      	ldr	r3, [r7, #4]
+ 8003396:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003398:	f423 5388 	bic.w	r3, r3, #4352	@ 0x1100
+ 800339c:	f023 0302 	bic.w	r3, r3, #2
+ 80033a0:	f043 0202 	orr.w	r2, r3, #2
+ 80033a4:	687b      	ldr	r3, [r7, #4]
+ 80033a6:	629a      	str	r2, [r3, #40]	@ 0x28
     /*  - continuous conversion mode                                          */
     /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
     /*       HAL_ADC_Start_xxx functions because if set in this function,     */
     /*       a conversion on injected group would start a conversion also on  */
     /*       regular group after ADC enabling.                                */
     tmp_cr2 |= (hadc->Init.DataAlign                                          |
- 8002c1c:	687b      	ldr	r3, [r7, #4]
- 8002c1e:	685a      	ldr	r2, [r3, #4]
+ 80033a8:	687b      	ldr	r3, [r7, #4]
+ 80033aa:	685a      	ldr	r2, [r3, #4]
                 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
- 8002c20:	687b      	ldr	r3, [r7, #4]
- 8002c22:	69db      	ldr	r3, [r3, #28]
+ 80033ac:	687b      	ldr	r3, [r7, #4]
+ 80033ae:	69db      	ldr	r3, [r3, #28]
     tmp_cr2 |= (hadc->Init.DataAlign                                          |
- 8002c24:	431a      	orrs	r2, r3
+ 80033b0:	431a      	orrs	r2, r3
                 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)   );
- 8002c26:	687b      	ldr	r3, [r7, #4]
- 8002c28:	7b1b      	ldrb	r3, [r3, #12]
- 8002c2a:	005b      	lsls	r3, r3, #1
+ 80033b2:	687b      	ldr	r3, [r7, #4]
+ 80033b4:	7b1b      	ldrb	r3, [r3, #12]
+ 80033b6:	005b      	lsls	r3, r3, #1
                 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
- 8002c2c:	4313      	orrs	r3, r2
+ 80033b8:	4313      	orrs	r3, r2
     tmp_cr2 |= (hadc->Init.DataAlign                                          |
- 8002c2e:	68ba      	ldr	r2, [r7, #8]
- 8002c30:	4313      	orrs	r3, r2
- 8002c32:	60bb      	str	r3, [r7, #8]
+ 80033ba:	68ba      	ldr	r2, [r7, #8]
+ 80033bc:	4313      	orrs	r3, r2
+ 80033be:	60bb      	str	r3, [r7, #8]
 
     /* Configuration of ADC:                                                  */
     /*  - scan mode                                                           */
     /*  - discontinuous mode disable/enable                                   */
     /*  - discontinuous mode number of conversions                            */
     tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
- 8002c34:	687b      	ldr	r3, [r7, #4]
- 8002c36:	689b      	ldr	r3, [r3, #8]
- 8002c38:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
- 8002c3c:	d003      	beq.n	8002c46 <HAL_ADC_Init+0xa2>
- 8002c3e:	687b      	ldr	r3, [r7, #4]
- 8002c40:	689b      	ldr	r3, [r3, #8]
- 8002c42:	2b01      	cmp	r3, #1
- 8002c44:	d102      	bne.n	8002c4c <HAL_ADC_Init+0xa8>
- 8002c46:	f44f 7380 	mov.w	r3, #256	@ 0x100
- 8002c4a:	e000      	b.n	8002c4e <HAL_ADC_Init+0xaa>
- 8002c4c:	2300      	movs	r3, #0
- 8002c4e:	693a      	ldr	r2, [r7, #16]
- 8002c50:	4313      	orrs	r3, r2
- 8002c52:	613b      	str	r3, [r7, #16]
+ 80033c0:	687b      	ldr	r3, [r7, #4]
+ 80033c2:	689b      	ldr	r3, [r3, #8]
+ 80033c4:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 80033c8:	d003      	beq.n	80033d2 <HAL_ADC_Init+0xa2>
+ 80033ca:	687b      	ldr	r3, [r7, #4]
+ 80033cc:	689b      	ldr	r3, [r3, #8]
+ 80033ce:	2b01      	cmp	r3, #1
+ 80033d0:	d102      	bne.n	80033d8 <HAL_ADC_Init+0xa8>
+ 80033d2:	f44f 7380 	mov.w	r3, #256	@ 0x100
+ 80033d6:	e000      	b.n	80033da <HAL_ADC_Init+0xaa>
+ 80033d8:	2300      	movs	r3, #0
+ 80033da:	693a      	ldr	r2, [r7, #16]
+ 80033dc:	4313      	orrs	r3, r2
+ 80033de:	613b      	str	r3, [r7, #16]
     
     /* Enable discontinuous mode only if continuous mode is disabled */
     /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
     /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
     if (hadc->Init.DiscontinuousConvMode == ENABLE)
- 8002c54:	687b      	ldr	r3, [r7, #4]
- 8002c56:	7d1b      	ldrb	r3, [r3, #20]
- 8002c58:	2b01      	cmp	r3, #1
- 8002c5a:	d119      	bne.n	8002c90 <HAL_ADC_Init+0xec>
+ 80033e0:	687b      	ldr	r3, [r7, #4]
+ 80033e2:	7d1b      	ldrb	r3, [r3, #20]
+ 80033e4:	2b01      	cmp	r3, #1
+ 80033e6:	d119      	bne.n	800341c <HAL_ADC_Init+0xec>
     {
       if (hadc->Init.ContinuousConvMode == DISABLE)
- 8002c5c:	687b      	ldr	r3, [r7, #4]
- 8002c5e:	7b1b      	ldrb	r3, [r3, #12]
- 8002c60:	2b00      	cmp	r3, #0
- 8002c62:	d109      	bne.n	8002c78 <HAL_ADC_Init+0xd4>
+ 80033e8:	687b      	ldr	r3, [r7, #4]
+ 80033ea:	7b1b      	ldrb	r3, [r3, #12]
+ 80033ec:	2b00      	cmp	r3, #0
+ 80033ee:	d109      	bne.n	8003404 <HAL_ADC_Init+0xd4>
       {
         /* Enable the selected ADC regular discontinuous mode */
         /* Set the number of channels to be converted in discontinuous mode */
         SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
- 8002c64:	687b      	ldr	r3, [r7, #4]
- 8002c66:	699b      	ldr	r3, [r3, #24]
- 8002c68:	3b01      	subs	r3, #1
- 8002c6a:	035a      	lsls	r2, r3, #13
- 8002c6c:	693b      	ldr	r3, [r7, #16]
- 8002c6e:	4313      	orrs	r3, r2
- 8002c70:	f443 6300 	orr.w	r3, r3, #2048	@ 0x800
- 8002c74:	613b      	str	r3, [r7, #16]
- 8002c76:	e00b      	b.n	8002c90 <HAL_ADC_Init+0xec>
+ 80033f0:	687b      	ldr	r3, [r7, #4]
+ 80033f2:	699b      	ldr	r3, [r3, #24]
+ 80033f4:	3b01      	subs	r3, #1
+ 80033f6:	035a      	lsls	r2, r3, #13
+ 80033f8:	693b      	ldr	r3, [r7, #16]
+ 80033fa:	4313      	orrs	r3, r2
+ 80033fc:	f443 6300 	orr.w	r3, r3, #2048	@ 0x800
+ 8003400:	613b      	str	r3, [r7, #16]
+ 8003402:	e00b      	b.n	800341c <HAL_ADC_Init+0xec>
       {
         /* ADC regular group settings continuous and sequencer discontinuous*/
         /* cannot be enabled simultaneously.                                */
         
         /* Update ADC state machine to error */
         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- 8002c78:	687b      	ldr	r3, [r7, #4]
- 8002c7a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002c7c:	f043 0220 	orr.w	r2, r3, #32
- 8002c80:	687b      	ldr	r3, [r7, #4]
- 8002c82:	629a      	str	r2, [r3, #40]	@ 0x28
+ 8003404:	687b      	ldr	r3, [r7, #4]
+ 8003406:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003408:	f043 0220 	orr.w	r2, r3, #32
+ 800340c:	687b      	ldr	r3, [r7, #4]
+ 800340e:	629a      	str	r2, [r3, #40]	@ 0x28
         
         /* Set ADC error code to ADC IP internal error */
         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- 8002c84:	687b      	ldr	r3, [r7, #4]
- 8002c86:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8002c88:	f043 0201 	orr.w	r2, r3, #1
- 8002c8c:	687b      	ldr	r3, [r7, #4]
- 8002c8e:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8003410:	687b      	ldr	r3, [r7, #4]
+ 8003412:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8003414:	f043 0201 	orr.w	r2, r3, #1
+ 8003418:	687b      	ldr	r3, [r7, #4]
+ 800341a:	62da      	str	r2, [r3, #44]	@ 0x2c
       }
     }
     
     /* Update ADC configuration register CR1 with previous settings */
       MODIFY_REG(hadc->Instance->CR1,
- 8002c90:	687b      	ldr	r3, [r7, #4]
- 8002c92:	681b      	ldr	r3, [r3, #0]
- 8002c94:	685b      	ldr	r3, [r3, #4]
- 8002c96:	f423 4169 	bic.w	r1, r3, #59648	@ 0xe900
- 8002c9a:	687b      	ldr	r3, [r7, #4]
- 8002c9c:	681b      	ldr	r3, [r3, #0]
- 8002c9e:	693a      	ldr	r2, [r7, #16]
- 8002ca0:	430a      	orrs	r2, r1
- 8002ca2:	605a      	str	r2, [r3, #4]
+ 800341c:	687b      	ldr	r3, [r7, #4]
+ 800341e:	681b      	ldr	r3, [r3, #0]
+ 8003420:	685b      	ldr	r3, [r3, #4]
+ 8003422:	f423 4169 	bic.w	r1, r3, #59648	@ 0xe900
+ 8003426:	687b      	ldr	r3, [r7, #4]
+ 8003428:	681b      	ldr	r3, [r3, #0]
+ 800342a:	693a      	ldr	r2, [r7, #16]
+ 800342c:	430a      	orrs	r2, r1
+ 800342e:	605a      	str	r2, [r3, #4]
                  ADC_CR1_DISCEN  |
                  ADC_CR1_DISCNUM    ,
                  tmp_cr1             );
     
     /* Update ADC configuration register CR2 with previous settings */
       MODIFY_REG(hadc->Instance->CR2,
- 8002ca4:	687b      	ldr	r3, [r7, #4]
- 8002ca6:	681b      	ldr	r3, [r3, #0]
- 8002ca8:	689a      	ldr	r2, [r3, #8]
- 8002caa:	4b28      	ldr	r3, [pc, #160]	@ (8002d4c <HAL_ADC_Init+0x1a8>)
- 8002cac:	4013      	ands	r3, r2
- 8002cae:	687a      	ldr	r2, [r7, #4]
- 8002cb0:	6812      	ldr	r2, [r2, #0]
- 8002cb2:	68b9      	ldr	r1, [r7, #8]
- 8002cb4:	430b      	orrs	r3, r1
- 8002cb6:	6093      	str	r3, [r2, #8]
+ 8003430:	687b      	ldr	r3, [r7, #4]
+ 8003432:	681b      	ldr	r3, [r3, #0]
+ 8003434:	689a      	ldr	r2, [r3, #8]
+ 8003436:	4b28      	ldr	r3, [pc, #160]	@ (80034d8 <HAL_ADC_Init+0x1a8>)
+ 8003438:	4013      	ands	r3, r2
+ 800343a:	687a      	ldr	r2, [r7, #4]
+ 800343c:	6812      	ldr	r2, [r2, #0]
+ 800343e:	68b9      	ldr	r1, [r7, #8]
+ 8003440:	430b      	orrs	r3, r1
+ 8003442:	6093      	str	r3, [r2, #8]
     /*   Note: Scan mode is present by hardware on this device and, if        */
     /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
     /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
     /* - if scan mode is enabled, regular channels sequence length is set to  */
     /*   parameter "NbrOfConversion"                                          */
     if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
- 8002cb8:	687b      	ldr	r3, [r7, #4]
- 8002cba:	689b      	ldr	r3, [r3, #8]
- 8002cbc:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
- 8002cc0:	d003      	beq.n	8002cca <HAL_ADC_Init+0x126>
- 8002cc2:	687b      	ldr	r3, [r7, #4]
- 8002cc4:	689b      	ldr	r3, [r3, #8]
- 8002cc6:	2b01      	cmp	r3, #1
- 8002cc8:	d104      	bne.n	8002cd4 <HAL_ADC_Init+0x130>
+ 8003444:	687b      	ldr	r3, [r7, #4]
+ 8003446:	689b      	ldr	r3, [r3, #8]
+ 8003448:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 800344c:	d003      	beq.n	8003456 <HAL_ADC_Init+0x126>
+ 800344e:	687b      	ldr	r3, [r7, #4]
+ 8003450:	689b      	ldr	r3, [r3, #8]
+ 8003452:	2b01      	cmp	r3, #1
+ 8003454:	d104      	bne.n	8003460 <HAL_ADC_Init+0x130>
     {
       tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
- 8002cca:	687b      	ldr	r3, [r7, #4]
- 8002ccc:	691b      	ldr	r3, [r3, #16]
- 8002cce:	3b01      	subs	r3, #1
- 8002cd0:	051b      	lsls	r3, r3, #20
- 8002cd2:	60fb      	str	r3, [r7, #12]
+ 8003456:	687b      	ldr	r3, [r7, #4]
+ 8003458:	691b      	ldr	r3, [r3, #16]
+ 800345a:	3b01      	subs	r3, #1
+ 800345c:	051b      	lsls	r3, r3, #20
+ 800345e:	60fb      	str	r3, [r7, #12]
     }
       
     MODIFY_REG(hadc->Instance->SQR1,
- 8002cd4:	687b      	ldr	r3, [r7, #4]
- 8002cd6:	681b      	ldr	r3, [r3, #0]
- 8002cd8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8002cda:	f423 0170 	bic.w	r1, r3, #15728640	@ 0xf00000
- 8002cde:	687b      	ldr	r3, [r7, #4]
- 8002ce0:	681b      	ldr	r3, [r3, #0]
- 8002ce2:	68fa      	ldr	r2, [r7, #12]
- 8002ce4:	430a      	orrs	r2, r1
- 8002ce6:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8003460:	687b      	ldr	r3, [r7, #4]
+ 8003462:	681b      	ldr	r3, [r3, #0]
+ 8003464:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8003466:	f423 0170 	bic.w	r1, r3, #15728640	@ 0xf00000
+ 800346a:	687b      	ldr	r3, [r7, #4]
+ 800346c:	681b      	ldr	r3, [r3, #0]
+ 800346e:	68fa      	ldr	r2, [r7, #12]
+ 8003470:	430a      	orrs	r2, r1
+ 8003472:	62da      	str	r2, [r3, #44]	@ 0x2c
     /* ensure of no potential problem of ADC core IP clocking.                */
     /* Check through register CR2 (excluding bits set in other functions:     */
     /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
     /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
     /* measurement path bit (TSVREFE).                                        */
     if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
- 8002ce8:	687b      	ldr	r3, [r7, #4]
- 8002cea:	681b      	ldr	r3, [r3, #0]
- 8002cec:	689a      	ldr	r2, [r3, #8]
- 8002cee:	4b18      	ldr	r3, [pc, #96]	@ (8002d50 <HAL_ADC_Init+0x1ac>)
- 8002cf0:	4013      	ands	r3, r2
- 8002cf2:	68ba      	ldr	r2, [r7, #8]
- 8002cf4:	429a      	cmp	r2, r3
- 8002cf6:	d10b      	bne.n	8002d10 <HAL_ADC_Init+0x16c>
+ 8003474:	687b      	ldr	r3, [r7, #4]
+ 8003476:	681b      	ldr	r3, [r3, #0]
+ 8003478:	689a      	ldr	r2, [r3, #8]
+ 800347a:	4b18      	ldr	r3, [pc, #96]	@ (80034dc <HAL_ADC_Init+0x1ac>)
+ 800347c:	4013      	ands	r3, r2
+ 800347e:	68ba      	ldr	r2, [r7, #8]
+ 8003480:	429a      	cmp	r2, r3
+ 8003482:	d10b      	bne.n	800349c <HAL_ADC_Init+0x16c>
                                         ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
                                         ADC_CR2_TSVREFE                     ))
          == tmp_cr2)
     {
       /* Set ADC error code to none */
       ADC_CLEAR_ERRORCODE(hadc);
- 8002cf8:	687b      	ldr	r3, [r7, #4]
- 8002cfa:	2200      	movs	r2, #0
- 8002cfc:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8003484:	687b      	ldr	r3, [r7, #4]
+ 8003486:	2200      	movs	r2, #0
+ 8003488:	62da      	str	r2, [r3, #44]	@ 0x2c
       
       /* Set the ADC state */
       ADC_STATE_CLR_SET(hadc->State,
- 8002cfe:	687b      	ldr	r3, [r7, #4]
- 8002d00:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002d02:	f023 0303 	bic.w	r3, r3, #3
- 8002d06:	f043 0201 	orr.w	r2, r3, #1
- 8002d0a:	687b      	ldr	r3, [r7, #4]
- 8002d0c:	629a      	str	r2, [r3, #40]	@ 0x28
+ 800348a:	687b      	ldr	r3, [r7, #4]
+ 800348c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 800348e:	f023 0303 	bic.w	r3, r3, #3
+ 8003492:	f043 0201 	orr.w	r2, r3, #1
+ 8003496:	687b      	ldr	r3, [r7, #4]
+ 8003498:	629a      	str	r2, [r3, #40]	@ 0x28
     if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
- 8002d0e:	e018      	b.n	8002d42 <HAL_ADC_Init+0x19e>
+ 800349a:	e018      	b.n	80034ce <HAL_ADC_Init+0x19e>
                         HAL_ADC_STATE_READY);
     }
     else
     {
       /* Update ADC state machine to error */
       ADC_STATE_CLR_SET(hadc->State,
- 8002d10:	687b      	ldr	r3, [r7, #4]
- 8002d12:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002d14:	f023 0312 	bic.w	r3, r3, #18
- 8002d18:	f043 0210 	orr.w	r2, r3, #16
- 8002d1c:	687b      	ldr	r3, [r7, #4]
- 8002d1e:	629a      	str	r2, [r3, #40]	@ 0x28
+ 800349c:	687b      	ldr	r3, [r7, #4]
+ 800349e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80034a0:	f023 0312 	bic.w	r3, r3, #18
+ 80034a4:	f043 0210 	orr.w	r2, r3, #16
+ 80034a8:	687b      	ldr	r3, [r7, #4]
+ 80034aa:	629a      	str	r2, [r3, #40]	@ 0x28
                         HAL_ADC_STATE_BUSY_INTERNAL,
                         HAL_ADC_STATE_ERROR_INTERNAL);
       
       /* Set ADC error code to ADC IP internal error */
       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- 8002d20:	687b      	ldr	r3, [r7, #4]
- 8002d22:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8002d24:	f043 0201 	orr.w	r2, r3, #1
- 8002d28:	687b      	ldr	r3, [r7, #4]
- 8002d2a:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 80034ac:	687b      	ldr	r3, [r7, #4]
+ 80034ae:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80034b0:	f043 0201 	orr.w	r2, r3, #1
+ 80034b4:	687b      	ldr	r3, [r7, #4]
+ 80034b6:	62da      	str	r2, [r3, #44]	@ 0x2c
       
       tmp_hal_status = HAL_ERROR;
- 8002d2c:	2301      	movs	r3, #1
- 8002d2e:	75fb      	strb	r3, [r7, #23]
+ 80034b8:	2301      	movs	r3, #1
+ 80034ba:	75fb      	strb	r3, [r7, #23]
     if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
- 8002d30:	e007      	b.n	8002d42 <HAL_ADC_Init+0x19e>
+ 80034bc:	e007      	b.n	80034ce <HAL_ADC_Init+0x19e>
   
   }
   else
   {
     /* Update ADC state machine to error */
     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- 8002d32:	687b      	ldr	r3, [r7, #4]
- 8002d34:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002d36:	f043 0210 	orr.w	r2, r3, #16
- 8002d3a:	687b      	ldr	r3, [r7, #4]
- 8002d3c:	629a      	str	r2, [r3, #40]	@ 0x28
+ 80034be:	687b      	ldr	r3, [r7, #4]
+ 80034c0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80034c2:	f043 0210 	orr.w	r2, r3, #16
+ 80034c6:	687b      	ldr	r3, [r7, #4]
+ 80034c8:	629a      	str	r2, [r3, #40]	@ 0x28
         
     tmp_hal_status = HAL_ERROR;
- 8002d3e:	2301      	movs	r3, #1
- 8002d40:	75fb      	strb	r3, [r7, #23]
+ 80034ca:	2301      	movs	r3, #1
+ 80034cc:	75fb      	strb	r3, [r7, #23]
   }
   
   /* Return function status */
   return tmp_hal_status;
- 8002d42:	7dfb      	ldrb	r3, [r7, #23]
+ 80034ce:	7dfb      	ldrb	r3, [r7, #23]
 }
- 8002d44:	4618      	mov	r0, r3
- 8002d46:	3718      	adds	r7, #24
- 8002d48:	46bd      	mov	sp, r7
- 8002d4a:	bd80      	pop	{r7, pc}
- 8002d4c:	ffe1f7fd 	.word	0xffe1f7fd
- 8002d50:	ff1f0efe 	.word	0xff1f0efe
+ 80034d0:	4618      	mov	r0, r3
+ 80034d2:	3718      	adds	r7, #24
+ 80034d4:	46bd      	mov	sp, r7
+ 80034d6:	bd80      	pop	{r7, pc}
+ 80034d8:	ffe1f7fd 	.word	0xffe1f7fd
+ 80034dc:	ff1f0efe 	.word	0xff1f0efe
 
-08002d54 <HAL_ADC_ConfigChannel>:
-  * @param  hadc: ADC handle
-  * @param  sConfig: Structure of ADC channel for regular group.
-  * @retval HAL status
+080034e0 <HAL_ADC_Start_DMA>:
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{ 
- 8002d54:	b480      	push	{r7}
- 8002d56:	b085      	sub	sp, #20
- 8002d58:	af00      	add	r7, sp, #0
- 8002d5a:	6078      	str	r0, [r7, #4]
- 8002d5c:	6039      	str	r1, [r7, #0]
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ 80034e0:	b580      	push	{r7, lr}
+ 80034e2:	b086      	sub	sp, #24
+ 80034e4:	af00      	add	r7, sp, #0
+ 80034e6:	60f8      	str	r0, [r7, #12]
+ 80034e8:	60b9      	str	r1, [r7, #8]
+ 80034ea:	607a      	str	r2, [r7, #4]
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- 8002d5e:	2300      	movs	r3, #0
- 8002d60:	73fb      	strb	r3, [r7, #15]
-  __IO uint32_t wait_loop_index = 0U;
- 8002d62:	2300      	movs	r3, #0
- 8002d64:	60bb      	str	r3, [r7, #8]
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
- 8002d66:	687b      	ldr	r3, [r7, #4]
- 8002d68:	f893 3024 	ldrb.w	r3, [r3, #36]	@ 0x24
- 8002d6c:	2b01      	cmp	r3, #1
- 8002d6e:	d101      	bne.n	8002d74 <HAL_ADC_ConfigChannel+0x20>
- 8002d70:	2302      	movs	r3, #2
- 8002d72:	e0dc      	b.n	8002f2e <HAL_ADC_ConfigChannel+0x1da>
- 8002d74:	687b      	ldr	r3, [r7, #4]
- 8002d76:	2201      	movs	r2, #1
- 8002d78:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
-  
-  
-  /* Regular sequence configuration */
-  /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7U)
- 8002d7c:	683b      	ldr	r3, [r7, #0]
- 8002d7e:	685b      	ldr	r3, [r3, #4]
- 8002d80:	2b06      	cmp	r3, #6
- 8002d82:	d81c      	bhi.n	8002dbe <HAL_ADC_ConfigChannel+0x6a>
+ 80034ec:	2300      	movs	r3, #0
+ 80034ee:	75fb      	strb	r3, [r7, #23]
+  assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
+    
+  /* Verification if multimode is disabled (for devices with several ADC)     */
+  /* If multimode is enabled, dedicated function multimode conversion         */
+  /* start DMA must be used.                                                  */
+  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
+ 80034f0:	68fb      	ldr	r3, [r7, #12]
+ 80034f2:	681b      	ldr	r3, [r3, #0]
+ 80034f4:	4a64      	ldr	r2, [pc, #400]	@ (8003688 <HAL_ADC_Start_DMA+0x1a8>)
+ 80034f6:	4293      	cmp	r3, r2
+ 80034f8:	d004      	beq.n	8003504 <HAL_ADC_Start_DMA+0x24>
+ 80034fa:	68fb      	ldr	r3, [r7, #12]
+ 80034fc:	681b      	ldr	r3, [r3, #0]
+ 80034fe:	4a63      	ldr	r2, [pc, #396]	@ (800368c <HAL_ADC_Start_DMA+0x1ac>)
+ 8003500:	4293      	cmp	r3, r2
+ 8003502:	d106      	bne.n	8003512 <HAL_ADC_Start_DMA+0x32>
+ 8003504:	4b60      	ldr	r3, [pc, #384]	@ (8003688 <HAL_ADC_Start_DMA+0x1a8>)
+ 8003506:	685b      	ldr	r3, [r3, #4]
+ 8003508:	f403 2370 	and.w	r3, r3, #983040	@ 0xf0000
+ 800350c:	2b00      	cmp	r3, #0
+ 800350e:	f040 80b3 	bne.w	8003678 <HAL_ADC_Start_DMA+0x198>
   {
-    MODIFY_REG(hadc->Instance->SQR3                        ,
- 8002d84:	687b      	ldr	r3, [r7, #4]
- 8002d86:	681b      	ldr	r3, [r3, #0]
- 8002d88:	6b59      	ldr	r1, [r3, #52]	@ 0x34
- 8002d8a:	683b      	ldr	r3, [r7, #0]
- 8002d8c:	685a      	ldr	r2, [r3, #4]
- 8002d8e:	4613      	mov	r3, r2
- 8002d90:	009b      	lsls	r3, r3, #2
- 8002d92:	4413      	add	r3, r2
- 8002d94:	3b05      	subs	r3, #5
- 8002d96:	221f      	movs	r2, #31
- 8002d98:	fa02 f303 	lsl.w	r3, r2, r3
- 8002d9c:	43db      	mvns	r3, r3
- 8002d9e:	4019      	ands	r1, r3
- 8002da0:	683b      	ldr	r3, [r7, #0]
- 8002da2:	6818      	ldr	r0, [r3, #0]
- 8002da4:	683b      	ldr	r3, [r7, #0]
- 8002da6:	685a      	ldr	r2, [r3, #4]
- 8002da8:	4613      	mov	r3, r2
- 8002daa:	009b      	lsls	r3, r3, #2
- 8002dac:	4413      	add	r3, r2
- 8002dae:	3b05      	subs	r3, #5
- 8002db0:	fa00 f203 	lsl.w	r2, r0, r3
- 8002db4:	687b      	ldr	r3, [r7, #4]
- 8002db6:	681b      	ldr	r3, [r3, #0]
- 8002db8:	430a      	orrs	r2, r1
- 8002dba:	635a      	str	r2, [r3, #52]	@ 0x34
- 8002dbc:	e03c      	b.n	8002e38 <HAL_ADC_ConfigChannel+0xe4>
-               ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
-               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13U)
- 8002dbe:	683b      	ldr	r3, [r7, #0]
- 8002dc0:	685b      	ldr	r3, [r3, #4]
- 8002dc2:	2b0c      	cmp	r3, #12
- 8002dc4:	d81c      	bhi.n	8002e00 <HAL_ADC_ConfigChannel+0xac>
-  {
-    MODIFY_REG(hadc->Instance->SQR2                        ,
- 8002dc6:	687b      	ldr	r3, [r7, #4]
- 8002dc8:	681b      	ldr	r3, [r3, #0]
- 8002dca:	6b19      	ldr	r1, [r3, #48]	@ 0x30
- 8002dcc:	683b      	ldr	r3, [r7, #0]
- 8002dce:	685a      	ldr	r2, [r3, #4]
- 8002dd0:	4613      	mov	r3, r2
- 8002dd2:	009b      	lsls	r3, r3, #2
- 8002dd4:	4413      	add	r3, r2
- 8002dd6:	3b23      	subs	r3, #35	@ 0x23
- 8002dd8:	221f      	movs	r2, #31
- 8002dda:	fa02 f303 	lsl.w	r3, r2, r3
- 8002dde:	43db      	mvns	r3, r3
- 8002de0:	4019      	ands	r1, r3
- 8002de2:	683b      	ldr	r3, [r7, #0]
- 8002de4:	6818      	ldr	r0, [r3, #0]
- 8002de6:	683b      	ldr	r3, [r7, #0]
- 8002de8:	685a      	ldr	r2, [r3, #4]
- 8002dea:	4613      	mov	r3, r2
- 8002dec:	009b      	lsls	r3, r3, #2
- 8002dee:	4413      	add	r3, r2
- 8002df0:	3b23      	subs	r3, #35	@ 0x23
- 8002df2:	fa00 f203 	lsl.w	r2, r0, r3
- 8002df6:	687b      	ldr	r3, [r7, #4]
- 8002df8:	681b      	ldr	r3, [r3, #0]
- 8002dfa:	430a      	orrs	r2, r1
- 8002dfc:	631a      	str	r2, [r3, #48]	@ 0x30
- 8002dfe:	e01b      	b.n	8002e38 <HAL_ADC_ConfigChannel+0xe4>
-               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 13 to 16 */
-  else
-  {
-    MODIFY_REG(hadc->Instance->SQR1                        ,
- 8002e00:	687b      	ldr	r3, [r7, #4]
- 8002e02:	681b      	ldr	r3, [r3, #0]
- 8002e04:	6ad9      	ldr	r1, [r3, #44]	@ 0x2c
- 8002e06:	683b      	ldr	r3, [r7, #0]
- 8002e08:	685a      	ldr	r2, [r3, #4]
- 8002e0a:	4613      	mov	r3, r2
- 8002e0c:	009b      	lsls	r3, r3, #2
- 8002e0e:	4413      	add	r3, r2
- 8002e10:	3b41      	subs	r3, #65	@ 0x41
- 8002e12:	221f      	movs	r2, #31
- 8002e14:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e18:	43db      	mvns	r3, r3
- 8002e1a:	4019      	ands	r1, r3
- 8002e1c:	683b      	ldr	r3, [r7, #0]
- 8002e1e:	6818      	ldr	r0, [r3, #0]
- 8002e20:	683b      	ldr	r3, [r7, #0]
- 8002e22:	685a      	ldr	r2, [r3, #4]
- 8002e24:	4613      	mov	r3, r2
- 8002e26:	009b      	lsls	r3, r3, #2
- 8002e28:	4413      	add	r3, r2
- 8002e2a:	3b41      	subs	r3, #65	@ 0x41
- 8002e2c:	fa00 f203 	lsl.w	r2, r0, r3
- 8002e30:	687b      	ldr	r3, [r7, #4]
- 8002e32:	681b      	ldr	r3, [r3, #0]
- 8002e34:	430a      	orrs	r2, r1
- 8002e36:	62da      	str	r2, [r3, #44]	@ 0x2c
-  }
-  
-  
-  /* Channel sampling time configuration */
-  /* For channels 10 to 17 */
-  if (sConfig->Channel >= ADC_CHANNEL_10)
- 8002e38:	683b      	ldr	r3, [r7, #0]
- 8002e3a:	681b      	ldr	r3, [r3, #0]
- 8002e3c:	2b09      	cmp	r3, #9
- 8002e3e:	d91c      	bls.n	8002e7a <HAL_ADC_ConfigChannel+0x126>
-  {
-    MODIFY_REG(hadc->Instance->SMPR1                             ,
- 8002e40:	687b      	ldr	r3, [r7, #4]
- 8002e42:	681b      	ldr	r3, [r3, #0]
- 8002e44:	68d9      	ldr	r1, [r3, #12]
- 8002e46:	683b      	ldr	r3, [r7, #0]
- 8002e48:	681a      	ldr	r2, [r3, #0]
- 8002e4a:	4613      	mov	r3, r2
- 8002e4c:	005b      	lsls	r3, r3, #1
- 8002e4e:	4413      	add	r3, r2
- 8002e50:	3b1e      	subs	r3, #30
- 8002e52:	2207      	movs	r2, #7
- 8002e54:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e58:	43db      	mvns	r3, r3
- 8002e5a:	4019      	ands	r1, r3
- 8002e5c:	683b      	ldr	r3, [r7, #0]
- 8002e5e:	6898      	ldr	r0, [r3, #8]
- 8002e60:	683b      	ldr	r3, [r7, #0]
- 8002e62:	681a      	ldr	r2, [r3, #0]
- 8002e64:	4613      	mov	r3, r2
- 8002e66:	005b      	lsls	r3, r3, #1
- 8002e68:	4413      	add	r3, r2
- 8002e6a:	3b1e      	subs	r3, #30
- 8002e6c:	fa00 f203 	lsl.w	r2, r0, r3
- 8002e70:	687b      	ldr	r3, [r7, #4]
- 8002e72:	681b      	ldr	r3, [r3, #0]
- 8002e74:	430a      	orrs	r2, r1
- 8002e76:	60da      	str	r2, [r3, #12]
- 8002e78:	e019      	b.n	8002eae <HAL_ADC_ConfigChannel+0x15a>
-               ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
-               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  else /* For channels 0 to 9 */
-  {
-    MODIFY_REG(hadc->Instance->SMPR2                             ,
- 8002e7a:	687b      	ldr	r3, [r7, #4]
- 8002e7c:	681b      	ldr	r3, [r3, #0]
- 8002e7e:	6919      	ldr	r1, [r3, #16]
- 8002e80:	683b      	ldr	r3, [r7, #0]
- 8002e82:	681a      	ldr	r2, [r3, #0]
- 8002e84:	4613      	mov	r3, r2
- 8002e86:	005b      	lsls	r3, r3, #1
- 8002e88:	4413      	add	r3, r2
- 8002e8a:	2207      	movs	r2, #7
- 8002e8c:	fa02 f303 	lsl.w	r3, r2, r3
- 8002e90:	43db      	mvns	r3, r3
- 8002e92:	4019      	ands	r1, r3
- 8002e94:	683b      	ldr	r3, [r7, #0]
- 8002e96:	6898      	ldr	r0, [r3, #8]
- 8002e98:	683b      	ldr	r3, [r7, #0]
- 8002e9a:	681a      	ldr	r2, [r3, #0]
- 8002e9c:	4613      	mov	r3, r2
- 8002e9e:	005b      	lsls	r3, r3, #1
- 8002ea0:	4413      	add	r3, r2
- 8002ea2:	fa00 f203 	lsl.w	r2, r0, r3
- 8002ea6:	687b      	ldr	r3, [r7, #4]
- 8002ea8:	681b      	ldr	r3, [r3, #0]
- 8002eaa:	430a      	orrs	r2, r1
- 8002eac:	611a      	str	r2, [r3, #16]
-               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  
-  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
-  /* and VREFINT measurement path.                                            */
-  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
- 8002eae:	683b      	ldr	r3, [r7, #0]
- 8002eb0:	681b      	ldr	r3, [r3, #0]
- 8002eb2:	2b10      	cmp	r3, #16
- 8002eb4:	d003      	beq.n	8002ebe <HAL_ADC_ConfigChannel+0x16a>
-      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
- 8002eb6:	683b      	ldr	r3, [r7, #0]
- 8002eb8:	681b      	ldr	r3, [r3, #0]
-  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
- 8002eba:	2b11      	cmp	r3, #17
- 8002ebc:	d132      	bne.n	8002f24 <HAL_ADC_ConfigChannel+0x1d0>
-  {
-    /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
-    /* measurement channels (VrefInt/TempSensor). If these channels are       */
-    /* intended to be set on other ADC instances, an error is reported.       */
-    if (hadc->Instance == ADC1)
- 8002ebe:	687b      	ldr	r3, [r7, #4]
- 8002ec0:	681b      	ldr	r3, [r3, #0]
- 8002ec2:	4a1d      	ldr	r2, [pc, #116]	@ (8002f38 <HAL_ADC_ConfigChannel+0x1e4>)
- 8002ec4:	4293      	cmp	r3, r2
- 8002ec6:	d125      	bne.n	8002f14 <HAL_ADC_ConfigChannel+0x1c0>
+    /* Process locked */
+    __HAL_LOCK(hadc);
+ 8003512:	68fb      	ldr	r3, [r7, #12]
+ 8003514:	f893 3024 	ldrb.w	r3, [r3, #36]	@ 0x24
+ 8003518:	2b01      	cmp	r3, #1
+ 800351a:	d101      	bne.n	8003520 <HAL_ADC_Start_DMA+0x40>
+ 800351c:	2302      	movs	r3, #2
+ 800351e:	e0ae      	b.n	800367e <HAL_ADC_Start_DMA+0x19e>
+ 8003520:	68fb      	ldr	r3, [r7, #12]
+ 8003522:	2201      	movs	r2, #1
+ 8003524:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+    
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+ 8003528:	68f8      	ldr	r0, [r7, #12]
+ 800352a:	f000 f9c1 	bl	80038b0 <ADC_Enable>
+ 800352e:	4603      	mov	r3, r0
+ 8003530:	75fb      	strb	r3, [r7, #23]
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+ 8003532:	7dfb      	ldrb	r3, [r7, #23]
+ 8003534:	2b00      	cmp	r3, #0
+ 8003536:	f040 809a 	bne.w	800366e <HAL_ADC_Start_DMA+0x18e>
     {
-      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
- 8002ec8:	687b      	ldr	r3, [r7, #4]
- 8002eca:	681b      	ldr	r3, [r3, #0]
- 8002ecc:	689b      	ldr	r3, [r3, #8]
- 8002ece:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
- 8002ed2:	2b00      	cmp	r3, #0
- 8002ed4:	d126      	bne.n	8002f24 <HAL_ADC_ConfigChannel+0x1d0>
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+ 800353a:	68fb      	ldr	r3, [r7, #12]
+ 800353c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 800353e:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
+ 8003542:	f023 0301 	bic.w	r3, r3, #1
+ 8003546:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
+ 800354a:	68fb      	ldr	r3, [r7, #12]
+ 800354c:	629a      	str	r2, [r3, #40]	@ 0x28
+                        HAL_ADC_STATE_REG_BUSY);
+    
+    /* Set group injected state (from auto-injection) and multimode state     */
+    /* for all cases of multimode: independent mode, multimode ADC master     */
+    /* or multimode ADC slave (for devices with several ADCs):                */
+    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ 800354e:	68fb      	ldr	r3, [r7, #12]
+ 8003550:	681b      	ldr	r3, [r3, #0]
+ 8003552:	4a4e      	ldr	r2, [pc, #312]	@ (800368c <HAL_ADC_Start_DMA+0x1ac>)
+ 8003554:	4293      	cmp	r3, r2
+ 8003556:	d105      	bne.n	8003564 <HAL_ADC_Start_DMA+0x84>
+ 8003558:	4b4b      	ldr	r3, [pc, #300]	@ (8003688 <HAL_ADC_Start_DMA+0x1a8>)
+ 800355a:	685b      	ldr	r3, [r3, #4]
+ 800355c:	f403 2370 	and.w	r3, r3, #983040	@ 0xf0000
+ 8003560:	2b00      	cmp	r3, #0
+ 8003562:	d115      	bne.n	8003590 <HAL_ADC_Start_DMA+0xb0>
+    {
+      /* Set ADC state (ADC independent or master) */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 8003564:	68fb      	ldr	r3, [r7, #12]
+ 8003566:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003568:	f423 1280 	bic.w	r2, r3, #1048576	@ 0x100000
+ 800356c:	68fb      	ldr	r3, [r7, #12]
+ 800356e:	629a      	str	r2, [r3, #40]	@ 0x28
+      
+      /* If conversions on group regular are also triggering group injected,  */
+      /* update ADC state.                                                    */
+      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ 8003570:	68fb      	ldr	r3, [r7, #12]
+ 8003572:	681b      	ldr	r3, [r3, #0]
+ 8003574:	685b      	ldr	r3, [r3, #4]
+ 8003576:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 800357a:	2b00      	cmp	r3, #0
+ 800357c:	d026      	beq.n	80035cc <HAL_ADC_Start_DMA+0xec>
       {
-        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
- 8002ed6:	687b      	ldr	r3, [r7, #4]
- 8002ed8:	681b      	ldr	r3, [r3, #0]
- 8002eda:	689a      	ldr	r2, [r3, #8]
- 8002edc:	687b      	ldr	r3, [r7, #4]
- 8002ede:	681b      	ldr	r3, [r3, #0]
- 8002ee0:	f442 0200 	orr.w	r2, r2, #8388608	@ 0x800000
- 8002ee4:	609a      	str	r2, [r3, #8]
-        
-        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
- 8002ee6:	683b      	ldr	r3, [r7, #0]
- 8002ee8:	681b      	ldr	r3, [r3, #0]
- 8002eea:	2b10      	cmp	r3, #16
- 8002eec:	d11a      	bne.n	8002f24 <HAL_ADC_ConfigChannel+0x1d0>
-        {
-          /* Delay for temperature sensor stabilization time */
-          /* Compute number of CPU cycles to wait for */
-          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- 8002eee:	4b13      	ldr	r3, [pc, #76]	@ (8002f3c <HAL_ADC_ConfigChannel+0x1e8>)
- 8002ef0:	681b      	ldr	r3, [r3, #0]
- 8002ef2:	4a13      	ldr	r2, [pc, #76]	@ (8002f40 <HAL_ADC_ConfigChannel+0x1ec>)
- 8002ef4:	fba2 2303 	umull	r2, r3, r2, r3
- 8002ef8:	0c9a      	lsrs	r2, r3, #18
- 8002efa:	4613      	mov	r3, r2
- 8002efc:	009b      	lsls	r3, r3, #2
- 8002efe:	4413      	add	r3, r2
- 8002f00:	005b      	lsls	r3, r3, #1
- 8002f02:	60bb      	str	r3, [r7, #8]
-          while(wait_loop_index != 0U)
- 8002f04:	e002      	b.n	8002f0c <HAL_ADC_ConfigChannel+0x1b8>
-          {
-            wait_loop_index--;
- 8002f06:	68bb      	ldr	r3, [r7, #8]
- 8002f08:	3b01      	subs	r3, #1
- 8002f0a:	60bb      	str	r3, [r7, #8]
-          while(wait_loop_index != 0U)
- 8002f0c:	68bb      	ldr	r3, [r7, #8]
- 8002f0e:	2b00      	cmp	r3, #0
- 8002f10:	d1f9      	bne.n	8002f06 <HAL_ADC_ConfigChannel+0x1b2>
- 8002f12:	e007      	b.n	8002f24 <HAL_ADC_ConfigChannel+0x1d0>
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+ 800357e:	68fb      	ldr	r3, [r7, #12]
+ 8003580:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003582:	f423 5340 	bic.w	r3, r3, #12288	@ 0x3000
+ 8003586:	f443 5280 	orr.w	r2, r3, #4096	@ 0x1000
+ 800358a:	68fb      	ldr	r3, [r7, #12]
+ 800358c:	629a      	str	r2, [r3, #40]	@ 0x28
+      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ 800358e:	e01d      	b.n	80035cc <HAL_ADC_Start_DMA+0xec>
       }
     }
     else
     {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- 8002f14:	687b      	ldr	r3, [r7, #4]
- 8002f16:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002f18:	f043 0220 	orr.w	r2, r3, #32
- 8002f1c:	687b      	ldr	r3, [r7, #4]
- 8002f1e:	629a      	str	r2, [r3, #40]	@ 0x28
+      /* Set ADC state (ADC slave) */
+      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 8003590:	68fb      	ldr	r3, [r7, #12]
+ 8003592:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003594:	f443 1280 	orr.w	r2, r3, #1048576	@ 0x100000
+ 8003598:	68fb      	ldr	r3, [r7, #12]
+ 800359a:	629a      	str	r2, [r3, #40]	@ 0x28
       
-      tmp_hal_status = HAL_ERROR;
- 8002f20:	2301      	movs	r3, #1
- 8002f22:	73fb      	strb	r3, [r7, #15]
+      /* If conversions on group regular are also triggering group injected,  */
+      /* update ADC state.                                                    */
+      if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ 800359c:	68fb      	ldr	r3, [r7, #12]
+ 800359e:	681b      	ldr	r3, [r3, #0]
+ 80035a0:	4a39      	ldr	r2, [pc, #228]	@ (8003688 <HAL_ADC_Start_DMA+0x1a8>)
+ 80035a2:	4293      	cmp	r3, r2
+ 80035a4:	d004      	beq.n	80035b0 <HAL_ADC_Start_DMA+0xd0>
+ 80035a6:	68fb      	ldr	r3, [r7, #12]
+ 80035a8:	681b      	ldr	r3, [r3, #0]
+ 80035aa:	4a38      	ldr	r2, [pc, #224]	@ (800368c <HAL_ADC_Start_DMA+0x1ac>)
+ 80035ac:	4293      	cmp	r3, r2
+ 80035ae:	d10d      	bne.n	80035cc <HAL_ADC_Start_DMA+0xec>
+ 80035b0:	4b35      	ldr	r3, [pc, #212]	@ (8003688 <HAL_ADC_Start_DMA+0x1a8>)
+ 80035b2:	685b      	ldr	r3, [r3, #4]
+ 80035b4:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 80035b8:	2b00      	cmp	r3, #0
+ 80035ba:	d007      	beq.n	80035cc <HAL_ADC_Start_DMA+0xec>
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ 80035bc:	68fb      	ldr	r3, [r7, #12]
+ 80035be:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80035c0:	f423 5340 	bic.w	r3, r3, #12288	@ 0x3000
+ 80035c4:	f443 5280 	orr.w	r2, r3, #4096	@ 0x1000
+ 80035c8:	68fb      	ldr	r3, [r7, #12]
+ 80035ca:	629a      	str	r2, [r3, #40]	@ 0x28
+      }
+    }
+      
+      /* State machine update: Check if an injected conversion is ongoing */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ 80035cc:	68fb      	ldr	r3, [r7, #12]
+ 80035ce:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80035d0:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
+ 80035d4:	2b00      	cmp	r3, #0
+ 80035d6:	d006      	beq.n	80035e6 <HAL_ADC_Start_DMA+0x106>
+      {
+        /* Reset ADC error code fields related to conversions on group regular */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+ 80035d8:	68fb      	ldr	r3, [r7, #12]
+ 80035da:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80035dc:	f023 0206 	bic.w	r2, r3, #6
+ 80035e0:	68fb      	ldr	r3, [r7, #12]
+ 80035e2:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 80035e4:	e002      	b.n	80035ec <HAL_ADC_Start_DMA+0x10c>
+      }
+      else
+      {
+        /* Reset ADC all error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+ 80035e6:	68fb      	ldr	r3, [r7, #12]
+ 80035e8:	2200      	movs	r2, #0
+ 80035ea:	62da      	str	r2, [r3, #44]	@ 0x2c
+      }
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+ 80035ec:	68fb      	ldr	r3, [r7, #12]
+ 80035ee:	2200      	movs	r2, #0
+ 80035f0:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+      
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+ 80035f4:	68fb      	ldr	r3, [r7, #12]
+ 80035f6:	6a1b      	ldr	r3, [r3, #32]
+ 80035f8:	4a25      	ldr	r2, [pc, #148]	@ (8003690 <HAL_ADC_Start_DMA+0x1b0>)
+ 80035fa:	629a      	str	r2, [r3, #40]	@ 0x28
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+ 80035fc:	68fb      	ldr	r3, [r7, #12]
+ 80035fe:	6a1b      	ldr	r3, [r3, #32]
+ 8003600:	4a24      	ldr	r2, [pc, #144]	@ (8003694 <HAL_ADC_Start_DMA+0x1b4>)
+ 8003602:	62da      	str	r2, [r3, #44]	@ 0x2c
+      
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+ 8003604:	68fb      	ldr	r3, [r7, #12]
+ 8003606:	6a1b      	ldr	r3, [r3, #32]
+ 8003608:	4a23      	ldr	r2, [pc, #140]	@ (8003698 <HAL_ADC_Start_DMA+0x1b8>)
+ 800360a:	631a      	str	r2, [r3, #48]	@ 0x30
+      /* start (in case of SW start):                                         */
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+ 800360c:	68fb      	ldr	r3, [r7, #12]
+ 800360e:	681b      	ldr	r3, [r3, #0]
+ 8003610:	f06f 0202 	mvn.w	r2, #2
+ 8003614:	601a      	str	r2, [r3, #0]
+      
+      /* Enable ADC DMA mode */
+      SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
+ 8003616:	68fb      	ldr	r3, [r7, #12]
+ 8003618:	681b      	ldr	r3, [r3, #0]
+ 800361a:	689a      	ldr	r2, [r3, #8]
+ 800361c:	68fb      	ldr	r3, [r7, #12]
+ 800361e:	681b      	ldr	r3, [r3, #0]
+ 8003620:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 8003624:	609a      	str	r2, [r3, #8]
+      
+      /* Start the DMA channel */
+      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+ 8003626:	68fb      	ldr	r3, [r7, #12]
+ 8003628:	6a18      	ldr	r0, [r3, #32]
+ 800362a:	68fb      	ldr	r3, [r7, #12]
+ 800362c:	681b      	ldr	r3, [r3, #0]
+ 800362e:	334c      	adds	r3, #76	@ 0x4c
+ 8003630:	4619      	mov	r1, r3
+ 8003632:	68ba      	ldr	r2, [r7, #8]
+ 8003634:	687b      	ldr	r3, [r7, #4]
+ 8003636:	f000 fc53 	bl	8003ee0 <HAL_DMA_Start_IT>
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ 800363a:	68fb      	ldr	r3, [r7, #12]
+ 800363c:	681b      	ldr	r3, [r3, #0]
+ 800363e:	689b      	ldr	r3, [r3, #8]
+ 8003640:	f403 2360 	and.w	r3, r3, #917504	@ 0xe0000
+ 8003644:	f5b3 2f60 	cmp.w	r3, #917504	@ 0xe0000
+ 8003648:	d108      	bne.n	800365c <HAL_ADC_Start_DMA+0x17c>
+      {
+        /* Start ADC conversion on regular group with SW start */
+        SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ 800364a:	68fb      	ldr	r3, [r7, #12]
+ 800364c:	681b      	ldr	r3, [r3, #0]
+ 800364e:	689a      	ldr	r2, [r3, #8]
+ 8003650:	68fb      	ldr	r3, [r7, #12]
+ 8003652:	681b      	ldr	r3, [r3, #0]
+ 8003654:	f442 02a0 	orr.w	r2, r2, #5242880	@ 0x500000
+ 8003658:	609a      	str	r2, [r3, #8]
+    if (tmp_hal_status == HAL_OK)
+ 800365a:	e00f      	b.n	800367c <HAL_ADC_Start_DMA+0x19c>
+      }
+      else
+      {
+        /* Start ADC conversion on regular group with external trigger */
+        SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ 800365c:	68fb      	ldr	r3, [r7, #12]
+ 800365e:	681b      	ldr	r3, [r3, #0]
+ 8003660:	689a      	ldr	r2, [r3, #8]
+ 8003662:	68fb      	ldr	r3, [r7, #12]
+ 8003664:	681b      	ldr	r3, [r3, #0]
+ 8003666:	f442 1280 	orr.w	r2, r2, #1048576	@ 0x100000
+ 800366a:	609a      	str	r2, [r3, #8]
+    if (tmp_hal_status == HAL_OK)
+ 800366c:	e006      	b.n	800367c <HAL_ADC_Start_DMA+0x19c>
+      }
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+ 800366e:	68fb      	ldr	r3, [r7, #12]
+ 8003670:	2200      	movs	r2, #0
+ 8003672:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+    if (tmp_hal_status == HAL_OK)
+ 8003676:	e001      	b.n	800367c <HAL_ADC_Start_DMA+0x19c>
     }
   }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
- 8002f24:	687b      	ldr	r3, [r7, #4]
- 8002f26:	2200      	movs	r2, #0
- 8002f28:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+ 8003678:	2301      	movs	r3, #1
+ 800367a:	75fb      	strb	r3, [r7, #23]
+  }
   
   /* Return function status */
   return tmp_hal_status;
- 8002f2c:	7bfb      	ldrb	r3, [r7, #15]
+ 800367c:	7dfb      	ldrb	r3, [r7, #23]
 }
- 8002f2e:	4618      	mov	r0, r3
- 8002f30:	3714      	adds	r7, #20
- 8002f32:	46bd      	mov	sp, r7
- 8002f34:	bc80      	pop	{r7}
- 8002f36:	4770      	bx	lr
- 8002f38:	40012400 	.word	0x40012400
- 8002f3c:	2000001c 	.word	0x2000001c
- 8002f40:	431bde83 	.word	0x431bde83
+ 800367e:	4618      	mov	r0, r3
+ 8003680:	3718      	adds	r7, #24
+ 8003682:	46bd      	mov	sp, r7
+ 8003684:	bd80      	pop	{r7, pc}
+ 8003686:	bf00      	nop
+ 8003688:	40012400 	.word	0x40012400
+ 800368c:	40012800 	.word	0x40012800
+ 8003690:	080039e7 	.word	0x080039e7
+ 8003694:	08003a63 	.word	0x08003a63
+ 8003698:	08003a7f 	.word	0x08003a7f
 
-08002f44 <ADC_ConversionStop_Disable>:
-  *         stopped to disable the ADC.
+0800369c <HAL_ADC_ConvHalfCpltCallback>:
+  * @brief  Conversion DMA half-transfer callback in non blocking mode 
   * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
-{
- 8002f44:	b580      	push	{r7, lr}
- 8002f46:	b084      	sub	sp, #16
- 8002f48:	af00      	add	r7, sp, #0
- 8002f4a:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart = 0U;
- 8002f4c:	2300      	movs	r3, #0
- 8002f4e:	60fb      	str	r3, [r7, #12]
-  
-  /* Verification if ADC is not already disabled */
-  if (ADC_IS_ENABLE(hadc) != RESET)
- 8002f50:	687b      	ldr	r3, [r7, #4]
- 8002f52:	681b      	ldr	r3, [r3, #0]
- 8002f54:	689b      	ldr	r3, [r3, #8]
- 8002f56:	f003 0301 	and.w	r3, r3, #1
- 8002f5a:	2b01      	cmp	r3, #1
- 8002f5c:	d12e      	bne.n	8002fbc <ADC_ConversionStop_Disable+0x78>
-  {
-    /* Disable the ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
- 8002f5e:	687b      	ldr	r3, [r7, #4]
- 8002f60:	681b      	ldr	r3, [r3, #0]
- 8002f62:	689a      	ldr	r2, [r3, #8]
- 8002f64:	687b      	ldr	r3, [r7, #4]
- 8002f66:	681b      	ldr	r3, [r3, #0]
- 8002f68:	f022 0201 	bic.w	r2, r2, #1
- 8002f6c:	609a      	str	r2, [r3, #8]
-     
-    /* Get tick count */
-    tickstart = HAL_GetTick();
- 8002f6e:	f7ff fdeb 	bl	8002b48 <HAL_GetTick>
- 8002f72:	60f8      	str	r0, [r7, #12]
-    
-    /* Wait for ADC effectively disabled */
-    while(ADC_IS_ENABLE(hadc) != RESET)
- 8002f74:	e01b      	b.n	8002fae <ADC_ConversionStop_Disable+0x6a>
-    {
-      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
- 8002f76:	f7ff fde7 	bl	8002b48 <HAL_GetTick>
- 8002f7a:	4602      	mov	r2, r0
- 8002f7c:	68fb      	ldr	r3, [r7, #12]
- 8002f7e:	1ad3      	subs	r3, r2, r3
- 8002f80:	2b02      	cmp	r3, #2
- 8002f82:	d914      	bls.n	8002fae <ADC_ConversionStop_Disable+0x6a>
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(ADC_IS_ENABLE(hadc) != RESET)
- 8002f84:	687b      	ldr	r3, [r7, #4]
- 8002f86:	681b      	ldr	r3, [r3, #0]
- 8002f88:	689b      	ldr	r3, [r3, #8]
- 8002f8a:	f003 0301 	and.w	r3, r3, #1
- 8002f8e:	2b01      	cmp	r3, #1
- 8002f90:	d10d      	bne.n	8002fae <ADC_ConversionStop_Disable+0x6a>
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- 8002f92:	687b      	ldr	r3, [r7, #4]
- 8002f94:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8002f96:	f043 0210 	orr.w	r2, r3, #16
- 8002f9a:	687b      	ldr	r3, [r7, #4]
- 8002f9c:	629a      	str	r2, [r3, #40]	@ 0x28
-
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- 8002f9e:	687b      	ldr	r3, [r7, #4]
- 8002fa0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8002fa2:	f043 0201 	orr.w	r2, r3, #1
- 8002fa6:	687b      	ldr	r3, [r7, #4]
- 8002fa8:	62da      	str	r2, [r3, #44]	@ 0x2c
-
-          return HAL_ERROR;
- 8002faa:	2301      	movs	r3, #1
- 8002fac:	e007      	b.n	8002fbe <ADC_ConversionStop_Disable+0x7a>
-    while(ADC_IS_ENABLE(hadc) != RESET)
- 8002fae:	687b      	ldr	r3, [r7, #4]
- 8002fb0:	681b      	ldr	r3, [r3, #0]
- 8002fb2:	689b      	ldr	r3, [r3, #8]
- 8002fb4:	f003 0301 	and.w	r3, r3, #1
- 8002fb8:	2b01      	cmp	r3, #1
- 8002fba:	d0dc      	beq.n	8002f76 <ADC_ConversionStop_Disable+0x32>
-      }
-    }
-  }
-  
-  /* Return HAL status */
-  return HAL_OK;
- 8002fbc:	2300      	movs	r3, #0
-}
- 8002fbe:	4618      	mov	r0, r3
- 8002fc0:	3710      	adds	r7, #16
- 8002fc2:	46bd      	mov	sp, r7
- 8002fc4:	bd80      	pop	{r7, pc}
-	...
-
-08002fc8 <__NVIC_SetPriorityGrouping>:
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8002fc8:	b480      	push	{r7}
- 8002fca:	b085      	sub	sp, #20
- 8002fcc:	af00      	add	r7, sp, #0
- 8002fce:	6078      	str	r0, [r7, #4]
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
- 8002fd0:	687b      	ldr	r3, [r7, #4]
- 8002fd2:	f003 0307 	and.w	r3, r3, #7
- 8002fd6:	60fb      	str	r3, [r7, #12]
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
- 8002fd8:	4b0c      	ldr	r3, [pc, #48]	@ (800300c <__NVIC_SetPriorityGrouping+0x44>)
- 8002fda:	68db      	ldr	r3, [r3, #12]
- 8002fdc:	60bb      	str	r3, [r7, #8]
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
- 8002fde:	68ba      	ldr	r2, [r7, #8]
- 8002fe0:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
- 8002fe4:	4013      	ands	r3, r2
- 8002fe6:	60bb      	str	r3, [r7, #8]
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
- 8002fe8:	68fb      	ldr	r3, [r7, #12]
- 8002fea:	021a      	lsls	r2, r3, #8
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8002fec:	68bb      	ldr	r3, [r7, #8]
- 8002fee:	4313      	orrs	r3, r2
-  reg_value  =  (reg_value                                   |
- 8002ff0:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
- 8002ff4:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
- 8002ff8:	60bb      	str	r3, [r7, #8]
-  SCB->AIRCR =  reg_value;
- 8002ffa:	4a04      	ldr	r2, [pc, #16]	@ (800300c <__NVIC_SetPriorityGrouping+0x44>)
- 8002ffc:	68bb      	ldr	r3, [r7, #8]
- 8002ffe:	60d3      	str	r3, [r2, #12]
-}
- 8003000:	bf00      	nop
- 8003002:	3714      	adds	r7, #20
- 8003004:	46bd      	mov	sp, r7
- 8003006:	bc80      	pop	{r7}
- 8003008:	4770      	bx	lr
- 800300a:	bf00      	nop
- 800300c:	e000ed00 	.word	0xe000ed00
-
-08003010 <__NVIC_GetPriorityGrouping>:
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8003010:	b480      	push	{r7}
- 8003012:	af00      	add	r7, sp, #0
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8003014:	4b04      	ldr	r3, [pc, #16]	@ (8003028 <__NVIC_GetPriorityGrouping+0x18>)
- 8003016:	68db      	ldr	r3, [r3, #12]
- 8003018:	0a1b      	lsrs	r3, r3, #8
- 800301a:	f003 0307 	and.w	r3, r3, #7
-}
- 800301e:	4618      	mov	r0, r3
- 8003020:	46bd      	mov	sp, r7
- 8003022:	bc80      	pop	{r7}
- 8003024:	4770      	bx	lr
- 8003026:	bf00      	nop
- 8003028:	e000ed00 	.word	0xe000ed00
-
-0800302c <__NVIC_EnableIRQ>:
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 800302c:	b480      	push	{r7}
- 800302e:	b083      	sub	sp, #12
- 8003030:	af00      	add	r7, sp, #0
- 8003032:	4603      	mov	r3, r0
- 8003034:	71fb      	strb	r3, [r7, #7]
-  if ((int32_t)(IRQn) >= 0)
- 8003036:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 800303a:	2b00      	cmp	r3, #0
- 800303c:	db0b      	blt.n	8003056 <__NVIC_EnableIRQ+0x2a>
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 800303e:	79fb      	ldrb	r3, [r7, #7]
- 8003040:	f003 021f 	and.w	r2, r3, #31
- 8003044:	4906      	ldr	r1, [pc, #24]	@ (8003060 <__NVIC_EnableIRQ+0x34>)
- 8003046:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 800304a:	095b      	lsrs	r3, r3, #5
- 800304c:	2001      	movs	r0, #1
- 800304e:	fa00 f202 	lsl.w	r2, r0, r2
- 8003052:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
-  }
-}
- 8003056:	bf00      	nop
- 8003058:	370c      	adds	r7, #12
- 800305a:	46bd      	mov	sp, r7
- 800305c:	bc80      	pop	{r7}
- 800305e:	4770      	bx	lr
- 8003060:	e000e100 	.word	0xe000e100
-
-08003064 <__NVIC_SetPriority>:
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8003064:	b480      	push	{r7}
- 8003066:	b083      	sub	sp, #12
- 8003068:	af00      	add	r7, sp, #0
- 800306a:	4603      	mov	r3, r0
- 800306c:	6039      	str	r1, [r7, #0]
- 800306e:	71fb      	strb	r3, [r7, #7]
-  if ((int32_t)(IRQn) >= 0)
- 8003070:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8003074:	2b00      	cmp	r3, #0
- 8003076:	db0a      	blt.n	800308e <__NVIC_SetPriority+0x2a>
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8003078:	683b      	ldr	r3, [r7, #0]
- 800307a:	b2da      	uxtb	r2, r3
- 800307c:	490c      	ldr	r1, [pc, #48]	@ (80030b0 <__NVIC_SetPriority+0x4c>)
- 800307e:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8003082:	0112      	lsls	r2, r2, #4
- 8003084:	b2d2      	uxtb	r2, r2
- 8003086:	440b      	add	r3, r1
- 8003088:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
- 800308c:	e00a      	b.n	80030a4 <__NVIC_SetPriority+0x40>
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 800308e:	683b      	ldr	r3, [r7, #0]
- 8003090:	b2da      	uxtb	r2, r3
- 8003092:	4908      	ldr	r1, [pc, #32]	@ (80030b4 <__NVIC_SetPriority+0x50>)
- 8003094:	79fb      	ldrb	r3, [r7, #7]
- 8003096:	f003 030f 	and.w	r3, r3, #15
- 800309a:	3b04      	subs	r3, #4
- 800309c:	0112      	lsls	r2, r2, #4
- 800309e:	b2d2      	uxtb	r2, r2
- 80030a0:	440b      	add	r3, r1
- 80030a2:	761a      	strb	r2, [r3, #24]
-}
- 80030a4:	bf00      	nop
- 80030a6:	370c      	adds	r7, #12
- 80030a8:	46bd      	mov	sp, r7
- 80030aa:	bc80      	pop	{r7}
- 80030ac:	4770      	bx	lr
- 80030ae:	bf00      	nop
- 80030b0:	e000e100 	.word	0xe000e100
- 80030b4:	e000ed00 	.word	0xe000ed00
-
-080030b8 <NVIC_EncodePriority>:
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 80030b8:	b480      	push	{r7}
- 80030ba:	b089      	sub	sp, #36	@ 0x24
- 80030bc:	af00      	add	r7, sp, #0
- 80030be:	60f8      	str	r0, [r7, #12]
- 80030c0:	60b9      	str	r1, [r7, #8]
- 80030c2:	607a      	str	r2, [r7, #4]
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
- 80030c4:	68fb      	ldr	r3, [r7, #12]
- 80030c6:	f003 0307 	and.w	r3, r3, #7
- 80030ca:	61fb      	str	r3, [r7, #28]
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 80030cc:	69fb      	ldr	r3, [r7, #28]
- 80030ce:	f1c3 0307 	rsb	r3, r3, #7
- 80030d2:	2b04      	cmp	r3, #4
- 80030d4:	bf28      	it	cs
- 80030d6:	2304      	movcs	r3, #4
- 80030d8:	61bb      	str	r3, [r7, #24]
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 80030da:	69fb      	ldr	r3, [r7, #28]
- 80030dc:	3304      	adds	r3, #4
- 80030de:	2b06      	cmp	r3, #6
- 80030e0:	d902      	bls.n	80030e8 <NVIC_EncodePriority+0x30>
- 80030e2:	69fb      	ldr	r3, [r7, #28]
- 80030e4:	3b03      	subs	r3, #3
- 80030e6:	e000      	b.n	80030ea <NVIC_EncodePriority+0x32>
- 80030e8:	2300      	movs	r3, #0
- 80030ea:	617b      	str	r3, [r7, #20]
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 80030ec:	f04f 32ff 	mov.w	r2, #4294967295
- 80030f0:	69bb      	ldr	r3, [r7, #24]
- 80030f2:	fa02 f303 	lsl.w	r3, r2, r3
- 80030f6:	43da      	mvns	r2, r3
- 80030f8:	68bb      	ldr	r3, [r7, #8]
- 80030fa:	401a      	ands	r2, r3
- 80030fc:	697b      	ldr	r3, [r7, #20]
- 80030fe:	409a      	lsls	r2, r3
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
- 8003100:	f04f 31ff 	mov.w	r1, #4294967295
- 8003104:	697b      	ldr	r3, [r7, #20]
- 8003106:	fa01 f303 	lsl.w	r3, r1, r3
- 800310a:	43d9      	mvns	r1, r3
- 800310c:	687b      	ldr	r3, [r7, #4]
- 800310e:	400b      	ands	r3, r1
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8003110:	4313      	orrs	r3, r2
-         );
-}
- 8003112:	4618      	mov	r0, r3
- 8003114:	3724      	adds	r7, #36	@ 0x24
- 8003116:	46bd      	mov	sp, r7
- 8003118:	bc80      	pop	{r7}
- 800311a:	4770      	bx	lr
-
-0800311c <SysTick_Config>:
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 800311c:	b580      	push	{r7, lr}
- 800311e:	b082      	sub	sp, #8
- 8003120:	af00      	add	r7, sp, #0
- 8003122:	6078      	str	r0, [r7, #4]
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8003124:	687b      	ldr	r3, [r7, #4]
- 8003126:	3b01      	subs	r3, #1
- 8003128:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
- 800312c:	d301      	bcc.n	8003132 <SysTick_Config+0x16>
-  {
-    return (1UL);                                                   /* Reload value impossible */
- 800312e:	2301      	movs	r3, #1
- 8003130:	e00f      	b.n	8003152 <SysTick_Config+0x36>
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 8003132:	4a0a      	ldr	r2, [pc, #40]	@ (800315c <SysTick_Config+0x40>)
- 8003134:	687b      	ldr	r3, [r7, #4]
- 8003136:	3b01      	subs	r3, #1
- 8003138:	6053      	str	r3, [r2, #4]
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 800313a:	210f      	movs	r1, #15
- 800313c:	f04f 30ff 	mov.w	r0, #4294967295
- 8003140:	f7ff ff90 	bl	8003064 <__NVIC_SetPriority>
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 8003144:	4b05      	ldr	r3, [pc, #20]	@ (800315c <SysTick_Config+0x40>)
- 8003146:	2200      	movs	r2, #0
- 8003148:	609a      	str	r2, [r3, #8]
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 800314a:	4b04      	ldr	r3, [pc, #16]	@ (800315c <SysTick_Config+0x40>)
- 800314c:	2207      	movs	r2, #7
- 800314e:	601a      	str	r2, [r3, #0]
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
- 8003150:	2300      	movs	r3, #0
-}
- 8003152:	4618      	mov	r0, r3
- 8003154:	3708      	adds	r7, #8
- 8003156:	46bd      	mov	sp, r7
- 8003158:	bd80      	pop	{r7, pc}
- 800315a:	bf00      	nop
- 800315c:	e000e010 	.word	0xe000e010
-
-08003160 <HAL_NVIC_SetPriorityGrouping>:
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
   * @retval None
   */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 {
- 8003160:	b580      	push	{r7, lr}
- 8003162:	b082      	sub	sp, #8
- 8003164:	af00      	add	r7, sp, #0
- 8003166:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
- 8003168:	6878      	ldr	r0, [r7, #4]
- 800316a:	f7ff ff2d 	bl	8002fc8 <__NVIC_SetPriorityGrouping>
-}
- 800316e:	bf00      	nop
- 8003170:	3708      	adds	r7, #8
- 8003172:	46bd      	mov	sp, r7
- 8003174:	bd80      	pop	{r7, pc}
-
-08003176 <HAL_NVIC_SetPriority>:
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
+ 800369c:	b480      	push	{r7}
+ 800369e:	b083      	sub	sp, #12
+ 80036a0:	af00      	add	r7, sp, #0
+ 80036a2:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
   */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{ 
- 8003176:	b580      	push	{r7, lr}
- 8003178:	b086      	sub	sp, #24
- 800317a:	af00      	add	r7, sp, #0
- 800317c:	4603      	mov	r3, r0
- 800317e:	60b9      	str	r1, [r7, #8]
- 8003180:	607a      	str	r2, [r7, #4]
- 8003182:	73fb      	strb	r3, [r7, #15]
-  uint32_t prioritygroup = 0x00U;
- 8003184:	2300      	movs	r3, #0
- 8003186:	617b      	str	r3, [r7, #20]
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
- 8003188:	f7ff ff42 	bl	8003010 <__NVIC_GetPriorityGrouping>
- 800318c:	6178      	str	r0, [r7, #20]
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 800318e:	687a      	ldr	r2, [r7, #4]
- 8003190:	68b9      	ldr	r1, [r7, #8]
- 8003192:	6978      	ldr	r0, [r7, #20]
- 8003194:	f7ff ff90 	bl	80030b8 <NVIC_EncodePriority>
- 8003198:	4602      	mov	r2, r0
- 800319a:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 800319e:	4611      	mov	r1, r2
- 80031a0:	4618      	mov	r0, r3
- 80031a2:	f7ff ff5f 	bl	8003064 <__NVIC_SetPriority>
-}
- 80031a6:	bf00      	nop
- 80031a8:	3718      	adds	r7, #24
- 80031aa:	46bd      	mov	sp, r7
- 80031ac:	bd80      	pop	{r7, pc}
-
-080031ae <HAL_NVIC_EnableIRQ>:
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 80031ae:	b580      	push	{r7, lr}
- 80031b0:	b082      	sub	sp, #8
- 80031b2:	af00      	add	r7, sp, #0
- 80031b4:	4603      	mov	r3, r0
- 80031b6:	71fb      	strb	r3, [r7, #7]
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
- 80031b8:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80031bc:	4618      	mov	r0, r3
- 80031be:	f7ff ff35 	bl	800302c <__NVIC_EnableIRQ>
-}
- 80031c2:	bf00      	nop
- 80031c4:	3708      	adds	r7, #8
- 80031c6:	46bd      	mov	sp, r7
- 80031c8:	bd80      	pop	{r7, pc}
-
-080031ca <HAL_SYSTICK_Config>:
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 80031ca:	b580      	push	{r7, lr}
- 80031cc:	b082      	sub	sp, #8
- 80031ce:	af00      	add	r7, sp, #0
- 80031d0:	6078      	str	r0, [r7, #4]
-   return SysTick_Config(TicksNumb);
- 80031d2:	6878      	ldr	r0, [r7, #4]
- 80031d4:	f7ff ffa2 	bl	800311c <SysTick_Config>
- 80031d8:	4603      	mov	r3, r0
-}
- 80031da:	4618      	mov	r0, r3
- 80031dc:	3708      	adds	r7, #8
- 80031de:	46bd      	mov	sp, r7
- 80031e0:	bd80      	pop	{r7, pc}
-
-080031e2 <HAL_DMA_Abort>:
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- 80031e2:	b480      	push	{r7}
- 80031e4:	b085      	sub	sp, #20
- 80031e6:	af00      	add	r7, sp, #0
- 80031e8:	6078      	str	r0, [r7, #4]
-  HAL_StatusTypeDef status = HAL_OK;
- 80031ea:	2300      	movs	r3, #0
- 80031ec:	73fb      	strb	r3, [r7, #15]
-  
-  if(hdma->State != HAL_DMA_STATE_BUSY)
- 80031ee:	687b      	ldr	r3, [r7, #4]
- 80031f0:	f893 3021 	ldrb.w	r3, [r3, #33]	@ 0x21
- 80031f4:	b2db      	uxtb	r3, r3
- 80031f6:	2b02      	cmp	r3, #2
- 80031f8:	d008      	beq.n	800320c <HAL_DMA_Abort+0x2a>
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 80031fa:	687b      	ldr	r3, [r7, #4]
- 80031fc:	2204      	movs	r2, #4
- 80031fe:	639a      	str	r2, [r3, #56]	@ 0x38
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
- 8003200:	687b      	ldr	r3, [r7, #4]
- 8003202:	2200      	movs	r2, #0
- 8003204:	f883 2020 	strb.w	r2, [r3, #32]
-    
-    return HAL_ERROR;
- 8003208:	2301      	movs	r3, #1
- 800320a:	e020      	b.n	800324e <HAL_DMA_Abort+0x6c>
-  }
-  else
-
-  {
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- 800320c:	687b      	ldr	r3, [r7, #4]
- 800320e:	681b      	ldr	r3, [r3, #0]
- 8003210:	681a      	ldr	r2, [r3, #0]
- 8003212:	687b      	ldr	r3, [r7, #4]
- 8003214:	681b      	ldr	r3, [r3, #0]
- 8003216:	f022 020e 	bic.w	r2, r2, #14
- 800321a:	601a      	str	r2, [r3, #0]
-      
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
- 800321c:	687b      	ldr	r3, [r7, #4]
- 800321e:	681b      	ldr	r3, [r3, #0]
- 8003220:	681a      	ldr	r2, [r3, #0]
- 8003222:	687b      	ldr	r3, [r7, #4]
- 8003224:	681b      	ldr	r3, [r3, #0]
- 8003226:	f022 0201 	bic.w	r2, r2, #1
- 800322a:	601a      	str	r2, [r3, #0]
-      
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
- 800322c:	687b      	ldr	r3, [r7, #4]
- 800322e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003230:	687b      	ldr	r3, [r7, #4]
- 8003232:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 8003234:	2101      	movs	r1, #1
- 8003236:	fa01 f202 	lsl.w	r2, r1, r2
- 800323a:	605a      	str	r2, [r3, #4]
-  }
-  /* Change the DMA state */
-  hdma->State = HAL_DMA_STATE_READY;
- 800323c:	687b      	ldr	r3, [r7, #4]
- 800323e:	2201      	movs	r2, #1
- 8003240:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma);      
- 8003244:	687b      	ldr	r3, [r7, #4]
- 8003246:	2200      	movs	r2, #0
- 8003248:	f883 2020 	strb.w	r2, [r3, #32]
-  
-  return status; 
- 800324c:	7bfb      	ldrb	r3, [r7, #15]
-}
- 800324e:	4618      	mov	r0, r3
- 8003250:	3714      	adds	r7, #20
- 8003252:	46bd      	mov	sp, r7
- 8003254:	bc80      	pop	{r7}
- 8003256:	4770      	bx	lr
-
-08003258 <HAL_DMA_Abort_IT>:
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{  
- 8003258:	b580      	push	{r7, lr}
- 800325a:	b084      	sub	sp, #16
- 800325c:	af00      	add	r7, sp, #0
- 800325e:	6078      	str	r0, [r7, #4]
-  HAL_StatusTypeDef status = HAL_OK;
- 8003260:	2300      	movs	r3, #0
- 8003262:	73fb      	strb	r3, [r7, #15]
-  
-  if(HAL_DMA_STATE_BUSY != hdma->State)
- 8003264:	687b      	ldr	r3, [r7, #4]
- 8003266:	f893 3021 	ldrb.w	r3, [r3, #33]	@ 0x21
- 800326a:	b2db      	uxtb	r3, r3
- 800326c:	2b02      	cmp	r3, #2
- 800326e:	d005      	beq.n	800327c <HAL_DMA_Abort_IT+0x24>
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8003270:	687b      	ldr	r3, [r7, #4]
- 8003272:	2204      	movs	r2, #4
- 8003274:	639a      	str	r2, [r3, #56]	@ 0x38
-        
-    status = HAL_ERROR;
- 8003276:	2301      	movs	r3, #1
- 8003278:	73fb      	strb	r3, [r7, #15]
- 800327a:	e051      	b.n	8003320 <HAL_DMA_Abort_IT+0xc8>
-  }
-  else
-  { 
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- 800327c:	687b      	ldr	r3, [r7, #4]
- 800327e:	681b      	ldr	r3, [r3, #0]
- 8003280:	681a      	ldr	r2, [r3, #0]
- 8003282:	687b      	ldr	r3, [r7, #4]
- 8003284:	681b      	ldr	r3, [r3, #0]
- 8003286:	f022 020e 	bic.w	r2, r2, #14
- 800328a:	601a      	str	r2, [r3, #0]
-
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
- 800328c:	687b      	ldr	r3, [r7, #4]
- 800328e:	681b      	ldr	r3, [r3, #0]
- 8003290:	681a      	ldr	r2, [r3, #0]
- 8003292:	687b      	ldr	r3, [r7, #4]
- 8003294:	681b      	ldr	r3, [r3, #0]
- 8003296:	f022 0201 	bic.w	r2, r2, #1
- 800329a:	601a      	str	r2, [r3, #0]
-
-    /* Clear all flags */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
- 800329c:	687b      	ldr	r3, [r7, #4]
- 800329e:	681b      	ldr	r3, [r3, #0]
- 80032a0:	4a22      	ldr	r2, [pc, #136]	@ (800332c <HAL_DMA_Abort_IT+0xd4>)
- 80032a2:	4293      	cmp	r3, r2
- 80032a4:	d029      	beq.n	80032fa <HAL_DMA_Abort_IT+0xa2>
- 80032a6:	687b      	ldr	r3, [r7, #4]
- 80032a8:	681b      	ldr	r3, [r3, #0]
- 80032aa:	4a21      	ldr	r2, [pc, #132]	@ (8003330 <HAL_DMA_Abort_IT+0xd8>)
- 80032ac:	4293      	cmp	r3, r2
- 80032ae:	d022      	beq.n	80032f6 <HAL_DMA_Abort_IT+0x9e>
- 80032b0:	687b      	ldr	r3, [r7, #4]
- 80032b2:	681b      	ldr	r3, [r3, #0]
- 80032b4:	4a1f      	ldr	r2, [pc, #124]	@ (8003334 <HAL_DMA_Abort_IT+0xdc>)
- 80032b6:	4293      	cmp	r3, r2
- 80032b8:	d01a      	beq.n	80032f0 <HAL_DMA_Abort_IT+0x98>
- 80032ba:	687b      	ldr	r3, [r7, #4]
- 80032bc:	681b      	ldr	r3, [r3, #0]
- 80032be:	4a1e      	ldr	r2, [pc, #120]	@ (8003338 <HAL_DMA_Abort_IT+0xe0>)
- 80032c0:	4293      	cmp	r3, r2
- 80032c2:	d012      	beq.n	80032ea <HAL_DMA_Abort_IT+0x92>
- 80032c4:	687b      	ldr	r3, [r7, #4]
- 80032c6:	681b      	ldr	r3, [r3, #0]
- 80032c8:	4a1c      	ldr	r2, [pc, #112]	@ (800333c <HAL_DMA_Abort_IT+0xe4>)
- 80032ca:	4293      	cmp	r3, r2
- 80032cc:	d00a      	beq.n	80032e4 <HAL_DMA_Abort_IT+0x8c>
- 80032ce:	687b      	ldr	r3, [r7, #4]
- 80032d0:	681b      	ldr	r3, [r3, #0]
- 80032d2:	4a1b      	ldr	r2, [pc, #108]	@ (8003340 <HAL_DMA_Abort_IT+0xe8>)
- 80032d4:	4293      	cmp	r3, r2
- 80032d6:	d102      	bne.n	80032de <HAL_DMA_Abort_IT+0x86>
- 80032d8:	f44f 1380 	mov.w	r3, #1048576	@ 0x100000
- 80032dc:	e00e      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032de:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
- 80032e2:	e00b      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032e4:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
- 80032e8:	e008      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032ea:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
- 80032ee:	e005      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032f0:	f44f 7380 	mov.w	r3, #256	@ 0x100
- 80032f4:	e002      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032f6:	2310      	movs	r3, #16
- 80032f8:	e000      	b.n	80032fc <HAL_DMA_Abort_IT+0xa4>
- 80032fa:	2301      	movs	r3, #1
- 80032fc:	4a11      	ldr	r2, [pc, #68]	@ (8003344 <HAL_DMA_Abort_IT+0xec>)
- 80032fe:	6053      	str	r3, [r2, #4]
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
- 8003300:	687b      	ldr	r3, [r7, #4]
- 8003302:	2201      	movs	r2, #1
- 8003304:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
- 8003308:	687b      	ldr	r3, [r7, #4]
- 800330a:	2200      	movs	r2, #0
- 800330c:	f883 2020 	strb.w	r2, [r3, #32]
-
-    /* Call User Abort callback */
-    if(hdma->XferAbortCallback != NULL)
- 8003310:	687b      	ldr	r3, [r7, #4]
- 8003312:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8003314:	2b00      	cmp	r3, #0
- 8003316:	d003      	beq.n	8003320 <HAL_DMA_Abort_IT+0xc8>
-    {
-      hdma->XferAbortCallback(hdma);
- 8003318:	687b      	ldr	r3, [r7, #4]
- 800331a:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 800331c:	6878      	ldr	r0, [r7, #4]
- 800331e:	4798      	blx	r3
-    } 
-  }
-  return status;
- 8003320:	7bfb      	ldrb	r3, [r7, #15]
-}
- 8003322:	4618      	mov	r0, r3
- 8003324:	3710      	adds	r7, #16
- 8003326:	46bd      	mov	sp, r7
- 8003328:	bd80      	pop	{r7, pc}
- 800332a:	bf00      	nop
- 800332c:	40020008 	.word	0x40020008
- 8003330:	4002001c 	.word	0x4002001c
- 8003334:	40020030 	.word	0x40020030
- 8003338:	40020044 	.word	0x40020044
- 800333c:	40020058 	.word	0x40020058
- 8003340:	4002006c 	.word	0x4002006c
- 8003344:	40020000 	.word	0x40020000
-
-08003348 <HAL_GPIO_Init>:
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8003348:	b480      	push	{r7}
- 800334a:	b08b      	sub	sp, #44	@ 0x2c
- 800334c:	af00      	add	r7, sp, #0
- 800334e:	6078      	str	r0, [r7, #4]
- 8003350:	6039      	str	r1, [r7, #0]
-  uint32_t position = 0x00u;
- 8003352:	2300      	movs	r3, #0
- 8003354:	627b      	str	r3, [r7, #36]	@ 0x24
-  uint32_t ioposition;
-  uint32_t iocurrent;
-  uint32_t temp;
-  uint32_t config = 0x00u;
- 8003356:	2300      	movs	r3, #0
- 8003358:	623b      	str	r3, [r7, #32]
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
-  /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != 0x00u)
- 800335a:	e169      	b.n	8003630 <HAL_GPIO_Init+0x2e8>
-  {
-    /* Get the IO position */
-    ioposition = (0x01uL << position);
- 800335c:	2201      	movs	r2, #1
- 800335e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003360:	fa02 f303 	lsl.w	r3, r2, r3
- 8003364:	61fb      	str	r3, [r7, #28]
-
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8003366:	683b      	ldr	r3, [r7, #0]
- 8003368:	681b      	ldr	r3, [r3, #0]
- 800336a:	69fa      	ldr	r2, [r7, #28]
- 800336c:	4013      	ands	r3, r2
- 800336e:	61bb      	str	r3, [r7, #24]
-
-    if (iocurrent == ioposition)
- 8003370:	69ba      	ldr	r2, [r7, #24]
- 8003372:	69fb      	ldr	r3, [r7, #28]
- 8003374:	429a      	cmp	r2, r3
- 8003376:	f040 8158 	bne.w	800362a <HAL_GPIO_Init+0x2e2>
-    {
-      /* Check the Alternate function parameters */
-      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-
-      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
-      switch (GPIO_Init->Mode)
- 800337a:	683b      	ldr	r3, [r7, #0]
- 800337c:	685b      	ldr	r3, [r3, #4]
- 800337e:	4a9a      	ldr	r2, [pc, #616]	@ (80035e8 <HAL_GPIO_Init+0x2a0>)
- 8003380:	4293      	cmp	r3, r2
- 8003382:	d05e      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
- 8003384:	4a98      	ldr	r2, [pc, #608]	@ (80035e8 <HAL_GPIO_Init+0x2a0>)
- 8003386:	4293      	cmp	r3, r2
- 8003388:	d875      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 800338a:	4a98      	ldr	r2, [pc, #608]	@ (80035ec <HAL_GPIO_Init+0x2a4>)
- 800338c:	4293      	cmp	r3, r2
- 800338e:	d058      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
- 8003390:	4a96      	ldr	r2, [pc, #600]	@ (80035ec <HAL_GPIO_Init+0x2a4>)
- 8003392:	4293      	cmp	r3, r2
- 8003394:	d86f      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 8003396:	4a96      	ldr	r2, [pc, #600]	@ (80035f0 <HAL_GPIO_Init+0x2a8>)
- 8003398:	4293      	cmp	r3, r2
- 800339a:	d052      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
- 800339c:	4a94      	ldr	r2, [pc, #592]	@ (80035f0 <HAL_GPIO_Init+0x2a8>)
- 800339e:	4293      	cmp	r3, r2
- 80033a0:	d869      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 80033a2:	4a94      	ldr	r2, [pc, #592]	@ (80035f4 <HAL_GPIO_Init+0x2ac>)
- 80033a4:	4293      	cmp	r3, r2
- 80033a6:	d04c      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
- 80033a8:	4a92      	ldr	r2, [pc, #584]	@ (80035f4 <HAL_GPIO_Init+0x2ac>)
- 80033aa:	4293      	cmp	r3, r2
- 80033ac:	d863      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 80033ae:	4a92      	ldr	r2, [pc, #584]	@ (80035f8 <HAL_GPIO_Init+0x2b0>)
- 80033b0:	4293      	cmp	r3, r2
- 80033b2:	d046      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
- 80033b4:	4a90      	ldr	r2, [pc, #576]	@ (80035f8 <HAL_GPIO_Init+0x2b0>)
- 80033b6:	4293      	cmp	r3, r2
- 80033b8:	d85d      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 80033ba:	2b12      	cmp	r3, #18
- 80033bc:	d82a      	bhi.n	8003414 <HAL_GPIO_Init+0xcc>
- 80033be:	2b12      	cmp	r3, #18
- 80033c0:	d859      	bhi.n	8003476 <HAL_GPIO_Init+0x12e>
- 80033c2:	a201      	add	r2, pc, #4	@ (adr r2, 80033c8 <HAL_GPIO_Init+0x80>)
- 80033c4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 80033c8:	08003443 	.word	0x08003443
- 80033cc:	0800341d 	.word	0x0800341d
- 80033d0:	0800342f 	.word	0x0800342f
- 80033d4:	08003471 	.word	0x08003471
- 80033d8:	08003477 	.word	0x08003477
- 80033dc:	08003477 	.word	0x08003477
- 80033e0:	08003477 	.word	0x08003477
- 80033e4:	08003477 	.word	0x08003477
- 80033e8:	08003477 	.word	0x08003477
- 80033ec:	08003477 	.word	0x08003477
- 80033f0:	08003477 	.word	0x08003477
- 80033f4:	08003477 	.word	0x08003477
- 80033f8:	08003477 	.word	0x08003477
- 80033fc:	08003477 	.word	0x08003477
- 8003400:	08003477 	.word	0x08003477
- 8003404:	08003477 	.word	0x08003477
- 8003408:	08003477 	.word	0x08003477
- 800340c:	08003425 	.word	0x08003425
- 8003410:	08003439 	.word	0x08003439
- 8003414:	4a79      	ldr	r2, [pc, #484]	@ (80035fc <HAL_GPIO_Init+0x2b4>)
- 8003416:	4293      	cmp	r3, r2
- 8003418:	d013      	beq.n	8003442 <HAL_GPIO_Init+0xfa>
-          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
-          break;
-
-        /* Parameters are checked with assert_param */
-        default:
-          break;
- 800341a:	e02c      	b.n	8003476 <HAL_GPIO_Init+0x12e>
-          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
- 800341c:	683b      	ldr	r3, [r7, #0]
- 800341e:	68db      	ldr	r3, [r3, #12]
- 8003420:	623b      	str	r3, [r7, #32]
-          break;
- 8003422:	e029      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
- 8003424:	683b      	ldr	r3, [r7, #0]
- 8003426:	68db      	ldr	r3, [r3, #12]
- 8003428:	3304      	adds	r3, #4
- 800342a:	623b      	str	r3, [r7, #32]
-          break;
- 800342c:	e024      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
- 800342e:	683b      	ldr	r3, [r7, #0]
- 8003430:	68db      	ldr	r3, [r3, #12]
- 8003432:	3308      	adds	r3, #8
- 8003434:	623b      	str	r3, [r7, #32]
-          break;
- 8003436:	e01f      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
- 8003438:	683b      	ldr	r3, [r7, #0]
- 800343a:	68db      	ldr	r3, [r3, #12]
- 800343c:	330c      	adds	r3, #12
- 800343e:	623b      	str	r3, [r7, #32]
-          break;
- 8003440:	e01a      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          if (GPIO_Init->Pull == GPIO_NOPULL)
- 8003442:	683b      	ldr	r3, [r7, #0]
- 8003444:	689b      	ldr	r3, [r3, #8]
- 8003446:	2b00      	cmp	r3, #0
- 8003448:	d102      	bne.n	8003450 <HAL_GPIO_Init+0x108>
-            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
- 800344a:	2304      	movs	r3, #4
- 800344c:	623b      	str	r3, [r7, #32]
-          break;
- 800344e:	e013      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          else if (GPIO_Init->Pull == GPIO_PULLUP)
- 8003450:	683b      	ldr	r3, [r7, #0]
- 8003452:	689b      	ldr	r3, [r3, #8]
- 8003454:	2b01      	cmp	r3, #1
- 8003456:	d105      	bne.n	8003464 <HAL_GPIO_Init+0x11c>
-            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
- 8003458:	2308      	movs	r3, #8
- 800345a:	623b      	str	r3, [r7, #32]
-            GPIOx->BSRR = ioposition;
- 800345c:	687b      	ldr	r3, [r7, #4]
- 800345e:	69fa      	ldr	r2, [r7, #28]
- 8003460:	611a      	str	r2, [r3, #16]
-          break;
- 8003462:	e009      	b.n	8003478 <HAL_GPIO_Init+0x130>
-            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
- 8003464:	2308      	movs	r3, #8
- 8003466:	623b      	str	r3, [r7, #32]
-            GPIOx->BRR = ioposition;
- 8003468:	687b      	ldr	r3, [r7, #4]
- 800346a:	69fa      	ldr	r2, [r7, #28]
- 800346c:	615a      	str	r2, [r3, #20]
-          break;
- 800346e:	e003      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
- 8003470:	2300      	movs	r3, #0
- 8003472:	623b      	str	r3, [r7, #32]
-          break;
- 8003474:	e000      	b.n	8003478 <HAL_GPIO_Init+0x130>
-          break;
- 8003476:	bf00      	nop
-      }
-
-      /* Check if the current bit belongs to first half or last half of the pin count number
-       in order to address CRH or CRL register*/
-      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
- 8003478:	69bb      	ldr	r3, [r7, #24]
- 800347a:	2bff      	cmp	r3, #255	@ 0xff
- 800347c:	d801      	bhi.n	8003482 <HAL_GPIO_Init+0x13a>
- 800347e:	687b      	ldr	r3, [r7, #4]
- 8003480:	e001      	b.n	8003486 <HAL_GPIO_Init+0x13e>
- 8003482:	687b      	ldr	r3, [r7, #4]
- 8003484:	3304      	adds	r3, #4
- 8003486:	617b      	str	r3, [r7, #20]
-      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
- 8003488:	69bb      	ldr	r3, [r7, #24]
- 800348a:	2bff      	cmp	r3, #255	@ 0xff
- 800348c:	d802      	bhi.n	8003494 <HAL_GPIO_Init+0x14c>
- 800348e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003490:	009b      	lsls	r3, r3, #2
- 8003492:	e002      	b.n	800349a <HAL_GPIO_Init+0x152>
- 8003494:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003496:	3b08      	subs	r3, #8
- 8003498:	009b      	lsls	r3, r3, #2
- 800349a:	613b      	str	r3, [r7, #16]
-
-      /* Apply the new configuration of the pin to the register */
-      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
- 800349c:	697b      	ldr	r3, [r7, #20]
- 800349e:	681a      	ldr	r2, [r3, #0]
- 80034a0:	210f      	movs	r1, #15
- 80034a2:	693b      	ldr	r3, [r7, #16]
- 80034a4:	fa01 f303 	lsl.w	r3, r1, r3
- 80034a8:	43db      	mvns	r3, r3
- 80034aa:	401a      	ands	r2, r3
- 80034ac:	6a39      	ldr	r1, [r7, #32]
- 80034ae:	693b      	ldr	r3, [r7, #16]
- 80034b0:	fa01 f303 	lsl.w	r3, r1, r3
- 80034b4:	431a      	orrs	r2, r3
- 80034b6:	697b      	ldr	r3, [r7, #20]
- 80034b8:	601a      	str	r2, [r3, #0]
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 80034ba:	683b      	ldr	r3, [r7, #0]
- 80034bc:	685b      	ldr	r3, [r3, #4]
- 80034be:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 80034c2:	2b00      	cmp	r3, #0
- 80034c4:	f000 80b1 	beq.w	800362a <HAL_GPIO_Init+0x2e2>
-      {
-        /* Enable AFIO Clock */
-        __HAL_RCC_AFIO_CLK_ENABLE();
- 80034c8:	4b4d      	ldr	r3, [pc, #308]	@ (8003600 <HAL_GPIO_Init+0x2b8>)
- 80034ca:	699b      	ldr	r3, [r3, #24]
- 80034cc:	4a4c      	ldr	r2, [pc, #304]	@ (8003600 <HAL_GPIO_Init+0x2b8>)
- 80034ce:	f043 0301 	orr.w	r3, r3, #1
- 80034d2:	6193      	str	r3, [r2, #24]
- 80034d4:	4b4a      	ldr	r3, [pc, #296]	@ (8003600 <HAL_GPIO_Init+0x2b8>)
- 80034d6:	699b      	ldr	r3, [r3, #24]
- 80034d8:	f003 0301 	and.w	r3, r3, #1
- 80034dc:	60bb      	str	r3, [r7, #8]
- 80034de:	68bb      	ldr	r3, [r7, #8]
-        temp = AFIO->EXTICR[position >> 2u];
- 80034e0:	4a48      	ldr	r2, [pc, #288]	@ (8003604 <HAL_GPIO_Init+0x2bc>)
- 80034e2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80034e4:	089b      	lsrs	r3, r3, #2
- 80034e6:	3302      	adds	r3, #2
- 80034e8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 80034ec:	60fb      	str	r3, [r7, #12]
-        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
- 80034ee:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80034f0:	f003 0303 	and.w	r3, r3, #3
- 80034f4:	009b      	lsls	r3, r3, #2
- 80034f6:	220f      	movs	r2, #15
- 80034f8:	fa02 f303 	lsl.w	r3, r2, r3
- 80034fc:	43db      	mvns	r3, r3
- 80034fe:	68fa      	ldr	r2, [r7, #12]
- 8003500:	4013      	ands	r3, r2
- 8003502:	60fb      	str	r3, [r7, #12]
-        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
- 8003504:	687b      	ldr	r3, [r7, #4]
- 8003506:	4a40      	ldr	r2, [pc, #256]	@ (8003608 <HAL_GPIO_Init+0x2c0>)
- 8003508:	4293      	cmp	r3, r2
- 800350a:	d013      	beq.n	8003534 <HAL_GPIO_Init+0x1ec>
- 800350c:	687b      	ldr	r3, [r7, #4]
- 800350e:	4a3f      	ldr	r2, [pc, #252]	@ (800360c <HAL_GPIO_Init+0x2c4>)
- 8003510:	4293      	cmp	r3, r2
- 8003512:	d00d      	beq.n	8003530 <HAL_GPIO_Init+0x1e8>
- 8003514:	687b      	ldr	r3, [r7, #4]
- 8003516:	4a3e      	ldr	r2, [pc, #248]	@ (8003610 <HAL_GPIO_Init+0x2c8>)
- 8003518:	4293      	cmp	r3, r2
- 800351a:	d007      	beq.n	800352c <HAL_GPIO_Init+0x1e4>
- 800351c:	687b      	ldr	r3, [r7, #4]
- 800351e:	4a3d      	ldr	r2, [pc, #244]	@ (8003614 <HAL_GPIO_Init+0x2cc>)
- 8003520:	4293      	cmp	r3, r2
- 8003522:	d101      	bne.n	8003528 <HAL_GPIO_Init+0x1e0>
- 8003524:	2303      	movs	r3, #3
- 8003526:	e006      	b.n	8003536 <HAL_GPIO_Init+0x1ee>
- 8003528:	2304      	movs	r3, #4
- 800352a:	e004      	b.n	8003536 <HAL_GPIO_Init+0x1ee>
- 800352c:	2302      	movs	r3, #2
- 800352e:	e002      	b.n	8003536 <HAL_GPIO_Init+0x1ee>
- 8003530:	2301      	movs	r3, #1
- 8003532:	e000      	b.n	8003536 <HAL_GPIO_Init+0x1ee>
- 8003534:	2300      	movs	r3, #0
- 8003536:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 8003538:	f002 0203 	and.w	r2, r2, #3
- 800353c:	0092      	lsls	r2, r2, #2
- 800353e:	4093      	lsls	r3, r2
- 8003540:	68fa      	ldr	r2, [r7, #12]
- 8003542:	4313      	orrs	r3, r2
- 8003544:	60fb      	str	r3, [r7, #12]
-        AFIO->EXTICR[position >> 2u] = temp;
- 8003546:	492f      	ldr	r1, [pc, #188]	@ (8003604 <HAL_GPIO_Init+0x2bc>)
- 8003548:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 800354a:	089b      	lsrs	r3, r3, #2
- 800354c:	3302      	adds	r3, #2
- 800354e:	68fa      	ldr	r2, [r7, #12]
- 8003550:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
-
-
-        /* Enable or disable the rising trigger */
-        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8003554:	683b      	ldr	r3, [r7, #0]
- 8003556:	685b      	ldr	r3, [r3, #4]
- 8003558:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
- 800355c:	2b00      	cmp	r3, #0
- 800355e:	d006      	beq.n	800356e <HAL_GPIO_Init+0x226>
-        {
-          SET_BIT(EXTI->RTSR, iocurrent);
- 8003560:	4b2d      	ldr	r3, [pc, #180]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 8003562:	689a      	ldr	r2, [r3, #8]
- 8003564:	492c      	ldr	r1, [pc, #176]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 8003566:	69bb      	ldr	r3, [r7, #24]
- 8003568:	4313      	orrs	r3, r2
- 800356a:	608b      	str	r3, [r1, #8]
- 800356c:	e006      	b.n	800357c <HAL_GPIO_Init+0x234>
-        }
-        else
-        {
-          CLEAR_BIT(EXTI->RTSR, iocurrent);
- 800356e:	4b2a      	ldr	r3, [pc, #168]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 8003570:	689a      	ldr	r2, [r3, #8]
- 8003572:	69bb      	ldr	r3, [r7, #24]
- 8003574:	43db      	mvns	r3, r3
- 8003576:	4928      	ldr	r1, [pc, #160]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 8003578:	4013      	ands	r3, r2
- 800357a:	608b      	str	r3, [r1, #8]
-        }
-
-        /* Enable or disable the falling trigger */
-        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 800357c:	683b      	ldr	r3, [r7, #0]
- 800357e:	685b      	ldr	r3, [r3, #4]
- 8003580:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
- 8003584:	2b00      	cmp	r3, #0
- 8003586:	d006      	beq.n	8003596 <HAL_GPIO_Init+0x24e>
-        {
-          SET_BIT(EXTI->FTSR, iocurrent);
- 8003588:	4b23      	ldr	r3, [pc, #140]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 800358a:	68da      	ldr	r2, [r3, #12]
- 800358c:	4922      	ldr	r1, [pc, #136]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 800358e:	69bb      	ldr	r3, [r7, #24]
- 8003590:	4313      	orrs	r3, r2
- 8003592:	60cb      	str	r3, [r1, #12]
- 8003594:	e006      	b.n	80035a4 <HAL_GPIO_Init+0x25c>
-        }
-        else
-        {
-          CLEAR_BIT(EXTI->FTSR, iocurrent);
- 8003596:	4b20      	ldr	r3, [pc, #128]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 8003598:	68da      	ldr	r2, [r3, #12]
- 800359a:	69bb      	ldr	r3, [r7, #24]
- 800359c:	43db      	mvns	r3, r3
- 800359e:	491e      	ldr	r1, [pc, #120]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035a0:	4013      	ands	r3, r2
- 80035a2:	60cb      	str	r3, [r1, #12]
-        }
-
-        /* Configure the event mask */
-        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 80035a4:	683b      	ldr	r3, [r7, #0]
- 80035a6:	685b      	ldr	r3, [r3, #4]
- 80035a8:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 80035ac:	2b00      	cmp	r3, #0
- 80035ae:	d006      	beq.n	80035be <HAL_GPIO_Init+0x276>
-        {
-          SET_BIT(EXTI->EMR, iocurrent);
- 80035b0:	4b19      	ldr	r3, [pc, #100]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035b2:	685a      	ldr	r2, [r3, #4]
- 80035b4:	4918      	ldr	r1, [pc, #96]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035b6:	69bb      	ldr	r3, [r7, #24]
- 80035b8:	4313      	orrs	r3, r2
- 80035ba:	604b      	str	r3, [r1, #4]
- 80035bc:	e006      	b.n	80035cc <HAL_GPIO_Init+0x284>
-        }
-        else
-        {
-          CLEAR_BIT(EXTI->EMR, iocurrent);
- 80035be:	4b16      	ldr	r3, [pc, #88]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035c0:	685a      	ldr	r2, [r3, #4]
- 80035c2:	69bb      	ldr	r3, [r7, #24]
- 80035c4:	43db      	mvns	r3, r3
- 80035c6:	4914      	ldr	r1, [pc, #80]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035c8:	4013      	ands	r3, r2
- 80035ca:	604b      	str	r3, [r1, #4]
-        }
-
-        /* Configure the interrupt mask */
-        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 80035cc:	683b      	ldr	r3, [r7, #0]
- 80035ce:	685b      	ldr	r3, [r3, #4]
- 80035d0:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 80035d4:	2b00      	cmp	r3, #0
- 80035d6:	d021      	beq.n	800361c <HAL_GPIO_Init+0x2d4>
-        {
-          SET_BIT(EXTI->IMR, iocurrent);
- 80035d8:	4b0f      	ldr	r3, [pc, #60]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035da:	681a      	ldr	r2, [r3, #0]
- 80035dc:	490e      	ldr	r1, [pc, #56]	@ (8003618 <HAL_GPIO_Init+0x2d0>)
- 80035de:	69bb      	ldr	r3, [r7, #24]
- 80035e0:	4313      	orrs	r3, r2
- 80035e2:	600b      	str	r3, [r1, #0]
- 80035e4:	e021      	b.n	800362a <HAL_GPIO_Init+0x2e2>
- 80035e6:	bf00      	nop
- 80035e8:	10320000 	.word	0x10320000
- 80035ec:	10310000 	.word	0x10310000
- 80035f0:	10220000 	.word	0x10220000
- 80035f4:	10210000 	.word	0x10210000
- 80035f8:	10120000 	.word	0x10120000
- 80035fc:	10110000 	.word	0x10110000
- 8003600:	40021000 	.word	0x40021000
- 8003604:	40010000 	.word	0x40010000
- 8003608:	40010800 	.word	0x40010800
- 800360c:	40010c00 	.word	0x40010c00
- 8003610:	40011000 	.word	0x40011000
- 8003614:	40011400 	.word	0x40011400
- 8003618:	40010400 	.word	0x40010400
-        }
-        else
-        {
-          CLEAR_BIT(EXTI->IMR, iocurrent);
- 800361c:	4b0b      	ldr	r3, [pc, #44]	@ (800364c <HAL_GPIO_Init+0x304>)
- 800361e:	681a      	ldr	r2, [r3, #0]
- 8003620:	69bb      	ldr	r3, [r7, #24]
- 8003622:	43db      	mvns	r3, r3
- 8003624:	4909      	ldr	r1, [pc, #36]	@ (800364c <HAL_GPIO_Init+0x304>)
- 8003626:	4013      	ands	r3, r2
- 8003628:	600b      	str	r3, [r1, #0]
-        }
-      }
-    }
-
-	position++;
- 800362a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 800362c:	3301      	adds	r3, #1
- 800362e:	627b      	str	r3, [r7, #36]	@ 0x24
-  while (((GPIO_Init->Pin) >> position) != 0x00u)
- 8003630:	683b      	ldr	r3, [r7, #0]
- 8003632:	681a      	ldr	r2, [r3, #0]
- 8003634:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003636:	fa22 f303 	lsr.w	r3, r2, r3
- 800363a:	2b00      	cmp	r3, #0
- 800363c:	f47f ae8e 	bne.w	800335c <HAL_GPIO_Init+0x14>
-  }
-}
- 8003640:	bf00      	nop
- 8003642:	bf00      	nop
- 8003644:	372c      	adds	r7, #44	@ 0x2c
- 8003646:	46bd      	mov	sp, r7
- 8003648:	bc80      	pop	{r7}
- 800364a:	4770      	bx	lr
- 800364c:	40010400 	.word	0x40010400
-
-08003650 <HAL_GPIO_ReadPin>:
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- 8003650:	b480      	push	{r7}
- 8003652:	b085      	sub	sp, #20
- 8003654:	af00      	add	r7, sp, #0
- 8003656:	6078      	str	r0, [r7, #4]
- 8003658:	460b      	mov	r3, r1
- 800365a:	807b      	strh	r3, [r7, #2]
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
- 800365c:	687b      	ldr	r3, [r7, #4]
- 800365e:	689a      	ldr	r2, [r3, #8]
- 8003660:	887b      	ldrh	r3, [r7, #2]
- 8003662:	4013      	ands	r3, r2
- 8003664:	2b00      	cmp	r3, #0
- 8003666:	d002      	beq.n	800366e <HAL_GPIO_ReadPin+0x1e>
-  {
-    bitstatus = GPIO_PIN_SET;
- 8003668:	2301      	movs	r3, #1
- 800366a:	73fb      	strb	r3, [r7, #15]
- 800366c:	e001      	b.n	8003672 <HAL_GPIO_ReadPin+0x22>
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
- 800366e:	2300      	movs	r3, #0
- 8003670:	73fb      	strb	r3, [r7, #15]
-  }
-  return bitstatus;
- 8003672:	7bfb      	ldrb	r3, [r7, #15]
-}
- 8003674:	4618      	mov	r0, r3
- 8003676:	3714      	adds	r7, #20
- 8003678:	46bd      	mov	sp, r7
- 800367a:	bc80      	pop	{r7}
- 800367c:	4770      	bx	lr
-
-0800367e <HAL_GPIO_WritePin>:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 800367e:	b480      	push	{r7}
- 8003680:	b083      	sub	sp, #12
- 8003682:	af00      	add	r7, sp, #0
- 8003684:	6078      	str	r0, [r7, #4]
- 8003686:	460b      	mov	r3, r1
- 8003688:	807b      	strh	r3, [r7, #2]
- 800368a:	4613      	mov	r3, r2
- 800368c:	707b      	strb	r3, [r7, #1]
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if (PinState != GPIO_PIN_RESET)
- 800368e:	787b      	ldrb	r3, [r7, #1]
- 8003690:	2b00      	cmp	r3, #0
- 8003692:	d003      	beq.n	800369c <HAL_GPIO_WritePin+0x1e>
-  {
-    GPIOx->BSRR = GPIO_Pin;
- 8003694:	887a      	ldrh	r2, [r7, #2]
- 8003696:	687b      	ldr	r3, [r7, #4]
- 8003698:	611a      	str	r2, [r3, #16]
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
-  }
-}
- 800369a:	e003      	b.n	80036a4 <HAL_GPIO_WritePin+0x26>
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
- 800369c:	887b      	ldrh	r3, [r7, #2]
- 800369e:	041a      	lsls	r2, r3, #16
- 80036a0:	687b      	ldr	r3, [r7, #4]
- 80036a2:	611a      	str	r2, [r3, #16]
 }
  80036a4:	bf00      	nop
  80036a6:	370c      	adds	r7, #12
  80036a8:	46bd      	mov	sp, r7
  80036aa:	bc80      	pop	{r7}
  80036ac:	4770      	bx	lr
+
+080036ae <HAL_ADC_ErrorCallback>:
+  *        (ADC conversion with interruption or transfer by DMA)
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ 80036ae:	b480      	push	{r7}
+ 80036b0:	b083      	sub	sp, #12
+ 80036b2:	af00      	add	r7, sp, #0
+ 80036b4:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+ 80036b6:	bf00      	nop
+ 80036b8:	370c      	adds	r7, #12
+ 80036ba:	46bd      	mov	sp, r7
+ 80036bc:	bc80      	pop	{r7}
+ 80036be:	4770      	bx	lr
+
+080036c0 <HAL_ADC_ConfigChannel>:
+  * @param  hadc: ADC handle
+  * @param  sConfig: Structure of ADC channel for regular group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{ 
+ 80036c0:	b480      	push	{r7}
+ 80036c2:	b085      	sub	sp, #20
+ 80036c4:	af00      	add	r7, sp, #0
+ 80036c6:	6078      	str	r0, [r7, #4]
+ 80036c8:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 80036ca:	2300      	movs	r3, #0
+ 80036cc:	73fb      	strb	r3, [r7, #15]
+  __IO uint32_t wait_loop_index = 0U;
+ 80036ce:	2300      	movs	r3, #0
+ 80036d0:	60bb      	str	r3, [r7, #8]
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 80036d2:	687b      	ldr	r3, [r7, #4]
+ 80036d4:	f893 3024 	ldrb.w	r3, [r3, #36]	@ 0x24
+ 80036d8:	2b01      	cmp	r3, #1
+ 80036da:	d101      	bne.n	80036e0 <HAL_ADC_ConfigChannel+0x20>
+ 80036dc:	2302      	movs	r3, #2
+ 80036de:	e0dc      	b.n	800389a <HAL_ADC_ConfigChannel+0x1da>
+ 80036e0:	687b      	ldr	r3, [r7, #4]
+ 80036e2:	2201      	movs	r2, #1
+ 80036e4:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+  
+  
+  /* Regular sequence configuration */
+  /* For Rank 1 to 6 */
+  if (sConfig->Rank < 7U)
+ 80036e8:	683b      	ldr	r3, [r7, #0]
+ 80036ea:	685b      	ldr	r3, [r3, #4]
+ 80036ec:	2b06      	cmp	r3, #6
+ 80036ee:	d81c      	bhi.n	800372a <HAL_ADC_ConfigChannel+0x6a>
+  {
+    MODIFY_REG(hadc->Instance->SQR3                        ,
+ 80036f0:	687b      	ldr	r3, [r7, #4]
+ 80036f2:	681b      	ldr	r3, [r3, #0]
+ 80036f4:	6b59      	ldr	r1, [r3, #52]	@ 0x34
+ 80036f6:	683b      	ldr	r3, [r7, #0]
+ 80036f8:	685a      	ldr	r2, [r3, #4]
+ 80036fa:	4613      	mov	r3, r2
+ 80036fc:	009b      	lsls	r3, r3, #2
+ 80036fe:	4413      	add	r3, r2
+ 8003700:	3b05      	subs	r3, #5
+ 8003702:	221f      	movs	r2, #31
+ 8003704:	fa02 f303 	lsl.w	r3, r2, r3
+ 8003708:	43db      	mvns	r3, r3
+ 800370a:	4019      	ands	r1, r3
+ 800370c:	683b      	ldr	r3, [r7, #0]
+ 800370e:	6818      	ldr	r0, [r3, #0]
+ 8003710:	683b      	ldr	r3, [r7, #0]
+ 8003712:	685a      	ldr	r2, [r3, #4]
+ 8003714:	4613      	mov	r3, r2
+ 8003716:	009b      	lsls	r3, r3, #2
+ 8003718:	4413      	add	r3, r2
+ 800371a:	3b05      	subs	r3, #5
+ 800371c:	fa00 f203 	lsl.w	r2, r0, r3
+ 8003720:	687b      	ldr	r3, [r7, #4]
+ 8003722:	681b      	ldr	r3, [r3, #0]
+ 8003724:	430a      	orrs	r2, r1
+ 8003726:	635a      	str	r2, [r3, #52]	@ 0x34
+ 8003728:	e03c      	b.n	80037a4 <HAL_ADC_ConfigChannel+0xe4>
+               ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
+               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+  }
+  /* For Rank 7 to 12 */
+  else if (sConfig->Rank < 13U)
+ 800372a:	683b      	ldr	r3, [r7, #0]
+ 800372c:	685b      	ldr	r3, [r3, #4]
+ 800372e:	2b0c      	cmp	r3, #12
+ 8003730:	d81c      	bhi.n	800376c <HAL_ADC_ConfigChannel+0xac>
+  {
+    MODIFY_REG(hadc->Instance->SQR2                        ,
+ 8003732:	687b      	ldr	r3, [r7, #4]
+ 8003734:	681b      	ldr	r3, [r3, #0]
+ 8003736:	6b19      	ldr	r1, [r3, #48]	@ 0x30
+ 8003738:	683b      	ldr	r3, [r7, #0]
+ 800373a:	685a      	ldr	r2, [r3, #4]
+ 800373c:	4613      	mov	r3, r2
+ 800373e:	009b      	lsls	r3, r3, #2
+ 8003740:	4413      	add	r3, r2
+ 8003742:	3b23      	subs	r3, #35	@ 0x23
+ 8003744:	221f      	movs	r2, #31
+ 8003746:	fa02 f303 	lsl.w	r3, r2, r3
+ 800374a:	43db      	mvns	r3, r3
+ 800374c:	4019      	ands	r1, r3
+ 800374e:	683b      	ldr	r3, [r7, #0]
+ 8003750:	6818      	ldr	r0, [r3, #0]
+ 8003752:	683b      	ldr	r3, [r7, #0]
+ 8003754:	685a      	ldr	r2, [r3, #4]
+ 8003756:	4613      	mov	r3, r2
+ 8003758:	009b      	lsls	r3, r3, #2
+ 800375a:	4413      	add	r3, r2
+ 800375c:	3b23      	subs	r3, #35	@ 0x23
+ 800375e:	fa00 f203 	lsl.w	r2, r0, r3
+ 8003762:	687b      	ldr	r3, [r7, #4]
+ 8003764:	681b      	ldr	r3, [r3, #0]
+ 8003766:	430a      	orrs	r2, r1
+ 8003768:	631a      	str	r2, [r3, #48]	@ 0x30
+ 800376a:	e01b      	b.n	80037a4 <HAL_ADC_ConfigChannel+0xe4>
+               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    MODIFY_REG(hadc->Instance->SQR1                        ,
+ 800376c:	687b      	ldr	r3, [r7, #4]
+ 800376e:	681b      	ldr	r3, [r3, #0]
+ 8003770:	6ad9      	ldr	r1, [r3, #44]	@ 0x2c
+ 8003772:	683b      	ldr	r3, [r7, #0]
+ 8003774:	685a      	ldr	r2, [r3, #4]
+ 8003776:	4613      	mov	r3, r2
+ 8003778:	009b      	lsls	r3, r3, #2
+ 800377a:	4413      	add	r3, r2
+ 800377c:	3b41      	subs	r3, #65	@ 0x41
+ 800377e:	221f      	movs	r2, #31
+ 8003780:	fa02 f303 	lsl.w	r3, r2, r3
+ 8003784:	43db      	mvns	r3, r3
+ 8003786:	4019      	ands	r1, r3
+ 8003788:	683b      	ldr	r3, [r7, #0]
+ 800378a:	6818      	ldr	r0, [r3, #0]
+ 800378c:	683b      	ldr	r3, [r7, #0]
+ 800378e:	685a      	ldr	r2, [r3, #4]
+ 8003790:	4613      	mov	r3, r2
+ 8003792:	009b      	lsls	r3, r3, #2
+ 8003794:	4413      	add	r3, r2
+ 8003796:	3b41      	subs	r3, #65	@ 0x41
+ 8003798:	fa00 f203 	lsl.w	r2, r0, r3
+ 800379c:	687b      	ldr	r3, [r7, #4]
+ 800379e:	681b      	ldr	r3, [r3, #0]
+ 80037a0:	430a      	orrs	r2, r1
+ 80037a2:	62da      	str	r2, [r3, #44]	@ 0x2c
+  }
+  
+  
+  /* Channel sampling time configuration */
+  /* For channels 10 to 17 */
+  if (sConfig->Channel >= ADC_CHANNEL_10)
+ 80037a4:	683b      	ldr	r3, [r7, #0]
+ 80037a6:	681b      	ldr	r3, [r3, #0]
+ 80037a8:	2b09      	cmp	r3, #9
+ 80037aa:	d91c      	bls.n	80037e6 <HAL_ADC_ConfigChannel+0x126>
+  {
+    MODIFY_REG(hadc->Instance->SMPR1                             ,
+ 80037ac:	687b      	ldr	r3, [r7, #4]
+ 80037ae:	681b      	ldr	r3, [r3, #0]
+ 80037b0:	68d9      	ldr	r1, [r3, #12]
+ 80037b2:	683b      	ldr	r3, [r7, #0]
+ 80037b4:	681a      	ldr	r2, [r3, #0]
+ 80037b6:	4613      	mov	r3, r2
+ 80037b8:	005b      	lsls	r3, r3, #1
+ 80037ba:	4413      	add	r3, r2
+ 80037bc:	3b1e      	subs	r3, #30
+ 80037be:	2207      	movs	r2, #7
+ 80037c0:	fa02 f303 	lsl.w	r3, r2, r3
+ 80037c4:	43db      	mvns	r3, r3
+ 80037c6:	4019      	ands	r1, r3
+ 80037c8:	683b      	ldr	r3, [r7, #0]
+ 80037ca:	6898      	ldr	r0, [r3, #8]
+ 80037cc:	683b      	ldr	r3, [r7, #0]
+ 80037ce:	681a      	ldr	r2, [r3, #0]
+ 80037d0:	4613      	mov	r3, r2
+ 80037d2:	005b      	lsls	r3, r3, #1
+ 80037d4:	4413      	add	r3, r2
+ 80037d6:	3b1e      	subs	r3, #30
+ 80037d8:	fa00 f203 	lsl.w	r2, r0, r3
+ 80037dc:	687b      	ldr	r3, [r7, #4]
+ 80037de:	681b      	ldr	r3, [r3, #0]
+ 80037e0:	430a      	orrs	r2, r1
+ 80037e2:	60da      	str	r2, [r3, #12]
+ 80037e4:	e019      	b.n	800381a <HAL_ADC_ConfigChannel+0x15a>
+               ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
+               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+  }
+  else /* For channels 0 to 9 */
+  {
+    MODIFY_REG(hadc->Instance->SMPR2                             ,
+ 80037e6:	687b      	ldr	r3, [r7, #4]
+ 80037e8:	681b      	ldr	r3, [r3, #0]
+ 80037ea:	6919      	ldr	r1, [r3, #16]
+ 80037ec:	683b      	ldr	r3, [r7, #0]
+ 80037ee:	681a      	ldr	r2, [r3, #0]
+ 80037f0:	4613      	mov	r3, r2
+ 80037f2:	005b      	lsls	r3, r3, #1
+ 80037f4:	4413      	add	r3, r2
+ 80037f6:	2207      	movs	r2, #7
+ 80037f8:	fa02 f303 	lsl.w	r3, r2, r3
+ 80037fc:	43db      	mvns	r3, r3
+ 80037fe:	4019      	ands	r1, r3
+ 8003800:	683b      	ldr	r3, [r7, #0]
+ 8003802:	6898      	ldr	r0, [r3, #8]
+ 8003804:	683b      	ldr	r3, [r7, #0]
+ 8003806:	681a      	ldr	r2, [r3, #0]
+ 8003808:	4613      	mov	r3, r2
+ 800380a:	005b      	lsls	r3, r3, #1
+ 800380c:	4413      	add	r3, r2
+ 800380e:	fa00 f203 	lsl.w	r2, r0, r3
+ 8003812:	687b      	ldr	r3, [r7, #4]
+ 8003814:	681b      	ldr	r3, [r3, #0]
+ 8003816:	430a      	orrs	r2, r1
+ 8003818:	611a      	str	r2, [r3, #16]
+               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+  }
+  
+  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
+  /* and VREFINT measurement path.                                            */
+  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
+ 800381a:	683b      	ldr	r3, [r7, #0]
+ 800381c:	681b      	ldr	r3, [r3, #0]
+ 800381e:	2b10      	cmp	r3, #16
+ 8003820:	d003      	beq.n	800382a <HAL_ADC_ConfigChannel+0x16a>
+      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
+ 8003822:	683b      	ldr	r3, [r7, #0]
+ 8003824:	681b      	ldr	r3, [r3, #0]
+  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
+ 8003826:	2b11      	cmp	r3, #17
+ 8003828:	d132      	bne.n	8003890 <HAL_ADC_ConfigChannel+0x1d0>
+  {
+    /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
+    /* measurement channels (VrefInt/TempSensor). If these channels are       */
+    /* intended to be set on other ADC instances, an error is reported.       */
+    if (hadc->Instance == ADC1)
+ 800382a:	687b      	ldr	r3, [r7, #4]
+ 800382c:	681b      	ldr	r3, [r3, #0]
+ 800382e:	4a1d      	ldr	r2, [pc, #116]	@ (80038a4 <HAL_ADC_ConfigChannel+0x1e4>)
+ 8003830:	4293      	cmp	r3, r2
+ 8003832:	d125      	bne.n	8003880 <HAL_ADC_ConfigChannel+0x1c0>
+    {
+      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
+ 8003834:	687b      	ldr	r3, [r7, #4]
+ 8003836:	681b      	ldr	r3, [r3, #0]
+ 8003838:	689b      	ldr	r3, [r3, #8]
+ 800383a:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 800383e:	2b00      	cmp	r3, #0
+ 8003840:	d126      	bne.n	8003890 <HAL_ADC_ConfigChannel+0x1d0>
+      {
+        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+ 8003842:	687b      	ldr	r3, [r7, #4]
+ 8003844:	681b      	ldr	r3, [r3, #0]
+ 8003846:	689a      	ldr	r2, [r3, #8]
+ 8003848:	687b      	ldr	r3, [r7, #4]
+ 800384a:	681b      	ldr	r3, [r3, #0]
+ 800384c:	f442 0200 	orr.w	r2, r2, #8388608	@ 0x800000
+ 8003850:	609a      	str	r2, [r3, #8]
+        
+        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ 8003852:	683b      	ldr	r3, [r7, #0]
+ 8003854:	681b      	ldr	r3, [r3, #0]
+ 8003856:	2b10      	cmp	r3, #16
+ 8003858:	d11a      	bne.n	8003890 <HAL_ADC_ConfigChannel+0x1d0>
+        {
+          /* Delay for temperature sensor stabilization time */
+          /* Compute number of CPU cycles to wait for */
+          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ 800385a:	4b13      	ldr	r3, [pc, #76]	@ (80038a8 <HAL_ADC_ConfigChannel+0x1e8>)
+ 800385c:	681b      	ldr	r3, [r3, #0]
+ 800385e:	4a13      	ldr	r2, [pc, #76]	@ (80038ac <HAL_ADC_ConfigChannel+0x1ec>)
+ 8003860:	fba2 2303 	umull	r2, r3, r2, r3
+ 8003864:	0c9a      	lsrs	r2, r3, #18
+ 8003866:	4613      	mov	r3, r2
+ 8003868:	009b      	lsls	r3, r3, #2
+ 800386a:	4413      	add	r3, r2
+ 800386c:	005b      	lsls	r3, r3, #1
+ 800386e:	60bb      	str	r3, [r7, #8]
+          while(wait_loop_index != 0U)
+ 8003870:	e002      	b.n	8003878 <HAL_ADC_ConfigChannel+0x1b8>
+          {
+            wait_loop_index--;
+ 8003872:	68bb      	ldr	r3, [r7, #8]
+ 8003874:	3b01      	subs	r3, #1
+ 8003876:	60bb      	str	r3, [r7, #8]
+          while(wait_loop_index != 0U)
+ 8003878:	68bb      	ldr	r3, [r7, #8]
+ 800387a:	2b00      	cmp	r3, #0
+ 800387c:	d1f9      	bne.n	8003872 <HAL_ADC_ConfigChannel+0x1b2>
+ 800387e:	e007      	b.n	8003890 <HAL_ADC_ConfigChannel+0x1d0>
+      }
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8003880:	687b      	ldr	r3, [r7, #4]
+ 8003882:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003884:	f043 0220 	orr.w	r2, r3, #32
+ 8003888:	687b      	ldr	r3, [r7, #4]
+ 800388a:	629a      	str	r2, [r3, #40]	@ 0x28
+      
+      tmp_hal_status = HAL_ERROR;
+ 800388c:	2301      	movs	r3, #1
+ 800388e:	73fb      	strb	r3, [r7, #15]
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 8003890:	687b      	ldr	r3, [r7, #4]
+ 8003892:	2200      	movs	r2, #0
+ 8003894:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+  
+  /* Return function status */
+  return tmp_hal_status;
+ 8003898:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 800389a:	4618      	mov	r0, r3
+ 800389c:	3714      	adds	r7, #20
+ 800389e:	46bd      	mov	sp, r7
+ 80038a0:	bc80      	pop	{r7}
+ 80038a2:	4770      	bx	lr
+ 80038a4:	40012400 	.word	0x40012400
+ 80038a8:	20000024 	.word	0x20000024
+ 80038ac:	431bde83 	.word	0x431bde83
+
+080038b0 <ADC_Enable>:
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ 80038b0:	b580      	push	{r7, lr}
+ 80038b2:	b084      	sub	sp, #16
+ 80038b4:	af00      	add	r7, sp, #0
+ 80038b6:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart = 0U;
+ 80038b8:	2300      	movs	r3, #0
+ 80038ba:	60fb      	str	r3, [r7, #12]
+  __IO uint32_t wait_loop_index = 0U;
+ 80038bc:	2300      	movs	r3, #0
+ 80038be:	60bb      	str	r3, [r7, #8]
+  
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+ 80038c0:	687b      	ldr	r3, [r7, #4]
+ 80038c2:	681b      	ldr	r3, [r3, #0]
+ 80038c4:	689b      	ldr	r3, [r3, #8]
+ 80038c6:	f003 0301 	and.w	r3, r3, #1
+ 80038ca:	2b01      	cmp	r3, #1
+ 80038cc:	d040      	beq.n	8003950 <ADC_Enable+0xa0>
+  {
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+ 80038ce:	687b      	ldr	r3, [r7, #4]
+ 80038d0:	681b      	ldr	r3, [r3, #0]
+ 80038d2:	689a      	ldr	r2, [r3, #8]
+ 80038d4:	687b      	ldr	r3, [r7, #4]
+ 80038d6:	681b      	ldr	r3, [r3, #0]
+ 80038d8:	f042 0201 	orr.w	r2, r2, #1
+ 80038dc:	609a      	str	r2, [r3, #8]
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ 80038de:	4b1f      	ldr	r3, [pc, #124]	@ (800395c <ADC_Enable+0xac>)
+ 80038e0:	681b      	ldr	r3, [r3, #0]
+ 80038e2:	4a1f      	ldr	r2, [pc, #124]	@ (8003960 <ADC_Enable+0xb0>)
+ 80038e4:	fba2 2303 	umull	r2, r3, r2, r3
+ 80038e8:	0c9b      	lsrs	r3, r3, #18
+ 80038ea:	60bb      	str	r3, [r7, #8]
+    while(wait_loop_index != 0U)
+ 80038ec:	e002      	b.n	80038f4 <ADC_Enable+0x44>
+    {
+      wait_loop_index--;
+ 80038ee:	68bb      	ldr	r3, [r7, #8]
+ 80038f0:	3b01      	subs	r3, #1
+ 80038f2:	60bb      	str	r3, [r7, #8]
+    while(wait_loop_index != 0U)
+ 80038f4:	68bb      	ldr	r3, [r7, #8]
+ 80038f6:	2b00      	cmp	r3, #0
+ 80038f8:	d1f9      	bne.n	80038ee <ADC_Enable+0x3e>
+    }
+    
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+ 80038fa:	f7ff fceb 	bl	80032d4 <HAL_GetTick>
+ 80038fe:	60f8      	str	r0, [r7, #12]
+
+    /* Wait for ADC effectively enabled */
+    while(ADC_IS_ENABLE(hadc) == RESET)
+ 8003900:	e01f      	b.n	8003942 <ADC_Enable+0x92>
+    {
+      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ 8003902:	f7ff fce7 	bl	80032d4 <HAL_GetTick>
+ 8003906:	4602      	mov	r2, r0
+ 8003908:	68fb      	ldr	r3, [r7, #12]
+ 800390a:	1ad3      	subs	r3, r2, r3
+ 800390c:	2b02      	cmp	r3, #2
+ 800390e:	d918      	bls.n	8003942 <ADC_Enable+0x92>
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(ADC_IS_ENABLE(hadc) == RESET)
+ 8003910:	687b      	ldr	r3, [r7, #4]
+ 8003912:	681b      	ldr	r3, [r3, #0]
+ 8003914:	689b      	ldr	r3, [r3, #8]
+ 8003916:	f003 0301 	and.w	r3, r3, #1
+ 800391a:	2b01      	cmp	r3, #1
+ 800391c:	d011      	beq.n	8003942 <ADC_Enable+0x92>
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 800391e:	687b      	ldr	r3, [r7, #4]
+ 8003920:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003922:	f043 0210 	orr.w	r2, r3, #16
+ 8003926:	687b      	ldr	r3, [r7, #4]
+ 8003928:	629a      	str	r2, [r3, #40]	@ 0x28
+
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 800392a:	687b      	ldr	r3, [r7, #4]
+ 800392c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 800392e:	f043 0201 	orr.w	r2, r3, #1
+ 8003932:	687b      	ldr	r3, [r7, #4]
+ 8003934:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+ 8003936:	687b      	ldr	r3, [r7, #4]
+ 8003938:	2200      	movs	r2, #0
+ 800393a:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+
+          return HAL_ERROR;
+ 800393e:	2301      	movs	r3, #1
+ 8003940:	e007      	b.n	8003952 <ADC_Enable+0xa2>
+    while(ADC_IS_ENABLE(hadc) == RESET)
+ 8003942:	687b      	ldr	r3, [r7, #4]
+ 8003944:	681b      	ldr	r3, [r3, #0]
+ 8003946:	689b      	ldr	r3, [r3, #8]
+ 8003948:	f003 0301 	and.w	r3, r3, #1
+ 800394c:	2b01      	cmp	r3, #1
+ 800394e:	d1d8      	bne.n	8003902 <ADC_Enable+0x52>
+      }
+    }
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+ 8003950:	2300      	movs	r3, #0
+}
+ 8003952:	4618      	mov	r0, r3
+ 8003954:	3710      	adds	r7, #16
+ 8003956:	46bd      	mov	sp, r7
+ 8003958:	bd80      	pop	{r7, pc}
+ 800395a:	bf00      	nop
+ 800395c:	20000024 	.word	0x20000024
+ 8003960:	431bde83 	.word	0x431bde83
+
+08003964 <ADC_ConversionStop_Disable>:
+  *         stopped to disable the ADC.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
+{
+ 8003964:	b580      	push	{r7, lr}
+ 8003966:	b084      	sub	sp, #16
+ 8003968:	af00      	add	r7, sp, #0
+ 800396a:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart = 0U;
+ 800396c:	2300      	movs	r3, #0
+ 800396e:	60fb      	str	r3, [r7, #12]
+  
+  /* Verification if ADC is not already disabled */
+  if (ADC_IS_ENABLE(hadc) != RESET)
+ 8003970:	687b      	ldr	r3, [r7, #4]
+ 8003972:	681b      	ldr	r3, [r3, #0]
+ 8003974:	689b      	ldr	r3, [r3, #8]
+ 8003976:	f003 0301 	and.w	r3, r3, #1
+ 800397a:	2b01      	cmp	r3, #1
+ 800397c:	d12e      	bne.n	80039dc <ADC_ConversionStop_Disable+0x78>
+  {
+    /* Disable the ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+ 800397e:	687b      	ldr	r3, [r7, #4]
+ 8003980:	681b      	ldr	r3, [r3, #0]
+ 8003982:	689a      	ldr	r2, [r3, #8]
+ 8003984:	687b      	ldr	r3, [r7, #4]
+ 8003986:	681b      	ldr	r3, [r3, #0]
+ 8003988:	f022 0201 	bic.w	r2, r2, #1
+ 800398c:	609a      	str	r2, [r3, #8]
+     
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+ 800398e:	f7ff fca1 	bl	80032d4 <HAL_GetTick>
+ 8003992:	60f8      	str	r0, [r7, #12]
+    
+    /* Wait for ADC effectively disabled */
+    while(ADC_IS_ENABLE(hadc) != RESET)
+ 8003994:	e01b      	b.n	80039ce <ADC_ConversionStop_Disable+0x6a>
+    {
+      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ 8003996:	f7ff fc9d 	bl	80032d4 <HAL_GetTick>
+ 800399a:	4602      	mov	r2, r0
+ 800399c:	68fb      	ldr	r3, [r7, #12]
+ 800399e:	1ad3      	subs	r3, r2, r3
+ 80039a0:	2b02      	cmp	r3, #2
+ 80039a2:	d914      	bls.n	80039ce <ADC_ConversionStop_Disable+0x6a>
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(ADC_IS_ENABLE(hadc) != RESET)
+ 80039a4:	687b      	ldr	r3, [r7, #4]
+ 80039a6:	681b      	ldr	r3, [r3, #0]
+ 80039a8:	689b      	ldr	r3, [r3, #8]
+ 80039aa:	f003 0301 	and.w	r3, r3, #1
+ 80039ae:	2b01      	cmp	r3, #1
+ 80039b0:	d10d      	bne.n	80039ce <ADC_ConversionStop_Disable+0x6a>
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 80039b2:	687b      	ldr	r3, [r7, #4]
+ 80039b4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80039b6:	f043 0210 	orr.w	r2, r3, #16
+ 80039ba:	687b      	ldr	r3, [r7, #4]
+ 80039bc:	629a      	str	r2, [r3, #40]	@ 0x28
+
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 80039be:	687b      	ldr	r3, [r7, #4]
+ 80039c0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80039c2:	f043 0201 	orr.w	r2, r3, #1
+ 80039c6:	687b      	ldr	r3, [r7, #4]
+ 80039c8:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+          return HAL_ERROR;
+ 80039ca:	2301      	movs	r3, #1
+ 80039cc:	e007      	b.n	80039de <ADC_ConversionStop_Disable+0x7a>
+    while(ADC_IS_ENABLE(hadc) != RESET)
+ 80039ce:	687b      	ldr	r3, [r7, #4]
+ 80039d0:	681b      	ldr	r3, [r3, #0]
+ 80039d2:	689b      	ldr	r3, [r3, #8]
+ 80039d4:	f003 0301 	and.w	r3, r3, #1
+ 80039d8:	2b01      	cmp	r3, #1
+ 80039da:	d0dc      	beq.n	8003996 <ADC_ConversionStop_Disable+0x32>
+      }
+    }
+  }
+  
+  /* Return HAL status */
+  return HAL_OK;
+ 80039dc:	2300      	movs	r3, #0
+}
+ 80039de:	4618      	mov	r0, r3
+ 80039e0:	3710      	adds	r7, #16
+ 80039e2:	46bd      	mov	sp, r7
+ 80039e4:	bd80      	pop	{r7, pc}
+
+080039e6 <ADC_DMAConvCplt>:
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ 80039e6:	b580      	push	{r7, lr}
+ 80039e8:	b084      	sub	sp, #16
+ 80039ea:	af00      	add	r7, sp, #0
+ 80039ec:	6078      	str	r0, [r7, #4]
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 80039ee:	687b      	ldr	r3, [r7, #4]
+ 80039f0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80039f2:	60fb      	str	r3, [r7, #12]
+ 
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ 80039f4:	68fb      	ldr	r3, [r7, #12]
+ 80039f6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80039f8:	f003 0350 	and.w	r3, r3, #80	@ 0x50
+ 80039fc:	2b00      	cmp	r3, #0
+ 80039fe:	d127      	bne.n	8003a50 <ADC_DMAConvCplt+0x6a>
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ 8003a00:	68fb      	ldr	r3, [r7, #12]
+ 8003a02:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003a04:	f443 7200 	orr.w	r2, r3, #512	@ 0x200
+ 8003a08:	68fb      	ldr	r3, [r7, #12]
+ 8003a0a:	629a      	str	r2, [r3, #40]	@ 0x28
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    /* Note: On STM32F1 devices, in case of sequencer enabled                 */
+    /*       (several ranks selected), end of conversion flag is raised       */
+    /*       at the end of the sequence.                                      */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+ 8003a0c:	68fb      	ldr	r3, [r7, #12]
+ 8003a0e:	681b      	ldr	r3, [r3, #0]
+ 8003a10:	689b      	ldr	r3, [r3, #8]
+ 8003a12:	f403 2360 	and.w	r3, r3, #917504	@ 0xe0000
+ 8003a16:	f5b3 2f60 	cmp.w	r3, #917504	@ 0xe0000
+ 8003a1a:	d115      	bne.n	8003a48 <ADC_DMAConvCplt+0x62>
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+ 8003a1c:	68fb      	ldr	r3, [r7, #12]
+ 8003a1e:	7b1b      	ldrb	r3, [r3, #12]
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+ 8003a20:	2b00      	cmp	r3, #0
+ 8003a22:	d111      	bne.n	8003a48 <ADC_DMAConvCplt+0x62>
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+ 8003a24:	68fb      	ldr	r3, [r7, #12]
+ 8003a26:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003a28:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
+ 8003a2c:	68fb      	ldr	r3, [r7, #12]
+ 8003a2e:	629a      	str	r2, [r3, #40]	@ 0x28
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ 8003a30:	68fb      	ldr	r3, [r7, #12]
+ 8003a32:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003a34:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
+ 8003a38:	2b00      	cmp	r3, #0
+ 8003a3a:	d105      	bne.n	8003a48 <ADC_DMAConvCplt+0x62>
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ 8003a3c:	68fb      	ldr	r3, [r7, #12]
+ 8003a3e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003a40:	f043 0201 	orr.w	r2, r3, #1
+ 8003a44:	68fb      	ldr	r3, [r7, #12]
+ 8003a46:	629a      	str	r2, [r3, #40]	@ 0x28
+    
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+ 8003a48:	68f8      	ldr	r0, [r7, #12]
+ 8003a4a:	f7ff f953 	bl	8002cf4 <HAL_ADC_ConvCpltCallback>
+  else
+  {
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
+  }
+}
+ 8003a4e:	e004      	b.n	8003a5a <ADC_DMAConvCplt+0x74>
+    hadc->DMA_Handle->XferErrorCallback(hdma);
+ 8003a50:	68fb      	ldr	r3, [r7, #12]
+ 8003a52:	6a1b      	ldr	r3, [r3, #32]
+ 8003a54:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8003a56:	6878      	ldr	r0, [r7, #4]
+ 8003a58:	4798      	blx	r3
+}
+ 8003a5a:	bf00      	nop
+ 8003a5c:	3710      	adds	r7, #16
+ 8003a5e:	46bd      	mov	sp, r7
+ 8003a60:	bd80      	pop	{r7, pc}
+
+08003a62 <ADC_DMAHalfConvCplt>:
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+ 8003a62:	b580      	push	{r7, lr}
+ 8003a64:	b084      	sub	sp, #16
+ 8003a66:	af00      	add	r7, sp, #0
+ 8003a68:	6078      	str	r0, [r7, #4]
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 8003a6a:	687b      	ldr	r3, [r7, #4]
+ 8003a6c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8003a6e:	60fb      	str	r3, [r7, #12]
+  
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+ 8003a70:	68f8      	ldr	r0, [r7, #12]
+ 8003a72:	f7ff fe13 	bl	800369c <HAL_ADC_ConvHalfCpltCallback>
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+ 8003a76:	bf00      	nop
+ 8003a78:	3710      	adds	r7, #16
+ 8003a7a:	46bd      	mov	sp, r7
+ 8003a7c:	bd80      	pop	{r7, pc}
+
+08003a7e <ADC_DMAError>:
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)   
+{
+ 8003a7e:	b580      	push	{r7, lr}
+ 8003a80:	b084      	sub	sp, #16
+ 8003a82:	af00      	add	r7, sp, #0
+ 8003a84:	6078      	str	r0, [r7, #4]
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 8003a86:	687b      	ldr	r3, [r7, #4]
+ 8003a88:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8003a8a:	60fb      	str	r3, [r7, #12]
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ 8003a8c:	68fb      	ldr	r3, [r7, #12]
+ 8003a8e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003a90:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
+ 8003a94:	68fb      	ldr	r3, [r7, #12]
+ 8003a96:	629a      	str	r2, [r3, #40]	@ 0x28
+  
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+ 8003a98:	68fb      	ldr	r3, [r7, #12]
+ 8003a9a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8003a9c:	f043 0204 	orr.w	r2, r3, #4
+ 8003aa0:	68fb      	ldr	r3, [r7, #12]
+ 8003aa2:	62da      	str	r2, [r3, #44]	@ 0x2c
+  
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+ 8003aa4:	68f8      	ldr	r0, [r7, #12]
+ 8003aa6:	f7ff fe02 	bl	80036ae <HAL_ADC_ErrorCallback>
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+ 8003aaa:	bf00      	nop
+ 8003aac:	3710      	adds	r7, #16
+ 8003aae:	46bd      	mov	sp, r7
+ 8003ab0:	bd80      	pop	{r7, pc}
 	...
 
-080036b0 <HAL_GPIO_EXTI_IRQHandler>:
+08003ab4 <HAL_ADCEx_Calibration_Start>:
+  *         the completion of this function.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+ 8003ab4:	b590      	push	{r4, r7, lr}
+ 8003ab6:	b087      	sub	sp, #28
+ 8003ab8:	af00      	add	r7, sp, #0
+ 8003aba:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 8003abc:	2300      	movs	r3, #0
+ 8003abe:	75fb      	strb	r3, [r7, #23]
+  uint32_t tickstart;
+  __IO uint32_t wait_loop_index = 0U;
+ 8003ac0:	2300      	movs	r3, #0
+ 8003ac2:	60fb      	str	r3, [r7, #12]
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 8003ac4:	687b      	ldr	r3, [r7, #4]
+ 8003ac6:	f893 3024 	ldrb.w	r3, [r3, #36]	@ 0x24
+ 8003aca:	2b01      	cmp	r3, #1
+ 8003acc:	d101      	bne.n	8003ad2 <HAL_ADCEx_Calibration_Start+0x1e>
+ 8003ace:	2302      	movs	r3, #2
+ 8003ad0:	e097      	b.n	8003c02 <HAL_ADCEx_Calibration_Start+0x14e>
+ 8003ad2:	687b      	ldr	r3, [r7, #4]
+ 8003ad4:	2201      	movs	r2, #1
+ 8003ad6:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+    
+   /* 1. Disable ADC peripheral                                                 */
+   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+ 8003ada:	6878      	ldr	r0, [r7, #4]
+ 8003adc:	f7ff ff42 	bl	8003964 <ADC_ConversionStop_Disable>
+ 8003ae0:	4603      	mov	r3, r0
+ 8003ae2:	75fb      	strb	r3, [r7, #23]
+  
+   /* 2. Calibration prerequisite delay before starting the calibration.       */
+   /*    - ADC must be enabled for at least two ADC clock cycles               */
+   tmp_hal_status = ADC_Enable(hadc);
+ 8003ae4:	6878      	ldr	r0, [r7, #4]
+ 8003ae6:	f7ff fee3 	bl	80038b0 <ADC_Enable>
+ 8003aea:	4603      	mov	r3, r0
+ 8003aec:	75fb      	strb	r3, [r7, #23]
+
+   /* Check if ADC is effectively enabled */
+   if (tmp_hal_status == HAL_OK)
+ 8003aee:	7dfb      	ldrb	r3, [r7, #23]
+ 8003af0:	2b00      	cmp	r3, #0
+ 8003af2:	f040 8081 	bne.w	8003bf8 <HAL_ADCEx_Calibration_Start+0x144>
+   {
+     /* Set ADC state */
+     ADC_STATE_CLR_SET(hadc->State,
+ 8003af6:	687b      	ldr	r3, [r7, #4]
+ 8003af8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003afa:	f423 5388 	bic.w	r3, r3, #4352	@ 0x1100
+ 8003afe:	f023 0302 	bic.w	r3, r3, #2
+ 8003b02:	f043 0202 	orr.w	r2, r3, #2
+ 8003b06:	687b      	ldr	r3, [r7, #4]
+ 8003b08:	629a      	str	r2, [r3, #40]	@ 0x28
+    
+    /* Hardware prerequisite: delay before starting the calibration.          */
+    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
+    /*  - Wait for the expected ADC clock cycles delay */
+    wait_loop_index = ((SystemCoreClock
+                        / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
+ 8003b0a:	4b40      	ldr	r3, [pc, #256]	@ (8003c0c <HAL_ADCEx_Calibration_Start+0x158>)
+ 8003b0c:	681c      	ldr	r4, [r3, #0]
+ 8003b0e:	2002      	movs	r0, #2
+ 8003b10:	f002 fcf6 	bl	8006500 <HAL_RCCEx_GetPeriphCLKFreq>
+ 8003b14:	4603      	mov	r3, r0
+ 8003b16:	fbb4 f3f3 	udiv	r3, r4, r3
+                       * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
+ 8003b1a:	005b      	lsls	r3, r3, #1
+    wait_loop_index = ((SystemCoreClock
+ 8003b1c:	60fb      	str	r3, [r7, #12]
+
+    while(wait_loop_index != 0U)
+ 8003b1e:	e002      	b.n	8003b26 <HAL_ADCEx_Calibration_Start+0x72>
+    {
+      wait_loop_index--;
+ 8003b20:	68fb      	ldr	r3, [r7, #12]
+ 8003b22:	3b01      	subs	r3, #1
+ 8003b24:	60fb      	str	r3, [r7, #12]
+    while(wait_loop_index != 0U)
+ 8003b26:	68fb      	ldr	r3, [r7, #12]
+ 8003b28:	2b00      	cmp	r3, #0
+ 8003b2a:	d1f9      	bne.n	8003b20 <HAL_ADCEx_Calibration_Start+0x6c>
+    }
+
+    /* 3. Resets ADC calibration registers */  
+    SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
+ 8003b2c:	687b      	ldr	r3, [r7, #4]
+ 8003b2e:	681b      	ldr	r3, [r3, #0]
+ 8003b30:	689a      	ldr	r2, [r3, #8]
+ 8003b32:	687b      	ldr	r3, [r7, #4]
+ 8003b34:	681b      	ldr	r3, [r3, #0]
+ 8003b36:	f042 0208 	orr.w	r2, r2, #8
+ 8003b3a:	609a      	str	r2, [r3, #8]
+    
+    tickstart = HAL_GetTick();  
+ 8003b3c:	f7ff fbca 	bl	80032d4 <HAL_GetTick>
+ 8003b40:	6138      	str	r0, [r7, #16]
+
+    /* Wait for calibration reset completion */
+    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ 8003b42:	e01b      	b.n	8003b7c <HAL_ADCEx_Calibration_Start+0xc8>
+    {
+      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ 8003b44:	f7ff fbc6 	bl	80032d4 <HAL_GetTick>
+ 8003b48:	4602      	mov	r2, r0
+ 8003b4a:	693b      	ldr	r3, [r7, #16]
+ 8003b4c:	1ad3      	subs	r3, r2, r3
+ 8003b4e:	2b0a      	cmp	r3, #10
+ 8003b50:	d914      	bls.n	8003b7c <HAL_ADCEx_Calibration_Start+0xc8>
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ 8003b52:	687b      	ldr	r3, [r7, #4]
+ 8003b54:	681b      	ldr	r3, [r3, #0]
+ 8003b56:	689b      	ldr	r3, [r3, #8]
+ 8003b58:	f003 0308 	and.w	r3, r3, #8
+ 8003b5c:	2b00      	cmp	r3, #0
+ 8003b5e:	d00d      	beq.n	8003b7c <HAL_ADCEx_Calibration_Start+0xc8>
+        {
+          /* Update ADC state machine to error */
+          ADC_STATE_CLR_SET(hadc->State,
+ 8003b60:	687b      	ldr	r3, [r7, #4]
+ 8003b62:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003b64:	f023 0312 	bic.w	r3, r3, #18
+ 8003b68:	f043 0210 	orr.w	r2, r3, #16
+ 8003b6c:	687b      	ldr	r3, [r7, #4]
+ 8003b6e:	629a      	str	r2, [r3, #40]	@ 0x28
+                            HAL_ADC_STATE_BUSY_INTERNAL,
+                            HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+ 8003b70:	687b      	ldr	r3, [r7, #4]
+ 8003b72:	2200      	movs	r2, #0
+ 8003b74:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+
+          return HAL_ERROR;
+ 8003b78:	2301      	movs	r3, #1
+ 8003b7a:	e042      	b.n	8003c02 <HAL_ADCEx_Calibration_Start+0x14e>
+    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ 8003b7c:	687b      	ldr	r3, [r7, #4]
+ 8003b7e:	681b      	ldr	r3, [r3, #0]
+ 8003b80:	689b      	ldr	r3, [r3, #8]
+ 8003b82:	f003 0308 	and.w	r3, r3, #8
+ 8003b86:	2b00      	cmp	r3, #0
+ 8003b88:	d1dc      	bne.n	8003b44 <HAL_ADCEx_Calibration_Start+0x90>
+        }
+      }
+    }
+    
+    /* 4. Start ADC calibration */
+    SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
+ 8003b8a:	687b      	ldr	r3, [r7, #4]
+ 8003b8c:	681b      	ldr	r3, [r3, #0]
+ 8003b8e:	689a      	ldr	r2, [r3, #8]
+ 8003b90:	687b      	ldr	r3, [r7, #4]
+ 8003b92:	681b      	ldr	r3, [r3, #0]
+ 8003b94:	f042 0204 	orr.w	r2, r2, #4
+ 8003b98:	609a      	str	r2, [r3, #8]
+    
+    tickstart = HAL_GetTick();  
+ 8003b9a:	f7ff fb9b 	bl	80032d4 <HAL_GetTick>
+ 8003b9e:	6138      	str	r0, [r7, #16]
+
+    /* Wait for calibration completion */
+    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ 8003ba0:	e01b      	b.n	8003bda <HAL_ADCEx_Calibration_Start+0x126>
+    {
+      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ 8003ba2:	f7ff fb97 	bl	80032d4 <HAL_GetTick>
+ 8003ba6:	4602      	mov	r2, r0
+ 8003ba8:	693b      	ldr	r3, [r7, #16]
+ 8003baa:	1ad3      	subs	r3, r2, r3
+ 8003bac:	2b0a      	cmp	r3, #10
+ 8003bae:	d914      	bls.n	8003bda <HAL_ADCEx_Calibration_Start+0x126>
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ 8003bb0:	687b      	ldr	r3, [r7, #4]
+ 8003bb2:	681b      	ldr	r3, [r3, #0]
+ 8003bb4:	689b      	ldr	r3, [r3, #8]
+ 8003bb6:	f003 0304 	and.w	r3, r3, #4
+ 8003bba:	2b00      	cmp	r3, #0
+ 8003bbc:	d00d      	beq.n	8003bda <HAL_ADCEx_Calibration_Start+0x126>
+        {
+          /* Update ADC state machine to error */
+          ADC_STATE_CLR_SET(hadc->State,
+ 8003bbe:	687b      	ldr	r3, [r7, #4]
+ 8003bc0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003bc2:	f023 0312 	bic.w	r3, r3, #18
+ 8003bc6:	f043 0210 	orr.w	r2, r3, #16
+ 8003bca:	687b      	ldr	r3, [r7, #4]
+ 8003bcc:	629a      	str	r2, [r3, #40]	@ 0x28
+                            HAL_ADC_STATE_BUSY_INTERNAL,
+                            HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+ 8003bce:	687b      	ldr	r3, [r7, #4]
+ 8003bd0:	2200      	movs	r2, #0
+ 8003bd2:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+
+          return HAL_ERROR;
+ 8003bd6:	2301      	movs	r3, #1
+ 8003bd8:	e013      	b.n	8003c02 <HAL_ADCEx_Calibration_Start+0x14e>
+    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ 8003bda:	687b      	ldr	r3, [r7, #4]
+ 8003bdc:	681b      	ldr	r3, [r3, #0]
+ 8003bde:	689b      	ldr	r3, [r3, #8]
+ 8003be0:	f003 0304 	and.w	r3, r3, #4
+ 8003be4:	2b00      	cmp	r3, #0
+ 8003be6:	d1dc      	bne.n	8003ba2 <HAL_ADCEx_Calibration_Start+0xee>
+        }
+      }
+    }
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+ 8003be8:	687b      	ldr	r3, [r7, #4]
+ 8003bea:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8003bec:	f023 0303 	bic.w	r3, r3, #3
+ 8003bf0:	f043 0201 	orr.w	r2, r3, #1
+ 8003bf4:	687b      	ldr	r3, [r7, #4]
+ 8003bf6:	629a      	str	r2, [r3, #40]	@ 0x28
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 8003bf8:	687b      	ldr	r3, [r7, #4]
+ 8003bfa:	2200      	movs	r2, #0
+ 8003bfc:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
+  
+  /* Return function status */
+  return tmp_hal_status;
+ 8003c00:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8003c02:	4618      	mov	r0, r3
+ 8003c04:	371c      	adds	r7, #28
+ 8003c06:	46bd      	mov	sp, r7
+ 8003c08:	bd90      	pop	{r4, r7, pc}
+ 8003c0a:	bf00      	nop
+ 8003c0c:	20000024 	.word	0x20000024
+
+08003c10 <__NVIC_SetPriorityGrouping>:
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8003c10:	b480      	push	{r7}
+ 8003c12:	b085      	sub	sp, #20
+ 8003c14:	af00      	add	r7, sp, #0
+ 8003c16:	6078      	str	r0, [r7, #4]
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+ 8003c18:	687b      	ldr	r3, [r7, #4]
+ 8003c1a:	f003 0307 	and.w	r3, r3, #7
+ 8003c1e:	60fb      	str	r3, [r7, #12]
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+ 8003c20:	4b0c      	ldr	r3, [pc, #48]	@ (8003c54 <__NVIC_SetPriorityGrouping+0x44>)
+ 8003c22:	68db      	ldr	r3, [r3, #12]
+ 8003c24:	60bb      	str	r3, [r7, #8]
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+ 8003c26:	68ba      	ldr	r2, [r7, #8]
+ 8003c28:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
+ 8003c2c:	4013      	ands	r3, r2
+ 8003c2e:	60bb      	str	r3, [r7, #8]
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+ 8003c30:	68fb      	ldr	r3, [r7, #12]
+ 8003c32:	021a      	lsls	r2, r3, #8
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8003c34:	68bb      	ldr	r3, [r7, #8]
+ 8003c36:	4313      	orrs	r3, r2
+  reg_value  =  (reg_value                                   |
+ 8003c38:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
+ 8003c3c:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 8003c40:	60bb      	str	r3, [r7, #8]
+  SCB->AIRCR =  reg_value;
+ 8003c42:	4a04      	ldr	r2, [pc, #16]	@ (8003c54 <__NVIC_SetPriorityGrouping+0x44>)
+ 8003c44:	68bb      	ldr	r3, [r7, #8]
+ 8003c46:	60d3      	str	r3, [r2, #12]
+}
+ 8003c48:	bf00      	nop
+ 8003c4a:	3714      	adds	r7, #20
+ 8003c4c:	46bd      	mov	sp, r7
+ 8003c4e:	bc80      	pop	{r7}
+ 8003c50:	4770      	bx	lr
+ 8003c52:	bf00      	nop
+ 8003c54:	e000ed00 	.word	0xe000ed00
+
+08003c58 <__NVIC_GetPriorityGrouping>:
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ 8003c58:	b480      	push	{r7}
+ 8003c5a:	af00      	add	r7, sp, #0
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8003c5c:	4b04      	ldr	r3, [pc, #16]	@ (8003c70 <__NVIC_GetPriorityGrouping+0x18>)
+ 8003c5e:	68db      	ldr	r3, [r3, #12]
+ 8003c60:	0a1b      	lsrs	r3, r3, #8
+ 8003c62:	f003 0307 	and.w	r3, r3, #7
+}
+ 8003c66:	4618      	mov	r0, r3
+ 8003c68:	46bd      	mov	sp, r7
+ 8003c6a:	bc80      	pop	{r7}
+ 8003c6c:	4770      	bx	lr
+ 8003c6e:	bf00      	nop
+ 8003c70:	e000ed00 	.word	0xe000ed00
+
+08003c74 <__NVIC_EnableIRQ>:
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8003c74:	b480      	push	{r7}
+ 8003c76:	b083      	sub	sp, #12
+ 8003c78:	af00      	add	r7, sp, #0
+ 8003c7a:	4603      	mov	r3, r0
+ 8003c7c:	71fb      	strb	r3, [r7, #7]
+  if ((int32_t)(IRQn) >= 0)
+ 8003c7e:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8003c82:	2b00      	cmp	r3, #0
+ 8003c84:	db0b      	blt.n	8003c9e <__NVIC_EnableIRQ+0x2a>
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8003c86:	79fb      	ldrb	r3, [r7, #7]
+ 8003c88:	f003 021f 	and.w	r2, r3, #31
+ 8003c8c:	4906      	ldr	r1, [pc, #24]	@ (8003ca8 <__NVIC_EnableIRQ+0x34>)
+ 8003c8e:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8003c92:	095b      	lsrs	r3, r3, #5
+ 8003c94:	2001      	movs	r0, #1
+ 8003c96:	fa00 f202 	lsl.w	r2, r0, r2
+ 8003c9a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+  }
+}
+ 8003c9e:	bf00      	nop
+ 8003ca0:	370c      	adds	r7, #12
+ 8003ca2:	46bd      	mov	sp, r7
+ 8003ca4:	bc80      	pop	{r7}
+ 8003ca6:	4770      	bx	lr
+ 8003ca8:	e000e100 	.word	0xe000e100
+
+08003cac <__NVIC_SetPriority>:
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 8003cac:	b480      	push	{r7}
+ 8003cae:	b083      	sub	sp, #12
+ 8003cb0:	af00      	add	r7, sp, #0
+ 8003cb2:	4603      	mov	r3, r0
+ 8003cb4:	6039      	str	r1, [r7, #0]
+ 8003cb6:	71fb      	strb	r3, [r7, #7]
+  if ((int32_t)(IRQn) >= 0)
+ 8003cb8:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8003cbc:	2b00      	cmp	r3, #0
+ 8003cbe:	db0a      	blt.n	8003cd6 <__NVIC_SetPriority+0x2a>
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8003cc0:	683b      	ldr	r3, [r7, #0]
+ 8003cc2:	b2da      	uxtb	r2, r3
+ 8003cc4:	490c      	ldr	r1, [pc, #48]	@ (8003cf8 <__NVIC_SetPriority+0x4c>)
+ 8003cc6:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8003cca:	0112      	lsls	r2, r2, #4
+ 8003ccc:	b2d2      	uxtb	r2, r2
+ 8003cce:	440b      	add	r3, r1
+ 8003cd0:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+ 8003cd4:	e00a      	b.n	8003cec <__NVIC_SetPriority+0x40>
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8003cd6:	683b      	ldr	r3, [r7, #0]
+ 8003cd8:	b2da      	uxtb	r2, r3
+ 8003cda:	4908      	ldr	r1, [pc, #32]	@ (8003cfc <__NVIC_SetPriority+0x50>)
+ 8003cdc:	79fb      	ldrb	r3, [r7, #7]
+ 8003cde:	f003 030f 	and.w	r3, r3, #15
+ 8003ce2:	3b04      	subs	r3, #4
+ 8003ce4:	0112      	lsls	r2, r2, #4
+ 8003ce6:	b2d2      	uxtb	r2, r2
+ 8003ce8:	440b      	add	r3, r1
+ 8003cea:	761a      	strb	r2, [r3, #24]
+}
+ 8003cec:	bf00      	nop
+ 8003cee:	370c      	adds	r7, #12
+ 8003cf0:	46bd      	mov	sp, r7
+ 8003cf2:	bc80      	pop	{r7}
+ 8003cf4:	4770      	bx	lr
+ 8003cf6:	bf00      	nop
+ 8003cf8:	e000e100 	.word	0xe000e100
+ 8003cfc:	e000ed00 	.word	0xe000ed00
+
+08003d00 <NVIC_EncodePriority>:
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8003d00:	b480      	push	{r7}
+ 8003d02:	b089      	sub	sp, #36	@ 0x24
+ 8003d04:	af00      	add	r7, sp, #0
+ 8003d06:	60f8      	str	r0, [r7, #12]
+ 8003d08:	60b9      	str	r1, [r7, #8]
+ 8003d0a:	607a      	str	r2, [r7, #4]
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+ 8003d0c:	68fb      	ldr	r3, [r7, #12]
+ 8003d0e:	f003 0307 	and.w	r3, r3, #7
+ 8003d12:	61fb      	str	r3, [r7, #28]
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 8003d14:	69fb      	ldr	r3, [r7, #28]
+ 8003d16:	f1c3 0307 	rsb	r3, r3, #7
+ 8003d1a:	2b04      	cmp	r3, #4
+ 8003d1c:	bf28      	it	cs
+ 8003d1e:	2304      	movcs	r3, #4
+ 8003d20:	61bb      	str	r3, [r7, #24]
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 8003d22:	69fb      	ldr	r3, [r7, #28]
+ 8003d24:	3304      	adds	r3, #4
+ 8003d26:	2b06      	cmp	r3, #6
+ 8003d28:	d902      	bls.n	8003d30 <NVIC_EncodePriority+0x30>
+ 8003d2a:	69fb      	ldr	r3, [r7, #28]
+ 8003d2c:	3b03      	subs	r3, #3
+ 8003d2e:	e000      	b.n	8003d32 <NVIC_EncodePriority+0x32>
+ 8003d30:	2300      	movs	r3, #0
+ 8003d32:	617b      	str	r3, [r7, #20]
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8003d34:	f04f 32ff 	mov.w	r2, #4294967295
+ 8003d38:	69bb      	ldr	r3, [r7, #24]
+ 8003d3a:	fa02 f303 	lsl.w	r3, r2, r3
+ 8003d3e:	43da      	mvns	r2, r3
+ 8003d40:	68bb      	ldr	r3, [r7, #8]
+ 8003d42:	401a      	ands	r2, r3
+ 8003d44:	697b      	ldr	r3, [r7, #20]
+ 8003d46:	409a      	lsls	r2, r3
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 8003d48:	f04f 31ff 	mov.w	r1, #4294967295
+ 8003d4c:	697b      	ldr	r3, [r7, #20]
+ 8003d4e:	fa01 f303 	lsl.w	r3, r1, r3
+ 8003d52:	43d9      	mvns	r1, r3
+ 8003d54:	687b      	ldr	r3, [r7, #4]
+ 8003d56:	400b      	ands	r3, r1
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8003d58:	4313      	orrs	r3, r2
+         );
+}
+ 8003d5a:	4618      	mov	r0, r3
+ 8003d5c:	3724      	adds	r7, #36	@ 0x24
+ 8003d5e:	46bd      	mov	sp, r7
+ 8003d60:	bc80      	pop	{r7}
+ 8003d62:	4770      	bx	lr
+
+08003d64 <SysTick_Config>:
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8003d64:	b580      	push	{r7, lr}
+ 8003d66:	b082      	sub	sp, #8
+ 8003d68:	af00      	add	r7, sp, #0
+ 8003d6a:	6078      	str	r0, [r7, #4]
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8003d6c:	687b      	ldr	r3, [r7, #4]
+ 8003d6e:	3b01      	subs	r3, #1
+ 8003d70:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 8003d74:	d301      	bcc.n	8003d7a <SysTick_Config+0x16>
+  {
+    return (1UL);                                                   /* Reload value impossible */
+ 8003d76:	2301      	movs	r3, #1
+ 8003d78:	e00f      	b.n	8003d9a <SysTick_Config+0x36>
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8003d7a:	4a0a      	ldr	r2, [pc, #40]	@ (8003da4 <SysTick_Config+0x40>)
+ 8003d7c:	687b      	ldr	r3, [r7, #4]
+ 8003d7e:	3b01      	subs	r3, #1
+ 8003d80:	6053      	str	r3, [r2, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8003d82:	210f      	movs	r1, #15
+ 8003d84:	f04f 30ff 	mov.w	r0, #4294967295
+ 8003d88:	f7ff ff90 	bl	8003cac <__NVIC_SetPriority>
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8003d8c:	4b05      	ldr	r3, [pc, #20]	@ (8003da4 <SysTick_Config+0x40>)
+ 8003d8e:	2200      	movs	r2, #0
+ 8003d90:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 8003d92:	4b04      	ldr	r3, [pc, #16]	@ (8003da4 <SysTick_Config+0x40>)
+ 8003d94:	2207      	movs	r2, #7
+ 8003d96:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+ 8003d98:	2300      	movs	r3, #0
+}
+ 8003d9a:	4618      	mov	r0, r3
+ 8003d9c:	3708      	adds	r7, #8
+ 8003d9e:	46bd      	mov	sp, r7
+ 8003da0:	bd80      	pop	{r7, pc}
+ 8003da2:	bf00      	nop
+ 8003da4:	e000e010 	.word	0xe000e010
+
+08003da8 <HAL_NVIC_SetPriorityGrouping>:
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8003da8:	b580      	push	{r7, lr}
+ 8003daa:	b082      	sub	sp, #8
+ 8003dac:	af00      	add	r7, sp, #0
+ 8003dae:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+ 8003db0:	6878      	ldr	r0, [r7, #4]
+ 8003db2:	f7ff ff2d 	bl	8003c10 <__NVIC_SetPriorityGrouping>
+}
+ 8003db6:	bf00      	nop
+ 8003db8:	3708      	adds	r7, #8
+ 8003dba:	46bd      	mov	sp, r7
+ 8003dbc:	bd80      	pop	{r7, pc}
+
+08003dbe <HAL_NVIC_SetPriority>:
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.          
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+ 8003dbe:	b580      	push	{r7, lr}
+ 8003dc0:	b086      	sub	sp, #24
+ 8003dc2:	af00      	add	r7, sp, #0
+ 8003dc4:	4603      	mov	r3, r0
+ 8003dc6:	60b9      	str	r1, [r7, #8]
+ 8003dc8:	607a      	str	r2, [r7, #4]
+ 8003dca:	73fb      	strb	r3, [r7, #15]
+  uint32_t prioritygroup = 0x00U;
+ 8003dcc:	2300      	movs	r3, #0
+ 8003dce:	617b      	str	r3, [r7, #20]
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  
+  prioritygroup = NVIC_GetPriorityGrouping();
+ 8003dd0:	f7ff ff42 	bl	8003c58 <__NVIC_GetPriorityGrouping>
+ 8003dd4:	6178      	str	r0, [r7, #20]
+  
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8003dd6:	687a      	ldr	r2, [r7, #4]
+ 8003dd8:	68b9      	ldr	r1, [r7, #8]
+ 8003dda:	6978      	ldr	r0, [r7, #20]
+ 8003ddc:	f7ff ff90 	bl	8003d00 <NVIC_EncodePriority>
+ 8003de0:	4602      	mov	r2, r0
+ 8003de2:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8003de6:	4611      	mov	r1, r2
+ 8003de8:	4618      	mov	r0, r3
+ 8003dea:	f7ff ff5f 	bl	8003cac <__NVIC_SetPriority>
+}
+ 8003dee:	bf00      	nop
+ 8003df0:	3718      	adds	r7, #24
+ 8003df2:	46bd      	mov	sp, r7
+ 8003df4:	bd80      	pop	{r7, pc}
+
+08003df6 <HAL_NVIC_EnableIRQ>:
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8003df6:	b580      	push	{r7, lr}
+ 8003df8:	b082      	sub	sp, #8
+ 8003dfa:	af00      	add	r7, sp, #0
+ 8003dfc:	4603      	mov	r3, r0
+ 8003dfe:	71fb      	strb	r3, [r7, #7]
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+ 8003e00:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8003e04:	4618      	mov	r0, r3
+ 8003e06:	f7ff ff35 	bl	8003c74 <__NVIC_EnableIRQ>
+}
+ 8003e0a:	bf00      	nop
+ 8003e0c:	3708      	adds	r7, #8
+ 8003e0e:	46bd      	mov	sp, r7
+ 8003e10:	bd80      	pop	{r7, pc}
+
+08003e12 <HAL_SYSTICK_Config>:
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8003e12:	b580      	push	{r7, lr}
+ 8003e14:	b082      	sub	sp, #8
+ 8003e16:	af00      	add	r7, sp, #0
+ 8003e18:	6078      	str	r0, [r7, #4]
+   return SysTick_Config(TicksNumb);
+ 8003e1a:	6878      	ldr	r0, [r7, #4]
+ 8003e1c:	f7ff ffa2 	bl	8003d64 <SysTick_Config>
+ 8003e20:	4603      	mov	r3, r0
+}
+ 8003e22:	4618      	mov	r0, r3
+ 8003e24:	3708      	adds	r7, #8
+ 8003e26:	46bd      	mov	sp, r7
+ 8003e28:	bd80      	pop	{r7, pc}
+	...
+
+08003e2c <HAL_DMA_Init>:
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ 8003e2c:	b480      	push	{r7}
+ 8003e2e:	b085      	sub	sp, #20
+ 8003e30:	af00      	add	r7, sp, #0
+ 8003e32:	6078      	str	r0, [r7, #4]
+  uint32_t tmp = 0U;
+ 8003e34:	2300      	movs	r3, #0
+ 8003e36:	60fb      	str	r3, [r7, #12]
+
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+ 8003e38:	687b      	ldr	r3, [r7, #4]
+ 8003e3a:	2b00      	cmp	r3, #0
+ 8003e3c:	d101      	bne.n	8003e42 <HAL_DMA_Init+0x16>
+  {
+    return HAL_ERROR;
+ 8003e3e:	2301      	movs	r3, #1
+ 8003e40:	e043      	b.n	8003eca <HAL_DMA_Init+0x9e>
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+#else
+  /* DMA1 */
+  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ 8003e42:	687b      	ldr	r3, [r7, #4]
+ 8003e44:	681b      	ldr	r3, [r3, #0]
+ 8003e46:	461a      	mov	r2, r3
+ 8003e48:	4b22      	ldr	r3, [pc, #136]	@ (8003ed4 <HAL_DMA_Init+0xa8>)
+ 8003e4a:	4413      	add	r3, r2
+ 8003e4c:	4a22      	ldr	r2, [pc, #136]	@ (8003ed8 <HAL_DMA_Init+0xac>)
+ 8003e4e:	fba2 2303 	umull	r2, r3, r2, r3
+ 8003e52:	091b      	lsrs	r3, r3, #4
+ 8003e54:	009a      	lsls	r2, r3, #2
+ 8003e56:	687b      	ldr	r3, [r7, #4]
+ 8003e58:	641a      	str	r2, [r3, #64]	@ 0x40
+  hdma->DmaBaseAddress = DMA1;
+ 8003e5a:	687b      	ldr	r3, [r7, #4]
+ 8003e5c:	4a1f      	ldr	r2, [pc, #124]	@ (8003edc <HAL_DMA_Init+0xb0>)
+ 8003e5e:	63da      	str	r2, [r3, #60]	@ 0x3c
+#endif /* DMA2 */
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+ 8003e60:	687b      	ldr	r3, [r7, #4]
+ 8003e62:	2202      	movs	r2, #2
+ 8003e64:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+ 8003e68:	687b      	ldr	r3, [r7, #4]
+ 8003e6a:	681b      	ldr	r3, [r3, #0]
+ 8003e6c:	681b      	ldr	r3, [r3, #0]
+ 8003e6e:	60fb      	str	r3, [r7, #12]
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+ 8003e70:	68fb      	ldr	r3, [r7, #12]
+ 8003e72:	f423 537f 	bic.w	r3, r3, #16320	@ 0x3fc0
+ 8003e76:	f023 0330 	bic.w	r3, r3, #48	@ 0x30
+ 8003e7a:	60fb      	str	r3, [r7, #12]
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
+                      DMA_CCR_DIR));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |=  hdma->Init.Direction        |
+ 8003e7c:	687b      	ldr	r3, [r7, #4]
+ 8003e7e:	685a      	ldr	r2, [r3, #4]
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8003e80:	687b      	ldr	r3, [r7, #4]
+ 8003e82:	689b      	ldr	r3, [r3, #8]
+  tmp |=  hdma->Init.Direction        |
+ 8003e84:	431a      	orrs	r2, r3
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8003e86:	687b      	ldr	r3, [r7, #4]
+ 8003e88:	68db      	ldr	r3, [r3, #12]
+ 8003e8a:	431a      	orrs	r2, r3
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8003e8c:	687b      	ldr	r3, [r7, #4]
+ 8003e8e:	691b      	ldr	r3, [r3, #16]
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8003e90:	431a      	orrs	r2, r3
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8003e92:	687b      	ldr	r3, [r7, #4]
+ 8003e94:	695b      	ldr	r3, [r3, #20]
+ 8003e96:	431a      	orrs	r2, r3
+          hdma->Init.Mode                | hdma->Init.Priority;
+ 8003e98:	687b      	ldr	r3, [r7, #4]
+ 8003e9a:	699b      	ldr	r3, [r3, #24]
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8003e9c:	431a      	orrs	r2, r3
+          hdma->Init.Mode                | hdma->Init.Priority;
+ 8003e9e:	687b      	ldr	r3, [r7, #4]
+ 8003ea0:	69db      	ldr	r3, [r3, #28]
+ 8003ea2:	4313      	orrs	r3, r2
+  tmp |=  hdma->Init.Direction        |
+ 8003ea4:	68fa      	ldr	r2, [r7, #12]
+ 8003ea6:	4313      	orrs	r3, r2
+ 8003ea8:	60fb      	str	r3, [r7, #12]
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+ 8003eaa:	687b      	ldr	r3, [r7, #4]
+ 8003eac:	681b      	ldr	r3, [r3, #0]
+ 8003eae:	68fa      	ldr	r2, [r7, #12]
+ 8003eb0:	601a      	str	r2, [r3, #0]
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8003eb2:	687b      	ldr	r3, [r7, #4]
+ 8003eb4:	2200      	movs	r2, #0
+ 8003eb6:	639a      	str	r2, [r3, #56]	@ 0x38
+
+  /* Initialize the DMA state*/
+  hdma->State = HAL_DMA_STATE_READY;
+ 8003eb8:	687b      	ldr	r3, [r7, #4]
+ 8003eba:	2201      	movs	r2, #1
+ 8003ebc:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+  /* Allocate lock resource and initialize it */
+  hdma->Lock = HAL_UNLOCKED;
+ 8003ec0:	687b      	ldr	r3, [r7, #4]
+ 8003ec2:	2200      	movs	r2, #0
+ 8003ec4:	f883 2020 	strb.w	r2, [r3, #32]
+
+  return HAL_OK;
+ 8003ec8:	2300      	movs	r3, #0
+}
+ 8003eca:	4618      	mov	r0, r3
+ 8003ecc:	3714      	adds	r7, #20
+ 8003ece:	46bd      	mov	sp, r7
+ 8003ed0:	bc80      	pop	{r7}
+ 8003ed2:	4770      	bx	lr
+ 8003ed4:	bffdfff8 	.word	0xbffdfff8
+ 8003ed8:	cccccccd 	.word	0xcccccccd
+ 8003edc:	40020000 	.word	0x40020000
+
+08003ee0 <HAL_DMA_Start_IT>:
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ 8003ee0:	b580      	push	{r7, lr}
+ 8003ee2:	b086      	sub	sp, #24
+ 8003ee4:	af00      	add	r7, sp, #0
+ 8003ee6:	60f8      	str	r0, [r7, #12]
+ 8003ee8:	60b9      	str	r1, [r7, #8]
+ 8003eea:	607a      	str	r2, [r7, #4]
+ 8003eec:	603b      	str	r3, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8003eee:	2300      	movs	r3, #0
+ 8003ef0:	75fb      	strb	r3, [r7, #23]
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+ 8003ef2:	68fb      	ldr	r3, [r7, #12]
+ 8003ef4:	f893 3020 	ldrb.w	r3, [r3, #32]
+ 8003ef8:	2b01      	cmp	r3, #1
+ 8003efa:	d101      	bne.n	8003f00 <HAL_DMA_Start_IT+0x20>
+ 8003efc:	2302      	movs	r3, #2
+ 8003efe:	e04b      	b.n	8003f98 <HAL_DMA_Start_IT+0xb8>
+ 8003f00:	68fb      	ldr	r3, [r7, #12]
+ 8003f02:	2201      	movs	r2, #1
+ 8003f04:	f883 2020 	strb.w	r2, [r3, #32]
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+ 8003f08:	68fb      	ldr	r3, [r7, #12]
+ 8003f0a:	f893 3021 	ldrb.w	r3, [r3, #33]	@ 0x21
+ 8003f0e:	b2db      	uxtb	r3, r3
+ 8003f10:	2b01      	cmp	r3, #1
+ 8003f12:	d13a      	bne.n	8003f8a <HAL_DMA_Start_IT+0xaa>
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8003f14:	68fb      	ldr	r3, [r7, #12]
+ 8003f16:	2202      	movs	r2, #2
+ 8003f18:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8003f1c:	68fb      	ldr	r3, [r7, #12]
+ 8003f1e:	2200      	movs	r2, #0
+ 8003f20:	639a      	str	r2, [r3, #56]	@ 0x38
+    
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+ 8003f22:	68fb      	ldr	r3, [r7, #12]
+ 8003f24:	681b      	ldr	r3, [r3, #0]
+ 8003f26:	681a      	ldr	r2, [r3, #0]
+ 8003f28:	68fb      	ldr	r3, [r7, #12]
+ 8003f2a:	681b      	ldr	r3, [r3, #0]
+ 8003f2c:	f022 0201 	bic.w	r2, r2, #1
+ 8003f30:	601a      	str	r2, [r3, #0]
+    
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 8003f32:	683b      	ldr	r3, [r7, #0]
+ 8003f34:	687a      	ldr	r2, [r7, #4]
+ 8003f36:	68b9      	ldr	r1, [r7, #8]
+ 8003f38:	68f8      	ldr	r0, [r7, #12]
+ 8003f3a:	f000 f9eb 	bl	8004314 <DMA_SetConfig>
+    
+    /* Enable the transfer complete interrupt */
+    /* Enable the transfer Error interrupt */
+    if(NULL != hdma->XferHalfCpltCallback)
+ 8003f3e:	68fb      	ldr	r3, [r7, #12]
+ 8003f40:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8003f42:	2b00      	cmp	r3, #0
+ 8003f44:	d008      	beq.n	8003f58 <HAL_DMA_Start_IT+0x78>
+    {
+      /* Enable the Half transfer complete interrupt as well */
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8003f46:	68fb      	ldr	r3, [r7, #12]
+ 8003f48:	681b      	ldr	r3, [r3, #0]
+ 8003f4a:	681a      	ldr	r2, [r3, #0]
+ 8003f4c:	68fb      	ldr	r3, [r7, #12]
+ 8003f4e:	681b      	ldr	r3, [r3, #0]
+ 8003f50:	f042 020e 	orr.w	r2, r2, #14
+ 8003f54:	601a      	str	r2, [r3, #0]
+ 8003f56:	e00f      	b.n	8003f78 <HAL_DMA_Start_IT+0x98>
+    }
+    else
+    {
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8003f58:	68fb      	ldr	r3, [r7, #12]
+ 8003f5a:	681b      	ldr	r3, [r3, #0]
+ 8003f5c:	681a      	ldr	r2, [r3, #0]
+ 8003f5e:	68fb      	ldr	r3, [r7, #12]
+ 8003f60:	681b      	ldr	r3, [r3, #0]
+ 8003f62:	f022 0204 	bic.w	r2, r2, #4
+ 8003f66:	601a      	str	r2, [r3, #0]
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ 8003f68:	68fb      	ldr	r3, [r7, #12]
+ 8003f6a:	681b      	ldr	r3, [r3, #0]
+ 8003f6c:	681a      	ldr	r2, [r3, #0]
+ 8003f6e:	68fb      	ldr	r3, [r7, #12]
+ 8003f70:	681b      	ldr	r3, [r3, #0]
+ 8003f72:	f042 020a 	orr.w	r2, r2, #10
+ 8003f76:	601a      	str	r2, [r3, #0]
+    }
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+ 8003f78:	68fb      	ldr	r3, [r7, #12]
+ 8003f7a:	681b      	ldr	r3, [r3, #0]
+ 8003f7c:	681a      	ldr	r2, [r3, #0]
+ 8003f7e:	68fb      	ldr	r3, [r7, #12]
+ 8003f80:	681b      	ldr	r3, [r3, #0]
+ 8003f82:	f042 0201 	orr.w	r2, r2, #1
+ 8003f86:	601a      	str	r2, [r3, #0]
+ 8003f88:	e005      	b.n	8003f96 <HAL_DMA_Start_IT+0xb6>
+  }
+  else
+  {      
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma); 
+ 8003f8a:	68fb      	ldr	r3, [r7, #12]
+ 8003f8c:	2200      	movs	r2, #0
+ 8003f8e:	f883 2020 	strb.w	r2, [r3, #32]
+
+    /* Remain BUSY */
+    status = HAL_BUSY;
+ 8003f92:	2302      	movs	r3, #2
+ 8003f94:	75fb      	strb	r3, [r7, #23]
+  }    
+  return status;
+ 8003f96:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8003f98:	4618      	mov	r0, r3
+ 8003f9a:	3718      	adds	r7, #24
+ 8003f9c:	46bd      	mov	sp, r7
+ 8003f9e:	bd80      	pop	{r7, pc}
+
+08003fa0 <HAL_DMA_Abort>:
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ 8003fa0:	b480      	push	{r7}
+ 8003fa2:	b085      	sub	sp, #20
+ 8003fa4:	af00      	add	r7, sp, #0
+ 8003fa6:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8003fa8:	2300      	movs	r3, #0
+ 8003faa:	73fb      	strb	r3, [r7, #15]
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+ 8003fac:	687b      	ldr	r3, [r7, #4]
+ 8003fae:	f893 3021 	ldrb.w	r3, [r3, #33]	@ 0x21
+ 8003fb2:	b2db      	uxtb	r3, r3
+ 8003fb4:	2b02      	cmp	r3, #2
+ 8003fb6:	d008      	beq.n	8003fca <HAL_DMA_Abort+0x2a>
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8003fb8:	687b      	ldr	r3, [r7, #4]
+ 8003fba:	2204      	movs	r2, #4
+ 8003fbc:	639a      	str	r2, [r3, #56]	@ 0x38
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8003fbe:	687b      	ldr	r3, [r7, #4]
+ 8003fc0:	2200      	movs	r2, #0
+ 8003fc2:	f883 2020 	strb.w	r2, [r3, #32]
+    
+    return HAL_ERROR;
+ 8003fc6:	2301      	movs	r3, #1
+ 8003fc8:	e020      	b.n	800400c <HAL_DMA_Abort+0x6c>
+  }
+  else
+
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8003fca:	687b      	ldr	r3, [r7, #4]
+ 8003fcc:	681b      	ldr	r3, [r3, #0]
+ 8003fce:	681a      	ldr	r2, [r3, #0]
+ 8003fd0:	687b      	ldr	r3, [r7, #4]
+ 8003fd2:	681b      	ldr	r3, [r3, #0]
+ 8003fd4:	f022 020e 	bic.w	r2, r2, #14
+ 8003fd8:	601a      	str	r2, [r3, #0]
+      
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+ 8003fda:	687b      	ldr	r3, [r7, #4]
+ 8003fdc:	681b      	ldr	r3, [r3, #0]
+ 8003fde:	681a      	ldr	r2, [r3, #0]
+ 8003fe0:	687b      	ldr	r3, [r7, #4]
+ 8003fe2:	681b      	ldr	r3, [r3, #0]
+ 8003fe4:	f022 0201 	bic.w	r2, r2, #1
+ 8003fe8:	601a      	str	r2, [r3, #0]
+      
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+ 8003fea:	687b      	ldr	r3, [r7, #4]
+ 8003fec:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 8003fee:	687b      	ldr	r3, [r7, #4]
+ 8003ff0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8003ff2:	2101      	movs	r1, #1
+ 8003ff4:	fa01 f202 	lsl.w	r2, r1, r2
+ 8003ff8:	605a      	str	r2, [r3, #4]
+  }
+  /* Change the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+ 8003ffa:	687b      	ldr	r3, [r7, #4]
+ 8003ffc:	2201      	movs	r2, #1
+ 8003ffe:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma);      
+ 8004002:	687b      	ldr	r3, [r7, #4]
+ 8004004:	2200      	movs	r2, #0
+ 8004006:	f883 2020 	strb.w	r2, [r3, #32]
+  
+  return status; 
+ 800400a:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 800400c:	4618      	mov	r0, r3
+ 800400e:	3714      	adds	r7, #20
+ 8004010:	46bd      	mov	sp, r7
+ 8004012:	bc80      	pop	{r7}
+ 8004014:	4770      	bx	lr
+	...
+
+08004018 <HAL_DMA_Abort_IT>:
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{  
+ 8004018:	b580      	push	{r7, lr}
+ 800401a:	b084      	sub	sp, #16
+ 800401c:	af00      	add	r7, sp, #0
+ 800401e:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8004020:	2300      	movs	r3, #0
+ 8004022:	73fb      	strb	r3, [r7, #15]
+  
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+ 8004024:	687b      	ldr	r3, [r7, #4]
+ 8004026:	f893 3021 	ldrb.w	r3, [r3, #33]	@ 0x21
+ 800402a:	b2db      	uxtb	r3, r3
+ 800402c:	2b02      	cmp	r3, #2
+ 800402e:	d005      	beq.n	800403c <HAL_DMA_Abort_IT+0x24>
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8004030:	687b      	ldr	r3, [r7, #4]
+ 8004032:	2204      	movs	r2, #4
+ 8004034:	639a      	str	r2, [r3, #56]	@ 0x38
+        
+    status = HAL_ERROR;
+ 8004036:	2301      	movs	r3, #1
+ 8004038:	73fb      	strb	r3, [r7, #15]
+ 800403a:	e051      	b.n	80040e0 <HAL_DMA_Abort_IT+0xc8>
+  }
+  else
+  { 
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 800403c:	687b      	ldr	r3, [r7, #4]
+ 800403e:	681b      	ldr	r3, [r3, #0]
+ 8004040:	681a      	ldr	r2, [r3, #0]
+ 8004042:	687b      	ldr	r3, [r7, #4]
+ 8004044:	681b      	ldr	r3, [r3, #0]
+ 8004046:	f022 020e 	bic.w	r2, r2, #14
+ 800404a:	601a      	str	r2, [r3, #0]
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+ 800404c:	687b      	ldr	r3, [r7, #4]
+ 800404e:	681b      	ldr	r3, [r3, #0]
+ 8004050:	681a      	ldr	r2, [r3, #0]
+ 8004052:	687b      	ldr	r3, [r7, #4]
+ 8004054:	681b      	ldr	r3, [r3, #0]
+ 8004056:	f022 0201 	bic.w	r2, r2, #1
+ 800405a:	601a      	str	r2, [r3, #0]
+
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+ 800405c:	687b      	ldr	r3, [r7, #4]
+ 800405e:	681b      	ldr	r3, [r3, #0]
+ 8004060:	4a22      	ldr	r2, [pc, #136]	@ (80040ec <HAL_DMA_Abort_IT+0xd4>)
+ 8004062:	4293      	cmp	r3, r2
+ 8004064:	d029      	beq.n	80040ba <HAL_DMA_Abort_IT+0xa2>
+ 8004066:	687b      	ldr	r3, [r7, #4]
+ 8004068:	681b      	ldr	r3, [r3, #0]
+ 800406a:	4a21      	ldr	r2, [pc, #132]	@ (80040f0 <HAL_DMA_Abort_IT+0xd8>)
+ 800406c:	4293      	cmp	r3, r2
+ 800406e:	d022      	beq.n	80040b6 <HAL_DMA_Abort_IT+0x9e>
+ 8004070:	687b      	ldr	r3, [r7, #4]
+ 8004072:	681b      	ldr	r3, [r3, #0]
+ 8004074:	4a1f      	ldr	r2, [pc, #124]	@ (80040f4 <HAL_DMA_Abort_IT+0xdc>)
+ 8004076:	4293      	cmp	r3, r2
+ 8004078:	d01a      	beq.n	80040b0 <HAL_DMA_Abort_IT+0x98>
+ 800407a:	687b      	ldr	r3, [r7, #4]
+ 800407c:	681b      	ldr	r3, [r3, #0]
+ 800407e:	4a1e      	ldr	r2, [pc, #120]	@ (80040f8 <HAL_DMA_Abort_IT+0xe0>)
+ 8004080:	4293      	cmp	r3, r2
+ 8004082:	d012      	beq.n	80040aa <HAL_DMA_Abort_IT+0x92>
+ 8004084:	687b      	ldr	r3, [r7, #4]
+ 8004086:	681b      	ldr	r3, [r3, #0]
+ 8004088:	4a1c      	ldr	r2, [pc, #112]	@ (80040fc <HAL_DMA_Abort_IT+0xe4>)
+ 800408a:	4293      	cmp	r3, r2
+ 800408c:	d00a      	beq.n	80040a4 <HAL_DMA_Abort_IT+0x8c>
+ 800408e:	687b      	ldr	r3, [r7, #4]
+ 8004090:	681b      	ldr	r3, [r3, #0]
+ 8004092:	4a1b      	ldr	r2, [pc, #108]	@ (8004100 <HAL_DMA_Abort_IT+0xe8>)
+ 8004094:	4293      	cmp	r3, r2
+ 8004096:	d102      	bne.n	800409e <HAL_DMA_Abort_IT+0x86>
+ 8004098:	f44f 1380 	mov.w	r3, #1048576	@ 0x100000
+ 800409c:	e00e      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 800409e:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
+ 80040a2:	e00b      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 80040a4:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
+ 80040a8:	e008      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 80040aa:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 80040ae:	e005      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 80040b0:	f44f 7380 	mov.w	r3, #256	@ 0x100
+ 80040b4:	e002      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 80040b6:	2310      	movs	r3, #16
+ 80040b8:	e000      	b.n	80040bc <HAL_DMA_Abort_IT+0xa4>
+ 80040ba:	2301      	movs	r3, #1
+ 80040bc:	4a11      	ldr	r2, [pc, #68]	@ (8004104 <HAL_DMA_Abort_IT+0xec>)
+ 80040be:	6053      	str	r3, [r2, #4]
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 80040c0:	687b      	ldr	r3, [r7, #4]
+ 80040c2:	2201      	movs	r2, #1
+ 80040c4:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 80040c8:	687b      	ldr	r3, [r7, #4]
+ 80040ca:	2200      	movs	r2, #0
+ 80040cc:	f883 2020 	strb.w	r2, [r3, #32]
+
+    /* Call User Abort callback */
+    if(hdma->XferAbortCallback != NULL)
+ 80040d0:	687b      	ldr	r3, [r7, #4]
+ 80040d2:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80040d4:	2b00      	cmp	r3, #0
+ 80040d6:	d003      	beq.n	80040e0 <HAL_DMA_Abort_IT+0xc8>
+    {
+      hdma->XferAbortCallback(hdma);
+ 80040d8:	687b      	ldr	r3, [r7, #4]
+ 80040da:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80040dc:	6878      	ldr	r0, [r7, #4]
+ 80040de:	4798      	blx	r3
+    } 
+  }
+  return status;
+ 80040e0:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 80040e2:	4618      	mov	r0, r3
+ 80040e4:	3710      	adds	r7, #16
+ 80040e6:	46bd      	mov	sp, r7
+ 80040e8:	bd80      	pop	{r7, pc}
+ 80040ea:	bf00      	nop
+ 80040ec:	40020008 	.word	0x40020008
+ 80040f0:	4002001c 	.word	0x4002001c
+ 80040f4:	40020030 	.word	0x40020030
+ 80040f8:	40020044 	.word	0x40020044
+ 80040fc:	40020058 	.word	0x40020058
+ 8004100:	4002006c 	.word	0x4002006c
+ 8004104:	40020000 	.word	0x40020000
+
+08004108 <HAL_DMA_IRQHandler>:
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.  
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ 8004108:	b580      	push	{r7, lr}
+ 800410a:	b084      	sub	sp, #16
+ 800410c:	af00      	add	r7, sp, #0
+ 800410e:	6078      	str	r0, [r7, #4]
+  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ 8004110:	687b      	ldr	r3, [r7, #4]
+ 8004112:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8004114:	681b      	ldr	r3, [r3, #0]
+ 8004116:	60fb      	str	r3, [r7, #12]
+  uint32_t source_it = hdma->Instance->CCR;
+ 8004118:	687b      	ldr	r3, [r7, #4]
+ 800411a:	681b      	ldr	r3, [r3, #0]
+ 800411c:	681b      	ldr	r3, [r3, #0]
+ 800411e:	60bb      	str	r3, [r7, #8]
+  
+  /* Half Transfer Complete Interrupt management ******************************/
+  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
+ 8004120:	687b      	ldr	r3, [r7, #4]
+ 8004122:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8004124:	2204      	movs	r2, #4
+ 8004126:	409a      	lsls	r2, r3
+ 8004128:	68fb      	ldr	r3, [r7, #12]
+ 800412a:	4013      	ands	r3, r2
+ 800412c:	2b00      	cmp	r3, #0
+ 800412e:	d04f      	beq.n	80041d0 <HAL_DMA_IRQHandler+0xc8>
+ 8004130:	68bb      	ldr	r3, [r7, #8]
+ 8004132:	f003 0304 	and.w	r3, r3, #4
+ 8004136:	2b00      	cmp	r3, #0
+ 8004138:	d04a      	beq.n	80041d0 <HAL_DMA_IRQHandler+0xc8>
+  {
+    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 800413a:	687b      	ldr	r3, [r7, #4]
+ 800413c:	681b      	ldr	r3, [r3, #0]
+ 800413e:	681b      	ldr	r3, [r3, #0]
+ 8004140:	f003 0320 	and.w	r3, r3, #32
+ 8004144:	2b00      	cmp	r3, #0
+ 8004146:	d107      	bne.n	8004158 <HAL_DMA_IRQHandler+0x50>
+    {
+      /* Disable the half transfer interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8004148:	687b      	ldr	r3, [r7, #4]
+ 800414a:	681b      	ldr	r3, [r3, #0]
+ 800414c:	681a      	ldr	r2, [r3, #0]
+ 800414e:	687b      	ldr	r3, [r7, #4]
+ 8004150:	681b      	ldr	r3, [r3, #0]
+ 8004152:	f022 0204 	bic.w	r2, r2, #4
+ 8004156:	601a      	str	r2, [r3, #0]
+    }
+    /* Clear the half transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 8004158:	687b      	ldr	r3, [r7, #4]
+ 800415a:	681b      	ldr	r3, [r3, #0]
+ 800415c:	4a66      	ldr	r2, [pc, #408]	@ (80042f8 <HAL_DMA_IRQHandler+0x1f0>)
+ 800415e:	4293      	cmp	r3, r2
+ 8004160:	d029      	beq.n	80041b6 <HAL_DMA_IRQHandler+0xae>
+ 8004162:	687b      	ldr	r3, [r7, #4]
+ 8004164:	681b      	ldr	r3, [r3, #0]
+ 8004166:	4a65      	ldr	r2, [pc, #404]	@ (80042fc <HAL_DMA_IRQHandler+0x1f4>)
+ 8004168:	4293      	cmp	r3, r2
+ 800416a:	d022      	beq.n	80041b2 <HAL_DMA_IRQHandler+0xaa>
+ 800416c:	687b      	ldr	r3, [r7, #4]
+ 800416e:	681b      	ldr	r3, [r3, #0]
+ 8004170:	4a63      	ldr	r2, [pc, #396]	@ (8004300 <HAL_DMA_IRQHandler+0x1f8>)
+ 8004172:	4293      	cmp	r3, r2
+ 8004174:	d01a      	beq.n	80041ac <HAL_DMA_IRQHandler+0xa4>
+ 8004176:	687b      	ldr	r3, [r7, #4]
+ 8004178:	681b      	ldr	r3, [r3, #0]
+ 800417a:	4a62      	ldr	r2, [pc, #392]	@ (8004304 <HAL_DMA_IRQHandler+0x1fc>)
+ 800417c:	4293      	cmp	r3, r2
+ 800417e:	d012      	beq.n	80041a6 <HAL_DMA_IRQHandler+0x9e>
+ 8004180:	687b      	ldr	r3, [r7, #4]
+ 8004182:	681b      	ldr	r3, [r3, #0]
+ 8004184:	4a60      	ldr	r2, [pc, #384]	@ (8004308 <HAL_DMA_IRQHandler+0x200>)
+ 8004186:	4293      	cmp	r3, r2
+ 8004188:	d00a      	beq.n	80041a0 <HAL_DMA_IRQHandler+0x98>
+ 800418a:	687b      	ldr	r3, [r7, #4]
+ 800418c:	681b      	ldr	r3, [r3, #0]
+ 800418e:	4a5f      	ldr	r2, [pc, #380]	@ (800430c <HAL_DMA_IRQHandler+0x204>)
+ 8004190:	4293      	cmp	r3, r2
+ 8004192:	d102      	bne.n	800419a <HAL_DMA_IRQHandler+0x92>
+ 8004194:	f44f 0380 	mov.w	r3, #4194304	@ 0x400000
+ 8004198:	e00e      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 800419a:	f04f 6380 	mov.w	r3, #67108864	@ 0x4000000
+ 800419e:	e00b      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 80041a0:	f44f 2380 	mov.w	r3, #262144	@ 0x40000
+ 80041a4:	e008      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 80041a6:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
+ 80041aa:	e005      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 80041ac:	f44f 6380 	mov.w	r3, #1024	@ 0x400
+ 80041b0:	e002      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 80041b2:	2340      	movs	r3, #64	@ 0x40
+ 80041b4:	e000      	b.n	80041b8 <HAL_DMA_IRQHandler+0xb0>
+ 80041b6:	2304      	movs	r3, #4
+ 80041b8:	4a55      	ldr	r2, [pc, #340]	@ (8004310 <HAL_DMA_IRQHandler+0x208>)
+ 80041ba:	6053      	str	r3, [r2, #4]
+
+    /* DMA peripheral state is not updated in Half Transfer */
+    /* but in Transfer Complete case */
+
+    if(hdma->XferHalfCpltCallback != NULL)
+ 80041bc:	687b      	ldr	r3, [r7, #4]
+ 80041be:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80041c0:	2b00      	cmp	r3, #0
+ 80041c2:	f000 8094 	beq.w	80042ee <HAL_DMA_IRQHandler+0x1e6>
+    {
+      /* Half transfer callback */
+      hdma->XferHalfCpltCallback(hdma);
+ 80041c6:	687b      	ldr	r3, [r7, #4]
+ 80041c8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80041ca:	6878      	ldr	r0, [r7, #4]
+ 80041cc:	4798      	blx	r3
+    if(hdma->XferHalfCpltCallback != NULL)
+ 80041ce:	e08e      	b.n	80042ee <HAL_DMA_IRQHandler+0x1e6>
+    }
+  }
+
+  /* Transfer Complete Interrupt management ***********************************/
+  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
+ 80041d0:	687b      	ldr	r3, [r7, #4]
+ 80041d2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80041d4:	2202      	movs	r2, #2
+ 80041d6:	409a      	lsls	r2, r3
+ 80041d8:	68fb      	ldr	r3, [r7, #12]
+ 80041da:	4013      	ands	r3, r2
+ 80041dc:	2b00      	cmp	r3, #0
+ 80041de:	d056      	beq.n	800428e <HAL_DMA_IRQHandler+0x186>
+ 80041e0:	68bb      	ldr	r3, [r7, #8]
+ 80041e2:	f003 0302 	and.w	r3, r3, #2
+ 80041e6:	2b00      	cmp	r3, #0
+ 80041e8:	d051      	beq.n	800428e <HAL_DMA_IRQHandler+0x186>
+  {
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 80041ea:	687b      	ldr	r3, [r7, #4]
+ 80041ec:	681b      	ldr	r3, [r3, #0]
+ 80041ee:	681b      	ldr	r3, [r3, #0]
+ 80041f0:	f003 0320 	and.w	r3, r3, #32
+ 80041f4:	2b00      	cmp	r3, #0
+ 80041f6:	d10b      	bne.n	8004210 <HAL_DMA_IRQHandler+0x108>
+    {
+      /* Disable the transfer complete and error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
+ 80041f8:	687b      	ldr	r3, [r7, #4]
+ 80041fa:	681b      	ldr	r3, [r3, #0]
+ 80041fc:	681a      	ldr	r2, [r3, #0]
+ 80041fe:	687b      	ldr	r3, [r7, #4]
+ 8004200:	681b      	ldr	r3, [r3, #0]
+ 8004202:	f022 020a 	bic.w	r2, r2, #10
+ 8004206:	601a      	str	r2, [r3, #0]
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+ 8004208:	687b      	ldr	r3, [r7, #4]
+ 800420a:	2201      	movs	r2, #1
+ 800420c:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+    }
+    /* Clear the transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ 8004210:	687b      	ldr	r3, [r7, #4]
+ 8004212:	681b      	ldr	r3, [r3, #0]
+ 8004214:	4a38      	ldr	r2, [pc, #224]	@ (80042f8 <HAL_DMA_IRQHandler+0x1f0>)
+ 8004216:	4293      	cmp	r3, r2
+ 8004218:	d029      	beq.n	800426e <HAL_DMA_IRQHandler+0x166>
+ 800421a:	687b      	ldr	r3, [r7, #4]
+ 800421c:	681b      	ldr	r3, [r3, #0]
+ 800421e:	4a37      	ldr	r2, [pc, #220]	@ (80042fc <HAL_DMA_IRQHandler+0x1f4>)
+ 8004220:	4293      	cmp	r3, r2
+ 8004222:	d022      	beq.n	800426a <HAL_DMA_IRQHandler+0x162>
+ 8004224:	687b      	ldr	r3, [r7, #4]
+ 8004226:	681b      	ldr	r3, [r3, #0]
+ 8004228:	4a35      	ldr	r2, [pc, #212]	@ (8004300 <HAL_DMA_IRQHandler+0x1f8>)
+ 800422a:	4293      	cmp	r3, r2
+ 800422c:	d01a      	beq.n	8004264 <HAL_DMA_IRQHandler+0x15c>
+ 800422e:	687b      	ldr	r3, [r7, #4]
+ 8004230:	681b      	ldr	r3, [r3, #0]
+ 8004232:	4a34      	ldr	r2, [pc, #208]	@ (8004304 <HAL_DMA_IRQHandler+0x1fc>)
+ 8004234:	4293      	cmp	r3, r2
+ 8004236:	d012      	beq.n	800425e <HAL_DMA_IRQHandler+0x156>
+ 8004238:	687b      	ldr	r3, [r7, #4]
+ 800423a:	681b      	ldr	r3, [r3, #0]
+ 800423c:	4a32      	ldr	r2, [pc, #200]	@ (8004308 <HAL_DMA_IRQHandler+0x200>)
+ 800423e:	4293      	cmp	r3, r2
+ 8004240:	d00a      	beq.n	8004258 <HAL_DMA_IRQHandler+0x150>
+ 8004242:	687b      	ldr	r3, [r7, #4]
+ 8004244:	681b      	ldr	r3, [r3, #0]
+ 8004246:	4a31      	ldr	r2, [pc, #196]	@ (800430c <HAL_DMA_IRQHandler+0x204>)
+ 8004248:	4293      	cmp	r3, r2
+ 800424a:	d102      	bne.n	8004252 <HAL_DMA_IRQHandler+0x14a>
+ 800424c:	f44f 1300 	mov.w	r3, #2097152	@ 0x200000
+ 8004250:	e00e      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 8004252:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
+ 8004256:	e00b      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 8004258:	f44f 3300 	mov.w	r3, #131072	@ 0x20000
+ 800425c:	e008      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 800425e:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
+ 8004262:	e005      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 8004264:	f44f 7300 	mov.w	r3, #512	@ 0x200
+ 8004268:	e002      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 800426a:	2320      	movs	r3, #32
+ 800426c:	e000      	b.n	8004270 <HAL_DMA_IRQHandler+0x168>
+ 800426e:	2302      	movs	r3, #2
+ 8004270:	4a27      	ldr	r2, [pc, #156]	@ (8004310 <HAL_DMA_IRQHandler+0x208>)
+ 8004272:	6053      	str	r3, [r2, #4]
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8004274:	687b      	ldr	r3, [r7, #4]
+ 8004276:	2200      	movs	r2, #0
+ 8004278:	f883 2020 	strb.w	r2, [r3, #32]
+
+    if(hdma->XferCpltCallback != NULL)
+ 800427c:	687b      	ldr	r3, [r7, #4]
+ 800427e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8004280:	2b00      	cmp	r3, #0
+ 8004282:	d034      	beq.n	80042ee <HAL_DMA_IRQHandler+0x1e6>
+    {
+      /* Transfer complete callback */
+      hdma->XferCpltCallback(hdma);
+ 8004284:	687b      	ldr	r3, [r7, #4]
+ 8004286:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8004288:	6878      	ldr	r0, [r7, #4]
+ 800428a:	4798      	blx	r3
+    if(hdma->XferCpltCallback != NULL)
+ 800428c:	e02f      	b.n	80042ee <HAL_DMA_IRQHandler+0x1e6>
+    }
+  }
+
+  /* Transfer Error Interrupt management **************************************/
+  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+ 800428e:	687b      	ldr	r3, [r7, #4]
+ 8004290:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8004292:	2208      	movs	r2, #8
+ 8004294:	409a      	lsls	r2, r3
+ 8004296:	68fb      	ldr	r3, [r7, #12]
+ 8004298:	4013      	ands	r3, r2
+ 800429a:	2b00      	cmp	r3, #0
+ 800429c:	d028      	beq.n	80042f0 <HAL_DMA_IRQHandler+0x1e8>
+ 800429e:	68bb      	ldr	r3, [r7, #8]
+ 80042a0:	f003 0308 	and.w	r3, r3, #8
+ 80042a4:	2b00      	cmp	r3, #0
+ 80042a6:	d023      	beq.n	80042f0 <HAL_DMA_IRQHandler+0x1e8>
+  {
+    /* When a DMA transfer error occurs */
+    /* A hardware clear of its EN bits is performed */
+    /* Disable ALL DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 80042a8:	687b      	ldr	r3, [r7, #4]
+ 80042aa:	681b      	ldr	r3, [r3, #0]
+ 80042ac:	681a      	ldr	r2, [r3, #0]
+ 80042ae:	687b      	ldr	r3, [r7, #4]
+ 80042b0:	681b      	ldr	r3, [r3, #0]
+ 80042b2:	f022 020e 	bic.w	r2, r2, #14
+ 80042b6:	601a      	str	r2, [r3, #0]
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+ 80042b8:	687b      	ldr	r3, [r7, #4]
+ 80042ba:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 80042bc:	687b      	ldr	r3, [r7, #4]
+ 80042be:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80042c0:	2101      	movs	r1, #1
+ 80042c2:	fa01 f202 	lsl.w	r2, r1, r2
+ 80042c6:	605a      	str	r2, [r3, #4]
+
+    /* Update error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 80042c8:	687b      	ldr	r3, [r7, #4]
+ 80042ca:	2201      	movs	r2, #1
+ 80042cc:	639a      	str	r2, [r3, #56]	@ 0x38
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 80042ce:	687b      	ldr	r3, [r7, #4]
+ 80042d0:	2201      	movs	r2, #1
+ 80042d2:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 80042d6:	687b      	ldr	r3, [r7, #4]
+ 80042d8:	2200      	movs	r2, #0
+ 80042da:	f883 2020 	strb.w	r2, [r3, #32]
+
+    if (hdma->XferErrorCallback != NULL)
+ 80042de:	687b      	ldr	r3, [r7, #4]
+ 80042e0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80042e2:	2b00      	cmp	r3, #0
+ 80042e4:	d004      	beq.n	80042f0 <HAL_DMA_IRQHandler+0x1e8>
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+ 80042e6:	687b      	ldr	r3, [r7, #4]
+ 80042e8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80042ea:	6878      	ldr	r0, [r7, #4]
+ 80042ec:	4798      	blx	r3
+    }
+  }
+  return;
+ 80042ee:	bf00      	nop
+ 80042f0:	bf00      	nop
+}
+ 80042f2:	3710      	adds	r7, #16
+ 80042f4:	46bd      	mov	sp, r7
+ 80042f6:	bd80      	pop	{r7, pc}
+ 80042f8:	40020008 	.word	0x40020008
+ 80042fc:	4002001c 	.word	0x4002001c
+ 8004300:	40020030 	.word	0x40020030
+ 8004304:	40020044 	.word	0x40020044
+ 8004308:	40020058 	.word	0x40020058
+ 800430c:	4002006c 	.word	0x4002006c
+ 8004310:	40020000 	.word	0x40020000
+
+08004314 <DMA_SetConfig>:
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ 8004314:	b480      	push	{r7}
+ 8004316:	b085      	sub	sp, #20
+ 8004318:	af00      	add	r7, sp, #0
+ 800431a:	60f8      	str	r0, [r7, #12]
+ 800431c:	60b9      	str	r1, [r7, #8]
+ 800431e:	607a      	str	r2, [r7, #4]
+ 8004320:	603b      	str	r3, [r7, #0]
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+ 8004322:	68fb      	ldr	r3, [r7, #12]
+ 8004324:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 8004326:	68fb      	ldr	r3, [r7, #12]
+ 8004328:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 800432a:	2101      	movs	r1, #1
+ 800432c:	fa01 f202 	lsl.w	r2, r1, r2
+ 8004330:	605a      	str	r2, [r3, #4]
+
+  /* Configure DMA Channel data length */
+  hdma->Instance->CNDTR = DataLength;
+ 8004332:	68fb      	ldr	r3, [r7, #12]
+ 8004334:	681b      	ldr	r3, [r3, #0]
+ 8004336:	683a      	ldr	r2, [r7, #0]
+ 8004338:	605a      	str	r2, [r3, #4]
+
+  /* Memory to Peripheral */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ 800433a:	68fb      	ldr	r3, [r7, #12]
+ 800433c:	685b      	ldr	r3, [r3, #4]
+ 800433e:	2b10      	cmp	r3, #16
+ 8004340:	d108      	bne.n	8004354 <DMA_SetConfig+0x40>
+  {
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CPAR = DstAddress;
+ 8004342:	68fb      	ldr	r3, [r7, #12]
+ 8004344:	681b      	ldr	r3, [r3, #0]
+ 8004346:	687a      	ldr	r2, [r7, #4]
+ 8004348:	609a      	str	r2, [r3, #8]
+
+    /* Configure DMA Channel source address */
+    hdma->Instance->CMAR = SrcAddress;
+ 800434a:	68fb      	ldr	r3, [r7, #12]
+ 800434c:	681b      	ldr	r3, [r3, #0]
+ 800434e:	68ba      	ldr	r2, [r7, #8]
+ 8004350:	60da      	str	r2, [r3, #12]
+    hdma->Instance->CPAR = SrcAddress;
+
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CMAR = DstAddress;
+  }
+}
+ 8004352:	e007      	b.n	8004364 <DMA_SetConfig+0x50>
+    hdma->Instance->CPAR = SrcAddress;
+ 8004354:	68fb      	ldr	r3, [r7, #12]
+ 8004356:	681b      	ldr	r3, [r3, #0]
+ 8004358:	68ba      	ldr	r2, [r7, #8]
+ 800435a:	609a      	str	r2, [r3, #8]
+    hdma->Instance->CMAR = DstAddress;
+ 800435c:	68fb      	ldr	r3, [r7, #12]
+ 800435e:	681b      	ldr	r3, [r3, #0]
+ 8004360:	687a      	ldr	r2, [r7, #4]
+ 8004362:	60da      	str	r2, [r3, #12]
+}
+ 8004364:	bf00      	nop
+ 8004366:	3714      	adds	r7, #20
+ 8004368:	46bd      	mov	sp, r7
+ 800436a:	bc80      	pop	{r7}
+ 800436c:	4770      	bx	lr
+	...
+
+08004370 <HAL_FLASH_Program>:
+  * @param  Data:         Specifies the data to be programmed
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ 8004370:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8004372:	b087      	sub	sp, #28
+ 8004374:	af00      	add	r7, sp, #0
+ 8004376:	60f8      	str	r0, [r7, #12]
+ 8004378:	60b9      	str	r1, [r7, #8]
+ 800437a:	e9c7 2300 	strd	r2, r3, [r7]
+  HAL_StatusTypeDef status = HAL_ERROR;
+ 800437e:	2301      	movs	r3, #1
+ 8004380:	75fb      	strb	r3, [r7, #23]
+  uint8_t index = 0;
+ 8004382:	2300      	movs	r3, #0
+ 8004384:	75bb      	strb	r3, [r7, #22]
+  uint8_t nbiterations = 0;
+ 8004386:	2300      	movs	r3, #0
+ 8004388:	757b      	strb	r3, [r7, #21]
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+ 800438a:	4b2f      	ldr	r3, [pc, #188]	@ (8004448 <HAL_FLASH_Program+0xd8>)
+ 800438c:	7e1b      	ldrb	r3, [r3, #24]
+ 800438e:	2b01      	cmp	r3, #1
+ 8004390:	d101      	bne.n	8004396 <HAL_FLASH_Program+0x26>
+ 8004392:	2302      	movs	r3, #2
+ 8004394:	e054      	b.n	8004440 <HAL_FLASH_Program+0xd0>
+ 8004396:	4b2c      	ldr	r3, [pc, #176]	@ (8004448 <HAL_FLASH_Program+0xd8>)
+ 8004398:	2201      	movs	r2, #1
+ 800439a:	761a      	strb	r2, [r3, #24]
+#if defined(FLASH_BANK2_END)
+  if(Address <= FLASH_BANK1_END)
+  {
+#endif /* FLASH_BANK2_END */
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ 800439c:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 80043a0:	f000 f8a8 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 80043a4:	4603      	mov	r3, r0
+ 80043a6:	75fb      	strb	r3, [r7, #23]
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
+  }
+#endif /* FLASH_BANK2_END */
+  
+  if(status == HAL_OK)
+ 80043a8:	7dfb      	ldrb	r3, [r7, #23]
+ 80043aa:	2b00      	cmp	r3, #0
+ 80043ac:	d144      	bne.n	8004438 <HAL_FLASH_Program+0xc8>
+  {
+    if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ 80043ae:	68fb      	ldr	r3, [r7, #12]
+ 80043b0:	2b01      	cmp	r3, #1
+ 80043b2:	d102      	bne.n	80043ba <HAL_FLASH_Program+0x4a>
+    {
+      /* Program halfword (16-bit) at a specified address. */
+      nbiterations = 1U;
+ 80043b4:	2301      	movs	r3, #1
+ 80043b6:	757b      	strb	r3, [r7, #21]
+ 80043b8:	e007      	b.n	80043ca <HAL_FLASH_Program+0x5a>
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ 80043ba:	68fb      	ldr	r3, [r7, #12]
+ 80043bc:	2b02      	cmp	r3, #2
+ 80043be:	d102      	bne.n	80043c6 <HAL_FLASH_Program+0x56>
+    {
+      /* Program word (32-bit = 2*16-bit) at a specified address. */
+      nbiterations = 2U;
+ 80043c0:	2302      	movs	r3, #2
+ 80043c2:	757b      	strb	r3, [r7, #21]
+ 80043c4:	e001      	b.n	80043ca <HAL_FLASH_Program+0x5a>
+    }
+    else
+    {
+      /* Program double word (64-bit = 4*16-bit) at a specified address. */
+      nbiterations = 4U;
+ 80043c6:	2304      	movs	r3, #4
+ 80043c8:	757b      	strb	r3, [r7, #21]
+    }
+
+    for (index = 0U; index < nbiterations; index++)
+ 80043ca:	2300      	movs	r3, #0
+ 80043cc:	75bb      	strb	r3, [r7, #22]
+ 80043ce:	e02d      	b.n	800442c <HAL_FLASH_Program+0xbc>
+    {
+      FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
+ 80043d0:	7dbb      	ldrb	r3, [r7, #22]
+ 80043d2:	005a      	lsls	r2, r3, #1
+ 80043d4:	68bb      	ldr	r3, [r7, #8]
+ 80043d6:	eb02 0c03 	add.w	ip, r2, r3
+ 80043da:	7dbb      	ldrb	r3, [r7, #22]
+ 80043dc:	0119      	lsls	r1, r3, #4
+ 80043de:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 80043e2:	f1c1 0620 	rsb	r6, r1, #32
+ 80043e6:	f1a1 0020 	sub.w	r0, r1, #32
+ 80043ea:	fa22 f401 	lsr.w	r4, r2, r1
+ 80043ee:	fa03 f606 	lsl.w	r6, r3, r6
+ 80043f2:	4334      	orrs	r4, r6
+ 80043f4:	fa23 f000 	lsr.w	r0, r3, r0
+ 80043f8:	4304      	orrs	r4, r0
+ 80043fa:	fa23 f501 	lsr.w	r5, r3, r1
+ 80043fe:	b2a3      	uxth	r3, r4
+ 8004400:	4619      	mov	r1, r3
+ 8004402:	4660      	mov	r0, ip
+ 8004404:	f000 f85a 	bl	80044bc <FLASH_Program_HalfWord>
+#if defined(FLASH_BANK2_END)
+      if(Address <= FLASH_BANK1_END)
+      {
+#endif /* FLASH_BANK2_END */
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ 8004408:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 800440c:	f000 f872 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 8004410:	4603      	mov	r3, r0
+ 8004412:	75fb      	strb	r3, [r7, #23]
+    
+        /* If the program operation is completed, disable the PG Bit */
+        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+ 8004414:	4b0d      	ldr	r3, [pc, #52]	@ (800444c <HAL_FLASH_Program+0xdc>)
+ 8004416:	691b      	ldr	r3, [r3, #16]
+ 8004418:	4a0c      	ldr	r2, [pc, #48]	@ (800444c <HAL_FLASH_Program+0xdc>)
+ 800441a:	f023 0301 	bic.w	r3, r3, #1
+ 800441e:	6113      	str	r3, [r2, #16]
+        /* If the program operation is completed, disable the PG Bit */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+      }
+#endif /* FLASH_BANK2_END */
+      /* In case of error, stop programation procedure */
+      if (status != HAL_OK)
+ 8004420:	7dfb      	ldrb	r3, [r7, #23]
+ 8004422:	2b00      	cmp	r3, #0
+ 8004424:	d107      	bne.n	8004436 <HAL_FLASH_Program+0xc6>
+    for (index = 0U; index < nbiterations; index++)
+ 8004426:	7dbb      	ldrb	r3, [r7, #22]
+ 8004428:	3301      	adds	r3, #1
+ 800442a:	75bb      	strb	r3, [r7, #22]
+ 800442c:	7dba      	ldrb	r2, [r7, #22]
+ 800442e:	7d7b      	ldrb	r3, [r7, #21]
+ 8004430:	429a      	cmp	r2, r3
+ 8004432:	d3cd      	bcc.n	80043d0 <HAL_FLASH_Program+0x60>
+ 8004434:	e000      	b.n	8004438 <HAL_FLASH_Program+0xc8>
+      {
+        break;
+ 8004436:	bf00      	nop
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+ 8004438:	4b03      	ldr	r3, [pc, #12]	@ (8004448 <HAL_FLASH_Program+0xd8>)
+ 800443a:	2200      	movs	r2, #0
+ 800443c:	761a      	strb	r2, [r3, #24]
+
+  return status;
+ 800443e:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8004440:	4618      	mov	r0, r3
+ 8004442:	371c      	adds	r7, #28
+ 8004444:	46bd      	mov	sp, r7
+ 8004446:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 8004448:	200007b8 	.word	0x200007b8
+ 800444c:	40022000 	.word	0x40022000
+
+08004450 <HAL_FLASH_Unlock>:
+/**
+  * @brief  Unlock the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ 8004450:	b480      	push	{r7}
+ 8004452:	b083      	sub	sp, #12
+ 8004454:	af00      	add	r7, sp, #0
+  HAL_StatusTypeDef status = HAL_OK;
+ 8004456:	2300      	movs	r3, #0
+ 8004458:	71fb      	strb	r3, [r7, #7]
+
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ 800445a:	4b0d      	ldr	r3, [pc, #52]	@ (8004490 <HAL_FLASH_Unlock+0x40>)
+ 800445c:	691b      	ldr	r3, [r3, #16]
+ 800445e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 8004462:	2b00      	cmp	r3, #0
+ 8004464:	d00d      	beq.n	8004482 <HAL_FLASH_Unlock+0x32>
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ 8004466:	4b0a      	ldr	r3, [pc, #40]	@ (8004490 <HAL_FLASH_Unlock+0x40>)
+ 8004468:	4a0a      	ldr	r2, [pc, #40]	@ (8004494 <HAL_FLASH_Unlock+0x44>)
+ 800446a:	605a      	str	r2, [r3, #4]
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ 800446c:	4b08      	ldr	r3, [pc, #32]	@ (8004490 <HAL_FLASH_Unlock+0x40>)
+ 800446e:	4a0a      	ldr	r2, [pc, #40]	@ (8004498 <HAL_FLASH_Unlock+0x48>)
+ 8004470:	605a      	str	r2, [r3, #4]
+
+    /* Verify Flash is unlocked */
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ 8004472:	4b07      	ldr	r3, [pc, #28]	@ (8004490 <HAL_FLASH_Unlock+0x40>)
+ 8004474:	691b      	ldr	r3, [r3, #16]
+ 8004476:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 800447a:	2b00      	cmp	r3, #0
+ 800447c:	d001      	beq.n	8004482 <HAL_FLASH_Unlock+0x32>
+    {
+      status = HAL_ERROR;
+ 800447e:	2301      	movs	r3, #1
+ 8004480:	71fb      	strb	r3, [r7, #7]
+      status = HAL_ERROR;
+    }
+  }
+#endif /* FLASH_BANK2_END */
+
+  return status;
+ 8004482:	79fb      	ldrb	r3, [r7, #7]
+}
+ 8004484:	4618      	mov	r0, r3
+ 8004486:	370c      	adds	r7, #12
+ 8004488:	46bd      	mov	sp, r7
+ 800448a:	bc80      	pop	{r7}
+ 800448c:	4770      	bx	lr
+ 800448e:	bf00      	nop
+ 8004490:	40022000 	.word	0x40022000
+ 8004494:	45670123 	.word	0x45670123
+ 8004498:	cdef89ab 	.word	0xcdef89ab
+
+0800449c <HAL_FLASH_Lock>:
+/**
+  * @brief  Locks the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ 800449c:	b480      	push	{r7}
+ 800449e:	af00      	add	r7, sp, #0
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+ 80044a0:	4b05      	ldr	r3, [pc, #20]	@ (80044b8 <HAL_FLASH_Lock+0x1c>)
+ 80044a2:	691b      	ldr	r3, [r3, #16]
+ 80044a4:	4a04      	ldr	r2, [pc, #16]	@ (80044b8 <HAL_FLASH_Lock+0x1c>)
+ 80044a6:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 80044aa:	6113      	str	r3, [r2, #16]
+#if defined(FLASH_BANK2_END)
+  /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
+
+#endif /* FLASH_BANK2_END */
+  return HAL_OK;  
+ 80044ac:	2300      	movs	r3, #0
+}
+ 80044ae:	4618      	mov	r0, r3
+ 80044b0:	46bd      	mov	sp, r7
+ 80044b2:	bc80      	pop	{r7}
+ 80044b4:	4770      	bx	lr
+ 80044b6:	bf00      	nop
+ 80044b8:	40022000 	.word	0x40022000
+
+080044bc <FLASH_Program_HalfWord>:
+  * @param  Address specify the address to be programmed.
+  * @param  Data    specify the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ 80044bc:	b480      	push	{r7}
+ 80044be:	b083      	sub	sp, #12
+ 80044c0:	af00      	add	r7, sp, #0
+ 80044c2:	6078      	str	r0, [r7, #4]
+ 80044c4:	460b      	mov	r3, r1
+ 80044c6:	807b      	strh	r3, [r7, #2]
+  /* Clean the error context */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 80044c8:	4b08      	ldr	r3, [pc, #32]	@ (80044ec <FLASH_Program_HalfWord+0x30>)
+ 80044ca:	2200      	movs	r2, #0
+ 80044cc:	61da      	str	r2, [r3, #28]
+#if defined(FLASH_BANK2_END)
+  if(Address <= FLASH_BANK1_END)
+  {
+#endif /* FLASH_BANK2_END */
+    /* Proceed to program the new data */
+    SET_BIT(FLASH->CR, FLASH_CR_PG);
+ 80044ce:	4b08      	ldr	r3, [pc, #32]	@ (80044f0 <FLASH_Program_HalfWord+0x34>)
+ 80044d0:	691b      	ldr	r3, [r3, #16]
+ 80044d2:	4a07      	ldr	r2, [pc, #28]	@ (80044f0 <FLASH_Program_HalfWord+0x34>)
+ 80044d4:	f043 0301 	orr.w	r3, r3, #1
+ 80044d8:	6113      	str	r3, [r2, #16]
+    SET_BIT(FLASH->CR2, FLASH_CR2_PG);
+  }
+#endif /* FLASH_BANK2_END */
+
+  /* Write data in the address */
+  *(__IO uint16_t*)Address = Data;
+ 80044da:	687b      	ldr	r3, [r7, #4]
+ 80044dc:	887a      	ldrh	r2, [r7, #2]
+ 80044de:	801a      	strh	r2, [r3, #0]
+}
+ 80044e0:	bf00      	nop
+ 80044e2:	370c      	adds	r7, #12
+ 80044e4:	46bd      	mov	sp, r7
+ 80044e6:	bc80      	pop	{r7}
+ 80044e8:	4770      	bx	lr
+ 80044ea:	bf00      	nop
+ 80044ec:	200007b8 	.word	0x200007b8
+ 80044f0:	40022000 	.word	0x40022000
+
+080044f4 <FLASH_WaitForLastOperation>:
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout  maximum flash operation timeout
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ 80044f4:	b580      	push	{r7, lr}
+ 80044f6:	b084      	sub	sp, #16
+ 80044f8:	af00      	add	r7, sp, #0
+ 80044fa:	6078      	str	r0, [r7, #4]
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+     
+  uint32_t tickstart = HAL_GetTick();
+ 80044fc:	f7fe feea 	bl	80032d4 <HAL_GetTick>
+ 8004500:	60f8      	str	r0, [r7, #12]
+     
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
+ 8004502:	e010      	b.n	8004526 <FLASH_WaitForLastOperation+0x32>
+  { 
+    if (Timeout != HAL_MAX_DELAY)
+ 8004504:	687b      	ldr	r3, [r7, #4]
+ 8004506:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800450a:	d00c      	beq.n	8004526 <FLASH_WaitForLastOperation+0x32>
+    {
+      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ 800450c:	687b      	ldr	r3, [r7, #4]
+ 800450e:	2b00      	cmp	r3, #0
+ 8004510:	d007      	beq.n	8004522 <FLASH_WaitForLastOperation+0x2e>
+ 8004512:	f7fe fedf 	bl	80032d4 <HAL_GetTick>
+ 8004516:	4602      	mov	r2, r0
+ 8004518:	68fb      	ldr	r3, [r7, #12]
+ 800451a:	1ad3      	subs	r3, r2, r3
+ 800451c:	687a      	ldr	r2, [r7, #4]
+ 800451e:	429a      	cmp	r2, r3
+ 8004520:	d201      	bcs.n	8004526 <FLASH_WaitForLastOperation+0x32>
+      {
+        return HAL_TIMEOUT;
+ 8004522:	2303      	movs	r3, #3
+ 8004524:	e025      	b.n	8004572 <FLASH_WaitForLastOperation+0x7e>
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
+ 8004526:	4b15      	ldr	r3, [pc, #84]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 8004528:	68db      	ldr	r3, [r3, #12]
+ 800452a:	f003 0301 	and.w	r3, r3, #1
+ 800452e:	2b00      	cmp	r3, #0
+ 8004530:	d1e8      	bne.n	8004504 <FLASH_WaitForLastOperation+0x10>
+      }
+    }
+  }
+  
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ 8004532:	4b12      	ldr	r3, [pc, #72]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 8004534:	68db      	ldr	r3, [r3, #12]
+ 8004536:	f003 0320 	and.w	r3, r3, #32
+ 800453a:	2b00      	cmp	r3, #0
+ 800453c:	d002      	beq.n	8004544 <FLASH_WaitForLastOperation+0x50>
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ 800453e:	4b0f      	ldr	r3, [pc, #60]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 8004540:	2220      	movs	r2, #32
+ 8004542:	60da      	str	r2, [r3, #12]
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
+ 8004544:	4b0d      	ldr	r3, [pc, #52]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 8004546:	68db      	ldr	r3, [r3, #12]
+ 8004548:	f003 0310 	and.w	r3, r3, #16
+ 800454c:	2b00      	cmp	r3, #0
+ 800454e:	d10b      	bne.n	8004568 <FLASH_WaitForLastOperation+0x74>
+     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
+ 8004550:	4b0a      	ldr	r3, [pc, #40]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 8004552:	69db      	ldr	r3, [r3, #28]
+ 8004554:	f003 0301 	and.w	r3, r3, #1
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
+ 8004558:	2b00      	cmp	r3, #0
+ 800455a:	d105      	bne.n	8004568 <FLASH_WaitForLastOperation+0x74>
+     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ 800455c:	4b07      	ldr	r3, [pc, #28]	@ (800457c <FLASH_WaitForLastOperation+0x88>)
+ 800455e:	68db      	ldr	r3, [r3, #12]
+ 8004560:	f003 0304 	and.w	r3, r3, #4
+     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
+ 8004564:	2b00      	cmp	r3, #0
+ 8004566:	d003      	beq.n	8004570 <FLASH_WaitForLastOperation+0x7c>
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+ 8004568:	f000 f80a 	bl	8004580 <FLASH_SetErrorCode>
+    return HAL_ERROR;
+ 800456c:	2301      	movs	r3, #1
+ 800456e:	e000      	b.n	8004572 <FLASH_WaitForLastOperation+0x7e>
+  }
+
+  /* There is no error flag set */
+  return HAL_OK;
+ 8004570:	2300      	movs	r3, #0
+}
+ 8004572:	4618      	mov	r0, r3
+ 8004574:	3710      	adds	r7, #16
+ 8004576:	46bd      	mov	sp, r7
+ 8004578:	bd80      	pop	{r7, pc}
+ 800457a:	bf00      	nop
+ 800457c:	40022000 	.word	0x40022000
+
+08004580 <FLASH_SetErrorCode>:
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{
+ 8004580:	b480      	push	{r7}
+ 8004582:	b083      	sub	sp, #12
+ 8004584:	af00      	add	r7, sp, #0
+  uint32_t flags = 0U;
+ 8004586:	2300      	movs	r3, #0
+ 8004588:	607b      	str	r3, [r7, #4]
+  
+#if defined(FLASH_BANK2_END)
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
+#else
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+ 800458a:	4b23      	ldr	r3, [pc, #140]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 800458c:	68db      	ldr	r3, [r3, #12]
+ 800458e:	f003 0310 	and.w	r3, r3, #16
+ 8004592:	2b00      	cmp	r3, #0
+ 8004594:	d009      	beq.n	80045aa <FLASH_SetErrorCode+0x2a>
+#endif /* FLASH_BANK2_END */
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ 8004596:	4b21      	ldr	r3, [pc, #132]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 8004598:	69db      	ldr	r3, [r3, #28]
+ 800459a:	f043 0302 	orr.w	r3, r3, #2
+ 800459e:	4a1f      	ldr	r2, [pc, #124]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 80045a0:	61d3      	str	r3, [r2, #28]
+#if defined(FLASH_BANK2_END)
+    flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
+#else
+    flags |= FLASH_FLAG_WRPERR;
+ 80045a2:	687b      	ldr	r3, [r7, #4]
+ 80045a4:	f043 0310 	orr.w	r3, r3, #16
+ 80045a8:	607b      	str	r3, [r7, #4]
+#endif /* FLASH_BANK2_END */
+  }
+#if defined(FLASH_BANK2_END)
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+#else
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ 80045aa:	4b1b      	ldr	r3, [pc, #108]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045ac:	68db      	ldr	r3, [r3, #12]
+ 80045ae:	f003 0304 	and.w	r3, r3, #4
+ 80045b2:	2b00      	cmp	r3, #0
+ 80045b4:	d009      	beq.n	80045ca <FLASH_SetErrorCode+0x4a>
+#endif /* FLASH_BANK2_END */
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ 80045b6:	4b19      	ldr	r3, [pc, #100]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 80045b8:	69db      	ldr	r3, [r3, #28]
+ 80045ba:	f043 0301 	orr.w	r3, r3, #1
+ 80045be:	4a17      	ldr	r2, [pc, #92]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 80045c0:	61d3      	str	r3, [r2, #28]
+#if defined(FLASH_BANK2_END)
+    flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
+#else
+    flags |= FLASH_FLAG_PGERR;
+ 80045c2:	687b      	ldr	r3, [r7, #4]
+ 80045c4:	f043 0304 	orr.w	r3, r3, #4
+ 80045c8:	607b      	str	r3, [r7, #4]
+#endif /* FLASH_BANK2_END */
+  }
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+ 80045ca:	4b13      	ldr	r3, [pc, #76]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045cc:	69db      	ldr	r3, [r3, #28]
+ 80045ce:	f003 0301 	and.w	r3, r3, #1
+ 80045d2:	2b00      	cmp	r3, #0
+ 80045d4:	d00b      	beq.n	80045ee <FLASH_SetErrorCode+0x6e>
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+ 80045d6:	4b11      	ldr	r3, [pc, #68]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 80045d8:	69db      	ldr	r3, [r3, #28]
+ 80045da:	f043 0304 	orr.w	r3, r3, #4
+ 80045de:	4a0f      	ldr	r2, [pc, #60]	@ (800461c <FLASH_SetErrorCode+0x9c>)
+ 80045e0:	61d3      	str	r3, [r2, #28]
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+ 80045e2:	4b0d      	ldr	r3, [pc, #52]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045e4:	69db      	ldr	r3, [r3, #28]
+ 80045e6:	4a0c      	ldr	r2, [pc, #48]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045e8:	f023 0301 	bic.w	r3, r3, #1
+ 80045ec:	61d3      	str	r3, [r2, #28]
+  }
+
+  /* Clear FLASH error pending bits */
+  __HAL_FLASH_CLEAR_FLAG(flags);
+ 80045ee:	687b      	ldr	r3, [r7, #4]
+ 80045f0:	f240 1201 	movw	r2, #257	@ 0x101
+ 80045f4:	4293      	cmp	r3, r2
+ 80045f6:	d106      	bne.n	8004606 <FLASH_SetErrorCode+0x86>
+ 80045f8:	4b07      	ldr	r3, [pc, #28]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045fa:	69db      	ldr	r3, [r3, #28]
+ 80045fc:	4a06      	ldr	r2, [pc, #24]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 80045fe:	f023 0301 	bic.w	r3, r3, #1
+ 8004602:	61d3      	str	r3, [r2, #28]
+}  
+ 8004604:	e002      	b.n	800460c <FLASH_SetErrorCode+0x8c>
+  __HAL_FLASH_CLEAR_FLAG(flags);
+ 8004606:	4a04      	ldr	r2, [pc, #16]	@ (8004618 <FLASH_SetErrorCode+0x98>)
+ 8004608:	687b      	ldr	r3, [r7, #4]
+ 800460a:	60d3      	str	r3, [r2, #12]
+}  
+ 800460c:	bf00      	nop
+ 800460e:	370c      	adds	r7, #12
+ 8004610:	46bd      	mov	sp, r7
+ 8004612:	bc80      	pop	{r7}
+ 8004614:	4770      	bx	lr
+ 8004616:	bf00      	nop
+ 8004618:	40022000 	.word	0x40022000
+ 800461c:	200007b8 	.word	0x200007b8
+
+08004620 <HAL_FLASHEx_Erase>:
+  *         (0xFFFFFFFF means that all the pages have been correctly erased)
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ 8004620:	b580      	push	{r7, lr}
+ 8004622:	b084      	sub	sp, #16
+ 8004624:	af00      	add	r7, sp, #0
+ 8004626:	6078      	str	r0, [r7, #4]
+ 8004628:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef status = HAL_ERROR;
+ 800462a:	2301      	movs	r3, #1
+ 800462c:	73fb      	strb	r3, [r7, #15]
+  uint32_t address = 0U;
+ 800462e:	2300      	movs	r3, #0
+ 8004630:	60bb      	str	r3, [r7, #8]
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+ 8004632:	4b2f      	ldr	r3, [pc, #188]	@ (80046f0 <HAL_FLASHEx_Erase+0xd0>)
+ 8004634:	7e1b      	ldrb	r3, [r3, #24]
+ 8004636:	2b01      	cmp	r3, #1
+ 8004638:	d101      	bne.n	800463e <HAL_FLASHEx_Erase+0x1e>
+ 800463a:	2302      	movs	r3, #2
+ 800463c:	e053      	b.n	80046e6 <HAL_FLASHEx_Erase+0xc6>
+ 800463e:	4b2c      	ldr	r3, [pc, #176]	@ (80046f0 <HAL_FLASHEx_Erase+0xd0>)
+ 8004640:	2201      	movs	r2, #1
+ 8004642:	761a      	strb	r2, [r3, #24]
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ 8004644:	687b      	ldr	r3, [r7, #4]
+ 8004646:	681b      	ldr	r3, [r3, #0]
+ 8004648:	2b02      	cmp	r3, #2
+ 800464a:	d116      	bne.n	800467a <HAL_FLASHEx_Erase+0x5a>
+    else 
+#endif /* FLASH_BANK2_END */
+    {
+      /* Mass Erase requested for Bank1 */
+      /* Wait for last operation to be completed */
+      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ 800464c:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 8004650:	f7ff ff50 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 8004654:	4603      	mov	r3, r0
+ 8004656:	2b00      	cmp	r3, #0
+ 8004658:	d141      	bne.n	80046de <HAL_FLASHEx_Erase+0xbe>
+      {
+        /*Mass erase to be done*/
+        FLASH_MassErase(FLASH_BANK_1);
+ 800465a:	2001      	movs	r0, #1
+ 800465c:	f000 f84c 	bl	80046f8 <FLASH_MassErase>
+        
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 8004660:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 8004664:	f7ff ff46 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 8004668:	4603      	mov	r3, r0
+ 800466a:	73fb      	strb	r3, [r7, #15]
+        
+        /* If the erase operation is completed, disable the MER Bit */
+        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ 800466c:	4b21      	ldr	r3, [pc, #132]	@ (80046f4 <HAL_FLASHEx_Erase+0xd4>)
+ 800466e:	691b      	ldr	r3, [r3, #16]
+ 8004670:	4a20      	ldr	r2, [pc, #128]	@ (80046f4 <HAL_FLASHEx_Erase+0xd4>)
+ 8004672:	f023 0304 	bic.w	r3, r3, #4
+ 8004676:	6113      	str	r3, [r2, #16]
+ 8004678:	e031      	b.n	80046de <HAL_FLASHEx_Erase+0xbe>
+    else
+#endif /* FLASH_BANK2_END */
+   {
+      /* Page Erase requested on address located on bank1 */
+      /* Wait for last operation to be completed */
+      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ 800467a:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 800467e:	f7ff ff39 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 8004682:	4603      	mov	r3, r0
+ 8004684:	2b00      	cmp	r3, #0
+ 8004686:	d12a      	bne.n	80046de <HAL_FLASHEx_Erase+0xbe>
+      {
+        /*Initialization of PageError variable*/
+        *PageError = 0xFFFFFFFFU;
+ 8004688:	683b      	ldr	r3, [r7, #0]
+ 800468a:	f04f 32ff 	mov.w	r2, #4294967295
+ 800468e:	601a      	str	r2, [r3, #0]
+        
+        /* Erase page by page to be done*/
+        for(address = pEraseInit->PageAddress;
+ 8004690:	687b      	ldr	r3, [r7, #4]
+ 8004692:	689b      	ldr	r3, [r3, #8]
+ 8004694:	60bb      	str	r3, [r7, #8]
+ 8004696:	e019      	b.n	80046cc <HAL_FLASHEx_Erase+0xac>
+            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
+            address += FLASH_PAGE_SIZE)
+        {
+          FLASH_PageErase(address);
+ 8004698:	68b8      	ldr	r0, [r7, #8]
+ 800469a:	f000 f849 	bl	8004730 <FLASH_PageErase>
+          
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 800469e:	f24c 3050 	movw	r0, #50000	@ 0xc350
+ 80046a2:	f7ff ff27 	bl	80044f4 <FLASH_WaitForLastOperation>
+ 80046a6:	4603      	mov	r3, r0
+ 80046a8:	73fb      	strb	r3, [r7, #15]
+          
+          /* If the erase operation is completed, disable the PER Bit */
+          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+ 80046aa:	4b12      	ldr	r3, [pc, #72]	@ (80046f4 <HAL_FLASHEx_Erase+0xd4>)
+ 80046ac:	691b      	ldr	r3, [r3, #16]
+ 80046ae:	4a11      	ldr	r2, [pc, #68]	@ (80046f4 <HAL_FLASHEx_Erase+0xd4>)
+ 80046b0:	f023 0302 	bic.w	r3, r3, #2
+ 80046b4:	6113      	str	r3, [r2, #16]
+          
+          if (status != HAL_OK)
+ 80046b6:	7bfb      	ldrb	r3, [r7, #15]
+ 80046b8:	2b00      	cmp	r3, #0
+ 80046ba:	d003      	beq.n	80046c4 <HAL_FLASHEx_Erase+0xa4>
+          {
+            /* In case of error, stop erase procedure and return the faulty address */
+            *PageError = address;
+ 80046bc:	683b      	ldr	r3, [r7, #0]
+ 80046be:	68ba      	ldr	r2, [r7, #8]
+ 80046c0:	601a      	str	r2, [r3, #0]
+            break;
+ 80046c2:	e00c      	b.n	80046de <HAL_FLASHEx_Erase+0xbe>
+            address += FLASH_PAGE_SIZE)
+ 80046c4:	68bb      	ldr	r3, [r7, #8]
+ 80046c6:	f503 6380 	add.w	r3, r3, #1024	@ 0x400
+ 80046ca:	60bb      	str	r3, [r7, #8]
+            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
+ 80046cc:	687b      	ldr	r3, [r7, #4]
+ 80046ce:	68db      	ldr	r3, [r3, #12]
+ 80046d0:	029a      	lsls	r2, r3, #10
+ 80046d2:	687b      	ldr	r3, [r7, #4]
+ 80046d4:	689b      	ldr	r3, [r3, #8]
+ 80046d6:	4413      	add	r3, r2
+ 80046d8:	68ba      	ldr	r2, [r7, #8]
+ 80046da:	429a      	cmp	r2, r3
+ 80046dc:	d3dc      	bcc.n	8004698 <HAL_FLASHEx_Erase+0x78>
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+ 80046de:	4b04      	ldr	r3, [pc, #16]	@ (80046f0 <HAL_FLASHEx_Erase+0xd0>)
+ 80046e0:	2200      	movs	r2, #0
+ 80046e2:	761a      	strb	r2, [r3, #24]
+
+  return status;
+ 80046e4:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 80046e6:	4618      	mov	r0, r3
+ 80046e8:	3710      	adds	r7, #16
+ 80046ea:	46bd      	mov	sp, r7
+ 80046ec:	bd80      	pop	{r7, pc}
+ 80046ee:	bf00      	nop
+ 80046f0:	200007b8 	.word	0x200007b8
+ 80046f4:	40022000 	.word	0x40022000
+
+080046f8 <FLASH_MassErase>:
+  @endif
+  *
+  * @retval None
+  */
+static void FLASH_MassErase(uint32_t Banks)
+{
+ 80046f8:	b480      	push	{r7}
+ 80046fa:	b083      	sub	sp, #12
+ 80046fc:	af00      	add	r7, sp, #0
+ 80046fe:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Clean the error context */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 8004700:	4b09      	ldr	r3, [pc, #36]	@ (8004728 <FLASH_MassErase+0x30>)
+ 8004702:	2200      	movs	r2, #0
+ 8004704:	61da      	str	r2, [r3, #28]
+#if !defined(FLASH_BANK2_END)
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Banks);
+#endif /* FLASH_BANK2_END */  
+    /* Only bank1 will be erased*/
+    SET_BIT(FLASH->CR, FLASH_CR_MER);
+ 8004706:	4b09      	ldr	r3, [pc, #36]	@ (800472c <FLASH_MassErase+0x34>)
+ 8004708:	691b      	ldr	r3, [r3, #16]
+ 800470a:	4a08      	ldr	r2, [pc, #32]	@ (800472c <FLASH_MassErase+0x34>)
+ 800470c:	f043 0304 	orr.w	r3, r3, #4
+ 8004710:	6113      	str	r3, [r2, #16]
+    SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ 8004712:	4b06      	ldr	r3, [pc, #24]	@ (800472c <FLASH_MassErase+0x34>)
+ 8004714:	691b      	ldr	r3, [r3, #16]
+ 8004716:	4a05      	ldr	r2, [pc, #20]	@ (800472c <FLASH_MassErase+0x34>)
+ 8004718:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
+ 800471c:	6113      	str	r3, [r2, #16]
+#if defined(FLASH_BANK2_END)
+  }
+#endif /* FLASH_BANK2_END */
+}
+ 800471e:	bf00      	nop
+ 8004720:	370c      	adds	r7, #12
+ 8004722:	46bd      	mov	sp, r7
+ 8004724:	bc80      	pop	{r7}
+ 8004726:	4770      	bx	lr
+ 8004728:	200007b8 	.word	0x200007b8
+ 800472c:	40022000 	.word	0x40022000
+
+08004730 <FLASH_PageErase>:
+  *         The value of this parameter depend on device used within the same series      
+  * 
+  * @retval None
+  */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ 8004730:	b480      	push	{r7}
+ 8004732:	b083      	sub	sp, #12
+ 8004734:	af00      	add	r7, sp, #0
+ 8004736:	6078      	str	r0, [r7, #4]
+  /* Clean the error context */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 8004738:	4b0b      	ldr	r3, [pc, #44]	@ (8004768 <FLASH_PageErase+0x38>)
+ 800473a:	2200      	movs	r2, #0
+ 800473c:	61da      	str	r2, [r3, #28]
+  }
+  else
+  {
+#endif /* FLASH_BANK2_END */
+    /* Proceed to erase the page */
+    SET_BIT(FLASH->CR, FLASH_CR_PER);
+ 800473e:	4b0b      	ldr	r3, [pc, #44]	@ (800476c <FLASH_PageErase+0x3c>)
+ 8004740:	691b      	ldr	r3, [r3, #16]
+ 8004742:	4a0a      	ldr	r2, [pc, #40]	@ (800476c <FLASH_PageErase+0x3c>)
+ 8004744:	f043 0302 	orr.w	r3, r3, #2
+ 8004748:	6113      	str	r3, [r2, #16]
+    WRITE_REG(FLASH->AR, PageAddress);
+ 800474a:	4a08      	ldr	r2, [pc, #32]	@ (800476c <FLASH_PageErase+0x3c>)
+ 800474c:	687b      	ldr	r3, [r7, #4]
+ 800474e:	6153      	str	r3, [r2, #20]
+    SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ 8004750:	4b06      	ldr	r3, [pc, #24]	@ (800476c <FLASH_PageErase+0x3c>)
+ 8004752:	691b      	ldr	r3, [r3, #16]
+ 8004754:	4a05      	ldr	r2, [pc, #20]	@ (800476c <FLASH_PageErase+0x3c>)
+ 8004756:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
+ 800475a:	6113      	str	r3, [r2, #16]
+#if defined(FLASH_BANK2_END)
+  }
+#endif /* FLASH_BANK2_END */
+}
+ 800475c:	bf00      	nop
+ 800475e:	370c      	adds	r7, #12
+ 8004760:	46bd      	mov	sp, r7
+ 8004762:	bc80      	pop	{r7}
+ 8004764:	4770      	bx	lr
+ 8004766:	bf00      	nop
+ 8004768:	200007b8 	.word	0x200007b8
+ 800476c:	40022000 	.word	0x40022000
+
+08004770 <HAL_GPIO_Init>:
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8004770:	b480      	push	{r7}
+ 8004772:	b08b      	sub	sp, #44	@ 0x2c
+ 8004774:	af00      	add	r7, sp, #0
+ 8004776:	6078      	str	r0, [r7, #4]
+ 8004778:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00u;
+ 800477a:	2300      	movs	r3, #0
+ 800477c:	627b      	str	r3, [r7, #36]	@ 0x24
+  uint32_t ioposition;
+  uint32_t iocurrent;
+  uint32_t temp;
+  uint32_t config = 0x00u;
+ 800477e:	2300      	movs	r3, #0
+ 8004780:	623b      	str	r3, [r7, #32]
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 8004782:	e169      	b.n	8004a58 <HAL_GPIO_Init+0x2e8>
+  {
+    /* Get the IO position */
+    ioposition = (0x01uL << position);
+ 8004784:	2201      	movs	r2, #1
+ 8004786:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004788:	fa02 f303 	lsl.w	r3, r2, r3
+ 800478c:	61fb      	str	r3, [r7, #28]
+
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ 800478e:	683b      	ldr	r3, [r7, #0]
+ 8004790:	681b      	ldr	r3, [r3, #0]
+ 8004792:	69fa      	ldr	r2, [r7, #28]
+ 8004794:	4013      	ands	r3, r2
+ 8004796:	61bb      	str	r3, [r7, #24]
+
+    if (iocurrent == ioposition)
+ 8004798:	69ba      	ldr	r2, [r7, #24]
+ 800479a:	69fb      	ldr	r3, [r7, #28]
+ 800479c:	429a      	cmp	r2, r3
+ 800479e:	f040 8158 	bne.w	8004a52 <HAL_GPIO_Init+0x2e2>
+    {
+      /* Check the Alternate function parameters */
+      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+
+      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
+      switch (GPIO_Init->Mode)
+ 80047a2:	683b      	ldr	r3, [r7, #0]
+ 80047a4:	685b      	ldr	r3, [r3, #4]
+ 80047a6:	4a9a      	ldr	r2, [pc, #616]	@ (8004a10 <HAL_GPIO_Init+0x2a0>)
+ 80047a8:	4293      	cmp	r3, r2
+ 80047aa:	d05e      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+ 80047ac:	4a98      	ldr	r2, [pc, #608]	@ (8004a10 <HAL_GPIO_Init+0x2a0>)
+ 80047ae:	4293      	cmp	r3, r2
+ 80047b0:	d875      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047b2:	4a98      	ldr	r2, [pc, #608]	@ (8004a14 <HAL_GPIO_Init+0x2a4>)
+ 80047b4:	4293      	cmp	r3, r2
+ 80047b6:	d058      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+ 80047b8:	4a96      	ldr	r2, [pc, #600]	@ (8004a14 <HAL_GPIO_Init+0x2a4>)
+ 80047ba:	4293      	cmp	r3, r2
+ 80047bc:	d86f      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047be:	4a96      	ldr	r2, [pc, #600]	@ (8004a18 <HAL_GPIO_Init+0x2a8>)
+ 80047c0:	4293      	cmp	r3, r2
+ 80047c2:	d052      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+ 80047c4:	4a94      	ldr	r2, [pc, #592]	@ (8004a18 <HAL_GPIO_Init+0x2a8>)
+ 80047c6:	4293      	cmp	r3, r2
+ 80047c8:	d869      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047ca:	4a94      	ldr	r2, [pc, #592]	@ (8004a1c <HAL_GPIO_Init+0x2ac>)
+ 80047cc:	4293      	cmp	r3, r2
+ 80047ce:	d04c      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+ 80047d0:	4a92      	ldr	r2, [pc, #584]	@ (8004a1c <HAL_GPIO_Init+0x2ac>)
+ 80047d2:	4293      	cmp	r3, r2
+ 80047d4:	d863      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047d6:	4a92      	ldr	r2, [pc, #584]	@ (8004a20 <HAL_GPIO_Init+0x2b0>)
+ 80047d8:	4293      	cmp	r3, r2
+ 80047da:	d046      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+ 80047dc:	4a90      	ldr	r2, [pc, #576]	@ (8004a20 <HAL_GPIO_Init+0x2b0>)
+ 80047de:	4293      	cmp	r3, r2
+ 80047e0:	d85d      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047e2:	2b12      	cmp	r3, #18
+ 80047e4:	d82a      	bhi.n	800483c <HAL_GPIO_Init+0xcc>
+ 80047e6:	2b12      	cmp	r3, #18
+ 80047e8:	d859      	bhi.n	800489e <HAL_GPIO_Init+0x12e>
+ 80047ea:	a201      	add	r2, pc, #4	@ (adr r2, 80047f0 <HAL_GPIO_Init+0x80>)
+ 80047ec:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80047f0:	0800486b 	.word	0x0800486b
+ 80047f4:	08004845 	.word	0x08004845
+ 80047f8:	08004857 	.word	0x08004857
+ 80047fc:	08004899 	.word	0x08004899
+ 8004800:	0800489f 	.word	0x0800489f
+ 8004804:	0800489f 	.word	0x0800489f
+ 8004808:	0800489f 	.word	0x0800489f
+ 800480c:	0800489f 	.word	0x0800489f
+ 8004810:	0800489f 	.word	0x0800489f
+ 8004814:	0800489f 	.word	0x0800489f
+ 8004818:	0800489f 	.word	0x0800489f
+ 800481c:	0800489f 	.word	0x0800489f
+ 8004820:	0800489f 	.word	0x0800489f
+ 8004824:	0800489f 	.word	0x0800489f
+ 8004828:	0800489f 	.word	0x0800489f
+ 800482c:	0800489f 	.word	0x0800489f
+ 8004830:	0800489f 	.word	0x0800489f
+ 8004834:	0800484d 	.word	0x0800484d
+ 8004838:	08004861 	.word	0x08004861
+ 800483c:	4a79      	ldr	r2, [pc, #484]	@ (8004a24 <HAL_GPIO_Init+0x2b4>)
+ 800483e:	4293      	cmp	r3, r2
+ 8004840:	d013      	beq.n	800486a <HAL_GPIO_Init+0xfa>
+          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
+          break;
+
+        /* Parameters are checked with assert_param */
+        default:
+          break;
+ 8004842:	e02c      	b.n	800489e <HAL_GPIO_Init+0x12e>
+          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
+ 8004844:	683b      	ldr	r3, [r7, #0]
+ 8004846:	68db      	ldr	r3, [r3, #12]
+ 8004848:	623b      	str	r3, [r7, #32]
+          break;
+ 800484a:	e029      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
+ 800484c:	683b      	ldr	r3, [r7, #0]
+ 800484e:	68db      	ldr	r3, [r3, #12]
+ 8004850:	3304      	adds	r3, #4
+ 8004852:	623b      	str	r3, [r7, #32]
+          break;
+ 8004854:	e024      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
+ 8004856:	683b      	ldr	r3, [r7, #0]
+ 8004858:	68db      	ldr	r3, [r3, #12]
+ 800485a:	3308      	adds	r3, #8
+ 800485c:	623b      	str	r3, [r7, #32]
+          break;
+ 800485e:	e01f      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
+ 8004860:	683b      	ldr	r3, [r7, #0]
+ 8004862:	68db      	ldr	r3, [r3, #12]
+ 8004864:	330c      	adds	r3, #12
+ 8004866:	623b      	str	r3, [r7, #32]
+          break;
+ 8004868:	e01a      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          if (GPIO_Init->Pull == GPIO_NOPULL)
+ 800486a:	683b      	ldr	r3, [r7, #0]
+ 800486c:	689b      	ldr	r3, [r3, #8]
+ 800486e:	2b00      	cmp	r3, #0
+ 8004870:	d102      	bne.n	8004878 <HAL_GPIO_Init+0x108>
+            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
+ 8004872:	2304      	movs	r3, #4
+ 8004874:	623b      	str	r3, [r7, #32]
+          break;
+ 8004876:	e013      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          else if (GPIO_Init->Pull == GPIO_PULLUP)
+ 8004878:	683b      	ldr	r3, [r7, #0]
+ 800487a:	689b      	ldr	r3, [r3, #8]
+ 800487c:	2b01      	cmp	r3, #1
+ 800487e:	d105      	bne.n	800488c <HAL_GPIO_Init+0x11c>
+            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+ 8004880:	2308      	movs	r3, #8
+ 8004882:	623b      	str	r3, [r7, #32]
+            GPIOx->BSRR = ioposition;
+ 8004884:	687b      	ldr	r3, [r7, #4]
+ 8004886:	69fa      	ldr	r2, [r7, #28]
+ 8004888:	611a      	str	r2, [r3, #16]
+          break;
+ 800488a:	e009      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+ 800488c:	2308      	movs	r3, #8
+ 800488e:	623b      	str	r3, [r7, #32]
+            GPIOx->BRR = ioposition;
+ 8004890:	687b      	ldr	r3, [r7, #4]
+ 8004892:	69fa      	ldr	r2, [r7, #28]
+ 8004894:	615a      	str	r2, [r3, #20]
+          break;
+ 8004896:	e003      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
+ 8004898:	2300      	movs	r3, #0
+ 800489a:	623b      	str	r3, [r7, #32]
+          break;
+ 800489c:	e000      	b.n	80048a0 <HAL_GPIO_Init+0x130>
+          break;
+ 800489e:	bf00      	nop
+      }
+
+      /* Check if the current bit belongs to first half or last half of the pin count number
+       in order to address CRH or CRL register*/
+      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
+ 80048a0:	69bb      	ldr	r3, [r7, #24]
+ 80048a2:	2bff      	cmp	r3, #255	@ 0xff
+ 80048a4:	d801      	bhi.n	80048aa <HAL_GPIO_Init+0x13a>
+ 80048a6:	687b      	ldr	r3, [r7, #4]
+ 80048a8:	e001      	b.n	80048ae <HAL_GPIO_Init+0x13e>
+ 80048aa:	687b      	ldr	r3, [r7, #4]
+ 80048ac:	3304      	adds	r3, #4
+ 80048ae:	617b      	str	r3, [r7, #20]
+      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
+ 80048b0:	69bb      	ldr	r3, [r7, #24]
+ 80048b2:	2bff      	cmp	r3, #255	@ 0xff
+ 80048b4:	d802      	bhi.n	80048bc <HAL_GPIO_Init+0x14c>
+ 80048b6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80048b8:	009b      	lsls	r3, r3, #2
+ 80048ba:	e002      	b.n	80048c2 <HAL_GPIO_Init+0x152>
+ 80048bc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80048be:	3b08      	subs	r3, #8
+ 80048c0:	009b      	lsls	r3, r3, #2
+ 80048c2:	613b      	str	r3, [r7, #16]
+
+      /* Apply the new configuration of the pin to the register */
+      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
+ 80048c4:	697b      	ldr	r3, [r7, #20]
+ 80048c6:	681a      	ldr	r2, [r3, #0]
+ 80048c8:	210f      	movs	r1, #15
+ 80048ca:	693b      	ldr	r3, [r7, #16]
+ 80048cc:	fa01 f303 	lsl.w	r3, r1, r3
+ 80048d0:	43db      	mvns	r3, r3
+ 80048d2:	401a      	ands	r2, r3
+ 80048d4:	6a39      	ldr	r1, [r7, #32]
+ 80048d6:	693b      	ldr	r3, [r7, #16]
+ 80048d8:	fa01 f303 	lsl.w	r3, r1, r3
+ 80048dc:	431a      	orrs	r2, r3
+ 80048de:	697b      	ldr	r3, [r7, #20]
+ 80048e0:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 80048e2:	683b      	ldr	r3, [r7, #0]
+ 80048e4:	685b      	ldr	r3, [r3, #4]
+ 80048e6:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 80048ea:	2b00      	cmp	r3, #0
+ 80048ec:	f000 80b1 	beq.w	8004a52 <HAL_GPIO_Init+0x2e2>
+      {
+        /* Enable AFIO Clock */
+        __HAL_RCC_AFIO_CLK_ENABLE();
+ 80048f0:	4b4d      	ldr	r3, [pc, #308]	@ (8004a28 <HAL_GPIO_Init+0x2b8>)
+ 80048f2:	699b      	ldr	r3, [r3, #24]
+ 80048f4:	4a4c      	ldr	r2, [pc, #304]	@ (8004a28 <HAL_GPIO_Init+0x2b8>)
+ 80048f6:	f043 0301 	orr.w	r3, r3, #1
+ 80048fa:	6193      	str	r3, [r2, #24]
+ 80048fc:	4b4a      	ldr	r3, [pc, #296]	@ (8004a28 <HAL_GPIO_Init+0x2b8>)
+ 80048fe:	699b      	ldr	r3, [r3, #24]
+ 8004900:	f003 0301 	and.w	r3, r3, #1
+ 8004904:	60bb      	str	r3, [r7, #8]
+ 8004906:	68bb      	ldr	r3, [r7, #8]
+        temp = AFIO->EXTICR[position >> 2u];
+ 8004908:	4a48      	ldr	r2, [pc, #288]	@ (8004a2c <HAL_GPIO_Init+0x2bc>)
+ 800490a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 800490c:	089b      	lsrs	r3, r3, #2
+ 800490e:	3302      	adds	r3, #2
+ 8004910:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8004914:	60fb      	str	r3, [r7, #12]
+        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
+ 8004916:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004918:	f003 0303 	and.w	r3, r3, #3
+ 800491c:	009b      	lsls	r3, r3, #2
+ 800491e:	220f      	movs	r2, #15
+ 8004920:	fa02 f303 	lsl.w	r3, r2, r3
+ 8004924:	43db      	mvns	r3, r3
+ 8004926:	68fa      	ldr	r2, [r7, #12]
+ 8004928:	4013      	ands	r3, r2
+ 800492a:	60fb      	str	r3, [r7, #12]
+        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
+ 800492c:	687b      	ldr	r3, [r7, #4]
+ 800492e:	4a40      	ldr	r2, [pc, #256]	@ (8004a30 <HAL_GPIO_Init+0x2c0>)
+ 8004930:	4293      	cmp	r3, r2
+ 8004932:	d013      	beq.n	800495c <HAL_GPIO_Init+0x1ec>
+ 8004934:	687b      	ldr	r3, [r7, #4]
+ 8004936:	4a3f      	ldr	r2, [pc, #252]	@ (8004a34 <HAL_GPIO_Init+0x2c4>)
+ 8004938:	4293      	cmp	r3, r2
+ 800493a:	d00d      	beq.n	8004958 <HAL_GPIO_Init+0x1e8>
+ 800493c:	687b      	ldr	r3, [r7, #4]
+ 800493e:	4a3e      	ldr	r2, [pc, #248]	@ (8004a38 <HAL_GPIO_Init+0x2c8>)
+ 8004940:	4293      	cmp	r3, r2
+ 8004942:	d007      	beq.n	8004954 <HAL_GPIO_Init+0x1e4>
+ 8004944:	687b      	ldr	r3, [r7, #4]
+ 8004946:	4a3d      	ldr	r2, [pc, #244]	@ (8004a3c <HAL_GPIO_Init+0x2cc>)
+ 8004948:	4293      	cmp	r3, r2
+ 800494a:	d101      	bne.n	8004950 <HAL_GPIO_Init+0x1e0>
+ 800494c:	2303      	movs	r3, #3
+ 800494e:	e006      	b.n	800495e <HAL_GPIO_Init+0x1ee>
+ 8004950:	2304      	movs	r3, #4
+ 8004952:	e004      	b.n	800495e <HAL_GPIO_Init+0x1ee>
+ 8004954:	2302      	movs	r3, #2
+ 8004956:	e002      	b.n	800495e <HAL_GPIO_Init+0x1ee>
+ 8004958:	2301      	movs	r3, #1
+ 800495a:	e000      	b.n	800495e <HAL_GPIO_Init+0x1ee>
+ 800495c:	2300      	movs	r3, #0
+ 800495e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8004960:	f002 0203 	and.w	r2, r2, #3
+ 8004964:	0092      	lsls	r2, r2, #2
+ 8004966:	4093      	lsls	r3, r2
+ 8004968:	68fa      	ldr	r2, [r7, #12]
+ 800496a:	4313      	orrs	r3, r2
+ 800496c:	60fb      	str	r3, [r7, #12]
+        AFIO->EXTICR[position >> 2u] = temp;
+ 800496e:	492f      	ldr	r1, [pc, #188]	@ (8004a2c <HAL_GPIO_Init+0x2bc>)
+ 8004970:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004972:	089b      	lsrs	r3, r3, #2
+ 8004974:	3302      	adds	r3, #2
+ 8004976:	68fa      	ldr	r2, [r7, #12]
+ 8004978:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+
+
+        /* Enable or disable the rising trigger */
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 800497c:	683b      	ldr	r3, [r7, #0]
+ 800497e:	685b      	ldr	r3, [r3, #4]
+ 8004980:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 8004984:	2b00      	cmp	r3, #0
+ 8004986:	d006      	beq.n	8004996 <HAL_GPIO_Init+0x226>
+        {
+          SET_BIT(EXTI->RTSR, iocurrent);
+ 8004988:	4b2d      	ldr	r3, [pc, #180]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 800498a:	689a      	ldr	r2, [r3, #8]
+ 800498c:	492c      	ldr	r1, [pc, #176]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 800498e:	69bb      	ldr	r3, [r7, #24]
+ 8004990:	4313      	orrs	r3, r2
+ 8004992:	608b      	str	r3, [r1, #8]
+ 8004994:	e006      	b.n	80049a4 <HAL_GPIO_Init+0x234>
+        }
+        else
+        {
+          CLEAR_BIT(EXTI->RTSR, iocurrent);
+ 8004996:	4b2a      	ldr	r3, [pc, #168]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 8004998:	689a      	ldr	r2, [r3, #8]
+ 800499a:	69bb      	ldr	r3, [r7, #24]
+ 800499c:	43db      	mvns	r3, r3
+ 800499e:	4928      	ldr	r1, [pc, #160]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049a0:	4013      	ands	r3, r2
+ 80049a2:	608b      	str	r3, [r1, #8]
+        }
+
+        /* Enable or disable the falling trigger */
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 80049a4:	683b      	ldr	r3, [r7, #0]
+ 80049a6:	685b      	ldr	r3, [r3, #4]
+ 80049a8:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
+ 80049ac:	2b00      	cmp	r3, #0
+ 80049ae:	d006      	beq.n	80049be <HAL_GPIO_Init+0x24e>
+        {
+          SET_BIT(EXTI->FTSR, iocurrent);
+ 80049b0:	4b23      	ldr	r3, [pc, #140]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049b2:	68da      	ldr	r2, [r3, #12]
+ 80049b4:	4922      	ldr	r1, [pc, #136]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049b6:	69bb      	ldr	r3, [r7, #24]
+ 80049b8:	4313      	orrs	r3, r2
+ 80049ba:	60cb      	str	r3, [r1, #12]
+ 80049bc:	e006      	b.n	80049cc <HAL_GPIO_Init+0x25c>
+        }
+        else
+        {
+          CLEAR_BIT(EXTI->FTSR, iocurrent);
+ 80049be:	4b20      	ldr	r3, [pc, #128]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049c0:	68da      	ldr	r2, [r3, #12]
+ 80049c2:	69bb      	ldr	r3, [r7, #24]
+ 80049c4:	43db      	mvns	r3, r3
+ 80049c6:	491e      	ldr	r1, [pc, #120]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049c8:	4013      	ands	r3, r2
+ 80049ca:	60cb      	str	r3, [r1, #12]
+        }
+
+        /* Configure the event mask */
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 80049cc:	683b      	ldr	r3, [r7, #0]
+ 80049ce:	685b      	ldr	r3, [r3, #4]
+ 80049d0:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 80049d4:	2b00      	cmp	r3, #0
+ 80049d6:	d006      	beq.n	80049e6 <HAL_GPIO_Init+0x276>
+        {
+          SET_BIT(EXTI->EMR, iocurrent);
+ 80049d8:	4b19      	ldr	r3, [pc, #100]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049da:	685a      	ldr	r2, [r3, #4]
+ 80049dc:	4918      	ldr	r1, [pc, #96]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049de:	69bb      	ldr	r3, [r7, #24]
+ 80049e0:	4313      	orrs	r3, r2
+ 80049e2:	604b      	str	r3, [r1, #4]
+ 80049e4:	e006      	b.n	80049f4 <HAL_GPIO_Init+0x284>
+        }
+        else
+        {
+          CLEAR_BIT(EXTI->EMR, iocurrent);
+ 80049e6:	4b16      	ldr	r3, [pc, #88]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049e8:	685a      	ldr	r2, [r3, #4]
+ 80049ea:	69bb      	ldr	r3, [r7, #24]
+ 80049ec:	43db      	mvns	r3, r3
+ 80049ee:	4914      	ldr	r1, [pc, #80]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 80049f0:	4013      	ands	r3, r2
+ 80049f2:	604b      	str	r3, [r1, #4]
+        }
+
+        /* Configure the interrupt mask */
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 80049f4:	683b      	ldr	r3, [r7, #0]
+ 80049f6:	685b      	ldr	r3, [r3, #4]
+ 80049f8:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 80049fc:	2b00      	cmp	r3, #0
+ 80049fe:	d021      	beq.n	8004a44 <HAL_GPIO_Init+0x2d4>
+        {
+          SET_BIT(EXTI->IMR, iocurrent);
+ 8004a00:	4b0f      	ldr	r3, [pc, #60]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 8004a02:	681a      	ldr	r2, [r3, #0]
+ 8004a04:	490e      	ldr	r1, [pc, #56]	@ (8004a40 <HAL_GPIO_Init+0x2d0>)
+ 8004a06:	69bb      	ldr	r3, [r7, #24]
+ 8004a08:	4313      	orrs	r3, r2
+ 8004a0a:	600b      	str	r3, [r1, #0]
+ 8004a0c:	e021      	b.n	8004a52 <HAL_GPIO_Init+0x2e2>
+ 8004a0e:	bf00      	nop
+ 8004a10:	10320000 	.word	0x10320000
+ 8004a14:	10310000 	.word	0x10310000
+ 8004a18:	10220000 	.word	0x10220000
+ 8004a1c:	10210000 	.word	0x10210000
+ 8004a20:	10120000 	.word	0x10120000
+ 8004a24:	10110000 	.word	0x10110000
+ 8004a28:	40021000 	.word	0x40021000
+ 8004a2c:	40010000 	.word	0x40010000
+ 8004a30:	40010800 	.word	0x40010800
+ 8004a34:	40010c00 	.word	0x40010c00
+ 8004a38:	40011000 	.word	0x40011000
+ 8004a3c:	40011400 	.word	0x40011400
+ 8004a40:	40010400 	.word	0x40010400
+        }
+        else
+        {
+          CLEAR_BIT(EXTI->IMR, iocurrent);
+ 8004a44:	4b0b      	ldr	r3, [pc, #44]	@ (8004a74 <HAL_GPIO_Init+0x304>)
+ 8004a46:	681a      	ldr	r2, [r3, #0]
+ 8004a48:	69bb      	ldr	r3, [r7, #24]
+ 8004a4a:	43db      	mvns	r3, r3
+ 8004a4c:	4909      	ldr	r1, [pc, #36]	@ (8004a74 <HAL_GPIO_Init+0x304>)
+ 8004a4e:	4013      	ands	r3, r2
+ 8004a50:	600b      	str	r3, [r1, #0]
+        }
+      }
+    }
+
+	position++;
+ 8004a52:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004a54:	3301      	adds	r3, #1
+ 8004a56:	627b      	str	r3, [r7, #36]	@ 0x24
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 8004a58:	683b      	ldr	r3, [r7, #0]
+ 8004a5a:	681a      	ldr	r2, [r3, #0]
+ 8004a5c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004a5e:	fa22 f303 	lsr.w	r3, r2, r3
+ 8004a62:	2b00      	cmp	r3, #0
+ 8004a64:	f47f ae8e 	bne.w	8004784 <HAL_GPIO_Init+0x14>
+  }
+}
+ 8004a68:	bf00      	nop
+ 8004a6a:	bf00      	nop
+ 8004a6c:	372c      	adds	r7, #44	@ 0x2c
+ 8004a6e:	46bd      	mov	sp, r7
+ 8004a70:	bc80      	pop	{r7}
+ 8004a72:	4770      	bx	lr
+ 8004a74:	40010400 	.word	0x40010400
+
+08004a78 <HAL_GPIO_ReadPin>:
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ 8004a78:	b480      	push	{r7}
+ 8004a7a:	b085      	sub	sp, #20
+ 8004a7c:	af00      	add	r7, sp, #0
+ 8004a7e:	6078      	str	r0, [r7, #4]
+ 8004a80:	460b      	mov	r3, r1
+ 8004a82:	807b      	strh	r3, [r7, #2]
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ 8004a84:	687b      	ldr	r3, [r7, #4]
+ 8004a86:	689a      	ldr	r2, [r3, #8]
+ 8004a88:	887b      	ldrh	r3, [r7, #2]
+ 8004a8a:	4013      	ands	r3, r2
+ 8004a8c:	2b00      	cmp	r3, #0
+ 8004a8e:	d002      	beq.n	8004a96 <HAL_GPIO_ReadPin+0x1e>
+  {
+    bitstatus = GPIO_PIN_SET;
+ 8004a90:	2301      	movs	r3, #1
+ 8004a92:	73fb      	strb	r3, [r7, #15]
+ 8004a94:	e001      	b.n	8004a9a <HAL_GPIO_ReadPin+0x22>
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+ 8004a96:	2300      	movs	r3, #0
+ 8004a98:	73fb      	strb	r3, [r7, #15]
+  }
+  return bitstatus;
+ 8004a9a:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8004a9c:	4618      	mov	r0, r3
+ 8004a9e:	3714      	adds	r7, #20
+ 8004aa0:	46bd      	mov	sp, r7
+ 8004aa2:	bc80      	pop	{r7}
+ 8004aa4:	4770      	bx	lr
+
+08004aa6 <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8004aa6:	b480      	push	{r7}
+ 8004aa8:	b083      	sub	sp, #12
+ 8004aaa:	af00      	add	r7, sp, #0
+ 8004aac:	6078      	str	r0, [r7, #4]
+ 8004aae:	460b      	mov	r3, r1
+ 8004ab0:	807b      	strh	r3, [r7, #2]
+ 8004ab2:	4613      	mov	r3, r2
+ 8004ab4:	707b      	strb	r3, [r7, #1]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 8004ab6:	787b      	ldrb	r3, [r7, #1]
+ 8004ab8:	2b00      	cmp	r3, #0
+ 8004aba:	d003      	beq.n	8004ac4 <HAL_GPIO_WritePin+0x1e>
+  {
+    GPIOx->BSRR = GPIO_Pin;
+ 8004abc:	887a      	ldrh	r2, [r7, #2]
+ 8004abe:	687b      	ldr	r3, [r7, #4]
+ 8004ac0:	611a      	str	r2, [r3, #16]
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
+  }
+}
+ 8004ac2:	e003      	b.n	8004acc <HAL_GPIO_WritePin+0x26>
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
+ 8004ac4:	887b      	ldrh	r3, [r7, #2]
+ 8004ac6:	041a      	lsls	r2, r3, #16
+ 8004ac8:	687b      	ldr	r3, [r7, #4]
+ 8004aca:	611a      	str	r2, [r3, #16]
+}
+ 8004acc:	bf00      	nop
+ 8004ace:	370c      	adds	r7, #12
+ 8004ad0:	46bd      	mov	sp, r7
+ 8004ad2:	bc80      	pop	{r7}
+ 8004ad4:	4770      	bx	lr
+	...
+
+08004ad8 <HAL_GPIO_EXTI_IRQHandler>:
   * @brief  This function handles EXTI interrupt request.
   * @param  GPIO_Pin: Specifies the pins connected EXTI line
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 {
- 80036b0:	b580      	push	{r7, lr}
- 80036b2:	b082      	sub	sp, #8
- 80036b4:	af00      	add	r7, sp, #0
- 80036b6:	4603      	mov	r3, r0
- 80036b8:	80fb      	strh	r3, [r7, #6]
+ 8004ad8:	b580      	push	{r7, lr}
+ 8004ada:	b082      	sub	sp, #8
+ 8004adc:	af00      	add	r7, sp, #0
+ 8004ade:	4603      	mov	r3, r0
+ 8004ae0:	80fb      	strh	r3, [r7, #6]
   /* EXTI line interrupt detected */
   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
- 80036ba:	4b08      	ldr	r3, [pc, #32]	@ (80036dc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80036bc:	695a      	ldr	r2, [r3, #20]
- 80036be:	88fb      	ldrh	r3, [r7, #6]
- 80036c0:	4013      	ands	r3, r2
- 80036c2:	2b00      	cmp	r3, #0
- 80036c4:	d006      	beq.n	80036d4 <HAL_GPIO_EXTI_IRQHandler+0x24>
+ 8004ae2:	4b08      	ldr	r3, [pc, #32]	@ (8004b04 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 8004ae4:	695a      	ldr	r2, [r3, #20]
+ 8004ae6:	88fb      	ldrh	r3, [r7, #6]
+ 8004ae8:	4013      	ands	r3, r2
+ 8004aea:	2b00      	cmp	r3, #0
+ 8004aec:	d006      	beq.n	8004afc <HAL_GPIO_EXTI_IRQHandler+0x24>
   {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 80036c6:	4a05      	ldr	r2, [pc, #20]	@ (80036dc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80036c8:	88fb      	ldrh	r3, [r7, #6]
- 80036ca:	6153      	str	r3, [r2, #20]
+ 8004aee:	4a05      	ldr	r2, [pc, #20]	@ (8004b04 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 8004af0:	88fb      	ldrh	r3, [r7, #6]
+ 8004af2:	6153      	str	r3, [r2, #20]
     HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 80036cc:	88fb      	ldrh	r3, [r7, #6]
- 80036ce:	4618      	mov	r0, r3
- 80036d0:	f7fe fc60 	bl	8001f94 <HAL_GPIO_EXTI_Callback>
+ 8004af4:	88fb      	ldrh	r3, [r7, #6]
+ 8004af6:	4618      	mov	r0, r3
+ 8004af8:	f7fd fc0e 	bl	8002318 <HAL_GPIO_EXTI_Callback>
   }
 }
- 80036d4:	bf00      	nop
- 80036d6:	3708      	adds	r7, #8
- 80036d8:	46bd      	mov	sp, r7
- 80036da:	bd80      	pop	{r7, pc}
- 80036dc:	40010400 	.word	0x40010400
+ 8004afc:	bf00      	nop
+ 8004afe:	3708      	adds	r7, #8
+ 8004b00:	46bd      	mov	sp, r7
+ 8004b02:	bd80      	pop	{r7, pc}
+ 8004b04:	40010400 	.word	0x40010400
 
-080036e0 <HAL_I2C_Init>:
+08004b08 <HAL_I2C_Init>:
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
 {
- 80036e0:	b580      	push	{r7, lr}
- 80036e2:	b084      	sub	sp, #16
- 80036e4:	af00      	add	r7, sp, #0
- 80036e6:	6078      	str	r0, [r7, #4]
+ 8004b08:	b580      	push	{r7, lr}
+ 8004b0a:	b084      	sub	sp, #16
+ 8004b0c:	af00      	add	r7, sp, #0
+ 8004b0e:	6078      	str	r0, [r7, #4]
   uint32_t freqrange;
   uint32_t pclk1;
 
   /* Check the I2C handle allocation */
   if (hi2c == NULL)
- 80036e8:	687b      	ldr	r3, [r7, #4]
- 80036ea:	2b00      	cmp	r3, #0
- 80036ec:	d101      	bne.n	80036f2 <HAL_I2C_Init+0x12>
+ 8004b10:	687b      	ldr	r3, [r7, #4]
+ 8004b12:	2b00      	cmp	r3, #0
+ 8004b14:	d101      	bne.n	8004b1a <HAL_I2C_Init+0x12>
   {
     return HAL_ERROR;
- 80036ee:	2301      	movs	r3, #1
- 80036f0:	e12b      	b.n	800394a <HAL_I2C_Init+0x26a>
+ 8004b16:	2301      	movs	r3, #1
+ 8004b18:	e12b      	b.n	8004d72 <HAL_I2C_Init+0x26a>
   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
 
   if (hi2c->State == HAL_I2C_STATE_RESET)
- 80036f2:	687b      	ldr	r3, [r7, #4]
- 80036f4:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
- 80036f8:	b2db      	uxtb	r3, r3
- 80036fa:	2b00      	cmp	r3, #0
- 80036fc:	d106      	bne.n	800370c <HAL_I2C_Init+0x2c>
+ 8004b1a:	687b      	ldr	r3, [r7, #4]
+ 8004b1c:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 8004b20:	b2db      	uxtb	r3, r3
+ 8004b22:	2b00      	cmp	r3, #0
+ 8004b24:	d106      	bne.n	8004b34 <HAL_I2C_Init+0x2c>
   {
     /* Allocate lock resource and initialize it */
     hi2c->Lock = HAL_UNLOCKED;
- 80036fe:	687b      	ldr	r3, [r7, #4]
- 8003700:	2200      	movs	r2, #0
- 8003702:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8004b26:	687b      	ldr	r3, [r7, #4]
+ 8004b28:	2200      	movs	r2, #0
+ 8004b2a:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     hi2c->MspInitCallback(hi2c);
 #else
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     HAL_I2C_MspInit(hi2c);
- 8003706:	6878      	ldr	r0, [r7, #4]
- 8003708:	f7fe fcf4 	bl	80020f4 <HAL_I2C_MspInit>
+ 8004b2e:	6878      	ldr	r0, [r7, #4]
+ 8004b30:	f7fd fca8 	bl	8002484 <HAL_I2C_MspInit>
 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
 
   hi2c->State = HAL_I2C_STATE_BUSY;
- 800370c:	687b      	ldr	r3, [r7, #4]
- 800370e:	2224      	movs	r2, #36	@ 0x24
- 8003710:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8004b34:	687b      	ldr	r3, [r7, #4]
+ 8004b36:	2224      	movs	r2, #36	@ 0x24
+ 8004b38:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
 
   /* Disable the selected I2C peripheral */
   __HAL_I2C_DISABLE(hi2c);
- 8003714:	687b      	ldr	r3, [r7, #4]
- 8003716:	681b      	ldr	r3, [r3, #0]
- 8003718:	681a      	ldr	r2, [r3, #0]
- 800371a:	687b      	ldr	r3, [r7, #4]
- 800371c:	681b      	ldr	r3, [r3, #0]
- 800371e:	f022 0201 	bic.w	r2, r2, #1
- 8003722:	601a      	str	r2, [r3, #0]
+ 8004b3c:	687b      	ldr	r3, [r7, #4]
+ 8004b3e:	681b      	ldr	r3, [r3, #0]
+ 8004b40:	681a      	ldr	r2, [r3, #0]
+ 8004b42:	687b      	ldr	r3, [r7, #4]
+ 8004b44:	681b      	ldr	r3, [r3, #0]
+ 8004b46:	f022 0201 	bic.w	r2, r2, #1
+ 8004b4a:	601a      	str	r2, [r3, #0]
 
   /*Reset I2C*/
   hi2c->Instance->CR1 |= I2C_CR1_SWRST;
- 8003724:	687b      	ldr	r3, [r7, #4]
- 8003726:	681b      	ldr	r3, [r3, #0]
- 8003728:	681a      	ldr	r2, [r3, #0]
- 800372a:	687b      	ldr	r3, [r7, #4]
- 800372c:	681b      	ldr	r3, [r3, #0]
- 800372e:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
- 8003732:	601a      	str	r2, [r3, #0]
+ 8004b4c:	687b      	ldr	r3, [r7, #4]
+ 8004b4e:	681b      	ldr	r3, [r3, #0]
+ 8004b50:	681a      	ldr	r2, [r3, #0]
+ 8004b52:	687b      	ldr	r3, [r7, #4]
+ 8004b54:	681b      	ldr	r3, [r3, #0]
+ 8004b56:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
+ 8004b5a:	601a      	str	r2, [r3, #0]
   hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
- 8003734:	687b      	ldr	r3, [r7, #4]
- 8003736:	681b      	ldr	r3, [r3, #0]
- 8003738:	681a      	ldr	r2, [r3, #0]
- 800373a:	687b      	ldr	r3, [r7, #4]
- 800373c:	681b      	ldr	r3, [r3, #0]
- 800373e:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
- 8003742:	601a      	str	r2, [r3, #0]
+ 8004b5c:	687b      	ldr	r3, [r7, #4]
+ 8004b5e:	681b      	ldr	r3, [r3, #0]
+ 8004b60:	681a      	ldr	r2, [r3, #0]
+ 8004b62:	687b      	ldr	r3, [r7, #4]
+ 8004b64:	681b      	ldr	r3, [r3, #0]
+ 8004b66:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 8004b6a:	601a      	str	r2, [r3, #0]
 
   /* Get PCLK1 frequency */
   pclk1 = HAL_RCC_GetPCLK1Freq();
- 8003744:	f001 fbcc 	bl	8004ee0 <HAL_RCC_GetPCLK1Freq>
- 8003748:	60f8      	str	r0, [r7, #12]
+ 8004b6c:	f001 fbcc 	bl	8006308 <HAL_RCC_GetPCLK1Freq>
+ 8004b70:	60f8      	str	r0, [r7, #12]
 
   /* Check the minimum allowed PCLK1 frequency */
   if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
- 800374a:	687b      	ldr	r3, [r7, #4]
- 800374c:	685b      	ldr	r3, [r3, #4]
- 800374e:	4a81      	ldr	r2, [pc, #516]	@ (8003954 <HAL_I2C_Init+0x274>)
- 8003750:	4293      	cmp	r3, r2
- 8003752:	d807      	bhi.n	8003764 <HAL_I2C_Init+0x84>
- 8003754:	68fb      	ldr	r3, [r7, #12]
- 8003756:	4a80      	ldr	r2, [pc, #512]	@ (8003958 <HAL_I2C_Init+0x278>)
- 8003758:	4293      	cmp	r3, r2
- 800375a:	bf94      	ite	ls
- 800375c:	2301      	movls	r3, #1
- 800375e:	2300      	movhi	r3, #0
- 8003760:	b2db      	uxtb	r3, r3
- 8003762:	e006      	b.n	8003772 <HAL_I2C_Init+0x92>
- 8003764:	68fb      	ldr	r3, [r7, #12]
- 8003766:	4a7d      	ldr	r2, [pc, #500]	@ (800395c <HAL_I2C_Init+0x27c>)
- 8003768:	4293      	cmp	r3, r2
- 800376a:	bf94      	ite	ls
- 800376c:	2301      	movls	r3, #1
- 800376e:	2300      	movhi	r3, #0
- 8003770:	b2db      	uxtb	r3, r3
- 8003772:	2b00      	cmp	r3, #0
- 8003774:	d001      	beq.n	800377a <HAL_I2C_Init+0x9a>
+ 8004b72:	687b      	ldr	r3, [r7, #4]
+ 8004b74:	685b      	ldr	r3, [r3, #4]
+ 8004b76:	4a81      	ldr	r2, [pc, #516]	@ (8004d7c <HAL_I2C_Init+0x274>)
+ 8004b78:	4293      	cmp	r3, r2
+ 8004b7a:	d807      	bhi.n	8004b8c <HAL_I2C_Init+0x84>
+ 8004b7c:	68fb      	ldr	r3, [r7, #12]
+ 8004b7e:	4a80      	ldr	r2, [pc, #512]	@ (8004d80 <HAL_I2C_Init+0x278>)
+ 8004b80:	4293      	cmp	r3, r2
+ 8004b82:	bf94      	ite	ls
+ 8004b84:	2301      	movls	r3, #1
+ 8004b86:	2300      	movhi	r3, #0
+ 8004b88:	b2db      	uxtb	r3, r3
+ 8004b8a:	e006      	b.n	8004b9a <HAL_I2C_Init+0x92>
+ 8004b8c:	68fb      	ldr	r3, [r7, #12]
+ 8004b8e:	4a7d      	ldr	r2, [pc, #500]	@ (8004d84 <HAL_I2C_Init+0x27c>)
+ 8004b90:	4293      	cmp	r3, r2
+ 8004b92:	bf94      	ite	ls
+ 8004b94:	2301      	movls	r3, #1
+ 8004b96:	2300      	movhi	r3, #0
+ 8004b98:	b2db      	uxtb	r3, r3
+ 8004b9a:	2b00      	cmp	r3, #0
+ 8004b9c:	d001      	beq.n	8004ba2 <HAL_I2C_Init+0x9a>
   {
     return HAL_ERROR;
- 8003776:	2301      	movs	r3, #1
- 8003778:	e0e7      	b.n	800394a <HAL_I2C_Init+0x26a>
+ 8004b9e:	2301      	movs	r3, #1
+ 8004ba0:	e0e7      	b.n	8004d72 <HAL_I2C_Init+0x26a>
   }
 
   /* Calculate frequency range */
   freqrange = I2C_FREQRANGE(pclk1);
- 800377a:	68fb      	ldr	r3, [r7, #12]
- 800377c:	4a78      	ldr	r2, [pc, #480]	@ (8003960 <HAL_I2C_Init+0x280>)
- 800377e:	fba2 2303 	umull	r2, r3, r2, r3
- 8003782:	0c9b      	lsrs	r3, r3, #18
- 8003784:	60bb      	str	r3, [r7, #8]
+ 8004ba2:	68fb      	ldr	r3, [r7, #12]
+ 8004ba4:	4a78      	ldr	r2, [pc, #480]	@ (8004d88 <HAL_I2C_Init+0x280>)
+ 8004ba6:	fba2 2303 	umull	r2, r3, r2, r3
+ 8004baa:	0c9b      	lsrs	r3, r3, #18
+ 8004bac:	60bb      	str	r3, [r7, #8]
 
   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
   /* Configure I2Cx: Frequency range */
   MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
- 8003786:	687b      	ldr	r3, [r7, #4]
- 8003788:	681b      	ldr	r3, [r3, #0]
- 800378a:	685b      	ldr	r3, [r3, #4]
- 800378c:	f023 013f 	bic.w	r1, r3, #63	@ 0x3f
- 8003790:	687b      	ldr	r3, [r7, #4]
- 8003792:	681b      	ldr	r3, [r3, #0]
- 8003794:	68ba      	ldr	r2, [r7, #8]
- 8003796:	430a      	orrs	r2, r1
- 8003798:	605a      	str	r2, [r3, #4]
+ 8004bae:	687b      	ldr	r3, [r7, #4]
+ 8004bb0:	681b      	ldr	r3, [r3, #0]
+ 8004bb2:	685b      	ldr	r3, [r3, #4]
+ 8004bb4:	f023 013f 	bic.w	r1, r3, #63	@ 0x3f
+ 8004bb8:	687b      	ldr	r3, [r7, #4]
+ 8004bba:	681b      	ldr	r3, [r3, #0]
+ 8004bbc:	68ba      	ldr	r2, [r7, #8]
+ 8004bbe:	430a      	orrs	r2, r1
+ 8004bc0:	605a      	str	r2, [r3, #4]
 
   /*---------------------------- I2Cx TRISE Configuration --------------------*/
   /* Configure I2Cx: Rise Time */
   MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
- 800379a:	687b      	ldr	r3, [r7, #4]
- 800379c:	681b      	ldr	r3, [r3, #0]
- 800379e:	6a1b      	ldr	r3, [r3, #32]
- 80037a0:	f023 013f 	bic.w	r1, r3, #63	@ 0x3f
- 80037a4:	687b      	ldr	r3, [r7, #4]
- 80037a6:	685b      	ldr	r3, [r3, #4]
- 80037a8:	4a6a      	ldr	r2, [pc, #424]	@ (8003954 <HAL_I2C_Init+0x274>)
- 80037aa:	4293      	cmp	r3, r2
- 80037ac:	d802      	bhi.n	80037b4 <HAL_I2C_Init+0xd4>
- 80037ae:	68bb      	ldr	r3, [r7, #8]
- 80037b0:	3301      	adds	r3, #1
- 80037b2:	e009      	b.n	80037c8 <HAL_I2C_Init+0xe8>
- 80037b4:	68bb      	ldr	r3, [r7, #8]
- 80037b6:	f44f 7296 	mov.w	r2, #300	@ 0x12c
- 80037ba:	fb02 f303 	mul.w	r3, r2, r3
- 80037be:	4a69      	ldr	r2, [pc, #420]	@ (8003964 <HAL_I2C_Init+0x284>)
- 80037c0:	fba2 2303 	umull	r2, r3, r2, r3
- 80037c4:	099b      	lsrs	r3, r3, #6
- 80037c6:	3301      	adds	r3, #1
- 80037c8:	687a      	ldr	r2, [r7, #4]
- 80037ca:	6812      	ldr	r2, [r2, #0]
- 80037cc:	430b      	orrs	r3, r1
- 80037ce:	6213      	str	r3, [r2, #32]
+ 8004bc2:	687b      	ldr	r3, [r7, #4]
+ 8004bc4:	681b      	ldr	r3, [r3, #0]
+ 8004bc6:	6a1b      	ldr	r3, [r3, #32]
+ 8004bc8:	f023 013f 	bic.w	r1, r3, #63	@ 0x3f
+ 8004bcc:	687b      	ldr	r3, [r7, #4]
+ 8004bce:	685b      	ldr	r3, [r3, #4]
+ 8004bd0:	4a6a      	ldr	r2, [pc, #424]	@ (8004d7c <HAL_I2C_Init+0x274>)
+ 8004bd2:	4293      	cmp	r3, r2
+ 8004bd4:	d802      	bhi.n	8004bdc <HAL_I2C_Init+0xd4>
+ 8004bd6:	68bb      	ldr	r3, [r7, #8]
+ 8004bd8:	3301      	adds	r3, #1
+ 8004bda:	e009      	b.n	8004bf0 <HAL_I2C_Init+0xe8>
+ 8004bdc:	68bb      	ldr	r3, [r7, #8]
+ 8004bde:	f44f 7296 	mov.w	r2, #300	@ 0x12c
+ 8004be2:	fb02 f303 	mul.w	r3, r2, r3
+ 8004be6:	4a69      	ldr	r2, [pc, #420]	@ (8004d8c <HAL_I2C_Init+0x284>)
+ 8004be8:	fba2 2303 	umull	r2, r3, r2, r3
+ 8004bec:	099b      	lsrs	r3, r3, #6
+ 8004bee:	3301      	adds	r3, #1
+ 8004bf0:	687a      	ldr	r2, [r7, #4]
+ 8004bf2:	6812      	ldr	r2, [r2, #0]
+ 8004bf4:	430b      	orrs	r3, r1
+ 8004bf6:	6213      	str	r3, [r2, #32]
 
   /*---------------------------- I2Cx CCR Configuration ----------------------*/
   /* Configure I2Cx: Speed */
   MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
- 80037d0:	687b      	ldr	r3, [r7, #4]
- 80037d2:	681b      	ldr	r3, [r3, #0]
- 80037d4:	69db      	ldr	r3, [r3, #28]
- 80037d6:	f423 424f 	bic.w	r2, r3, #52992	@ 0xcf00
- 80037da:	f022 02ff 	bic.w	r2, r2, #255	@ 0xff
- 80037de:	687b      	ldr	r3, [r7, #4]
- 80037e0:	685b      	ldr	r3, [r3, #4]
- 80037e2:	495c      	ldr	r1, [pc, #368]	@ (8003954 <HAL_I2C_Init+0x274>)
- 80037e4:	428b      	cmp	r3, r1
- 80037e6:	d819      	bhi.n	800381c <HAL_I2C_Init+0x13c>
- 80037e8:	68fb      	ldr	r3, [r7, #12]
- 80037ea:	1e59      	subs	r1, r3, #1
- 80037ec:	687b      	ldr	r3, [r7, #4]
- 80037ee:	685b      	ldr	r3, [r3, #4]
- 80037f0:	005b      	lsls	r3, r3, #1
- 80037f2:	fbb1 f3f3 	udiv	r3, r1, r3
- 80037f6:	1c59      	adds	r1, r3, #1
- 80037f8:	f640 73fc 	movw	r3, #4092	@ 0xffc
- 80037fc:	400b      	ands	r3, r1
- 80037fe:	2b00      	cmp	r3, #0
- 8003800:	d00a      	beq.n	8003818 <HAL_I2C_Init+0x138>
- 8003802:	68fb      	ldr	r3, [r7, #12]
- 8003804:	1e59      	subs	r1, r3, #1
- 8003806:	687b      	ldr	r3, [r7, #4]
- 8003808:	685b      	ldr	r3, [r3, #4]
- 800380a:	005b      	lsls	r3, r3, #1
- 800380c:	fbb1 f3f3 	udiv	r3, r1, r3
- 8003810:	3301      	adds	r3, #1
- 8003812:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 8003816:	e051      	b.n	80038bc <HAL_I2C_Init+0x1dc>
- 8003818:	2304      	movs	r3, #4
- 800381a:	e04f      	b.n	80038bc <HAL_I2C_Init+0x1dc>
- 800381c:	687b      	ldr	r3, [r7, #4]
- 800381e:	689b      	ldr	r3, [r3, #8]
- 8003820:	2b00      	cmp	r3, #0
- 8003822:	d111      	bne.n	8003848 <HAL_I2C_Init+0x168>
- 8003824:	68fb      	ldr	r3, [r7, #12]
- 8003826:	1e58      	subs	r0, r3, #1
- 8003828:	687b      	ldr	r3, [r7, #4]
- 800382a:	6859      	ldr	r1, [r3, #4]
- 800382c:	460b      	mov	r3, r1
- 800382e:	005b      	lsls	r3, r3, #1
- 8003830:	440b      	add	r3, r1
- 8003832:	fbb0 f3f3 	udiv	r3, r0, r3
- 8003836:	3301      	adds	r3, #1
- 8003838:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 800383c:	2b00      	cmp	r3, #0
- 800383e:	bf0c      	ite	eq
- 8003840:	2301      	moveq	r3, #1
- 8003842:	2300      	movne	r3, #0
- 8003844:	b2db      	uxtb	r3, r3
- 8003846:	e012      	b.n	800386e <HAL_I2C_Init+0x18e>
- 8003848:	68fb      	ldr	r3, [r7, #12]
- 800384a:	1e58      	subs	r0, r3, #1
- 800384c:	687b      	ldr	r3, [r7, #4]
- 800384e:	6859      	ldr	r1, [r3, #4]
- 8003850:	460b      	mov	r3, r1
- 8003852:	009b      	lsls	r3, r3, #2
- 8003854:	440b      	add	r3, r1
- 8003856:	0099      	lsls	r1, r3, #2
- 8003858:	440b      	add	r3, r1
- 800385a:	fbb0 f3f3 	udiv	r3, r0, r3
- 800385e:	3301      	adds	r3, #1
- 8003860:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 8003864:	2b00      	cmp	r3, #0
- 8003866:	bf0c      	ite	eq
- 8003868:	2301      	moveq	r3, #1
- 800386a:	2300      	movne	r3, #0
- 800386c:	b2db      	uxtb	r3, r3
- 800386e:	2b00      	cmp	r3, #0
- 8003870:	d001      	beq.n	8003876 <HAL_I2C_Init+0x196>
- 8003872:	2301      	movs	r3, #1
- 8003874:	e022      	b.n	80038bc <HAL_I2C_Init+0x1dc>
- 8003876:	687b      	ldr	r3, [r7, #4]
- 8003878:	689b      	ldr	r3, [r3, #8]
- 800387a:	2b00      	cmp	r3, #0
- 800387c:	d10e      	bne.n	800389c <HAL_I2C_Init+0x1bc>
- 800387e:	68fb      	ldr	r3, [r7, #12]
- 8003880:	1e58      	subs	r0, r3, #1
- 8003882:	687b      	ldr	r3, [r7, #4]
- 8003884:	6859      	ldr	r1, [r3, #4]
- 8003886:	460b      	mov	r3, r1
- 8003888:	005b      	lsls	r3, r3, #1
- 800388a:	440b      	add	r3, r1
- 800388c:	fbb0 f3f3 	udiv	r3, r0, r3
- 8003890:	3301      	adds	r3, #1
- 8003892:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 8003896:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
- 800389a:	e00f      	b.n	80038bc <HAL_I2C_Init+0x1dc>
- 800389c:	68fb      	ldr	r3, [r7, #12]
- 800389e:	1e58      	subs	r0, r3, #1
- 80038a0:	687b      	ldr	r3, [r7, #4]
- 80038a2:	6859      	ldr	r1, [r3, #4]
- 80038a4:	460b      	mov	r3, r1
- 80038a6:	009b      	lsls	r3, r3, #2
- 80038a8:	440b      	add	r3, r1
- 80038aa:	0099      	lsls	r1, r3, #2
- 80038ac:	440b      	add	r3, r1
- 80038ae:	fbb0 f3f3 	udiv	r3, r0, r3
- 80038b2:	3301      	adds	r3, #1
- 80038b4:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 80038b8:	f443 4340 	orr.w	r3, r3, #49152	@ 0xc000
- 80038bc:	6879      	ldr	r1, [r7, #4]
- 80038be:	6809      	ldr	r1, [r1, #0]
- 80038c0:	4313      	orrs	r3, r2
- 80038c2:	61cb      	str	r3, [r1, #28]
+ 8004bf8:	687b      	ldr	r3, [r7, #4]
+ 8004bfa:	681b      	ldr	r3, [r3, #0]
+ 8004bfc:	69db      	ldr	r3, [r3, #28]
+ 8004bfe:	f423 424f 	bic.w	r2, r3, #52992	@ 0xcf00
+ 8004c02:	f022 02ff 	bic.w	r2, r2, #255	@ 0xff
+ 8004c06:	687b      	ldr	r3, [r7, #4]
+ 8004c08:	685b      	ldr	r3, [r3, #4]
+ 8004c0a:	495c      	ldr	r1, [pc, #368]	@ (8004d7c <HAL_I2C_Init+0x274>)
+ 8004c0c:	428b      	cmp	r3, r1
+ 8004c0e:	d819      	bhi.n	8004c44 <HAL_I2C_Init+0x13c>
+ 8004c10:	68fb      	ldr	r3, [r7, #12]
+ 8004c12:	1e59      	subs	r1, r3, #1
+ 8004c14:	687b      	ldr	r3, [r7, #4]
+ 8004c16:	685b      	ldr	r3, [r3, #4]
+ 8004c18:	005b      	lsls	r3, r3, #1
+ 8004c1a:	fbb1 f3f3 	udiv	r3, r1, r3
+ 8004c1e:	1c59      	adds	r1, r3, #1
+ 8004c20:	f640 73fc 	movw	r3, #4092	@ 0xffc
+ 8004c24:	400b      	ands	r3, r1
+ 8004c26:	2b00      	cmp	r3, #0
+ 8004c28:	d00a      	beq.n	8004c40 <HAL_I2C_Init+0x138>
+ 8004c2a:	68fb      	ldr	r3, [r7, #12]
+ 8004c2c:	1e59      	subs	r1, r3, #1
+ 8004c2e:	687b      	ldr	r3, [r7, #4]
+ 8004c30:	685b      	ldr	r3, [r3, #4]
+ 8004c32:	005b      	lsls	r3, r3, #1
+ 8004c34:	fbb1 f3f3 	udiv	r3, r1, r3
+ 8004c38:	3301      	adds	r3, #1
+ 8004c3a:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8004c3e:	e051      	b.n	8004ce4 <HAL_I2C_Init+0x1dc>
+ 8004c40:	2304      	movs	r3, #4
+ 8004c42:	e04f      	b.n	8004ce4 <HAL_I2C_Init+0x1dc>
+ 8004c44:	687b      	ldr	r3, [r7, #4]
+ 8004c46:	689b      	ldr	r3, [r3, #8]
+ 8004c48:	2b00      	cmp	r3, #0
+ 8004c4a:	d111      	bne.n	8004c70 <HAL_I2C_Init+0x168>
+ 8004c4c:	68fb      	ldr	r3, [r7, #12]
+ 8004c4e:	1e58      	subs	r0, r3, #1
+ 8004c50:	687b      	ldr	r3, [r7, #4]
+ 8004c52:	6859      	ldr	r1, [r3, #4]
+ 8004c54:	460b      	mov	r3, r1
+ 8004c56:	005b      	lsls	r3, r3, #1
+ 8004c58:	440b      	add	r3, r1
+ 8004c5a:	fbb0 f3f3 	udiv	r3, r0, r3
+ 8004c5e:	3301      	adds	r3, #1
+ 8004c60:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8004c64:	2b00      	cmp	r3, #0
+ 8004c66:	bf0c      	ite	eq
+ 8004c68:	2301      	moveq	r3, #1
+ 8004c6a:	2300      	movne	r3, #0
+ 8004c6c:	b2db      	uxtb	r3, r3
+ 8004c6e:	e012      	b.n	8004c96 <HAL_I2C_Init+0x18e>
+ 8004c70:	68fb      	ldr	r3, [r7, #12]
+ 8004c72:	1e58      	subs	r0, r3, #1
+ 8004c74:	687b      	ldr	r3, [r7, #4]
+ 8004c76:	6859      	ldr	r1, [r3, #4]
+ 8004c78:	460b      	mov	r3, r1
+ 8004c7a:	009b      	lsls	r3, r3, #2
+ 8004c7c:	440b      	add	r3, r1
+ 8004c7e:	0099      	lsls	r1, r3, #2
+ 8004c80:	440b      	add	r3, r1
+ 8004c82:	fbb0 f3f3 	udiv	r3, r0, r3
+ 8004c86:	3301      	adds	r3, #1
+ 8004c88:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8004c8c:	2b00      	cmp	r3, #0
+ 8004c8e:	bf0c      	ite	eq
+ 8004c90:	2301      	moveq	r3, #1
+ 8004c92:	2300      	movne	r3, #0
+ 8004c94:	b2db      	uxtb	r3, r3
+ 8004c96:	2b00      	cmp	r3, #0
+ 8004c98:	d001      	beq.n	8004c9e <HAL_I2C_Init+0x196>
+ 8004c9a:	2301      	movs	r3, #1
+ 8004c9c:	e022      	b.n	8004ce4 <HAL_I2C_Init+0x1dc>
+ 8004c9e:	687b      	ldr	r3, [r7, #4]
+ 8004ca0:	689b      	ldr	r3, [r3, #8]
+ 8004ca2:	2b00      	cmp	r3, #0
+ 8004ca4:	d10e      	bne.n	8004cc4 <HAL_I2C_Init+0x1bc>
+ 8004ca6:	68fb      	ldr	r3, [r7, #12]
+ 8004ca8:	1e58      	subs	r0, r3, #1
+ 8004caa:	687b      	ldr	r3, [r7, #4]
+ 8004cac:	6859      	ldr	r1, [r3, #4]
+ 8004cae:	460b      	mov	r3, r1
+ 8004cb0:	005b      	lsls	r3, r3, #1
+ 8004cb2:	440b      	add	r3, r1
+ 8004cb4:	fbb0 f3f3 	udiv	r3, r0, r3
+ 8004cb8:	3301      	adds	r3, #1
+ 8004cba:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8004cbe:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
+ 8004cc2:	e00f      	b.n	8004ce4 <HAL_I2C_Init+0x1dc>
+ 8004cc4:	68fb      	ldr	r3, [r7, #12]
+ 8004cc6:	1e58      	subs	r0, r3, #1
+ 8004cc8:	687b      	ldr	r3, [r7, #4]
+ 8004cca:	6859      	ldr	r1, [r3, #4]
+ 8004ccc:	460b      	mov	r3, r1
+ 8004cce:	009b      	lsls	r3, r3, #2
+ 8004cd0:	440b      	add	r3, r1
+ 8004cd2:	0099      	lsls	r1, r3, #2
+ 8004cd4:	440b      	add	r3, r1
+ 8004cd6:	fbb0 f3f3 	udiv	r3, r0, r3
+ 8004cda:	3301      	adds	r3, #1
+ 8004cdc:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8004ce0:	f443 4340 	orr.w	r3, r3, #49152	@ 0xc000
+ 8004ce4:	6879      	ldr	r1, [r7, #4]
+ 8004ce6:	6809      	ldr	r1, [r1, #0]
+ 8004ce8:	4313      	orrs	r3, r2
+ 8004cea:	61cb      	str	r3, [r1, #28]
 
   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
   /* Configure I2Cx: Generalcall and NoStretch mode */
   MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
- 80038c4:	687b      	ldr	r3, [r7, #4]
- 80038c6:	681b      	ldr	r3, [r3, #0]
- 80038c8:	681b      	ldr	r3, [r3, #0]
- 80038ca:	f023 01c0 	bic.w	r1, r3, #192	@ 0xc0
- 80038ce:	687b      	ldr	r3, [r7, #4]
- 80038d0:	69da      	ldr	r2, [r3, #28]
- 80038d2:	687b      	ldr	r3, [r7, #4]
- 80038d4:	6a1b      	ldr	r3, [r3, #32]
- 80038d6:	431a      	orrs	r2, r3
- 80038d8:	687b      	ldr	r3, [r7, #4]
- 80038da:	681b      	ldr	r3, [r3, #0]
- 80038dc:	430a      	orrs	r2, r1
- 80038de:	601a      	str	r2, [r3, #0]
+ 8004cec:	687b      	ldr	r3, [r7, #4]
+ 8004cee:	681b      	ldr	r3, [r3, #0]
+ 8004cf0:	681b      	ldr	r3, [r3, #0]
+ 8004cf2:	f023 01c0 	bic.w	r1, r3, #192	@ 0xc0
+ 8004cf6:	687b      	ldr	r3, [r7, #4]
+ 8004cf8:	69da      	ldr	r2, [r3, #28]
+ 8004cfa:	687b      	ldr	r3, [r7, #4]
+ 8004cfc:	6a1b      	ldr	r3, [r3, #32]
+ 8004cfe:	431a      	orrs	r2, r3
+ 8004d00:	687b      	ldr	r3, [r7, #4]
+ 8004d02:	681b      	ldr	r3, [r3, #0]
+ 8004d04:	430a      	orrs	r2, r1
+ 8004d06:	601a      	str	r2, [r3, #0]
 
   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
   /* Configure I2Cx: Own Address1 and addressing mode */
   MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
- 80038e0:	687b      	ldr	r3, [r7, #4]
- 80038e2:	681b      	ldr	r3, [r3, #0]
- 80038e4:	689b      	ldr	r3, [r3, #8]
- 80038e6:	f423 4303 	bic.w	r3, r3, #33536	@ 0x8300
- 80038ea:	f023 03ff 	bic.w	r3, r3, #255	@ 0xff
- 80038ee:	687a      	ldr	r2, [r7, #4]
- 80038f0:	6911      	ldr	r1, [r2, #16]
- 80038f2:	687a      	ldr	r2, [r7, #4]
- 80038f4:	68d2      	ldr	r2, [r2, #12]
- 80038f6:	4311      	orrs	r1, r2
- 80038f8:	687a      	ldr	r2, [r7, #4]
- 80038fa:	6812      	ldr	r2, [r2, #0]
- 80038fc:	430b      	orrs	r3, r1
- 80038fe:	6093      	str	r3, [r2, #8]
+ 8004d08:	687b      	ldr	r3, [r7, #4]
+ 8004d0a:	681b      	ldr	r3, [r3, #0]
+ 8004d0c:	689b      	ldr	r3, [r3, #8]
+ 8004d0e:	f423 4303 	bic.w	r3, r3, #33536	@ 0x8300
+ 8004d12:	f023 03ff 	bic.w	r3, r3, #255	@ 0xff
+ 8004d16:	687a      	ldr	r2, [r7, #4]
+ 8004d18:	6911      	ldr	r1, [r2, #16]
+ 8004d1a:	687a      	ldr	r2, [r7, #4]
+ 8004d1c:	68d2      	ldr	r2, [r2, #12]
+ 8004d1e:	4311      	orrs	r1, r2
+ 8004d20:	687a      	ldr	r2, [r7, #4]
+ 8004d22:	6812      	ldr	r2, [r2, #0]
+ 8004d24:	430b      	orrs	r3, r1
+ 8004d26:	6093      	str	r3, [r2, #8]
 
   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
   /* Configure I2Cx: Dual mode and Own Address2 */
   MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
- 8003900:	687b      	ldr	r3, [r7, #4]
- 8003902:	681b      	ldr	r3, [r3, #0]
- 8003904:	68db      	ldr	r3, [r3, #12]
- 8003906:	f023 01ff 	bic.w	r1, r3, #255	@ 0xff
- 800390a:	687b      	ldr	r3, [r7, #4]
- 800390c:	695a      	ldr	r2, [r3, #20]
- 800390e:	687b      	ldr	r3, [r7, #4]
- 8003910:	699b      	ldr	r3, [r3, #24]
- 8003912:	431a      	orrs	r2, r3
- 8003914:	687b      	ldr	r3, [r7, #4]
- 8003916:	681b      	ldr	r3, [r3, #0]
- 8003918:	430a      	orrs	r2, r1
- 800391a:	60da      	str	r2, [r3, #12]
+ 8004d28:	687b      	ldr	r3, [r7, #4]
+ 8004d2a:	681b      	ldr	r3, [r3, #0]
+ 8004d2c:	68db      	ldr	r3, [r3, #12]
+ 8004d2e:	f023 01ff 	bic.w	r1, r3, #255	@ 0xff
+ 8004d32:	687b      	ldr	r3, [r7, #4]
+ 8004d34:	695a      	ldr	r2, [r3, #20]
+ 8004d36:	687b      	ldr	r3, [r7, #4]
+ 8004d38:	699b      	ldr	r3, [r3, #24]
+ 8004d3a:	431a      	orrs	r2, r3
+ 8004d3c:	687b      	ldr	r3, [r7, #4]
+ 8004d3e:	681b      	ldr	r3, [r3, #0]
+ 8004d40:	430a      	orrs	r2, r1
+ 8004d42:	60da      	str	r2, [r3, #12]
 
   /* Enable the selected I2C peripheral */
   __HAL_I2C_ENABLE(hi2c);
- 800391c:	687b      	ldr	r3, [r7, #4]
- 800391e:	681b      	ldr	r3, [r3, #0]
- 8003920:	681a      	ldr	r2, [r3, #0]
- 8003922:	687b      	ldr	r3, [r7, #4]
- 8003924:	681b      	ldr	r3, [r3, #0]
- 8003926:	f042 0201 	orr.w	r2, r2, #1
- 800392a:	601a      	str	r2, [r3, #0]
+ 8004d44:	687b      	ldr	r3, [r7, #4]
+ 8004d46:	681b      	ldr	r3, [r3, #0]
+ 8004d48:	681a      	ldr	r2, [r3, #0]
+ 8004d4a:	687b      	ldr	r3, [r7, #4]
+ 8004d4c:	681b      	ldr	r3, [r3, #0]
+ 8004d4e:	f042 0201 	orr.w	r2, r2, #1
+ 8004d52:	601a      	str	r2, [r3, #0]
 
   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- 800392c:	687b      	ldr	r3, [r7, #4]
- 800392e:	2200      	movs	r2, #0
- 8003930:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8004d54:	687b      	ldr	r3, [r7, #4]
+ 8004d56:	2200      	movs	r2, #0
+ 8004d58:	641a      	str	r2, [r3, #64]	@ 0x40
   hi2c->State = HAL_I2C_STATE_READY;
- 8003932:	687b      	ldr	r3, [r7, #4]
- 8003934:	2220      	movs	r2, #32
- 8003936:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8004d5a:	687b      	ldr	r3, [r7, #4]
+ 8004d5c:	2220      	movs	r2, #32
+ 8004d5e:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
   hi2c->PreviousState = I2C_STATE_NONE;
- 800393a:	687b      	ldr	r3, [r7, #4]
- 800393c:	2200      	movs	r2, #0
- 800393e:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8004d62:	687b      	ldr	r3, [r7, #4]
+ 8004d64:	2200      	movs	r2, #0
+ 8004d66:	631a      	str	r2, [r3, #48]	@ 0x30
   hi2c->Mode = HAL_I2C_MODE_NONE;
- 8003940:	687b      	ldr	r3, [r7, #4]
- 8003942:	2200      	movs	r2, #0
- 8003944:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8004d68:	687b      	ldr	r3, [r7, #4]
+ 8004d6a:	2200      	movs	r2, #0
+ 8004d6c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 
   return HAL_OK;
- 8003948:	2300      	movs	r3, #0
+ 8004d70:	2300      	movs	r3, #0
 }
- 800394a:	4618      	mov	r0, r3
- 800394c:	3710      	adds	r7, #16
- 800394e:	46bd      	mov	sp, r7
- 8003950:	bd80      	pop	{r7, pc}
- 8003952:	bf00      	nop
- 8003954:	000186a0 	.word	0x000186a0
- 8003958:	001e847f 	.word	0x001e847f
- 800395c:	003d08ff 	.word	0x003d08ff
- 8003960:	431bde83 	.word	0x431bde83
- 8003964:	10624dd3 	.word	0x10624dd3
+ 8004d72:	4618      	mov	r0, r3
+ 8004d74:	3710      	adds	r7, #16
+ 8004d76:	46bd      	mov	sp, r7
+ 8004d78:	bd80      	pop	{r7, pc}
+ 8004d7a:	bf00      	nop
+ 8004d7c:	000186a0 	.word	0x000186a0
+ 8004d80:	001e847f 	.word	0x001e847f
+ 8004d84:	003d08ff 	.word	0x003d08ff
+ 8004d88:	431bde83 	.word	0x431bde83
+ 8004d8c:	10624dd3 	.word	0x10624dd3
 
-08003968 <HAL_I2C_Master_Transmit>:
+08004d90 <HAL_I2C_Master_Transmit>:
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
- 8003968:	b580      	push	{r7, lr}
- 800396a:	b088      	sub	sp, #32
- 800396c:	af02      	add	r7, sp, #8
- 800396e:	60f8      	str	r0, [r7, #12]
- 8003970:	607a      	str	r2, [r7, #4]
- 8003972:	461a      	mov	r2, r3
- 8003974:	460b      	mov	r3, r1
- 8003976:	817b      	strh	r3, [r7, #10]
- 8003978:	4613      	mov	r3, r2
- 800397a:	813b      	strh	r3, [r7, #8]
+ 8004d90:	b580      	push	{r7, lr}
+ 8004d92:	b088      	sub	sp, #32
+ 8004d94:	af02      	add	r7, sp, #8
+ 8004d96:	60f8      	str	r0, [r7, #12]
+ 8004d98:	607a      	str	r2, [r7, #4]
+ 8004d9a:	461a      	mov	r2, r3
+ 8004d9c:	460b      	mov	r3, r1
+ 8004d9e:	817b      	strh	r3, [r7, #10]
+ 8004da0:	4613      	mov	r3, r2
+ 8004da2:	813b      	strh	r3, [r7, #8]
   /* Init tickstart for timeout management*/
   uint32_t tickstart = HAL_GetTick();
- 800397c:	f7ff f8e4 	bl	8002b48 <HAL_GetTick>
- 8003980:	6178      	str	r0, [r7, #20]
+ 8004da4:	f7fe fa96 	bl	80032d4 <HAL_GetTick>
+ 8004da8:	6178      	str	r0, [r7, #20]
 
   if (hi2c->State == HAL_I2C_STATE_READY)
- 8003982:	68fb      	ldr	r3, [r7, #12]
- 8003984:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
- 8003988:	b2db      	uxtb	r3, r3
- 800398a:	2b20      	cmp	r3, #32
- 800398c:	f040 80e0 	bne.w	8003b50 <HAL_I2C_Master_Transmit+0x1e8>
+ 8004daa:	68fb      	ldr	r3, [r7, #12]
+ 8004dac:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 8004db0:	b2db      	uxtb	r3, r3
+ 8004db2:	2b20      	cmp	r3, #32
+ 8004db4:	f040 80e0 	bne.w	8004f78 <HAL_I2C_Master_Transmit+0x1e8>
   {
     /* Wait until BUSY flag is reset */
     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- 8003990:	697b      	ldr	r3, [r7, #20]
- 8003992:	9300      	str	r3, [sp, #0]
- 8003994:	2319      	movs	r3, #25
- 8003996:	2201      	movs	r2, #1
- 8003998:	4970      	ldr	r1, [pc, #448]	@ (8003b5c <HAL_I2C_Master_Transmit+0x1f4>)
- 800399a:	68f8      	ldr	r0, [r7, #12]
- 800399c:	f000 fc9e 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 80039a0:	4603      	mov	r3, r0
- 80039a2:	2b00      	cmp	r3, #0
- 80039a4:	d001      	beq.n	80039aa <HAL_I2C_Master_Transmit+0x42>
+ 8004db8:	697b      	ldr	r3, [r7, #20]
+ 8004dba:	9300      	str	r3, [sp, #0]
+ 8004dbc:	2319      	movs	r3, #25
+ 8004dbe:	2201      	movs	r2, #1
+ 8004dc0:	4970      	ldr	r1, [pc, #448]	@ (8004f84 <HAL_I2C_Master_Transmit+0x1f4>)
+ 8004dc2:	68f8      	ldr	r0, [r7, #12]
+ 8004dc4:	f000 fc9e 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 8004dc8:	4603      	mov	r3, r0
+ 8004dca:	2b00      	cmp	r3, #0
+ 8004dcc:	d001      	beq.n	8004dd2 <HAL_I2C_Master_Transmit+0x42>
     {
       return HAL_BUSY;
- 80039a6:	2302      	movs	r3, #2
- 80039a8:	e0d3      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
+ 8004dce:	2302      	movs	r3, #2
+ 8004dd0:	e0d3      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
- 80039aa:	68fb      	ldr	r3, [r7, #12]
- 80039ac:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
- 80039b0:	2b01      	cmp	r3, #1
- 80039b2:	d101      	bne.n	80039b8 <HAL_I2C_Master_Transmit+0x50>
- 80039b4:	2302      	movs	r3, #2
- 80039b6:	e0cc      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
- 80039b8:	68fb      	ldr	r3, [r7, #12]
- 80039ba:	2201      	movs	r2, #1
- 80039bc:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8004dd2:	68fb      	ldr	r3, [r7, #12]
+ 8004dd4:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 8004dd8:	2b01      	cmp	r3, #1
+ 8004dda:	d101      	bne.n	8004de0 <HAL_I2C_Master_Transmit+0x50>
+ 8004ddc:	2302      	movs	r3, #2
+ 8004dde:	e0cc      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
+ 8004de0:	68fb      	ldr	r3, [r7, #12]
+ 8004de2:	2201      	movs	r2, #1
+ 8004de4:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     /* Check if the I2C is already enabled */
     if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- 80039c0:	68fb      	ldr	r3, [r7, #12]
- 80039c2:	681b      	ldr	r3, [r3, #0]
- 80039c4:	681b      	ldr	r3, [r3, #0]
- 80039c6:	f003 0301 	and.w	r3, r3, #1
- 80039ca:	2b01      	cmp	r3, #1
- 80039cc:	d007      	beq.n	80039de <HAL_I2C_Master_Transmit+0x76>
+ 8004de8:	68fb      	ldr	r3, [r7, #12]
+ 8004dea:	681b      	ldr	r3, [r3, #0]
+ 8004dec:	681b      	ldr	r3, [r3, #0]
+ 8004dee:	f003 0301 	and.w	r3, r3, #1
+ 8004df2:	2b01      	cmp	r3, #1
+ 8004df4:	d007      	beq.n	8004e06 <HAL_I2C_Master_Transmit+0x76>
     {
       /* Enable I2C peripheral */
       __HAL_I2C_ENABLE(hi2c);
- 80039ce:	68fb      	ldr	r3, [r7, #12]
- 80039d0:	681b      	ldr	r3, [r3, #0]
- 80039d2:	681a      	ldr	r2, [r3, #0]
- 80039d4:	68fb      	ldr	r3, [r7, #12]
- 80039d6:	681b      	ldr	r3, [r3, #0]
- 80039d8:	f042 0201 	orr.w	r2, r2, #1
- 80039dc:	601a      	str	r2, [r3, #0]
+ 8004df6:	68fb      	ldr	r3, [r7, #12]
+ 8004df8:	681b      	ldr	r3, [r3, #0]
+ 8004dfa:	681a      	ldr	r2, [r3, #0]
+ 8004dfc:	68fb      	ldr	r3, [r7, #12]
+ 8004dfe:	681b      	ldr	r3, [r3, #0]
+ 8004e00:	f042 0201 	orr.w	r2, r2, #1
+ 8004e04:	601a      	str	r2, [r3, #0]
     }
 
     /* Disable Pos */
     CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- 80039de:	68fb      	ldr	r3, [r7, #12]
- 80039e0:	681b      	ldr	r3, [r3, #0]
- 80039e2:	681a      	ldr	r2, [r3, #0]
- 80039e4:	68fb      	ldr	r3, [r7, #12]
- 80039e6:	681b      	ldr	r3, [r3, #0]
- 80039e8:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
- 80039ec:	601a      	str	r2, [r3, #0]
+ 8004e06:	68fb      	ldr	r3, [r7, #12]
+ 8004e08:	681b      	ldr	r3, [r3, #0]
+ 8004e0a:	681a      	ldr	r2, [r3, #0]
+ 8004e0c:	68fb      	ldr	r3, [r7, #12]
+ 8004e0e:	681b      	ldr	r3, [r3, #0]
+ 8004e10:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
+ 8004e14:	601a      	str	r2, [r3, #0]
 
     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
- 80039ee:	68fb      	ldr	r3, [r7, #12]
- 80039f0:	2221      	movs	r2, #33	@ 0x21
- 80039f2:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8004e16:	68fb      	ldr	r3, [r7, #12]
+ 8004e18:	2221      	movs	r2, #33	@ 0x21
+ 8004e1a:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
     hi2c->Mode        = HAL_I2C_MODE_MASTER;
- 80039f6:	68fb      	ldr	r3, [r7, #12]
- 80039f8:	2210      	movs	r2, #16
- 80039fa:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8004e1e:	68fb      	ldr	r3, [r7, #12]
+ 8004e20:	2210      	movs	r2, #16
+ 8004e22:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
- 80039fe:	68fb      	ldr	r3, [r7, #12]
- 8003a00:	2200      	movs	r2, #0
- 8003a02:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8004e26:	68fb      	ldr	r3, [r7, #12]
+ 8004e28:	2200      	movs	r2, #0
+ 8004e2a:	641a      	str	r2, [r3, #64]	@ 0x40
 
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
- 8003a04:	68fb      	ldr	r3, [r7, #12]
- 8003a06:	687a      	ldr	r2, [r7, #4]
- 8003a08:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8004e2c:	68fb      	ldr	r3, [r7, #12]
+ 8004e2e:	687a      	ldr	r2, [r7, #4]
+ 8004e30:	625a      	str	r2, [r3, #36]	@ 0x24
     hi2c->XferCount   = Size;
- 8003a0a:	68fb      	ldr	r3, [r7, #12]
- 8003a0c:	893a      	ldrh	r2, [r7, #8]
- 8003a0e:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8004e32:	68fb      	ldr	r3, [r7, #12]
+ 8004e34:	893a      	ldrh	r2, [r7, #8]
+ 8004e36:	855a      	strh	r2, [r3, #42]	@ 0x2a
     hi2c->XferSize    = hi2c->XferCount;
- 8003a10:	68fb      	ldr	r3, [r7, #12]
- 8003a12:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003a14:	b29a      	uxth	r2, r3
- 8003a16:	68fb      	ldr	r3, [r7, #12]
- 8003a18:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8004e38:	68fb      	ldr	r3, [r7, #12]
+ 8004e3a:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8004e3c:	b29a      	uxth	r2, r3
+ 8004e3e:	68fb      	ldr	r3, [r7, #12]
+ 8004e40:	851a      	strh	r2, [r3, #40]	@ 0x28
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- 8003a1a:	68fb      	ldr	r3, [r7, #12]
- 8003a1c:	4a50      	ldr	r2, [pc, #320]	@ (8003b60 <HAL_I2C_Master_Transmit+0x1f8>)
- 8003a1e:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8004e42:	68fb      	ldr	r3, [r7, #12]
+ 8004e44:	4a50      	ldr	r2, [pc, #320]	@ (8004f88 <HAL_I2C_Master_Transmit+0x1f8>)
+ 8004e46:	62da      	str	r2, [r3, #44]	@ 0x2c
 
     /* Send Slave Address */
     if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
- 8003a20:	8979      	ldrh	r1, [r7, #10]
- 8003a22:	697b      	ldr	r3, [r7, #20]
- 8003a24:	6a3a      	ldr	r2, [r7, #32]
- 8003a26:	68f8      	ldr	r0, [r7, #12]
- 8003a28:	f000 fb08 	bl	800403c <I2C_MasterRequestWrite>
- 8003a2c:	4603      	mov	r3, r0
- 8003a2e:	2b00      	cmp	r3, #0
- 8003a30:	d001      	beq.n	8003a36 <HAL_I2C_Master_Transmit+0xce>
+ 8004e48:	8979      	ldrh	r1, [r7, #10]
+ 8004e4a:	697b      	ldr	r3, [r7, #20]
+ 8004e4c:	6a3a      	ldr	r2, [r7, #32]
+ 8004e4e:	68f8      	ldr	r0, [r7, #12]
+ 8004e50:	f000 fb08 	bl	8005464 <I2C_MasterRequestWrite>
+ 8004e54:	4603      	mov	r3, r0
+ 8004e56:	2b00      	cmp	r3, #0
+ 8004e58:	d001      	beq.n	8004e5e <HAL_I2C_Master_Transmit+0xce>
     {
       return HAL_ERROR;
- 8003a32:	2301      	movs	r3, #1
- 8003a34:	e08d      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
+ 8004e5a:	2301      	movs	r3, #1
+ 8004e5c:	e08d      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8003a36:	2300      	movs	r3, #0
- 8003a38:	613b      	str	r3, [r7, #16]
- 8003a3a:	68fb      	ldr	r3, [r7, #12]
- 8003a3c:	681b      	ldr	r3, [r3, #0]
- 8003a3e:	695b      	ldr	r3, [r3, #20]
- 8003a40:	613b      	str	r3, [r7, #16]
- 8003a42:	68fb      	ldr	r3, [r7, #12]
- 8003a44:	681b      	ldr	r3, [r3, #0]
- 8003a46:	699b      	ldr	r3, [r3, #24]
- 8003a48:	613b      	str	r3, [r7, #16]
- 8003a4a:	693b      	ldr	r3, [r7, #16]
+ 8004e5e:	2300      	movs	r3, #0
+ 8004e60:	613b      	str	r3, [r7, #16]
+ 8004e62:	68fb      	ldr	r3, [r7, #12]
+ 8004e64:	681b      	ldr	r3, [r3, #0]
+ 8004e66:	695b      	ldr	r3, [r3, #20]
+ 8004e68:	613b      	str	r3, [r7, #16]
+ 8004e6a:	68fb      	ldr	r3, [r7, #12]
+ 8004e6c:	681b      	ldr	r3, [r3, #0]
+ 8004e6e:	699b      	ldr	r3, [r3, #24]
+ 8004e70:	613b      	str	r3, [r7, #16]
+ 8004e72:	693b      	ldr	r3, [r7, #16]
 
     while (hi2c->XferSize > 0U)
- 8003a4c:	e066      	b.n	8003b1c <HAL_I2C_Master_Transmit+0x1b4>
+ 8004e74:	e066      	b.n	8004f44 <HAL_I2C_Master_Transmit+0x1b4>
     {
       /* Wait until TXE flag is set */
       if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8003a4e:	697a      	ldr	r2, [r7, #20]
- 8003a50:	6a39      	ldr	r1, [r7, #32]
- 8003a52:	68f8      	ldr	r0, [r7, #12]
- 8003a54:	f000 fd5c 	bl	8004510 <I2C_WaitOnTXEFlagUntilTimeout>
- 8003a58:	4603      	mov	r3, r0
- 8003a5a:	2b00      	cmp	r3, #0
- 8003a5c:	d00d      	beq.n	8003a7a <HAL_I2C_Master_Transmit+0x112>
+ 8004e76:	697a      	ldr	r2, [r7, #20]
+ 8004e78:	6a39      	ldr	r1, [r7, #32]
+ 8004e7a:	68f8      	ldr	r0, [r7, #12]
+ 8004e7c:	f000 fd5c 	bl	8005938 <I2C_WaitOnTXEFlagUntilTimeout>
+ 8004e80:	4603      	mov	r3, r0
+ 8004e82:	2b00      	cmp	r3, #0
+ 8004e84:	d00d      	beq.n	8004ea2 <HAL_I2C_Master_Transmit+0x112>
       {
         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- 8003a5e:	68fb      	ldr	r3, [r7, #12]
- 8003a60:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8003a62:	2b04      	cmp	r3, #4
- 8003a64:	d107      	bne.n	8003a76 <HAL_I2C_Master_Transmit+0x10e>
+ 8004e86:	68fb      	ldr	r3, [r7, #12]
+ 8004e88:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8004e8a:	2b04      	cmp	r3, #4
+ 8004e8c:	d107      	bne.n	8004e9e <HAL_I2C_Master_Transmit+0x10e>
         {
           /* Generate Stop */
           SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003a66:	68fb      	ldr	r3, [r7, #12]
- 8003a68:	681b      	ldr	r3, [r3, #0]
- 8003a6a:	681a      	ldr	r2, [r3, #0]
- 8003a6c:	68fb      	ldr	r3, [r7, #12]
- 8003a6e:	681b      	ldr	r3, [r3, #0]
- 8003a70:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003a74:	601a      	str	r2, [r3, #0]
+ 8004e8e:	68fb      	ldr	r3, [r7, #12]
+ 8004e90:	681b      	ldr	r3, [r3, #0]
+ 8004e92:	681a      	ldr	r2, [r3, #0]
+ 8004e94:	68fb      	ldr	r3, [r7, #12]
+ 8004e96:	681b      	ldr	r3, [r3, #0]
+ 8004e98:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 8004e9c:	601a      	str	r2, [r3, #0]
         }
         return HAL_ERROR;
- 8003a76:	2301      	movs	r3, #1
- 8003a78:	e06b      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
+ 8004e9e:	2301      	movs	r3, #1
+ 8004ea0:	e06b      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
       }
 
       /* Write data to DR */
       hi2c->Instance->DR = *hi2c->pBuffPtr;
- 8003a7a:	68fb      	ldr	r3, [r7, #12]
- 8003a7c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003a7e:	781a      	ldrb	r2, [r3, #0]
- 8003a80:	68fb      	ldr	r3, [r7, #12]
- 8003a82:	681b      	ldr	r3, [r3, #0]
- 8003a84:	611a      	str	r2, [r3, #16]
+ 8004ea2:	68fb      	ldr	r3, [r7, #12]
+ 8004ea4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8004ea6:	781a      	ldrb	r2, [r3, #0]
+ 8004ea8:	68fb      	ldr	r3, [r7, #12]
+ 8004eaa:	681b      	ldr	r3, [r3, #0]
+ 8004eac:	611a      	str	r2, [r3, #16]
 
       /* Increment Buffer pointer */
       hi2c->pBuffPtr++;
- 8003a86:	68fb      	ldr	r3, [r7, #12]
- 8003a88:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003a8a:	1c5a      	adds	r2, r3, #1
- 8003a8c:	68fb      	ldr	r3, [r7, #12]
- 8003a8e:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8004eae:	68fb      	ldr	r3, [r7, #12]
+ 8004eb0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8004eb2:	1c5a      	adds	r2, r3, #1
+ 8004eb4:	68fb      	ldr	r3, [r7, #12]
+ 8004eb6:	625a      	str	r2, [r3, #36]	@ 0x24
 
       /* Update counter */
       hi2c->XferCount--;
- 8003a90:	68fb      	ldr	r3, [r7, #12]
- 8003a92:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003a94:	b29b      	uxth	r3, r3
- 8003a96:	3b01      	subs	r3, #1
- 8003a98:	b29a      	uxth	r2, r3
- 8003a9a:	68fb      	ldr	r3, [r7, #12]
- 8003a9c:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8004eb8:	68fb      	ldr	r3, [r7, #12]
+ 8004eba:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8004ebc:	b29b      	uxth	r3, r3
+ 8004ebe:	3b01      	subs	r3, #1
+ 8004ec0:	b29a      	uxth	r2, r3
+ 8004ec2:	68fb      	ldr	r3, [r7, #12]
+ 8004ec4:	855a      	strh	r2, [r3, #42]	@ 0x2a
       hi2c->XferSize--;
- 8003a9e:	68fb      	ldr	r3, [r7, #12]
- 8003aa0:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003aa2:	3b01      	subs	r3, #1
- 8003aa4:	b29a      	uxth	r2, r3
- 8003aa6:	68fb      	ldr	r3, [r7, #12]
- 8003aa8:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8004ec6:	68fb      	ldr	r3, [r7, #12]
+ 8004ec8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8004eca:	3b01      	subs	r3, #1
+ 8004ecc:	b29a      	uxth	r2, r3
+ 8004ece:	68fb      	ldr	r3, [r7, #12]
+ 8004ed0:	851a      	strh	r2, [r3, #40]	@ 0x28
 
       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
- 8003aaa:	68fb      	ldr	r3, [r7, #12]
- 8003aac:	681b      	ldr	r3, [r3, #0]
- 8003aae:	695b      	ldr	r3, [r3, #20]
- 8003ab0:	f003 0304 	and.w	r3, r3, #4
- 8003ab4:	2b04      	cmp	r3, #4
- 8003ab6:	d11b      	bne.n	8003af0 <HAL_I2C_Master_Transmit+0x188>
- 8003ab8:	68fb      	ldr	r3, [r7, #12]
- 8003aba:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003abc:	2b00      	cmp	r3, #0
- 8003abe:	d017      	beq.n	8003af0 <HAL_I2C_Master_Transmit+0x188>
+ 8004ed2:	68fb      	ldr	r3, [r7, #12]
+ 8004ed4:	681b      	ldr	r3, [r3, #0]
+ 8004ed6:	695b      	ldr	r3, [r3, #20]
+ 8004ed8:	f003 0304 	and.w	r3, r3, #4
+ 8004edc:	2b04      	cmp	r3, #4
+ 8004ede:	d11b      	bne.n	8004f18 <HAL_I2C_Master_Transmit+0x188>
+ 8004ee0:	68fb      	ldr	r3, [r7, #12]
+ 8004ee2:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8004ee4:	2b00      	cmp	r3, #0
+ 8004ee6:	d017      	beq.n	8004f18 <HAL_I2C_Master_Transmit+0x188>
       {
         /* Write data to DR */
         hi2c->Instance->DR = *hi2c->pBuffPtr;
- 8003ac0:	68fb      	ldr	r3, [r7, #12]
- 8003ac2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003ac4:	781a      	ldrb	r2, [r3, #0]
- 8003ac6:	68fb      	ldr	r3, [r7, #12]
- 8003ac8:	681b      	ldr	r3, [r3, #0]
- 8003aca:	611a      	str	r2, [r3, #16]
+ 8004ee8:	68fb      	ldr	r3, [r7, #12]
+ 8004eea:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8004eec:	781a      	ldrb	r2, [r3, #0]
+ 8004eee:	68fb      	ldr	r3, [r7, #12]
+ 8004ef0:	681b      	ldr	r3, [r3, #0]
+ 8004ef2:	611a      	str	r2, [r3, #16]
 
         /* Increment Buffer pointer */
         hi2c->pBuffPtr++;
- 8003acc:	68fb      	ldr	r3, [r7, #12]
- 8003ace:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003ad0:	1c5a      	adds	r2, r3, #1
- 8003ad2:	68fb      	ldr	r3, [r7, #12]
- 8003ad4:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8004ef4:	68fb      	ldr	r3, [r7, #12]
+ 8004ef6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8004ef8:	1c5a      	adds	r2, r3, #1
+ 8004efa:	68fb      	ldr	r3, [r7, #12]
+ 8004efc:	625a      	str	r2, [r3, #36]	@ 0x24
 
         /* Update counter */
         hi2c->XferCount--;
- 8003ad6:	68fb      	ldr	r3, [r7, #12]
- 8003ad8:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003ada:	b29b      	uxth	r3, r3
- 8003adc:	3b01      	subs	r3, #1
- 8003ade:	b29a      	uxth	r2, r3
- 8003ae0:	68fb      	ldr	r3, [r7, #12]
- 8003ae2:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8004efe:	68fb      	ldr	r3, [r7, #12]
+ 8004f00:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8004f02:	b29b      	uxth	r3, r3
+ 8004f04:	3b01      	subs	r3, #1
+ 8004f06:	b29a      	uxth	r2, r3
+ 8004f08:	68fb      	ldr	r3, [r7, #12]
+ 8004f0a:	855a      	strh	r2, [r3, #42]	@ 0x2a
         hi2c->XferSize--;
- 8003ae4:	68fb      	ldr	r3, [r7, #12]
- 8003ae6:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003ae8:	3b01      	subs	r3, #1
- 8003aea:	b29a      	uxth	r2, r3
- 8003aec:	68fb      	ldr	r3, [r7, #12]
- 8003aee:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8004f0c:	68fb      	ldr	r3, [r7, #12]
+ 8004f0e:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8004f10:	3b01      	subs	r3, #1
+ 8004f12:	b29a      	uxth	r2, r3
+ 8004f14:	68fb      	ldr	r3, [r7, #12]
+ 8004f16:	851a      	strh	r2, [r3, #40]	@ 0x28
       }
 
       /* Wait until BTF flag is set */
       if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8003af0:	697a      	ldr	r2, [r7, #20]
- 8003af2:	6a39      	ldr	r1, [r7, #32]
- 8003af4:	68f8      	ldr	r0, [r7, #12]
- 8003af6:	f000 fd53 	bl	80045a0 <I2C_WaitOnBTFFlagUntilTimeout>
- 8003afa:	4603      	mov	r3, r0
- 8003afc:	2b00      	cmp	r3, #0
- 8003afe:	d00d      	beq.n	8003b1c <HAL_I2C_Master_Transmit+0x1b4>
+ 8004f18:	697a      	ldr	r2, [r7, #20]
+ 8004f1a:	6a39      	ldr	r1, [r7, #32]
+ 8004f1c:	68f8      	ldr	r0, [r7, #12]
+ 8004f1e:	f000 fd53 	bl	80059c8 <I2C_WaitOnBTFFlagUntilTimeout>
+ 8004f22:	4603      	mov	r3, r0
+ 8004f24:	2b00      	cmp	r3, #0
+ 8004f26:	d00d      	beq.n	8004f44 <HAL_I2C_Master_Transmit+0x1b4>
       {
         if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- 8003b00:	68fb      	ldr	r3, [r7, #12]
- 8003b02:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8003b04:	2b04      	cmp	r3, #4
- 8003b06:	d107      	bne.n	8003b18 <HAL_I2C_Master_Transmit+0x1b0>
+ 8004f28:	68fb      	ldr	r3, [r7, #12]
+ 8004f2a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8004f2c:	2b04      	cmp	r3, #4
+ 8004f2e:	d107      	bne.n	8004f40 <HAL_I2C_Master_Transmit+0x1b0>
         {
           /* Generate Stop */
           SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003b08:	68fb      	ldr	r3, [r7, #12]
- 8003b0a:	681b      	ldr	r3, [r3, #0]
- 8003b0c:	681a      	ldr	r2, [r3, #0]
- 8003b0e:	68fb      	ldr	r3, [r7, #12]
- 8003b10:	681b      	ldr	r3, [r3, #0]
- 8003b12:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003b16:	601a      	str	r2, [r3, #0]
+ 8004f30:	68fb      	ldr	r3, [r7, #12]
+ 8004f32:	681b      	ldr	r3, [r3, #0]
+ 8004f34:	681a      	ldr	r2, [r3, #0]
+ 8004f36:	68fb      	ldr	r3, [r7, #12]
+ 8004f38:	681b      	ldr	r3, [r3, #0]
+ 8004f3a:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 8004f3e:	601a      	str	r2, [r3, #0]
         }
         return HAL_ERROR;
- 8003b18:	2301      	movs	r3, #1
- 8003b1a:	e01a      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
+ 8004f40:	2301      	movs	r3, #1
+ 8004f42:	e01a      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
     while (hi2c->XferSize > 0U)
- 8003b1c:	68fb      	ldr	r3, [r7, #12]
- 8003b1e:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003b20:	2b00      	cmp	r3, #0
- 8003b22:	d194      	bne.n	8003a4e <HAL_I2C_Master_Transmit+0xe6>
+ 8004f44:	68fb      	ldr	r3, [r7, #12]
+ 8004f46:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8004f48:	2b00      	cmp	r3, #0
+ 8004f4a:	d194      	bne.n	8004e76 <HAL_I2C_Master_Transmit+0xe6>
       }
     }
 
     /* Generate Stop */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003b24:	68fb      	ldr	r3, [r7, #12]
- 8003b26:	681b      	ldr	r3, [r3, #0]
- 8003b28:	681a      	ldr	r2, [r3, #0]
- 8003b2a:	68fb      	ldr	r3, [r7, #12]
- 8003b2c:	681b      	ldr	r3, [r3, #0]
- 8003b2e:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003b32:	601a      	str	r2, [r3, #0]
+ 8004f4c:	68fb      	ldr	r3, [r7, #12]
+ 8004f4e:	681b      	ldr	r3, [r3, #0]
+ 8004f50:	681a      	ldr	r2, [r3, #0]
+ 8004f52:	68fb      	ldr	r3, [r7, #12]
+ 8004f54:	681b      	ldr	r3, [r3, #0]
+ 8004f56:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 8004f5a:	601a      	str	r2, [r3, #0]
 
     hi2c->State = HAL_I2C_STATE_READY;
- 8003b34:	68fb      	ldr	r3, [r7, #12]
- 8003b36:	2220      	movs	r2, #32
- 8003b38:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8004f5c:	68fb      	ldr	r3, [r7, #12]
+ 8004f5e:	2220      	movs	r2, #32
+ 8004f60:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
     hi2c->Mode = HAL_I2C_MODE_NONE;
- 8003b3c:	68fb      	ldr	r3, [r7, #12]
- 8003b3e:	2200      	movs	r2, #0
- 8003b40:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8004f64:	68fb      	ldr	r3, [r7, #12]
+ 8004f66:	2200      	movs	r2, #0
+ 8004f68:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
- 8003b44:	68fb      	ldr	r3, [r7, #12]
- 8003b46:	2200      	movs	r2, #0
- 8003b48:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8004f6c:	68fb      	ldr	r3, [r7, #12]
+ 8004f6e:	2200      	movs	r2, #0
+ 8004f70:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     return HAL_OK;
- 8003b4c:	2300      	movs	r3, #0
- 8003b4e:	e000      	b.n	8003b52 <HAL_I2C_Master_Transmit+0x1ea>
+ 8004f74:	2300      	movs	r3, #0
+ 8004f76:	e000      	b.n	8004f7a <HAL_I2C_Master_Transmit+0x1ea>
   }
   else
   {
     return HAL_BUSY;
- 8003b50:	2302      	movs	r3, #2
+ 8004f78:	2302      	movs	r3, #2
   }
 }
- 8003b52:	4618      	mov	r0, r3
- 8003b54:	3718      	adds	r7, #24
- 8003b56:	46bd      	mov	sp, r7
- 8003b58:	bd80      	pop	{r7, pc}
- 8003b5a:	bf00      	nop
- 8003b5c:	00100002 	.word	0x00100002
- 8003b60:	ffff0000 	.word	0xffff0000
+ 8004f7a:	4618      	mov	r0, r3
+ 8004f7c:	3718      	adds	r7, #24
+ 8004f7e:	46bd      	mov	sp, r7
+ 8004f80:	bd80      	pop	{r7, pc}
+ 8004f82:	bf00      	nop
+ 8004f84:	00100002 	.word	0x00100002
+ 8004f88:	ffff0000 	.word	0xffff0000
 
-08003b64 <HAL_I2C_Master_Receive>:
+08004f8c <HAL_I2C_Master_Receive>:
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
- 8003b64:	b580      	push	{r7, lr}
- 8003b66:	b08c      	sub	sp, #48	@ 0x30
- 8003b68:	af02      	add	r7, sp, #8
- 8003b6a:	60f8      	str	r0, [r7, #12]
- 8003b6c:	607a      	str	r2, [r7, #4]
- 8003b6e:	461a      	mov	r2, r3
- 8003b70:	460b      	mov	r3, r1
- 8003b72:	817b      	strh	r3, [r7, #10]
- 8003b74:	4613      	mov	r3, r2
- 8003b76:	813b      	strh	r3, [r7, #8]
+ 8004f8c:	b580      	push	{r7, lr}
+ 8004f8e:	b08c      	sub	sp, #48	@ 0x30
+ 8004f90:	af02      	add	r7, sp, #8
+ 8004f92:	60f8      	str	r0, [r7, #12]
+ 8004f94:	607a      	str	r2, [r7, #4]
+ 8004f96:	461a      	mov	r2, r3
+ 8004f98:	460b      	mov	r3, r1
+ 8004f9a:	817b      	strh	r3, [r7, #10]
+ 8004f9c:	4613      	mov	r3, r2
+ 8004f9e:	813b      	strh	r3, [r7, #8]
   __IO uint32_t count = 0U;
- 8003b78:	2300      	movs	r3, #0
- 8003b7a:	623b      	str	r3, [r7, #32]
+ 8004fa0:	2300      	movs	r3, #0
+ 8004fa2:	623b      	str	r3, [r7, #32]
 
   /* Init tickstart for timeout management*/
   uint32_t tickstart = HAL_GetTick();
- 8003b7c:	f7fe ffe4 	bl	8002b48 <HAL_GetTick>
- 8003b80:	6278      	str	r0, [r7, #36]	@ 0x24
+ 8004fa4:	f7fe f996 	bl	80032d4 <HAL_GetTick>
+ 8004fa8:	6278      	str	r0, [r7, #36]	@ 0x24
 
   if (hi2c->State == HAL_I2C_STATE_READY)
- 8003b82:	68fb      	ldr	r3, [r7, #12]
- 8003b84:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
- 8003b88:	b2db      	uxtb	r3, r3
- 8003b8a:	2b20      	cmp	r3, #32
- 8003b8c:	f040 824b 	bne.w	8004026 <HAL_I2C_Master_Receive+0x4c2>
+ 8004faa:	68fb      	ldr	r3, [r7, #12]
+ 8004fac:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 8004fb0:	b2db      	uxtb	r3, r3
+ 8004fb2:	2b20      	cmp	r3, #32
+ 8004fb4:	f040 824b 	bne.w	800544e <HAL_I2C_Master_Receive+0x4c2>
   {
     /* Wait until BUSY flag is reset */
     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- 8003b90:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003b92:	9300      	str	r3, [sp, #0]
- 8003b94:	2319      	movs	r3, #25
- 8003b96:	2201      	movs	r2, #1
- 8003b98:	497f      	ldr	r1, [pc, #508]	@ (8003d98 <HAL_I2C_Master_Receive+0x234>)
- 8003b9a:	68f8      	ldr	r0, [r7, #12]
- 8003b9c:	f000 fb9e 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 8003ba0:	4603      	mov	r3, r0
- 8003ba2:	2b00      	cmp	r3, #0
- 8003ba4:	d001      	beq.n	8003baa <HAL_I2C_Master_Receive+0x46>
+ 8004fb8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8004fba:	9300      	str	r3, [sp, #0]
+ 8004fbc:	2319      	movs	r3, #25
+ 8004fbe:	2201      	movs	r2, #1
+ 8004fc0:	497f      	ldr	r1, [pc, #508]	@ (80051c0 <HAL_I2C_Master_Receive+0x234>)
+ 8004fc2:	68f8      	ldr	r0, [r7, #12]
+ 8004fc4:	f000 fb9e 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 8004fc8:	4603      	mov	r3, r0
+ 8004fca:	2b00      	cmp	r3, #0
+ 8004fcc:	d001      	beq.n	8004fd2 <HAL_I2C_Master_Receive+0x46>
     {
       return HAL_BUSY;
- 8003ba6:	2302      	movs	r3, #2
- 8003ba8:	e23e      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 8004fce:	2302      	movs	r3, #2
+ 8004fd0:	e23e      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
- 8003baa:	68fb      	ldr	r3, [r7, #12]
- 8003bac:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
- 8003bb0:	2b01      	cmp	r3, #1
- 8003bb2:	d101      	bne.n	8003bb8 <HAL_I2C_Master_Receive+0x54>
- 8003bb4:	2302      	movs	r3, #2
- 8003bb6:	e237      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
- 8003bb8:	68fb      	ldr	r3, [r7, #12]
- 8003bba:	2201      	movs	r2, #1
- 8003bbc:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8004fd2:	68fb      	ldr	r3, [r7, #12]
+ 8004fd4:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 8004fd8:	2b01      	cmp	r3, #1
+ 8004fda:	d101      	bne.n	8004fe0 <HAL_I2C_Master_Receive+0x54>
+ 8004fdc:	2302      	movs	r3, #2
+ 8004fde:	e237      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
+ 8004fe0:	68fb      	ldr	r3, [r7, #12]
+ 8004fe2:	2201      	movs	r2, #1
+ 8004fe4:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     /* Check if the I2C is already enabled */
     if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- 8003bc0:	68fb      	ldr	r3, [r7, #12]
- 8003bc2:	681b      	ldr	r3, [r3, #0]
- 8003bc4:	681b      	ldr	r3, [r3, #0]
- 8003bc6:	f003 0301 	and.w	r3, r3, #1
- 8003bca:	2b01      	cmp	r3, #1
- 8003bcc:	d007      	beq.n	8003bde <HAL_I2C_Master_Receive+0x7a>
+ 8004fe8:	68fb      	ldr	r3, [r7, #12]
+ 8004fea:	681b      	ldr	r3, [r3, #0]
+ 8004fec:	681b      	ldr	r3, [r3, #0]
+ 8004fee:	f003 0301 	and.w	r3, r3, #1
+ 8004ff2:	2b01      	cmp	r3, #1
+ 8004ff4:	d007      	beq.n	8005006 <HAL_I2C_Master_Receive+0x7a>
     {
       /* Enable I2C peripheral */
       __HAL_I2C_ENABLE(hi2c);
- 8003bce:	68fb      	ldr	r3, [r7, #12]
- 8003bd0:	681b      	ldr	r3, [r3, #0]
- 8003bd2:	681a      	ldr	r2, [r3, #0]
- 8003bd4:	68fb      	ldr	r3, [r7, #12]
- 8003bd6:	681b      	ldr	r3, [r3, #0]
- 8003bd8:	f042 0201 	orr.w	r2, r2, #1
- 8003bdc:	601a      	str	r2, [r3, #0]
+ 8004ff6:	68fb      	ldr	r3, [r7, #12]
+ 8004ff8:	681b      	ldr	r3, [r3, #0]
+ 8004ffa:	681a      	ldr	r2, [r3, #0]
+ 8004ffc:	68fb      	ldr	r3, [r7, #12]
+ 8004ffe:	681b      	ldr	r3, [r3, #0]
+ 8005000:	f042 0201 	orr.w	r2, r2, #1
+ 8005004:	601a      	str	r2, [r3, #0]
     }
 
     /* Disable Pos */
     CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- 8003bde:	68fb      	ldr	r3, [r7, #12]
- 8003be0:	681b      	ldr	r3, [r3, #0]
- 8003be2:	681a      	ldr	r2, [r3, #0]
- 8003be4:	68fb      	ldr	r3, [r7, #12]
- 8003be6:	681b      	ldr	r3, [r3, #0]
- 8003be8:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
- 8003bec:	601a      	str	r2, [r3, #0]
+ 8005006:	68fb      	ldr	r3, [r7, #12]
+ 8005008:	681b      	ldr	r3, [r3, #0]
+ 800500a:	681a      	ldr	r2, [r3, #0]
+ 800500c:	68fb      	ldr	r3, [r7, #12]
+ 800500e:	681b      	ldr	r3, [r3, #0]
+ 8005010:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
+ 8005014:	601a      	str	r2, [r3, #0]
 
     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
- 8003bee:	68fb      	ldr	r3, [r7, #12]
- 8003bf0:	2222      	movs	r2, #34	@ 0x22
- 8003bf2:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005016:	68fb      	ldr	r3, [r7, #12]
+ 8005018:	2222      	movs	r2, #34	@ 0x22
+ 800501a:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
     hi2c->Mode        = HAL_I2C_MODE_MASTER;
- 8003bf6:	68fb      	ldr	r3, [r7, #12]
- 8003bf8:	2210      	movs	r2, #16
- 8003bfa:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 800501e:	68fb      	ldr	r3, [r7, #12]
+ 8005020:	2210      	movs	r2, #16
+ 8005022:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
- 8003bfe:	68fb      	ldr	r3, [r7, #12]
- 8003c00:	2200      	movs	r2, #0
- 8003c02:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005026:	68fb      	ldr	r3, [r7, #12]
+ 8005028:	2200      	movs	r2, #0
+ 800502a:	641a      	str	r2, [r3, #64]	@ 0x40
 
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
- 8003c04:	68fb      	ldr	r3, [r7, #12]
- 8003c06:	687a      	ldr	r2, [r7, #4]
- 8003c08:	625a      	str	r2, [r3, #36]	@ 0x24
+ 800502c:	68fb      	ldr	r3, [r7, #12]
+ 800502e:	687a      	ldr	r2, [r7, #4]
+ 8005030:	625a      	str	r2, [r3, #36]	@ 0x24
     hi2c->XferCount   = Size;
- 8003c0a:	68fb      	ldr	r3, [r7, #12]
- 8003c0c:	893a      	ldrh	r2, [r7, #8]
- 8003c0e:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8005032:	68fb      	ldr	r3, [r7, #12]
+ 8005034:	893a      	ldrh	r2, [r7, #8]
+ 8005036:	855a      	strh	r2, [r3, #42]	@ 0x2a
     hi2c->XferSize    = hi2c->XferCount;
- 8003c10:	68fb      	ldr	r3, [r7, #12]
- 8003c12:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003c14:	b29a      	uxth	r2, r3
- 8003c16:	68fb      	ldr	r3, [r7, #12]
- 8003c18:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8005038:	68fb      	ldr	r3, [r7, #12]
+ 800503a:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 800503c:	b29a      	uxth	r2, r3
+ 800503e:	68fb      	ldr	r3, [r7, #12]
+ 8005040:	851a      	strh	r2, [r3, #40]	@ 0x28
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- 8003c1a:	68fb      	ldr	r3, [r7, #12]
- 8003c1c:	4a5f      	ldr	r2, [pc, #380]	@ (8003d9c <HAL_I2C_Master_Receive+0x238>)
- 8003c1e:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8005042:	68fb      	ldr	r3, [r7, #12]
+ 8005044:	4a5f      	ldr	r2, [pc, #380]	@ (80051c4 <HAL_I2C_Master_Receive+0x238>)
+ 8005046:	62da      	str	r2, [r3, #44]	@ 0x2c
 
     /* Send Slave Address */
     if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
- 8003c20:	8979      	ldrh	r1, [r7, #10]
- 8003c22:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003c24:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
- 8003c26:	68f8      	ldr	r0, [r7, #12]
- 8003c28:	f000 fa8a 	bl	8004140 <I2C_MasterRequestRead>
- 8003c2c:	4603      	mov	r3, r0
- 8003c2e:	2b00      	cmp	r3, #0
- 8003c30:	d001      	beq.n	8003c36 <HAL_I2C_Master_Receive+0xd2>
+ 8005048:	8979      	ldrh	r1, [r7, #10]
+ 800504a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 800504c:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 800504e:	68f8      	ldr	r0, [r7, #12]
+ 8005050:	f000 fa8a 	bl	8005568 <I2C_MasterRequestRead>
+ 8005054:	4603      	mov	r3, r0
+ 8005056:	2b00      	cmp	r3, #0
+ 8005058:	d001      	beq.n	800505e <HAL_I2C_Master_Receive+0xd2>
     {
       return HAL_ERROR;
- 8003c32:	2301      	movs	r3, #1
- 8003c34:	e1f8      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 800505a:	2301      	movs	r3, #1
+ 800505c:	e1f8      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
     }
 
     if (hi2c->XferSize == 0U)
- 8003c36:	68fb      	ldr	r3, [r7, #12]
- 8003c38:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003c3a:	2b00      	cmp	r3, #0
- 8003c3c:	d113      	bne.n	8003c66 <HAL_I2C_Master_Receive+0x102>
+ 800505e:	68fb      	ldr	r3, [r7, #12]
+ 8005060:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005062:	2b00      	cmp	r3, #0
+ 8005064:	d113      	bne.n	800508e <HAL_I2C_Master_Receive+0x102>
     {
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8003c3e:	2300      	movs	r3, #0
- 8003c40:	61fb      	str	r3, [r7, #28]
- 8003c42:	68fb      	ldr	r3, [r7, #12]
- 8003c44:	681b      	ldr	r3, [r3, #0]
- 8003c46:	695b      	ldr	r3, [r3, #20]
- 8003c48:	61fb      	str	r3, [r7, #28]
- 8003c4a:	68fb      	ldr	r3, [r7, #12]
- 8003c4c:	681b      	ldr	r3, [r3, #0]
- 8003c4e:	699b      	ldr	r3, [r3, #24]
- 8003c50:	61fb      	str	r3, [r7, #28]
- 8003c52:	69fb      	ldr	r3, [r7, #28]
+ 8005066:	2300      	movs	r3, #0
+ 8005068:	61fb      	str	r3, [r7, #28]
+ 800506a:	68fb      	ldr	r3, [r7, #12]
+ 800506c:	681b      	ldr	r3, [r3, #0]
+ 800506e:	695b      	ldr	r3, [r3, #20]
+ 8005070:	61fb      	str	r3, [r7, #28]
+ 8005072:	68fb      	ldr	r3, [r7, #12]
+ 8005074:	681b      	ldr	r3, [r3, #0]
+ 8005076:	699b      	ldr	r3, [r3, #24]
+ 8005078:	61fb      	str	r3, [r7, #28]
+ 800507a:	69fb      	ldr	r3, [r7, #28]
 
       /* Generate Stop */
       SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003c54:	68fb      	ldr	r3, [r7, #12]
- 8003c56:	681b      	ldr	r3, [r3, #0]
- 8003c58:	681a      	ldr	r2, [r3, #0]
- 8003c5a:	68fb      	ldr	r3, [r7, #12]
- 8003c5c:	681b      	ldr	r3, [r3, #0]
- 8003c5e:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003c62:	601a      	str	r2, [r3, #0]
- 8003c64:	e1cc      	b.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 800507c:	68fb      	ldr	r3, [r7, #12]
+ 800507e:	681b      	ldr	r3, [r3, #0]
+ 8005080:	681a      	ldr	r2, [r3, #0]
+ 8005082:	68fb      	ldr	r3, [r7, #12]
+ 8005084:	681b      	ldr	r3, [r3, #0]
+ 8005086:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 800508a:	601a      	str	r2, [r3, #0]
+ 800508c:	e1cc      	b.n	8005428 <HAL_I2C_Master_Receive+0x49c>
     }
     else if (hi2c->XferSize == 1U)
- 8003c66:	68fb      	ldr	r3, [r7, #12]
- 8003c68:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003c6a:	2b01      	cmp	r3, #1
- 8003c6c:	d11e      	bne.n	8003cac <HAL_I2C_Master_Receive+0x148>
+ 800508e:	68fb      	ldr	r3, [r7, #12]
+ 8005090:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005092:	2b01      	cmp	r3, #1
+ 8005094:	d11e      	bne.n	80050d4 <HAL_I2C_Master_Receive+0x148>
     {
       /* Disable Acknowledge */
       CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8003c6e:	68fb      	ldr	r3, [r7, #12]
- 8003c70:	681b      	ldr	r3, [r3, #0]
- 8003c72:	681a      	ldr	r2, [r3, #0]
- 8003c74:	68fb      	ldr	r3, [r7, #12]
- 8003c76:	681b      	ldr	r3, [r3, #0]
- 8003c78:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
- 8003c7c:	601a      	str	r2, [r3, #0]
+ 8005096:	68fb      	ldr	r3, [r7, #12]
+ 8005098:	681b      	ldr	r3, [r3, #0]
+ 800509a:	681a      	ldr	r2, [r3, #0]
+ 800509c:	68fb      	ldr	r3, [r7, #12]
+ 800509e:	681b      	ldr	r3, [r3, #0]
+ 80050a0:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
+ 80050a4:	601a      	str	r2, [r3, #0]
   __ASM volatile ("cpsid i" : : : "memory");
- 8003c7e:	b672      	cpsid	i
+ 80050a6:	b672      	cpsid	i
 }
- 8003c80:	bf00      	nop
+ 80050a8:	bf00      	nop
       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
       software sequence must complete before the current byte end of transfer */
       __disable_irq();
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8003c82:	2300      	movs	r3, #0
- 8003c84:	61bb      	str	r3, [r7, #24]
- 8003c86:	68fb      	ldr	r3, [r7, #12]
- 8003c88:	681b      	ldr	r3, [r3, #0]
- 8003c8a:	695b      	ldr	r3, [r3, #20]
- 8003c8c:	61bb      	str	r3, [r7, #24]
- 8003c8e:	68fb      	ldr	r3, [r7, #12]
- 8003c90:	681b      	ldr	r3, [r3, #0]
- 8003c92:	699b      	ldr	r3, [r3, #24]
- 8003c94:	61bb      	str	r3, [r7, #24]
- 8003c96:	69bb      	ldr	r3, [r7, #24]
+ 80050aa:	2300      	movs	r3, #0
+ 80050ac:	61bb      	str	r3, [r7, #24]
+ 80050ae:	68fb      	ldr	r3, [r7, #12]
+ 80050b0:	681b      	ldr	r3, [r3, #0]
+ 80050b2:	695b      	ldr	r3, [r3, #20]
+ 80050b4:	61bb      	str	r3, [r7, #24]
+ 80050b6:	68fb      	ldr	r3, [r7, #12]
+ 80050b8:	681b      	ldr	r3, [r3, #0]
+ 80050ba:	699b      	ldr	r3, [r3, #24]
+ 80050bc:	61bb      	str	r3, [r7, #24]
+ 80050be:	69bb      	ldr	r3, [r7, #24]
 
       /* Generate Stop */
       SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003c98:	68fb      	ldr	r3, [r7, #12]
- 8003c9a:	681b      	ldr	r3, [r3, #0]
- 8003c9c:	681a      	ldr	r2, [r3, #0]
- 8003c9e:	68fb      	ldr	r3, [r7, #12]
- 8003ca0:	681b      	ldr	r3, [r3, #0]
- 8003ca2:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003ca6:	601a      	str	r2, [r3, #0]
+ 80050c0:	68fb      	ldr	r3, [r7, #12]
+ 80050c2:	681b      	ldr	r3, [r3, #0]
+ 80050c4:	681a      	ldr	r2, [r3, #0]
+ 80050c6:	68fb      	ldr	r3, [r7, #12]
+ 80050c8:	681b      	ldr	r3, [r3, #0]
+ 80050ca:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 80050ce:	601a      	str	r2, [r3, #0]
   __ASM volatile ("cpsie i" : : : "memory");
- 8003ca8:	b662      	cpsie	i
+ 80050d0:	b662      	cpsie	i
 }
- 8003caa:	e035      	b.n	8003d18 <HAL_I2C_Master_Receive+0x1b4>
+ 80050d2:	e035      	b.n	8005140 <HAL_I2C_Master_Receive+0x1b4>
 
       /* Re-enable IRQs */
       __enable_irq();
     }
     else if (hi2c->XferSize == 2U)
- 8003cac:	68fb      	ldr	r3, [r7, #12]
- 8003cae:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003cb0:	2b02      	cmp	r3, #2
- 8003cb2:	d11e      	bne.n	8003cf2 <HAL_I2C_Master_Receive+0x18e>
+ 80050d4:	68fb      	ldr	r3, [r7, #12]
+ 80050d6:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80050d8:	2b02      	cmp	r3, #2
+ 80050da:	d11e      	bne.n	800511a <HAL_I2C_Master_Receive+0x18e>
     {
       /* Enable Pos */
       SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- 8003cb4:	68fb      	ldr	r3, [r7, #12]
- 8003cb6:	681b      	ldr	r3, [r3, #0]
- 8003cb8:	681a      	ldr	r2, [r3, #0]
- 8003cba:	68fb      	ldr	r3, [r7, #12]
- 8003cbc:	681b      	ldr	r3, [r3, #0]
- 8003cbe:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
- 8003cc2:	601a      	str	r2, [r3, #0]
+ 80050dc:	68fb      	ldr	r3, [r7, #12]
+ 80050de:	681b      	ldr	r3, [r3, #0]
+ 80050e0:	681a      	ldr	r2, [r3, #0]
+ 80050e2:	68fb      	ldr	r3, [r7, #12]
+ 80050e4:	681b      	ldr	r3, [r3, #0]
+ 80050e6:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
+ 80050ea:	601a      	str	r2, [r3, #0]
   __ASM volatile ("cpsid i" : : : "memory");
- 8003cc4:	b672      	cpsid	i
+ 80050ec:	b672      	cpsid	i
 }
- 8003cc6:	bf00      	nop
+ 80050ee:	bf00      	nop
       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
       software sequence must complete before the current byte end of transfer */
       __disable_irq();
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8003cc8:	2300      	movs	r3, #0
- 8003cca:	617b      	str	r3, [r7, #20]
- 8003ccc:	68fb      	ldr	r3, [r7, #12]
- 8003cce:	681b      	ldr	r3, [r3, #0]
- 8003cd0:	695b      	ldr	r3, [r3, #20]
- 8003cd2:	617b      	str	r3, [r7, #20]
- 8003cd4:	68fb      	ldr	r3, [r7, #12]
- 8003cd6:	681b      	ldr	r3, [r3, #0]
- 8003cd8:	699b      	ldr	r3, [r3, #24]
- 8003cda:	617b      	str	r3, [r7, #20]
- 8003cdc:	697b      	ldr	r3, [r7, #20]
+ 80050f0:	2300      	movs	r3, #0
+ 80050f2:	617b      	str	r3, [r7, #20]
+ 80050f4:	68fb      	ldr	r3, [r7, #12]
+ 80050f6:	681b      	ldr	r3, [r3, #0]
+ 80050f8:	695b      	ldr	r3, [r3, #20]
+ 80050fa:	617b      	str	r3, [r7, #20]
+ 80050fc:	68fb      	ldr	r3, [r7, #12]
+ 80050fe:	681b      	ldr	r3, [r3, #0]
+ 8005100:	699b      	ldr	r3, [r3, #24]
+ 8005102:	617b      	str	r3, [r7, #20]
+ 8005104:	697b      	ldr	r3, [r7, #20]
 
       /* Disable Acknowledge */
       CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8003cde:	68fb      	ldr	r3, [r7, #12]
- 8003ce0:	681b      	ldr	r3, [r3, #0]
- 8003ce2:	681a      	ldr	r2, [r3, #0]
- 8003ce4:	68fb      	ldr	r3, [r7, #12]
- 8003ce6:	681b      	ldr	r3, [r3, #0]
- 8003ce8:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
- 8003cec:	601a      	str	r2, [r3, #0]
+ 8005106:	68fb      	ldr	r3, [r7, #12]
+ 8005108:	681b      	ldr	r3, [r3, #0]
+ 800510a:	681a      	ldr	r2, [r3, #0]
+ 800510c:	68fb      	ldr	r3, [r7, #12]
+ 800510e:	681b      	ldr	r3, [r3, #0]
+ 8005110:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
+ 8005114:	601a      	str	r2, [r3, #0]
   __ASM volatile ("cpsie i" : : : "memory");
- 8003cee:	b662      	cpsie	i
+ 8005116:	b662      	cpsie	i
 }
- 8003cf0:	e012      	b.n	8003d18 <HAL_I2C_Master_Receive+0x1b4>
+ 8005118:	e012      	b.n	8005140 <HAL_I2C_Master_Receive+0x1b4>
       __enable_irq();
     }
     else
     {
       /* Enable Acknowledge */
       SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8003cf2:	68fb      	ldr	r3, [r7, #12]
- 8003cf4:	681b      	ldr	r3, [r3, #0]
- 8003cf6:	681a      	ldr	r2, [r3, #0]
- 8003cf8:	68fb      	ldr	r3, [r7, #12]
- 8003cfa:	681b      	ldr	r3, [r3, #0]
- 8003cfc:	f442 6280 	orr.w	r2, r2, #1024	@ 0x400
- 8003d00:	601a      	str	r2, [r3, #0]
+ 800511a:	68fb      	ldr	r3, [r7, #12]
+ 800511c:	681b      	ldr	r3, [r3, #0]
+ 800511e:	681a      	ldr	r2, [r3, #0]
+ 8005120:	68fb      	ldr	r3, [r7, #12]
+ 8005122:	681b      	ldr	r3, [r3, #0]
+ 8005124:	f442 6280 	orr.w	r2, r2, #1024	@ 0x400
+ 8005128:	601a      	str	r2, [r3, #0]
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8003d02:	2300      	movs	r3, #0
- 8003d04:	613b      	str	r3, [r7, #16]
- 8003d06:	68fb      	ldr	r3, [r7, #12]
- 8003d08:	681b      	ldr	r3, [r3, #0]
- 8003d0a:	695b      	ldr	r3, [r3, #20]
- 8003d0c:	613b      	str	r3, [r7, #16]
- 8003d0e:	68fb      	ldr	r3, [r7, #12]
- 8003d10:	681b      	ldr	r3, [r3, #0]
- 8003d12:	699b      	ldr	r3, [r3, #24]
- 8003d14:	613b      	str	r3, [r7, #16]
- 8003d16:	693b      	ldr	r3, [r7, #16]
+ 800512a:	2300      	movs	r3, #0
+ 800512c:	613b      	str	r3, [r7, #16]
+ 800512e:	68fb      	ldr	r3, [r7, #12]
+ 8005130:	681b      	ldr	r3, [r3, #0]
+ 8005132:	695b      	ldr	r3, [r3, #20]
+ 8005134:	613b      	str	r3, [r7, #16]
+ 8005136:	68fb      	ldr	r3, [r7, #12]
+ 8005138:	681b      	ldr	r3, [r3, #0]
+ 800513a:	699b      	ldr	r3, [r3, #24]
+ 800513c:	613b      	str	r3, [r7, #16]
+ 800513e:	693b      	ldr	r3, [r7, #16]
     }
 
     while (hi2c->XferSize > 0U)
- 8003d18:	e172      	b.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 8005140:	e172      	b.n	8005428 <HAL_I2C_Master_Receive+0x49c>
     {
       if (hi2c->XferSize <= 3U)
- 8003d1a:	68fb      	ldr	r3, [r7, #12]
- 8003d1c:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003d1e:	2b03      	cmp	r3, #3
- 8003d20:	f200 811f 	bhi.w	8003f62 <HAL_I2C_Master_Receive+0x3fe>
+ 8005142:	68fb      	ldr	r3, [r7, #12]
+ 8005144:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005146:	2b03      	cmp	r3, #3
+ 8005148:	f200 811f 	bhi.w	800538a <HAL_I2C_Master_Receive+0x3fe>
       {
         /* One byte */
         if (hi2c->XferSize == 1U)
- 8003d24:	68fb      	ldr	r3, [r7, #12]
- 8003d26:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003d28:	2b01      	cmp	r3, #1
- 8003d2a:	d123      	bne.n	8003d74 <HAL_I2C_Master_Receive+0x210>
+ 800514c:	68fb      	ldr	r3, [r7, #12]
+ 800514e:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005150:	2b01      	cmp	r3, #1
+ 8005152:	d123      	bne.n	800519c <HAL_I2C_Master_Receive+0x210>
         {
           /* Wait until RXNE flag is set */
           if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8003d2c:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 8003d2e:	6b39      	ldr	r1, [r7, #48]	@ 0x30
- 8003d30:	68f8      	ldr	r0, [r7, #12]
- 8003d32:	f000 fc7d 	bl	8004630 <I2C_WaitOnRXNEFlagUntilTimeout>
- 8003d36:	4603      	mov	r3, r0
- 8003d38:	2b00      	cmp	r3, #0
- 8003d3a:	d001      	beq.n	8003d40 <HAL_I2C_Master_Receive+0x1dc>
+ 8005154:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8005156:	6b39      	ldr	r1, [r7, #48]	@ 0x30
+ 8005158:	68f8      	ldr	r0, [r7, #12]
+ 800515a:	f000 fc7d 	bl	8005a58 <I2C_WaitOnRXNEFlagUntilTimeout>
+ 800515e:	4603      	mov	r3, r0
+ 8005160:	2b00      	cmp	r3, #0
+ 8005162:	d001      	beq.n	8005168 <HAL_I2C_Master_Receive+0x1dc>
           {
             return HAL_ERROR;
- 8003d3c:	2301      	movs	r3, #1
- 8003d3e:	e173      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 8005164:	2301      	movs	r3, #1
+ 8005166:	e173      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
           }
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003d40:	68fb      	ldr	r3, [r7, #12]
- 8003d42:	681b      	ldr	r3, [r3, #0]
- 8003d44:	691a      	ldr	r2, [r3, #16]
- 8003d46:	68fb      	ldr	r3, [r7, #12]
- 8003d48:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003d4a:	b2d2      	uxtb	r2, r2
- 8003d4c:	701a      	strb	r2, [r3, #0]
+ 8005168:	68fb      	ldr	r3, [r7, #12]
+ 800516a:	681b      	ldr	r3, [r3, #0]
+ 800516c:	691a      	ldr	r2, [r3, #16]
+ 800516e:	68fb      	ldr	r3, [r7, #12]
+ 8005170:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005172:	b2d2      	uxtb	r2, r2
+ 8005174:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003d4e:	68fb      	ldr	r3, [r7, #12]
- 8003d50:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003d52:	1c5a      	adds	r2, r3, #1
- 8003d54:	68fb      	ldr	r3, [r7, #12]
- 8003d56:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8005176:	68fb      	ldr	r3, [r7, #12]
+ 8005178:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800517a:	1c5a      	adds	r2, r3, #1
+ 800517c:	68fb      	ldr	r3, [r7, #12]
+ 800517e:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003d58:	68fb      	ldr	r3, [r7, #12]
- 8003d5a:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003d5c:	3b01      	subs	r3, #1
- 8003d5e:	b29a      	uxth	r2, r3
- 8003d60:	68fb      	ldr	r3, [r7, #12]
- 8003d62:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8005180:	68fb      	ldr	r3, [r7, #12]
+ 8005182:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005184:	3b01      	subs	r3, #1
+ 8005186:	b29a      	uxth	r2, r3
+ 8005188:	68fb      	ldr	r3, [r7, #12]
+ 800518a:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003d64:	68fb      	ldr	r3, [r7, #12]
- 8003d66:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003d68:	b29b      	uxth	r3, r3
- 8003d6a:	3b01      	subs	r3, #1
- 8003d6c:	b29a      	uxth	r2, r3
- 8003d6e:	68fb      	ldr	r3, [r7, #12]
- 8003d70:	855a      	strh	r2, [r3, #42]	@ 0x2a
- 8003d72:	e145      	b.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 800518c:	68fb      	ldr	r3, [r7, #12]
+ 800518e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8005190:	b29b      	uxth	r3, r3
+ 8005192:	3b01      	subs	r3, #1
+ 8005194:	b29a      	uxth	r2, r3
+ 8005196:	68fb      	ldr	r3, [r7, #12]
+ 8005198:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 800519a:	e145      	b.n	8005428 <HAL_I2C_Master_Receive+0x49c>
         }
         /* Two bytes */
         else if (hi2c->XferSize == 2U)
- 8003d74:	68fb      	ldr	r3, [r7, #12]
- 8003d76:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003d78:	2b02      	cmp	r3, #2
- 8003d7a:	d152      	bne.n	8003e22 <HAL_I2C_Master_Receive+0x2be>
+ 800519c:	68fb      	ldr	r3, [r7, #12]
+ 800519e:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80051a0:	2b02      	cmp	r3, #2
+ 80051a2:	d152      	bne.n	800524a <HAL_I2C_Master_Receive+0x2be>
         {
           /* Wait until BTF flag is set */
           if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- 8003d7c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003d7e:	9300      	str	r3, [sp, #0]
- 8003d80:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 8003d82:	2200      	movs	r2, #0
- 8003d84:	4906      	ldr	r1, [pc, #24]	@ (8003da0 <HAL_I2C_Master_Receive+0x23c>)
- 8003d86:	68f8      	ldr	r0, [r7, #12]
- 8003d88:	f000 faa8 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 8003d8c:	4603      	mov	r3, r0
- 8003d8e:	2b00      	cmp	r3, #0
- 8003d90:	d008      	beq.n	8003da4 <HAL_I2C_Master_Receive+0x240>
+ 80051a4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80051a6:	9300      	str	r3, [sp, #0]
+ 80051a8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 80051aa:	2200      	movs	r2, #0
+ 80051ac:	4906      	ldr	r1, [pc, #24]	@ (80051c8 <HAL_I2C_Master_Receive+0x23c>)
+ 80051ae:	68f8      	ldr	r0, [r7, #12]
+ 80051b0:	f000 faa8 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 80051b4:	4603      	mov	r3, r0
+ 80051b6:	2b00      	cmp	r3, #0
+ 80051b8:	d008      	beq.n	80051cc <HAL_I2C_Master_Receive+0x240>
           {
             return HAL_ERROR;
- 8003d92:	2301      	movs	r3, #1
- 8003d94:	e148      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
- 8003d96:	bf00      	nop
- 8003d98:	00100002 	.word	0x00100002
- 8003d9c:	ffff0000 	.word	0xffff0000
- 8003da0:	00010004 	.word	0x00010004
+ 80051ba:	2301      	movs	r3, #1
+ 80051bc:	e148      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
+ 80051be:	bf00      	nop
+ 80051c0:	00100002 	.word	0x00100002
+ 80051c4:	ffff0000 	.word	0xffff0000
+ 80051c8:	00010004 	.word	0x00010004
   __ASM volatile ("cpsid i" : : : "memory");
- 8003da4:	b672      	cpsid	i
+ 80051cc:	b672      	cpsid	i
 }
- 8003da6:	bf00      	nop
+ 80051ce:	bf00      	nop
           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
              software sequence must complete before the current byte end of transfer */
           __disable_irq();
 
           /* Generate Stop */
           SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003da8:	68fb      	ldr	r3, [r7, #12]
- 8003daa:	681b      	ldr	r3, [r3, #0]
- 8003dac:	681a      	ldr	r2, [r3, #0]
- 8003dae:	68fb      	ldr	r3, [r7, #12]
- 8003db0:	681b      	ldr	r3, [r3, #0]
- 8003db2:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003db6:	601a      	str	r2, [r3, #0]
+ 80051d0:	68fb      	ldr	r3, [r7, #12]
+ 80051d2:	681b      	ldr	r3, [r3, #0]
+ 80051d4:	681a      	ldr	r2, [r3, #0]
+ 80051d6:	68fb      	ldr	r3, [r7, #12]
+ 80051d8:	681b      	ldr	r3, [r3, #0]
+ 80051da:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 80051de:	601a      	str	r2, [r3, #0]
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003db8:	68fb      	ldr	r3, [r7, #12]
- 8003dba:	681b      	ldr	r3, [r3, #0]
- 8003dbc:	691a      	ldr	r2, [r3, #16]
- 8003dbe:	68fb      	ldr	r3, [r7, #12]
- 8003dc0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003dc2:	b2d2      	uxtb	r2, r2
- 8003dc4:	701a      	strb	r2, [r3, #0]
+ 80051e0:	68fb      	ldr	r3, [r7, #12]
+ 80051e2:	681b      	ldr	r3, [r3, #0]
+ 80051e4:	691a      	ldr	r2, [r3, #16]
+ 80051e6:	68fb      	ldr	r3, [r7, #12]
+ 80051e8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80051ea:	b2d2      	uxtb	r2, r2
+ 80051ec:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003dc6:	68fb      	ldr	r3, [r7, #12]
- 8003dc8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003dca:	1c5a      	adds	r2, r3, #1
- 8003dcc:	68fb      	ldr	r3, [r7, #12]
- 8003dce:	625a      	str	r2, [r3, #36]	@ 0x24
+ 80051ee:	68fb      	ldr	r3, [r7, #12]
+ 80051f0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80051f2:	1c5a      	adds	r2, r3, #1
+ 80051f4:	68fb      	ldr	r3, [r7, #12]
+ 80051f6:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003dd0:	68fb      	ldr	r3, [r7, #12]
- 8003dd2:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003dd4:	3b01      	subs	r3, #1
- 8003dd6:	b29a      	uxth	r2, r3
- 8003dd8:	68fb      	ldr	r3, [r7, #12]
- 8003dda:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 80051f8:	68fb      	ldr	r3, [r7, #12]
+ 80051fa:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80051fc:	3b01      	subs	r3, #1
+ 80051fe:	b29a      	uxth	r2, r3
+ 8005200:	68fb      	ldr	r3, [r7, #12]
+ 8005202:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003ddc:	68fb      	ldr	r3, [r7, #12]
- 8003dde:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003de0:	b29b      	uxth	r3, r3
- 8003de2:	3b01      	subs	r3, #1
- 8003de4:	b29a      	uxth	r2, r3
- 8003de6:	68fb      	ldr	r3, [r7, #12]
- 8003de8:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8005204:	68fb      	ldr	r3, [r7, #12]
+ 8005206:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8005208:	b29b      	uxth	r3, r3
+ 800520a:	3b01      	subs	r3, #1
+ 800520c:	b29a      	uxth	r2, r3
+ 800520e:	68fb      	ldr	r3, [r7, #12]
+ 8005210:	855a      	strh	r2, [r3, #42]	@ 0x2a
   __ASM volatile ("cpsie i" : : : "memory");
- 8003dea:	b662      	cpsie	i
+ 8005212:	b662      	cpsie	i
 }
- 8003dec:	bf00      	nop
+ 8005214:	bf00      	nop
 
           /* Re-enable IRQs */
           __enable_irq();
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003dee:	68fb      	ldr	r3, [r7, #12]
- 8003df0:	681b      	ldr	r3, [r3, #0]
- 8003df2:	691a      	ldr	r2, [r3, #16]
- 8003df4:	68fb      	ldr	r3, [r7, #12]
- 8003df6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003df8:	b2d2      	uxtb	r2, r2
- 8003dfa:	701a      	strb	r2, [r3, #0]
+ 8005216:	68fb      	ldr	r3, [r7, #12]
+ 8005218:	681b      	ldr	r3, [r3, #0]
+ 800521a:	691a      	ldr	r2, [r3, #16]
+ 800521c:	68fb      	ldr	r3, [r7, #12]
+ 800521e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005220:	b2d2      	uxtb	r2, r2
+ 8005222:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003dfc:	68fb      	ldr	r3, [r7, #12]
- 8003dfe:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003e00:	1c5a      	adds	r2, r3, #1
- 8003e02:	68fb      	ldr	r3, [r7, #12]
- 8003e04:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8005224:	68fb      	ldr	r3, [r7, #12]
+ 8005226:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005228:	1c5a      	adds	r2, r3, #1
+ 800522a:	68fb      	ldr	r3, [r7, #12]
+ 800522c:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003e06:	68fb      	ldr	r3, [r7, #12]
- 8003e08:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003e0a:	3b01      	subs	r3, #1
- 8003e0c:	b29a      	uxth	r2, r3
- 8003e0e:	68fb      	ldr	r3, [r7, #12]
- 8003e10:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 800522e:	68fb      	ldr	r3, [r7, #12]
+ 8005230:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005232:	3b01      	subs	r3, #1
+ 8005234:	b29a      	uxth	r2, r3
+ 8005236:	68fb      	ldr	r3, [r7, #12]
+ 8005238:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003e12:	68fb      	ldr	r3, [r7, #12]
- 8003e14:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003e16:	b29b      	uxth	r3, r3
- 8003e18:	3b01      	subs	r3, #1
- 8003e1a:	b29a      	uxth	r2, r3
- 8003e1c:	68fb      	ldr	r3, [r7, #12]
- 8003e1e:	855a      	strh	r2, [r3, #42]	@ 0x2a
- 8003e20:	e0ee      	b.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 800523a:	68fb      	ldr	r3, [r7, #12]
+ 800523c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 800523e:	b29b      	uxth	r3, r3
+ 8005240:	3b01      	subs	r3, #1
+ 8005242:	b29a      	uxth	r2, r3
+ 8005244:	68fb      	ldr	r3, [r7, #12]
+ 8005246:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8005248:	e0ee      	b.n	8005428 <HAL_I2C_Master_Receive+0x49c>
         }
         /* 3 Last bytes */
         else
         {
           /* Wait until BTF flag is set */
           if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- 8003e22:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8003e24:	9300      	str	r3, [sp, #0]
- 8003e26:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 8003e28:	2200      	movs	r2, #0
- 8003e2a:	4981      	ldr	r1, [pc, #516]	@ (8004030 <HAL_I2C_Master_Receive+0x4cc>)
- 8003e2c:	68f8      	ldr	r0, [r7, #12]
- 8003e2e:	f000 fa55 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 8003e32:	4603      	mov	r3, r0
- 8003e34:	2b00      	cmp	r3, #0
- 8003e36:	d001      	beq.n	8003e3c <HAL_I2C_Master_Receive+0x2d8>
+ 800524a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 800524c:	9300      	str	r3, [sp, #0]
+ 800524e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 8005250:	2200      	movs	r2, #0
+ 8005252:	4981      	ldr	r1, [pc, #516]	@ (8005458 <HAL_I2C_Master_Receive+0x4cc>)
+ 8005254:	68f8      	ldr	r0, [r7, #12]
+ 8005256:	f000 fa55 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 800525a:	4603      	mov	r3, r0
+ 800525c:	2b00      	cmp	r3, #0
+ 800525e:	d001      	beq.n	8005264 <HAL_I2C_Master_Receive+0x2d8>
           {
             return HAL_ERROR;
- 8003e38:	2301      	movs	r3, #1
- 8003e3a:	e0f5      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 8005260:	2301      	movs	r3, #1
+ 8005262:	e0f5      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
           }
 
           /* Disable Acknowledge */
           CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8003e3c:	68fb      	ldr	r3, [r7, #12]
- 8003e3e:	681b      	ldr	r3, [r3, #0]
- 8003e40:	681a      	ldr	r2, [r3, #0]
- 8003e42:	68fb      	ldr	r3, [r7, #12]
- 8003e44:	681b      	ldr	r3, [r3, #0]
- 8003e46:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
- 8003e4a:	601a      	str	r2, [r3, #0]
+ 8005264:	68fb      	ldr	r3, [r7, #12]
+ 8005266:	681b      	ldr	r3, [r3, #0]
+ 8005268:	681a      	ldr	r2, [r3, #0]
+ 800526a:	68fb      	ldr	r3, [r7, #12]
+ 800526c:	681b      	ldr	r3, [r3, #0]
+ 800526e:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
+ 8005272:	601a      	str	r2, [r3, #0]
   __ASM volatile ("cpsid i" : : : "memory");
- 8003e4c:	b672      	cpsid	i
+ 8005274:	b672      	cpsid	i
 }
- 8003e4e:	bf00      	nop
+ 8005276:	bf00      	nop
           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
              software sequence must complete before the current byte end of transfer */
           __disable_irq();
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003e50:	68fb      	ldr	r3, [r7, #12]
- 8003e52:	681b      	ldr	r3, [r3, #0]
- 8003e54:	691a      	ldr	r2, [r3, #16]
- 8003e56:	68fb      	ldr	r3, [r7, #12]
- 8003e58:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003e5a:	b2d2      	uxtb	r2, r2
- 8003e5c:	701a      	strb	r2, [r3, #0]
+ 8005278:	68fb      	ldr	r3, [r7, #12]
+ 800527a:	681b      	ldr	r3, [r3, #0]
+ 800527c:	691a      	ldr	r2, [r3, #16]
+ 800527e:	68fb      	ldr	r3, [r7, #12]
+ 8005280:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005282:	b2d2      	uxtb	r2, r2
+ 8005284:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003e5e:	68fb      	ldr	r3, [r7, #12]
- 8003e60:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003e62:	1c5a      	adds	r2, r3, #1
- 8003e64:	68fb      	ldr	r3, [r7, #12]
- 8003e66:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8005286:	68fb      	ldr	r3, [r7, #12]
+ 8005288:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800528a:	1c5a      	adds	r2, r3, #1
+ 800528c:	68fb      	ldr	r3, [r7, #12]
+ 800528e:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003e68:	68fb      	ldr	r3, [r7, #12]
- 8003e6a:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003e6c:	3b01      	subs	r3, #1
- 8003e6e:	b29a      	uxth	r2, r3
- 8003e70:	68fb      	ldr	r3, [r7, #12]
- 8003e72:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8005290:	68fb      	ldr	r3, [r7, #12]
+ 8005292:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005294:	3b01      	subs	r3, #1
+ 8005296:	b29a      	uxth	r2, r3
+ 8005298:	68fb      	ldr	r3, [r7, #12]
+ 800529a:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003e74:	68fb      	ldr	r3, [r7, #12]
- 8003e76:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003e78:	b29b      	uxth	r3, r3
- 8003e7a:	3b01      	subs	r3, #1
- 8003e7c:	b29a      	uxth	r2, r3
- 8003e7e:	68fb      	ldr	r3, [r7, #12]
- 8003e80:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 800529c:	68fb      	ldr	r3, [r7, #12]
+ 800529e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 80052a0:	b29b      	uxth	r3, r3
+ 80052a2:	3b01      	subs	r3, #1
+ 80052a4:	b29a      	uxth	r2, r3
+ 80052a6:	68fb      	ldr	r3, [r7, #12]
+ 80052a8:	855a      	strh	r2, [r3, #42]	@ 0x2a
 
           /* Wait until BTF flag is set */
           count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
- 8003e82:	4b6c      	ldr	r3, [pc, #432]	@ (8004034 <HAL_I2C_Master_Receive+0x4d0>)
- 8003e84:	681b      	ldr	r3, [r3, #0]
- 8003e86:	08db      	lsrs	r3, r3, #3
- 8003e88:	4a6b      	ldr	r2, [pc, #428]	@ (8004038 <HAL_I2C_Master_Receive+0x4d4>)
- 8003e8a:	fba2 2303 	umull	r2, r3, r2, r3
- 8003e8e:	0a1a      	lsrs	r2, r3, #8
- 8003e90:	4613      	mov	r3, r2
- 8003e92:	009b      	lsls	r3, r3, #2
- 8003e94:	4413      	add	r3, r2
- 8003e96:	00da      	lsls	r2, r3, #3
- 8003e98:	1ad3      	subs	r3, r2, r3
- 8003e9a:	623b      	str	r3, [r7, #32]
+ 80052aa:	4b6c      	ldr	r3, [pc, #432]	@ (800545c <HAL_I2C_Master_Receive+0x4d0>)
+ 80052ac:	681b      	ldr	r3, [r3, #0]
+ 80052ae:	08db      	lsrs	r3, r3, #3
+ 80052b0:	4a6b      	ldr	r2, [pc, #428]	@ (8005460 <HAL_I2C_Master_Receive+0x4d4>)
+ 80052b2:	fba2 2303 	umull	r2, r3, r2, r3
+ 80052b6:	0a1a      	lsrs	r2, r3, #8
+ 80052b8:	4613      	mov	r3, r2
+ 80052ba:	009b      	lsls	r3, r3, #2
+ 80052bc:	4413      	add	r3, r2
+ 80052be:	00da      	lsls	r2, r3, #3
+ 80052c0:	1ad3      	subs	r3, r2, r3
+ 80052c2:	623b      	str	r3, [r7, #32]
           do
           {
             count--;
- 8003e9c:	6a3b      	ldr	r3, [r7, #32]
- 8003e9e:	3b01      	subs	r3, #1
- 8003ea0:	623b      	str	r3, [r7, #32]
+ 80052c4:	6a3b      	ldr	r3, [r7, #32]
+ 80052c6:	3b01      	subs	r3, #1
+ 80052c8:	623b      	str	r3, [r7, #32]
             if (count == 0U)
- 8003ea2:	6a3b      	ldr	r3, [r7, #32]
- 8003ea4:	2b00      	cmp	r3, #0
- 8003ea6:	d118      	bne.n	8003eda <HAL_I2C_Master_Receive+0x376>
+ 80052ca:	6a3b      	ldr	r3, [r7, #32]
+ 80052cc:	2b00      	cmp	r3, #0
+ 80052ce:	d118      	bne.n	8005302 <HAL_I2C_Master_Receive+0x376>
             {
               hi2c->PreviousState       = I2C_STATE_NONE;
- 8003ea8:	68fb      	ldr	r3, [r7, #12]
- 8003eaa:	2200      	movs	r2, #0
- 8003eac:	631a      	str	r2, [r3, #48]	@ 0x30
+ 80052d0:	68fb      	ldr	r3, [r7, #12]
+ 80052d2:	2200      	movs	r2, #0
+ 80052d4:	631a      	str	r2, [r3, #48]	@ 0x30
               hi2c->State               = HAL_I2C_STATE_READY;
- 8003eae:	68fb      	ldr	r3, [r7, #12]
- 8003eb0:	2220      	movs	r2, #32
- 8003eb2:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 80052d6:	68fb      	ldr	r3, [r7, #12]
+ 80052d8:	2220      	movs	r2, #32
+ 80052da:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
               hi2c->Mode                = HAL_I2C_MODE_NONE;
- 8003eb6:	68fb      	ldr	r3, [r7, #12]
- 8003eb8:	2200      	movs	r2, #0
- 8003eba:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 80052de:	68fb      	ldr	r3, [r7, #12]
+ 80052e0:	2200      	movs	r2, #0
+ 80052e2:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
               hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
- 8003ebe:	68fb      	ldr	r3, [r7, #12]
- 8003ec0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8003ec2:	f043 0220 	orr.w	r2, r3, #32
- 8003ec6:	68fb      	ldr	r3, [r7, #12]
- 8003ec8:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80052e6:	68fb      	ldr	r3, [r7, #12]
+ 80052e8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80052ea:	f043 0220 	orr.w	r2, r3, #32
+ 80052ee:	68fb      	ldr	r3, [r7, #12]
+ 80052f0:	641a      	str	r2, [r3, #64]	@ 0x40
   __ASM volatile ("cpsie i" : : : "memory");
- 8003eca:	b662      	cpsie	i
+ 80052f2:	b662      	cpsie	i
 }
- 8003ecc:	bf00      	nop
+ 80052f4:	bf00      	nop
 
               /* Re-enable IRQs */
               __enable_irq();
 
               /* Process Unlocked */
               __HAL_UNLOCK(hi2c);
- 8003ece:	68fb      	ldr	r3, [r7, #12]
- 8003ed0:	2200      	movs	r2, #0
- 8003ed2:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 80052f6:	68fb      	ldr	r3, [r7, #12]
+ 80052f8:	2200      	movs	r2, #0
+ 80052fa:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
               return HAL_ERROR;
- 8003ed6:	2301      	movs	r3, #1
- 8003ed8:	e0a6      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 80052fe:	2301      	movs	r3, #1
+ 8005300:	e0a6      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
             }
           }
           while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
- 8003eda:	68fb      	ldr	r3, [r7, #12]
- 8003edc:	681b      	ldr	r3, [r3, #0]
- 8003ede:	695b      	ldr	r3, [r3, #20]
- 8003ee0:	f003 0304 	and.w	r3, r3, #4
- 8003ee4:	2b04      	cmp	r3, #4
- 8003ee6:	d1d9      	bne.n	8003e9c <HAL_I2C_Master_Receive+0x338>
+ 8005302:	68fb      	ldr	r3, [r7, #12]
+ 8005304:	681b      	ldr	r3, [r3, #0]
+ 8005306:	695b      	ldr	r3, [r3, #20]
+ 8005308:	f003 0304 	and.w	r3, r3, #4
+ 800530c:	2b04      	cmp	r3, #4
+ 800530e:	d1d9      	bne.n	80052c4 <HAL_I2C_Master_Receive+0x338>
 
           /* Generate Stop */
           SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 8003ee8:	68fb      	ldr	r3, [r7, #12]
- 8003eea:	681b      	ldr	r3, [r3, #0]
- 8003eec:	681a      	ldr	r2, [r3, #0]
- 8003eee:	68fb      	ldr	r3, [r7, #12]
- 8003ef0:	681b      	ldr	r3, [r3, #0]
- 8003ef2:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 8003ef6:	601a      	str	r2, [r3, #0]
+ 8005310:	68fb      	ldr	r3, [r7, #12]
+ 8005312:	681b      	ldr	r3, [r3, #0]
+ 8005314:	681a      	ldr	r2, [r3, #0]
+ 8005316:	68fb      	ldr	r3, [r7, #12]
+ 8005318:	681b      	ldr	r3, [r3, #0]
+ 800531a:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 800531e:	601a      	str	r2, [r3, #0]
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003ef8:	68fb      	ldr	r3, [r7, #12]
- 8003efa:	681b      	ldr	r3, [r3, #0]
- 8003efc:	691a      	ldr	r2, [r3, #16]
- 8003efe:	68fb      	ldr	r3, [r7, #12]
- 8003f00:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f02:	b2d2      	uxtb	r2, r2
- 8003f04:	701a      	strb	r2, [r3, #0]
+ 8005320:	68fb      	ldr	r3, [r7, #12]
+ 8005322:	681b      	ldr	r3, [r3, #0]
+ 8005324:	691a      	ldr	r2, [r3, #16]
+ 8005326:	68fb      	ldr	r3, [r7, #12]
+ 8005328:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800532a:	b2d2      	uxtb	r2, r2
+ 800532c:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003f06:	68fb      	ldr	r3, [r7, #12]
- 8003f08:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f0a:	1c5a      	adds	r2, r3, #1
- 8003f0c:	68fb      	ldr	r3, [r7, #12]
- 8003f0e:	625a      	str	r2, [r3, #36]	@ 0x24
+ 800532e:	68fb      	ldr	r3, [r7, #12]
+ 8005330:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005332:	1c5a      	adds	r2, r3, #1
+ 8005334:	68fb      	ldr	r3, [r7, #12]
+ 8005336:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003f10:	68fb      	ldr	r3, [r7, #12]
- 8003f12:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003f14:	3b01      	subs	r3, #1
- 8003f16:	b29a      	uxth	r2, r3
- 8003f18:	68fb      	ldr	r3, [r7, #12]
- 8003f1a:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8005338:	68fb      	ldr	r3, [r7, #12]
+ 800533a:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 800533c:	3b01      	subs	r3, #1
+ 800533e:	b29a      	uxth	r2, r3
+ 8005340:	68fb      	ldr	r3, [r7, #12]
+ 8005342:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003f1c:	68fb      	ldr	r3, [r7, #12]
- 8003f1e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003f20:	b29b      	uxth	r3, r3
- 8003f22:	3b01      	subs	r3, #1
- 8003f24:	b29a      	uxth	r2, r3
- 8003f26:	68fb      	ldr	r3, [r7, #12]
- 8003f28:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8005344:	68fb      	ldr	r3, [r7, #12]
+ 8005346:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8005348:	b29b      	uxth	r3, r3
+ 800534a:	3b01      	subs	r3, #1
+ 800534c:	b29a      	uxth	r2, r3
+ 800534e:	68fb      	ldr	r3, [r7, #12]
+ 8005350:	855a      	strh	r2, [r3, #42]	@ 0x2a
   __ASM volatile ("cpsie i" : : : "memory");
- 8003f2a:	b662      	cpsie	i
+ 8005352:	b662      	cpsie	i
 }
- 8003f2c:	bf00      	nop
+ 8005354:	bf00      	nop
 
           /* Re-enable IRQs */
           __enable_irq();
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003f2e:	68fb      	ldr	r3, [r7, #12]
- 8003f30:	681b      	ldr	r3, [r3, #0]
- 8003f32:	691a      	ldr	r2, [r3, #16]
- 8003f34:	68fb      	ldr	r3, [r7, #12]
- 8003f36:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f38:	b2d2      	uxtb	r2, r2
- 8003f3a:	701a      	strb	r2, [r3, #0]
+ 8005356:	68fb      	ldr	r3, [r7, #12]
+ 8005358:	681b      	ldr	r3, [r3, #0]
+ 800535a:	691a      	ldr	r2, [r3, #16]
+ 800535c:	68fb      	ldr	r3, [r7, #12]
+ 800535e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005360:	b2d2      	uxtb	r2, r2
+ 8005362:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003f3c:	68fb      	ldr	r3, [r7, #12]
- 8003f3e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f40:	1c5a      	adds	r2, r3, #1
- 8003f42:	68fb      	ldr	r3, [r7, #12]
- 8003f44:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8005364:	68fb      	ldr	r3, [r7, #12]
+ 8005366:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005368:	1c5a      	adds	r2, r3, #1
+ 800536a:	68fb      	ldr	r3, [r7, #12]
+ 800536c:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003f46:	68fb      	ldr	r3, [r7, #12]
- 8003f48:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003f4a:	3b01      	subs	r3, #1
- 8003f4c:	b29a      	uxth	r2, r3
- 8003f4e:	68fb      	ldr	r3, [r7, #12]
- 8003f50:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 800536e:	68fb      	ldr	r3, [r7, #12]
+ 8005370:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005372:	3b01      	subs	r3, #1
+ 8005374:	b29a      	uxth	r2, r3
+ 8005376:	68fb      	ldr	r3, [r7, #12]
+ 8005378:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003f52:	68fb      	ldr	r3, [r7, #12]
- 8003f54:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003f56:	b29b      	uxth	r3, r3
- 8003f58:	3b01      	subs	r3, #1
- 8003f5a:	b29a      	uxth	r2, r3
- 8003f5c:	68fb      	ldr	r3, [r7, #12]
- 8003f5e:	855a      	strh	r2, [r3, #42]	@ 0x2a
- 8003f60:	e04e      	b.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 800537a:	68fb      	ldr	r3, [r7, #12]
+ 800537c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 800537e:	b29b      	uxth	r3, r3
+ 8005380:	3b01      	subs	r3, #1
+ 8005382:	b29a      	uxth	r2, r3
+ 8005384:	68fb      	ldr	r3, [r7, #12]
+ 8005386:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 8005388:	e04e      	b.n	8005428 <HAL_I2C_Master_Receive+0x49c>
         }
       }
       else
       {
         /* Wait until RXNE flag is set */
         if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8003f62:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 8003f64:	6b39      	ldr	r1, [r7, #48]	@ 0x30
- 8003f66:	68f8      	ldr	r0, [r7, #12]
- 8003f68:	f000 fb62 	bl	8004630 <I2C_WaitOnRXNEFlagUntilTimeout>
- 8003f6c:	4603      	mov	r3, r0
- 8003f6e:	2b00      	cmp	r3, #0
- 8003f70:	d001      	beq.n	8003f76 <HAL_I2C_Master_Receive+0x412>
+ 800538a:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 800538c:	6b39      	ldr	r1, [r7, #48]	@ 0x30
+ 800538e:	68f8      	ldr	r0, [r7, #12]
+ 8005390:	f000 fb62 	bl	8005a58 <I2C_WaitOnRXNEFlagUntilTimeout>
+ 8005394:	4603      	mov	r3, r0
+ 8005396:	2b00      	cmp	r3, #0
+ 8005398:	d001      	beq.n	800539e <HAL_I2C_Master_Receive+0x412>
         {
           return HAL_ERROR;
- 8003f72:	2301      	movs	r3, #1
- 8003f74:	e058      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 800539a:	2301      	movs	r3, #1
+ 800539c:	e058      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
         }
 
         /* Read data from DR */
         *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003f76:	68fb      	ldr	r3, [r7, #12]
- 8003f78:	681b      	ldr	r3, [r3, #0]
- 8003f7a:	691a      	ldr	r2, [r3, #16]
- 8003f7c:	68fb      	ldr	r3, [r7, #12]
- 8003f7e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f80:	b2d2      	uxtb	r2, r2
- 8003f82:	701a      	strb	r2, [r3, #0]
+ 800539e:	68fb      	ldr	r3, [r7, #12]
+ 80053a0:	681b      	ldr	r3, [r3, #0]
+ 80053a2:	691a      	ldr	r2, [r3, #16]
+ 80053a4:	68fb      	ldr	r3, [r7, #12]
+ 80053a6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80053a8:	b2d2      	uxtb	r2, r2
+ 80053aa:	701a      	strb	r2, [r3, #0]
 
         /* Increment Buffer pointer */
         hi2c->pBuffPtr++;
- 8003f84:	68fb      	ldr	r3, [r7, #12]
- 8003f86:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003f88:	1c5a      	adds	r2, r3, #1
- 8003f8a:	68fb      	ldr	r3, [r7, #12]
- 8003f8c:	625a      	str	r2, [r3, #36]	@ 0x24
+ 80053ac:	68fb      	ldr	r3, [r7, #12]
+ 80053ae:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80053b0:	1c5a      	adds	r2, r3, #1
+ 80053b2:	68fb      	ldr	r3, [r7, #12]
+ 80053b4:	625a      	str	r2, [r3, #36]	@ 0x24
 
         /* Update counter */
         hi2c->XferSize--;
- 8003f8e:	68fb      	ldr	r3, [r7, #12]
- 8003f90:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003f92:	3b01      	subs	r3, #1
- 8003f94:	b29a      	uxth	r2, r3
- 8003f96:	68fb      	ldr	r3, [r7, #12]
- 8003f98:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 80053b6:	68fb      	ldr	r3, [r7, #12]
+ 80053b8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80053ba:	3b01      	subs	r3, #1
+ 80053bc:	b29a      	uxth	r2, r3
+ 80053be:	68fb      	ldr	r3, [r7, #12]
+ 80053c0:	851a      	strh	r2, [r3, #40]	@ 0x28
         hi2c->XferCount--;
- 8003f9a:	68fb      	ldr	r3, [r7, #12]
- 8003f9c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003f9e:	b29b      	uxth	r3, r3
- 8003fa0:	3b01      	subs	r3, #1
- 8003fa2:	b29a      	uxth	r2, r3
- 8003fa4:	68fb      	ldr	r3, [r7, #12]
- 8003fa6:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 80053c2:	68fb      	ldr	r3, [r7, #12]
+ 80053c4:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 80053c6:	b29b      	uxth	r3, r3
+ 80053c8:	3b01      	subs	r3, #1
+ 80053ca:	b29a      	uxth	r2, r3
+ 80053cc:	68fb      	ldr	r3, [r7, #12]
+ 80053ce:	855a      	strh	r2, [r3, #42]	@ 0x2a
 
         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
- 8003fa8:	68fb      	ldr	r3, [r7, #12]
- 8003faa:	681b      	ldr	r3, [r3, #0]
- 8003fac:	695b      	ldr	r3, [r3, #20]
- 8003fae:	f003 0304 	and.w	r3, r3, #4
- 8003fb2:	2b04      	cmp	r3, #4
- 8003fb4:	d124      	bne.n	8004000 <HAL_I2C_Master_Receive+0x49c>
+ 80053d0:	68fb      	ldr	r3, [r7, #12]
+ 80053d2:	681b      	ldr	r3, [r3, #0]
+ 80053d4:	695b      	ldr	r3, [r3, #20]
+ 80053d6:	f003 0304 	and.w	r3, r3, #4
+ 80053da:	2b04      	cmp	r3, #4
+ 80053dc:	d124      	bne.n	8005428 <HAL_I2C_Master_Receive+0x49c>
         {
 
           if (hi2c->XferSize == 3U)
- 8003fb6:	68fb      	ldr	r3, [r7, #12]
- 8003fb8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003fba:	2b03      	cmp	r3, #3
- 8003fbc:	d107      	bne.n	8003fce <HAL_I2C_Master_Receive+0x46a>
+ 80053de:	68fb      	ldr	r3, [r7, #12]
+ 80053e0:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80053e2:	2b03      	cmp	r3, #3
+ 80053e4:	d107      	bne.n	80053f6 <HAL_I2C_Master_Receive+0x46a>
           {
             /* Disable Acknowledge */
             CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8003fbe:	68fb      	ldr	r3, [r7, #12]
- 8003fc0:	681b      	ldr	r3, [r3, #0]
- 8003fc2:	681a      	ldr	r2, [r3, #0]
- 8003fc4:	68fb      	ldr	r3, [r7, #12]
- 8003fc6:	681b      	ldr	r3, [r3, #0]
- 8003fc8:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
- 8003fcc:	601a      	str	r2, [r3, #0]
+ 80053e6:	68fb      	ldr	r3, [r7, #12]
+ 80053e8:	681b      	ldr	r3, [r3, #0]
+ 80053ea:	681a      	ldr	r2, [r3, #0]
+ 80053ec:	68fb      	ldr	r3, [r7, #12]
+ 80053ee:	681b      	ldr	r3, [r3, #0]
+ 80053f0:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
+ 80053f4:	601a      	str	r2, [r3, #0]
           }
 
           /* Read data from DR */
           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
- 8003fce:	68fb      	ldr	r3, [r7, #12]
- 8003fd0:	681b      	ldr	r3, [r3, #0]
- 8003fd2:	691a      	ldr	r2, [r3, #16]
- 8003fd4:	68fb      	ldr	r3, [r7, #12]
- 8003fd6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003fd8:	b2d2      	uxtb	r2, r2
- 8003fda:	701a      	strb	r2, [r3, #0]
+ 80053f6:	68fb      	ldr	r3, [r7, #12]
+ 80053f8:	681b      	ldr	r3, [r3, #0]
+ 80053fa:	691a      	ldr	r2, [r3, #16]
+ 80053fc:	68fb      	ldr	r3, [r7, #12]
+ 80053fe:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005400:	b2d2      	uxtb	r2, r2
+ 8005402:	701a      	strb	r2, [r3, #0]
 
           /* Increment Buffer pointer */
           hi2c->pBuffPtr++;
- 8003fdc:	68fb      	ldr	r3, [r7, #12]
- 8003fde:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8003fe0:	1c5a      	adds	r2, r3, #1
- 8003fe2:	68fb      	ldr	r3, [r7, #12]
- 8003fe4:	625a      	str	r2, [r3, #36]	@ 0x24
+ 8005404:	68fb      	ldr	r3, [r7, #12]
+ 8005406:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005408:	1c5a      	adds	r2, r3, #1
+ 800540a:	68fb      	ldr	r3, [r7, #12]
+ 800540c:	625a      	str	r2, [r3, #36]	@ 0x24
 
           /* Update counter */
           hi2c->XferSize--;
- 8003fe6:	68fb      	ldr	r3, [r7, #12]
- 8003fe8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8003fea:	3b01      	subs	r3, #1
- 8003fec:	b29a      	uxth	r2, r3
- 8003fee:	68fb      	ldr	r3, [r7, #12]
- 8003ff0:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 800540e:	68fb      	ldr	r3, [r7, #12]
+ 8005410:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8005412:	3b01      	subs	r3, #1
+ 8005414:	b29a      	uxth	r2, r3
+ 8005416:	68fb      	ldr	r3, [r7, #12]
+ 8005418:	851a      	strh	r2, [r3, #40]	@ 0x28
           hi2c->XferCount--;
- 8003ff2:	68fb      	ldr	r3, [r7, #12]
- 8003ff4:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
- 8003ff6:	b29b      	uxth	r3, r3
- 8003ff8:	3b01      	subs	r3, #1
- 8003ffa:	b29a      	uxth	r2, r3
- 8003ffc:	68fb      	ldr	r3, [r7, #12]
- 8003ffe:	855a      	strh	r2, [r3, #42]	@ 0x2a
+ 800541a:	68fb      	ldr	r3, [r7, #12]
+ 800541c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 800541e:	b29b      	uxth	r3, r3
+ 8005420:	3b01      	subs	r3, #1
+ 8005422:	b29a      	uxth	r2, r3
+ 8005424:	68fb      	ldr	r3, [r7, #12]
+ 8005426:	855a      	strh	r2, [r3, #42]	@ 0x2a
     while (hi2c->XferSize > 0U)
- 8004000:	68fb      	ldr	r3, [r7, #12]
- 8004002:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
- 8004004:	2b00      	cmp	r3, #0
- 8004006:	f47f ae88 	bne.w	8003d1a <HAL_I2C_Master_Receive+0x1b6>
+ 8005428:	68fb      	ldr	r3, [r7, #12]
+ 800542a:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 800542c:	2b00      	cmp	r3, #0
+ 800542e:	f47f ae88 	bne.w	8005142 <HAL_I2C_Master_Receive+0x1b6>
         }
       }
     }
 
     hi2c->State = HAL_I2C_STATE_READY;
- 800400a:	68fb      	ldr	r3, [r7, #12]
- 800400c:	2220      	movs	r2, #32
- 800400e:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005432:	68fb      	ldr	r3, [r7, #12]
+ 8005434:	2220      	movs	r2, #32
+ 8005436:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
     hi2c->Mode = HAL_I2C_MODE_NONE;
- 8004012:	68fb      	ldr	r3, [r7, #12]
- 8004014:	2200      	movs	r2, #0
- 8004016:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 800543a:	68fb      	ldr	r3, [r7, #12]
+ 800543c:	2200      	movs	r2, #0
+ 800543e:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
- 800401a:	68fb      	ldr	r3, [r7, #12]
- 800401c:	2200      	movs	r2, #0
- 800401e:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005442:	68fb      	ldr	r3, [r7, #12]
+ 8005444:	2200      	movs	r2, #0
+ 8005446:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     return HAL_OK;
- 8004022:	2300      	movs	r3, #0
- 8004024:	e000      	b.n	8004028 <HAL_I2C_Master_Receive+0x4c4>
+ 800544a:	2300      	movs	r3, #0
+ 800544c:	e000      	b.n	8005450 <HAL_I2C_Master_Receive+0x4c4>
   }
   else
   {
     return HAL_BUSY;
- 8004026:	2302      	movs	r3, #2
+ 800544e:	2302      	movs	r3, #2
   }
 }
- 8004028:	4618      	mov	r0, r3
- 800402a:	3728      	adds	r7, #40	@ 0x28
- 800402c:	46bd      	mov	sp, r7
- 800402e:	bd80      	pop	{r7, pc}
- 8004030:	00010004 	.word	0x00010004
- 8004034:	2000001c 	.word	0x2000001c
- 8004038:	14f8b589 	.word	0x14f8b589
+ 8005450:	4618      	mov	r0, r3
+ 8005452:	3728      	adds	r7, #40	@ 0x28
+ 8005454:	46bd      	mov	sp, r7
+ 8005456:	bd80      	pop	{r7, pc}
+ 8005458:	00010004 	.word	0x00010004
+ 800545c:	20000024 	.word	0x20000024
+ 8005460:	14f8b589 	.word	0x14f8b589
 
-0800403c <I2C_MasterRequestWrite>:
+08005464 <I2C_MasterRequestWrite>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
- 800403c:	b580      	push	{r7, lr}
- 800403e:	b088      	sub	sp, #32
- 8004040:	af02      	add	r7, sp, #8
- 8004042:	60f8      	str	r0, [r7, #12]
- 8004044:	607a      	str	r2, [r7, #4]
- 8004046:	603b      	str	r3, [r7, #0]
- 8004048:	460b      	mov	r3, r1
- 800404a:	817b      	strh	r3, [r7, #10]
+ 8005464:	b580      	push	{r7, lr}
+ 8005466:	b088      	sub	sp, #32
+ 8005468:	af02      	add	r7, sp, #8
+ 800546a:	60f8      	str	r0, [r7, #12]
+ 800546c:	607a      	str	r2, [r7, #4]
+ 800546e:	603b      	str	r3, [r7, #0]
+ 8005470:	460b      	mov	r3, r1
+ 8005472:	817b      	strh	r3, [r7, #10]
   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
   uint32_t CurrentXferOptions = hi2c->XferOptions;
- 800404c:	68fb      	ldr	r3, [r7, #12]
- 800404e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8004050:	617b      	str	r3, [r7, #20]
+ 8005474:	68fb      	ldr	r3, [r7, #12]
+ 8005476:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8005478:	617b      	str	r3, [r7, #20]
 
   /* Generate Start condition if first transfer */
   if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
- 8004052:	697b      	ldr	r3, [r7, #20]
- 8004054:	2b08      	cmp	r3, #8
- 8004056:	d006      	beq.n	8004066 <I2C_MasterRequestWrite+0x2a>
- 8004058:	697b      	ldr	r3, [r7, #20]
- 800405a:	2b01      	cmp	r3, #1
- 800405c:	d003      	beq.n	8004066 <I2C_MasterRequestWrite+0x2a>
- 800405e:	697b      	ldr	r3, [r7, #20]
- 8004060:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
- 8004064:	d108      	bne.n	8004078 <I2C_MasterRequestWrite+0x3c>
+ 800547a:	697b      	ldr	r3, [r7, #20]
+ 800547c:	2b08      	cmp	r3, #8
+ 800547e:	d006      	beq.n	800548e <I2C_MasterRequestWrite+0x2a>
+ 8005480:	697b      	ldr	r3, [r7, #20]
+ 8005482:	2b01      	cmp	r3, #1
+ 8005484:	d003      	beq.n	800548e <I2C_MasterRequestWrite+0x2a>
+ 8005486:	697b      	ldr	r3, [r7, #20]
+ 8005488:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 800548c:	d108      	bne.n	80054a0 <I2C_MasterRequestWrite+0x3c>
   {
     /* Generate Start */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- 8004066:	68fb      	ldr	r3, [r7, #12]
- 8004068:	681b      	ldr	r3, [r3, #0]
- 800406a:	681a      	ldr	r2, [r3, #0]
- 800406c:	68fb      	ldr	r3, [r7, #12]
- 800406e:	681b      	ldr	r3, [r3, #0]
- 8004070:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
- 8004074:	601a      	str	r2, [r3, #0]
- 8004076:	e00b      	b.n	8004090 <I2C_MasterRequestWrite+0x54>
+ 800548e:	68fb      	ldr	r3, [r7, #12]
+ 8005490:	681b      	ldr	r3, [r3, #0]
+ 8005492:	681a      	ldr	r2, [r3, #0]
+ 8005494:	68fb      	ldr	r3, [r7, #12]
+ 8005496:	681b      	ldr	r3, [r3, #0]
+ 8005498:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 800549c:	601a      	str	r2, [r3, #0]
+ 800549e:	e00b      	b.n	80054b8 <I2C_MasterRequestWrite+0x54>
   }
   else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
- 8004078:	68fb      	ldr	r3, [r7, #12]
- 800407a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 800407c:	2b12      	cmp	r3, #18
- 800407e:	d107      	bne.n	8004090 <I2C_MasterRequestWrite+0x54>
+ 80054a0:	68fb      	ldr	r3, [r7, #12]
+ 80054a2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80054a4:	2b12      	cmp	r3, #18
+ 80054a6:	d107      	bne.n	80054b8 <I2C_MasterRequestWrite+0x54>
   {
     /* Generate ReStart */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- 8004080:	68fb      	ldr	r3, [r7, #12]
- 8004082:	681b      	ldr	r3, [r3, #0]
- 8004084:	681a      	ldr	r2, [r3, #0]
- 8004086:	68fb      	ldr	r3, [r7, #12]
- 8004088:	681b      	ldr	r3, [r3, #0]
- 800408a:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
- 800408e:	601a      	str	r2, [r3, #0]
+ 80054a8:	68fb      	ldr	r3, [r7, #12]
+ 80054aa:	681b      	ldr	r3, [r3, #0]
+ 80054ac:	681a      	ldr	r2, [r3, #0]
+ 80054ae:	68fb      	ldr	r3, [r7, #12]
+ 80054b0:	681b      	ldr	r3, [r3, #0]
+ 80054b2:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 80054b6:	601a      	str	r2, [r3, #0]
   {
     /* Do nothing */
   }
 
   /* Wait until SB flag is set */
   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- 8004090:	683b      	ldr	r3, [r7, #0]
- 8004092:	9300      	str	r3, [sp, #0]
- 8004094:	687b      	ldr	r3, [r7, #4]
- 8004096:	2200      	movs	r2, #0
- 8004098:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
- 800409c:	68f8      	ldr	r0, [r7, #12]
- 800409e:	f000 f91d 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 80040a2:	4603      	mov	r3, r0
- 80040a4:	2b00      	cmp	r3, #0
- 80040a6:	d00d      	beq.n	80040c4 <I2C_MasterRequestWrite+0x88>
+ 80054b8:	683b      	ldr	r3, [r7, #0]
+ 80054ba:	9300      	str	r3, [sp, #0]
+ 80054bc:	687b      	ldr	r3, [r7, #4]
+ 80054be:	2200      	movs	r2, #0
+ 80054c0:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
+ 80054c4:	68f8      	ldr	r0, [r7, #12]
+ 80054c6:	f000 f91d 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 80054ca:	4603      	mov	r3, r0
+ 80054cc:	2b00      	cmp	r3, #0
+ 80054ce:	d00d      	beq.n	80054ec <I2C_MasterRequestWrite+0x88>
   {
     if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
- 80040a8:	68fb      	ldr	r3, [r7, #12]
- 80040aa:	681b      	ldr	r3, [r3, #0]
- 80040ac:	681b      	ldr	r3, [r3, #0]
- 80040ae:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 80040b2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
- 80040b6:	d103      	bne.n	80040c0 <I2C_MasterRequestWrite+0x84>
+ 80054d0:	68fb      	ldr	r3, [r7, #12]
+ 80054d2:	681b      	ldr	r3, [r3, #0]
+ 80054d4:	681b      	ldr	r3, [r3, #0]
+ 80054d6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80054da:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 80054de:	d103      	bne.n	80054e8 <I2C_MasterRequestWrite+0x84>
     {
       hi2c->ErrorCode = HAL_I2C_WRONG_START;
- 80040b8:	68fb      	ldr	r3, [r7, #12]
- 80040ba:	f44f 7200 	mov.w	r2, #512	@ 0x200
- 80040be:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80054e0:	68fb      	ldr	r3, [r7, #12]
+ 80054e2:	f44f 7200 	mov.w	r2, #512	@ 0x200
+ 80054e6:	641a      	str	r2, [r3, #64]	@ 0x40
     }
     return HAL_TIMEOUT;
- 80040c0:	2303      	movs	r3, #3
- 80040c2:	e035      	b.n	8004130 <I2C_MasterRequestWrite+0xf4>
+ 80054e8:	2303      	movs	r3, #3
+ 80054ea:	e035      	b.n	8005558 <I2C_MasterRequestWrite+0xf4>
   }
 
   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- 80040c4:	68fb      	ldr	r3, [r7, #12]
- 80040c6:	691b      	ldr	r3, [r3, #16]
- 80040c8:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
- 80040cc:	d108      	bne.n	80040e0 <I2C_MasterRequestWrite+0xa4>
+ 80054ec:	68fb      	ldr	r3, [r7, #12]
+ 80054ee:	691b      	ldr	r3, [r3, #16]
+ 80054f0:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 80054f4:	d108      	bne.n	8005508 <I2C_MasterRequestWrite+0xa4>
   {
     /* Send slave address */
     hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
- 80040ce:	897b      	ldrh	r3, [r7, #10]
- 80040d0:	b2db      	uxtb	r3, r3
- 80040d2:	461a      	mov	r2, r3
- 80040d4:	68fb      	ldr	r3, [r7, #12]
- 80040d6:	681b      	ldr	r3, [r3, #0]
- 80040d8:	f002 02fe 	and.w	r2, r2, #254	@ 0xfe
- 80040dc:	611a      	str	r2, [r3, #16]
- 80040de:	e01b      	b.n	8004118 <I2C_MasterRequestWrite+0xdc>
+ 80054f6:	897b      	ldrh	r3, [r7, #10]
+ 80054f8:	b2db      	uxtb	r3, r3
+ 80054fa:	461a      	mov	r2, r3
+ 80054fc:	68fb      	ldr	r3, [r7, #12]
+ 80054fe:	681b      	ldr	r3, [r3, #0]
+ 8005500:	f002 02fe 	and.w	r2, r2, #254	@ 0xfe
+ 8005504:	611a      	str	r2, [r3, #16]
+ 8005506:	e01b      	b.n	8005540 <I2C_MasterRequestWrite+0xdc>
   }
   else
   {
     /* Send header of slave address */
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
- 80040e0:	897b      	ldrh	r3, [r7, #10]
- 80040e2:	11db      	asrs	r3, r3, #7
- 80040e4:	b2db      	uxtb	r3, r3
- 80040e6:	f003 0306 	and.w	r3, r3, #6
- 80040ea:	b2db      	uxtb	r3, r3
- 80040ec:	f063 030f 	orn	r3, r3, #15
- 80040f0:	b2da      	uxtb	r2, r3
- 80040f2:	68fb      	ldr	r3, [r7, #12]
- 80040f4:	681b      	ldr	r3, [r3, #0]
- 80040f6:	611a      	str	r2, [r3, #16]
+ 8005508:	897b      	ldrh	r3, [r7, #10]
+ 800550a:	11db      	asrs	r3, r3, #7
+ 800550c:	b2db      	uxtb	r3, r3
+ 800550e:	f003 0306 	and.w	r3, r3, #6
+ 8005512:	b2db      	uxtb	r3, r3
+ 8005514:	f063 030f 	orn	r3, r3, #15
+ 8005518:	b2da      	uxtb	r2, r3
+ 800551a:	68fb      	ldr	r3, [r7, #12]
+ 800551c:	681b      	ldr	r3, [r3, #0]
+ 800551e:	611a      	str	r2, [r3, #16]
 
     /* Wait until ADD10 flag is set */
     if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
- 80040f8:	683b      	ldr	r3, [r7, #0]
- 80040fa:	687a      	ldr	r2, [r7, #4]
- 80040fc:	490e      	ldr	r1, [pc, #56]	@ (8004138 <I2C_MasterRequestWrite+0xfc>)
- 80040fe:	68f8      	ldr	r0, [r7, #12]
- 8004100:	f000 f966 	bl	80043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
- 8004104:	4603      	mov	r3, r0
- 8004106:	2b00      	cmp	r3, #0
- 8004108:	d001      	beq.n	800410e <I2C_MasterRequestWrite+0xd2>
+ 8005520:	683b      	ldr	r3, [r7, #0]
+ 8005522:	687a      	ldr	r2, [r7, #4]
+ 8005524:	490e      	ldr	r1, [pc, #56]	@ (8005560 <I2C_MasterRequestWrite+0xfc>)
+ 8005526:	68f8      	ldr	r0, [r7, #12]
+ 8005528:	f000 f966 	bl	80057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>
+ 800552c:	4603      	mov	r3, r0
+ 800552e:	2b00      	cmp	r3, #0
+ 8005530:	d001      	beq.n	8005536 <I2C_MasterRequestWrite+0xd2>
     {
       return HAL_ERROR;
- 800410a:	2301      	movs	r3, #1
- 800410c:	e010      	b.n	8004130 <I2C_MasterRequestWrite+0xf4>
+ 8005532:	2301      	movs	r3, #1
+ 8005534:	e010      	b.n	8005558 <I2C_MasterRequestWrite+0xf4>
     }
 
     /* Send slave address */
     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
- 800410e:	897b      	ldrh	r3, [r7, #10]
- 8004110:	b2da      	uxtb	r2, r3
- 8004112:	68fb      	ldr	r3, [r7, #12]
- 8004114:	681b      	ldr	r3, [r3, #0]
- 8004116:	611a      	str	r2, [r3, #16]
+ 8005536:	897b      	ldrh	r3, [r7, #10]
+ 8005538:	b2da      	uxtb	r2, r3
+ 800553a:	68fb      	ldr	r3, [r7, #12]
+ 800553c:	681b      	ldr	r3, [r3, #0]
+ 800553e:	611a      	str	r2, [r3, #16]
   }
 
   /* Wait until ADDR flag is set */
   if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- 8004118:	683b      	ldr	r3, [r7, #0]
- 800411a:	687a      	ldr	r2, [r7, #4]
- 800411c:	4907      	ldr	r1, [pc, #28]	@ (800413c <I2C_MasterRequestWrite+0x100>)
- 800411e:	68f8      	ldr	r0, [r7, #12]
- 8004120:	f000 f956 	bl	80043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
- 8004124:	4603      	mov	r3, r0
- 8004126:	2b00      	cmp	r3, #0
- 8004128:	d001      	beq.n	800412e <I2C_MasterRequestWrite+0xf2>
+ 8005540:	683b      	ldr	r3, [r7, #0]
+ 8005542:	687a      	ldr	r2, [r7, #4]
+ 8005544:	4907      	ldr	r1, [pc, #28]	@ (8005564 <I2C_MasterRequestWrite+0x100>)
+ 8005546:	68f8      	ldr	r0, [r7, #12]
+ 8005548:	f000 f956 	bl	80057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>
+ 800554c:	4603      	mov	r3, r0
+ 800554e:	2b00      	cmp	r3, #0
+ 8005550:	d001      	beq.n	8005556 <I2C_MasterRequestWrite+0xf2>
   {
     return HAL_ERROR;
- 800412a:	2301      	movs	r3, #1
- 800412c:	e000      	b.n	8004130 <I2C_MasterRequestWrite+0xf4>
+ 8005552:	2301      	movs	r3, #1
+ 8005554:	e000      	b.n	8005558 <I2C_MasterRequestWrite+0xf4>
   }
 
   return HAL_OK;
- 800412e:	2300      	movs	r3, #0
+ 8005556:	2300      	movs	r3, #0
 }
- 8004130:	4618      	mov	r0, r3
- 8004132:	3718      	adds	r7, #24
- 8004134:	46bd      	mov	sp, r7
- 8004136:	bd80      	pop	{r7, pc}
- 8004138:	00010008 	.word	0x00010008
- 800413c:	00010002 	.word	0x00010002
+ 8005558:	4618      	mov	r0, r3
+ 800555a:	3718      	adds	r7, #24
+ 800555c:	46bd      	mov	sp, r7
+ 800555e:	bd80      	pop	{r7, pc}
+ 8005560:	00010008 	.word	0x00010008
+ 8005564:	00010002 	.word	0x00010002
 
-08004140 <I2C_MasterRequestRead>:
+08005568 <I2C_MasterRequestRead>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
- 8004140:	b580      	push	{r7, lr}
- 8004142:	b088      	sub	sp, #32
- 8004144:	af02      	add	r7, sp, #8
- 8004146:	60f8      	str	r0, [r7, #12]
- 8004148:	607a      	str	r2, [r7, #4]
- 800414a:	603b      	str	r3, [r7, #0]
- 800414c:	460b      	mov	r3, r1
- 800414e:	817b      	strh	r3, [r7, #10]
+ 8005568:	b580      	push	{r7, lr}
+ 800556a:	b088      	sub	sp, #32
+ 800556c:	af02      	add	r7, sp, #8
+ 800556e:	60f8      	str	r0, [r7, #12]
+ 8005570:	607a      	str	r2, [r7, #4]
+ 8005572:	603b      	str	r3, [r7, #0]
+ 8005574:	460b      	mov	r3, r1
+ 8005576:	817b      	strh	r3, [r7, #10]
   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
   uint32_t CurrentXferOptions = hi2c->XferOptions;
- 8004150:	68fb      	ldr	r3, [r7, #12]
- 8004152:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8004154:	617b      	str	r3, [r7, #20]
+ 8005578:	68fb      	ldr	r3, [r7, #12]
+ 800557a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 800557c:	617b      	str	r3, [r7, #20]
 
   /* Enable Acknowledge */
   SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- 8004156:	68fb      	ldr	r3, [r7, #12]
- 8004158:	681b      	ldr	r3, [r3, #0]
- 800415a:	681a      	ldr	r2, [r3, #0]
- 800415c:	68fb      	ldr	r3, [r7, #12]
- 800415e:	681b      	ldr	r3, [r3, #0]
- 8004160:	f442 6280 	orr.w	r2, r2, #1024	@ 0x400
- 8004164:	601a      	str	r2, [r3, #0]
+ 800557e:	68fb      	ldr	r3, [r7, #12]
+ 8005580:	681b      	ldr	r3, [r3, #0]
+ 8005582:	681a      	ldr	r2, [r3, #0]
+ 8005584:	68fb      	ldr	r3, [r7, #12]
+ 8005586:	681b      	ldr	r3, [r3, #0]
+ 8005588:	f442 6280 	orr.w	r2, r2, #1024	@ 0x400
+ 800558c:	601a      	str	r2, [r3, #0]
 
   /* Generate Start condition if first transfer */
   if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
- 8004166:	697b      	ldr	r3, [r7, #20]
- 8004168:	2b08      	cmp	r3, #8
- 800416a:	d006      	beq.n	800417a <I2C_MasterRequestRead+0x3a>
- 800416c:	697b      	ldr	r3, [r7, #20]
- 800416e:	2b01      	cmp	r3, #1
- 8004170:	d003      	beq.n	800417a <I2C_MasterRequestRead+0x3a>
- 8004172:	697b      	ldr	r3, [r7, #20]
- 8004174:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
- 8004178:	d108      	bne.n	800418c <I2C_MasterRequestRead+0x4c>
+ 800558e:	697b      	ldr	r3, [r7, #20]
+ 8005590:	2b08      	cmp	r3, #8
+ 8005592:	d006      	beq.n	80055a2 <I2C_MasterRequestRead+0x3a>
+ 8005594:	697b      	ldr	r3, [r7, #20]
+ 8005596:	2b01      	cmp	r3, #1
+ 8005598:	d003      	beq.n	80055a2 <I2C_MasterRequestRead+0x3a>
+ 800559a:	697b      	ldr	r3, [r7, #20]
+ 800559c:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 80055a0:	d108      	bne.n	80055b4 <I2C_MasterRequestRead+0x4c>
   {
     /* Generate Start */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- 800417a:	68fb      	ldr	r3, [r7, #12]
- 800417c:	681b      	ldr	r3, [r3, #0]
- 800417e:	681a      	ldr	r2, [r3, #0]
- 8004180:	68fb      	ldr	r3, [r7, #12]
- 8004182:	681b      	ldr	r3, [r3, #0]
- 8004184:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
- 8004188:	601a      	str	r2, [r3, #0]
- 800418a:	e00b      	b.n	80041a4 <I2C_MasterRequestRead+0x64>
+ 80055a2:	68fb      	ldr	r3, [r7, #12]
+ 80055a4:	681b      	ldr	r3, [r3, #0]
+ 80055a6:	681a      	ldr	r2, [r3, #0]
+ 80055a8:	68fb      	ldr	r3, [r7, #12]
+ 80055aa:	681b      	ldr	r3, [r3, #0]
+ 80055ac:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 80055b0:	601a      	str	r2, [r3, #0]
+ 80055b2:	e00b      	b.n	80055cc <I2C_MasterRequestRead+0x64>
   }
   else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
- 800418c:	68fb      	ldr	r3, [r7, #12]
- 800418e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 8004190:	2b11      	cmp	r3, #17
- 8004192:	d107      	bne.n	80041a4 <I2C_MasterRequestRead+0x64>
+ 80055b4:	68fb      	ldr	r3, [r7, #12]
+ 80055b6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80055b8:	2b11      	cmp	r3, #17
+ 80055ba:	d107      	bne.n	80055cc <I2C_MasterRequestRead+0x64>
   {
     /* Generate ReStart */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- 8004194:	68fb      	ldr	r3, [r7, #12]
- 8004196:	681b      	ldr	r3, [r3, #0]
- 8004198:	681a      	ldr	r2, [r3, #0]
- 800419a:	68fb      	ldr	r3, [r7, #12]
- 800419c:	681b      	ldr	r3, [r3, #0]
- 800419e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
- 80041a2:	601a      	str	r2, [r3, #0]
+ 80055bc:	68fb      	ldr	r3, [r7, #12]
+ 80055be:	681b      	ldr	r3, [r3, #0]
+ 80055c0:	681a      	ldr	r2, [r3, #0]
+ 80055c2:	68fb      	ldr	r3, [r7, #12]
+ 80055c4:	681b      	ldr	r3, [r3, #0]
+ 80055c6:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 80055ca:	601a      	str	r2, [r3, #0]
   {
     /* Do nothing */
   }
 
   /* Wait until SB flag is set */
   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- 80041a4:	683b      	ldr	r3, [r7, #0]
- 80041a6:	9300      	str	r3, [sp, #0]
- 80041a8:	687b      	ldr	r3, [r7, #4]
- 80041aa:	2200      	movs	r2, #0
- 80041ac:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
- 80041b0:	68f8      	ldr	r0, [r7, #12]
- 80041b2:	f000 f893 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 80041b6:	4603      	mov	r3, r0
- 80041b8:	2b00      	cmp	r3, #0
- 80041ba:	d00d      	beq.n	80041d8 <I2C_MasterRequestRead+0x98>
+ 80055cc:	683b      	ldr	r3, [r7, #0]
+ 80055ce:	9300      	str	r3, [sp, #0]
+ 80055d0:	687b      	ldr	r3, [r7, #4]
+ 80055d2:	2200      	movs	r2, #0
+ 80055d4:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
+ 80055d8:	68f8      	ldr	r0, [r7, #12]
+ 80055da:	f000 f893 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 80055de:	4603      	mov	r3, r0
+ 80055e0:	2b00      	cmp	r3, #0
+ 80055e2:	d00d      	beq.n	8005600 <I2C_MasterRequestRead+0x98>
   {
     if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
- 80041bc:	68fb      	ldr	r3, [r7, #12]
- 80041be:	681b      	ldr	r3, [r3, #0]
- 80041c0:	681b      	ldr	r3, [r3, #0]
- 80041c2:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 80041c6:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
- 80041ca:	d103      	bne.n	80041d4 <I2C_MasterRequestRead+0x94>
+ 80055e4:	68fb      	ldr	r3, [r7, #12]
+ 80055e6:	681b      	ldr	r3, [r3, #0]
+ 80055e8:	681b      	ldr	r3, [r3, #0]
+ 80055ea:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80055ee:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 80055f2:	d103      	bne.n	80055fc <I2C_MasterRequestRead+0x94>
     {
       hi2c->ErrorCode = HAL_I2C_WRONG_START;
- 80041cc:	68fb      	ldr	r3, [r7, #12]
- 80041ce:	f44f 7200 	mov.w	r2, #512	@ 0x200
- 80041d2:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80055f4:	68fb      	ldr	r3, [r7, #12]
+ 80055f6:	f44f 7200 	mov.w	r2, #512	@ 0x200
+ 80055fa:	641a      	str	r2, [r3, #64]	@ 0x40
     }
     return HAL_TIMEOUT;
- 80041d4:	2303      	movs	r3, #3
- 80041d6:	e079      	b.n	80042cc <I2C_MasterRequestRead+0x18c>
+ 80055fc:	2303      	movs	r3, #3
+ 80055fe:	e079      	b.n	80056f4 <I2C_MasterRequestRead+0x18c>
   }
 
   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- 80041d8:	68fb      	ldr	r3, [r7, #12]
- 80041da:	691b      	ldr	r3, [r3, #16]
- 80041dc:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
- 80041e0:	d108      	bne.n	80041f4 <I2C_MasterRequestRead+0xb4>
+ 8005600:	68fb      	ldr	r3, [r7, #12]
+ 8005602:	691b      	ldr	r3, [r3, #16]
+ 8005604:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 8005608:	d108      	bne.n	800561c <I2C_MasterRequestRead+0xb4>
   {
     /* Send slave address */
     hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
- 80041e2:	897b      	ldrh	r3, [r7, #10]
- 80041e4:	b2db      	uxtb	r3, r3
- 80041e6:	f043 0301 	orr.w	r3, r3, #1
- 80041ea:	b2da      	uxtb	r2, r3
- 80041ec:	68fb      	ldr	r3, [r7, #12]
- 80041ee:	681b      	ldr	r3, [r3, #0]
- 80041f0:	611a      	str	r2, [r3, #16]
- 80041f2:	e05f      	b.n	80042b4 <I2C_MasterRequestRead+0x174>
+ 800560a:	897b      	ldrh	r3, [r7, #10]
+ 800560c:	b2db      	uxtb	r3, r3
+ 800560e:	f043 0301 	orr.w	r3, r3, #1
+ 8005612:	b2da      	uxtb	r2, r3
+ 8005614:	68fb      	ldr	r3, [r7, #12]
+ 8005616:	681b      	ldr	r3, [r3, #0]
+ 8005618:	611a      	str	r2, [r3, #16]
+ 800561a:	e05f      	b.n	80056dc <I2C_MasterRequestRead+0x174>
   }
   else
   {
     /* Send header of slave address */
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
- 80041f4:	897b      	ldrh	r3, [r7, #10]
- 80041f6:	11db      	asrs	r3, r3, #7
- 80041f8:	b2db      	uxtb	r3, r3
- 80041fa:	f003 0306 	and.w	r3, r3, #6
- 80041fe:	b2db      	uxtb	r3, r3
- 8004200:	f063 030f 	orn	r3, r3, #15
- 8004204:	b2da      	uxtb	r2, r3
- 8004206:	68fb      	ldr	r3, [r7, #12]
- 8004208:	681b      	ldr	r3, [r3, #0]
- 800420a:	611a      	str	r2, [r3, #16]
+ 800561c:	897b      	ldrh	r3, [r7, #10]
+ 800561e:	11db      	asrs	r3, r3, #7
+ 8005620:	b2db      	uxtb	r3, r3
+ 8005622:	f003 0306 	and.w	r3, r3, #6
+ 8005626:	b2db      	uxtb	r3, r3
+ 8005628:	f063 030f 	orn	r3, r3, #15
+ 800562c:	b2da      	uxtb	r2, r3
+ 800562e:	68fb      	ldr	r3, [r7, #12]
+ 8005630:	681b      	ldr	r3, [r3, #0]
+ 8005632:	611a      	str	r2, [r3, #16]
 
     /* Wait until ADD10 flag is set */
     if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
- 800420c:	683b      	ldr	r3, [r7, #0]
- 800420e:	687a      	ldr	r2, [r7, #4]
- 8004210:	4930      	ldr	r1, [pc, #192]	@ (80042d4 <I2C_MasterRequestRead+0x194>)
- 8004212:	68f8      	ldr	r0, [r7, #12]
- 8004214:	f000 f8dc 	bl	80043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
- 8004218:	4603      	mov	r3, r0
- 800421a:	2b00      	cmp	r3, #0
- 800421c:	d001      	beq.n	8004222 <I2C_MasterRequestRead+0xe2>
+ 8005634:	683b      	ldr	r3, [r7, #0]
+ 8005636:	687a      	ldr	r2, [r7, #4]
+ 8005638:	4930      	ldr	r1, [pc, #192]	@ (80056fc <I2C_MasterRequestRead+0x194>)
+ 800563a:	68f8      	ldr	r0, [r7, #12]
+ 800563c:	f000 f8dc 	bl	80057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>
+ 8005640:	4603      	mov	r3, r0
+ 8005642:	2b00      	cmp	r3, #0
+ 8005644:	d001      	beq.n	800564a <I2C_MasterRequestRead+0xe2>
     {
       return HAL_ERROR;
- 800421e:	2301      	movs	r3, #1
- 8004220:	e054      	b.n	80042cc <I2C_MasterRequestRead+0x18c>
+ 8005646:	2301      	movs	r3, #1
+ 8005648:	e054      	b.n	80056f4 <I2C_MasterRequestRead+0x18c>
     }
 
     /* Send slave address */
     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
- 8004222:	897b      	ldrh	r3, [r7, #10]
- 8004224:	b2da      	uxtb	r2, r3
- 8004226:	68fb      	ldr	r3, [r7, #12]
- 8004228:	681b      	ldr	r3, [r3, #0]
- 800422a:	611a      	str	r2, [r3, #16]
+ 800564a:	897b      	ldrh	r3, [r7, #10]
+ 800564c:	b2da      	uxtb	r2, r3
+ 800564e:	68fb      	ldr	r3, [r7, #12]
+ 8005650:	681b      	ldr	r3, [r3, #0]
+ 8005652:	611a      	str	r2, [r3, #16]
 
     /* Wait until ADDR flag is set */
     if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- 800422c:	683b      	ldr	r3, [r7, #0]
- 800422e:	687a      	ldr	r2, [r7, #4]
- 8004230:	4929      	ldr	r1, [pc, #164]	@ (80042d8 <I2C_MasterRequestRead+0x198>)
- 8004232:	68f8      	ldr	r0, [r7, #12]
- 8004234:	f000 f8cc 	bl	80043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
- 8004238:	4603      	mov	r3, r0
- 800423a:	2b00      	cmp	r3, #0
- 800423c:	d001      	beq.n	8004242 <I2C_MasterRequestRead+0x102>
+ 8005654:	683b      	ldr	r3, [r7, #0]
+ 8005656:	687a      	ldr	r2, [r7, #4]
+ 8005658:	4929      	ldr	r1, [pc, #164]	@ (8005700 <I2C_MasterRequestRead+0x198>)
+ 800565a:	68f8      	ldr	r0, [r7, #12]
+ 800565c:	f000 f8cc 	bl	80057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>
+ 8005660:	4603      	mov	r3, r0
+ 8005662:	2b00      	cmp	r3, #0
+ 8005664:	d001      	beq.n	800566a <I2C_MasterRequestRead+0x102>
     {
       return HAL_ERROR;
- 800423e:	2301      	movs	r3, #1
- 8004240:	e044      	b.n	80042cc <I2C_MasterRequestRead+0x18c>
+ 8005666:	2301      	movs	r3, #1
+ 8005668:	e044      	b.n	80056f4 <I2C_MasterRequestRead+0x18c>
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- 8004242:	2300      	movs	r3, #0
- 8004244:	613b      	str	r3, [r7, #16]
- 8004246:	68fb      	ldr	r3, [r7, #12]
- 8004248:	681b      	ldr	r3, [r3, #0]
- 800424a:	695b      	ldr	r3, [r3, #20]
- 800424c:	613b      	str	r3, [r7, #16]
- 800424e:	68fb      	ldr	r3, [r7, #12]
- 8004250:	681b      	ldr	r3, [r3, #0]
- 8004252:	699b      	ldr	r3, [r3, #24]
- 8004254:	613b      	str	r3, [r7, #16]
- 8004256:	693b      	ldr	r3, [r7, #16]
+ 800566a:	2300      	movs	r3, #0
+ 800566c:	613b      	str	r3, [r7, #16]
+ 800566e:	68fb      	ldr	r3, [r7, #12]
+ 8005670:	681b      	ldr	r3, [r3, #0]
+ 8005672:	695b      	ldr	r3, [r3, #20]
+ 8005674:	613b      	str	r3, [r7, #16]
+ 8005676:	68fb      	ldr	r3, [r7, #12]
+ 8005678:	681b      	ldr	r3, [r3, #0]
+ 800567a:	699b      	ldr	r3, [r3, #24]
+ 800567c:	613b      	str	r3, [r7, #16]
+ 800567e:	693b      	ldr	r3, [r7, #16]
 
     /* Generate Restart */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- 8004258:	68fb      	ldr	r3, [r7, #12]
- 800425a:	681b      	ldr	r3, [r3, #0]
- 800425c:	681a      	ldr	r2, [r3, #0]
- 800425e:	68fb      	ldr	r3, [r7, #12]
- 8004260:	681b      	ldr	r3, [r3, #0]
- 8004262:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
- 8004266:	601a      	str	r2, [r3, #0]
+ 8005680:	68fb      	ldr	r3, [r7, #12]
+ 8005682:	681b      	ldr	r3, [r3, #0]
+ 8005684:	681a      	ldr	r2, [r3, #0]
+ 8005686:	68fb      	ldr	r3, [r7, #12]
+ 8005688:	681b      	ldr	r3, [r3, #0]
+ 800568a:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 800568e:	601a      	str	r2, [r3, #0]
 
     /* Wait until SB flag is set */
     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- 8004268:	683b      	ldr	r3, [r7, #0]
- 800426a:	9300      	str	r3, [sp, #0]
- 800426c:	687b      	ldr	r3, [r7, #4]
- 800426e:	2200      	movs	r2, #0
- 8004270:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
- 8004274:	68f8      	ldr	r0, [r7, #12]
- 8004276:	f000 f831 	bl	80042dc <I2C_WaitOnFlagUntilTimeout>
- 800427a:	4603      	mov	r3, r0
- 800427c:	2b00      	cmp	r3, #0
- 800427e:	d00d      	beq.n	800429c <I2C_MasterRequestRead+0x15c>
+ 8005690:	683b      	ldr	r3, [r7, #0]
+ 8005692:	9300      	str	r3, [sp, #0]
+ 8005694:	687b      	ldr	r3, [r7, #4]
+ 8005696:	2200      	movs	r2, #0
+ 8005698:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
+ 800569c:	68f8      	ldr	r0, [r7, #12]
+ 800569e:	f000 f831 	bl	8005704 <I2C_WaitOnFlagUntilTimeout>
+ 80056a2:	4603      	mov	r3, r0
+ 80056a4:	2b00      	cmp	r3, #0
+ 80056a6:	d00d      	beq.n	80056c4 <I2C_MasterRequestRead+0x15c>
     {
       if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
- 8004280:	68fb      	ldr	r3, [r7, #12]
- 8004282:	681b      	ldr	r3, [r3, #0]
- 8004284:	681b      	ldr	r3, [r3, #0]
- 8004286:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 800428a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
- 800428e:	d103      	bne.n	8004298 <I2C_MasterRequestRead+0x158>
+ 80056a8:	68fb      	ldr	r3, [r7, #12]
+ 80056aa:	681b      	ldr	r3, [r3, #0]
+ 80056ac:	681b      	ldr	r3, [r3, #0]
+ 80056ae:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80056b2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 80056b6:	d103      	bne.n	80056c0 <I2C_MasterRequestRead+0x158>
       {
         hi2c->ErrorCode = HAL_I2C_WRONG_START;
- 8004290:	68fb      	ldr	r3, [r7, #12]
- 8004292:	f44f 7200 	mov.w	r2, #512	@ 0x200
- 8004296:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80056b8:	68fb      	ldr	r3, [r7, #12]
+ 80056ba:	f44f 7200 	mov.w	r2, #512	@ 0x200
+ 80056be:	641a      	str	r2, [r3, #64]	@ 0x40
       }
       return HAL_TIMEOUT;
- 8004298:	2303      	movs	r3, #3
- 800429a:	e017      	b.n	80042cc <I2C_MasterRequestRead+0x18c>
+ 80056c0:	2303      	movs	r3, #3
+ 80056c2:	e017      	b.n	80056f4 <I2C_MasterRequestRead+0x18c>
     }
 
     /* Send header of slave address */
     hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
- 800429c:	897b      	ldrh	r3, [r7, #10]
- 800429e:	11db      	asrs	r3, r3, #7
- 80042a0:	b2db      	uxtb	r3, r3
- 80042a2:	f003 0306 	and.w	r3, r3, #6
- 80042a6:	b2db      	uxtb	r3, r3
- 80042a8:	f063 030e 	orn	r3, r3, #14
- 80042ac:	b2da      	uxtb	r2, r3
- 80042ae:	68fb      	ldr	r3, [r7, #12]
- 80042b0:	681b      	ldr	r3, [r3, #0]
- 80042b2:	611a      	str	r2, [r3, #16]
+ 80056c4:	897b      	ldrh	r3, [r7, #10]
+ 80056c6:	11db      	asrs	r3, r3, #7
+ 80056c8:	b2db      	uxtb	r3, r3
+ 80056ca:	f003 0306 	and.w	r3, r3, #6
+ 80056ce:	b2db      	uxtb	r3, r3
+ 80056d0:	f063 030e 	orn	r3, r3, #14
+ 80056d4:	b2da      	uxtb	r2, r3
+ 80056d6:	68fb      	ldr	r3, [r7, #12]
+ 80056d8:	681b      	ldr	r3, [r3, #0]
+ 80056da:	611a      	str	r2, [r3, #16]
   }
 
   /* Wait until ADDR flag is set */
   if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- 80042b4:	683b      	ldr	r3, [r7, #0]
- 80042b6:	687a      	ldr	r2, [r7, #4]
- 80042b8:	4907      	ldr	r1, [pc, #28]	@ (80042d8 <I2C_MasterRequestRead+0x198>)
- 80042ba:	68f8      	ldr	r0, [r7, #12]
- 80042bc:	f000 f888 	bl	80043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>
- 80042c0:	4603      	mov	r3, r0
- 80042c2:	2b00      	cmp	r3, #0
- 80042c4:	d001      	beq.n	80042ca <I2C_MasterRequestRead+0x18a>
+ 80056dc:	683b      	ldr	r3, [r7, #0]
+ 80056de:	687a      	ldr	r2, [r7, #4]
+ 80056e0:	4907      	ldr	r1, [pc, #28]	@ (8005700 <I2C_MasterRequestRead+0x198>)
+ 80056e2:	68f8      	ldr	r0, [r7, #12]
+ 80056e4:	f000 f888 	bl	80057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>
+ 80056e8:	4603      	mov	r3, r0
+ 80056ea:	2b00      	cmp	r3, #0
+ 80056ec:	d001      	beq.n	80056f2 <I2C_MasterRequestRead+0x18a>
   {
     return HAL_ERROR;
- 80042c6:	2301      	movs	r3, #1
- 80042c8:	e000      	b.n	80042cc <I2C_MasterRequestRead+0x18c>
+ 80056ee:	2301      	movs	r3, #1
+ 80056f0:	e000      	b.n	80056f4 <I2C_MasterRequestRead+0x18c>
   }
 
   return HAL_OK;
- 80042ca:	2300      	movs	r3, #0
+ 80056f2:	2300      	movs	r3, #0
 }
- 80042cc:	4618      	mov	r0, r3
- 80042ce:	3718      	adds	r7, #24
- 80042d0:	46bd      	mov	sp, r7
- 80042d2:	bd80      	pop	{r7, pc}
- 80042d4:	00010008 	.word	0x00010008
- 80042d8:	00010002 	.word	0x00010002
+ 80056f4:	4618      	mov	r0, r3
+ 80056f6:	3718      	adds	r7, #24
+ 80056f8:	46bd      	mov	sp, r7
+ 80056fa:	bd80      	pop	{r7, pc}
+ 80056fc:	00010008 	.word	0x00010008
+ 8005700:	00010002 	.word	0x00010002
 
-080042dc <I2C_WaitOnFlagUntilTimeout>:
+08005704 <I2C_WaitOnFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
 {
- 80042dc:	b580      	push	{r7, lr}
- 80042de:	b084      	sub	sp, #16
- 80042e0:	af00      	add	r7, sp, #0
- 80042e2:	60f8      	str	r0, [r7, #12]
- 80042e4:	60b9      	str	r1, [r7, #8]
- 80042e6:	603b      	str	r3, [r7, #0]
- 80042e8:	4613      	mov	r3, r2
- 80042ea:	71fb      	strb	r3, [r7, #7]
+ 8005704:	b580      	push	{r7, lr}
+ 8005706:	b084      	sub	sp, #16
+ 8005708:	af00      	add	r7, sp, #0
+ 800570a:	60f8      	str	r0, [r7, #12]
+ 800570c:	60b9      	str	r1, [r7, #8]
+ 800570e:	603b      	str	r3, [r7, #0]
+ 8005710:	4613      	mov	r3, r2
+ 8005712:	71fb      	strb	r3, [r7, #7]
   /* Wait until flag is set */
   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- 80042ec:	e048      	b.n	8004380 <I2C_WaitOnFlagUntilTimeout+0xa4>
+ 8005714:	e048      	b.n	80057a8 <I2C_WaitOnFlagUntilTimeout+0xa4>
   {
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 80042ee:	683b      	ldr	r3, [r7, #0]
- 80042f0:	f1b3 3fff 	cmp.w	r3, #4294967295
- 80042f4:	d044      	beq.n	8004380 <I2C_WaitOnFlagUntilTimeout+0xa4>
+ 8005716:	683b      	ldr	r3, [r7, #0]
+ 8005718:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800571c:	d044      	beq.n	80057a8 <I2C_WaitOnFlagUntilTimeout+0xa4>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 80042f6:	f7fe fc27 	bl	8002b48 <HAL_GetTick>
- 80042fa:	4602      	mov	r2, r0
- 80042fc:	69bb      	ldr	r3, [r7, #24]
- 80042fe:	1ad3      	subs	r3, r2, r3
- 8004300:	683a      	ldr	r2, [r7, #0]
- 8004302:	429a      	cmp	r2, r3
- 8004304:	d302      	bcc.n	800430c <I2C_WaitOnFlagUntilTimeout+0x30>
- 8004306:	683b      	ldr	r3, [r7, #0]
- 8004308:	2b00      	cmp	r3, #0
- 800430a:	d139      	bne.n	8004380 <I2C_WaitOnFlagUntilTimeout+0xa4>
+ 800571e:	f7fd fdd9 	bl	80032d4 <HAL_GetTick>
+ 8005722:	4602      	mov	r2, r0
+ 8005724:	69bb      	ldr	r3, [r7, #24]
+ 8005726:	1ad3      	subs	r3, r2, r3
+ 8005728:	683a      	ldr	r2, [r7, #0]
+ 800572a:	429a      	cmp	r2, r3
+ 800572c:	d302      	bcc.n	8005734 <I2C_WaitOnFlagUntilTimeout+0x30>
+ 800572e:	683b      	ldr	r3, [r7, #0]
+ 8005730:	2b00      	cmp	r3, #0
+ 8005732:	d139      	bne.n	80057a8 <I2C_WaitOnFlagUntilTimeout+0xa4>
       {
         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
- 800430c:	68bb      	ldr	r3, [r7, #8]
- 800430e:	0c1b      	lsrs	r3, r3, #16
- 8004310:	b2db      	uxtb	r3, r3
- 8004312:	2b01      	cmp	r3, #1
- 8004314:	d10d      	bne.n	8004332 <I2C_WaitOnFlagUntilTimeout+0x56>
- 8004316:	68fb      	ldr	r3, [r7, #12]
- 8004318:	681b      	ldr	r3, [r3, #0]
- 800431a:	695b      	ldr	r3, [r3, #20]
- 800431c:	43da      	mvns	r2, r3
- 800431e:	68bb      	ldr	r3, [r7, #8]
- 8004320:	4013      	ands	r3, r2
- 8004322:	b29b      	uxth	r3, r3
- 8004324:	2b00      	cmp	r3, #0
- 8004326:	bf0c      	ite	eq
- 8004328:	2301      	moveq	r3, #1
- 800432a:	2300      	movne	r3, #0
- 800432c:	b2db      	uxtb	r3, r3
- 800432e:	461a      	mov	r2, r3
- 8004330:	e00c      	b.n	800434c <I2C_WaitOnFlagUntilTimeout+0x70>
- 8004332:	68fb      	ldr	r3, [r7, #12]
- 8004334:	681b      	ldr	r3, [r3, #0]
- 8004336:	699b      	ldr	r3, [r3, #24]
- 8004338:	43da      	mvns	r2, r3
- 800433a:	68bb      	ldr	r3, [r7, #8]
- 800433c:	4013      	ands	r3, r2
- 800433e:	b29b      	uxth	r3, r3
- 8004340:	2b00      	cmp	r3, #0
- 8004342:	bf0c      	ite	eq
- 8004344:	2301      	moveq	r3, #1
- 8004346:	2300      	movne	r3, #0
- 8004348:	b2db      	uxtb	r3, r3
- 800434a:	461a      	mov	r2, r3
- 800434c:	79fb      	ldrb	r3, [r7, #7]
- 800434e:	429a      	cmp	r2, r3
- 8004350:	d116      	bne.n	8004380 <I2C_WaitOnFlagUntilTimeout+0xa4>
+ 8005734:	68bb      	ldr	r3, [r7, #8]
+ 8005736:	0c1b      	lsrs	r3, r3, #16
+ 8005738:	b2db      	uxtb	r3, r3
+ 800573a:	2b01      	cmp	r3, #1
+ 800573c:	d10d      	bne.n	800575a <I2C_WaitOnFlagUntilTimeout+0x56>
+ 800573e:	68fb      	ldr	r3, [r7, #12]
+ 8005740:	681b      	ldr	r3, [r3, #0]
+ 8005742:	695b      	ldr	r3, [r3, #20]
+ 8005744:	43da      	mvns	r2, r3
+ 8005746:	68bb      	ldr	r3, [r7, #8]
+ 8005748:	4013      	ands	r3, r2
+ 800574a:	b29b      	uxth	r3, r3
+ 800574c:	2b00      	cmp	r3, #0
+ 800574e:	bf0c      	ite	eq
+ 8005750:	2301      	moveq	r3, #1
+ 8005752:	2300      	movne	r3, #0
+ 8005754:	b2db      	uxtb	r3, r3
+ 8005756:	461a      	mov	r2, r3
+ 8005758:	e00c      	b.n	8005774 <I2C_WaitOnFlagUntilTimeout+0x70>
+ 800575a:	68fb      	ldr	r3, [r7, #12]
+ 800575c:	681b      	ldr	r3, [r3, #0]
+ 800575e:	699b      	ldr	r3, [r3, #24]
+ 8005760:	43da      	mvns	r2, r3
+ 8005762:	68bb      	ldr	r3, [r7, #8]
+ 8005764:	4013      	ands	r3, r2
+ 8005766:	b29b      	uxth	r3, r3
+ 8005768:	2b00      	cmp	r3, #0
+ 800576a:	bf0c      	ite	eq
+ 800576c:	2301      	moveq	r3, #1
+ 800576e:	2300      	movne	r3, #0
+ 8005770:	b2db      	uxtb	r3, r3
+ 8005772:	461a      	mov	r2, r3
+ 8005774:	79fb      	ldrb	r3, [r7, #7]
+ 8005776:	429a      	cmp	r2, r3
+ 8005778:	d116      	bne.n	80057a8 <I2C_WaitOnFlagUntilTimeout+0xa4>
         {
           hi2c->PreviousState     = I2C_STATE_NONE;
- 8004352:	68fb      	ldr	r3, [r7, #12]
- 8004354:	2200      	movs	r2, #0
- 8004356:	631a      	str	r2, [r3, #48]	@ 0x30
+ 800577a:	68fb      	ldr	r3, [r7, #12]
+ 800577c:	2200      	movs	r2, #0
+ 800577e:	631a      	str	r2, [r3, #48]	@ 0x30
           hi2c->State             = HAL_I2C_STATE_READY;
- 8004358:	68fb      	ldr	r3, [r7, #12]
- 800435a:	2220      	movs	r2, #32
- 800435c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005780:	68fb      	ldr	r3, [r7, #12]
+ 8005782:	2220      	movs	r2, #32
+ 8005784:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
           hi2c->Mode              = HAL_I2C_MODE_NONE;
- 8004360:	68fb      	ldr	r3, [r7, #12]
- 8004362:	2200      	movs	r2, #0
- 8004364:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005788:	68fb      	ldr	r3, [r7, #12]
+ 800578a:	2200      	movs	r2, #0
+ 800578c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
           hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
- 8004368:	68fb      	ldr	r3, [r7, #12]
- 800436a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 800436c:	f043 0220 	orr.w	r2, r3, #32
- 8004370:	68fb      	ldr	r3, [r7, #12]
- 8004372:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005790:	68fb      	ldr	r3, [r7, #12]
+ 8005792:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8005794:	f043 0220 	orr.w	r2, r3, #32
+ 8005798:	68fb      	ldr	r3, [r7, #12]
+ 800579a:	641a      	str	r2, [r3, #64]	@ 0x40
 
           /* Process Unlocked */
           __HAL_UNLOCK(hi2c);
- 8004374:	68fb      	ldr	r3, [r7, #12]
- 8004376:	2200      	movs	r2, #0
- 8004378:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 800579c:	68fb      	ldr	r3, [r7, #12]
+ 800579e:	2200      	movs	r2, #0
+ 80057a0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
           return HAL_ERROR;
- 800437c:	2301      	movs	r3, #1
- 800437e:	e023      	b.n	80043c8 <I2C_WaitOnFlagUntilTimeout+0xec>
+ 80057a4:	2301      	movs	r3, #1
+ 80057a6:	e023      	b.n	80057f0 <I2C_WaitOnFlagUntilTimeout+0xec>
   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- 8004380:	68bb      	ldr	r3, [r7, #8]
- 8004382:	0c1b      	lsrs	r3, r3, #16
- 8004384:	b2db      	uxtb	r3, r3
- 8004386:	2b01      	cmp	r3, #1
- 8004388:	d10d      	bne.n	80043a6 <I2C_WaitOnFlagUntilTimeout+0xca>
- 800438a:	68fb      	ldr	r3, [r7, #12]
- 800438c:	681b      	ldr	r3, [r3, #0]
- 800438e:	695b      	ldr	r3, [r3, #20]
- 8004390:	43da      	mvns	r2, r3
- 8004392:	68bb      	ldr	r3, [r7, #8]
- 8004394:	4013      	ands	r3, r2
- 8004396:	b29b      	uxth	r3, r3
- 8004398:	2b00      	cmp	r3, #0
- 800439a:	bf0c      	ite	eq
- 800439c:	2301      	moveq	r3, #1
- 800439e:	2300      	movne	r3, #0
- 80043a0:	b2db      	uxtb	r3, r3
- 80043a2:	461a      	mov	r2, r3
- 80043a4:	e00c      	b.n	80043c0 <I2C_WaitOnFlagUntilTimeout+0xe4>
- 80043a6:	68fb      	ldr	r3, [r7, #12]
- 80043a8:	681b      	ldr	r3, [r3, #0]
- 80043aa:	699b      	ldr	r3, [r3, #24]
- 80043ac:	43da      	mvns	r2, r3
- 80043ae:	68bb      	ldr	r3, [r7, #8]
- 80043b0:	4013      	ands	r3, r2
- 80043b2:	b29b      	uxth	r3, r3
- 80043b4:	2b00      	cmp	r3, #0
- 80043b6:	bf0c      	ite	eq
- 80043b8:	2301      	moveq	r3, #1
- 80043ba:	2300      	movne	r3, #0
- 80043bc:	b2db      	uxtb	r3, r3
- 80043be:	461a      	mov	r2, r3
- 80043c0:	79fb      	ldrb	r3, [r7, #7]
- 80043c2:	429a      	cmp	r2, r3
- 80043c4:	d093      	beq.n	80042ee <I2C_WaitOnFlagUntilTimeout+0x12>
+ 80057a8:	68bb      	ldr	r3, [r7, #8]
+ 80057aa:	0c1b      	lsrs	r3, r3, #16
+ 80057ac:	b2db      	uxtb	r3, r3
+ 80057ae:	2b01      	cmp	r3, #1
+ 80057b0:	d10d      	bne.n	80057ce <I2C_WaitOnFlagUntilTimeout+0xca>
+ 80057b2:	68fb      	ldr	r3, [r7, #12]
+ 80057b4:	681b      	ldr	r3, [r3, #0]
+ 80057b6:	695b      	ldr	r3, [r3, #20]
+ 80057b8:	43da      	mvns	r2, r3
+ 80057ba:	68bb      	ldr	r3, [r7, #8]
+ 80057bc:	4013      	ands	r3, r2
+ 80057be:	b29b      	uxth	r3, r3
+ 80057c0:	2b00      	cmp	r3, #0
+ 80057c2:	bf0c      	ite	eq
+ 80057c4:	2301      	moveq	r3, #1
+ 80057c6:	2300      	movne	r3, #0
+ 80057c8:	b2db      	uxtb	r3, r3
+ 80057ca:	461a      	mov	r2, r3
+ 80057cc:	e00c      	b.n	80057e8 <I2C_WaitOnFlagUntilTimeout+0xe4>
+ 80057ce:	68fb      	ldr	r3, [r7, #12]
+ 80057d0:	681b      	ldr	r3, [r3, #0]
+ 80057d2:	699b      	ldr	r3, [r3, #24]
+ 80057d4:	43da      	mvns	r2, r3
+ 80057d6:	68bb      	ldr	r3, [r7, #8]
+ 80057d8:	4013      	ands	r3, r2
+ 80057da:	b29b      	uxth	r3, r3
+ 80057dc:	2b00      	cmp	r3, #0
+ 80057de:	bf0c      	ite	eq
+ 80057e0:	2301      	moveq	r3, #1
+ 80057e2:	2300      	movne	r3, #0
+ 80057e4:	b2db      	uxtb	r3, r3
+ 80057e6:	461a      	mov	r2, r3
+ 80057e8:	79fb      	ldrb	r3, [r7, #7]
+ 80057ea:	429a      	cmp	r2, r3
+ 80057ec:	d093      	beq.n	8005716 <I2C_WaitOnFlagUntilTimeout+0x12>
         }
       }
     }
   }
   return HAL_OK;
- 80043c6:	2300      	movs	r3, #0
+ 80057ee:	2300      	movs	r3, #0
 }
- 80043c8:	4618      	mov	r0, r3
- 80043ca:	3710      	adds	r7, #16
- 80043cc:	46bd      	mov	sp, r7
- 80043ce:	bd80      	pop	{r7, pc}
+ 80057f0:	4618      	mov	r0, r3
+ 80057f2:	3710      	adds	r7, #16
+ 80057f4:	46bd      	mov	sp, r7
+ 80057f6:	bd80      	pop	{r7, pc}
 
-080043d0 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
+080057f8 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
 {
- 80043d0:	b580      	push	{r7, lr}
- 80043d2:	b084      	sub	sp, #16
- 80043d4:	af00      	add	r7, sp, #0
- 80043d6:	60f8      	str	r0, [r7, #12]
- 80043d8:	60b9      	str	r1, [r7, #8]
- 80043da:	607a      	str	r2, [r7, #4]
- 80043dc:	603b      	str	r3, [r7, #0]
+ 80057f8:	b580      	push	{r7, lr}
+ 80057fa:	b084      	sub	sp, #16
+ 80057fc:	af00      	add	r7, sp, #0
+ 80057fe:	60f8      	str	r0, [r7, #12]
+ 8005800:	60b9      	str	r1, [r7, #8]
+ 8005802:	607a      	str	r2, [r7, #4]
+ 8005804:	603b      	str	r3, [r7, #0]
   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
- 80043de:	e071      	b.n	80044c4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
+ 8005806:	e071      	b.n	80058ec <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
   {
     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- 80043e0:	68fb      	ldr	r3, [r7, #12]
- 80043e2:	681b      	ldr	r3, [r3, #0]
- 80043e4:	695b      	ldr	r3, [r3, #20]
- 80043e6:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
- 80043ea:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
- 80043ee:	d123      	bne.n	8004438 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
+ 8005808:	68fb      	ldr	r3, [r7, #12]
+ 800580a:	681b      	ldr	r3, [r3, #0]
+ 800580c:	695b      	ldr	r3, [r3, #20]
+ 800580e:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8005812:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
+ 8005816:	d123      	bne.n	8005860 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
     {
       /* Generate Stop */
       SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- 80043f0:	68fb      	ldr	r3, [r7, #12]
- 80043f2:	681b      	ldr	r3, [r3, #0]
- 80043f4:	681a      	ldr	r2, [r3, #0]
- 80043f6:	68fb      	ldr	r3, [r7, #12]
- 80043f8:	681b      	ldr	r3, [r3, #0]
- 80043fa:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
- 80043fe:	601a      	str	r2, [r3, #0]
+ 8005818:	68fb      	ldr	r3, [r7, #12]
+ 800581a:	681b      	ldr	r3, [r3, #0]
+ 800581c:	681a      	ldr	r2, [r3, #0]
+ 800581e:	68fb      	ldr	r3, [r7, #12]
+ 8005820:	681b      	ldr	r3, [r3, #0]
+ 8005822:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 8005826:	601a      	str	r2, [r3, #0]
 
       /* Clear AF Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- 8004400:	68fb      	ldr	r3, [r7, #12]
- 8004402:	681b      	ldr	r3, [r3, #0]
- 8004404:	f46f 6280 	mvn.w	r2, #1024	@ 0x400
- 8004408:	615a      	str	r2, [r3, #20]
+ 8005828:	68fb      	ldr	r3, [r7, #12]
+ 800582a:	681b      	ldr	r3, [r3, #0]
+ 800582c:	f46f 6280 	mvn.w	r2, #1024	@ 0x400
+ 8005830:	615a      	str	r2, [r3, #20]
 
       hi2c->PreviousState       = I2C_STATE_NONE;
- 800440a:	68fb      	ldr	r3, [r7, #12]
- 800440c:	2200      	movs	r2, #0
- 800440e:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005832:	68fb      	ldr	r3, [r7, #12]
+ 8005834:	2200      	movs	r2, #0
+ 8005836:	631a      	str	r2, [r3, #48]	@ 0x30
       hi2c->State               = HAL_I2C_STATE_READY;
- 8004410:	68fb      	ldr	r3, [r7, #12]
- 8004412:	2220      	movs	r2, #32
- 8004414:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005838:	68fb      	ldr	r3, [r7, #12]
+ 800583a:	2220      	movs	r2, #32
+ 800583c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
       hi2c->Mode                = HAL_I2C_MODE_NONE;
- 8004418:	68fb      	ldr	r3, [r7, #12]
- 800441a:	2200      	movs	r2, #0
- 800441c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005840:	68fb      	ldr	r3, [r7, #12]
+ 8005842:	2200      	movs	r2, #0
+ 8005844:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
       hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
- 8004420:	68fb      	ldr	r3, [r7, #12]
- 8004422:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004424:	f043 0204 	orr.w	r2, r3, #4
- 8004428:	68fb      	ldr	r3, [r7, #12]
- 800442a:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005848:	68fb      	ldr	r3, [r7, #12]
+ 800584a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 800584c:	f043 0204 	orr.w	r2, r3, #4
+ 8005850:	68fb      	ldr	r3, [r7, #12]
+ 8005852:	641a      	str	r2, [r3, #64]	@ 0x40
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
- 800442c:	68fb      	ldr	r3, [r7, #12]
- 800442e:	2200      	movs	r2, #0
- 8004430:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005854:	68fb      	ldr	r3, [r7, #12]
+ 8005856:	2200      	movs	r2, #0
+ 8005858:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
       return HAL_ERROR;
- 8004434:	2301      	movs	r3, #1
- 8004436:	e067      	b.n	8004508 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
+ 800585c:	2301      	movs	r3, #1
+ 800585e:	e067      	b.n	8005930 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
     }
 
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 8004438:	687b      	ldr	r3, [r7, #4]
- 800443a:	f1b3 3fff 	cmp.w	r3, #4294967295
- 800443e:	d041      	beq.n	80044c4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
+ 8005860:	687b      	ldr	r3, [r7, #4]
+ 8005862:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8005866:	d041      	beq.n	80058ec <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8004440:	f7fe fb82 	bl	8002b48 <HAL_GetTick>
- 8004444:	4602      	mov	r2, r0
- 8004446:	683b      	ldr	r3, [r7, #0]
- 8004448:	1ad3      	subs	r3, r2, r3
- 800444a:	687a      	ldr	r2, [r7, #4]
- 800444c:	429a      	cmp	r2, r3
- 800444e:	d302      	bcc.n	8004456 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
- 8004450:	687b      	ldr	r3, [r7, #4]
- 8004452:	2b00      	cmp	r3, #0
- 8004454:	d136      	bne.n	80044c4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
+ 8005868:	f7fd fd34 	bl	80032d4 <HAL_GetTick>
+ 800586c:	4602      	mov	r2, r0
+ 800586e:	683b      	ldr	r3, [r7, #0]
+ 8005870:	1ad3      	subs	r3, r2, r3
+ 8005872:	687a      	ldr	r2, [r7, #4]
+ 8005874:	429a      	cmp	r2, r3
+ 8005876:	d302      	bcc.n	800587e <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
+ 8005878:	687b      	ldr	r3, [r7, #4]
+ 800587a:	2b00      	cmp	r3, #0
+ 800587c:	d136      	bne.n	80058ec <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
       {
         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
- 8004456:	68bb      	ldr	r3, [r7, #8]
- 8004458:	0c1b      	lsrs	r3, r3, #16
- 800445a:	b2db      	uxtb	r3, r3
- 800445c:	2b01      	cmp	r3, #1
- 800445e:	d10c      	bne.n	800447a <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
- 8004460:	68fb      	ldr	r3, [r7, #12]
- 8004462:	681b      	ldr	r3, [r3, #0]
- 8004464:	695b      	ldr	r3, [r3, #20]
- 8004466:	43da      	mvns	r2, r3
- 8004468:	68bb      	ldr	r3, [r7, #8]
- 800446a:	4013      	ands	r3, r2
- 800446c:	b29b      	uxth	r3, r3
- 800446e:	2b00      	cmp	r3, #0
- 8004470:	bf14      	ite	ne
- 8004472:	2301      	movne	r3, #1
- 8004474:	2300      	moveq	r3, #0
- 8004476:	b2db      	uxtb	r3, r3
- 8004478:	e00b      	b.n	8004492 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
- 800447a:	68fb      	ldr	r3, [r7, #12]
- 800447c:	681b      	ldr	r3, [r3, #0]
- 800447e:	699b      	ldr	r3, [r3, #24]
- 8004480:	43da      	mvns	r2, r3
- 8004482:	68bb      	ldr	r3, [r7, #8]
- 8004484:	4013      	ands	r3, r2
- 8004486:	b29b      	uxth	r3, r3
- 8004488:	2b00      	cmp	r3, #0
- 800448a:	bf14      	ite	ne
- 800448c:	2301      	movne	r3, #1
- 800448e:	2300      	moveq	r3, #0
- 8004490:	b2db      	uxtb	r3, r3
- 8004492:	2b00      	cmp	r3, #0
- 8004494:	d016      	beq.n	80044c4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
+ 800587e:	68bb      	ldr	r3, [r7, #8]
+ 8005880:	0c1b      	lsrs	r3, r3, #16
+ 8005882:	b2db      	uxtb	r3, r3
+ 8005884:	2b01      	cmp	r3, #1
+ 8005886:	d10c      	bne.n	80058a2 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
+ 8005888:	68fb      	ldr	r3, [r7, #12]
+ 800588a:	681b      	ldr	r3, [r3, #0]
+ 800588c:	695b      	ldr	r3, [r3, #20]
+ 800588e:	43da      	mvns	r2, r3
+ 8005890:	68bb      	ldr	r3, [r7, #8]
+ 8005892:	4013      	ands	r3, r2
+ 8005894:	b29b      	uxth	r3, r3
+ 8005896:	2b00      	cmp	r3, #0
+ 8005898:	bf14      	ite	ne
+ 800589a:	2301      	movne	r3, #1
+ 800589c:	2300      	moveq	r3, #0
+ 800589e:	b2db      	uxtb	r3, r3
+ 80058a0:	e00b      	b.n	80058ba <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
+ 80058a2:	68fb      	ldr	r3, [r7, #12]
+ 80058a4:	681b      	ldr	r3, [r3, #0]
+ 80058a6:	699b      	ldr	r3, [r3, #24]
+ 80058a8:	43da      	mvns	r2, r3
+ 80058aa:	68bb      	ldr	r3, [r7, #8]
+ 80058ac:	4013      	ands	r3, r2
+ 80058ae:	b29b      	uxth	r3, r3
+ 80058b0:	2b00      	cmp	r3, #0
+ 80058b2:	bf14      	ite	ne
+ 80058b4:	2301      	movne	r3, #1
+ 80058b6:	2300      	moveq	r3, #0
+ 80058b8:	b2db      	uxtb	r3, r3
+ 80058ba:	2b00      	cmp	r3, #0
+ 80058bc:	d016      	beq.n	80058ec <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
         {
           hi2c->PreviousState       = I2C_STATE_NONE;
- 8004496:	68fb      	ldr	r3, [r7, #12]
- 8004498:	2200      	movs	r2, #0
- 800449a:	631a      	str	r2, [r3, #48]	@ 0x30
+ 80058be:	68fb      	ldr	r3, [r7, #12]
+ 80058c0:	2200      	movs	r2, #0
+ 80058c2:	631a      	str	r2, [r3, #48]	@ 0x30
           hi2c->State               = HAL_I2C_STATE_READY;
- 800449c:	68fb      	ldr	r3, [r7, #12]
- 800449e:	2220      	movs	r2, #32
- 80044a0:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 80058c4:	68fb      	ldr	r3, [r7, #12]
+ 80058c6:	2220      	movs	r2, #32
+ 80058c8:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
           hi2c->Mode                = HAL_I2C_MODE_NONE;
- 80044a4:	68fb      	ldr	r3, [r7, #12]
- 80044a6:	2200      	movs	r2, #0
- 80044a8:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 80058cc:	68fb      	ldr	r3, [r7, #12]
+ 80058ce:	2200      	movs	r2, #0
+ 80058d0:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
           hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
- 80044ac:	68fb      	ldr	r3, [r7, #12]
- 80044ae:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 80044b0:	f043 0220 	orr.w	r2, r3, #32
- 80044b4:	68fb      	ldr	r3, [r7, #12]
- 80044b6:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80058d4:	68fb      	ldr	r3, [r7, #12]
+ 80058d6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80058d8:	f043 0220 	orr.w	r2, r3, #32
+ 80058dc:	68fb      	ldr	r3, [r7, #12]
+ 80058de:	641a      	str	r2, [r3, #64]	@ 0x40
 
           /* Process Unlocked */
           __HAL_UNLOCK(hi2c);
- 80044b8:	68fb      	ldr	r3, [r7, #12]
- 80044ba:	2200      	movs	r2, #0
- 80044bc:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 80058e0:	68fb      	ldr	r3, [r7, #12]
+ 80058e2:	2200      	movs	r2, #0
+ 80058e4:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
           return HAL_ERROR;
- 80044c0:	2301      	movs	r3, #1
- 80044c2:	e021      	b.n	8004508 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
+ 80058e8:	2301      	movs	r3, #1
+ 80058ea:	e021      	b.n	8005930 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
- 80044c4:	68bb      	ldr	r3, [r7, #8]
- 80044c6:	0c1b      	lsrs	r3, r3, #16
- 80044c8:	b2db      	uxtb	r3, r3
- 80044ca:	2b01      	cmp	r3, #1
- 80044cc:	d10c      	bne.n	80044e8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
- 80044ce:	68fb      	ldr	r3, [r7, #12]
- 80044d0:	681b      	ldr	r3, [r3, #0]
- 80044d2:	695b      	ldr	r3, [r3, #20]
- 80044d4:	43da      	mvns	r2, r3
- 80044d6:	68bb      	ldr	r3, [r7, #8]
- 80044d8:	4013      	ands	r3, r2
- 80044da:	b29b      	uxth	r3, r3
- 80044dc:	2b00      	cmp	r3, #0
- 80044de:	bf14      	ite	ne
- 80044e0:	2301      	movne	r3, #1
- 80044e2:	2300      	moveq	r3, #0
- 80044e4:	b2db      	uxtb	r3, r3
- 80044e6:	e00b      	b.n	8004500 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
- 80044e8:	68fb      	ldr	r3, [r7, #12]
- 80044ea:	681b      	ldr	r3, [r3, #0]
- 80044ec:	699b      	ldr	r3, [r3, #24]
- 80044ee:	43da      	mvns	r2, r3
- 80044f0:	68bb      	ldr	r3, [r7, #8]
- 80044f2:	4013      	ands	r3, r2
- 80044f4:	b29b      	uxth	r3, r3
- 80044f6:	2b00      	cmp	r3, #0
- 80044f8:	bf14      	ite	ne
- 80044fa:	2301      	movne	r3, #1
- 80044fc:	2300      	moveq	r3, #0
- 80044fe:	b2db      	uxtb	r3, r3
- 8004500:	2b00      	cmp	r3, #0
- 8004502:	f47f af6d 	bne.w	80043e0 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
+ 80058ec:	68bb      	ldr	r3, [r7, #8]
+ 80058ee:	0c1b      	lsrs	r3, r3, #16
+ 80058f0:	b2db      	uxtb	r3, r3
+ 80058f2:	2b01      	cmp	r3, #1
+ 80058f4:	d10c      	bne.n	8005910 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
+ 80058f6:	68fb      	ldr	r3, [r7, #12]
+ 80058f8:	681b      	ldr	r3, [r3, #0]
+ 80058fa:	695b      	ldr	r3, [r3, #20]
+ 80058fc:	43da      	mvns	r2, r3
+ 80058fe:	68bb      	ldr	r3, [r7, #8]
+ 8005900:	4013      	ands	r3, r2
+ 8005902:	b29b      	uxth	r3, r3
+ 8005904:	2b00      	cmp	r3, #0
+ 8005906:	bf14      	ite	ne
+ 8005908:	2301      	movne	r3, #1
+ 800590a:	2300      	moveq	r3, #0
+ 800590c:	b2db      	uxtb	r3, r3
+ 800590e:	e00b      	b.n	8005928 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
+ 8005910:	68fb      	ldr	r3, [r7, #12]
+ 8005912:	681b      	ldr	r3, [r3, #0]
+ 8005914:	699b      	ldr	r3, [r3, #24]
+ 8005916:	43da      	mvns	r2, r3
+ 8005918:	68bb      	ldr	r3, [r7, #8]
+ 800591a:	4013      	ands	r3, r2
+ 800591c:	b29b      	uxth	r3, r3
+ 800591e:	2b00      	cmp	r3, #0
+ 8005920:	bf14      	ite	ne
+ 8005922:	2301      	movne	r3, #1
+ 8005924:	2300      	moveq	r3, #0
+ 8005926:	b2db      	uxtb	r3, r3
+ 8005928:	2b00      	cmp	r3, #0
+ 800592a:	f47f af6d 	bne.w	8005808 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
         }
       }
     }
   }
   return HAL_OK;
- 8004506:	2300      	movs	r3, #0
+ 800592e:	2300      	movs	r3, #0
 }
- 8004508:	4618      	mov	r0, r3
- 800450a:	3710      	adds	r7, #16
- 800450c:	46bd      	mov	sp, r7
- 800450e:	bd80      	pop	{r7, pc}
+ 8005930:	4618      	mov	r0, r3
+ 8005932:	3710      	adds	r7, #16
+ 8005934:	46bd      	mov	sp, r7
+ 8005936:	bd80      	pop	{r7, pc}
 
-08004510 <I2C_WaitOnTXEFlagUntilTimeout>:
+08005938 <I2C_WaitOnTXEFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
- 8004510:	b580      	push	{r7, lr}
- 8004512:	b084      	sub	sp, #16
- 8004514:	af00      	add	r7, sp, #0
- 8004516:	60f8      	str	r0, [r7, #12]
- 8004518:	60b9      	str	r1, [r7, #8]
- 800451a:	607a      	str	r2, [r7, #4]
+ 8005938:	b580      	push	{r7, lr}
+ 800593a:	b084      	sub	sp, #16
+ 800593c:	af00      	add	r7, sp, #0
+ 800593e:	60f8      	str	r0, [r7, #12]
+ 8005940:	60b9      	str	r1, [r7, #8]
+ 8005942:	607a      	str	r2, [r7, #4]
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- 800451c:	e034      	b.n	8004588 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
+ 8005944:	e034      	b.n	80059b0 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
   {
     /* Check if a NACK is detected */
     if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
- 800451e:	68f8      	ldr	r0, [r7, #12]
- 8004520:	f000 f8e3 	bl	80046ea <I2C_IsAcknowledgeFailed>
- 8004524:	4603      	mov	r3, r0
- 8004526:	2b00      	cmp	r3, #0
- 8004528:	d001      	beq.n	800452e <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
+ 8005946:	68f8      	ldr	r0, [r7, #12]
+ 8005948:	f000 f8e3 	bl	8005b12 <I2C_IsAcknowledgeFailed>
+ 800594c:	4603      	mov	r3, r0
+ 800594e:	2b00      	cmp	r3, #0
+ 8005950:	d001      	beq.n	8005956 <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
     {
       return HAL_ERROR;
- 800452a:	2301      	movs	r3, #1
- 800452c:	e034      	b.n	8004598 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
+ 8005952:	2301      	movs	r3, #1
+ 8005954:	e034      	b.n	80059c0 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
     }
 
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 800452e:	68bb      	ldr	r3, [r7, #8]
- 8004530:	f1b3 3fff 	cmp.w	r3, #4294967295
- 8004534:	d028      	beq.n	8004588 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
+ 8005956:	68bb      	ldr	r3, [r7, #8]
+ 8005958:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 800595c:	d028      	beq.n	80059b0 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8004536:	f7fe fb07 	bl	8002b48 <HAL_GetTick>
- 800453a:	4602      	mov	r2, r0
- 800453c:	687b      	ldr	r3, [r7, #4]
- 800453e:	1ad3      	subs	r3, r2, r3
- 8004540:	68ba      	ldr	r2, [r7, #8]
- 8004542:	429a      	cmp	r2, r3
- 8004544:	d302      	bcc.n	800454c <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
- 8004546:	68bb      	ldr	r3, [r7, #8]
- 8004548:	2b00      	cmp	r3, #0
- 800454a:	d11d      	bne.n	8004588 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
+ 800595e:	f7fd fcb9 	bl	80032d4 <HAL_GetTick>
+ 8005962:	4602      	mov	r2, r0
+ 8005964:	687b      	ldr	r3, [r7, #4]
+ 8005966:	1ad3      	subs	r3, r2, r3
+ 8005968:	68ba      	ldr	r2, [r7, #8]
+ 800596a:	429a      	cmp	r2, r3
+ 800596c:	d302      	bcc.n	8005974 <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
+ 800596e:	68bb      	ldr	r3, [r7, #8]
+ 8005970:	2b00      	cmp	r3, #0
+ 8005972:	d11d      	bne.n	80059b0 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
       {
         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
- 800454c:	68fb      	ldr	r3, [r7, #12]
- 800454e:	681b      	ldr	r3, [r3, #0]
- 8004550:	695b      	ldr	r3, [r3, #20]
- 8004552:	f003 0380 	and.w	r3, r3, #128	@ 0x80
- 8004556:	2b80      	cmp	r3, #128	@ 0x80
- 8004558:	d016      	beq.n	8004588 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
+ 8005974:	68fb      	ldr	r3, [r7, #12]
+ 8005976:	681b      	ldr	r3, [r3, #0]
+ 8005978:	695b      	ldr	r3, [r3, #20]
+ 800597a:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 800597e:	2b80      	cmp	r3, #128	@ 0x80
+ 8005980:	d016      	beq.n	80059b0 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
         {
           hi2c->PreviousState       = I2C_STATE_NONE;
- 800455a:	68fb      	ldr	r3, [r7, #12]
- 800455c:	2200      	movs	r2, #0
- 800455e:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005982:	68fb      	ldr	r3, [r7, #12]
+ 8005984:	2200      	movs	r2, #0
+ 8005986:	631a      	str	r2, [r3, #48]	@ 0x30
           hi2c->State               = HAL_I2C_STATE_READY;
- 8004560:	68fb      	ldr	r3, [r7, #12]
- 8004562:	2220      	movs	r2, #32
- 8004564:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005988:	68fb      	ldr	r3, [r7, #12]
+ 800598a:	2220      	movs	r2, #32
+ 800598c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
           hi2c->Mode                = HAL_I2C_MODE_NONE;
- 8004568:	68fb      	ldr	r3, [r7, #12]
- 800456a:	2200      	movs	r2, #0
- 800456c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005990:	68fb      	ldr	r3, [r7, #12]
+ 8005992:	2200      	movs	r2, #0
+ 8005994:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
           hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
- 8004570:	68fb      	ldr	r3, [r7, #12]
- 8004572:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004574:	f043 0220 	orr.w	r2, r3, #32
- 8004578:	68fb      	ldr	r3, [r7, #12]
- 800457a:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005998:	68fb      	ldr	r3, [r7, #12]
+ 800599a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 800599c:	f043 0220 	orr.w	r2, r3, #32
+ 80059a0:	68fb      	ldr	r3, [r7, #12]
+ 80059a2:	641a      	str	r2, [r3, #64]	@ 0x40
 
           /* Process Unlocked */
           __HAL_UNLOCK(hi2c);
- 800457c:	68fb      	ldr	r3, [r7, #12]
- 800457e:	2200      	movs	r2, #0
- 8004580:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 80059a4:	68fb      	ldr	r3, [r7, #12]
+ 80059a6:	2200      	movs	r2, #0
+ 80059a8:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
           return HAL_ERROR;
- 8004584:	2301      	movs	r3, #1
- 8004586:	e007      	b.n	8004598 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
+ 80059ac:	2301      	movs	r3, #1
+ 80059ae:	e007      	b.n	80059c0 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- 8004588:	68fb      	ldr	r3, [r7, #12]
- 800458a:	681b      	ldr	r3, [r3, #0]
- 800458c:	695b      	ldr	r3, [r3, #20]
- 800458e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
- 8004592:	2b80      	cmp	r3, #128	@ 0x80
- 8004594:	d1c3      	bne.n	800451e <I2C_WaitOnTXEFlagUntilTimeout+0xe>
+ 80059b0:	68fb      	ldr	r3, [r7, #12]
+ 80059b2:	681b      	ldr	r3, [r3, #0]
+ 80059b4:	695b      	ldr	r3, [r3, #20]
+ 80059b6:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 80059ba:	2b80      	cmp	r3, #128	@ 0x80
+ 80059bc:	d1c3      	bne.n	8005946 <I2C_WaitOnTXEFlagUntilTimeout+0xe>
         }
       }
     }
   }
   return HAL_OK;
- 8004596:	2300      	movs	r3, #0
+ 80059be:	2300      	movs	r3, #0
 }
- 8004598:	4618      	mov	r0, r3
- 800459a:	3710      	adds	r7, #16
- 800459c:	46bd      	mov	sp, r7
- 800459e:	bd80      	pop	{r7, pc}
+ 80059c0:	4618      	mov	r0, r3
+ 80059c2:	3710      	adds	r7, #16
+ 80059c4:	46bd      	mov	sp, r7
+ 80059c6:	bd80      	pop	{r7, pc}
 
-080045a0 <I2C_WaitOnBTFFlagUntilTimeout>:
+080059c8 <I2C_WaitOnBTFFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
- 80045a0:	b580      	push	{r7, lr}
- 80045a2:	b084      	sub	sp, #16
- 80045a4:	af00      	add	r7, sp, #0
- 80045a6:	60f8      	str	r0, [r7, #12]
- 80045a8:	60b9      	str	r1, [r7, #8]
- 80045aa:	607a      	str	r2, [r7, #4]
+ 80059c8:	b580      	push	{r7, lr}
+ 80059ca:	b084      	sub	sp, #16
+ 80059cc:	af00      	add	r7, sp, #0
+ 80059ce:	60f8      	str	r0, [r7, #12]
+ 80059d0:	60b9      	str	r1, [r7, #8]
+ 80059d2:	607a      	str	r2, [r7, #4]
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
- 80045ac:	e034      	b.n	8004618 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
+ 80059d4:	e034      	b.n	8005a40 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
   {
     /* Check if a NACK is detected */
     if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
- 80045ae:	68f8      	ldr	r0, [r7, #12]
- 80045b0:	f000 f89b 	bl	80046ea <I2C_IsAcknowledgeFailed>
- 80045b4:	4603      	mov	r3, r0
- 80045b6:	2b00      	cmp	r3, #0
- 80045b8:	d001      	beq.n	80045be <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
+ 80059d6:	68f8      	ldr	r0, [r7, #12]
+ 80059d8:	f000 f89b 	bl	8005b12 <I2C_IsAcknowledgeFailed>
+ 80059dc:	4603      	mov	r3, r0
+ 80059de:	2b00      	cmp	r3, #0
+ 80059e0:	d001      	beq.n	80059e6 <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
     {
       return HAL_ERROR;
- 80045ba:	2301      	movs	r3, #1
- 80045bc:	e034      	b.n	8004628 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
+ 80059e2:	2301      	movs	r3, #1
+ 80059e4:	e034      	b.n	8005a50 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
     }
 
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 80045be:	68bb      	ldr	r3, [r7, #8]
- 80045c0:	f1b3 3fff 	cmp.w	r3, #4294967295
- 80045c4:	d028      	beq.n	8004618 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
+ 80059e6:	68bb      	ldr	r3, [r7, #8]
+ 80059e8:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 80059ec:	d028      	beq.n	8005a40 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 80045c6:	f7fe fabf 	bl	8002b48 <HAL_GetTick>
- 80045ca:	4602      	mov	r2, r0
- 80045cc:	687b      	ldr	r3, [r7, #4]
- 80045ce:	1ad3      	subs	r3, r2, r3
- 80045d0:	68ba      	ldr	r2, [r7, #8]
- 80045d2:	429a      	cmp	r2, r3
- 80045d4:	d302      	bcc.n	80045dc <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
- 80045d6:	68bb      	ldr	r3, [r7, #8]
- 80045d8:	2b00      	cmp	r3, #0
- 80045da:	d11d      	bne.n	8004618 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
+ 80059ee:	f7fd fc71 	bl	80032d4 <HAL_GetTick>
+ 80059f2:	4602      	mov	r2, r0
+ 80059f4:	687b      	ldr	r3, [r7, #4]
+ 80059f6:	1ad3      	subs	r3, r2, r3
+ 80059f8:	68ba      	ldr	r2, [r7, #8]
+ 80059fa:	429a      	cmp	r2, r3
+ 80059fc:	d302      	bcc.n	8005a04 <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
+ 80059fe:	68bb      	ldr	r3, [r7, #8]
+ 8005a00:	2b00      	cmp	r3, #0
+ 8005a02:	d11d      	bne.n	8005a40 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
       {
         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
- 80045dc:	68fb      	ldr	r3, [r7, #12]
- 80045de:	681b      	ldr	r3, [r3, #0]
- 80045e0:	695b      	ldr	r3, [r3, #20]
- 80045e2:	f003 0304 	and.w	r3, r3, #4
- 80045e6:	2b04      	cmp	r3, #4
- 80045e8:	d016      	beq.n	8004618 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
+ 8005a04:	68fb      	ldr	r3, [r7, #12]
+ 8005a06:	681b      	ldr	r3, [r3, #0]
+ 8005a08:	695b      	ldr	r3, [r3, #20]
+ 8005a0a:	f003 0304 	and.w	r3, r3, #4
+ 8005a0e:	2b04      	cmp	r3, #4
+ 8005a10:	d016      	beq.n	8005a40 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
         {
           hi2c->PreviousState       = I2C_STATE_NONE;
- 80045ea:	68fb      	ldr	r3, [r7, #12]
- 80045ec:	2200      	movs	r2, #0
- 80045ee:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005a12:	68fb      	ldr	r3, [r7, #12]
+ 8005a14:	2200      	movs	r2, #0
+ 8005a16:	631a      	str	r2, [r3, #48]	@ 0x30
           hi2c->State               = HAL_I2C_STATE_READY;
- 80045f0:	68fb      	ldr	r3, [r7, #12]
- 80045f2:	2220      	movs	r2, #32
- 80045f4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005a18:	68fb      	ldr	r3, [r7, #12]
+ 8005a1a:	2220      	movs	r2, #32
+ 8005a1c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
           hi2c->Mode                = HAL_I2C_MODE_NONE;
- 80045f8:	68fb      	ldr	r3, [r7, #12]
- 80045fa:	2200      	movs	r2, #0
- 80045fc:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005a20:	68fb      	ldr	r3, [r7, #12]
+ 8005a22:	2200      	movs	r2, #0
+ 8005a24:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
           hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
- 8004600:	68fb      	ldr	r3, [r7, #12]
- 8004602:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004604:	f043 0220 	orr.w	r2, r3, #32
- 8004608:	68fb      	ldr	r3, [r7, #12]
- 800460a:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005a28:	68fb      	ldr	r3, [r7, #12]
+ 8005a2a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8005a2c:	f043 0220 	orr.w	r2, r3, #32
+ 8005a30:	68fb      	ldr	r3, [r7, #12]
+ 8005a32:	641a      	str	r2, [r3, #64]	@ 0x40
 
           /* Process Unlocked */
           __HAL_UNLOCK(hi2c);
- 800460c:	68fb      	ldr	r3, [r7, #12]
- 800460e:	2200      	movs	r2, #0
- 8004610:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005a34:	68fb      	ldr	r3, [r7, #12]
+ 8005a36:	2200      	movs	r2, #0
+ 8005a38:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
           return HAL_ERROR;
- 8004614:	2301      	movs	r3, #1
- 8004616:	e007      	b.n	8004628 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
+ 8005a3c:	2301      	movs	r3, #1
+ 8005a3e:	e007      	b.n	8005a50 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
- 8004618:	68fb      	ldr	r3, [r7, #12]
- 800461a:	681b      	ldr	r3, [r3, #0]
- 800461c:	695b      	ldr	r3, [r3, #20]
- 800461e:	f003 0304 	and.w	r3, r3, #4
- 8004622:	2b04      	cmp	r3, #4
- 8004624:	d1c3      	bne.n	80045ae <I2C_WaitOnBTFFlagUntilTimeout+0xe>
+ 8005a40:	68fb      	ldr	r3, [r7, #12]
+ 8005a42:	681b      	ldr	r3, [r3, #0]
+ 8005a44:	695b      	ldr	r3, [r3, #20]
+ 8005a46:	f003 0304 	and.w	r3, r3, #4
+ 8005a4a:	2b04      	cmp	r3, #4
+ 8005a4c:	d1c3      	bne.n	80059d6 <I2C_WaitOnBTFFlagUntilTimeout+0xe>
         }
       }
     }
   }
   return HAL_OK;
- 8004626:	2300      	movs	r3, #0
+ 8005a4e:	2300      	movs	r3, #0
 }
- 8004628:	4618      	mov	r0, r3
- 800462a:	3710      	adds	r7, #16
- 800462c:	46bd      	mov	sp, r7
- 800462e:	bd80      	pop	{r7, pc}
+ 8005a50:	4618      	mov	r0, r3
+ 8005a52:	3710      	adds	r7, #16
+ 8005a54:	46bd      	mov	sp, r7
+ 8005a56:	bd80      	pop	{r7, pc}
 
-08004630 <I2C_WaitOnRXNEFlagUntilTimeout>:
+08005a58 <I2C_WaitOnRXNEFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
- 8004630:	b580      	push	{r7, lr}
- 8004632:	b084      	sub	sp, #16
- 8004634:	af00      	add	r7, sp, #0
- 8004636:	60f8      	str	r0, [r7, #12]
- 8004638:	60b9      	str	r1, [r7, #8]
- 800463a:	607a      	str	r2, [r7, #4]
+ 8005a58:	b580      	push	{r7, lr}
+ 8005a5a:	b084      	sub	sp, #16
+ 8005a5c:	af00      	add	r7, sp, #0
+ 8005a5e:	60f8      	str	r0, [r7, #12]
+ 8005a60:	60b9      	str	r1, [r7, #8]
+ 8005a62:	607a      	str	r2, [r7, #4]
 
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- 800463c:	e049      	b.n	80046d2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
+ 8005a64:	e049      	b.n	8005afa <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
   {
     /* Check if a STOPF is detected */
     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- 800463e:	68fb      	ldr	r3, [r7, #12]
- 8004640:	681b      	ldr	r3, [r3, #0]
- 8004642:	695b      	ldr	r3, [r3, #20]
- 8004644:	f003 0310 	and.w	r3, r3, #16
- 8004648:	2b10      	cmp	r3, #16
- 800464a:	d119      	bne.n	8004680 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
+ 8005a66:	68fb      	ldr	r3, [r7, #12]
+ 8005a68:	681b      	ldr	r3, [r3, #0]
+ 8005a6a:	695b      	ldr	r3, [r3, #20]
+ 8005a6c:	f003 0310 	and.w	r3, r3, #16
+ 8005a70:	2b10      	cmp	r3, #16
+ 8005a72:	d119      	bne.n	8005aa8 <I2C_WaitOnRXNEFlagUntilTimeout+0x50>
     {
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 800464c:	68fb      	ldr	r3, [r7, #12]
- 800464e:	681b      	ldr	r3, [r3, #0]
- 8004650:	f06f 0210 	mvn.w	r2, #16
- 8004654:	615a      	str	r2, [r3, #20]
+ 8005a74:	68fb      	ldr	r3, [r7, #12]
+ 8005a76:	681b      	ldr	r3, [r3, #0]
+ 8005a78:	f06f 0210 	mvn.w	r2, #16
+ 8005a7c:	615a      	str	r2, [r3, #20]
 
       hi2c->PreviousState       = I2C_STATE_NONE;
- 8004656:	68fb      	ldr	r3, [r7, #12]
- 8004658:	2200      	movs	r2, #0
- 800465a:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005a7e:	68fb      	ldr	r3, [r7, #12]
+ 8005a80:	2200      	movs	r2, #0
+ 8005a82:	631a      	str	r2, [r3, #48]	@ 0x30
       hi2c->State               = HAL_I2C_STATE_READY;
- 800465c:	68fb      	ldr	r3, [r7, #12]
- 800465e:	2220      	movs	r2, #32
- 8004660:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005a84:	68fb      	ldr	r3, [r7, #12]
+ 8005a86:	2220      	movs	r2, #32
+ 8005a88:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
       hi2c->Mode                = HAL_I2C_MODE_NONE;
- 8004664:	68fb      	ldr	r3, [r7, #12]
- 8004666:	2200      	movs	r2, #0
- 8004668:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005a8c:	68fb      	ldr	r3, [r7, #12]
+ 8005a8e:	2200      	movs	r2, #0
+ 8005a90:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
       hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;
- 800466c:	68fb      	ldr	r3, [r7, #12]
- 800466e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8004670:	68fb      	ldr	r3, [r7, #12]
- 8004672:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005a94:	68fb      	ldr	r3, [r7, #12]
+ 8005a96:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 8005a98:	68fb      	ldr	r3, [r7, #12]
+ 8005a9a:	641a      	str	r2, [r3, #64]	@ 0x40
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
- 8004674:	68fb      	ldr	r3, [r7, #12]
- 8004676:	2200      	movs	r2, #0
- 8004678:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005a9c:	68fb      	ldr	r3, [r7, #12]
+ 8005a9e:	2200      	movs	r2, #0
+ 8005aa0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
       return HAL_ERROR;
- 800467c:	2301      	movs	r3, #1
- 800467e:	e030      	b.n	80046e2 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
+ 8005aa4:	2301      	movs	r3, #1
+ 8005aa6:	e030      	b.n	8005b0a <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
     }
 
     /* Check for the Timeout */
     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8004680:	f7fe fa62 	bl	8002b48 <HAL_GetTick>
- 8004684:	4602      	mov	r2, r0
- 8004686:	687b      	ldr	r3, [r7, #4]
- 8004688:	1ad3      	subs	r3, r2, r3
- 800468a:	68ba      	ldr	r2, [r7, #8]
- 800468c:	429a      	cmp	r2, r3
- 800468e:	d302      	bcc.n	8004696 <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
- 8004690:	68bb      	ldr	r3, [r7, #8]
- 8004692:	2b00      	cmp	r3, #0
- 8004694:	d11d      	bne.n	80046d2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
+ 8005aa8:	f7fd fc14 	bl	80032d4 <HAL_GetTick>
+ 8005aac:	4602      	mov	r2, r0
+ 8005aae:	687b      	ldr	r3, [r7, #4]
+ 8005ab0:	1ad3      	subs	r3, r2, r3
+ 8005ab2:	68ba      	ldr	r2, [r7, #8]
+ 8005ab4:	429a      	cmp	r2, r3
+ 8005ab6:	d302      	bcc.n	8005abe <I2C_WaitOnRXNEFlagUntilTimeout+0x66>
+ 8005ab8:	68bb      	ldr	r3, [r7, #8]
+ 8005aba:	2b00      	cmp	r3, #0
+ 8005abc:	d11d      	bne.n	8005afa <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
     {
       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
- 8004696:	68fb      	ldr	r3, [r7, #12]
- 8004698:	681b      	ldr	r3, [r3, #0]
- 800469a:	695b      	ldr	r3, [r3, #20]
- 800469c:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 80046a0:	2b40      	cmp	r3, #64	@ 0x40
- 80046a2:	d016      	beq.n	80046d2 <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
+ 8005abe:	68fb      	ldr	r3, [r7, #12]
+ 8005ac0:	681b      	ldr	r3, [r3, #0]
+ 8005ac2:	695b      	ldr	r3, [r3, #20]
+ 8005ac4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8005ac8:	2b40      	cmp	r3, #64	@ 0x40
+ 8005aca:	d016      	beq.n	8005afa <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
       {
         hi2c->PreviousState       = I2C_STATE_NONE;
- 80046a4:	68fb      	ldr	r3, [r7, #12]
- 80046a6:	2200      	movs	r2, #0
- 80046a8:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005acc:	68fb      	ldr	r3, [r7, #12]
+ 8005ace:	2200      	movs	r2, #0
+ 8005ad0:	631a      	str	r2, [r3, #48]	@ 0x30
         hi2c->State               = HAL_I2C_STATE_READY;
- 80046aa:	68fb      	ldr	r3, [r7, #12]
- 80046ac:	2220      	movs	r2, #32
- 80046ae:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005ad2:	68fb      	ldr	r3, [r7, #12]
+ 8005ad4:	2220      	movs	r2, #32
+ 8005ad6:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
         hi2c->Mode                = HAL_I2C_MODE_NONE;
- 80046b2:	68fb      	ldr	r3, [r7, #12]
- 80046b4:	2200      	movs	r2, #0
- 80046b6:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005ada:	68fb      	ldr	r3, [r7, #12]
+ 8005adc:	2200      	movs	r2, #0
+ 8005ade:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
         hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
- 80046ba:	68fb      	ldr	r3, [r7, #12]
- 80046bc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 80046be:	f043 0220 	orr.w	r2, r3, #32
- 80046c2:	68fb      	ldr	r3, [r7, #12]
- 80046c4:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005ae2:	68fb      	ldr	r3, [r7, #12]
+ 8005ae4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8005ae6:	f043 0220 	orr.w	r2, r3, #32
+ 8005aea:	68fb      	ldr	r3, [r7, #12]
+ 8005aec:	641a      	str	r2, [r3, #64]	@ 0x40
 
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
- 80046c6:	68fb      	ldr	r3, [r7, #12]
- 80046c8:	2200      	movs	r2, #0
- 80046ca:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005aee:	68fb      	ldr	r3, [r7, #12]
+ 8005af0:	2200      	movs	r2, #0
+ 8005af2:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
         return HAL_ERROR;
- 80046ce:	2301      	movs	r3, #1
- 80046d0:	e007      	b.n	80046e2 <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
+ 8005af6:	2301      	movs	r3, #1
+ 8005af8:	e007      	b.n	8005b0a <I2C_WaitOnRXNEFlagUntilTimeout+0xb2>
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- 80046d2:	68fb      	ldr	r3, [r7, #12]
- 80046d4:	681b      	ldr	r3, [r3, #0]
- 80046d6:	695b      	ldr	r3, [r3, #20]
- 80046d8:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 80046dc:	2b40      	cmp	r3, #64	@ 0x40
- 80046de:	d1ae      	bne.n	800463e <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
+ 8005afa:	68fb      	ldr	r3, [r7, #12]
+ 8005afc:	681b      	ldr	r3, [r3, #0]
+ 8005afe:	695b      	ldr	r3, [r3, #20]
+ 8005b00:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8005b04:	2b40      	cmp	r3, #64	@ 0x40
+ 8005b06:	d1ae      	bne.n	8005a66 <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
       }
     }
   }
   return HAL_OK;
- 80046e0:	2300      	movs	r3, #0
+ 8005b08:	2300      	movs	r3, #0
 }
- 80046e2:	4618      	mov	r0, r3
- 80046e4:	3710      	adds	r7, #16
- 80046e6:	46bd      	mov	sp, r7
- 80046e8:	bd80      	pop	{r7, pc}
+ 8005b0a:	4618      	mov	r0, r3
+ 8005b0c:	3710      	adds	r7, #16
+ 8005b0e:	46bd      	mov	sp, r7
+ 8005b10:	bd80      	pop	{r7, pc}
 
-080046ea <I2C_IsAcknowledgeFailed>:
+08005b12 <I2C_IsAcknowledgeFailed>:
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
 {
- 80046ea:	b480      	push	{r7}
- 80046ec:	b083      	sub	sp, #12
- 80046ee:	af00      	add	r7, sp, #0
- 80046f0:	6078      	str	r0, [r7, #4]
+ 8005b12:	b480      	push	{r7}
+ 8005b14:	b083      	sub	sp, #12
+ 8005b16:	af00      	add	r7, sp, #0
+ 8005b18:	6078      	str	r0, [r7, #4]
   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- 80046f2:	687b      	ldr	r3, [r7, #4]
- 80046f4:	681b      	ldr	r3, [r3, #0]
- 80046f6:	695b      	ldr	r3, [r3, #20]
- 80046f8:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
- 80046fc:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
- 8004700:	d11b      	bne.n	800473a <I2C_IsAcknowledgeFailed+0x50>
+ 8005b1a:	687b      	ldr	r3, [r7, #4]
+ 8005b1c:	681b      	ldr	r3, [r3, #0]
+ 8005b1e:	695b      	ldr	r3, [r3, #20]
+ 8005b20:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8005b24:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
+ 8005b28:	d11b      	bne.n	8005b62 <I2C_IsAcknowledgeFailed+0x50>
   {
     /* Clear NACKF Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- 8004702:	687b      	ldr	r3, [r7, #4]
- 8004704:	681b      	ldr	r3, [r3, #0]
- 8004706:	f46f 6280 	mvn.w	r2, #1024	@ 0x400
- 800470a:	615a      	str	r2, [r3, #20]
+ 8005b2a:	687b      	ldr	r3, [r7, #4]
+ 8005b2c:	681b      	ldr	r3, [r3, #0]
+ 8005b2e:	f46f 6280 	mvn.w	r2, #1024	@ 0x400
+ 8005b32:	615a      	str	r2, [r3, #20]
 
     hi2c->PreviousState       = I2C_STATE_NONE;
- 800470c:	687b      	ldr	r3, [r7, #4]
- 800470e:	2200      	movs	r2, #0
- 8004710:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8005b34:	687b      	ldr	r3, [r7, #4]
+ 8005b36:	2200      	movs	r2, #0
+ 8005b38:	631a      	str	r2, [r3, #48]	@ 0x30
     hi2c->State               = HAL_I2C_STATE_READY;
- 8004712:	687b      	ldr	r3, [r7, #4]
- 8004714:	2220      	movs	r2, #32
- 8004716:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+ 8005b3a:	687b      	ldr	r3, [r7, #4]
+ 8005b3c:	2220      	movs	r2, #32
+ 8005b3e:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
     hi2c->Mode                = HAL_I2C_MODE_NONE;
- 800471a:	687b      	ldr	r3, [r7, #4]
- 800471c:	2200      	movs	r2, #0
- 800471e:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 8005b42:	687b      	ldr	r3, [r7, #4]
+ 8005b44:	2200      	movs	r2, #0
+ 8005b46:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
     hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
- 8004722:	687b      	ldr	r3, [r7, #4]
- 8004724:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004726:	f043 0204 	orr.w	r2, r3, #4
- 800472a:	687b      	ldr	r3, [r7, #4]
- 800472c:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8005b4a:	687b      	ldr	r3, [r7, #4]
+ 8005b4c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8005b4e:	f043 0204 	orr.w	r2, r3, #4
+ 8005b52:	687b      	ldr	r3, [r7, #4]
+ 8005b54:	641a      	str	r2, [r3, #64]	@ 0x40
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
- 800472e:	687b      	ldr	r3, [r7, #4]
- 8004730:	2200      	movs	r2, #0
- 8004732:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8005b56:	687b      	ldr	r3, [r7, #4]
+ 8005b58:	2200      	movs	r2, #0
+ 8005b5a:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
 
     return HAL_ERROR;
- 8004736:	2301      	movs	r3, #1
- 8004738:	e000      	b.n	800473c <I2C_IsAcknowledgeFailed+0x52>
+ 8005b5e:	2301      	movs	r3, #1
+ 8005b60:	e000      	b.n	8005b64 <I2C_IsAcknowledgeFailed+0x52>
   }
   return HAL_OK;
- 800473a:	2300      	movs	r3, #0
+ 8005b62:	2300      	movs	r3, #0
 }
- 800473c:	4618      	mov	r0, r3
- 800473e:	370c      	adds	r7, #12
- 8004740:	46bd      	mov	sp, r7
- 8004742:	bc80      	pop	{r7}
- 8004744:	4770      	bx	lr
+ 8005b64:	4618      	mov	r0, r3
+ 8005b66:	370c      	adds	r7, #12
+ 8005b68:	46bd      	mov	sp, r7
+ 8005b6a:	bc80      	pop	{r7}
+ 8005b6c:	4770      	bx	lr
 	...
 
-08004748 <HAL_RCC_OscConfig>:
+08005b70 <HAL_RCC_OscConfig>:
   *         supported by this macro. User should request a transition to HSE Off
   *         first and then HSE On or HSE Bypass.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
- 8004748:	b580      	push	{r7, lr}
- 800474a:	b086      	sub	sp, #24
- 800474c:	af00      	add	r7, sp, #0
- 800474e:	6078      	str	r0, [r7, #4]
+ 8005b70:	b580      	push	{r7, lr}
+ 8005b72:	b086      	sub	sp, #24
+ 8005b74:	af00      	add	r7, sp, #0
+ 8005b76:	6078      	str	r0, [r7, #4]
   uint32_t tickstart;
   uint32_t pll_config;
 
   /* Check Null pointer */
   if (RCC_OscInitStruct == NULL)
- 8004750:	687b      	ldr	r3, [r7, #4]
- 8004752:	2b00      	cmp	r3, #0
- 8004754:	d101      	bne.n	800475a <HAL_RCC_OscConfig+0x12>
+ 8005b78:	687b      	ldr	r3, [r7, #4]
+ 8005b7a:	2b00      	cmp	r3, #0
+ 8005b7c:	d101      	bne.n	8005b82 <HAL_RCC_OscConfig+0x12>
   {
     return HAL_ERROR;
- 8004756:	2301      	movs	r3, #1
- 8004758:	e272      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005b7e:	2301      	movs	r3, #1
+ 8005b80:	e272      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
 
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 
   /*------------------------------- HSE Configuration ------------------------*/
   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 800475a:	687b      	ldr	r3, [r7, #4]
- 800475c:	681b      	ldr	r3, [r3, #0]
- 800475e:	f003 0301 	and.w	r3, r3, #1
- 8004762:	2b00      	cmp	r3, #0
- 8004764:	f000 8087 	beq.w	8004876 <HAL_RCC_OscConfig+0x12e>
+ 8005b82:	687b      	ldr	r3, [r7, #4]
+ 8005b84:	681b      	ldr	r3, [r3, #0]
+ 8005b86:	f003 0301 	and.w	r3, r3, #1
+ 8005b8a:	2b00      	cmp	r3, #0
+ 8005b8c:	f000 8087 	beq.w	8005c9e <HAL_RCC_OscConfig+0x12e>
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 
     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
     if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8004768:	4b92      	ldr	r3, [pc, #584]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 800476a:	685b      	ldr	r3, [r3, #4]
- 800476c:	f003 030c 	and.w	r3, r3, #12
- 8004770:	2b04      	cmp	r3, #4
- 8004772:	d00c      	beq.n	800478e <HAL_RCC_OscConfig+0x46>
+ 8005b90:	4b92      	ldr	r3, [pc, #584]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005b92:	685b      	ldr	r3, [r3, #4]
+ 8005b94:	f003 030c 	and.w	r3, r3, #12
+ 8005b98:	2b04      	cmp	r3, #4
+ 8005b9a:	d00c      	beq.n	8005bb6 <HAL_RCC_OscConfig+0x46>
         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- 8004774:	4b8f      	ldr	r3, [pc, #572]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004776:	685b      	ldr	r3, [r3, #4]
- 8004778:	f003 030c 	and.w	r3, r3, #12
- 800477c:	2b08      	cmp	r3, #8
- 800477e:	d112      	bne.n	80047a6 <HAL_RCC_OscConfig+0x5e>
- 8004780:	4b8c      	ldr	r3, [pc, #560]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004782:	685b      	ldr	r3, [r3, #4]
- 8004784:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 8004788:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
- 800478c:	d10b      	bne.n	80047a6 <HAL_RCC_OscConfig+0x5e>
+ 8005b9c:	4b8f      	ldr	r3, [pc, #572]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005b9e:	685b      	ldr	r3, [r3, #4]
+ 8005ba0:	f003 030c 	and.w	r3, r3, #12
+ 8005ba4:	2b08      	cmp	r3, #8
+ 8005ba6:	d112      	bne.n	8005bce <HAL_RCC_OscConfig+0x5e>
+ 8005ba8:	4b8c      	ldr	r3, [pc, #560]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005baa:	685b      	ldr	r3, [r3, #4]
+ 8005bac:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8005bb0:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8005bb4:	d10b      	bne.n	8005bce <HAL_RCC_OscConfig+0x5e>
     {
       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800478e:	4b89      	ldr	r3, [pc, #548]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004790:	681b      	ldr	r3, [r3, #0]
- 8004792:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8004796:	2b00      	cmp	r3, #0
- 8004798:	d06c      	beq.n	8004874 <HAL_RCC_OscConfig+0x12c>
- 800479a:	687b      	ldr	r3, [r7, #4]
- 800479c:	685b      	ldr	r3, [r3, #4]
- 800479e:	2b00      	cmp	r3, #0
- 80047a0:	d168      	bne.n	8004874 <HAL_RCC_OscConfig+0x12c>
+ 8005bb6:	4b89      	ldr	r3, [pc, #548]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bb8:	681b      	ldr	r3, [r3, #0]
+ 8005bba:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8005bbe:	2b00      	cmp	r3, #0
+ 8005bc0:	d06c      	beq.n	8005c9c <HAL_RCC_OscConfig+0x12c>
+ 8005bc2:	687b      	ldr	r3, [r7, #4]
+ 8005bc4:	685b      	ldr	r3, [r3, #4]
+ 8005bc6:	2b00      	cmp	r3, #0
+ 8005bc8:	d168      	bne.n	8005c9c <HAL_RCC_OscConfig+0x12c>
       {
         return HAL_ERROR;
- 80047a2:	2301      	movs	r3, #1
- 80047a4:	e24c      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005bca:	2301      	movs	r3, #1
+ 8005bcc:	e24c      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       }
     }
     else
     {
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 80047a6:	687b      	ldr	r3, [r7, #4]
- 80047a8:	685b      	ldr	r3, [r3, #4]
- 80047aa:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
- 80047ae:	d106      	bne.n	80047be <HAL_RCC_OscConfig+0x76>
- 80047b0:	4b80      	ldr	r3, [pc, #512]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047b2:	681b      	ldr	r3, [r3, #0]
- 80047b4:	4a7f      	ldr	r2, [pc, #508]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047b6:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
- 80047ba:	6013      	str	r3, [r2, #0]
- 80047bc:	e02e      	b.n	800481c <HAL_RCC_OscConfig+0xd4>
- 80047be:	687b      	ldr	r3, [r7, #4]
- 80047c0:	685b      	ldr	r3, [r3, #4]
- 80047c2:	2b00      	cmp	r3, #0
- 80047c4:	d10c      	bne.n	80047e0 <HAL_RCC_OscConfig+0x98>
- 80047c6:	4b7b      	ldr	r3, [pc, #492]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047c8:	681b      	ldr	r3, [r3, #0]
- 80047ca:	4a7a      	ldr	r2, [pc, #488]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047cc:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
- 80047d0:	6013      	str	r3, [r2, #0]
- 80047d2:	4b78      	ldr	r3, [pc, #480]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047d4:	681b      	ldr	r3, [r3, #0]
- 80047d6:	4a77      	ldr	r2, [pc, #476]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047d8:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
- 80047dc:	6013      	str	r3, [r2, #0]
- 80047de:	e01d      	b.n	800481c <HAL_RCC_OscConfig+0xd4>
- 80047e0:	687b      	ldr	r3, [r7, #4]
- 80047e2:	685b      	ldr	r3, [r3, #4]
- 80047e4:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
- 80047e8:	d10c      	bne.n	8004804 <HAL_RCC_OscConfig+0xbc>
- 80047ea:	4b72      	ldr	r3, [pc, #456]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047ec:	681b      	ldr	r3, [r3, #0]
- 80047ee:	4a71      	ldr	r2, [pc, #452]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047f0:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
- 80047f4:	6013      	str	r3, [r2, #0]
- 80047f6:	4b6f      	ldr	r3, [pc, #444]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047f8:	681b      	ldr	r3, [r3, #0]
- 80047fa:	4a6e      	ldr	r2, [pc, #440]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80047fc:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
- 8004800:	6013      	str	r3, [r2, #0]
- 8004802:	e00b      	b.n	800481c <HAL_RCC_OscConfig+0xd4>
- 8004804:	4b6b      	ldr	r3, [pc, #428]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004806:	681b      	ldr	r3, [r3, #0]
- 8004808:	4a6a      	ldr	r2, [pc, #424]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 800480a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
- 800480e:	6013      	str	r3, [r2, #0]
- 8004810:	4b68      	ldr	r3, [pc, #416]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004812:	681b      	ldr	r3, [r3, #0]
- 8004814:	4a67      	ldr	r2, [pc, #412]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004816:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
- 800481a:	6013      	str	r3, [r2, #0]
+ 8005bce:	687b      	ldr	r3, [r7, #4]
+ 8005bd0:	685b      	ldr	r3, [r3, #4]
+ 8005bd2:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8005bd6:	d106      	bne.n	8005be6 <HAL_RCC_OscConfig+0x76>
+ 8005bd8:	4b80      	ldr	r3, [pc, #512]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bda:	681b      	ldr	r3, [r3, #0]
+ 8005bdc:	4a7f      	ldr	r2, [pc, #508]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bde:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8005be2:	6013      	str	r3, [r2, #0]
+ 8005be4:	e02e      	b.n	8005c44 <HAL_RCC_OscConfig+0xd4>
+ 8005be6:	687b      	ldr	r3, [r7, #4]
+ 8005be8:	685b      	ldr	r3, [r3, #4]
+ 8005bea:	2b00      	cmp	r3, #0
+ 8005bec:	d10c      	bne.n	8005c08 <HAL_RCC_OscConfig+0x98>
+ 8005bee:	4b7b      	ldr	r3, [pc, #492]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bf0:	681b      	ldr	r3, [r3, #0]
+ 8005bf2:	4a7a      	ldr	r2, [pc, #488]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bf4:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 8005bf8:	6013      	str	r3, [r2, #0]
+ 8005bfa:	4b78      	ldr	r3, [pc, #480]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005bfc:	681b      	ldr	r3, [r3, #0]
+ 8005bfe:	4a77      	ldr	r2, [pc, #476]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c00:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 8005c04:	6013      	str	r3, [r2, #0]
+ 8005c06:	e01d      	b.n	8005c44 <HAL_RCC_OscConfig+0xd4>
+ 8005c08:	687b      	ldr	r3, [r7, #4]
+ 8005c0a:	685b      	ldr	r3, [r3, #4]
+ 8005c0c:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 8005c10:	d10c      	bne.n	8005c2c <HAL_RCC_OscConfig+0xbc>
+ 8005c12:	4b72      	ldr	r3, [pc, #456]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c14:	681b      	ldr	r3, [r3, #0]
+ 8005c16:	4a71      	ldr	r2, [pc, #452]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c18:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
+ 8005c1c:	6013      	str	r3, [r2, #0]
+ 8005c1e:	4b6f      	ldr	r3, [pc, #444]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c20:	681b      	ldr	r3, [r3, #0]
+ 8005c22:	4a6e      	ldr	r2, [pc, #440]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c24:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8005c28:	6013      	str	r3, [r2, #0]
+ 8005c2a:	e00b      	b.n	8005c44 <HAL_RCC_OscConfig+0xd4>
+ 8005c2c:	4b6b      	ldr	r3, [pc, #428]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c2e:	681b      	ldr	r3, [r3, #0]
+ 8005c30:	4a6a      	ldr	r2, [pc, #424]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c32:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 8005c36:	6013      	str	r3, [r2, #0]
+ 8005c38:	4b68      	ldr	r3, [pc, #416]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c3a:	681b      	ldr	r3, [r3, #0]
+ 8005c3c:	4a67      	ldr	r2, [pc, #412]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c3e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 8005c42:	6013      	str	r3, [r2, #0]
 
 
       /* Check the HSE State */
       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 800481c:	687b      	ldr	r3, [r7, #4]
- 800481e:	685b      	ldr	r3, [r3, #4]
- 8004820:	2b00      	cmp	r3, #0
- 8004822:	d013      	beq.n	800484c <HAL_RCC_OscConfig+0x104>
+ 8005c44:	687b      	ldr	r3, [r7, #4]
+ 8005c46:	685b      	ldr	r3, [r3, #4]
+ 8005c48:	2b00      	cmp	r3, #0
+ 8005c4a:	d013      	beq.n	8005c74 <HAL_RCC_OscConfig+0x104>
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8004824:	f7fe f990 	bl	8002b48 <HAL_GetTick>
- 8004828:	6138      	str	r0, [r7, #16]
+ 8005c4c:	f7fd fb42 	bl	80032d4 <HAL_GetTick>
+ 8005c50:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is ready */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800482a:	e008      	b.n	800483e <HAL_RCC_OscConfig+0xf6>
+ 8005c52:	e008      	b.n	8005c66 <HAL_RCC_OscConfig+0xf6>
         {
           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- 800482c:	f7fe f98c 	bl	8002b48 <HAL_GetTick>
- 8004830:	4602      	mov	r2, r0
- 8004832:	693b      	ldr	r3, [r7, #16]
- 8004834:	1ad3      	subs	r3, r2, r3
- 8004836:	2b64      	cmp	r3, #100	@ 0x64
- 8004838:	d901      	bls.n	800483e <HAL_RCC_OscConfig+0xf6>
+ 8005c54:	f7fd fb3e 	bl	80032d4 <HAL_GetTick>
+ 8005c58:	4602      	mov	r2, r0
+ 8005c5a:	693b      	ldr	r3, [r7, #16]
+ 8005c5c:	1ad3      	subs	r3, r2, r3
+ 8005c5e:	2b64      	cmp	r3, #100	@ 0x64
+ 8005c60:	d901      	bls.n	8005c66 <HAL_RCC_OscConfig+0xf6>
           {
             return HAL_TIMEOUT;
- 800483a:	2303      	movs	r3, #3
- 800483c:	e200      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005c62:	2303      	movs	r3, #3
+ 8005c64:	e200      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800483e:	4b5d      	ldr	r3, [pc, #372]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004840:	681b      	ldr	r3, [r3, #0]
- 8004842:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8004846:	2b00      	cmp	r3, #0
- 8004848:	d0f0      	beq.n	800482c <HAL_RCC_OscConfig+0xe4>
- 800484a:	e014      	b.n	8004876 <HAL_RCC_OscConfig+0x12e>
+ 8005c66:	4b5d      	ldr	r3, [pc, #372]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c68:	681b      	ldr	r3, [r3, #0]
+ 8005c6a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8005c6e:	2b00      	cmp	r3, #0
+ 8005c70:	d0f0      	beq.n	8005c54 <HAL_RCC_OscConfig+0xe4>
+ 8005c72:	e014      	b.n	8005c9e <HAL_RCC_OscConfig+0x12e>
         }
       }
       else
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 800484c:	f7fe f97c 	bl	8002b48 <HAL_GetTick>
- 8004850:	6138      	str	r0, [r7, #16]
+ 8005c74:	f7fd fb2e 	bl	80032d4 <HAL_GetTick>
+ 8005c78:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is disabled */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8004852:	e008      	b.n	8004866 <HAL_RCC_OscConfig+0x11e>
+ 8005c7a:	e008      	b.n	8005c8e <HAL_RCC_OscConfig+0x11e>
         {
           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- 8004854:	f7fe f978 	bl	8002b48 <HAL_GetTick>
- 8004858:	4602      	mov	r2, r0
- 800485a:	693b      	ldr	r3, [r7, #16]
- 800485c:	1ad3      	subs	r3, r2, r3
- 800485e:	2b64      	cmp	r3, #100	@ 0x64
- 8004860:	d901      	bls.n	8004866 <HAL_RCC_OscConfig+0x11e>
+ 8005c7c:	f7fd fb2a 	bl	80032d4 <HAL_GetTick>
+ 8005c80:	4602      	mov	r2, r0
+ 8005c82:	693b      	ldr	r3, [r7, #16]
+ 8005c84:	1ad3      	subs	r3, r2, r3
+ 8005c86:	2b64      	cmp	r3, #100	@ 0x64
+ 8005c88:	d901      	bls.n	8005c8e <HAL_RCC_OscConfig+0x11e>
           {
             return HAL_TIMEOUT;
- 8004862:	2303      	movs	r3, #3
- 8004864:	e1ec      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005c8a:	2303      	movs	r3, #3
+ 8005c8c:	e1ec      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8004866:	4b53      	ldr	r3, [pc, #332]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004868:	681b      	ldr	r3, [r3, #0]
- 800486a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 800486e:	2b00      	cmp	r3, #0
- 8004870:	d1f0      	bne.n	8004854 <HAL_RCC_OscConfig+0x10c>
- 8004872:	e000      	b.n	8004876 <HAL_RCC_OscConfig+0x12e>
+ 8005c8e:	4b53      	ldr	r3, [pc, #332]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005c90:	681b      	ldr	r3, [r3, #0]
+ 8005c92:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8005c96:	2b00      	cmp	r3, #0
+ 8005c98:	d1f0      	bne.n	8005c7c <HAL_RCC_OscConfig+0x10c>
+ 8005c9a:	e000      	b.n	8005c9e <HAL_RCC_OscConfig+0x12e>
       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8004874:	bf00      	nop
+ 8005c9c:	bf00      	nop
         }
       }
     }
   }
   /*----------------------------- HSI Configuration --------------------------*/
   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8004876:	687b      	ldr	r3, [r7, #4]
- 8004878:	681b      	ldr	r3, [r3, #0]
- 800487a:	f003 0302 	and.w	r3, r3, #2
- 800487e:	2b00      	cmp	r3, #0
- 8004880:	d063      	beq.n	800494a <HAL_RCC_OscConfig+0x202>
+ 8005c9e:	687b      	ldr	r3, [r7, #4]
+ 8005ca0:	681b      	ldr	r3, [r3, #0]
+ 8005ca2:	f003 0302 	and.w	r3, r3, #2
+ 8005ca6:	2b00      	cmp	r3, #0
+ 8005ca8:	d063      	beq.n	8005d72 <HAL_RCC_OscConfig+0x202>
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
     if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 8004882:	4b4c      	ldr	r3, [pc, #304]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004884:	685b      	ldr	r3, [r3, #4]
- 8004886:	f003 030c 	and.w	r3, r3, #12
- 800488a:	2b00      	cmp	r3, #0
- 800488c:	d00b      	beq.n	80048a6 <HAL_RCC_OscConfig+0x15e>
+ 8005caa:	4b4c      	ldr	r3, [pc, #304]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005cac:	685b      	ldr	r3, [r3, #4]
+ 8005cae:	f003 030c 	and.w	r3, r3, #12
+ 8005cb2:	2b00      	cmp	r3, #0
+ 8005cb4:	d00b      	beq.n	8005cce <HAL_RCC_OscConfig+0x15e>
         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
- 800488e:	4b49      	ldr	r3, [pc, #292]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004890:	685b      	ldr	r3, [r3, #4]
- 8004892:	f003 030c 	and.w	r3, r3, #12
- 8004896:	2b08      	cmp	r3, #8
- 8004898:	d11c      	bne.n	80048d4 <HAL_RCC_OscConfig+0x18c>
- 800489a:	4b46      	ldr	r3, [pc, #280]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 800489c:	685b      	ldr	r3, [r3, #4]
- 800489e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 80048a2:	2b00      	cmp	r3, #0
- 80048a4:	d116      	bne.n	80048d4 <HAL_RCC_OscConfig+0x18c>
+ 8005cb6:	4b49      	ldr	r3, [pc, #292]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005cb8:	685b      	ldr	r3, [r3, #4]
+ 8005cba:	f003 030c 	and.w	r3, r3, #12
+ 8005cbe:	2b08      	cmp	r3, #8
+ 8005cc0:	d11c      	bne.n	8005cfc <HAL_RCC_OscConfig+0x18c>
+ 8005cc2:	4b46      	ldr	r3, [pc, #280]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005cc4:	685b      	ldr	r3, [r3, #4]
+ 8005cc6:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8005cca:	2b00      	cmp	r3, #0
+ 8005ccc:	d116      	bne.n	8005cfc <HAL_RCC_OscConfig+0x18c>
     {
       /* When HSI is used as system clock it will not disabled */
       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80048a6:	4b43      	ldr	r3, [pc, #268]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80048a8:	681b      	ldr	r3, [r3, #0]
- 80048aa:	f003 0302 	and.w	r3, r3, #2
- 80048ae:	2b00      	cmp	r3, #0
- 80048b0:	d005      	beq.n	80048be <HAL_RCC_OscConfig+0x176>
- 80048b2:	687b      	ldr	r3, [r7, #4]
- 80048b4:	691b      	ldr	r3, [r3, #16]
- 80048b6:	2b01      	cmp	r3, #1
- 80048b8:	d001      	beq.n	80048be <HAL_RCC_OscConfig+0x176>
+ 8005cce:	4b43      	ldr	r3, [pc, #268]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005cd0:	681b      	ldr	r3, [r3, #0]
+ 8005cd2:	f003 0302 	and.w	r3, r3, #2
+ 8005cd6:	2b00      	cmp	r3, #0
+ 8005cd8:	d005      	beq.n	8005ce6 <HAL_RCC_OscConfig+0x176>
+ 8005cda:	687b      	ldr	r3, [r7, #4]
+ 8005cdc:	691b      	ldr	r3, [r3, #16]
+ 8005cde:	2b01      	cmp	r3, #1
+ 8005ce0:	d001      	beq.n	8005ce6 <HAL_RCC_OscConfig+0x176>
       {
         return HAL_ERROR;
- 80048ba:	2301      	movs	r3, #1
- 80048bc:	e1c0      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005ce2:	2301      	movs	r3, #1
+ 8005ce4:	e1c0      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       }
       /* Otherwise, just the calibration is allowed */
       else
       {
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80048be:	4b3d      	ldr	r3, [pc, #244]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80048c0:	681b      	ldr	r3, [r3, #0]
- 80048c2:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
- 80048c6:	687b      	ldr	r3, [r7, #4]
- 80048c8:	695b      	ldr	r3, [r3, #20]
- 80048ca:	00db      	lsls	r3, r3, #3
- 80048cc:	4939      	ldr	r1, [pc, #228]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80048ce:	4313      	orrs	r3, r2
- 80048d0:	600b      	str	r3, [r1, #0]
+ 8005ce6:	4b3d      	ldr	r3, [pc, #244]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005ce8:	681b      	ldr	r3, [r3, #0]
+ 8005cea:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
+ 8005cee:	687b      	ldr	r3, [r7, #4]
+ 8005cf0:	695b      	ldr	r3, [r3, #20]
+ 8005cf2:	00db      	lsls	r3, r3, #3
+ 8005cf4:	4939      	ldr	r1, [pc, #228]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005cf6:	4313      	orrs	r3, r2
+ 8005cf8:	600b      	str	r3, [r1, #0]
       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80048d2:	e03a      	b.n	800494a <HAL_RCC_OscConfig+0x202>
+ 8005cfa:	e03a      	b.n	8005d72 <HAL_RCC_OscConfig+0x202>
       }
     }
     else
     {
       /* Check the HSI State */
       if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- 80048d4:	687b      	ldr	r3, [r7, #4]
- 80048d6:	691b      	ldr	r3, [r3, #16]
- 80048d8:	2b00      	cmp	r3, #0
- 80048da:	d020      	beq.n	800491e <HAL_RCC_OscConfig+0x1d6>
+ 8005cfc:	687b      	ldr	r3, [r7, #4]
+ 8005cfe:	691b      	ldr	r3, [r3, #16]
+ 8005d00:	2b00      	cmp	r3, #0
+ 8005d02:	d020      	beq.n	8005d46 <HAL_RCC_OscConfig+0x1d6>
       {
         /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
- 80048dc:	4b36      	ldr	r3, [pc, #216]	@ (80049b8 <HAL_RCC_OscConfig+0x270>)
- 80048de:	2201      	movs	r2, #1
- 80048e0:	601a      	str	r2, [r3, #0]
+ 8005d04:	4b36      	ldr	r3, [pc, #216]	@ (8005de0 <HAL_RCC_OscConfig+0x270>)
+ 8005d06:	2201      	movs	r2, #1
+ 8005d08:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80048e2:	f7fe f931 	bl	8002b48 <HAL_GetTick>
- 80048e6:	6138      	str	r0, [r7, #16]
+ 8005d0a:	f7fd fae3 	bl	80032d4 <HAL_GetTick>
+ 8005d0e:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is ready */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80048e8:	e008      	b.n	80048fc <HAL_RCC_OscConfig+0x1b4>
+ 8005d10:	e008      	b.n	8005d24 <HAL_RCC_OscConfig+0x1b4>
         {
           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- 80048ea:	f7fe f92d 	bl	8002b48 <HAL_GetTick>
- 80048ee:	4602      	mov	r2, r0
- 80048f0:	693b      	ldr	r3, [r7, #16]
- 80048f2:	1ad3      	subs	r3, r2, r3
- 80048f4:	2b02      	cmp	r3, #2
- 80048f6:	d901      	bls.n	80048fc <HAL_RCC_OscConfig+0x1b4>
+ 8005d12:	f7fd fadf 	bl	80032d4 <HAL_GetTick>
+ 8005d16:	4602      	mov	r2, r0
+ 8005d18:	693b      	ldr	r3, [r7, #16]
+ 8005d1a:	1ad3      	subs	r3, r2, r3
+ 8005d1c:	2b02      	cmp	r3, #2
+ 8005d1e:	d901      	bls.n	8005d24 <HAL_RCC_OscConfig+0x1b4>
           {
             return HAL_TIMEOUT;
- 80048f8:	2303      	movs	r3, #3
- 80048fa:	e1a1      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005d20:	2303      	movs	r3, #3
+ 8005d22:	e1a1      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80048fc:	4b2d      	ldr	r3, [pc, #180]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 80048fe:	681b      	ldr	r3, [r3, #0]
- 8004900:	f003 0302 	and.w	r3, r3, #2
- 8004904:	2b00      	cmp	r3, #0
- 8004906:	d0f0      	beq.n	80048ea <HAL_RCC_OscConfig+0x1a2>
+ 8005d24:	4b2d      	ldr	r3, [pc, #180]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005d26:	681b      	ldr	r3, [r3, #0]
+ 8005d28:	f003 0302 	and.w	r3, r3, #2
+ 8005d2c:	2b00      	cmp	r3, #0
+ 8005d2e:	d0f0      	beq.n	8005d12 <HAL_RCC_OscConfig+0x1a2>
           }
         }
 
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8004908:	4b2a      	ldr	r3, [pc, #168]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 800490a:	681b      	ldr	r3, [r3, #0]
- 800490c:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
- 8004910:	687b      	ldr	r3, [r7, #4]
- 8004912:	695b      	ldr	r3, [r3, #20]
- 8004914:	00db      	lsls	r3, r3, #3
- 8004916:	4927      	ldr	r1, [pc, #156]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004918:	4313      	orrs	r3, r2
- 800491a:	600b      	str	r3, [r1, #0]
- 800491c:	e015      	b.n	800494a <HAL_RCC_OscConfig+0x202>
+ 8005d30:	4b2a      	ldr	r3, [pc, #168]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005d32:	681b      	ldr	r3, [r3, #0]
+ 8005d34:	f023 02f8 	bic.w	r2, r3, #248	@ 0xf8
+ 8005d38:	687b      	ldr	r3, [r7, #4]
+ 8005d3a:	695b      	ldr	r3, [r3, #20]
+ 8005d3c:	00db      	lsls	r3, r3, #3
+ 8005d3e:	4927      	ldr	r1, [pc, #156]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005d40:	4313      	orrs	r3, r2
+ 8005d42:	600b      	str	r3, [r1, #0]
+ 8005d44:	e015      	b.n	8005d72 <HAL_RCC_OscConfig+0x202>
       }
       else
       {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
- 800491e:	4b26      	ldr	r3, [pc, #152]	@ (80049b8 <HAL_RCC_OscConfig+0x270>)
- 8004920:	2200      	movs	r2, #0
- 8004922:	601a      	str	r2, [r3, #0]
+ 8005d46:	4b26      	ldr	r3, [pc, #152]	@ (8005de0 <HAL_RCC_OscConfig+0x270>)
+ 8005d48:	2200      	movs	r2, #0
+ 8005d4a:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8004924:	f7fe f910 	bl	8002b48 <HAL_GetTick>
- 8004928:	6138      	str	r0, [r7, #16]
+ 8005d4c:	f7fd fac2 	bl	80032d4 <HAL_GetTick>
+ 8005d50:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is disabled */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800492a:	e008      	b.n	800493e <HAL_RCC_OscConfig+0x1f6>
+ 8005d52:	e008      	b.n	8005d66 <HAL_RCC_OscConfig+0x1f6>
         {
           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- 800492c:	f7fe f90c 	bl	8002b48 <HAL_GetTick>
- 8004930:	4602      	mov	r2, r0
- 8004932:	693b      	ldr	r3, [r7, #16]
- 8004934:	1ad3      	subs	r3, r2, r3
- 8004936:	2b02      	cmp	r3, #2
- 8004938:	d901      	bls.n	800493e <HAL_RCC_OscConfig+0x1f6>
+ 8005d54:	f7fd fabe 	bl	80032d4 <HAL_GetTick>
+ 8005d58:	4602      	mov	r2, r0
+ 8005d5a:	693b      	ldr	r3, [r7, #16]
+ 8005d5c:	1ad3      	subs	r3, r2, r3
+ 8005d5e:	2b02      	cmp	r3, #2
+ 8005d60:	d901      	bls.n	8005d66 <HAL_RCC_OscConfig+0x1f6>
           {
             return HAL_TIMEOUT;
- 800493a:	2303      	movs	r3, #3
- 800493c:	e180      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005d62:	2303      	movs	r3, #3
+ 8005d64:	e180      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800493e:	4b1d      	ldr	r3, [pc, #116]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004940:	681b      	ldr	r3, [r3, #0]
- 8004942:	f003 0302 	and.w	r3, r3, #2
- 8004946:	2b00      	cmp	r3, #0
- 8004948:	d1f0      	bne.n	800492c <HAL_RCC_OscConfig+0x1e4>
+ 8005d66:	4b1d      	ldr	r3, [pc, #116]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005d68:	681b      	ldr	r3, [r3, #0]
+ 8005d6a:	f003 0302 	and.w	r3, r3, #2
+ 8005d6e:	2b00      	cmp	r3, #0
+ 8005d70:	d1f0      	bne.n	8005d54 <HAL_RCC_OscConfig+0x1e4>
         }
       }
     }
   }
   /*------------------------------ LSI Configuration -------------------------*/
   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 800494a:	687b      	ldr	r3, [r7, #4]
- 800494c:	681b      	ldr	r3, [r3, #0]
- 800494e:	f003 0308 	and.w	r3, r3, #8
- 8004952:	2b00      	cmp	r3, #0
- 8004954:	d03a      	beq.n	80049cc <HAL_RCC_OscConfig+0x284>
+ 8005d72:	687b      	ldr	r3, [r7, #4]
+ 8005d74:	681b      	ldr	r3, [r3, #0]
+ 8005d76:	f003 0308 	and.w	r3, r3, #8
+ 8005d7a:	2b00      	cmp	r3, #0
+ 8005d7c:	d03a      	beq.n	8005df4 <HAL_RCC_OscConfig+0x284>
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 
     /* Check the LSI State */
     if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- 8004956:	687b      	ldr	r3, [r7, #4]
- 8004958:	699b      	ldr	r3, [r3, #24]
- 800495a:	2b00      	cmp	r3, #0
- 800495c:	d019      	beq.n	8004992 <HAL_RCC_OscConfig+0x24a>
+ 8005d7e:	687b      	ldr	r3, [r7, #4]
+ 8005d80:	699b      	ldr	r3, [r3, #24]
+ 8005d82:	2b00      	cmp	r3, #0
+ 8005d84:	d019      	beq.n	8005dba <HAL_RCC_OscConfig+0x24a>
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
- 800495e:	4b17      	ldr	r3, [pc, #92]	@ (80049bc <HAL_RCC_OscConfig+0x274>)
- 8004960:	2201      	movs	r2, #1
- 8004962:	601a      	str	r2, [r3, #0]
+ 8005d86:	4b17      	ldr	r3, [pc, #92]	@ (8005de4 <HAL_RCC_OscConfig+0x274>)
+ 8005d88:	2201      	movs	r2, #1
+ 8005d8a:	601a      	str	r2, [r3, #0]
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8004964:	f7fe f8f0 	bl	8002b48 <HAL_GetTick>
- 8004968:	6138      	str	r0, [r7, #16]
+ 8005d8c:	f7fd faa2 	bl	80032d4 <HAL_GetTick>
+ 8005d90:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is ready */
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800496a:	e008      	b.n	800497e <HAL_RCC_OscConfig+0x236>
+ 8005d92:	e008      	b.n	8005da6 <HAL_RCC_OscConfig+0x236>
       {
         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- 800496c:	f7fe f8ec 	bl	8002b48 <HAL_GetTick>
- 8004970:	4602      	mov	r2, r0
- 8004972:	693b      	ldr	r3, [r7, #16]
- 8004974:	1ad3      	subs	r3, r2, r3
- 8004976:	2b02      	cmp	r3, #2
- 8004978:	d901      	bls.n	800497e <HAL_RCC_OscConfig+0x236>
+ 8005d94:	f7fd fa9e 	bl	80032d4 <HAL_GetTick>
+ 8005d98:	4602      	mov	r2, r0
+ 8005d9a:	693b      	ldr	r3, [r7, #16]
+ 8005d9c:	1ad3      	subs	r3, r2, r3
+ 8005d9e:	2b02      	cmp	r3, #2
+ 8005da0:	d901      	bls.n	8005da6 <HAL_RCC_OscConfig+0x236>
         {
           return HAL_TIMEOUT;
- 800497a:	2303      	movs	r3, #3
- 800497c:	e160      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005da2:	2303      	movs	r3, #3
+ 8005da4:	e160      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800497e:	4b0d      	ldr	r3, [pc, #52]	@ (80049b4 <HAL_RCC_OscConfig+0x26c>)
- 8004980:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8004982:	f003 0302 	and.w	r3, r3, #2
- 8004986:	2b00      	cmp	r3, #0
- 8004988:	d0f0      	beq.n	800496c <HAL_RCC_OscConfig+0x224>
+ 8005da6:	4b0d      	ldr	r3, [pc, #52]	@ (8005ddc <HAL_RCC_OscConfig+0x26c>)
+ 8005da8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005daa:	f003 0302 	and.w	r3, r3, #2
+ 8005dae:	2b00      	cmp	r3, #0
+ 8005db0:	d0f0      	beq.n	8005d94 <HAL_RCC_OscConfig+0x224>
         }
       }
       /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
           should be added.*/
       RCC_Delay(1);
- 800498a:	2001      	movs	r0, #1
- 800498c:	f000 fad0 	bl	8004f30 <RCC_Delay>
- 8004990:	e01c      	b.n	80049cc <HAL_RCC_OscConfig+0x284>
+ 8005db2:	2001      	movs	r0, #1
+ 8005db4:	f000 fad0 	bl	8006358 <RCC_Delay>
+ 8005db8:	e01c      	b.n	8005df4 <HAL_RCC_OscConfig+0x284>
     }
     else
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
- 8004992:	4b0a      	ldr	r3, [pc, #40]	@ (80049bc <HAL_RCC_OscConfig+0x274>)
- 8004994:	2200      	movs	r2, #0
- 8004996:	601a      	str	r2, [r3, #0]
+ 8005dba:	4b0a      	ldr	r3, [pc, #40]	@ (8005de4 <HAL_RCC_OscConfig+0x274>)
+ 8005dbc:	2200      	movs	r2, #0
+ 8005dbe:	601a      	str	r2, [r3, #0]
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8004998:	f7fe f8d6 	bl	8002b48 <HAL_GetTick>
- 800499c:	6138      	str	r0, [r7, #16]
+ 8005dc0:	f7fd fa88 	bl	80032d4 <HAL_GetTick>
+ 8005dc4:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is disabled */
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 800499e:	e00f      	b.n	80049c0 <HAL_RCC_OscConfig+0x278>
+ 8005dc6:	e00f      	b.n	8005de8 <HAL_RCC_OscConfig+0x278>
       {
         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- 80049a0:	f7fe f8d2 	bl	8002b48 <HAL_GetTick>
- 80049a4:	4602      	mov	r2, r0
- 80049a6:	693b      	ldr	r3, [r7, #16]
- 80049a8:	1ad3      	subs	r3, r2, r3
- 80049aa:	2b02      	cmp	r3, #2
- 80049ac:	d908      	bls.n	80049c0 <HAL_RCC_OscConfig+0x278>
+ 8005dc8:	f7fd fa84 	bl	80032d4 <HAL_GetTick>
+ 8005dcc:	4602      	mov	r2, r0
+ 8005dce:	693b      	ldr	r3, [r7, #16]
+ 8005dd0:	1ad3      	subs	r3, r2, r3
+ 8005dd2:	2b02      	cmp	r3, #2
+ 8005dd4:	d908      	bls.n	8005de8 <HAL_RCC_OscConfig+0x278>
         {
           return HAL_TIMEOUT;
- 80049ae:	2303      	movs	r3, #3
- 80049b0:	e146      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
- 80049b2:	bf00      	nop
- 80049b4:	40021000 	.word	0x40021000
- 80049b8:	42420000 	.word	0x42420000
- 80049bc:	42420480 	.word	0x42420480
+ 8005dd6:	2303      	movs	r3, #3
+ 8005dd8:	e146      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
+ 8005dda:	bf00      	nop
+ 8005ddc:	40021000 	.word	0x40021000
+ 8005de0:	42420000 	.word	0x42420000
+ 8005de4:	42420480 	.word	0x42420480
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80049c0:	4b92      	ldr	r3, [pc, #584]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 80049c2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80049c4:	f003 0302 	and.w	r3, r3, #2
- 80049c8:	2b00      	cmp	r3, #0
- 80049ca:	d1e9      	bne.n	80049a0 <HAL_RCC_OscConfig+0x258>
+ 8005de8:	4b92      	ldr	r3, [pc, #584]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005dea:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005dec:	f003 0302 	and.w	r3, r3, #2
+ 8005df0:	2b00      	cmp	r3, #0
+ 8005df2:	d1e9      	bne.n	8005dc8 <HAL_RCC_OscConfig+0x258>
         }
       }
     }
   }
   /*------------------------------ LSE Configuration -------------------------*/
   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 80049cc:	687b      	ldr	r3, [r7, #4]
- 80049ce:	681b      	ldr	r3, [r3, #0]
- 80049d0:	f003 0304 	and.w	r3, r3, #4
- 80049d4:	2b00      	cmp	r3, #0
- 80049d6:	f000 80a6 	beq.w	8004b26 <HAL_RCC_OscConfig+0x3de>
+ 8005df4:	687b      	ldr	r3, [r7, #4]
+ 8005df6:	681b      	ldr	r3, [r3, #0]
+ 8005df8:	f003 0304 	and.w	r3, r3, #4
+ 8005dfc:	2b00      	cmp	r3, #0
+ 8005dfe:	f000 80a6 	beq.w	8005f4e <HAL_RCC_OscConfig+0x3de>
   {
     FlagStatus       pwrclkchanged = RESET;
- 80049da:	2300      	movs	r3, #0
- 80049dc:	75fb      	strb	r3, [r7, #23]
+ 8005e02:	2300      	movs	r3, #0
+ 8005e04:	75fb      	strb	r3, [r7, #23]
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
     /* Update LSE configuration in Backup Domain control register    */
     /* Requires to enable write access to Backup Domain of necessary */
     if (__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80049de:	4b8b      	ldr	r3, [pc, #556]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 80049e0:	69db      	ldr	r3, [r3, #28]
- 80049e2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 80049e6:	2b00      	cmp	r3, #0
- 80049e8:	d10d      	bne.n	8004a06 <HAL_RCC_OscConfig+0x2be>
+ 8005e06:	4b8b      	ldr	r3, [pc, #556]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e08:	69db      	ldr	r3, [r3, #28]
+ 8005e0a:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8005e0e:	2b00      	cmp	r3, #0
+ 8005e10:	d10d      	bne.n	8005e2e <HAL_RCC_OscConfig+0x2be>
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 80049ea:	4b88      	ldr	r3, [pc, #544]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 80049ec:	69db      	ldr	r3, [r3, #28]
- 80049ee:	4a87      	ldr	r2, [pc, #540]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 80049f0:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 80049f4:	61d3      	str	r3, [r2, #28]
- 80049f6:	4b85      	ldr	r3, [pc, #532]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 80049f8:	69db      	ldr	r3, [r3, #28]
- 80049fa:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 80049fe:	60bb      	str	r3, [r7, #8]
- 8004a00:	68bb      	ldr	r3, [r7, #8]
+ 8005e12:	4b88      	ldr	r3, [pc, #544]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e14:	69db      	ldr	r3, [r3, #28]
+ 8005e16:	4a87      	ldr	r2, [pc, #540]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e18:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 8005e1c:	61d3      	str	r3, [r2, #28]
+ 8005e1e:	4b85      	ldr	r3, [pc, #532]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e20:	69db      	ldr	r3, [r3, #28]
+ 8005e22:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8005e26:	60bb      	str	r3, [r7, #8]
+ 8005e28:	68bb      	ldr	r3, [r7, #8]
       pwrclkchanged = SET;
- 8004a02:	2301      	movs	r3, #1
- 8004a04:	75fb      	strb	r3, [r7, #23]
+ 8005e2a:	2301      	movs	r3, #1
+ 8005e2c:	75fb      	strb	r3, [r7, #23]
     }
 
     if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004a06:	4b82      	ldr	r3, [pc, #520]	@ (8004c10 <HAL_RCC_OscConfig+0x4c8>)
- 8004a08:	681b      	ldr	r3, [r3, #0]
- 8004a0a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 8004a0e:	2b00      	cmp	r3, #0
- 8004a10:	d118      	bne.n	8004a44 <HAL_RCC_OscConfig+0x2fc>
+ 8005e2e:	4b82      	ldr	r3, [pc, #520]	@ (8006038 <HAL_RCC_OscConfig+0x4c8>)
+ 8005e30:	681b      	ldr	r3, [r3, #0]
+ 8005e32:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8005e36:	2b00      	cmp	r3, #0
+ 8005e38:	d118      	bne.n	8005e6c <HAL_RCC_OscConfig+0x2fc>
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
- 8004a12:	4b7f      	ldr	r3, [pc, #508]	@ (8004c10 <HAL_RCC_OscConfig+0x4c8>)
- 8004a14:	681b      	ldr	r3, [r3, #0]
- 8004a16:	4a7e      	ldr	r2, [pc, #504]	@ (8004c10 <HAL_RCC_OscConfig+0x4c8>)
- 8004a18:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
- 8004a1c:	6013      	str	r3, [r2, #0]
+ 8005e3a:	4b7f      	ldr	r3, [pc, #508]	@ (8006038 <HAL_RCC_OscConfig+0x4c8>)
+ 8005e3c:	681b      	ldr	r3, [r3, #0]
+ 8005e3e:	4a7e      	ldr	r2, [pc, #504]	@ (8006038 <HAL_RCC_OscConfig+0x4c8>)
+ 8005e40:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 8005e44:	6013      	str	r3, [r2, #0]
 
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
- 8004a1e:	f7fe f893 	bl	8002b48 <HAL_GetTick>
- 8004a22:	6138      	str	r0, [r7, #16]
+ 8005e46:	f7fd fa45 	bl	80032d4 <HAL_GetTick>
+ 8005e4a:	6138      	str	r0, [r7, #16]
 
       while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004a24:	e008      	b.n	8004a38 <HAL_RCC_OscConfig+0x2f0>
+ 8005e4c:	e008      	b.n	8005e60 <HAL_RCC_OscConfig+0x2f0>
       {
         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8004a26:	f7fe f88f 	bl	8002b48 <HAL_GetTick>
- 8004a2a:	4602      	mov	r2, r0
- 8004a2c:	693b      	ldr	r3, [r7, #16]
- 8004a2e:	1ad3      	subs	r3, r2, r3
- 8004a30:	2b64      	cmp	r3, #100	@ 0x64
- 8004a32:	d901      	bls.n	8004a38 <HAL_RCC_OscConfig+0x2f0>
+ 8005e4e:	f7fd fa41 	bl	80032d4 <HAL_GetTick>
+ 8005e52:	4602      	mov	r2, r0
+ 8005e54:	693b      	ldr	r3, [r7, #16]
+ 8005e56:	1ad3      	subs	r3, r2, r3
+ 8005e58:	2b64      	cmp	r3, #100	@ 0x64
+ 8005e5a:	d901      	bls.n	8005e60 <HAL_RCC_OscConfig+0x2f0>
         {
           return HAL_TIMEOUT;
- 8004a34:	2303      	movs	r3, #3
- 8004a36:	e103      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005e5c:	2303      	movs	r3, #3
+ 8005e5e:	e103      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004a38:	4b75      	ldr	r3, [pc, #468]	@ (8004c10 <HAL_RCC_OscConfig+0x4c8>)
- 8004a3a:	681b      	ldr	r3, [r3, #0]
- 8004a3c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 8004a40:	2b00      	cmp	r3, #0
- 8004a42:	d0f0      	beq.n	8004a26 <HAL_RCC_OscConfig+0x2de>
+ 8005e60:	4b75      	ldr	r3, [pc, #468]	@ (8006038 <HAL_RCC_OscConfig+0x4c8>)
+ 8005e62:	681b      	ldr	r3, [r3, #0]
+ 8005e64:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8005e68:	2b00      	cmp	r3, #0
+ 8005e6a:	d0f0      	beq.n	8005e4e <HAL_RCC_OscConfig+0x2de>
         }
       }
     }
 
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8004a44:	687b      	ldr	r3, [r7, #4]
- 8004a46:	68db      	ldr	r3, [r3, #12]
- 8004a48:	2b01      	cmp	r3, #1
- 8004a4a:	d106      	bne.n	8004a5a <HAL_RCC_OscConfig+0x312>
- 8004a4c:	4b6f      	ldr	r3, [pc, #444]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a4e:	6a1b      	ldr	r3, [r3, #32]
- 8004a50:	4a6e      	ldr	r2, [pc, #440]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a52:	f043 0301 	orr.w	r3, r3, #1
- 8004a56:	6213      	str	r3, [r2, #32]
- 8004a58:	e02d      	b.n	8004ab6 <HAL_RCC_OscConfig+0x36e>
- 8004a5a:	687b      	ldr	r3, [r7, #4]
- 8004a5c:	68db      	ldr	r3, [r3, #12]
- 8004a5e:	2b00      	cmp	r3, #0
- 8004a60:	d10c      	bne.n	8004a7c <HAL_RCC_OscConfig+0x334>
- 8004a62:	4b6a      	ldr	r3, [pc, #424]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a64:	6a1b      	ldr	r3, [r3, #32]
- 8004a66:	4a69      	ldr	r2, [pc, #420]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a68:	f023 0301 	bic.w	r3, r3, #1
- 8004a6c:	6213      	str	r3, [r2, #32]
- 8004a6e:	4b67      	ldr	r3, [pc, #412]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a70:	6a1b      	ldr	r3, [r3, #32]
- 8004a72:	4a66      	ldr	r2, [pc, #408]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a74:	f023 0304 	bic.w	r3, r3, #4
- 8004a78:	6213      	str	r3, [r2, #32]
- 8004a7a:	e01c      	b.n	8004ab6 <HAL_RCC_OscConfig+0x36e>
- 8004a7c:	687b      	ldr	r3, [r7, #4]
- 8004a7e:	68db      	ldr	r3, [r3, #12]
- 8004a80:	2b05      	cmp	r3, #5
- 8004a82:	d10c      	bne.n	8004a9e <HAL_RCC_OscConfig+0x356>
- 8004a84:	4b61      	ldr	r3, [pc, #388]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a86:	6a1b      	ldr	r3, [r3, #32]
- 8004a88:	4a60      	ldr	r2, [pc, #384]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a8a:	f043 0304 	orr.w	r3, r3, #4
- 8004a8e:	6213      	str	r3, [r2, #32]
- 8004a90:	4b5e      	ldr	r3, [pc, #376]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a92:	6a1b      	ldr	r3, [r3, #32]
- 8004a94:	4a5d      	ldr	r2, [pc, #372]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004a96:	f043 0301 	orr.w	r3, r3, #1
- 8004a9a:	6213      	str	r3, [r2, #32]
- 8004a9c:	e00b      	b.n	8004ab6 <HAL_RCC_OscConfig+0x36e>
- 8004a9e:	4b5b      	ldr	r3, [pc, #364]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004aa0:	6a1b      	ldr	r3, [r3, #32]
- 8004aa2:	4a5a      	ldr	r2, [pc, #360]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004aa4:	f023 0301 	bic.w	r3, r3, #1
- 8004aa8:	6213      	str	r3, [r2, #32]
- 8004aaa:	4b58      	ldr	r3, [pc, #352]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004aac:	6a1b      	ldr	r3, [r3, #32]
- 8004aae:	4a57      	ldr	r2, [pc, #348]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004ab0:	f023 0304 	bic.w	r3, r3, #4
- 8004ab4:	6213      	str	r3, [r2, #32]
+ 8005e6c:	687b      	ldr	r3, [r7, #4]
+ 8005e6e:	68db      	ldr	r3, [r3, #12]
+ 8005e70:	2b01      	cmp	r3, #1
+ 8005e72:	d106      	bne.n	8005e82 <HAL_RCC_OscConfig+0x312>
+ 8005e74:	4b6f      	ldr	r3, [pc, #444]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e76:	6a1b      	ldr	r3, [r3, #32]
+ 8005e78:	4a6e      	ldr	r2, [pc, #440]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e7a:	f043 0301 	orr.w	r3, r3, #1
+ 8005e7e:	6213      	str	r3, [r2, #32]
+ 8005e80:	e02d      	b.n	8005ede <HAL_RCC_OscConfig+0x36e>
+ 8005e82:	687b      	ldr	r3, [r7, #4]
+ 8005e84:	68db      	ldr	r3, [r3, #12]
+ 8005e86:	2b00      	cmp	r3, #0
+ 8005e88:	d10c      	bne.n	8005ea4 <HAL_RCC_OscConfig+0x334>
+ 8005e8a:	4b6a      	ldr	r3, [pc, #424]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e8c:	6a1b      	ldr	r3, [r3, #32]
+ 8005e8e:	4a69      	ldr	r2, [pc, #420]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e90:	f023 0301 	bic.w	r3, r3, #1
+ 8005e94:	6213      	str	r3, [r2, #32]
+ 8005e96:	4b67      	ldr	r3, [pc, #412]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e98:	6a1b      	ldr	r3, [r3, #32]
+ 8005e9a:	4a66      	ldr	r2, [pc, #408]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005e9c:	f023 0304 	bic.w	r3, r3, #4
+ 8005ea0:	6213      	str	r3, [r2, #32]
+ 8005ea2:	e01c      	b.n	8005ede <HAL_RCC_OscConfig+0x36e>
+ 8005ea4:	687b      	ldr	r3, [r7, #4]
+ 8005ea6:	68db      	ldr	r3, [r3, #12]
+ 8005ea8:	2b05      	cmp	r3, #5
+ 8005eaa:	d10c      	bne.n	8005ec6 <HAL_RCC_OscConfig+0x356>
+ 8005eac:	4b61      	ldr	r3, [pc, #388]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005eae:	6a1b      	ldr	r3, [r3, #32]
+ 8005eb0:	4a60      	ldr	r2, [pc, #384]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005eb2:	f043 0304 	orr.w	r3, r3, #4
+ 8005eb6:	6213      	str	r3, [r2, #32]
+ 8005eb8:	4b5e      	ldr	r3, [pc, #376]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005eba:	6a1b      	ldr	r3, [r3, #32]
+ 8005ebc:	4a5d      	ldr	r2, [pc, #372]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005ebe:	f043 0301 	orr.w	r3, r3, #1
+ 8005ec2:	6213      	str	r3, [r2, #32]
+ 8005ec4:	e00b      	b.n	8005ede <HAL_RCC_OscConfig+0x36e>
+ 8005ec6:	4b5b      	ldr	r3, [pc, #364]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005ec8:	6a1b      	ldr	r3, [r3, #32]
+ 8005eca:	4a5a      	ldr	r2, [pc, #360]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005ecc:	f023 0301 	bic.w	r3, r3, #1
+ 8005ed0:	6213      	str	r3, [r2, #32]
+ 8005ed2:	4b58      	ldr	r3, [pc, #352]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005ed4:	6a1b      	ldr	r3, [r3, #32]
+ 8005ed6:	4a57      	ldr	r2, [pc, #348]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005ed8:	f023 0304 	bic.w	r3, r3, #4
+ 8005edc:	6213      	str	r3, [r2, #32]
     /* Check the LSE State */
     if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- 8004ab6:	687b      	ldr	r3, [r7, #4]
- 8004ab8:	68db      	ldr	r3, [r3, #12]
- 8004aba:	2b00      	cmp	r3, #0
- 8004abc:	d015      	beq.n	8004aea <HAL_RCC_OscConfig+0x3a2>
+ 8005ede:	687b      	ldr	r3, [r7, #4]
+ 8005ee0:	68db      	ldr	r3, [r3, #12]
+ 8005ee2:	2b00      	cmp	r3, #0
+ 8005ee4:	d015      	beq.n	8005f12 <HAL_RCC_OscConfig+0x3a2>
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8004abe:	f7fe f843 	bl	8002b48 <HAL_GetTick>
- 8004ac2:	6138      	str	r0, [r7, #16]
+ 8005ee6:	f7fd f9f5 	bl	80032d4 <HAL_GetTick>
+ 8005eea:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is ready */
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8004ac4:	e00a      	b.n	8004adc <HAL_RCC_OscConfig+0x394>
+ 8005eec:	e00a      	b.n	8005f04 <HAL_RCC_OscConfig+0x394>
       {
         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8004ac6:	f7fe f83f 	bl	8002b48 <HAL_GetTick>
- 8004aca:	4602      	mov	r2, r0
- 8004acc:	693b      	ldr	r3, [r7, #16]
- 8004ace:	1ad3      	subs	r3, r2, r3
- 8004ad0:	f241 3288 	movw	r2, #5000	@ 0x1388
- 8004ad4:	4293      	cmp	r3, r2
- 8004ad6:	d901      	bls.n	8004adc <HAL_RCC_OscConfig+0x394>
+ 8005eee:	f7fd f9f1 	bl	80032d4 <HAL_GetTick>
+ 8005ef2:	4602      	mov	r2, r0
+ 8005ef4:	693b      	ldr	r3, [r7, #16]
+ 8005ef6:	1ad3      	subs	r3, r2, r3
+ 8005ef8:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 8005efc:	4293      	cmp	r3, r2
+ 8005efe:	d901      	bls.n	8005f04 <HAL_RCC_OscConfig+0x394>
         {
           return HAL_TIMEOUT;
- 8004ad8:	2303      	movs	r3, #3
- 8004ada:	e0b1      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005f00:	2303      	movs	r3, #3
+ 8005f02:	e0b1      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8004adc:	4b4b      	ldr	r3, [pc, #300]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004ade:	6a1b      	ldr	r3, [r3, #32]
- 8004ae0:	f003 0302 	and.w	r3, r3, #2
- 8004ae4:	2b00      	cmp	r3, #0
- 8004ae6:	d0ee      	beq.n	8004ac6 <HAL_RCC_OscConfig+0x37e>
- 8004ae8:	e014      	b.n	8004b14 <HAL_RCC_OscConfig+0x3cc>
+ 8005f04:	4b4b      	ldr	r3, [pc, #300]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f06:	6a1b      	ldr	r3, [r3, #32]
+ 8005f08:	f003 0302 	and.w	r3, r3, #2
+ 8005f0c:	2b00      	cmp	r3, #0
+ 8005f0e:	d0ee      	beq.n	8005eee <HAL_RCC_OscConfig+0x37e>
+ 8005f10:	e014      	b.n	8005f3c <HAL_RCC_OscConfig+0x3cc>
       }
     }
     else
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8004aea:	f7fe f82d 	bl	8002b48 <HAL_GetTick>
- 8004aee:	6138      	str	r0, [r7, #16]
+ 8005f12:	f7fd f9df 	bl	80032d4 <HAL_GetTick>
+ 8005f16:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is disabled */
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8004af0:	e00a      	b.n	8004b08 <HAL_RCC_OscConfig+0x3c0>
+ 8005f18:	e00a      	b.n	8005f30 <HAL_RCC_OscConfig+0x3c0>
       {
         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8004af2:	f7fe f829 	bl	8002b48 <HAL_GetTick>
- 8004af6:	4602      	mov	r2, r0
- 8004af8:	693b      	ldr	r3, [r7, #16]
- 8004afa:	1ad3      	subs	r3, r2, r3
- 8004afc:	f241 3288 	movw	r2, #5000	@ 0x1388
- 8004b00:	4293      	cmp	r3, r2
- 8004b02:	d901      	bls.n	8004b08 <HAL_RCC_OscConfig+0x3c0>
+ 8005f1a:	f7fd f9db 	bl	80032d4 <HAL_GetTick>
+ 8005f1e:	4602      	mov	r2, r0
+ 8005f20:	693b      	ldr	r3, [r7, #16]
+ 8005f22:	1ad3      	subs	r3, r2, r3
+ 8005f24:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 8005f28:	4293      	cmp	r3, r2
+ 8005f2a:	d901      	bls.n	8005f30 <HAL_RCC_OscConfig+0x3c0>
         {
           return HAL_TIMEOUT;
- 8004b04:	2303      	movs	r3, #3
- 8004b06:	e09b      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005f2c:	2303      	movs	r3, #3
+ 8005f2e:	e09b      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8004b08:	4b40      	ldr	r3, [pc, #256]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b0a:	6a1b      	ldr	r3, [r3, #32]
- 8004b0c:	f003 0302 	and.w	r3, r3, #2
- 8004b10:	2b00      	cmp	r3, #0
- 8004b12:	d1ee      	bne.n	8004af2 <HAL_RCC_OscConfig+0x3aa>
+ 8005f30:	4b40      	ldr	r3, [pc, #256]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f32:	6a1b      	ldr	r3, [r3, #32]
+ 8005f34:	f003 0302 	and.w	r3, r3, #2
+ 8005f38:	2b00      	cmp	r3, #0
+ 8005f3a:	d1ee      	bne.n	8005f1a <HAL_RCC_OscConfig+0x3aa>
         }
       }
     }
 
     /* Require to disable power clock if necessary */
     if (pwrclkchanged == SET)
- 8004b14:	7dfb      	ldrb	r3, [r7, #23]
- 8004b16:	2b01      	cmp	r3, #1
- 8004b18:	d105      	bne.n	8004b26 <HAL_RCC_OscConfig+0x3de>
+ 8005f3c:	7dfb      	ldrb	r3, [r7, #23]
+ 8005f3e:	2b01      	cmp	r3, #1
+ 8005f40:	d105      	bne.n	8005f4e <HAL_RCC_OscConfig+0x3de>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 8004b1a:	4b3c      	ldr	r3, [pc, #240]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b1c:	69db      	ldr	r3, [r3, #28]
- 8004b1e:	4a3b      	ldr	r2, [pc, #236]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b20:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
- 8004b24:	61d3      	str	r3, [r2, #28]
+ 8005f42:	4b3c      	ldr	r3, [pc, #240]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f44:	69db      	ldr	r3, [r3, #28]
+ 8005f46:	4a3b      	ldr	r2, [pc, #236]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f48:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 8005f4c:	61d3      	str	r3, [r2, #28]
 
 #endif /* RCC_CR_PLL2ON */
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8004b26:	687b      	ldr	r3, [r7, #4]
- 8004b28:	69db      	ldr	r3, [r3, #28]
- 8004b2a:	2b00      	cmp	r3, #0
- 8004b2c:	f000 8087 	beq.w	8004c3e <HAL_RCC_OscConfig+0x4f6>
+ 8005f4e:	687b      	ldr	r3, [r7, #4]
+ 8005f50:	69db      	ldr	r3, [r3, #28]
+ 8005f52:	2b00      	cmp	r3, #0
+ 8005f54:	f000 8087 	beq.w	8006066 <HAL_RCC_OscConfig+0x4f6>
   {
     /* Check if the PLL is used as system clock or not */
     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8004b30:	4b36      	ldr	r3, [pc, #216]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b32:	685b      	ldr	r3, [r3, #4]
- 8004b34:	f003 030c 	and.w	r3, r3, #12
- 8004b38:	2b08      	cmp	r3, #8
- 8004b3a:	d061      	beq.n	8004c00 <HAL_RCC_OscConfig+0x4b8>
+ 8005f58:	4b36      	ldr	r3, [pc, #216]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f5a:	685b      	ldr	r3, [r3, #4]
+ 8005f5c:	f003 030c 	and.w	r3, r3, #12
+ 8005f60:	2b08      	cmp	r3, #8
+ 8005f62:	d061      	beq.n	8006028 <HAL_RCC_OscConfig+0x4b8>
     {
       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8004b3c:	687b      	ldr	r3, [r7, #4]
- 8004b3e:	69db      	ldr	r3, [r3, #28]
- 8004b40:	2b02      	cmp	r3, #2
- 8004b42:	d146      	bne.n	8004bd2 <HAL_RCC_OscConfig+0x48a>
+ 8005f64:	687b      	ldr	r3, [r7, #4]
+ 8005f66:	69db      	ldr	r3, [r3, #28]
+ 8005f68:	2b02      	cmp	r3, #2
+ 8005f6a:	d146      	bne.n	8005ffa <HAL_RCC_OscConfig+0x48a>
         /* Check the parameters */
         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
 
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 8004b44:	4b33      	ldr	r3, [pc, #204]	@ (8004c14 <HAL_RCC_OscConfig+0x4cc>)
- 8004b46:	2200      	movs	r2, #0
- 8004b48:	601a      	str	r2, [r3, #0]
+ 8005f6c:	4b33      	ldr	r3, [pc, #204]	@ (800603c <HAL_RCC_OscConfig+0x4cc>)
+ 8005f6e:	2200      	movs	r2, #0
+ 8005f70:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8004b4a:	f7fd fffd 	bl	8002b48 <HAL_GetTick>
- 8004b4e:	6138      	str	r0, [r7, #16]
+ 8005f72:	f7fd f9af 	bl	80032d4 <HAL_GetTick>
+ 8005f76:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is disabled */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8004b50:	e008      	b.n	8004b64 <HAL_RCC_OscConfig+0x41c>
+ 8005f78:	e008      	b.n	8005f8c <HAL_RCC_OscConfig+0x41c>
         {
           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 8004b52:	f7fd fff9 	bl	8002b48 <HAL_GetTick>
- 8004b56:	4602      	mov	r2, r0
- 8004b58:	693b      	ldr	r3, [r7, #16]
- 8004b5a:	1ad3      	subs	r3, r2, r3
- 8004b5c:	2b02      	cmp	r3, #2
- 8004b5e:	d901      	bls.n	8004b64 <HAL_RCC_OscConfig+0x41c>
+ 8005f7a:	f7fd f9ab 	bl	80032d4 <HAL_GetTick>
+ 8005f7e:	4602      	mov	r2, r0
+ 8005f80:	693b      	ldr	r3, [r7, #16]
+ 8005f82:	1ad3      	subs	r3, r2, r3
+ 8005f84:	2b02      	cmp	r3, #2
+ 8005f86:	d901      	bls.n	8005f8c <HAL_RCC_OscConfig+0x41c>
           {
             return HAL_TIMEOUT;
- 8004b60:	2303      	movs	r3, #3
- 8004b62:	e06d      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005f88:	2303      	movs	r3, #3
+ 8005f8a:	e06d      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8004b64:	4b29      	ldr	r3, [pc, #164]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b66:	681b      	ldr	r3, [r3, #0]
- 8004b68:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 8004b6c:	2b00      	cmp	r3, #0
- 8004b6e:	d1f0      	bne.n	8004b52 <HAL_RCC_OscConfig+0x40a>
+ 8005f8c:	4b29      	ldr	r3, [pc, #164]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005f8e:	681b      	ldr	r3, [r3, #0]
+ 8005f90:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 8005f94:	2b00      	cmp	r3, #0
+ 8005f96:	d1f0      	bne.n	8005f7a <HAL_RCC_OscConfig+0x40a>
           }
         }
 
         /* Configure the HSE prediv factor --------------------------------*/
         /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
         if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
- 8004b70:	687b      	ldr	r3, [r7, #4]
- 8004b72:	6a1b      	ldr	r3, [r3, #32]
- 8004b74:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
- 8004b78:	d108      	bne.n	8004b8c <HAL_RCC_OscConfig+0x444>
+ 8005f98:	687b      	ldr	r3, [r7, #4]
+ 8005f9a:	6a1b      	ldr	r3, [r3, #32]
+ 8005f9c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8005fa0:	d108      	bne.n	8005fb4 <HAL_RCC_OscConfig+0x444>
           /* Set PREDIV1 source */
           SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
 #endif /* RCC_CFGR2_PREDIV1SRC */
 
           /* Set PREDIV1 Value */
           __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
- 8004b7a:	4b24      	ldr	r3, [pc, #144]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b7c:	685b      	ldr	r3, [r3, #4]
- 8004b7e:	f423 3200 	bic.w	r2, r3, #131072	@ 0x20000
- 8004b82:	687b      	ldr	r3, [r7, #4]
- 8004b84:	689b      	ldr	r3, [r3, #8]
- 8004b86:	4921      	ldr	r1, [pc, #132]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b88:	4313      	orrs	r3, r2
- 8004b8a:	604b      	str	r3, [r1, #4]
+ 8005fa2:	4b24      	ldr	r3, [pc, #144]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005fa4:	685b      	ldr	r3, [r3, #4]
+ 8005fa6:	f423 3200 	bic.w	r2, r3, #131072	@ 0x20000
+ 8005faa:	687b      	ldr	r3, [r7, #4]
+ 8005fac:	689b      	ldr	r3, [r3, #8]
+ 8005fae:	4921      	ldr	r1, [pc, #132]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005fb0:	4313      	orrs	r3, r2
+ 8005fb2:	604b      	str	r3, [r1, #4]
         }
 
         /* Configure the main PLL clock source and multiplication factors. */
         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8004b8c:	4b1f      	ldr	r3, [pc, #124]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004b8e:	685b      	ldr	r3, [r3, #4]
- 8004b90:	f423 1274 	bic.w	r2, r3, #3997696	@ 0x3d0000
- 8004b94:	687b      	ldr	r3, [r7, #4]
- 8004b96:	6a19      	ldr	r1, [r3, #32]
- 8004b98:	687b      	ldr	r3, [r7, #4]
- 8004b9a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8004b9c:	430b      	orrs	r3, r1
- 8004b9e:	491b      	ldr	r1, [pc, #108]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004ba0:	4313      	orrs	r3, r2
- 8004ba2:	604b      	str	r3, [r1, #4]
+ 8005fb4:	4b1f      	ldr	r3, [pc, #124]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005fb6:	685b      	ldr	r3, [r3, #4]
+ 8005fb8:	f423 1274 	bic.w	r2, r3, #3997696	@ 0x3d0000
+ 8005fbc:	687b      	ldr	r3, [r7, #4]
+ 8005fbe:	6a19      	ldr	r1, [r3, #32]
+ 8005fc0:	687b      	ldr	r3, [r7, #4]
+ 8005fc2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8005fc4:	430b      	orrs	r3, r1
+ 8005fc6:	491b      	ldr	r1, [pc, #108]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005fc8:	4313      	orrs	r3, r2
+ 8005fca:	604b      	str	r3, [r1, #4]
                              RCC_OscInitStruct->PLL.PLLMUL);
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
- 8004ba4:	4b1b      	ldr	r3, [pc, #108]	@ (8004c14 <HAL_RCC_OscConfig+0x4cc>)
- 8004ba6:	2201      	movs	r2, #1
- 8004ba8:	601a      	str	r2, [r3, #0]
+ 8005fcc:	4b1b      	ldr	r3, [pc, #108]	@ (800603c <HAL_RCC_OscConfig+0x4cc>)
+ 8005fce:	2201      	movs	r2, #1
+ 8005fd0:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8004baa:	f7fd ffcd 	bl	8002b48 <HAL_GetTick>
- 8004bae:	6138      	str	r0, [r7, #16]
+ 8005fd2:	f7fd f97f 	bl	80032d4 <HAL_GetTick>
+ 8005fd6:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is ready */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
- 8004bb0:	e008      	b.n	8004bc4 <HAL_RCC_OscConfig+0x47c>
+ 8005fd8:	e008      	b.n	8005fec <HAL_RCC_OscConfig+0x47c>
         {
           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 8004bb2:	f7fd ffc9 	bl	8002b48 <HAL_GetTick>
- 8004bb6:	4602      	mov	r2, r0
- 8004bb8:	693b      	ldr	r3, [r7, #16]
- 8004bba:	1ad3      	subs	r3, r2, r3
- 8004bbc:	2b02      	cmp	r3, #2
- 8004bbe:	d901      	bls.n	8004bc4 <HAL_RCC_OscConfig+0x47c>
+ 8005fda:	f7fd f97b 	bl	80032d4 <HAL_GetTick>
+ 8005fde:	4602      	mov	r2, r0
+ 8005fe0:	693b      	ldr	r3, [r7, #16]
+ 8005fe2:	1ad3      	subs	r3, r2, r3
+ 8005fe4:	2b02      	cmp	r3, #2
+ 8005fe6:	d901      	bls.n	8005fec <HAL_RCC_OscConfig+0x47c>
           {
             return HAL_TIMEOUT;
- 8004bc0:	2303      	movs	r3, #3
- 8004bc2:	e03d      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8005fe8:	2303      	movs	r3, #3
+ 8005fea:	e03d      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
- 8004bc4:	4b11      	ldr	r3, [pc, #68]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004bc6:	681b      	ldr	r3, [r3, #0]
- 8004bc8:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 8004bcc:	2b00      	cmp	r3, #0
- 8004bce:	d0f0      	beq.n	8004bb2 <HAL_RCC_OscConfig+0x46a>
- 8004bd0:	e035      	b.n	8004c3e <HAL_RCC_OscConfig+0x4f6>
+ 8005fec:	4b11      	ldr	r3, [pc, #68]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 8005fee:	681b      	ldr	r3, [r3, #0]
+ 8005ff0:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 8005ff4:	2b00      	cmp	r3, #0
+ 8005ff6:	d0f0      	beq.n	8005fda <HAL_RCC_OscConfig+0x46a>
+ 8005ff8:	e035      	b.n	8006066 <HAL_RCC_OscConfig+0x4f6>
         }
       }
       else
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 8004bd2:	4b10      	ldr	r3, [pc, #64]	@ (8004c14 <HAL_RCC_OscConfig+0x4cc>)
- 8004bd4:	2200      	movs	r2, #0
- 8004bd6:	601a      	str	r2, [r3, #0]
+ 8005ffa:	4b10      	ldr	r3, [pc, #64]	@ (800603c <HAL_RCC_OscConfig+0x4cc>)
+ 8005ffc:	2200      	movs	r2, #0
+ 8005ffe:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8004bd8:	f7fd ffb6 	bl	8002b48 <HAL_GetTick>
- 8004bdc:	6138      	str	r0, [r7, #16]
+ 8006000:	f7fd f968 	bl	80032d4 <HAL_GetTick>
+ 8006004:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is disabled */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8004bde:	e008      	b.n	8004bf2 <HAL_RCC_OscConfig+0x4aa>
+ 8006006:	e008      	b.n	800601a <HAL_RCC_OscConfig+0x4aa>
         {
           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- 8004be0:	f7fd ffb2 	bl	8002b48 <HAL_GetTick>
- 8004be4:	4602      	mov	r2, r0
- 8004be6:	693b      	ldr	r3, [r7, #16]
- 8004be8:	1ad3      	subs	r3, r2, r3
- 8004bea:	2b02      	cmp	r3, #2
- 8004bec:	d901      	bls.n	8004bf2 <HAL_RCC_OscConfig+0x4aa>
+ 8006008:	f7fd f964 	bl	80032d4 <HAL_GetTick>
+ 800600c:	4602      	mov	r2, r0
+ 800600e:	693b      	ldr	r3, [r7, #16]
+ 8006010:	1ad3      	subs	r3, r2, r3
+ 8006012:	2b02      	cmp	r3, #2
+ 8006014:	d901      	bls.n	800601a <HAL_RCC_OscConfig+0x4aa>
           {
             return HAL_TIMEOUT;
- 8004bee:	2303      	movs	r3, #3
- 8004bf0:	e026      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8006016:	2303      	movs	r3, #3
+ 8006018:	e026      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8004bf2:	4b06      	ldr	r3, [pc, #24]	@ (8004c0c <HAL_RCC_OscConfig+0x4c4>)
- 8004bf4:	681b      	ldr	r3, [r3, #0]
- 8004bf6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 8004bfa:	2b00      	cmp	r3, #0
- 8004bfc:	d1f0      	bne.n	8004be0 <HAL_RCC_OscConfig+0x498>
- 8004bfe:	e01e      	b.n	8004c3e <HAL_RCC_OscConfig+0x4f6>
+ 800601a:	4b06      	ldr	r3, [pc, #24]	@ (8006034 <HAL_RCC_OscConfig+0x4c4>)
+ 800601c:	681b      	ldr	r3, [r3, #0]
+ 800601e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 8006022:	2b00      	cmp	r3, #0
+ 8006024:	d1f0      	bne.n	8006008 <HAL_RCC_OscConfig+0x498>
+ 8006026:	e01e      	b.n	8006066 <HAL_RCC_OscConfig+0x4f6>
       }
     }
     else
     {
       /* Check if there is a request to disable the PLL used as System clock source */
       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 8004c00:	687b      	ldr	r3, [r7, #4]
- 8004c02:	69db      	ldr	r3, [r3, #28]
- 8004c04:	2b01      	cmp	r3, #1
- 8004c06:	d107      	bne.n	8004c18 <HAL_RCC_OscConfig+0x4d0>
+ 8006028:	687b      	ldr	r3, [r7, #4]
+ 800602a:	69db      	ldr	r3, [r3, #28]
+ 800602c:	2b01      	cmp	r3, #1
+ 800602e:	d107      	bne.n	8006040 <HAL_RCC_OscConfig+0x4d0>
       {
         return HAL_ERROR;
- 8004c08:	2301      	movs	r3, #1
- 8004c0a:	e019      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
- 8004c0c:	40021000 	.word	0x40021000
- 8004c10:	40007000 	.word	0x40007000
- 8004c14:	42420060 	.word	0x42420060
+ 8006030:	2301      	movs	r3, #1
+ 8006032:	e019      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
+ 8006034:	40021000 	.word	0x40021000
+ 8006038:	40007000 	.word	0x40007000
+ 800603c:	42420060 	.word	0x42420060
       }
       else
       {
         /* Do not return HAL_ERROR if request repeats the current configuration */
         pll_config = RCC->CFGR;
- 8004c18:	4b0b      	ldr	r3, [pc, #44]	@ (8004c48 <HAL_RCC_OscConfig+0x500>)
- 8004c1a:	685b      	ldr	r3, [r3, #4]
- 8004c1c:	60fb      	str	r3, [r7, #12]
+ 8006040:	4b0b      	ldr	r3, [pc, #44]	@ (8006070 <HAL_RCC_OscConfig+0x500>)
+ 8006042:	685b      	ldr	r3, [r3, #4]
+ 8006044:	60fb      	str	r3, [r7, #12]
         if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8004c1e:	68fb      	ldr	r3, [r7, #12]
- 8004c20:	f403 3280 	and.w	r2, r3, #65536	@ 0x10000
- 8004c24:	687b      	ldr	r3, [r7, #4]
- 8004c26:	6a1b      	ldr	r3, [r3, #32]
- 8004c28:	429a      	cmp	r2, r3
- 8004c2a:	d106      	bne.n	8004c3a <HAL_RCC_OscConfig+0x4f2>
+ 8006046:	68fb      	ldr	r3, [r7, #12]
+ 8006048:	f403 3280 	and.w	r2, r3, #65536	@ 0x10000
+ 800604c:	687b      	ldr	r3, [r7, #4]
+ 800604e:	6a1b      	ldr	r3, [r3, #32]
+ 8006050:	429a      	cmp	r2, r3
+ 8006052:	d106      	bne.n	8006062 <HAL_RCC_OscConfig+0x4f2>
             (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
- 8004c2c:	68fb      	ldr	r3, [r7, #12]
- 8004c2e:	f403 1270 	and.w	r2, r3, #3932160	@ 0x3c0000
- 8004c32:	687b      	ldr	r3, [r7, #4]
- 8004c34:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8006054:	68fb      	ldr	r3, [r7, #12]
+ 8006056:	f403 1270 	and.w	r2, r3, #3932160	@ 0x3c0000
+ 800605a:	687b      	ldr	r3, [r7, #4]
+ 800605c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
         if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8004c36:	429a      	cmp	r2, r3
- 8004c38:	d001      	beq.n	8004c3e <HAL_RCC_OscConfig+0x4f6>
+ 800605e:	429a      	cmp	r2, r3
+ 8006060:	d001      	beq.n	8006066 <HAL_RCC_OscConfig+0x4f6>
         {
           return HAL_ERROR;
- 8004c3a:	2301      	movs	r3, #1
- 8004c3c:	e000      	b.n	8004c40 <HAL_RCC_OscConfig+0x4f8>
+ 8006062:	2301      	movs	r3, #1
+ 8006064:	e000      	b.n	8006068 <HAL_RCC_OscConfig+0x4f8>
         }
       }
     }
   }
 
   return HAL_OK;
- 8004c3e:	2300      	movs	r3, #0
+ 8006066:	2300      	movs	r3, #0
 }
- 8004c40:	4618      	mov	r0, r3
- 8004c42:	3718      	adds	r7, #24
- 8004c44:	46bd      	mov	sp, r7
- 8004c46:	bd80      	pop	{r7, pc}
- 8004c48:	40021000 	.word	0x40021000
+ 8006068:	4618      	mov	r0, r3
+ 800606a:	3718      	adds	r7, #24
+ 800606c:	46bd      	mov	sp, r7
+ 800606e:	bd80      	pop	{r7, pc}
+ 8006070:	40021000 	.word	0x40021000
 
-08004c4c <HAL_RCC_ClockConfig>:
+08006074 <HAL_RCC_ClockConfig>:
   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
   *         currently used as system clock source.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 {
- 8004c4c:	b580      	push	{r7, lr}
- 8004c4e:	b084      	sub	sp, #16
- 8004c50:	af00      	add	r7, sp, #0
- 8004c52:	6078      	str	r0, [r7, #4]
- 8004c54:	6039      	str	r1, [r7, #0]
+ 8006074:	b580      	push	{r7, lr}
+ 8006076:	b084      	sub	sp, #16
+ 8006078:	af00      	add	r7, sp, #0
+ 800607a:	6078      	str	r0, [r7, #4]
+ 800607c:	6039      	str	r1, [r7, #0]
   uint32_t tickstart;
 
   /* Check Null pointer */
   if (RCC_ClkInitStruct == NULL)
- 8004c56:	687b      	ldr	r3, [r7, #4]
- 8004c58:	2b00      	cmp	r3, #0
- 8004c5a:	d101      	bne.n	8004c60 <HAL_RCC_ClockConfig+0x14>
+ 800607e:	687b      	ldr	r3, [r7, #4]
+ 8006080:	2b00      	cmp	r3, #0
+ 8006082:	d101      	bne.n	8006088 <HAL_RCC_ClockConfig+0x14>
   {
     return HAL_ERROR;
- 8004c5c:	2301      	movs	r3, #1
- 8004c5e:	e0d0      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 8006084:	2301      	movs	r3, #1
+ 8006086:	e0d0      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
   must be correctly programmed according to the frequency of the CPU clock
     (HCLK) of the device. */
 
 #if defined(FLASH_ACR_LATENCY)
   /* Increasing the number of wait states because of higher CPU frequency */
   if (FLatency > __HAL_FLASH_GET_LATENCY())
- 8004c60:	4b6a      	ldr	r3, [pc, #424]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004c62:	681b      	ldr	r3, [r3, #0]
- 8004c64:	f003 0307 	and.w	r3, r3, #7
- 8004c68:	683a      	ldr	r2, [r7, #0]
- 8004c6a:	429a      	cmp	r2, r3
- 8004c6c:	d910      	bls.n	8004c90 <HAL_RCC_ClockConfig+0x44>
+ 8006088:	4b6a      	ldr	r3, [pc, #424]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 800608a:	681b      	ldr	r3, [r3, #0]
+ 800608c:	f003 0307 	and.w	r3, r3, #7
+ 8006090:	683a      	ldr	r2, [r7, #0]
+ 8006092:	429a      	cmp	r2, r3
+ 8006094:	d910      	bls.n	80060b8 <HAL_RCC_ClockConfig+0x44>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8004c6e:	4b67      	ldr	r3, [pc, #412]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004c70:	681b      	ldr	r3, [r3, #0]
- 8004c72:	f023 0207 	bic.w	r2, r3, #7
- 8004c76:	4965      	ldr	r1, [pc, #404]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004c78:	683b      	ldr	r3, [r7, #0]
- 8004c7a:	4313      	orrs	r3, r2
- 8004c7c:	600b      	str	r3, [r1, #0]
+ 8006096:	4b67      	ldr	r3, [pc, #412]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 8006098:	681b      	ldr	r3, [r3, #0]
+ 800609a:	f023 0207 	bic.w	r2, r3, #7
+ 800609e:	4965      	ldr	r1, [pc, #404]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 80060a0:	683b      	ldr	r3, [r7, #0]
+ 80060a2:	4313      	orrs	r3, r2
+ 80060a4:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8004c7e:	4b63      	ldr	r3, [pc, #396]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004c80:	681b      	ldr	r3, [r3, #0]
- 8004c82:	f003 0307 	and.w	r3, r3, #7
- 8004c86:	683a      	ldr	r2, [r7, #0]
- 8004c88:	429a      	cmp	r2, r3
- 8004c8a:	d001      	beq.n	8004c90 <HAL_RCC_ClockConfig+0x44>
+ 80060a6:	4b63      	ldr	r3, [pc, #396]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 80060a8:	681b      	ldr	r3, [r3, #0]
+ 80060aa:	f003 0307 	and.w	r3, r3, #7
+ 80060ae:	683a      	ldr	r2, [r7, #0]
+ 80060b0:	429a      	cmp	r2, r3
+ 80060b2:	d001      	beq.n	80060b8 <HAL_RCC_ClockConfig+0x44>
   {
     return HAL_ERROR;
- 8004c8c:	2301      	movs	r3, #1
- 8004c8e:	e0b8      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 80060b4:	2301      	movs	r3, #1
+ 80060b6:	e0b8      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
   }
 }
 
 #endif /* FLASH_ACR_LATENCY */
 /*-------------------------- HCLK Configuration --------------------------*/
 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8004c90:	687b      	ldr	r3, [r7, #4]
- 8004c92:	681b      	ldr	r3, [r3, #0]
- 8004c94:	f003 0302 	and.w	r3, r3, #2
- 8004c98:	2b00      	cmp	r3, #0
- 8004c9a:	d020      	beq.n	8004cde <HAL_RCC_ClockConfig+0x92>
+ 80060b8:	687b      	ldr	r3, [r7, #4]
+ 80060ba:	681b      	ldr	r3, [r3, #0]
+ 80060bc:	f003 0302 	and.w	r3, r3, #2
+ 80060c0:	2b00      	cmp	r3, #0
+ 80060c2:	d020      	beq.n	8006106 <HAL_RCC_ClockConfig+0x92>
   {
     /* Set the highest APBx dividers in order to ensure that we do not go through
     a non-spec phase whatever we decrease or increase HCLK. */
     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8004c9c:	687b      	ldr	r3, [r7, #4]
- 8004c9e:	681b      	ldr	r3, [r3, #0]
- 8004ca0:	f003 0304 	and.w	r3, r3, #4
- 8004ca4:	2b00      	cmp	r3, #0
- 8004ca6:	d005      	beq.n	8004cb4 <HAL_RCC_ClockConfig+0x68>
+ 80060c4:	687b      	ldr	r3, [r7, #4]
+ 80060c6:	681b      	ldr	r3, [r3, #0]
+ 80060c8:	f003 0304 	and.w	r3, r3, #4
+ 80060cc:	2b00      	cmp	r3, #0
+ 80060ce:	d005      	beq.n	80060dc <HAL_RCC_ClockConfig+0x68>
     {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8004ca8:	4b59      	ldr	r3, [pc, #356]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004caa:	685b      	ldr	r3, [r3, #4]
- 8004cac:	4a58      	ldr	r2, [pc, #352]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cae:	f443 63e0 	orr.w	r3, r3, #1792	@ 0x700
- 8004cb2:	6053      	str	r3, [r2, #4]
+ 80060d0:	4b59      	ldr	r3, [pc, #356]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80060d2:	685b      	ldr	r3, [r3, #4]
+ 80060d4:	4a58      	ldr	r2, [pc, #352]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80060d6:	f443 63e0 	orr.w	r3, r3, #1792	@ 0x700
+ 80060da:	6053      	str	r3, [r2, #4]
     }
 
     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8004cb4:	687b      	ldr	r3, [r7, #4]
- 8004cb6:	681b      	ldr	r3, [r3, #0]
- 8004cb8:	f003 0308 	and.w	r3, r3, #8
- 8004cbc:	2b00      	cmp	r3, #0
- 8004cbe:	d005      	beq.n	8004ccc <HAL_RCC_ClockConfig+0x80>
+ 80060dc:	687b      	ldr	r3, [r7, #4]
+ 80060de:	681b      	ldr	r3, [r3, #0]
+ 80060e0:	f003 0308 	and.w	r3, r3, #8
+ 80060e4:	2b00      	cmp	r3, #0
+ 80060e6:	d005      	beq.n	80060f4 <HAL_RCC_ClockConfig+0x80>
     {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 8004cc0:	4b53      	ldr	r3, [pc, #332]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cc2:	685b      	ldr	r3, [r3, #4]
- 8004cc4:	4a52      	ldr	r2, [pc, #328]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cc6:	f443 5360 	orr.w	r3, r3, #14336	@ 0x3800
- 8004cca:	6053      	str	r3, [r2, #4]
+ 80060e8:	4b53      	ldr	r3, [pc, #332]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80060ea:	685b      	ldr	r3, [r3, #4]
+ 80060ec:	4a52      	ldr	r2, [pc, #328]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80060ee:	f443 5360 	orr.w	r3, r3, #14336	@ 0x3800
+ 80060f2:	6053      	str	r3, [r2, #4]
     }
 
     /* Set the new HCLK clock divider */
     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8004ccc:	4b50      	ldr	r3, [pc, #320]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cce:	685b      	ldr	r3, [r3, #4]
- 8004cd0:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
- 8004cd4:	687b      	ldr	r3, [r7, #4]
- 8004cd6:	689b      	ldr	r3, [r3, #8]
- 8004cd8:	494d      	ldr	r1, [pc, #308]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cda:	4313      	orrs	r3, r2
- 8004cdc:	604b      	str	r3, [r1, #4]
+ 80060f4:	4b50      	ldr	r3, [pc, #320]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80060f6:	685b      	ldr	r3, [r3, #4]
+ 80060f8:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
+ 80060fc:	687b      	ldr	r3, [r7, #4]
+ 80060fe:	689b      	ldr	r3, [r3, #8]
+ 8006100:	494d      	ldr	r1, [pc, #308]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006102:	4313      	orrs	r3, r2
+ 8006104:	604b      	str	r3, [r1, #4]
   }
 
   /*------------------------- SYSCLK Configuration ---------------------------*/
   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8004cde:	687b      	ldr	r3, [r7, #4]
- 8004ce0:	681b      	ldr	r3, [r3, #0]
- 8004ce2:	f003 0301 	and.w	r3, r3, #1
- 8004ce6:	2b00      	cmp	r3, #0
- 8004ce8:	d040      	beq.n	8004d6c <HAL_RCC_ClockConfig+0x120>
+ 8006106:	687b      	ldr	r3, [r7, #4]
+ 8006108:	681b      	ldr	r3, [r3, #0]
+ 800610a:	f003 0301 	and.w	r3, r3, #1
+ 800610e:	2b00      	cmp	r3, #0
+ 8006110:	d040      	beq.n	8006194 <HAL_RCC_ClockConfig+0x120>
   {
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 
     /* HSE is selected as System Clock Source */
     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8004cea:	687b      	ldr	r3, [r7, #4]
- 8004cec:	685b      	ldr	r3, [r3, #4]
- 8004cee:	2b01      	cmp	r3, #1
- 8004cf0:	d107      	bne.n	8004d02 <HAL_RCC_ClockConfig+0xb6>
+ 8006112:	687b      	ldr	r3, [r7, #4]
+ 8006114:	685b      	ldr	r3, [r3, #4]
+ 8006116:	2b01      	cmp	r3, #1
+ 8006118:	d107      	bne.n	800612a <HAL_RCC_ClockConfig+0xb6>
     {
       /* Check the HSE ready flag */
       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8004cf2:	4b47      	ldr	r3, [pc, #284]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004cf4:	681b      	ldr	r3, [r3, #0]
- 8004cf6:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8004cfa:	2b00      	cmp	r3, #0
- 8004cfc:	d115      	bne.n	8004d2a <HAL_RCC_ClockConfig+0xde>
+ 800611a:	4b47      	ldr	r3, [pc, #284]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 800611c:	681b      	ldr	r3, [r3, #0]
+ 800611e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8006122:	2b00      	cmp	r3, #0
+ 8006124:	d115      	bne.n	8006152 <HAL_RCC_ClockConfig+0xde>
       {
         return HAL_ERROR;
- 8004cfe:	2301      	movs	r3, #1
- 8004d00:	e07f      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 8006126:	2301      	movs	r3, #1
+ 8006128:	e07f      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
       }
     }
     /* PLL is selected as System Clock Source */
     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8004d02:	687b      	ldr	r3, [r7, #4]
- 8004d04:	685b      	ldr	r3, [r3, #4]
- 8004d06:	2b02      	cmp	r3, #2
- 8004d08:	d107      	bne.n	8004d1a <HAL_RCC_ClockConfig+0xce>
+ 800612a:	687b      	ldr	r3, [r7, #4]
+ 800612c:	685b      	ldr	r3, [r3, #4]
+ 800612e:	2b02      	cmp	r3, #2
+ 8006130:	d107      	bne.n	8006142 <HAL_RCC_ClockConfig+0xce>
     {
       /* Check the PLL ready flag */
       if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8004d0a:	4b41      	ldr	r3, [pc, #260]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004d0c:	681b      	ldr	r3, [r3, #0]
- 8004d0e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 8004d12:	2b00      	cmp	r3, #0
- 8004d14:	d109      	bne.n	8004d2a <HAL_RCC_ClockConfig+0xde>
+ 8006132:	4b41      	ldr	r3, [pc, #260]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006134:	681b      	ldr	r3, [r3, #0]
+ 8006136:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 800613a:	2b00      	cmp	r3, #0
+ 800613c:	d109      	bne.n	8006152 <HAL_RCC_ClockConfig+0xde>
       {
         return HAL_ERROR;
- 8004d16:	2301      	movs	r3, #1
- 8004d18:	e073      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 800613e:	2301      	movs	r3, #1
+ 8006140:	e073      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
     }
     /* HSI is selected as System Clock Source */
     else
     {
       /* Check the HSI ready flag */
       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8004d1a:	4b3d      	ldr	r3, [pc, #244]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004d1c:	681b      	ldr	r3, [r3, #0]
- 8004d1e:	f003 0302 	and.w	r3, r3, #2
- 8004d22:	2b00      	cmp	r3, #0
- 8004d24:	d101      	bne.n	8004d2a <HAL_RCC_ClockConfig+0xde>
+ 8006142:	4b3d      	ldr	r3, [pc, #244]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006144:	681b      	ldr	r3, [r3, #0]
+ 8006146:	f003 0302 	and.w	r3, r3, #2
+ 800614a:	2b00      	cmp	r3, #0
+ 800614c:	d101      	bne.n	8006152 <HAL_RCC_ClockConfig+0xde>
       {
         return HAL_ERROR;
- 8004d26:	2301      	movs	r3, #1
- 8004d28:	e06b      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 800614e:	2301      	movs	r3, #1
+ 8006150:	e06b      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
       }
     }
     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8004d2a:	4b39      	ldr	r3, [pc, #228]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004d2c:	685b      	ldr	r3, [r3, #4]
- 8004d2e:	f023 0203 	bic.w	r2, r3, #3
- 8004d32:	687b      	ldr	r3, [r7, #4]
- 8004d34:	685b      	ldr	r3, [r3, #4]
- 8004d36:	4936      	ldr	r1, [pc, #216]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004d38:	4313      	orrs	r3, r2
- 8004d3a:	604b      	str	r3, [r1, #4]
+ 8006152:	4b39      	ldr	r3, [pc, #228]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006154:	685b      	ldr	r3, [r3, #4]
+ 8006156:	f023 0203 	bic.w	r2, r3, #3
+ 800615a:	687b      	ldr	r3, [r7, #4]
+ 800615c:	685b      	ldr	r3, [r3, #4]
+ 800615e:	4936      	ldr	r1, [pc, #216]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006160:	4313      	orrs	r3, r2
+ 8006162:	604b      	str	r3, [r1, #4]
 
     /* Get Start Tick */
     tickstart = HAL_GetTick();
- 8004d3c:	f7fd ff04 	bl	8002b48 <HAL_GetTick>
- 8004d40:	60f8      	str	r0, [r7, #12]
+ 8006164:	f7fd f8b6 	bl	80032d4 <HAL_GetTick>
+ 8006168:	60f8      	str	r0, [r7, #12]
 
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8004d42:	e00a      	b.n	8004d5a <HAL_RCC_ClockConfig+0x10e>
+ 800616a:	e00a      	b.n	8006182 <HAL_RCC_ClockConfig+0x10e>
     {
       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8004d44:	f7fd ff00 	bl	8002b48 <HAL_GetTick>
- 8004d48:	4602      	mov	r2, r0
- 8004d4a:	68fb      	ldr	r3, [r7, #12]
- 8004d4c:	1ad3      	subs	r3, r2, r3
- 8004d4e:	f241 3288 	movw	r2, #5000	@ 0x1388
- 8004d52:	4293      	cmp	r3, r2
- 8004d54:	d901      	bls.n	8004d5a <HAL_RCC_ClockConfig+0x10e>
+ 800616c:	f7fd f8b2 	bl	80032d4 <HAL_GetTick>
+ 8006170:	4602      	mov	r2, r0
+ 8006172:	68fb      	ldr	r3, [r7, #12]
+ 8006174:	1ad3      	subs	r3, r2, r3
+ 8006176:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 800617a:	4293      	cmp	r3, r2
+ 800617c:	d901      	bls.n	8006182 <HAL_RCC_ClockConfig+0x10e>
       {
         return HAL_TIMEOUT;
- 8004d56:	2303      	movs	r3, #3
- 8004d58:	e053      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 800617e:	2303      	movs	r3, #3
+ 8006180:	e053      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8004d5a:	4b2d      	ldr	r3, [pc, #180]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004d5c:	685b      	ldr	r3, [r3, #4]
- 8004d5e:	f003 020c 	and.w	r2, r3, #12
- 8004d62:	687b      	ldr	r3, [r7, #4]
- 8004d64:	685b      	ldr	r3, [r3, #4]
- 8004d66:	009b      	lsls	r3, r3, #2
- 8004d68:	429a      	cmp	r2, r3
- 8004d6a:	d1eb      	bne.n	8004d44 <HAL_RCC_ClockConfig+0xf8>
+ 8006182:	4b2d      	ldr	r3, [pc, #180]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 8006184:	685b      	ldr	r3, [r3, #4]
+ 8006186:	f003 020c 	and.w	r2, r3, #12
+ 800618a:	687b      	ldr	r3, [r7, #4]
+ 800618c:	685b      	ldr	r3, [r3, #4]
+ 800618e:	009b      	lsls	r3, r3, #2
+ 8006190:	429a      	cmp	r2, r3
+ 8006192:	d1eb      	bne.n	800616c <HAL_RCC_ClockConfig+0xf8>
     }
   }
 
 #if defined(FLASH_ACR_LATENCY)
   /* Decreasing the number of wait states because of lower CPU frequency */
   if (FLatency < __HAL_FLASH_GET_LATENCY())
- 8004d6c:	4b27      	ldr	r3, [pc, #156]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004d6e:	681b      	ldr	r3, [r3, #0]
- 8004d70:	f003 0307 	and.w	r3, r3, #7
- 8004d74:	683a      	ldr	r2, [r7, #0]
- 8004d76:	429a      	cmp	r2, r3
- 8004d78:	d210      	bcs.n	8004d9c <HAL_RCC_ClockConfig+0x150>
+ 8006194:	4b27      	ldr	r3, [pc, #156]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 8006196:	681b      	ldr	r3, [r3, #0]
+ 8006198:	f003 0307 	and.w	r3, r3, #7
+ 800619c:	683a      	ldr	r2, [r7, #0]
+ 800619e:	429a      	cmp	r2, r3
+ 80061a0:	d210      	bcs.n	80061c4 <HAL_RCC_ClockConfig+0x150>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8004d7a:	4b24      	ldr	r3, [pc, #144]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004d7c:	681b      	ldr	r3, [r3, #0]
- 8004d7e:	f023 0207 	bic.w	r2, r3, #7
- 8004d82:	4922      	ldr	r1, [pc, #136]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004d84:	683b      	ldr	r3, [r7, #0]
- 8004d86:	4313      	orrs	r3, r2
- 8004d88:	600b      	str	r3, [r1, #0]
+ 80061a2:	4b24      	ldr	r3, [pc, #144]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 80061a4:	681b      	ldr	r3, [r3, #0]
+ 80061a6:	f023 0207 	bic.w	r2, r3, #7
+ 80061aa:	4922      	ldr	r1, [pc, #136]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 80061ac:	683b      	ldr	r3, [r7, #0]
+ 80061ae:	4313      	orrs	r3, r2
+ 80061b0:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8004d8a:	4b20      	ldr	r3, [pc, #128]	@ (8004e0c <HAL_RCC_ClockConfig+0x1c0>)
- 8004d8c:	681b      	ldr	r3, [r3, #0]
- 8004d8e:	f003 0307 	and.w	r3, r3, #7
- 8004d92:	683a      	ldr	r2, [r7, #0]
- 8004d94:	429a      	cmp	r2, r3
- 8004d96:	d001      	beq.n	8004d9c <HAL_RCC_ClockConfig+0x150>
+ 80061b2:	4b20      	ldr	r3, [pc, #128]	@ (8006234 <HAL_RCC_ClockConfig+0x1c0>)
+ 80061b4:	681b      	ldr	r3, [r3, #0]
+ 80061b6:	f003 0307 	and.w	r3, r3, #7
+ 80061ba:	683a      	ldr	r2, [r7, #0]
+ 80061bc:	429a      	cmp	r2, r3
+ 80061be:	d001      	beq.n	80061c4 <HAL_RCC_ClockConfig+0x150>
   {
     return HAL_ERROR;
- 8004d98:	2301      	movs	r3, #1
- 8004d9a:	e032      	b.n	8004e02 <HAL_RCC_ClockConfig+0x1b6>
+ 80061c0:	2301      	movs	r3, #1
+ 80061c2:	e032      	b.n	800622a <HAL_RCC_ClockConfig+0x1b6>
   }
 }
 #endif /* FLASH_ACR_LATENCY */
 
 /*-------------------------- PCLK1 Configuration ---------------------------*/
 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8004d9c:	687b      	ldr	r3, [r7, #4]
- 8004d9e:	681b      	ldr	r3, [r3, #0]
- 8004da0:	f003 0304 	and.w	r3, r3, #4
- 8004da4:	2b00      	cmp	r3, #0
- 8004da6:	d008      	beq.n	8004dba <HAL_RCC_ClockConfig+0x16e>
+ 80061c4:	687b      	ldr	r3, [r7, #4]
+ 80061c6:	681b      	ldr	r3, [r3, #0]
+ 80061c8:	f003 0304 	and.w	r3, r3, #4
+ 80061cc:	2b00      	cmp	r3, #0
+ 80061ce:	d008      	beq.n	80061e2 <HAL_RCC_ClockConfig+0x16e>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8004da8:	4b19      	ldr	r3, [pc, #100]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004daa:	685b      	ldr	r3, [r3, #4]
- 8004dac:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
- 8004db0:	687b      	ldr	r3, [r7, #4]
- 8004db2:	68db      	ldr	r3, [r3, #12]
- 8004db4:	4916      	ldr	r1, [pc, #88]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004db6:	4313      	orrs	r3, r2
- 8004db8:	604b      	str	r3, [r1, #4]
+ 80061d0:	4b19      	ldr	r3, [pc, #100]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80061d2:	685b      	ldr	r3, [r3, #4]
+ 80061d4:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
+ 80061d8:	687b      	ldr	r3, [r7, #4]
+ 80061da:	68db      	ldr	r3, [r3, #12]
+ 80061dc:	4916      	ldr	r1, [pc, #88]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80061de:	4313      	orrs	r3, r2
+ 80061e0:	604b      	str	r3, [r1, #4]
   }
 
   /*-------------------------- PCLK2 Configuration ---------------------------*/
   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8004dba:	687b      	ldr	r3, [r7, #4]
- 8004dbc:	681b      	ldr	r3, [r3, #0]
- 8004dbe:	f003 0308 	and.w	r3, r3, #8
- 8004dc2:	2b00      	cmp	r3, #0
- 8004dc4:	d009      	beq.n	8004dda <HAL_RCC_ClockConfig+0x18e>
+ 80061e2:	687b      	ldr	r3, [r7, #4]
+ 80061e4:	681b      	ldr	r3, [r3, #0]
+ 80061e6:	f003 0308 	and.w	r3, r3, #8
+ 80061ea:	2b00      	cmp	r3, #0
+ 80061ec:	d009      	beq.n	8006202 <HAL_RCC_ClockConfig+0x18e>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8004dc6:	4b12      	ldr	r3, [pc, #72]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004dc8:	685b      	ldr	r3, [r3, #4]
- 8004dca:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
- 8004dce:	687b      	ldr	r3, [r7, #4]
- 8004dd0:	691b      	ldr	r3, [r3, #16]
- 8004dd2:	00db      	lsls	r3, r3, #3
- 8004dd4:	490e      	ldr	r1, [pc, #56]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004dd6:	4313      	orrs	r3, r2
- 8004dd8:	604b      	str	r3, [r1, #4]
+ 80061ee:	4b12      	ldr	r3, [pc, #72]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80061f0:	685b      	ldr	r3, [r3, #4]
+ 80061f2:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
+ 80061f6:	687b      	ldr	r3, [r7, #4]
+ 80061f8:	691b      	ldr	r3, [r3, #16]
+ 80061fa:	00db      	lsls	r3, r3, #3
+ 80061fc:	490e      	ldr	r1, [pc, #56]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 80061fe:	4313      	orrs	r3, r2
+ 8006200:	604b      	str	r3, [r1, #4]
   }
 
   /* Update the SystemCoreClock global variable */
   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
- 8004dda:	f000 f821 	bl	8004e20 <HAL_RCC_GetSysClockFreq>
- 8004dde:	4602      	mov	r2, r0
- 8004de0:	4b0b      	ldr	r3, [pc, #44]	@ (8004e10 <HAL_RCC_ClockConfig+0x1c4>)
- 8004de2:	685b      	ldr	r3, [r3, #4]
- 8004de4:	091b      	lsrs	r3, r3, #4
- 8004de6:	f003 030f 	and.w	r3, r3, #15
- 8004dea:	490a      	ldr	r1, [pc, #40]	@ (8004e14 <HAL_RCC_ClockConfig+0x1c8>)
- 8004dec:	5ccb      	ldrb	r3, [r1, r3]
- 8004dee:	fa22 f303 	lsr.w	r3, r2, r3
- 8004df2:	4a09      	ldr	r2, [pc, #36]	@ (8004e18 <HAL_RCC_ClockConfig+0x1cc>)
- 8004df4:	6013      	str	r3, [r2, #0]
+ 8006202:	f000 f821 	bl	8006248 <HAL_RCC_GetSysClockFreq>
+ 8006206:	4602      	mov	r2, r0
+ 8006208:	4b0b      	ldr	r3, [pc, #44]	@ (8006238 <HAL_RCC_ClockConfig+0x1c4>)
+ 800620a:	685b      	ldr	r3, [r3, #4]
+ 800620c:	091b      	lsrs	r3, r3, #4
+ 800620e:	f003 030f 	and.w	r3, r3, #15
+ 8006212:	490a      	ldr	r1, [pc, #40]	@ (800623c <HAL_RCC_ClockConfig+0x1c8>)
+ 8006214:	5ccb      	ldrb	r3, [r1, r3]
+ 8006216:	fa22 f303 	lsr.w	r3, r2, r3
+ 800621a:	4a09      	ldr	r2, [pc, #36]	@ (8006240 <HAL_RCC_ClockConfig+0x1cc>)
+ 800621c:	6013      	str	r3, [r2, #0]
 
   /* Configure the source of time base considering new system clocks settings*/
   HAL_InitTick(uwTickPrio);
- 8004df6:	4b09      	ldr	r3, [pc, #36]	@ (8004e1c <HAL_RCC_ClockConfig+0x1d0>)
- 8004df8:	681b      	ldr	r3, [r3, #0]
- 8004dfa:	4618      	mov	r0, r3
- 8004dfc:	f7fd fe62 	bl	8002ac4 <HAL_InitTick>
+ 800621e:	4b09      	ldr	r3, [pc, #36]	@ (8006244 <HAL_RCC_ClockConfig+0x1d0>)
+ 8006220:	681b      	ldr	r3, [r3, #0]
+ 8006222:	4618      	mov	r0, r3
+ 8006224:	f7fd f814 	bl	8003250 <HAL_InitTick>
 
   return HAL_OK;
- 8004e00:	2300      	movs	r3, #0
+ 8006228:	2300      	movs	r3, #0
 }
- 8004e02:	4618      	mov	r0, r3
- 8004e04:	3710      	adds	r7, #16
- 8004e06:	46bd      	mov	sp, r7
- 8004e08:	bd80      	pop	{r7, pc}
- 8004e0a:	bf00      	nop
- 8004e0c:	40022000 	.word	0x40022000
- 8004e10:	40021000 	.word	0x40021000
- 8004e14:	08005f34 	.word	0x08005f34
- 8004e18:	2000001c 	.word	0x2000001c
- 8004e1c:	20000020 	.word	0x20000020
+ 800622a:	4618      	mov	r0, r3
+ 800622c:	3710      	adds	r7, #16
+ 800622e:	46bd      	mov	sp, r7
+ 8006230:	bd80      	pop	{r7, pc}
+ 8006232:	bf00      	nop
+ 8006234:	40022000 	.word	0x40022000
+ 8006238:	40021000 	.word	0x40021000
+ 800623c:	08007a60 	.word	0x08007a60
+ 8006240:	20000024 	.word	0x20000024
+ 8006244:	20000028 	.word	0x20000028
 
-08004e20 <HAL_RCC_GetSysClockFreq>:
+08006248 <HAL_RCC_GetSysClockFreq>:
   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
   *
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
- 8004e20:	b480      	push	{r7}
- 8004e22:	b087      	sub	sp, #28
- 8004e24:	af00      	add	r7, sp, #0
+ 8006248:	b480      	push	{r7}
+ 800624a:	b087      	sub	sp, #28
+ 800624c:	af00      	add	r7, sp, #0
 #else
   static const uint8_t aPredivFactorTable[2U] = {1, 2};
 #endif /*RCC_CFGR2_PREDIV1*/
 
 #endif
   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
- 8004e26:	2300      	movs	r3, #0
- 8004e28:	60fb      	str	r3, [r7, #12]
- 8004e2a:	2300      	movs	r3, #0
- 8004e2c:	60bb      	str	r3, [r7, #8]
- 8004e2e:	2300      	movs	r3, #0
- 8004e30:	617b      	str	r3, [r7, #20]
- 8004e32:	2300      	movs	r3, #0
- 8004e34:	607b      	str	r3, [r7, #4]
+ 800624e:	2300      	movs	r3, #0
+ 8006250:	60fb      	str	r3, [r7, #12]
+ 8006252:	2300      	movs	r3, #0
+ 8006254:	60bb      	str	r3, [r7, #8]
+ 8006256:	2300      	movs	r3, #0
+ 8006258:	617b      	str	r3, [r7, #20]
+ 800625a:	2300      	movs	r3, #0
+ 800625c:	607b      	str	r3, [r7, #4]
   uint32_t sysclockfreq = 0U;
- 8004e36:	2300      	movs	r3, #0
- 8004e38:	613b      	str	r3, [r7, #16]
+ 800625e:	2300      	movs	r3, #0
+ 8006260:	613b      	str	r3, [r7, #16]
 #if defined(RCC_CFGR2_PREDIV1SRC)
   uint32_t prediv2 = 0U, pll2mul = 0U;
 #endif /*RCC_CFGR2_PREDIV1SRC*/
 
   tmpreg = RCC->CFGR;
- 8004e3a:	4b1e      	ldr	r3, [pc, #120]	@ (8004eb4 <HAL_RCC_GetSysClockFreq+0x94>)
- 8004e3c:	685b      	ldr	r3, [r3, #4]
- 8004e3e:	60fb      	str	r3, [r7, #12]
+ 8006262:	4b1e      	ldr	r3, [pc, #120]	@ (80062dc <HAL_RCC_GetSysClockFreq+0x94>)
+ 8006264:	685b      	ldr	r3, [r3, #4]
+ 8006266:	60fb      	str	r3, [r7, #12]
 
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (tmpreg & RCC_CFGR_SWS)
- 8004e40:	68fb      	ldr	r3, [r7, #12]
- 8004e42:	f003 030c 	and.w	r3, r3, #12
- 8004e46:	2b04      	cmp	r3, #4
- 8004e48:	d002      	beq.n	8004e50 <HAL_RCC_GetSysClockFreq+0x30>
- 8004e4a:	2b08      	cmp	r3, #8
- 8004e4c:	d003      	beq.n	8004e56 <HAL_RCC_GetSysClockFreq+0x36>
- 8004e4e:	e027      	b.n	8004ea0 <HAL_RCC_GetSysClockFreq+0x80>
+ 8006268:	68fb      	ldr	r3, [r7, #12]
+ 800626a:	f003 030c 	and.w	r3, r3, #12
+ 800626e:	2b04      	cmp	r3, #4
+ 8006270:	d002      	beq.n	8006278 <HAL_RCC_GetSysClockFreq+0x30>
+ 8006272:	2b08      	cmp	r3, #8
+ 8006274:	d003      	beq.n	800627e <HAL_RCC_GetSysClockFreq+0x36>
+ 8006276:	e027      	b.n	80062c8 <HAL_RCC_GetSysClockFreq+0x80>
   {
     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
     {
       sysclockfreq = HSE_VALUE;
- 8004e50:	4b19      	ldr	r3, [pc, #100]	@ (8004eb8 <HAL_RCC_GetSysClockFreq+0x98>)
- 8004e52:	613b      	str	r3, [r7, #16]
+ 8006278:	4b19      	ldr	r3, [pc, #100]	@ (80062e0 <HAL_RCC_GetSysClockFreq+0x98>)
+ 800627a:	613b      	str	r3, [r7, #16]
       break;
- 8004e54:	e027      	b.n	8004ea6 <HAL_RCC_GetSysClockFreq+0x86>
+ 800627c:	e027      	b.n	80062ce <HAL_RCC_GetSysClockFreq+0x86>
     }
     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
     {
       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
- 8004e56:	68fb      	ldr	r3, [r7, #12]
- 8004e58:	0c9b      	lsrs	r3, r3, #18
- 8004e5a:	f003 030f 	and.w	r3, r3, #15
- 8004e5e:	4a17      	ldr	r2, [pc, #92]	@ (8004ebc <HAL_RCC_GetSysClockFreq+0x9c>)
- 8004e60:	5cd3      	ldrb	r3, [r2, r3]
- 8004e62:	607b      	str	r3, [r7, #4]
+ 800627e:	68fb      	ldr	r3, [r7, #12]
+ 8006280:	0c9b      	lsrs	r3, r3, #18
+ 8006282:	f003 030f 	and.w	r3, r3, #15
+ 8006286:	4a17      	ldr	r2, [pc, #92]	@ (80062e4 <HAL_RCC_GetSysClockFreq+0x9c>)
+ 8006288:	5cd3      	ldrb	r3, [r2, r3]
+ 800628a:	607b      	str	r3, [r7, #4]
       if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- 8004e64:	68fb      	ldr	r3, [r7, #12]
- 8004e66:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 8004e6a:	2b00      	cmp	r3, #0
- 8004e6c:	d010      	beq.n	8004e90 <HAL_RCC_GetSysClockFreq+0x70>
+ 800628c:	68fb      	ldr	r3, [r7, #12]
+ 800628e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8006292:	2b00      	cmp	r3, #0
+ 8006294:	d010      	beq.n	80062b8 <HAL_RCC_GetSysClockFreq+0x70>
       {
 #if defined(RCC_CFGR2_PREDIV1)
         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 #else
         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
- 8004e6e:	4b11      	ldr	r3, [pc, #68]	@ (8004eb4 <HAL_RCC_GetSysClockFreq+0x94>)
- 8004e70:	685b      	ldr	r3, [r3, #4]
- 8004e72:	0c5b      	lsrs	r3, r3, #17
- 8004e74:	f003 0301 	and.w	r3, r3, #1
- 8004e78:	4a11      	ldr	r2, [pc, #68]	@ (8004ec0 <HAL_RCC_GetSysClockFreq+0xa0>)
- 8004e7a:	5cd3      	ldrb	r3, [r2, r3]
- 8004e7c:	60bb      	str	r3, [r7, #8]
+ 8006296:	4b11      	ldr	r3, [pc, #68]	@ (80062dc <HAL_RCC_GetSysClockFreq+0x94>)
+ 8006298:	685b      	ldr	r3, [r3, #4]
+ 800629a:	0c5b      	lsrs	r3, r3, #17
+ 800629c:	f003 0301 	and.w	r3, r3, #1
+ 80062a0:	4a11      	ldr	r2, [pc, #68]	@ (80062e8 <HAL_RCC_GetSysClockFreq+0xa0>)
+ 80062a2:	5cd3      	ldrb	r3, [r2, r3]
+ 80062a4:	60bb      	str	r3, [r7, #8]
         {
           pllclk = pllclk / 2;
         }
 #else
         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
         pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
- 8004e7e:	687b      	ldr	r3, [r7, #4]
- 8004e80:	4a0d      	ldr	r2, [pc, #52]	@ (8004eb8 <HAL_RCC_GetSysClockFreq+0x98>)
- 8004e82:	fb03 f202 	mul.w	r2, r3, r2
- 8004e86:	68bb      	ldr	r3, [r7, #8]
- 8004e88:	fbb2 f3f3 	udiv	r3, r2, r3
- 8004e8c:	617b      	str	r3, [r7, #20]
- 8004e8e:	e004      	b.n	8004e9a <HAL_RCC_GetSysClockFreq+0x7a>
+ 80062a6:	687b      	ldr	r3, [r7, #4]
+ 80062a8:	4a0d      	ldr	r2, [pc, #52]	@ (80062e0 <HAL_RCC_GetSysClockFreq+0x98>)
+ 80062aa:	fb03 f202 	mul.w	r2, r3, r2
+ 80062ae:	68bb      	ldr	r3, [r7, #8]
+ 80062b0:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80062b4:	617b      	str	r3, [r7, #20]
+ 80062b6:	e004      	b.n	80062c2 <HAL_RCC_GetSysClockFreq+0x7a>
 #endif /*RCC_CFGR2_PREDIV1SRC*/
       }
       else
       {
         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
         pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
- 8004e90:	687b      	ldr	r3, [r7, #4]
- 8004e92:	4a0c      	ldr	r2, [pc, #48]	@ (8004ec4 <HAL_RCC_GetSysClockFreq+0xa4>)
- 8004e94:	fb02 f303 	mul.w	r3, r2, r3
- 8004e98:	617b      	str	r3, [r7, #20]
+ 80062b8:	687b      	ldr	r3, [r7, #4]
+ 80062ba:	4a0c      	ldr	r2, [pc, #48]	@ (80062ec <HAL_RCC_GetSysClockFreq+0xa4>)
+ 80062bc:	fb02 f303 	mul.w	r3, r2, r3
+ 80062c0:	617b      	str	r3, [r7, #20]
       }
       sysclockfreq = pllclk;
- 8004e9a:	697b      	ldr	r3, [r7, #20]
- 8004e9c:	613b      	str	r3, [r7, #16]
+ 80062c2:	697b      	ldr	r3, [r7, #20]
+ 80062c4:	613b      	str	r3, [r7, #16]
       break;
- 8004e9e:	e002      	b.n	8004ea6 <HAL_RCC_GetSysClockFreq+0x86>
+ 80062c6:	e002      	b.n	80062ce <HAL_RCC_GetSysClockFreq+0x86>
     }
     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
     default: /* HSI used as system clock */
     {
       sysclockfreq = HSI_VALUE;
- 8004ea0:	4b09      	ldr	r3, [pc, #36]	@ (8004ec8 <HAL_RCC_GetSysClockFreq+0xa8>)
- 8004ea2:	613b      	str	r3, [r7, #16]
+ 80062c8:	4b09      	ldr	r3, [pc, #36]	@ (80062f0 <HAL_RCC_GetSysClockFreq+0xa8>)
+ 80062ca:	613b      	str	r3, [r7, #16]
       break;
- 8004ea4:	bf00      	nop
+ 80062cc:	bf00      	nop
     }
   }
   return sysclockfreq;
- 8004ea6:	693b      	ldr	r3, [r7, #16]
+ 80062ce:	693b      	ldr	r3, [r7, #16]
 }
- 8004ea8:	4618      	mov	r0, r3
- 8004eaa:	371c      	adds	r7, #28
- 8004eac:	46bd      	mov	sp, r7
- 8004eae:	bc80      	pop	{r7}
- 8004eb0:	4770      	bx	lr
- 8004eb2:	bf00      	nop
- 8004eb4:	40021000 	.word	0x40021000
- 8004eb8:	00b71b00 	.word	0x00b71b00
- 8004ebc:	08005f4c 	.word	0x08005f4c
- 8004ec0:	08005f5c 	.word	0x08005f5c
- 8004ec4:	003d0900 	.word	0x003d0900
- 8004ec8:	007a1200 	.word	0x007a1200
+ 80062d0:	4618      	mov	r0, r3
+ 80062d2:	371c      	adds	r7, #28
+ 80062d4:	46bd      	mov	sp, r7
+ 80062d6:	bc80      	pop	{r7}
+ 80062d8:	4770      	bx	lr
+ 80062da:	bf00      	nop
+ 80062dc:	40021000 	.word	0x40021000
+ 80062e0:	00b71b00 	.word	0x00b71b00
+ 80062e4:	08007a78 	.word	0x08007a78
+ 80062e8:	08007a88 	.word	0x08007a88
+ 80062ec:	003d0900 	.word	0x003d0900
+ 80062f0:	007a1200 	.word	0x007a1200
 
-08004ecc <HAL_RCC_GetHCLKFreq>:
+080062f4 <HAL_RCC_GetHCLKFreq>:
   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated within this function
   * @retval HCLK frequency
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
- 8004ecc:	b480      	push	{r7}
- 8004ece:	af00      	add	r7, sp, #0
+ 80062f4:	b480      	push	{r7}
+ 80062f6:	af00      	add	r7, sp, #0
   return SystemCoreClock;
- 8004ed0:	4b02      	ldr	r3, [pc, #8]	@ (8004edc <HAL_RCC_GetHCLKFreq+0x10>)
- 8004ed2:	681b      	ldr	r3, [r3, #0]
+ 80062f8:	4b02      	ldr	r3, [pc, #8]	@ (8006304 <HAL_RCC_GetHCLKFreq+0x10>)
+ 80062fa:	681b      	ldr	r3, [r3, #0]
 }
- 8004ed4:	4618      	mov	r0, r3
- 8004ed6:	46bd      	mov	sp, r7
- 8004ed8:	bc80      	pop	{r7}
- 8004eda:	4770      	bx	lr
- 8004edc:	2000001c 	.word	0x2000001c
+ 80062fc:	4618      	mov	r0, r3
+ 80062fe:	46bd      	mov	sp, r7
+ 8006300:	bc80      	pop	{r7}
+ 8006302:	4770      	bx	lr
+ 8006304:	20000024 	.word	0x20000024
 
-08004ee0 <HAL_RCC_GetPCLK1Freq>:
+08006308 <HAL_RCC_GetPCLK1Freq>:
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
   */
 uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
- 8004ee0:	b580      	push	{r7, lr}
- 8004ee2:	af00      	add	r7, sp, #0
+ 8006308:	b580      	push	{r7, lr}
+ 800630a:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
- 8004ee4:	f7ff fff2 	bl	8004ecc <HAL_RCC_GetHCLKFreq>
- 8004ee8:	4602      	mov	r2, r0
- 8004eea:	4b05      	ldr	r3, [pc, #20]	@ (8004f00 <HAL_RCC_GetPCLK1Freq+0x20>)
- 8004eec:	685b      	ldr	r3, [r3, #4]
- 8004eee:	0a1b      	lsrs	r3, r3, #8
- 8004ef0:	f003 0307 	and.w	r3, r3, #7
- 8004ef4:	4903      	ldr	r1, [pc, #12]	@ (8004f04 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8004ef6:	5ccb      	ldrb	r3, [r1, r3]
- 8004ef8:	fa22 f303 	lsr.w	r3, r2, r3
+ 800630c:	f7ff fff2 	bl	80062f4 <HAL_RCC_GetHCLKFreq>
+ 8006310:	4602      	mov	r2, r0
+ 8006312:	4b05      	ldr	r3, [pc, #20]	@ (8006328 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 8006314:	685b      	ldr	r3, [r3, #4]
+ 8006316:	0a1b      	lsrs	r3, r3, #8
+ 8006318:	f003 0307 	and.w	r3, r3, #7
+ 800631c:	4903      	ldr	r1, [pc, #12]	@ (800632c <HAL_RCC_GetPCLK1Freq+0x24>)
+ 800631e:	5ccb      	ldrb	r3, [r1, r3]
+ 8006320:	fa22 f303 	lsr.w	r3, r2, r3
 }
- 8004efc:	4618      	mov	r0, r3
- 8004efe:	bd80      	pop	{r7, pc}
- 8004f00:	40021000 	.word	0x40021000
- 8004f04:	08005f44 	.word	0x08005f44
+ 8006324:	4618      	mov	r0, r3
+ 8006326:	bd80      	pop	{r7, pc}
+ 8006328:	40021000 	.word	0x40021000
+ 800632c:	08007a70 	.word	0x08007a70
 
-08004f08 <HAL_RCC_GetPCLK2Freq>:
+08006330 <HAL_RCC_GetPCLK2Freq>:
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK2 frequency
   */
 uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
- 8004f08:	b580      	push	{r7, lr}
- 8004f0a:	af00      	add	r7, sp, #0
+ 8006330:	b580      	push	{r7, lr}
+ 8006332:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
- 8004f0c:	f7ff ffde 	bl	8004ecc <HAL_RCC_GetHCLKFreq>
- 8004f10:	4602      	mov	r2, r0
- 8004f12:	4b05      	ldr	r3, [pc, #20]	@ (8004f28 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8004f14:	685b      	ldr	r3, [r3, #4]
- 8004f16:	0adb      	lsrs	r3, r3, #11
- 8004f18:	f003 0307 	and.w	r3, r3, #7
- 8004f1c:	4903      	ldr	r1, [pc, #12]	@ (8004f2c <HAL_RCC_GetPCLK2Freq+0x24>)
- 8004f1e:	5ccb      	ldrb	r3, [r1, r3]
- 8004f20:	fa22 f303 	lsr.w	r3, r2, r3
+ 8006334:	f7ff ffde 	bl	80062f4 <HAL_RCC_GetHCLKFreq>
+ 8006338:	4602      	mov	r2, r0
+ 800633a:	4b05      	ldr	r3, [pc, #20]	@ (8006350 <HAL_RCC_GetPCLK2Freq+0x20>)
+ 800633c:	685b      	ldr	r3, [r3, #4]
+ 800633e:	0adb      	lsrs	r3, r3, #11
+ 8006340:	f003 0307 	and.w	r3, r3, #7
+ 8006344:	4903      	ldr	r1, [pc, #12]	@ (8006354 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8006346:	5ccb      	ldrb	r3, [r1, r3]
+ 8006348:	fa22 f303 	lsr.w	r3, r2, r3
 }
- 8004f24:	4618      	mov	r0, r3
- 8004f26:	bd80      	pop	{r7, pc}
- 8004f28:	40021000 	.word	0x40021000
- 8004f2c:	08005f44 	.word	0x08005f44
+ 800634c:	4618      	mov	r0, r3
+ 800634e:	bd80      	pop	{r7, pc}
+ 8006350:	40021000 	.word	0x40021000
+ 8006354:	08007a70 	.word	0x08007a70
 
-08004f30 <RCC_Delay>:
+08006358 <RCC_Delay>:
   * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
   * @param  mdelay: specifies the delay time length, in milliseconds.
   * @retval None
   */
 static void RCC_Delay(uint32_t mdelay)
 {
- 8004f30:	b480      	push	{r7}
- 8004f32:	b085      	sub	sp, #20
- 8004f34:	af00      	add	r7, sp, #0
- 8004f36:	6078      	str	r0, [r7, #4]
+ 8006358:	b480      	push	{r7}
+ 800635a:	b085      	sub	sp, #20
+ 800635c:	af00      	add	r7, sp, #0
+ 800635e:	6078      	str	r0, [r7, #4]
   __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
- 8004f38:	4b0a      	ldr	r3, [pc, #40]	@ (8004f64 <RCC_Delay+0x34>)
- 8004f3a:	681b      	ldr	r3, [r3, #0]
- 8004f3c:	4a0a      	ldr	r2, [pc, #40]	@ (8004f68 <RCC_Delay+0x38>)
- 8004f3e:	fba2 2303 	umull	r2, r3, r2, r3
- 8004f42:	0a5b      	lsrs	r3, r3, #9
- 8004f44:	687a      	ldr	r2, [r7, #4]
- 8004f46:	fb02 f303 	mul.w	r3, r2, r3
- 8004f4a:	60fb      	str	r3, [r7, #12]
+ 8006360:	4b0a      	ldr	r3, [pc, #40]	@ (800638c <RCC_Delay+0x34>)
+ 8006362:	681b      	ldr	r3, [r3, #0]
+ 8006364:	4a0a      	ldr	r2, [pc, #40]	@ (8006390 <RCC_Delay+0x38>)
+ 8006366:	fba2 2303 	umull	r2, r3, r2, r3
+ 800636a:	0a5b      	lsrs	r3, r3, #9
+ 800636c:	687a      	ldr	r2, [r7, #4]
+ 800636e:	fb02 f303 	mul.w	r3, r2, r3
+ 8006372:	60fb      	str	r3, [r7, #12]
   do
   {
     __NOP();
- 8004f4c:	bf00      	nop
+ 8006374:	bf00      	nop
   }
   while (Delay --);
- 8004f4e:	68fb      	ldr	r3, [r7, #12]
- 8004f50:	1e5a      	subs	r2, r3, #1
- 8004f52:	60fa      	str	r2, [r7, #12]
- 8004f54:	2b00      	cmp	r3, #0
- 8004f56:	d1f9      	bne.n	8004f4c <RCC_Delay+0x1c>
+ 8006376:	68fb      	ldr	r3, [r7, #12]
+ 8006378:	1e5a      	subs	r2, r3, #1
+ 800637a:	60fa      	str	r2, [r7, #12]
+ 800637c:	2b00      	cmp	r3, #0
+ 800637e:	d1f9      	bne.n	8006374 <RCC_Delay+0x1c>
 }
- 8004f58:	bf00      	nop
- 8004f5a:	bf00      	nop
- 8004f5c:	3714      	adds	r7, #20
- 8004f5e:	46bd      	mov	sp, r7
- 8004f60:	bc80      	pop	{r7}
- 8004f62:	4770      	bx	lr
- 8004f64:	2000001c 	.word	0x2000001c
- 8004f68:	10624dd3 	.word	0x10624dd3
+ 8006380:	bf00      	nop
+ 8006382:	bf00      	nop
+ 8006384:	3714      	adds	r7, #20
+ 8006386:	46bd      	mov	sp, r7
+ 8006388:	bc80      	pop	{r7}
+ 800638a:	4770      	bx	lr
+ 800638c:	20000024 	.word	0x20000024
+ 8006390:	10624dd3 	.word	0x10624dd3
 
-08004f6c <HAL_RCCEx_PeriphCLKConfig>:
+08006394 <HAL_RCCEx_PeriphCLKConfig>:
   *         manually disable it.
   *
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
- 8004f6c:	b580      	push	{r7, lr}
- 8004f6e:	b086      	sub	sp, #24
- 8004f70:	af00      	add	r7, sp, #0
- 8004f72:	6078      	str	r0, [r7, #4]
+ 8006394:	b580      	push	{r7, lr}
+ 8006396:	b086      	sub	sp, #24
+ 8006398:	af00      	add	r7, sp, #0
+ 800639a:	6078      	str	r0, [r7, #4]
   uint32_t tickstart = 0U, temp_reg = 0U;
- 8004f74:	2300      	movs	r3, #0
- 8004f76:	613b      	str	r3, [r7, #16]
- 8004f78:	2300      	movs	r3, #0
- 8004f7a:	60fb      	str	r3, [r7, #12]
+ 800639c:	2300      	movs	r3, #0
+ 800639e:	613b      	str	r3, [r7, #16]
+ 80063a0:	2300      	movs	r3, #0
+ 80063a2:	60fb      	str	r3, [r7, #12]
 
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 
   /*------------------------------- RTC/LCD Configuration ------------------------*/
   if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
- 8004f7c:	687b      	ldr	r3, [r7, #4]
- 8004f7e:	681b      	ldr	r3, [r3, #0]
- 8004f80:	f003 0301 	and.w	r3, r3, #1
- 8004f84:	2b00      	cmp	r3, #0
- 8004f86:	d07d      	beq.n	8005084 <HAL_RCCEx_PeriphCLKConfig+0x118>
+ 80063a4:	687b      	ldr	r3, [r7, #4]
+ 80063a6:	681b      	ldr	r3, [r3, #0]
+ 80063a8:	f003 0301 	and.w	r3, r3, #1
+ 80063ac:	2b00      	cmp	r3, #0
+ 80063ae:	d07d      	beq.n	80064ac <HAL_RCCEx_PeriphCLKConfig+0x118>
   {
     FlagStatus pwrclkchanged = RESET;
- 8004f88:	2300      	movs	r3, #0
- 8004f8a:	75fb      	strb	r3, [r7, #23]
+ 80063b0:	2300      	movs	r3, #0
+ 80063b2:	75fb      	strb	r3, [r7, #23]
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 
     /* As soon as function is called to change RTC clock source, activation of the
        power domain is done. */
     /* Requires to enable write access to Backup Domain of necessary */
     if (__HAL_RCC_PWR_IS_CLK_DISABLED())
- 8004f8c:	4b4f      	ldr	r3, [pc, #316]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8004f8e:	69db      	ldr	r3, [r3, #28]
- 8004f90:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 8004f94:	2b00      	cmp	r3, #0
- 8004f96:	d10d      	bne.n	8004fb4 <HAL_RCCEx_PeriphCLKConfig+0x48>
+ 80063b4:	4b4f      	ldr	r3, [pc, #316]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80063b6:	69db      	ldr	r3, [r3, #28]
+ 80063b8:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 80063bc:	2b00      	cmp	r3, #0
+ 80063be:	d10d      	bne.n	80063dc <HAL_RCCEx_PeriphCLKConfig+0x48>
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 8004f98:	4b4c      	ldr	r3, [pc, #304]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8004f9a:	69db      	ldr	r3, [r3, #28]
- 8004f9c:	4a4b      	ldr	r2, [pc, #300]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8004f9e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 8004fa2:	61d3      	str	r3, [r2, #28]
- 8004fa4:	4b49      	ldr	r3, [pc, #292]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8004fa6:	69db      	ldr	r3, [r3, #28]
- 8004fa8:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 8004fac:	60bb      	str	r3, [r7, #8]
- 8004fae:	68bb      	ldr	r3, [r7, #8]
+ 80063c0:	4b4c      	ldr	r3, [pc, #304]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80063c2:	69db      	ldr	r3, [r3, #28]
+ 80063c4:	4a4b      	ldr	r2, [pc, #300]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80063c6:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 80063ca:	61d3      	str	r3, [r2, #28]
+ 80063cc:	4b49      	ldr	r3, [pc, #292]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80063ce:	69db      	ldr	r3, [r3, #28]
+ 80063d0:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 80063d4:	60bb      	str	r3, [r7, #8]
+ 80063d6:	68bb      	ldr	r3, [r7, #8]
       pwrclkchanged = SET;
- 8004fb0:	2301      	movs	r3, #1
- 8004fb2:	75fb      	strb	r3, [r7, #23]
+ 80063d8:	2301      	movs	r3, #1
+ 80063da:	75fb      	strb	r3, [r7, #23]
     }
 
     if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004fb4:	4b46      	ldr	r3, [pc, #280]	@ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
- 8004fb6:	681b      	ldr	r3, [r3, #0]
- 8004fb8:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 8004fbc:	2b00      	cmp	r3, #0
- 8004fbe:	d118      	bne.n	8004ff2 <HAL_RCCEx_PeriphCLKConfig+0x86>
+ 80063dc:	4b46      	ldr	r3, [pc, #280]	@ (80064f8 <HAL_RCCEx_PeriphCLKConfig+0x164>)
+ 80063de:	681b      	ldr	r3, [r3, #0]
+ 80063e0:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80063e4:	2b00      	cmp	r3, #0
+ 80063e6:	d118      	bne.n	800641a <HAL_RCCEx_PeriphCLKConfig+0x86>
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
- 8004fc0:	4b43      	ldr	r3, [pc, #268]	@ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
- 8004fc2:	681b      	ldr	r3, [r3, #0]
- 8004fc4:	4a42      	ldr	r2, [pc, #264]	@ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
- 8004fc6:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
- 8004fca:	6013      	str	r3, [r2, #0]
+ 80063e8:	4b43      	ldr	r3, [pc, #268]	@ (80064f8 <HAL_RCCEx_PeriphCLKConfig+0x164>)
+ 80063ea:	681b      	ldr	r3, [r3, #0]
+ 80063ec:	4a42      	ldr	r2, [pc, #264]	@ (80064f8 <HAL_RCCEx_PeriphCLKConfig+0x164>)
+ 80063ee:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 80063f2:	6013      	str	r3, [r2, #0]
 
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
- 8004fcc:	f7fd fdbc 	bl	8002b48 <HAL_GetTick>
- 8004fd0:	6138      	str	r0, [r7, #16]
+ 80063f4:	f7fc ff6e 	bl	80032d4 <HAL_GetTick>
+ 80063f8:	6138      	str	r0, [r7, #16]
 
       while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004fd2:	e008      	b.n	8004fe6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
+ 80063fa:	e008      	b.n	800640e <HAL_RCCEx_PeriphCLKConfig+0x7a>
       {
         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8004fd4:	f7fd fdb8 	bl	8002b48 <HAL_GetTick>
- 8004fd8:	4602      	mov	r2, r0
- 8004fda:	693b      	ldr	r3, [r7, #16]
- 8004fdc:	1ad3      	subs	r3, r2, r3
- 8004fde:	2b64      	cmp	r3, #100	@ 0x64
- 8004fe0:	d901      	bls.n	8004fe6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
+ 80063fc:	f7fc ff6a 	bl	80032d4 <HAL_GetTick>
+ 8006400:	4602      	mov	r2, r0
+ 8006402:	693b      	ldr	r3, [r7, #16]
+ 8006404:	1ad3      	subs	r3, r2, r3
+ 8006406:	2b64      	cmp	r3, #100	@ 0x64
+ 8006408:	d901      	bls.n	800640e <HAL_RCCEx_PeriphCLKConfig+0x7a>
         {
           return HAL_TIMEOUT;
- 8004fe2:	2303      	movs	r3, #3
- 8004fe4:	e06d      	b.n	80050c2 <HAL_RCCEx_PeriphCLKConfig+0x156>
+ 800640a:	2303      	movs	r3, #3
+ 800640c:	e06d      	b.n	80064ea <HAL_RCCEx_PeriphCLKConfig+0x156>
       while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8004fe6:	4b3a      	ldr	r3, [pc, #232]	@ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
- 8004fe8:	681b      	ldr	r3, [r3, #0]
- 8004fea:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 8004fee:	2b00      	cmp	r3, #0
- 8004ff0:	d0f0      	beq.n	8004fd4 <HAL_RCCEx_PeriphCLKConfig+0x68>
+ 800640e:	4b3a      	ldr	r3, [pc, #232]	@ (80064f8 <HAL_RCCEx_PeriphCLKConfig+0x164>)
+ 8006410:	681b      	ldr	r3, [r3, #0]
+ 8006412:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8006416:	2b00      	cmp	r3, #0
+ 8006418:	d0f0      	beq.n	80063fc <HAL_RCCEx_PeriphCLKConfig+0x68>
         }
       }
     }
 
     /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
     temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8004ff2:	4b36      	ldr	r3, [pc, #216]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8004ff4:	6a1b      	ldr	r3, [r3, #32]
- 8004ff6:	f403 7340 	and.w	r3, r3, #768	@ 0x300
- 8004ffa:	60fb      	str	r3, [r7, #12]
+ 800641a:	4b36      	ldr	r3, [pc, #216]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 800641c:	6a1b      	ldr	r3, [r3, #32]
+ 800641e:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 8006422:	60fb      	str	r3, [r7, #12]
     if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8004ffc:	68fb      	ldr	r3, [r7, #12]
- 8004ffe:	2b00      	cmp	r3, #0
- 8005000:	d02e      	beq.n	8005060 <HAL_RCCEx_PeriphCLKConfig+0xf4>
- 8005002:	687b      	ldr	r3, [r7, #4]
- 8005004:	685b      	ldr	r3, [r3, #4]
- 8005006:	f403 7340 	and.w	r3, r3, #768	@ 0x300
- 800500a:	68fa      	ldr	r2, [r7, #12]
- 800500c:	429a      	cmp	r2, r3
- 800500e:	d027      	beq.n	8005060 <HAL_RCCEx_PeriphCLKConfig+0xf4>
+ 8006424:	68fb      	ldr	r3, [r7, #12]
+ 8006426:	2b00      	cmp	r3, #0
+ 8006428:	d02e      	beq.n	8006488 <HAL_RCCEx_PeriphCLKConfig+0xf4>
+ 800642a:	687b      	ldr	r3, [r7, #4]
+ 800642c:	685b      	ldr	r3, [r3, #4]
+ 800642e:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 8006432:	68fa      	ldr	r2, [r7, #12]
+ 8006434:	429a      	cmp	r2, r3
+ 8006436:	d027      	beq.n	8006488 <HAL_RCCEx_PeriphCLKConfig+0xf4>
     {
       /* Store the content of BDCR register before the reset of Backup Domain */
       temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8005010:	4b2e      	ldr	r3, [pc, #184]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8005012:	6a1b      	ldr	r3, [r3, #32]
- 8005014:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
- 8005018:	60fb      	str	r3, [r7, #12]
+ 8006438:	4b2e      	ldr	r3, [pc, #184]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 800643a:	6a1b      	ldr	r3, [r3, #32]
+ 800643c:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
+ 8006440:	60fb      	str	r3, [r7, #12]
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
       __HAL_RCC_BACKUPRESET_FORCE();
- 800501a:	4b2e      	ldr	r3, [pc, #184]	@ (80050d4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
- 800501c:	2201      	movs	r2, #1
- 800501e:	601a      	str	r2, [r3, #0]
+ 8006442:	4b2e      	ldr	r3, [pc, #184]	@ (80064fc <HAL_RCCEx_PeriphCLKConfig+0x168>)
+ 8006444:	2201      	movs	r2, #1
+ 8006446:	601a      	str	r2, [r3, #0]
       __HAL_RCC_BACKUPRESET_RELEASE();
- 8005020:	4b2c      	ldr	r3, [pc, #176]	@ (80050d4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
- 8005022:	2200      	movs	r2, #0
- 8005024:	601a      	str	r2, [r3, #0]
+ 8006448:	4b2c      	ldr	r3, [pc, #176]	@ (80064fc <HAL_RCCEx_PeriphCLKConfig+0x168>)
+ 800644a:	2200      	movs	r2, #0
+ 800644c:	601a      	str	r2, [r3, #0]
       /* Restore the Content of BDCR register */
       RCC->BDCR = temp_reg;
- 8005026:	4a29      	ldr	r2, [pc, #164]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8005028:	68fb      	ldr	r3, [r7, #12]
- 800502a:	6213      	str	r3, [r2, #32]
+ 800644e:	4a29      	ldr	r2, [pc, #164]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 8006450:	68fb      	ldr	r3, [r7, #12]
+ 8006452:	6213      	str	r3, [r2, #32]
 
       /* Wait for LSERDY if LSE was enabled */
       if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
- 800502c:	68fb      	ldr	r3, [r7, #12]
- 800502e:	f003 0301 	and.w	r3, r3, #1
- 8005032:	2b00      	cmp	r3, #0
- 8005034:	d014      	beq.n	8005060 <HAL_RCCEx_PeriphCLKConfig+0xf4>
+ 8006454:	68fb      	ldr	r3, [r7, #12]
+ 8006456:	f003 0301 	and.w	r3, r3, #1
+ 800645a:	2b00      	cmp	r3, #0
+ 800645c:	d014      	beq.n	8006488 <HAL_RCCEx_PeriphCLKConfig+0xf4>
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8005036:	f7fd fd87 	bl	8002b48 <HAL_GetTick>
- 800503a:	6138      	str	r0, [r7, #16]
+ 800645e:	f7fc ff39 	bl	80032d4 <HAL_GetTick>
+ 8006462:	6138      	str	r0, [r7, #16]
 
         /* Wait till LSE is ready */
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 800503c:	e00a      	b.n	8005054 <HAL_RCCEx_PeriphCLKConfig+0xe8>
+ 8006464:	e00a      	b.n	800647c <HAL_RCCEx_PeriphCLKConfig+0xe8>
         {
           if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 800503e:	f7fd fd83 	bl	8002b48 <HAL_GetTick>
- 8005042:	4602      	mov	r2, r0
- 8005044:	693b      	ldr	r3, [r7, #16]
- 8005046:	1ad3      	subs	r3, r2, r3
- 8005048:	f241 3288 	movw	r2, #5000	@ 0x1388
- 800504c:	4293      	cmp	r3, r2
- 800504e:	d901      	bls.n	8005054 <HAL_RCCEx_PeriphCLKConfig+0xe8>
+ 8006466:	f7fc ff35 	bl	80032d4 <HAL_GetTick>
+ 800646a:	4602      	mov	r2, r0
+ 800646c:	693b      	ldr	r3, [r7, #16]
+ 800646e:	1ad3      	subs	r3, r2, r3
+ 8006470:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 8006474:	4293      	cmp	r3, r2
+ 8006476:	d901      	bls.n	800647c <HAL_RCCEx_PeriphCLKConfig+0xe8>
           {
             return HAL_TIMEOUT;
- 8005050:	2303      	movs	r3, #3
- 8005052:	e036      	b.n	80050c2 <HAL_RCCEx_PeriphCLKConfig+0x156>
+ 8006478:	2303      	movs	r3, #3
+ 800647a:	e036      	b.n	80064ea <HAL_RCCEx_PeriphCLKConfig+0x156>
         while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8005054:	4b1d      	ldr	r3, [pc, #116]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8005056:	6a1b      	ldr	r3, [r3, #32]
- 8005058:	f003 0302 	and.w	r3, r3, #2
- 800505c:	2b00      	cmp	r3, #0
- 800505e:	d0ee      	beq.n	800503e <HAL_RCCEx_PeriphCLKConfig+0xd2>
+ 800647c:	4b1d      	ldr	r3, [pc, #116]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 800647e:	6a1b      	ldr	r3, [r3, #32]
+ 8006480:	f003 0302 	and.w	r3, r3, #2
+ 8006484:	2b00      	cmp	r3, #0
+ 8006486:	d0ee      	beq.n	8006466 <HAL_RCCEx_PeriphCLKConfig+0xd2>
           }
         }
       }
     }
     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8005060:	4b1a      	ldr	r3, [pc, #104]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8005062:	6a1b      	ldr	r3, [r3, #32]
- 8005064:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
- 8005068:	687b      	ldr	r3, [r7, #4]
- 800506a:	685b      	ldr	r3, [r3, #4]
- 800506c:	4917      	ldr	r1, [pc, #92]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 800506e:	4313      	orrs	r3, r2
- 8005070:	620b      	str	r3, [r1, #32]
+ 8006488:	4b1a      	ldr	r3, [pc, #104]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 800648a:	6a1b      	ldr	r3, [r3, #32]
+ 800648c:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
+ 8006490:	687b      	ldr	r3, [r7, #4]
+ 8006492:	685b      	ldr	r3, [r3, #4]
+ 8006494:	4917      	ldr	r1, [pc, #92]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 8006496:	4313      	orrs	r3, r2
+ 8006498:	620b      	str	r3, [r1, #32]
 
     /* Require to disable power clock if necessary */
     if (pwrclkchanged == SET)
- 8005072:	7dfb      	ldrb	r3, [r7, #23]
- 8005074:	2b01      	cmp	r3, #1
- 8005076:	d105      	bne.n	8005084 <HAL_RCCEx_PeriphCLKConfig+0x118>
+ 800649a:	7dfb      	ldrb	r3, [r7, #23]
+ 800649c:	2b01      	cmp	r3, #1
+ 800649e:	d105      	bne.n	80064ac <HAL_RCCEx_PeriphCLKConfig+0x118>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 8005078:	4b14      	ldr	r3, [pc, #80]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 800507a:	69db      	ldr	r3, [r3, #28]
- 800507c:	4a13      	ldr	r2, [pc, #76]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 800507e:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
- 8005082:	61d3      	str	r3, [r2, #28]
+ 80064a0:	4b14      	ldr	r3, [pc, #80]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064a2:	69db      	ldr	r3, [r3, #28]
+ 80064a4:	4a13      	ldr	r2, [pc, #76]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064a6:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 80064aa:	61d3      	str	r3, [r2, #28]
     }
   }
 
   /*------------------------------ ADC clock Configuration ------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- 8005084:	687b      	ldr	r3, [r7, #4]
- 8005086:	681b      	ldr	r3, [r3, #0]
- 8005088:	f003 0302 	and.w	r3, r3, #2
- 800508c:	2b00      	cmp	r3, #0
- 800508e:	d008      	beq.n	80050a2 <HAL_RCCEx_PeriphCLKConfig+0x136>
+ 80064ac:	687b      	ldr	r3, [r7, #4]
+ 80064ae:	681b      	ldr	r3, [r3, #0]
+ 80064b0:	f003 0302 	and.w	r3, r3, #2
+ 80064b4:	2b00      	cmp	r3, #0
+ 80064b6:	d008      	beq.n	80064ca <HAL_RCCEx_PeriphCLKConfig+0x136>
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
 
     /* Configure the ADC clock source */
     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
- 8005090:	4b0e      	ldr	r3, [pc, #56]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 8005092:	685b      	ldr	r3, [r3, #4]
- 8005094:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
- 8005098:	687b      	ldr	r3, [r7, #4]
- 800509a:	689b      	ldr	r3, [r3, #8]
- 800509c:	490b      	ldr	r1, [pc, #44]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 800509e:	4313      	orrs	r3, r2
- 80050a0:	604b      	str	r3, [r1, #4]
+ 80064b8:	4b0e      	ldr	r3, [pc, #56]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064ba:	685b      	ldr	r3, [r3, #4]
+ 80064bc:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
+ 80064c0:	687b      	ldr	r3, [r7, #4]
+ 80064c2:	689b      	ldr	r3, [r3, #8]
+ 80064c4:	490b      	ldr	r1, [pc, #44]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064c6:	4313      	orrs	r3, r2
+ 80064c8:	604b      	str	r3, [r1, #4]
 
 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
  || defined(STM32F105xC) || defined(STM32F107xC)
   /*------------------------------ USB clock Configuration ------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
- 80050a2:	687b      	ldr	r3, [r7, #4]
- 80050a4:	681b      	ldr	r3, [r3, #0]
- 80050a6:	f003 0310 	and.w	r3, r3, #16
- 80050aa:	2b00      	cmp	r3, #0
- 80050ac:	d008      	beq.n	80050c0 <HAL_RCCEx_PeriphCLKConfig+0x154>
+ 80064ca:	687b      	ldr	r3, [r7, #4]
+ 80064cc:	681b      	ldr	r3, [r3, #0]
+ 80064ce:	f003 0310 	and.w	r3, r3, #16
+ 80064d2:	2b00      	cmp	r3, #0
+ 80064d4:	d008      	beq.n	80064e8 <HAL_RCCEx_PeriphCLKConfig+0x154>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
 
     /* Configure the USB clock source */
     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
- 80050ae:	4b07      	ldr	r3, [pc, #28]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 80050b0:	685b      	ldr	r3, [r3, #4]
- 80050b2:	f423 0280 	bic.w	r2, r3, #4194304	@ 0x400000
- 80050b6:	687b      	ldr	r3, [r7, #4]
- 80050b8:	68db      	ldr	r3, [r3, #12]
- 80050ba:	4904      	ldr	r1, [pc, #16]	@ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x160>)
- 80050bc:	4313      	orrs	r3, r2
- 80050be:	604b      	str	r3, [r1, #4]
+ 80064d6:	4b07      	ldr	r3, [pc, #28]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064d8:	685b      	ldr	r3, [r3, #4]
+ 80064da:	f423 0280 	bic.w	r2, r3, #4194304	@ 0x400000
+ 80064de:	687b      	ldr	r3, [r7, #4]
+ 80064e0:	68db      	ldr	r3, [r3, #12]
+ 80064e2:	4904      	ldr	r1, [pc, #16]	@ (80064f4 <HAL_RCCEx_PeriphCLKConfig+0x160>)
+ 80064e4:	4313      	orrs	r3, r2
+ 80064e6:	604b      	str	r3, [r1, #4]
   }
 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 
   return HAL_OK;
- 80050c0:	2300      	movs	r3, #0
+ 80064e8:	2300      	movs	r3, #0
 }
- 80050c2:	4618      	mov	r0, r3
- 80050c4:	3718      	adds	r7, #24
- 80050c6:	46bd      	mov	sp, r7
- 80050c8:	bd80      	pop	{r7, pc}
- 80050ca:	bf00      	nop
- 80050cc:	40021000 	.word	0x40021000
- 80050d0:	40007000 	.word	0x40007000
- 80050d4:	42420440 	.word	0x42420440
+ 80064ea:	4618      	mov	r0, r3
+ 80064ec:	3718      	adds	r7, #24
+ 80064ee:	46bd      	mov	sp, r7
+ 80064f0:	bd80      	pop	{r7, pc}
+ 80064f2:	bf00      	nop
+ 80064f4:	40021000 	.word	0x40021000
+ 80064f8:	40007000 	.word	0x40007000
+ 80064fc:	42420440 	.word	0x42420440
 
-080050d8 <HAL_UART_Init>:
+08006500 <HAL_RCCEx_GetPeriphCLKFreq>:
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
+  @endif
+  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ 8006500:	b580      	push	{r7, lr}
+ 8006502:	b088      	sub	sp, #32
+ 8006504:	af00      	add	r7, sp, #0
+ 8006506:	6078      	str	r0, [r7, #4]
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
+    defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+  static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+  static const uint8_t aPredivFactorTable[2U] = {1, 2};
+
+  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
+ 8006508:	2300      	movs	r3, #0
+ 800650a:	617b      	str	r3, [r7, #20]
+ 800650c:	2300      	movs	r3, #0
+ 800650e:	61fb      	str	r3, [r7, #28]
+ 8006510:	2300      	movs	r3, #0
+ 8006512:	613b      	str	r3, [r7, #16]
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+  uint32_t temp_reg = 0U, frequency = 0U;
+ 8006514:	2300      	movs	r3, #0
+ 8006516:	60fb      	str	r3, [r7, #12]
+ 8006518:	2300      	movs	r3, #0
+ 800651a:	61bb      	str	r3, [r7, #24]
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+  switch (PeriphClk)
+ 800651c:	687b      	ldr	r3, [r7, #4]
+ 800651e:	2b10      	cmp	r3, #16
+ 8006520:	d00a      	beq.n	8006538 <HAL_RCCEx_GetPeriphCLKFreq+0x38>
+ 8006522:	687b      	ldr	r3, [r7, #4]
+ 8006524:	2b10      	cmp	r3, #16
+ 8006526:	f200 8089 	bhi.w	800663c <HAL_RCCEx_GetPeriphCLKFreq+0x13c>
+ 800652a:	687b      	ldr	r3, [r7, #4]
+ 800652c:	2b01      	cmp	r3, #1
+ 800652e:	d045      	beq.n	80065bc <HAL_RCCEx_GetPeriphCLKFreq+0xbc>
+ 8006530:	687b      	ldr	r3, [r7, #4]
+ 8006532:	2b02      	cmp	r3, #2
+ 8006534:	d074      	beq.n	8006620 <HAL_RCCEx_GetPeriphCLKFreq+0x120>
+      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
+      break;
+    }
+    default:
+    {
+      break;
+ 8006536:	e081      	b.n	800663c <HAL_RCCEx_GetPeriphCLKFreq+0x13c>
+      temp_reg = RCC->CFGR;
+ 8006538:	4b45      	ldr	r3, [pc, #276]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 800653a:	685b      	ldr	r3, [r3, #4]
+ 800653c:	60fb      	str	r3, [r7, #12]
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON))
+ 800653e:	4b44      	ldr	r3, [pc, #272]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 8006540:	681b      	ldr	r3, [r3, #0]
+ 8006542:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 8006546:	2b00      	cmp	r3, #0
+ 8006548:	d07a      	beq.n	8006640 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
+        pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
+ 800654a:	68fb      	ldr	r3, [r7, #12]
+ 800654c:	0c9b      	lsrs	r3, r3, #18
+ 800654e:	f003 030f 	and.w	r3, r3, #15
+ 8006552:	4a40      	ldr	r2, [pc, #256]	@ (8006654 <HAL_RCCEx_GetPeriphCLKFreq+0x154>)
+ 8006554:	5cd3      	ldrb	r3, [r2, r3]
+ 8006556:	613b      	str	r3, [r7, #16]
+        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ 8006558:	68fb      	ldr	r3, [r7, #12]
+ 800655a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 800655e:	2b00      	cmp	r3, #0
+ 8006560:	d015      	beq.n	800658e <HAL_RCCEx_GetPeriphCLKFreq+0x8e>
+          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
+ 8006562:	4b3b      	ldr	r3, [pc, #236]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 8006564:	685b      	ldr	r3, [r3, #4]
+ 8006566:	0c5b      	lsrs	r3, r3, #17
+ 8006568:	f003 0301 	and.w	r3, r3, #1
+ 800656c:	4a3a      	ldr	r2, [pc, #232]	@ (8006658 <HAL_RCCEx_GetPeriphCLKFreq+0x158>)
+ 800656e:	5cd3      	ldrb	r3, [r2, r3]
+ 8006570:	617b      	str	r3, [r7, #20]
+          if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ 8006572:	68fb      	ldr	r3, [r7, #12]
+ 8006574:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8006578:	2b00      	cmp	r3, #0
+ 800657a:	d00d      	beq.n	8006598 <HAL_RCCEx_GetPeriphCLKFreq+0x98>
+            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ 800657c:	4a37      	ldr	r2, [pc, #220]	@ (800665c <HAL_RCCEx_GetPeriphCLKFreq+0x15c>)
+ 800657e:	697b      	ldr	r3, [r7, #20]
+ 8006580:	fbb2 f2f3 	udiv	r2, r2, r3
+ 8006584:	693b      	ldr	r3, [r7, #16]
+ 8006586:	fb02 f303 	mul.w	r3, r2, r3
+ 800658a:	61fb      	str	r3, [r7, #28]
+ 800658c:	e004      	b.n	8006598 <HAL_RCCEx_GetPeriphCLKFreq+0x98>
+          pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ 800658e:	693b      	ldr	r3, [r7, #16]
+ 8006590:	4a33      	ldr	r2, [pc, #204]	@ (8006660 <HAL_RCCEx_GetPeriphCLKFreq+0x160>)
+ 8006592:	fb02 f303 	mul.w	r3, r2, r3
+ 8006596:	61fb      	str	r3, [r7, #28]
+        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
+ 8006598:	4b2d      	ldr	r3, [pc, #180]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 800659a:	685b      	ldr	r3, [r3, #4]
+ 800659c:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 80065a0:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
+ 80065a4:	d102      	bne.n	80065ac <HAL_RCCEx_GetPeriphCLKFreq+0xac>
+          frequency = pllclk;
+ 80065a6:	69fb      	ldr	r3, [r7, #28]
+ 80065a8:	61bb      	str	r3, [r7, #24]
+      break;
+ 80065aa:	e049      	b.n	8006640 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
+          frequency = (pllclk * 2) / 3;
+ 80065ac:	69fb      	ldr	r3, [r7, #28]
+ 80065ae:	005b      	lsls	r3, r3, #1
+ 80065b0:	4a2c      	ldr	r2, [pc, #176]	@ (8006664 <HAL_RCCEx_GetPeriphCLKFreq+0x164>)
+ 80065b2:	fba2 2303 	umull	r2, r3, r2, r3
+ 80065b6:	085b      	lsrs	r3, r3, #1
+ 80065b8:	61bb      	str	r3, [r7, #24]
+      break;
+ 80065ba:	e041      	b.n	8006640 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
+      temp_reg = RCC->BDCR;
+ 80065bc:	4b24      	ldr	r3, [pc, #144]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 80065be:	6a1b      	ldr	r3, [r3, #32]
+ 80065c0:	60fb      	str	r3, [r7, #12]
+      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
+ 80065c2:	68fb      	ldr	r3, [r7, #12]
+ 80065c4:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 80065c8:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 80065cc:	d108      	bne.n	80065e0 <HAL_RCCEx_GetPeriphCLKFreq+0xe0>
+ 80065ce:	68fb      	ldr	r3, [r7, #12]
+ 80065d0:	f003 0302 	and.w	r3, r3, #2
+ 80065d4:	2b00      	cmp	r3, #0
+ 80065d6:	d003      	beq.n	80065e0 <HAL_RCCEx_GetPeriphCLKFreq+0xe0>
+        frequency = LSE_VALUE;
+ 80065d8:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 80065dc:	61bb      	str	r3, [r7, #24]
+ 80065de:	e01e      	b.n	800661e <HAL_RCCEx_GetPeriphCLKFreq+0x11e>
+      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ 80065e0:	68fb      	ldr	r3, [r7, #12]
+ 80065e2:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 80065e6:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
+ 80065ea:	d109      	bne.n	8006600 <HAL_RCCEx_GetPeriphCLKFreq+0x100>
+ 80065ec:	4b18      	ldr	r3, [pc, #96]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 80065ee:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80065f0:	f003 0302 	and.w	r3, r3, #2
+ 80065f4:	2b00      	cmp	r3, #0
+ 80065f6:	d003      	beq.n	8006600 <HAL_RCCEx_GetPeriphCLKFreq+0x100>
+        frequency = LSI_VALUE;
+ 80065f8:	f649 4340 	movw	r3, #40000	@ 0x9c40
+ 80065fc:	61bb      	str	r3, [r7, #24]
+ 80065fe:	e00e      	b.n	800661e <HAL_RCCEx_GetPeriphCLKFreq+0x11e>
+      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ 8006600:	68fb      	ldr	r3, [r7, #12]
+ 8006602:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 8006606:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 800660a:	d11b      	bne.n	8006644 <HAL_RCCEx_GetPeriphCLKFreq+0x144>
+ 800660c:	4b10      	ldr	r3, [pc, #64]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 800660e:	681b      	ldr	r3, [r3, #0]
+ 8006610:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8006614:	2b00      	cmp	r3, #0
+ 8006616:	d015      	beq.n	8006644 <HAL_RCCEx_GetPeriphCLKFreq+0x144>
+        frequency = HSE_VALUE / 128U;
+ 8006618:	4b13      	ldr	r3, [pc, #76]	@ (8006668 <HAL_RCCEx_GetPeriphCLKFreq+0x168>)
+ 800661a:	61bb      	str	r3, [r7, #24]
+      break;
+ 800661c:	e012      	b.n	8006644 <HAL_RCCEx_GetPeriphCLKFreq+0x144>
+ 800661e:	e011      	b.n	8006644 <HAL_RCCEx_GetPeriphCLKFreq+0x144>
+      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
+ 8006620:	f7ff fe86 	bl	8006330 <HAL_RCC_GetPCLK2Freq>
+ 8006624:	4602      	mov	r2, r0
+ 8006626:	4b0a      	ldr	r3, [pc, #40]	@ (8006650 <HAL_RCCEx_GetPeriphCLKFreq+0x150>)
+ 8006628:	685b      	ldr	r3, [r3, #4]
+ 800662a:	0b9b      	lsrs	r3, r3, #14
+ 800662c:	f003 0303 	and.w	r3, r3, #3
+ 8006630:	3301      	adds	r3, #1
+ 8006632:	005b      	lsls	r3, r3, #1
+ 8006634:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8006638:	61bb      	str	r3, [r7, #24]
+      break;
+ 800663a:	e004      	b.n	8006646 <HAL_RCCEx_GetPeriphCLKFreq+0x146>
+      break;
+ 800663c:	bf00      	nop
+ 800663e:	e002      	b.n	8006646 <HAL_RCCEx_GetPeriphCLKFreq+0x146>
+      break;
+ 8006640:	bf00      	nop
+ 8006642:	e000      	b.n	8006646 <HAL_RCCEx_GetPeriphCLKFreq+0x146>
+      break;
+ 8006644:	bf00      	nop
+    }
+  }
+  return (frequency);
+ 8006646:	69bb      	ldr	r3, [r7, #24]
+}
+ 8006648:	4618      	mov	r0, r3
+ 800664a:	3720      	adds	r7, #32
+ 800664c:	46bd      	mov	sp, r7
+ 800664e:	bd80      	pop	{r7, pc}
+ 8006650:	40021000 	.word	0x40021000
+ 8006654:	08007a8c 	.word	0x08007a8c
+ 8006658:	08007a9c 	.word	0x08007a9c
+ 800665c:	00b71b00 	.word	0x00b71b00
+ 8006660:	003d0900 	.word	0x003d0900
+ 8006664:	aaaaaaab 	.word	0xaaaaaaab
+ 8006668:	00016e36 	.word	0x00016e36
+
+0800666c <HAL_TIM_Base_Init>:
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 800666c:	b580      	push	{r7, lr}
+ 800666e:	b082      	sub	sp, #8
+ 8006670:	af00      	add	r7, sp, #0
+ 8006672:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 8006674:	687b      	ldr	r3, [r7, #4]
+ 8006676:	2b00      	cmp	r3, #0
+ 8006678:	d101      	bne.n	800667e <HAL_TIM_Base_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800667a:	2301      	movs	r3, #1
+ 800667c:	e041      	b.n	8006702 <HAL_TIM_Base_Init+0x96>
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 800667e:	687b      	ldr	r3, [r7, #4]
+ 8006680:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 8006684:	b2db      	uxtb	r3, r3
+ 8006686:	2b00      	cmp	r3, #0
+ 8006688:	d106      	bne.n	8006698 <HAL_TIM_Base_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 800668a:	687b      	ldr	r3, [r7, #4]
+ 800668c:	2200      	movs	r2, #0
+ 800668e:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+ 8006692:	6878      	ldr	r0, [r7, #4]
+ 8006694:	f7fc fd04 	bl	80030a0 <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8006698:	687b      	ldr	r3, [r7, #4]
+ 800669a:	2202      	movs	r2, #2
+ 800669c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 80066a0:	687b      	ldr	r3, [r7, #4]
+ 80066a2:	681a      	ldr	r2, [r3, #0]
+ 80066a4:	687b      	ldr	r3, [r7, #4]
+ 80066a6:	3304      	adds	r3, #4
+ 80066a8:	4619      	mov	r1, r3
+ 80066aa:	4610      	mov	r0, r2
+ 80066ac:	f000 f940 	bl	8006930 <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 80066b0:	687b      	ldr	r3, [r7, #4]
+ 80066b2:	2201      	movs	r2, #1
+ 80066b4:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 80066b8:	687b      	ldr	r3, [r7, #4]
+ 80066ba:	2201      	movs	r2, #1
+ 80066bc:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 80066c0:	687b      	ldr	r3, [r7, #4]
+ 80066c2:	2201      	movs	r2, #1
+ 80066c4:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
+ 80066c8:	687b      	ldr	r3, [r7, #4]
+ 80066ca:	2201      	movs	r2, #1
+ 80066cc:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+ 80066d0:	687b      	ldr	r3, [r7, #4]
+ 80066d2:	2201      	movs	r2, #1
+ 80066d4:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 80066d8:	687b      	ldr	r3, [r7, #4]
+ 80066da:	2201      	movs	r2, #1
+ 80066dc:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 80066e0:	687b      	ldr	r3, [r7, #4]
+ 80066e2:	2201      	movs	r2, #1
+ 80066e4:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
+ 80066e8:	687b      	ldr	r3, [r7, #4]
+ 80066ea:	2201      	movs	r2, #1
+ 80066ec:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
+ 80066f0:	687b      	ldr	r3, [r7, #4]
+ 80066f2:	2201      	movs	r2, #1
+ 80066f4:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 80066f8:	687b      	ldr	r3, [r7, #4]
+ 80066fa:	2201      	movs	r2, #1
+ 80066fc:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  return HAL_OK;
+ 8006700:	2300      	movs	r3, #0
+}
+ 8006702:	4618      	mov	r0, r3
+ 8006704:	3708      	adds	r7, #8
+ 8006706:	46bd      	mov	sp, r7
+ 8006708:	bd80      	pop	{r7, pc}
+	...
+
+0800670c <HAL_TIM_Base_Start>:
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ 800670c:	b480      	push	{r7}
+ 800670e:	b085      	sub	sp, #20
+ 8006710:	af00      	add	r7, sp, #0
+ 8006712:	6078      	str	r0, [r7, #4]
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+ 8006714:	687b      	ldr	r3, [r7, #4]
+ 8006716:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 800671a:	b2db      	uxtb	r3, r3
+ 800671c:	2b01      	cmp	r3, #1
+ 800671e:	d001      	beq.n	8006724 <HAL_TIM_Base_Start+0x18>
+  {
+    return HAL_ERROR;
+ 8006720:	2301      	movs	r3, #1
+ 8006722:	e032      	b.n	800678a <HAL_TIM_Base_Start+0x7e>
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8006724:	687b      	ldr	r3, [r7, #4]
+ 8006726:	2202      	movs	r2, #2
+ 8006728:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 800672c:	687b      	ldr	r3, [r7, #4]
+ 800672e:	681b      	ldr	r3, [r3, #0]
+ 8006730:	4a18      	ldr	r2, [pc, #96]	@ (8006794 <HAL_TIM_Base_Start+0x88>)
+ 8006732:	4293      	cmp	r3, r2
+ 8006734:	d00e      	beq.n	8006754 <HAL_TIM_Base_Start+0x48>
+ 8006736:	687b      	ldr	r3, [r7, #4]
+ 8006738:	681b      	ldr	r3, [r3, #0]
+ 800673a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 800673e:	d009      	beq.n	8006754 <HAL_TIM_Base_Start+0x48>
+ 8006740:	687b      	ldr	r3, [r7, #4]
+ 8006742:	681b      	ldr	r3, [r3, #0]
+ 8006744:	4a14      	ldr	r2, [pc, #80]	@ (8006798 <HAL_TIM_Base_Start+0x8c>)
+ 8006746:	4293      	cmp	r3, r2
+ 8006748:	d004      	beq.n	8006754 <HAL_TIM_Base_Start+0x48>
+ 800674a:	687b      	ldr	r3, [r7, #4]
+ 800674c:	681b      	ldr	r3, [r3, #0]
+ 800674e:	4a13      	ldr	r2, [pc, #76]	@ (800679c <HAL_TIM_Base_Start+0x90>)
+ 8006750:	4293      	cmp	r3, r2
+ 8006752:	d111      	bne.n	8006778 <HAL_TIM_Base_Start+0x6c>
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 8006754:	687b      	ldr	r3, [r7, #4]
+ 8006756:	681b      	ldr	r3, [r3, #0]
+ 8006758:	689b      	ldr	r3, [r3, #8]
+ 800675a:	f003 0307 	and.w	r3, r3, #7
+ 800675e:	60fb      	str	r3, [r7, #12]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8006760:	68fb      	ldr	r3, [r7, #12]
+ 8006762:	2b06      	cmp	r3, #6
+ 8006764:	d010      	beq.n	8006788 <HAL_TIM_Base_Start+0x7c>
+    {
+      __HAL_TIM_ENABLE(htim);
+ 8006766:	687b      	ldr	r3, [r7, #4]
+ 8006768:	681b      	ldr	r3, [r3, #0]
+ 800676a:	681a      	ldr	r2, [r3, #0]
+ 800676c:	687b      	ldr	r3, [r7, #4]
+ 800676e:	681b      	ldr	r3, [r3, #0]
+ 8006770:	f042 0201 	orr.w	r2, r2, #1
+ 8006774:	601a      	str	r2, [r3, #0]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8006776:	e007      	b.n	8006788 <HAL_TIM_Base_Start+0x7c>
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+ 8006778:	687b      	ldr	r3, [r7, #4]
+ 800677a:	681b      	ldr	r3, [r3, #0]
+ 800677c:	681a      	ldr	r2, [r3, #0]
+ 800677e:	687b      	ldr	r3, [r7, #4]
+ 8006780:	681b      	ldr	r3, [r3, #0]
+ 8006782:	f042 0201 	orr.w	r2, r2, #1
+ 8006786:	601a      	str	r2, [r3, #0]
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 8006788:	2300      	movs	r3, #0
+}
+ 800678a:	4618      	mov	r0, r3
+ 800678c:	3714      	adds	r7, #20
+ 800678e:	46bd      	mov	sp, r7
+ 8006790:	bc80      	pop	{r7}
+ 8006792:	4770      	bx	lr
+ 8006794:	40012c00 	.word	0x40012c00
+ 8006798:	40000400 	.word	0x40000400
+ 800679c:	40000800 	.word	0x40000800
+
+080067a0 <HAL_TIM_ConfigClockSource>:
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ 80067a0:	b580      	push	{r7, lr}
+ 80067a2:	b084      	sub	sp, #16
+ 80067a4:	af00      	add	r7, sp, #0
+ 80067a6:	6078      	str	r0, [r7, #4]
+ 80067a8:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 80067aa:	2300      	movs	r3, #0
+ 80067ac:	73fb      	strb	r3, [r7, #15]
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 80067ae:	687b      	ldr	r3, [r7, #4]
+ 80067b0:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 80067b4:	2b01      	cmp	r3, #1
+ 80067b6:	d101      	bne.n	80067bc <HAL_TIM_ConfigClockSource+0x1c>
+ 80067b8:	2302      	movs	r3, #2
+ 80067ba:	e0b4      	b.n	8006926 <HAL_TIM_ConfigClockSource+0x186>
+ 80067bc:	687b      	ldr	r3, [r7, #4]
+ 80067be:	2201      	movs	r2, #1
+ 80067c0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  htim->State = HAL_TIM_STATE_BUSY;
+ 80067c4:	687b      	ldr	r3, [r7, #4]
+ 80067c6:	2202      	movs	r2, #2
+ 80067c8:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+ 80067cc:	687b      	ldr	r3, [r7, #4]
+ 80067ce:	681b      	ldr	r3, [r3, #0]
+ 80067d0:	689b      	ldr	r3, [r3, #8]
+ 80067d2:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 80067d4:	68bb      	ldr	r3, [r7, #8]
+ 80067d6:	f023 0377 	bic.w	r3, r3, #119	@ 0x77
+ 80067da:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 80067dc:	68bb      	ldr	r3, [r7, #8]
+ 80067de:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
+ 80067e2:	60bb      	str	r3, [r7, #8]
+  htim->Instance->SMCR = tmpsmcr;
+ 80067e4:	687b      	ldr	r3, [r7, #4]
+ 80067e6:	681b      	ldr	r3, [r3, #0]
+ 80067e8:	68ba      	ldr	r2, [r7, #8]
+ 80067ea:	609a      	str	r2, [r3, #8]
+
+  switch (sClockSourceConfig->ClockSource)
+ 80067ec:	683b      	ldr	r3, [r7, #0]
+ 80067ee:	681b      	ldr	r3, [r3, #0]
+ 80067f0:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 80067f4:	d03e      	beq.n	8006874 <HAL_TIM_ConfigClockSource+0xd4>
+ 80067f6:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 80067fa:	f200 8087 	bhi.w	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 80067fe:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 8006802:	f000 8086 	beq.w	8006912 <HAL_TIM_ConfigClockSource+0x172>
+ 8006806:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 800680a:	d87f      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 800680c:	2b70      	cmp	r3, #112	@ 0x70
+ 800680e:	d01a      	beq.n	8006846 <HAL_TIM_ConfigClockSource+0xa6>
+ 8006810:	2b70      	cmp	r3, #112	@ 0x70
+ 8006812:	d87b      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 8006814:	2b60      	cmp	r3, #96	@ 0x60
+ 8006816:	d050      	beq.n	80068ba <HAL_TIM_ConfigClockSource+0x11a>
+ 8006818:	2b60      	cmp	r3, #96	@ 0x60
+ 800681a:	d877      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 800681c:	2b50      	cmp	r3, #80	@ 0x50
+ 800681e:	d03c      	beq.n	800689a <HAL_TIM_ConfigClockSource+0xfa>
+ 8006820:	2b50      	cmp	r3, #80	@ 0x50
+ 8006822:	d873      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 8006824:	2b40      	cmp	r3, #64	@ 0x40
+ 8006826:	d058      	beq.n	80068da <HAL_TIM_ConfigClockSource+0x13a>
+ 8006828:	2b40      	cmp	r3, #64	@ 0x40
+ 800682a:	d86f      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 800682c:	2b30      	cmp	r3, #48	@ 0x30
+ 800682e:	d064      	beq.n	80068fa <HAL_TIM_ConfigClockSource+0x15a>
+ 8006830:	2b30      	cmp	r3, #48	@ 0x30
+ 8006832:	d86b      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 8006834:	2b20      	cmp	r3, #32
+ 8006836:	d060      	beq.n	80068fa <HAL_TIM_ConfigClockSource+0x15a>
+ 8006838:	2b20      	cmp	r3, #32
+ 800683a:	d867      	bhi.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+ 800683c:	2b00      	cmp	r3, #0
+ 800683e:	d05c      	beq.n	80068fa <HAL_TIM_ConfigClockSource+0x15a>
+ 8006840:	2b10      	cmp	r3, #16
+ 8006842:	d05a      	beq.n	80068fa <HAL_TIM_ConfigClockSource+0x15a>
+ 8006844:	e062      	b.n	800690c <HAL_TIM_ConfigClockSource+0x16c>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 8006846:	687b      	ldr	r3, [r7, #4]
+ 8006848:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 800684a:	683b      	ldr	r3, [r7, #0]
+ 800684c:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 800684e:	683b      	ldr	r3, [r7, #0]
+ 8006850:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 8006852:	683b      	ldr	r3, [r7, #0]
+ 8006854:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 8006856:	f000 f950 	bl	8006afa <TIM_ETR_SetConfig>
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+ 800685a:	687b      	ldr	r3, [r7, #4]
+ 800685c:	681b      	ldr	r3, [r3, #0]
+ 800685e:	689b      	ldr	r3, [r3, #8]
+ 8006860:	60bb      	str	r3, [r7, #8]
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8006862:	68bb      	ldr	r3, [r7, #8]
+ 8006864:	f043 0377 	orr.w	r3, r3, #119	@ 0x77
+ 8006868:	60bb      	str	r3, [r7, #8]
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+ 800686a:	687b      	ldr	r3, [r7, #4]
+ 800686c:	681b      	ldr	r3, [r3, #0]
+ 800686e:	68ba      	ldr	r2, [r7, #8]
+ 8006870:	609a      	str	r2, [r3, #8]
+      break;
+ 8006872:	e04f      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 8006874:	687b      	ldr	r3, [r7, #4]
+ 8006876:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 8006878:	683b      	ldr	r3, [r7, #0]
+ 800687a:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 800687c:	683b      	ldr	r3, [r7, #0]
+ 800687e:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 8006880:	683b      	ldr	r3, [r7, #0]
+ 8006882:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 8006884:	f000 f939 	bl	8006afa <TIM_ETR_SetConfig>
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 8006888:	687b      	ldr	r3, [r7, #4]
+ 800688a:	681b      	ldr	r3, [r3, #0]
+ 800688c:	689a      	ldr	r2, [r3, #8]
+ 800688e:	687b      	ldr	r3, [r7, #4]
+ 8006890:	681b      	ldr	r3, [r3, #0]
+ 8006892:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
+ 8006896:	609a      	str	r2, [r3, #8]
+      break;
+ 8006898:	e03c      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 800689a:	687b      	ldr	r3, [r7, #4]
+ 800689c:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 800689e:	683b      	ldr	r3, [r7, #0]
+ 80068a0:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 80068a2:	683b      	ldr	r3, [r7, #0]
+ 80068a4:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 80068a6:	461a      	mov	r2, r3
+ 80068a8:	f000 f8b0 	bl	8006a0c <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ 80068ac:	687b      	ldr	r3, [r7, #4]
+ 80068ae:	681b      	ldr	r3, [r3, #0]
+ 80068b0:	2150      	movs	r1, #80	@ 0x50
+ 80068b2:	4618      	mov	r0, r3
+ 80068b4:	f000 f907 	bl	8006ac6 <TIM_ITRx_SetConfig>
+      break;
+ 80068b8:	e02c      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 80068ba:	687b      	ldr	r3, [r7, #4]
+ 80068bc:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 80068be:	683b      	ldr	r3, [r7, #0]
+ 80068c0:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 80068c2:	683b      	ldr	r3, [r7, #0]
+ 80068c4:	68db      	ldr	r3, [r3, #12]
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 80068c6:	461a      	mov	r2, r3
+ 80068c8:	f000 f8ce 	bl	8006a68 <TIM_TI2_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ 80068cc:	687b      	ldr	r3, [r7, #4]
+ 80068ce:	681b      	ldr	r3, [r3, #0]
+ 80068d0:	2160      	movs	r1, #96	@ 0x60
+ 80068d2:	4618      	mov	r0, r3
+ 80068d4:	f000 f8f7 	bl	8006ac6 <TIM_ITRx_SetConfig>
+      break;
+ 80068d8:	e01c      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 80068da:	687b      	ldr	r3, [r7, #4]
+ 80068dc:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 80068de:	683b      	ldr	r3, [r7, #0]
+ 80068e0:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 80068e2:	683b      	ldr	r3, [r7, #0]
+ 80068e4:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 80068e6:	461a      	mov	r2, r3
+ 80068e8:	f000 f890 	bl	8006a0c <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ 80068ec:	687b      	ldr	r3, [r7, #4]
+ 80068ee:	681b      	ldr	r3, [r3, #0]
+ 80068f0:	2140      	movs	r1, #64	@ 0x40
+ 80068f2:	4618      	mov	r0, r3
+ 80068f4:	f000 f8e7 	bl	8006ac6 <TIM_ITRx_SetConfig>
+      break;
+ 80068f8:	e00c      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ 80068fa:	687b      	ldr	r3, [r7, #4]
+ 80068fc:	681a      	ldr	r2, [r3, #0]
+ 80068fe:	683b      	ldr	r3, [r7, #0]
+ 8006900:	681b      	ldr	r3, [r3, #0]
+ 8006902:	4619      	mov	r1, r3
+ 8006904:	4610      	mov	r0, r2
+ 8006906:	f000 f8de 	bl	8006ac6 <TIM_ITRx_SetConfig>
+      break;
+ 800690a:	e003      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+    }
+
+    default:
+      status = HAL_ERROR;
+ 800690c:	2301      	movs	r3, #1
+ 800690e:	73fb      	strb	r3, [r7, #15]
+      break;
+ 8006910:	e000      	b.n	8006914 <HAL_TIM_ConfigClockSource+0x174>
+      break;
+ 8006912:	bf00      	nop
+  }
+  htim->State = HAL_TIM_STATE_READY;
+ 8006914:	687b      	ldr	r3, [r7, #4]
+ 8006916:	2201      	movs	r2, #1
+ 8006918:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  __HAL_UNLOCK(htim);
+ 800691c:	687b      	ldr	r3, [r7, #4]
+ 800691e:	2200      	movs	r2, #0
+ 8006920:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  return status;
+ 8006924:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8006926:	4618      	mov	r0, r3
+ 8006928:	3710      	adds	r7, #16
+ 800692a:	46bd      	mov	sp, r7
+ 800692c:	bd80      	pop	{r7, pc}
+	...
+
+08006930 <TIM_Base_SetConfig>:
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+ 8006930:	b480      	push	{r7}
+ 8006932:	b085      	sub	sp, #20
+ 8006934:	af00      	add	r7, sp, #0
+ 8006936:	6078      	str	r0, [r7, #4]
+ 8006938:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+ 800693a:	687b      	ldr	r3, [r7, #4]
+ 800693c:	681b      	ldr	r3, [r3, #0]
+ 800693e:	60fb      	str	r3, [r7, #12]
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 8006940:	687b      	ldr	r3, [r7, #4]
+ 8006942:	4a2f      	ldr	r2, [pc, #188]	@ (8006a00 <TIM_Base_SetConfig+0xd0>)
+ 8006944:	4293      	cmp	r3, r2
+ 8006946:	d00b      	beq.n	8006960 <TIM_Base_SetConfig+0x30>
+ 8006948:	687b      	ldr	r3, [r7, #4]
+ 800694a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 800694e:	d007      	beq.n	8006960 <TIM_Base_SetConfig+0x30>
+ 8006950:	687b      	ldr	r3, [r7, #4]
+ 8006952:	4a2c      	ldr	r2, [pc, #176]	@ (8006a04 <TIM_Base_SetConfig+0xd4>)
+ 8006954:	4293      	cmp	r3, r2
+ 8006956:	d003      	beq.n	8006960 <TIM_Base_SetConfig+0x30>
+ 8006958:	687b      	ldr	r3, [r7, #4]
+ 800695a:	4a2b      	ldr	r2, [pc, #172]	@ (8006a08 <TIM_Base_SetConfig+0xd8>)
+ 800695c:	4293      	cmp	r3, r2
+ 800695e:	d108      	bne.n	8006972 <TIM_Base_SetConfig+0x42>
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 8006960:	68fb      	ldr	r3, [r7, #12]
+ 8006962:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 8006966:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= Structure->CounterMode;
+ 8006968:	683b      	ldr	r3, [r7, #0]
+ 800696a:	685b      	ldr	r3, [r3, #4]
+ 800696c:	68fa      	ldr	r2, [r7, #12]
+ 800696e:	4313      	orrs	r3, r2
+ 8006970:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 8006972:	687b      	ldr	r3, [r7, #4]
+ 8006974:	4a22      	ldr	r2, [pc, #136]	@ (8006a00 <TIM_Base_SetConfig+0xd0>)
+ 8006976:	4293      	cmp	r3, r2
+ 8006978:	d00b      	beq.n	8006992 <TIM_Base_SetConfig+0x62>
+ 800697a:	687b      	ldr	r3, [r7, #4]
+ 800697c:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 8006980:	d007      	beq.n	8006992 <TIM_Base_SetConfig+0x62>
+ 8006982:	687b      	ldr	r3, [r7, #4]
+ 8006984:	4a1f      	ldr	r2, [pc, #124]	@ (8006a04 <TIM_Base_SetConfig+0xd4>)
+ 8006986:	4293      	cmp	r3, r2
+ 8006988:	d003      	beq.n	8006992 <TIM_Base_SetConfig+0x62>
+ 800698a:	687b      	ldr	r3, [r7, #4]
+ 800698c:	4a1e      	ldr	r2, [pc, #120]	@ (8006a08 <TIM_Base_SetConfig+0xd8>)
+ 800698e:	4293      	cmp	r3, r2
+ 8006990:	d108      	bne.n	80069a4 <TIM_Base_SetConfig+0x74>
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 8006992:	68fb      	ldr	r3, [r7, #12]
+ 8006994:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
+ 8006998:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 800699a:	683b      	ldr	r3, [r7, #0]
+ 800699c:	68db      	ldr	r3, [r3, #12]
+ 800699e:	68fa      	ldr	r2, [r7, #12]
+ 80069a0:	4313      	orrs	r3, r2
+ 80069a2:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 80069a4:	68fb      	ldr	r3, [r7, #12]
+ 80069a6:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
+ 80069aa:	683b      	ldr	r3, [r7, #0]
+ 80069ac:	695b      	ldr	r3, [r3, #20]
+ 80069ae:	4313      	orrs	r3, r2
+ 80069b0:	60fb      	str	r3, [r7, #12]
+
+  TIMx->CR1 = tmpcr1;
+ 80069b2:	687b      	ldr	r3, [r7, #4]
+ 80069b4:	68fa      	ldr	r2, [r7, #12]
+ 80069b6:	601a      	str	r2, [r3, #0]
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 80069b8:	683b      	ldr	r3, [r7, #0]
+ 80069ba:	689a      	ldr	r2, [r3, #8]
+ 80069bc:	687b      	ldr	r3, [r7, #4]
+ 80069be:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+ 80069c0:	683b      	ldr	r3, [r7, #0]
+ 80069c2:	681a      	ldr	r2, [r3, #0]
+ 80069c4:	687b      	ldr	r3, [r7, #4]
+ 80069c6:	629a      	str	r2, [r3, #40]	@ 0x28
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 80069c8:	687b      	ldr	r3, [r7, #4]
+ 80069ca:	4a0d      	ldr	r2, [pc, #52]	@ (8006a00 <TIM_Base_SetConfig+0xd0>)
+ 80069cc:	4293      	cmp	r3, r2
+ 80069ce:	d103      	bne.n	80069d8 <TIM_Base_SetConfig+0xa8>
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+ 80069d0:	683b      	ldr	r3, [r7, #0]
+ 80069d2:	691a      	ldr	r2, [r3, #16]
+ 80069d4:	687b      	ldr	r3, [r7, #4]
+ 80069d6:	631a      	str	r2, [r3, #48]	@ 0x30
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+ 80069d8:	687b      	ldr	r3, [r7, #4]
+ 80069da:	2201      	movs	r2, #1
+ 80069dc:	615a      	str	r2, [r3, #20]
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ 80069de:	687b      	ldr	r3, [r7, #4]
+ 80069e0:	691b      	ldr	r3, [r3, #16]
+ 80069e2:	f003 0301 	and.w	r3, r3, #1
+ 80069e6:	2b00      	cmp	r3, #0
+ 80069e8:	d005      	beq.n	80069f6 <TIM_Base_SetConfig+0xc6>
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ 80069ea:	687b      	ldr	r3, [r7, #4]
+ 80069ec:	691b      	ldr	r3, [r3, #16]
+ 80069ee:	f023 0201 	bic.w	r2, r3, #1
+ 80069f2:	687b      	ldr	r3, [r7, #4]
+ 80069f4:	611a      	str	r2, [r3, #16]
+  }
+}
+ 80069f6:	bf00      	nop
+ 80069f8:	3714      	adds	r7, #20
+ 80069fa:	46bd      	mov	sp, r7
+ 80069fc:	bc80      	pop	{r7}
+ 80069fe:	4770      	bx	lr
+ 8006a00:	40012c00 	.word	0x40012c00
+ 8006a04:	40000400 	.word	0x40000400
+ 8006a08:	40000800 	.word	0x40000800
+
+08006a0c <TIM_TI1_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8006a0c:	b480      	push	{r7}
+ 8006a0e:	b087      	sub	sp, #28
+ 8006a10:	af00      	add	r7, sp, #0
+ 8006a12:	60f8      	str	r0, [r7, #12]
+ 8006a14:	60b9      	str	r1, [r7, #8]
+ 8006a16:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+ 8006a18:	68fb      	ldr	r3, [r7, #12]
+ 8006a1a:	6a1b      	ldr	r3, [r3, #32]
+ 8006a1c:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8006a1e:	68fb      	ldr	r3, [r7, #12]
+ 8006a20:	6a1b      	ldr	r3, [r3, #32]
+ 8006a22:	f023 0201 	bic.w	r2, r3, #1
+ 8006a26:	68fb      	ldr	r3, [r7, #12]
+ 8006a28:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 8006a2a:	68fb      	ldr	r3, [r7, #12]
+ 8006a2c:	699b      	ldr	r3, [r3, #24]
+ 8006a2e:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 8006a30:	693b      	ldr	r3, [r7, #16]
+ 8006a32:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
+ 8006a36:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8006a38:	687b      	ldr	r3, [r7, #4]
+ 8006a3a:	011b      	lsls	r3, r3, #4
+ 8006a3c:	693a      	ldr	r2, [r7, #16]
+ 8006a3e:	4313      	orrs	r3, r2
+ 8006a40:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 8006a42:	697b      	ldr	r3, [r7, #20]
+ 8006a44:	f023 030a 	bic.w	r3, r3, #10
+ 8006a48:	617b      	str	r3, [r7, #20]
+  tmpccer |= TIM_ICPolarity;
+ 8006a4a:	697a      	ldr	r2, [r7, #20]
+ 8006a4c:	68bb      	ldr	r3, [r7, #8]
+ 8006a4e:	4313      	orrs	r3, r2
+ 8006a50:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+ 8006a52:	68fb      	ldr	r3, [r7, #12]
+ 8006a54:	693a      	ldr	r2, [r7, #16]
+ 8006a56:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 8006a58:	68fb      	ldr	r3, [r7, #12]
+ 8006a5a:	697a      	ldr	r2, [r7, #20]
+ 8006a5c:	621a      	str	r2, [r3, #32]
+}
+ 8006a5e:	bf00      	nop
+ 8006a60:	371c      	adds	r7, #28
+ 8006a62:	46bd      	mov	sp, r7
+ 8006a64:	bc80      	pop	{r7}
+ 8006a66:	4770      	bx	lr
+
+08006a68 <TIM_TI2_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8006a68:	b480      	push	{r7}
+ 8006a6a:	b087      	sub	sp, #28
+ 8006a6c:	af00      	add	r7, sp, #0
+ 8006a6e:	60f8      	str	r0, [r7, #12]
+ 8006a70:	60b9      	str	r1, [r7, #8]
+ 8006a72:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+ 8006a74:	68fb      	ldr	r3, [r7, #12]
+ 8006a76:	6a1b      	ldr	r3, [r3, #32]
+ 8006a78:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8006a7a:	68fb      	ldr	r3, [r7, #12]
+ 8006a7c:	6a1b      	ldr	r3, [r3, #32]
+ 8006a7e:	f023 0210 	bic.w	r2, r3, #16
+ 8006a82:	68fb      	ldr	r3, [r7, #12]
+ 8006a84:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 8006a86:	68fb      	ldr	r3, [r7, #12]
+ 8006a88:	699b      	ldr	r3, [r3, #24]
+ 8006a8a:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 8006a8c:	693b      	ldr	r3, [r7, #16]
+ 8006a8e:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
+ 8006a92:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 8006a94:	687b      	ldr	r3, [r7, #4]
+ 8006a96:	031b      	lsls	r3, r3, #12
+ 8006a98:	693a      	ldr	r2, [r7, #16]
+ 8006a9a:	4313      	orrs	r3, r2
+ 8006a9c:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 8006a9e:	697b      	ldr	r3, [r7, #20]
+ 8006aa0:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
+ 8006aa4:	617b      	str	r3, [r7, #20]
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 8006aa6:	68bb      	ldr	r3, [r7, #8]
+ 8006aa8:	011b      	lsls	r3, r3, #4
+ 8006aaa:	697a      	ldr	r2, [r7, #20]
+ 8006aac:	4313      	orrs	r3, r2
+ 8006aae:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+ 8006ab0:	68fb      	ldr	r3, [r7, #12]
+ 8006ab2:	693a      	ldr	r2, [r7, #16]
+ 8006ab4:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 8006ab6:	68fb      	ldr	r3, [r7, #12]
+ 8006ab8:	697a      	ldr	r2, [r7, #20]
+ 8006aba:	621a      	str	r2, [r3, #32]
+}
+ 8006abc:	bf00      	nop
+ 8006abe:	371c      	adds	r7, #28
+ 8006ac0:	46bd      	mov	sp, r7
+ 8006ac2:	bc80      	pop	{r7}
+ 8006ac4:	4770      	bx	lr
+
+08006ac6 <TIM_ITRx_SetConfig>:
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ 8006ac6:	b480      	push	{r7}
+ 8006ac8:	b085      	sub	sp, #20
+ 8006aca:	af00      	add	r7, sp, #0
+ 8006acc:	6078      	str	r0, [r7, #4]
+ 8006ace:	6039      	str	r1, [r7, #0]
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+ 8006ad0:	687b      	ldr	r3, [r7, #4]
+ 8006ad2:	689b      	ldr	r3, [r3, #8]
+ 8006ad4:	60fb      	str	r3, [r7, #12]
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8006ad6:	68fb      	ldr	r3, [r7, #12]
+ 8006ad8:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 8006adc:	60fb      	str	r3, [r7, #12]
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 8006ade:	683a      	ldr	r2, [r7, #0]
+ 8006ae0:	68fb      	ldr	r3, [r7, #12]
+ 8006ae2:	4313      	orrs	r3, r2
+ 8006ae4:	f043 0307 	orr.w	r3, r3, #7
+ 8006ae8:	60fb      	str	r3, [r7, #12]
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 8006aea:	687b      	ldr	r3, [r7, #4]
+ 8006aec:	68fa      	ldr	r2, [r7, #12]
+ 8006aee:	609a      	str	r2, [r3, #8]
+}
+ 8006af0:	bf00      	nop
+ 8006af2:	3714      	adds	r7, #20
+ 8006af4:	46bd      	mov	sp, r7
+ 8006af6:	bc80      	pop	{r7}
+ 8006af8:	4770      	bx	lr
+
+08006afa <TIM_ETR_SetConfig>:
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ 8006afa:	b480      	push	{r7}
+ 8006afc:	b087      	sub	sp, #28
+ 8006afe:	af00      	add	r7, sp, #0
+ 8006b00:	60f8      	str	r0, [r7, #12]
+ 8006b02:	60b9      	str	r1, [r7, #8]
+ 8006b04:	607a      	str	r2, [r7, #4]
+ 8006b06:	603b      	str	r3, [r7, #0]
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+ 8006b08:	68fb      	ldr	r3, [r7, #12]
+ 8006b0a:	689b      	ldr	r3, [r3, #8]
+ 8006b0c:	617b      	str	r3, [r7, #20]
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8006b0e:	697b      	ldr	r3, [r7, #20]
+ 8006b10:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
+ 8006b14:	617b      	str	r3, [r7, #20]
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 8006b16:	683b      	ldr	r3, [r7, #0]
+ 8006b18:	021a      	lsls	r2, r3, #8
+ 8006b1a:	687b      	ldr	r3, [r7, #4]
+ 8006b1c:	431a      	orrs	r2, r3
+ 8006b1e:	68bb      	ldr	r3, [r7, #8]
+ 8006b20:	4313      	orrs	r3, r2
+ 8006b22:	697a      	ldr	r2, [r7, #20]
+ 8006b24:	4313      	orrs	r3, r2
+ 8006b26:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 8006b28:	68fb      	ldr	r3, [r7, #12]
+ 8006b2a:	697a      	ldr	r2, [r7, #20]
+ 8006b2c:	609a      	str	r2, [r3, #8]
+}
+ 8006b2e:	bf00      	nop
+ 8006b30:	371c      	adds	r7, #28
+ 8006b32:	46bd      	mov	sp, r7
+ 8006b34:	bc80      	pop	{r7}
+ 8006b36:	4770      	bx	lr
+
+08006b38 <HAL_TIMEx_MasterConfigSynchronization>:
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 8006b38:	b480      	push	{r7}
+ 8006b3a:	b085      	sub	sp, #20
+ 8006b3c:	af00      	add	r7, sp, #0
+ 8006b3e:	6078      	str	r0, [r7, #4]
+ 8006b40:	6039      	str	r1, [r7, #0]
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+ 8006b42:	687b      	ldr	r3, [r7, #4]
+ 8006b44:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 8006b48:	2b01      	cmp	r3, #1
+ 8006b4a:	d101      	bne.n	8006b50 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8006b4c:	2302      	movs	r3, #2
+ 8006b4e:	e046      	b.n	8006bde <HAL_TIMEx_MasterConfigSynchronization+0xa6>
+ 8006b50:	687b      	ldr	r3, [r7, #4]
+ 8006b52:	2201      	movs	r2, #1
+ 8006b54:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8006b58:	687b      	ldr	r3, [r7, #4]
+ 8006b5a:	2202      	movs	r2, #2
+ 8006b5c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+ 8006b60:	687b      	ldr	r3, [r7, #4]
+ 8006b62:	681b      	ldr	r3, [r3, #0]
+ 8006b64:	685b      	ldr	r3, [r3, #4]
+ 8006b66:	60fb      	str	r3, [r7, #12]
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 8006b68:	687b      	ldr	r3, [r7, #4]
+ 8006b6a:	681b      	ldr	r3, [r3, #0]
+ 8006b6c:	689b      	ldr	r3, [r3, #8]
+ 8006b6e:	60bb      	str	r3, [r7, #8]
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+ 8006b70:	68fb      	ldr	r3, [r7, #12]
+ 8006b72:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 8006b76:	60fb      	str	r3, [r7, #12]
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+ 8006b78:	683b      	ldr	r3, [r7, #0]
+ 8006b7a:	681b      	ldr	r3, [r3, #0]
+ 8006b7c:	68fa      	ldr	r2, [r7, #12]
+ 8006b7e:	4313      	orrs	r3, r2
+ 8006b80:	60fb      	str	r3, [r7, #12]
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+ 8006b82:	687b      	ldr	r3, [r7, #4]
+ 8006b84:	681b      	ldr	r3, [r3, #0]
+ 8006b86:	68fa      	ldr	r2, [r7, #12]
+ 8006b88:	605a      	str	r2, [r3, #4]
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 8006b8a:	687b      	ldr	r3, [r7, #4]
+ 8006b8c:	681b      	ldr	r3, [r3, #0]
+ 8006b8e:	4a16      	ldr	r2, [pc, #88]	@ (8006be8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 8006b90:	4293      	cmp	r3, r2
+ 8006b92:	d00e      	beq.n	8006bb2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8006b94:	687b      	ldr	r3, [r7, #4]
+ 8006b96:	681b      	ldr	r3, [r3, #0]
+ 8006b98:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 8006b9c:	d009      	beq.n	8006bb2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8006b9e:	687b      	ldr	r3, [r7, #4]
+ 8006ba0:	681b      	ldr	r3, [r3, #0]
+ 8006ba2:	4a12      	ldr	r2, [pc, #72]	@ (8006bec <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8006ba4:	4293      	cmp	r3, r2
+ 8006ba6:	d004      	beq.n	8006bb2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8006ba8:	687b      	ldr	r3, [r7, #4]
+ 8006baa:	681b      	ldr	r3, [r3, #0]
+ 8006bac:	4a10      	ldr	r2, [pc, #64]	@ (8006bf0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
+ 8006bae:	4293      	cmp	r3, r2
+ 8006bb0:	d10c      	bne.n	8006bcc <HAL_TIMEx_MasterConfigSynchronization+0x94>
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+ 8006bb2:	68bb      	ldr	r3, [r7, #8]
+ 8006bb4:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 8006bb8:	60bb      	str	r3, [r7, #8]
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 8006bba:	683b      	ldr	r3, [r7, #0]
+ 8006bbc:	685b      	ldr	r3, [r3, #4]
+ 8006bbe:	68ba      	ldr	r2, [r7, #8]
+ 8006bc0:	4313      	orrs	r3, r2
+ 8006bc2:	60bb      	str	r3, [r7, #8]
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+ 8006bc4:	687b      	ldr	r3, [r7, #4]
+ 8006bc6:	681b      	ldr	r3, [r3, #0]
+ 8006bc8:	68ba      	ldr	r2, [r7, #8]
+ 8006bca:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+ 8006bcc:	687b      	ldr	r3, [r7, #4]
+ 8006bce:	2201      	movs	r2, #1
+ 8006bd0:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  __HAL_UNLOCK(htim);
+ 8006bd4:	687b      	ldr	r3, [r7, #4]
+ 8006bd6:	2200      	movs	r2, #0
+ 8006bd8:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  return HAL_OK;
+ 8006bdc:	2300      	movs	r3, #0
+}
+ 8006bde:	4618      	mov	r0, r3
+ 8006be0:	3714      	adds	r7, #20
+ 8006be2:	46bd      	mov	sp, r7
+ 8006be4:	bc80      	pop	{r7}
+ 8006be6:	4770      	bx	lr
+ 8006be8:	40012c00 	.word	0x40012c00
+ 8006bec:	40000400 	.word	0x40000400
+ 8006bf0:	40000800 	.word	0x40000800
+
+08006bf4 <HAL_UART_Init>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
 {
- 80050d8:	b580      	push	{r7, lr}
- 80050da:	b082      	sub	sp, #8
- 80050dc:	af00      	add	r7, sp, #0
- 80050de:	6078      	str	r0, [r7, #4]
+ 8006bf4:	b580      	push	{r7, lr}
+ 8006bf6:	b082      	sub	sp, #8
+ 8006bf8:	af00      	add	r7, sp, #0
+ 8006bfa:	6078      	str	r0, [r7, #4]
   /* Check the UART handle allocation */
   if (huart == NULL)
- 80050e0:	687b      	ldr	r3, [r7, #4]
- 80050e2:	2b00      	cmp	r3, #0
- 80050e4:	d101      	bne.n	80050ea <HAL_UART_Init+0x12>
+ 8006bfc:	687b      	ldr	r3, [r7, #4]
+ 8006bfe:	2b00      	cmp	r3, #0
+ 8006c00:	d101      	bne.n	8006c06 <HAL_UART_Init+0x12>
   {
     return HAL_ERROR;
- 80050e6:	2301      	movs	r3, #1
- 80050e8:	e042      	b.n	8005170 <HAL_UART_Init+0x98>
+ 8006c02:	2301      	movs	r3, #1
+ 8006c04:	e042      	b.n	8006c8c <HAL_UART_Init+0x98>
   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
 #if defined(USART_CR1_OVER8)
   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
 #endif /* USART_CR1_OVER8 */
 
   if (huart->gState == HAL_UART_STATE_RESET)
- 80050ea:	687b      	ldr	r3, [r7, #4]
- 80050ec:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
- 80050f0:	b2db      	uxtb	r3, r3
- 80050f2:	2b00      	cmp	r3, #0
- 80050f4:	d106      	bne.n	8005104 <HAL_UART_Init+0x2c>
+ 8006c06:	687b      	ldr	r3, [r7, #4]
+ 8006c08:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8006c0c:	b2db      	uxtb	r3, r3
+ 8006c0e:	2b00      	cmp	r3, #0
+ 8006c10:	d106      	bne.n	8006c20 <HAL_UART_Init+0x2c>
   {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
- 80050f6:	687b      	ldr	r3, [r7, #4]
- 80050f8:	2200      	movs	r2, #0
- 80050fa:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+ 8006c12:	687b      	ldr	r3, [r7, #4]
+ 8006c14:	2200      	movs	r2, #0
+ 8006c16:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 
     /* Init the low level hardware */
     huart->MspInitCallback(huart);
 #else
     /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
- 80050fe:	6878      	ldr	r0, [r7, #4]
- 8005100:	f7fd fc50 	bl	80029a4 <HAL_UART_MspInit>
+ 8006c1a:	6878      	ldr	r0, [r7, #4]
+ 8006c1c:	f7fc fa88 	bl	8003130 <HAL_UART_MspInit>
 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
   huart->gState = HAL_UART_STATE_BUSY;
- 8005104:	687b      	ldr	r3, [r7, #4]
- 8005106:	2224      	movs	r2, #36	@ 0x24
- 8005108:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006c20:	687b      	ldr	r3, [r7, #4]
+ 8006c22:	2224      	movs	r2, #36	@ 0x24
+ 8006c24:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
- 800510c:	687b      	ldr	r3, [r7, #4]
- 800510e:	681b      	ldr	r3, [r3, #0]
- 8005110:	68da      	ldr	r2, [r3, #12]
- 8005112:	687b      	ldr	r3, [r7, #4]
- 8005114:	681b      	ldr	r3, [r3, #0]
- 8005116:	f422 5200 	bic.w	r2, r2, #8192	@ 0x2000
- 800511a:	60da      	str	r2, [r3, #12]
+ 8006c28:	687b      	ldr	r3, [r7, #4]
+ 8006c2a:	681b      	ldr	r3, [r3, #0]
+ 8006c2c:	68da      	ldr	r2, [r3, #12]
+ 8006c2e:	687b      	ldr	r3, [r7, #4]
+ 8006c30:	681b      	ldr	r3, [r3, #0]
+ 8006c32:	f422 5200 	bic.w	r2, r2, #8192	@ 0x2000
+ 8006c36:	60da      	str	r2, [r3, #12]
 
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
- 800511c:	6878      	ldr	r0, [r7, #4]
- 800511e:	f000 fd63 	bl	8005be8 <UART_SetConfig>
+ 8006c38:	6878      	ldr	r0, [r7, #4]
+ 8006c3a:	f000 fd63 	bl	8007704 <UART_SetConfig>
 
   /* In asynchronous mode, the following bits must be kept cleared:
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8005122:	687b      	ldr	r3, [r7, #4]
- 8005124:	681b      	ldr	r3, [r3, #0]
- 8005126:	691a      	ldr	r2, [r3, #16]
- 8005128:	687b      	ldr	r3, [r7, #4]
- 800512a:	681b      	ldr	r3, [r3, #0]
- 800512c:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
- 8005130:	611a      	str	r2, [r3, #16]
+ 8006c3e:	687b      	ldr	r3, [r7, #4]
+ 8006c40:	681b      	ldr	r3, [r3, #0]
+ 8006c42:	691a      	ldr	r2, [r3, #16]
+ 8006c44:	687b      	ldr	r3, [r7, #4]
+ 8006c46:	681b      	ldr	r3, [r3, #0]
+ 8006c48:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
+ 8006c4c:	611a      	str	r2, [r3, #16]
   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8005132:	687b      	ldr	r3, [r7, #4]
- 8005134:	681b      	ldr	r3, [r3, #0]
- 8005136:	695a      	ldr	r2, [r3, #20]
- 8005138:	687b      	ldr	r3, [r7, #4]
- 800513a:	681b      	ldr	r3, [r3, #0]
- 800513c:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
- 8005140:	615a      	str	r2, [r3, #20]
+ 8006c4e:	687b      	ldr	r3, [r7, #4]
+ 8006c50:	681b      	ldr	r3, [r3, #0]
+ 8006c52:	695a      	ldr	r2, [r3, #20]
+ 8006c54:	687b      	ldr	r3, [r7, #4]
+ 8006c56:	681b      	ldr	r3, [r3, #0]
+ 8006c58:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
+ 8006c5c:	615a      	str	r2, [r3, #20]
 
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
- 8005142:	687b      	ldr	r3, [r7, #4]
- 8005144:	681b      	ldr	r3, [r3, #0]
- 8005146:	68da      	ldr	r2, [r3, #12]
- 8005148:	687b      	ldr	r3, [r7, #4]
- 800514a:	681b      	ldr	r3, [r3, #0]
- 800514c:	f442 5200 	orr.w	r2, r2, #8192	@ 0x2000
- 8005150:	60da      	str	r2, [r3, #12]
+ 8006c5e:	687b      	ldr	r3, [r7, #4]
+ 8006c60:	681b      	ldr	r3, [r3, #0]
+ 8006c62:	68da      	ldr	r2, [r3, #12]
+ 8006c64:	687b      	ldr	r3, [r7, #4]
+ 8006c66:	681b      	ldr	r3, [r3, #0]
+ 8006c68:	f442 5200 	orr.w	r2, r2, #8192	@ 0x2000
+ 8006c6c:	60da      	str	r2, [r3, #12]
 
   /* Initialize the UART state */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8005152:	687b      	ldr	r3, [r7, #4]
- 8005154:	2200      	movs	r2, #0
- 8005156:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006c6e:	687b      	ldr	r3, [r7, #4]
+ 8006c70:	2200      	movs	r2, #0
+ 8006c72:	645a      	str	r2, [r3, #68]	@ 0x44
   huart->gState = HAL_UART_STATE_READY;
- 8005158:	687b      	ldr	r3, [r7, #4]
- 800515a:	2220      	movs	r2, #32
- 800515c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006c74:	687b      	ldr	r3, [r7, #4]
+ 8006c76:	2220      	movs	r2, #32
+ 8006c78:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
   huart->RxState = HAL_UART_STATE_READY;
- 8005160:	687b      	ldr	r3, [r7, #4]
- 8005162:	2220      	movs	r2, #32
- 8005164:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 8006c7c:	687b      	ldr	r3, [r7, #4]
+ 8006c7e:	2220      	movs	r2, #32
+ 8006c80:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
   huart->RxEventType = HAL_UART_RXEVENT_TC;
- 8005168:	687b      	ldr	r3, [r7, #4]
- 800516a:	2200      	movs	r2, #0
- 800516c:	635a      	str	r2, [r3, #52]	@ 0x34
+ 8006c84:	687b      	ldr	r3, [r7, #4]
+ 8006c86:	2200      	movs	r2, #0
+ 8006c88:	635a      	str	r2, [r3, #52]	@ 0x34
 
   return HAL_OK;
- 800516e:	2300      	movs	r3, #0
+ 8006c8a:	2300      	movs	r3, #0
 }
- 8005170:	4618      	mov	r0, r3
- 8005172:	3708      	adds	r7, #8
- 8005174:	46bd      	mov	sp, r7
- 8005176:	bd80      	pop	{r7, pc}
+ 8006c8c:	4618      	mov	r0, r3
+ 8006c8e:	3708      	adds	r7, #8
+ 8006c90:	46bd      	mov	sp, r7
+ 8006c92:	bd80      	pop	{r7, pc}
 
-08005178 <HAL_UART_Transmit>:
+08006c94 <HAL_UART_Transmit>:
   * @param  Size  Amount of data elements (u8 or u16) to be sent
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
- 8005178:	b580      	push	{r7, lr}
- 800517a:	b08a      	sub	sp, #40	@ 0x28
- 800517c:	af02      	add	r7, sp, #8
- 800517e:	60f8      	str	r0, [r7, #12]
- 8005180:	60b9      	str	r1, [r7, #8]
- 8005182:	603b      	str	r3, [r7, #0]
- 8005184:	4613      	mov	r3, r2
- 8005186:	80fb      	strh	r3, [r7, #6]
+ 8006c94:	b580      	push	{r7, lr}
+ 8006c96:	b08a      	sub	sp, #40	@ 0x28
+ 8006c98:	af02      	add	r7, sp, #8
+ 8006c9a:	60f8      	str	r0, [r7, #12]
+ 8006c9c:	60b9      	str	r1, [r7, #8]
+ 8006c9e:	603b      	str	r3, [r7, #0]
+ 8006ca0:	4613      	mov	r3, r2
+ 8006ca2:	80fb      	strh	r3, [r7, #6]
   const uint8_t  *pdata8bits;
   const uint16_t *pdata16bits;
   uint32_t tickstart = 0U;
- 8005188:	2300      	movs	r3, #0
- 800518a:	617b      	str	r3, [r7, #20]
+ 8006ca4:	2300      	movs	r3, #0
+ 8006ca6:	617b      	str	r3, [r7, #20]
 
   /* Check that a Tx process is not already ongoing */
   if (huart->gState == HAL_UART_STATE_READY)
- 800518c:	68fb      	ldr	r3, [r7, #12]
- 800518e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
- 8005192:	b2db      	uxtb	r3, r3
- 8005194:	2b20      	cmp	r3, #32
- 8005196:	d175      	bne.n	8005284 <HAL_UART_Transmit+0x10c>
+ 8006ca8:	68fb      	ldr	r3, [r7, #12]
+ 8006caa:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8006cae:	b2db      	uxtb	r3, r3
+ 8006cb0:	2b20      	cmp	r3, #32
+ 8006cb2:	d175      	bne.n	8006da0 <HAL_UART_Transmit+0x10c>
   {
     if ((pData == NULL) || (Size == 0U))
- 8005198:	68bb      	ldr	r3, [r7, #8]
- 800519a:	2b00      	cmp	r3, #0
- 800519c:	d002      	beq.n	80051a4 <HAL_UART_Transmit+0x2c>
- 800519e:	88fb      	ldrh	r3, [r7, #6]
- 80051a0:	2b00      	cmp	r3, #0
- 80051a2:	d101      	bne.n	80051a8 <HAL_UART_Transmit+0x30>
+ 8006cb4:	68bb      	ldr	r3, [r7, #8]
+ 8006cb6:	2b00      	cmp	r3, #0
+ 8006cb8:	d002      	beq.n	8006cc0 <HAL_UART_Transmit+0x2c>
+ 8006cba:	88fb      	ldrh	r3, [r7, #6]
+ 8006cbc:	2b00      	cmp	r3, #0
+ 8006cbe:	d101      	bne.n	8006cc4 <HAL_UART_Transmit+0x30>
     {
       return  HAL_ERROR;
- 80051a4:	2301      	movs	r3, #1
- 80051a6:	e06e      	b.n	8005286 <HAL_UART_Transmit+0x10e>
+ 8006cc0:	2301      	movs	r3, #1
+ 8006cc2:	e06e      	b.n	8006da2 <HAL_UART_Transmit+0x10e>
     }
 
     huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80051a8:	68fb      	ldr	r3, [r7, #12]
- 80051aa:	2200      	movs	r2, #0
- 80051ac:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006cc4:	68fb      	ldr	r3, [r7, #12]
+ 8006cc6:	2200      	movs	r2, #0
+ 8006cc8:	645a      	str	r2, [r3, #68]	@ 0x44
     huart->gState = HAL_UART_STATE_BUSY_TX;
- 80051ae:	68fb      	ldr	r3, [r7, #12]
- 80051b0:	2221      	movs	r2, #33	@ 0x21
- 80051b2:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006cca:	68fb      	ldr	r3, [r7, #12]
+ 8006ccc:	2221      	movs	r2, #33	@ 0x21
+ 8006cce:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
     /* Init tickstart for timeout management */
     tickstart = HAL_GetTick();
- 80051b6:	f7fd fcc7 	bl	8002b48 <HAL_GetTick>
- 80051ba:	6178      	str	r0, [r7, #20]
+ 8006cd2:	f7fc faff 	bl	80032d4 <HAL_GetTick>
+ 8006cd6:	6178      	str	r0, [r7, #20]
 
     huart->TxXferSize = Size;
- 80051bc:	68fb      	ldr	r3, [r7, #12]
- 80051be:	88fa      	ldrh	r2, [r7, #6]
- 80051c0:	849a      	strh	r2, [r3, #36]	@ 0x24
+ 8006cd8:	68fb      	ldr	r3, [r7, #12]
+ 8006cda:	88fa      	ldrh	r2, [r7, #6]
+ 8006cdc:	849a      	strh	r2, [r3, #36]	@ 0x24
     huart->TxXferCount = Size;
- 80051c2:	68fb      	ldr	r3, [r7, #12]
- 80051c4:	88fa      	ldrh	r2, [r7, #6]
- 80051c6:	84da      	strh	r2, [r3, #38]	@ 0x26
+ 8006cde:	68fb      	ldr	r3, [r7, #12]
+ 8006ce0:	88fa      	ldrh	r2, [r7, #6]
+ 8006ce2:	84da      	strh	r2, [r3, #38]	@ 0x26
 
     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 80051c8:	68fb      	ldr	r3, [r7, #12]
- 80051ca:	689b      	ldr	r3, [r3, #8]
- 80051cc:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
- 80051d0:	d108      	bne.n	80051e4 <HAL_UART_Transmit+0x6c>
- 80051d2:	68fb      	ldr	r3, [r7, #12]
- 80051d4:	691b      	ldr	r3, [r3, #16]
- 80051d6:	2b00      	cmp	r3, #0
- 80051d8:	d104      	bne.n	80051e4 <HAL_UART_Transmit+0x6c>
+ 8006ce4:	68fb      	ldr	r3, [r7, #12]
+ 8006ce6:	689b      	ldr	r3, [r3, #8]
+ 8006ce8:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 8006cec:	d108      	bne.n	8006d00 <HAL_UART_Transmit+0x6c>
+ 8006cee:	68fb      	ldr	r3, [r7, #12]
+ 8006cf0:	691b      	ldr	r3, [r3, #16]
+ 8006cf2:	2b00      	cmp	r3, #0
+ 8006cf4:	d104      	bne.n	8006d00 <HAL_UART_Transmit+0x6c>
     {
       pdata8bits  = NULL;
- 80051da:	2300      	movs	r3, #0
- 80051dc:	61fb      	str	r3, [r7, #28]
+ 8006cf6:	2300      	movs	r3, #0
+ 8006cf8:	61fb      	str	r3, [r7, #28]
       pdata16bits = (const uint16_t *) pData;
- 80051de:	68bb      	ldr	r3, [r7, #8]
- 80051e0:	61bb      	str	r3, [r7, #24]
- 80051e2:	e003      	b.n	80051ec <HAL_UART_Transmit+0x74>
+ 8006cfa:	68bb      	ldr	r3, [r7, #8]
+ 8006cfc:	61bb      	str	r3, [r7, #24]
+ 8006cfe:	e003      	b.n	8006d08 <HAL_UART_Transmit+0x74>
     }
     else
     {
       pdata8bits  = pData;
- 80051e4:	68bb      	ldr	r3, [r7, #8]
- 80051e6:	61fb      	str	r3, [r7, #28]
+ 8006d00:	68bb      	ldr	r3, [r7, #8]
+ 8006d02:	61fb      	str	r3, [r7, #28]
       pdata16bits = NULL;
- 80051e8:	2300      	movs	r3, #0
- 80051ea:	61bb      	str	r3, [r7, #24]
+ 8006d04:	2300      	movs	r3, #0
+ 8006d06:	61bb      	str	r3, [r7, #24]
     }
 
     while (huart->TxXferCount > 0U)
- 80051ec:	e02e      	b.n	800524c <HAL_UART_Transmit+0xd4>
+ 8006d08:	e02e      	b.n	8006d68 <HAL_UART_Transmit+0xd4>
     {
       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 80051ee:	683b      	ldr	r3, [r7, #0]
- 80051f0:	9300      	str	r3, [sp, #0]
- 80051f2:	697b      	ldr	r3, [r7, #20]
- 80051f4:	2200      	movs	r2, #0
- 80051f6:	2180      	movs	r1, #128	@ 0x80
- 80051f8:	68f8      	ldr	r0, [r7, #12]
- 80051fa:	f000 fb01 	bl	8005800 <UART_WaitOnFlagUntilTimeout>
- 80051fe:	4603      	mov	r3, r0
- 8005200:	2b00      	cmp	r3, #0
- 8005202:	d005      	beq.n	8005210 <HAL_UART_Transmit+0x98>
+ 8006d0a:	683b      	ldr	r3, [r7, #0]
+ 8006d0c:	9300      	str	r3, [sp, #0]
+ 8006d0e:	697b      	ldr	r3, [r7, #20]
+ 8006d10:	2200      	movs	r2, #0
+ 8006d12:	2180      	movs	r1, #128	@ 0x80
+ 8006d14:	68f8      	ldr	r0, [r7, #12]
+ 8006d16:	f000 fb01 	bl	800731c <UART_WaitOnFlagUntilTimeout>
+ 8006d1a:	4603      	mov	r3, r0
+ 8006d1c:	2b00      	cmp	r3, #0
+ 8006d1e:	d005      	beq.n	8006d2c <HAL_UART_Transmit+0x98>
       {
         huart->gState = HAL_UART_STATE_READY;
- 8005204:	68fb      	ldr	r3, [r7, #12]
- 8005206:	2220      	movs	r2, #32
- 8005208:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006d20:	68fb      	ldr	r3, [r7, #12]
+ 8006d22:	2220      	movs	r2, #32
+ 8006d24:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
         return HAL_TIMEOUT;
- 800520c:	2303      	movs	r3, #3
- 800520e:	e03a      	b.n	8005286 <HAL_UART_Transmit+0x10e>
+ 8006d28:	2303      	movs	r3, #3
+ 8006d2a:	e03a      	b.n	8006da2 <HAL_UART_Transmit+0x10e>
       }
       if (pdata8bits == NULL)
- 8005210:	69fb      	ldr	r3, [r7, #28]
- 8005212:	2b00      	cmp	r3, #0
- 8005214:	d10b      	bne.n	800522e <HAL_UART_Transmit+0xb6>
+ 8006d2c:	69fb      	ldr	r3, [r7, #28]
+ 8006d2e:	2b00      	cmp	r3, #0
+ 8006d30:	d10b      	bne.n	8006d4a <HAL_UART_Transmit+0xb6>
       {
         huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
- 8005216:	69bb      	ldr	r3, [r7, #24]
- 8005218:	881b      	ldrh	r3, [r3, #0]
- 800521a:	461a      	mov	r2, r3
- 800521c:	68fb      	ldr	r3, [r7, #12]
- 800521e:	681b      	ldr	r3, [r3, #0]
- 8005220:	f3c2 0208 	ubfx	r2, r2, #0, #9
- 8005224:	605a      	str	r2, [r3, #4]
+ 8006d32:	69bb      	ldr	r3, [r7, #24]
+ 8006d34:	881b      	ldrh	r3, [r3, #0]
+ 8006d36:	461a      	mov	r2, r3
+ 8006d38:	68fb      	ldr	r3, [r7, #12]
+ 8006d3a:	681b      	ldr	r3, [r3, #0]
+ 8006d3c:	f3c2 0208 	ubfx	r2, r2, #0, #9
+ 8006d40:	605a      	str	r2, [r3, #4]
         pdata16bits++;
- 8005226:	69bb      	ldr	r3, [r7, #24]
- 8005228:	3302      	adds	r3, #2
- 800522a:	61bb      	str	r3, [r7, #24]
- 800522c:	e007      	b.n	800523e <HAL_UART_Transmit+0xc6>
+ 8006d42:	69bb      	ldr	r3, [r7, #24]
+ 8006d44:	3302      	adds	r3, #2
+ 8006d46:	61bb      	str	r3, [r7, #24]
+ 8006d48:	e007      	b.n	8006d5a <HAL_UART_Transmit+0xc6>
       }
       else
       {
         huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
- 800522e:	69fb      	ldr	r3, [r7, #28]
- 8005230:	781a      	ldrb	r2, [r3, #0]
- 8005232:	68fb      	ldr	r3, [r7, #12]
- 8005234:	681b      	ldr	r3, [r3, #0]
- 8005236:	605a      	str	r2, [r3, #4]
+ 8006d4a:	69fb      	ldr	r3, [r7, #28]
+ 8006d4c:	781a      	ldrb	r2, [r3, #0]
+ 8006d4e:	68fb      	ldr	r3, [r7, #12]
+ 8006d50:	681b      	ldr	r3, [r3, #0]
+ 8006d52:	605a      	str	r2, [r3, #4]
         pdata8bits++;
- 8005238:	69fb      	ldr	r3, [r7, #28]
- 800523a:	3301      	adds	r3, #1
- 800523c:	61fb      	str	r3, [r7, #28]
+ 8006d54:	69fb      	ldr	r3, [r7, #28]
+ 8006d56:	3301      	adds	r3, #1
+ 8006d58:	61fb      	str	r3, [r7, #28]
       }
       huart->TxXferCount--;
- 800523e:	68fb      	ldr	r3, [r7, #12]
- 8005240:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
- 8005242:	b29b      	uxth	r3, r3
- 8005244:	3b01      	subs	r3, #1
- 8005246:	b29a      	uxth	r2, r3
- 8005248:	68fb      	ldr	r3, [r7, #12]
- 800524a:	84da      	strh	r2, [r3, #38]	@ 0x26
+ 8006d5a:	68fb      	ldr	r3, [r7, #12]
+ 8006d5c:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
+ 8006d5e:	b29b      	uxth	r3, r3
+ 8006d60:	3b01      	subs	r3, #1
+ 8006d62:	b29a      	uxth	r2, r3
+ 8006d64:	68fb      	ldr	r3, [r7, #12]
+ 8006d66:	84da      	strh	r2, [r3, #38]	@ 0x26
     while (huart->TxXferCount > 0U)
- 800524c:	68fb      	ldr	r3, [r7, #12]
- 800524e:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
- 8005250:	b29b      	uxth	r3, r3
- 8005252:	2b00      	cmp	r3, #0
- 8005254:	d1cb      	bne.n	80051ee <HAL_UART_Transmit+0x76>
+ 8006d68:	68fb      	ldr	r3, [r7, #12]
+ 8006d6a:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
+ 8006d6c:	b29b      	uxth	r3, r3
+ 8006d6e:	2b00      	cmp	r3, #0
+ 8006d70:	d1cb      	bne.n	8006d0a <HAL_UART_Transmit+0x76>
     }
 
     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8005256:	683b      	ldr	r3, [r7, #0]
- 8005258:	9300      	str	r3, [sp, #0]
- 800525a:	697b      	ldr	r3, [r7, #20]
- 800525c:	2200      	movs	r2, #0
- 800525e:	2140      	movs	r1, #64	@ 0x40
- 8005260:	68f8      	ldr	r0, [r7, #12]
- 8005262:	f000 facd 	bl	8005800 <UART_WaitOnFlagUntilTimeout>
- 8005266:	4603      	mov	r3, r0
- 8005268:	2b00      	cmp	r3, #0
- 800526a:	d005      	beq.n	8005278 <HAL_UART_Transmit+0x100>
+ 8006d72:	683b      	ldr	r3, [r7, #0]
+ 8006d74:	9300      	str	r3, [sp, #0]
+ 8006d76:	697b      	ldr	r3, [r7, #20]
+ 8006d78:	2200      	movs	r2, #0
+ 8006d7a:	2140      	movs	r1, #64	@ 0x40
+ 8006d7c:	68f8      	ldr	r0, [r7, #12]
+ 8006d7e:	f000 facd 	bl	800731c <UART_WaitOnFlagUntilTimeout>
+ 8006d82:	4603      	mov	r3, r0
+ 8006d84:	2b00      	cmp	r3, #0
+ 8006d86:	d005      	beq.n	8006d94 <HAL_UART_Transmit+0x100>
     {
       huart->gState = HAL_UART_STATE_READY;
- 800526c:	68fb      	ldr	r3, [r7, #12]
- 800526e:	2220      	movs	r2, #32
- 8005270:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006d88:	68fb      	ldr	r3, [r7, #12]
+ 8006d8a:	2220      	movs	r2, #32
+ 8006d8c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
       return HAL_TIMEOUT;
- 8005274:	2303      	movs	r3, #3
- 8005276:	e006      	b.n	8005286 <HAL_UART_Transmit+0x10e>
+ 8006d90:	2303      	movs	r3, #3
+ 8006d92:	e006      	b.n	8006da2 <HAL_UART_Transmit+0x10e>
     }
 
     /* At end of Tx process, restore huart->gState to Ready */
     huart->gState = HAL_UART_STATE_READY;
- 8005278:	68fb      	ldr	r3, [r7, #12]
- 800527a:	2220      	movs	r2, #32
- 800527c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8006d94:	68fb      	ldr	r3, [r7, #12]
+ 8006d96:	2220      	movs	r2, #32
+ 8006d98:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
     return HAL_OK;
- 8005280:	2300      	movs	r3, #0
- 8005282:	e000      	b.n	8005286 <HAL_UART_Transmit+0x10e>
+ 8006d9c:	2300      	movs	r3, #0
+ 8006d9e:	e000      	b.n	8006da2 <HAL_UART_Transmit+0x10e>
   }
   else
   {
     return HAL_BUSY;
- 8005284:	2302      	movs	r3, #2
+ 8006da0:	2302      	movs	r3, #2
   }
 }
- 8005286:	4618      	mov	r0, r3
- 8005288:	3720      	adds	r7, #32
- 800528a:	46bd      	mov	sp, r7
- 800528c:	bd80      	pop	{r7, pc}
+ 8006da2:	4618      	mov	r0, r3
+ 8006da4:	3720      	adds	r7, #32
+ 8006da6:	46bd      	mov	sp, r7
+ 8006da8:	bd80      	pop	{r7, pc}
 	...
 
-08005290 <HAL_UART_IRQHandler>:
+08006dac <HAL_UART_IRQHandler>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
 {
- 8005290:	b580      	push	{r7, lr}
- 8005292:	b0ba      	sub	sp, #232	@ 0xe8
- 8005294:	af00      	add	r7, sp, #0
- 8005296:	6078      	str	r0, [r7, #4]
+ 8006dac:	b580      	push	{r7, lr}
+ 8006dae:	b0ba      	sub	sp, #232	@ 0xe8
+ 8006db0:	af00      	add	r7, sp, #0
+ 8006db2:	6078      	str	r0, [r7, #4]
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
- 8005298:	687b      	ldr	r3, [r7, #4]
- 800529a:	681b      	ldr	r3, [r3, #0]
- 800529c:	681b      	ldr	r3, [r3, #0]
- 800529e:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+ 8006db4:	687b      	ldr	r3, [r7, #4]
+ 8006db6:	681b      	ldr	r3, [r3, #0]
+ 8006db8:	681b      	ldr	r3, [r3, #0]
+ 8006dba:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
- 80052a2:	687b      	ldr	r3, [r7, #4]
- 80052a4:	681b      	ldr	r3, [r3, #0]
- 80052a6:	68db      	ldr	r3, [r3, #12]
- 80052a8:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+ 8006dbe:	687b      	ldr	r3, [r7, #4]
+ 8006dc0:	681b      	ldr	r3, [r3, #0]
+ 8006dc2:	68db      	ldr	r3, [r3, #12]
+ 8006dc4:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
- 80052ac:	687b      	ldr	r3, [r7, #4]
- 80052ae:	681b      	ldr	r3, [r3, #0]
- 80052b0:	695b      	ldr	r3, [r3, #20]
- 80052b2:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+ 8006dc8:	687b      	ldr	r3, [r7, #4]
+ 8006dca:	681b      	ldr	r3, [r3, #0]
+ 8006dcc:	695b      	ldr	r3, [r3, #20]
+ 8006dce:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
   uint32_t errorflags = 0x00U;
- 80052b6:	2300      	movs	r3, #0
- 80052b8:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+ 8006dd2:	2300      	movs	r3, #0
+ 8006dd4:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
   uint32_t dmarequest = 0x00U;
- 80052bc:	2300      	movs	r3, #0
- 80052be:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+ 8006dd8:	2300      	movs	r3, #0
+ 8006dda:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
 
   /* If no error occurs */
   errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- 80052c2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 80052c6:	f003 030f 	and.w	r3, r3, #15
- 80052ca:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+ 8006dde:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006de2:	f003 030f 	and.w	r3, r3, #15
+ 8006de6:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
   if (errorflags == RESET)
- 80052ce:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
- 80052d2:	2b00      	cmp	r3, #0
- 80052d4:	d10f      	bne.n	80052f6 <HAL_UART_IRQHandler+0x66>
+ 8006dea:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
+ 8006dee:	2b00      	cmp	r3, #0
+ 8006df0:	d10f      	bne.n	8006e12 <HAL_UART_IRQHandler+0x66>
   {
     /* UART in mode Receiver -------------------------------------------------*/
     if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- 80052d6:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 80052da:	f003 0320 	and.w	r3, r3, #32
- 80052de:	2b00      	cmp	r3, #0
- 80052e0:	d009      	beq.n	80052f6 <HAL_UART_IRQHandler+0x66>
- 80052e2:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 80052e6:	f003 0320 	and.w	r3, r3, #32
- 80052ea:	2b00      	cmp	r3, #0
- 80052ec:	d003      	beq.n	80052f6 <HAL_UART_IRQHandler+0x66>
+ 8006df2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006df6:	f003 0320 	and.w	r3, r3, #32
+ 8006dfa:	2b00      	cmp	r3, #0
+ 8006dfc:	d009      	beq.n	8006e12 <HAL_UART_IRQHandler+0x66>
+ 8006dfe:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006e02:	f003 0320 	and.w	r3, r3, #32
+ 8006e06:	2b00      	cmp	r3, #0
+ 8006e08:	d003      	beq.n	8006e12 <HAL_UART_IRQHandler+0x66>
     {
       UART_Receive_IT(huart);
- 80052ee:	6878      	ldr	r0, [r7, #4]
- 80052f0:	f000 fbbc 	bl	8005a6c <UART_Receive_IT>
+ 8006e0a:	6878      	ldr	r0, [r7, #4]
+ 8006e0c:	f000 fbbc 	bl	8007588 <UART_Receive_IT>
       return;
- 80052f4:	e25b      	b.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 8006e10:	e25b      	b.n	80072ca <HAL_UART_IRQHandler+0x51e>
     }
   }
 
   /* If some errors occur */
   if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
- 80052f6:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
- 80052fa:	2b00      	cmp	r3, #0
- 80052fc:	f000 80de 	beq.w	80054bc <HAL_UART_IRQHandler+0x22c>
- 8005300:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
- 8005304:	f003 0301 	and.w	r3, r3, #1
- 8005308:	2b00      	cmp	r3, #0
- 800530a:	d106      	bne.n	800531a <HAL_UART_IRQHandler+0x8a>
+ 8006e12:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
+ 8006e16:	2b00      	cmp	r3, #0
+ 8006e18:	f000 80de 	beq.w	8006fd8 <HAL_UART_IRQHandler+0x22c>
+ 8006e1c:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 8006e20:	f003 0301 	and.w	r3, r3, #1
+ 8006e24:	2b00      	cmp	r3, #0
+ 8006e26:	d106      	bne.n	8006e36 <HAL_UART_IRQHandler+0x8a>
                                 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- 800530c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 8005310:	f403 7390 	and.w	r3, r3, #288	@ 0x120
- 8005314:	2b00      	cmp	r3, #0
- 8005316:	f000 80d1 	beq.w	80054bc <HAL_UART_IRQHandler+0x22c>
+ 8006e28:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006e2c:	f403 7390 	and.w	r3, r3, #288	@ 0x120
+ 8006e30:	2b00      	cmp	r3, #0
+ 8006e32:	f000 80d1 	beq.w	8006fd8 <HAL_UART_IRQHandler+0x22c>
   {
     /* UART parity error interrupt occurred ----------------------------------*/
     if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- 800531a:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 800531e:	f003 0301 	and.w	r3, r3, #1
- 8005322:	2b00      	cmp	r3, #0
- 8005324:	d00b      	beq.n	800533e <HAL_UART_IRQHandler+0xae>
- 8005326:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 800532a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 800532e:	2b00      	cmp	r3, #0
- 8005330:	d005      	beq.n	800533e <HAL_UART_IRQHandler+0xae>
+ 8006e36:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006e3a:	f003 0301 	and.w	r3, r3, #1
+ 8006e3e:	2b00      	cmp	r3, #0
+ 8006e40:	d00b      	beq.n	8006e5a <HAL_UART_IRQHandler+0xae>
+ 8006e42:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006e46:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8006e4a:	2b00      	cmp	r3, #0
+ 8006e4c:	d005      	beq.n	8006e5a <HAL_UART_IRQHandler+0xae>
     {
       huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8005332:	687b      	ldr	r3, [r7, #4]
- 8005334:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 8005336:	f043 0201 	orr.w	r2, r3, #1
- 800533a:	687b      	ldr	r3, [r7, #4]
- 800533c:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006e4e:	687b      	ldr	r3, [r7, #4]
+ 8006e50:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006e52:	f043 0201 	orr.w	r2, r3, #1
+ 8006e56:	687b      	ldr	r3, [r7, #4]
+ 8006e58:	645a      	str	r2, [r3, #68]	@ 0x44
     }
 
     /* UART noise error interrupt occurred -----------------------------------*/
     if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- 800533e:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 8005342:	f003 0304 	and.w	r3, r3, #4
- 8005346:	2b00      	cmp	r3, #0
- 8005348:	d00b      	beq.n	8005362 <HAL_UART_IRQHandler+0xd2>
- 800534a:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
- 800534e:	f003 0301 	and.w	r3, r3, #1
- 8005352:	2b00      	cmp	r3, #0
- 8005354:	d005      	beq.n	8005362 <HAL_UART_IRQHandler+0xd2>
+ 8006e5a:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006e5e:	f003 0304 	and.w	r3, r3, #4
+ 8006e62:	2b00      	cmp	r3, #0
+ 8006e64:	d00b      	beq.n	8006e7e <HAL_UART_IRQHandler+0xd2>
+ 8006e66:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 8006e6a:	f003 0301 	and.w	r3, r3, #1
+ 8006e6e:	2b00      	cmp	r3, #0
+ 8006e70:	d005      	beq.n	8006e7e <HAL_UART_IRQHandler+0xd2>
     {
       huart->ErrorCode |= HAL_UART_ERROR_NE;
- 8005356:	687b      	ldr	r3, [r7, #4]
- 8005358:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 800535a:	f043 0202 	orr.w	r2, r3, #2
- 800535e:	687b      	ldr	r3, [r7, #4]
- 8005360:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006e72:	687b      	ldr	r3, [r7, #4]
+ 8006e74:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006e76:	f043 0202 	orr.w	r2, r3, #2
+ 8006e7a:	687b      	ldr	r3, [r7, #4]
+ 8006e7c:	645a      	str	r2, [r3, #68]	@ 0x44
     }
 
     /* UART frame error interrupt occurred -----------------------------------*/
     if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- 8005362:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 8005366:	f003 0302 	and.w	r3, r3, #2
- 800536a:	2b00      	cmp	r3, #0
- 800536c:	d00b      	beq.n	8005386 <HAL_UART_IRQHandler+0xf6>
- 800536e:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
- 8005372:	f003 0301 	and.w	r3, r3, #1
- 8005376:	2b00      	cmp	r3, #0
- 8005378:	d005      	beq.n	8005386 <HAL_UART_IRQHandler+0xf6>
+ 8006e7e:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006e82:	f003 0302 	and.w	r3, r3, #2
+ 8006e86:	2b00      	cmp	r3, #0
+ 8006e88:	d00b      	beq.n	8006ea2 <HAL_UART_IRQHandler+0xf6>
+ 8006e8a:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 8006e8e:	f003 0301 	and.w	r3, r3, #1
+ 8006e92:	2b00      	cmp	r3, #0
+ 8006e94:	d005      	beq.n	8006ea2 <HAL_UART_IRQHandler+0xf6>
     {
       huart->ErrorCode |= HAL_UART_ERROR_FE;
- 800537a:	687b      	ldr	r3, [r7, #4]
- 800537c:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 800537e:	f043 0204 	orr.w	r2, r3, #4
- 8005382:	687b      	ldr	r3, [r7, #4]
- 8005384:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006e96:	687b      	ldr	r3, [r7, #4]
+ 8006e98:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006e9a:	f043 0204 	orr.w	r2, r3, #4
+ 8006e9e:	687b      	ldr	r3, [r7, #4]
+ 8006ea0:	645a      	str	r2, [r3, #68]	@ 0x44
     }
 
     /* UART Over-Run interrupt occurred --------------------------------------*/
     if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
- 8005386:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 800538a:	f003 0308 	and.w	r3, r3, #8
- 800538e:	2b00      	cmp	r3, #0
- 8005390:	d011      	beq.n	80053b6 <HAL_UART_IRQHandler+0x126>
- 8005392:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 8005396:	f003 0320 	and.w	r3, r3, #32
- 800539a:	2b00      	cmp	r3, #0
- 800539c:	d105      	bne.n	80053aa <HAL_UART_IRQHandler+0x11a>
+ 8006ea2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006ea6:	f003 0308 	and.w	r3, r3, #8
+ 8006eaa:	2b00      	cmp	r3, #0
+ 8006eac:	d011      	beq.n	8006ed2 <HAL_UART_IRQHandler+0x126>
+ 8006eae:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006eb2:	f003 0320 	and.w	r3, r3, #32
+ 8006eb6:	2b00      	cmp	r3, #0
+ 8006eb8:	d105      	bne.n	8006ec6 <HAL_UART_IRQHandler+0x11a>
                                                  || ((cr3its & USART_CR3_EIE) != RESET)))
- 800539e:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
- 80053a2:	f003 0301 	and.w	r3, r3, #1
- 80053a6:	2b00      	cmp	r3, #0
- 80053a8:	d005      	beq.n	80053b6 <HAL_UART_IRQHandler+0x126>
+ 8006eba:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 8006ebe:	f003 0301 	and.w	r3, r3, #1
+ 8006ec2:	2b00      	cmp	r3, #0
+ 8006ec4:	d005      	beq.n	8006ed2 <HAL_UART_IRQHandler+0x126>
     {
       huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 80053aa:	687b      	ldr	r3, [r7, #4]
- 80053ac:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80053ae:	f043 0208 	orr.w	r2, r3, #8
- 80053b2:	687b      	ldr	r3, [r7, #4]
- 80053b4:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006ec6:	687b      	ldr	r3, [r7, #4]
+ 8006ec8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006eca:	f043 0208 	orr.w	r2, r3, #8
+ 8006ece:	687b      	ldr	r3, [r7, #4]
+ 8006ed0:	645a      	str	r2, [r3, #68]	@ 0x44
     }
 
     /* Call UART Error Call back function if need be --------------------------*/
     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 80053b6:	687b      	ldr	r3, [r7, #4]
- 80053b8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80053ba:	2b00      	cmp	r3, #0
- 80053bc:	f000 81f2 	beq.w	80057a4 <HAL_UART_IRQHandler+0x514>
+ 8006ed2:	687b      	ldr	r3, [r7, #4]
+ 8006ed4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006ed6:	2b00      	cmp	r3, #0
+ 8006ed8:	f000 81f2 	beq.w	80072c0 <HAL_UART_IRQHandler+0x514>
     {
       /* UART in mode Receiver -----------------------------------------------*/
       if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- 80053c0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 80053c4:	f003 0320 	and.w	r3, r3, #32
- 80053c8:	2b00      	cmp	r3, #0
- 80053ca:	d008      	beq.n	80053de <HAL_UART_IRQHandler+0x14e>
- 80053cc:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 80053d0:	f003 0320 	and.w	r3, r3, #32
- 80053d4:	2b00      	cmp	r3, #0
- 80053d6:	d002      	beq.n	80053de <HAL_UART_IRQHandler+0x14e>
+ 8006edc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006ee0:	f003 0320 	and.w	r3, r3, #32
+ 8006ee4:	2b00      	cmp	r3, #0
+ 8006ee6:	d008      	beq.n	8006efa <HAL_UART_IRQHandler+0x14e>
+ 8006ee8:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006eec:	f003 0320 	and.w	r3, r3, #32
+ 8006ef0:	2b00      	cmp	r3, #0
+ 8006ef2:	d002      	beq.n	8006efa <HAL_UART_IRQHandler+0x14e>
       {
         UART_Receive_IT(huart);
- 80053d8:	6878      	ldr	r0, [r7, #4]
- 80053da:	f000 fb47 	bl	8005a6c <UART_Receive_IT>
+ 8006ef4:	6878      	ldr	r0, [r7, #4]
+ 8006ef6:	f000 fb47 	bl	8007588 <UART_Receive_IT>
       }
 
       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
          consider error as blocking */
       dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- 80053de:	687b      	ldr	r3, [r7, #4]
- 80053e0:	681b      	ldr	r3, [r3, #0]
- 80053e2:	695b      	ldr	r3, [r3, #20]
- 80053e4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 80053e8:	2b00      	cmp	r3, #0
- 80053ea:	bf14      	ite	ne
- 80053ec:	2301      	movne	r3, #1
- 80053ee:	2300      	moveq	r3, #0
- 80053f0:	b2db      	uxtb	r3, r3
- 80053f2:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+ 8006efa:	687b      	ldr	r3, [r7, #4]
+ 8006efc:	681b      	ldr	r3, [r3, #0]
+ 8006efe:	695b      	ldr	r3, [r3, #20]
+ 8006f00:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8006f04:	2b00      	cmp	r3, #0
+ 8006f06:	bf14      	ite	ne
+ 8006f08:	2301      	movne	r3, #1
+ 8006f0a:	2300      	moveq	r3, #0
+ 8006f0c:	b2db      	uxtb	r3, r3
+ 8006f0e:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
       if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
- 80053f6:	687b      	ldr	r3, [r7, #4]
- 80053f8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80053fa:	f003 0308 	and.w	r3, r3, #8
- 80053fe:	2b00      	cmp	r3, #0
- 8005400:	d103      	bne.n	800540a <HAL_UART_IRQHandler+0x17a>
- 8005402:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
- 8005406:	2b00      	cmp	r3, #0
- 8005408:	d04f      	beq.n	80054aa <HAL_UART_IRQHandler+0x21a>
+ 8006f12:	687b      	ldr	r3, [r7, #4]
+ 8006f14:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8006f16:	f003 0308 	and.w	r3, r3, #8
+ 8006f1a:	2b00      	cmp	r3, #0
+ 8006f1c:	d103      	bne.n	8006f26 <HAL_UART_IRQHandler+0x17a>
+ 8006f1e:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
+ 8006f22:	2b00      	cmp	r3, #0
+ 8006f24:	d04f      	beq.n	8006fc6 <HAL_UART_IRQHandler+0x21a>
       {
         /* Blocking error : transfer is aborted
            Set the UART state ready to be able to start again the process,
            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
         UART_EndRxTransfer(huart);
- 800540a:	6878      	ldr	r0, [r7, #4]
- 800540c:	f000 fa51 	bl	80058b2 <UART_EndRxTransfer>
+ 8006f26:	6878      	ldr	r0, [r7, #4]
+ 8006f28:	f000 fa51 	bl	80073ce <UART_EndRxTransfer>
 
         /* Disable the UART DMA Rx request if enabled */
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8005410:	687b      	ldr	r3, [r7, #4]
- 8005412:	681b      	ldr	r3, [r3, #0]
- 8005414:	695b      	ldr	r3, [r3, #20]
- 8005416:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 800541a:	2b00      	cmp	r3, #0
- 800541c:	d041      	beq.n	80054a2 <HAL_UART_IRQHandler+0x212>
+ 8006f2c:	687b      	ldr	r3, [r7, #4]
+ 8006f2e:	681b      	ldr	r3, [r3, #0]
+ 8006f30:	695b      	ldr	r3, [r3, #20]
+ 8006f32:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8006f36:	2b00      	cmp	r3, #0
+ 8006f38:	d041      	beq.n	8006fbe <HAL_UART_IRQHandler+0x212>
         {
           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 800541e:	687b      	ldr	r3, [r7, #4]
- 8005420:	681b      	ldr	r3, [r3, #0]
- 8005422:	3314      	adds	r3, #20
- 8005424:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
+ 8006f3a:	687b      	ldr	r3, [r7, #4]
+ 8006f3c:	681b      	ldr	r3, [r3, #0]
+ 8006f3e:	3314      	adds	r3, #20
+ 8006f40:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
  */
 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 {
     uint32_t result;
 
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005428:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
- 800542c:	e853 3f00 	ldrex	r3, [r3]
- 8005430:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
+ 8006f44:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
+ 8006f48:	e853 3f00 	ldrex	r3, [r3]
+ 8006f4c:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
    return(result);
- 8005434:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
- 8005438:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
- 800543c:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
- 8005440:	687b      	ldr	r3, [r7, #4]
- 8005442:	681b      	ldr	r3, [r3, #0]
- 8005444:	3314      	adds	r3, #20
- 8005446:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
- 800544a:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
- 800544e:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
+ 8006f50:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
+ 8006f54:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
+ 8006f58:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
+ 8006f5c:	687b      	ldr	r3, [r7, #4]
+ 8006f5e:	681b      	ldr	r3, [r3, #0]
+ 8006f60:	3314      	adds	r3, #20
+ 8006f62:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
+ 8006f66:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
+ 8006f6a:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
  */
 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 {
    uint32_t result;
 
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005452:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
- 8005456:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
- 800545a:	e841 2300 	strex	r3, r2, [r1]
- 800545e:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
+ 8006f6e:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
+ 8006f72:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
+ 8006f76:	e841 2300 	strex	r3, r2, [r1]
+ 8006f7a:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    return(result);
- 8005462:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
- 8005466:	2b00      	cmp	r3, #0
- 8005468:	d1d9      	bne.n	800541e <HAL_UART_IRQHandler+0x18e>
+ 8006f7e:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
+ 8006f82:	2b00      	cmp	r3, #0
+ 8006f84:	d1d9      	bne.n	8006f3a <HAL_UART_IRQHandler+0x18e>
 
           /* Abort the UART DMA Rx channel */
           if (huart->hdmarx != NULL)
- 800546a:	687b      	ldr	r3, [r7, #4]
- 800546c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 800546e:	2b00      	cmp	r3, #0
- 8005470:	d013      	beq.n	800549a <HAL_UART_IRQHandler+0x20a>
+ 8006f86:	687b      	ldr	r3, [r7, #4]
+ 8006f88:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8006f8a:	2b00      	cmp	r3, #0
+ 8006f8c:	d013      	beq.n	8006fb6 <HAL_UART_IRQHandler+0x20a>
           {
             /* Set the UART DMA Abort callback :
                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8005472:	687b      	ldr	r3, [r7, #4]
- 8005474:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 8005476:	4a7e      	ldr	r2, [pc, #504]	@ (8005670 <HAL_UART_IRQHandler+0x3e0>)
- 8005478:	635a      	str	r2, [r3, #52]	@ 0x34
+ 8006f8e:	687b      	ldr	r3, [r7, #4]
+ 8006f90:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8006f92:	4a7e      	ldr	r2, [pc, #504]	@ (800718c <HAL_UART_IRQHandler+0x3e0>)
+ 8006f94:	635a      	str	r2, [r3, #52]	@ 0x34
             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 800547a:	687b      	ldr	r3, [r7, #4]
- 800547c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 800547e:	4618      	mov	r0, r3
- 8005480:	f7fd feea 	bl	8003258 <HAL_DMA_Abort_IT>
- 8005484:	4603      	mov	r3, r0
- 8005486:	2b00      	cmp	r3, #0
- 8005488:	d016      	beq.n	80054b8 <HAL_UART_IRQHandler+0x228>
+ 8006f96:	687b      	ldr	r3, [r7, #4]
+ 8006f98:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8006f9a:	4618      	mov	r0, r3
+ 8006f9c:	f7fd f83c 	bl	8004018 <HAL_DMA_Abort_IT>
+ 8006fa0:	4603      	mov	r3, r0
+ 8006fa2:	2b00      	cmp	r3, #0
+ 8006fa4:	d016      	beq.n	8006fd4 <HAL_UART_IRQHandler+0x228>
             {
               /* Call Directly XferAbortCallback function in case of error */
               huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 800548a:	687b      	ldr	r3, [r7, #4]
- 800548c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 800548e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8005490:	687a      	ldr	r2, [r7, #4]
- 8005492:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
- 8005494:	4610      	mov	r0, r2
- 8005496:	4798      	blx	r3
+ 8006fa6:	687b      	ldr	r3, [r7, #4]
+ 8006fa8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8006faa:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8006fac:	687a      	ldr	r2, [r7, #4]
+ 8006fae:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
+ 8006fb0:	4610      	mov	r0, r2
+ 8006fb2:	4798      	blx	r3
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8005498:	e00e      	b.n	80054b8 <HAL_UART_IRQHandler+0x228>
+ 8006fb4:	e00e      	b.n	8006fd4 <HAL_UART_IRQHandler+0x228>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
             /*Call registered error callback*/
             huart->ErrorCallback(huart);
 #else
             /*Call legacy weak error callback*/
             HAL_UART_ErrorCallback(huart);
- 800549a:	6878      	ldr	r0, [r7, #4]
- 800549c:	f000 f99c 	bl	80057d8 <HAL_UART_ErrorCallback>
+ 8006fb6:	6878      	ldr	r0, [r7, #4]
+ 8006fb8:	f000 f99c 	bl	80072f4 <HAL_UART_ErrorCallback>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80054a0:	e00a      	b.n	80054b8 <HAL_UART_IRQHandler+0x228>
+ 8006fbc:	e00a      	b.n	8006fd4 <HAL_UART_IRQHandler+0x228>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
           /*Call registered error callback*/
           huart->ErrorCallback(huart);
 #else
           /*Call legacy weak error callback*/
           HAL_UART_ErrorCallback(huart);
- 80054a2:	6878      	ldr	r0, [r7, #4]
- 80054a4:	f000 f998 	bl	80057d8 <HAL_UART_ErrorCallback>
+ 8006fbe:	6878      	ldr	r0, [r7, #4]
+ 8006fc0:	f000 f998 	bl	80072f4 <HAL_UART_ErrorCallback>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80054a8:	e006      	b.n	80054b8 <HAL_UART_IRQHandler+0x228>
+ 8006fc4:	e006      	b.n	8006fd4 <HAL_UART_IRQHandler+0x228>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered error callback*/
         huart->ErrorCallback(huart);
 #else
         /*Call legacy weak error callback*/
         HAL_UART_ErrorCallback(huart);
- 80054aa:	6878      	ldr	r0, [r7, #4]
- 80054ac:	f000 f994 	bl	80057d8 <HAL_UART_ErrorCallback>
+ 8006fc6:	6878      	ldr	r0, [r7, #4]
+ 8006fc8:	f000 f994 	bl	80072f4 <HAL_UART_ErrorCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 
         huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80054b0:	687b      	ldr	r3, [r7, #4]
- 80054b2:	2200      	movs	r2, #0
- 80054b4:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8006fcc:	687b      	ldr	r3, [r7, #4]
+ 8006fce:	2200      	movs	r2, #0
+ 8006fd0:	645a      	str	r2, [r3, #68]	@ 0x44
       }
     }
     return;
- 80054b6:	e175      	b.n	80057a4 <HAL_UART_IRQHandler+0x514>
+ 8006fd2:	e175      	b.n	80072c0 <HAL_UART_IRQHandler+0x514>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80054b8:	bf00      	nop
+ 8006fd4:	bf00      	nop
     return;
- 80054ba:	e173      	b.n	80057a4 <HAL_UART_IRQHandler+0x514>
+ 8006fd6:	e173      	b.n	80072c0 <HAL_UART_IRQHandler+0x514>
   } /* End if some error occurs */
 
   /* Check current reception Mode :
      If Reception till IDLE event has been selected : */
   if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 80054bc:	687b      	ldr	r3, [r7, #4]
- 80054be:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 80054c0:	2b01      	cmp	r3, #1
- 80054c2:	f040 814f 	bne.w	8005764 <HAL_UART_IRQHandler+0x4d4>
+ 8006fd8:	687b      	ldr	r3, [r7, #4]
+ 8006fda:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8006fdc:	2b01      	cmp	r3, #1
+ 8006fde:	f040 814f 	bne.w	8007280 <HAL_UART_IRQHandler+0x4d4>
       && ((isrflags & USART_SR_IDLE) != 0U)
- 80054c6:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 80054ca:	f003 0310 	and.w	r3, r3, #16
- 80054ce:	2b00      	cmp	r3, #0
- 80054d0:	f000 8148 	beq.w	8005764 <HAL_UART_IRQHandler+0x4d4>
+ 8006fe2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8006fe6:	f003 0310 	and.w	r3, r3, #16
+ 8006fea:	2b00      	cmp	r3, #0
+ 8006fec:	f000 8148 	beq.w	8007280 <HAL_UART_IRQHandler+0x4d4>
       && ((cr1its & USART_SR_IDLE) != 0U))
- 80054d4:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 80054d8:	f003 0310 	and.w	r3, r3, #16
- 80054dc:	2b00      	cmp	r3, #0
- 80054de:	f000 8141 	beq.w	8005764 <HAL_UART_IRQHandler+0x4d4>
+ 8006ff0:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8006ff4:	f003 0310 	and.w	r3, r3, #16
+ 8006ff8:	2b00      	cmp	r3, #0
+ 8006ffa:	f000 8141 	beq.w	8007280 <HAL_UART_IRQHandler+0x4d4>
   {
     __HAL_UART_CLEAR_IDLEFLAG(huart);
- 80054e2:	2300      	movs	r3, #0
- 80054e4:	60bb      	str	r3, [r7, #8]
- 80054e6:	687b      	ldr	r3, [r7, #4]
- 80054e8:	681b      	ldr	r3, [r3, #0]
- 80054ea:	681b      	ldr	r3, [r3, #0]
- 80054ec:	60bb      	str	r3, [r7, #8]
- 80054ee:	687b      	ldr	r3, [r7, #4]
- 80054f0:	681b      	ldr	r3, [r3, #0]
- 80054f2:	685b      	ldr	r3, [r3, #4]
- 80054f4:	60bb      	str	r3, [r7, #8]
- 80054f6:	68bb      	ldr	r3, [r7, #8]
+ 8006ffe:	2300      	movs	r3, #0
+ 8007000:	60bb      	str	r3, [r7, #8]
+ 8007002:	687b      	ldr	r3, [r7, #4]
+ 8007004:	681b      	ldr	r3, [r3, #0]
+ 8007006:	681b      	ldr	r3, [r3, #0]
+ 8007008:	60bb      	str	r3, [r7, #8]
+ 800700a:	687b      	ldr	r3, [r7, #4]
+ 800700c:	681b      	ldr	r3, [r3, #0]
+ 800700e:	685b      	ldr	r3, [r3, #4]
+ 8007010:	60bb      	str	r3, [r7, #8]
+ 8007012:	68bb      	ldr	r3, [r7, #8]
 
     /* Check if DMA mode is enabled in UART */
     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80054f8:	687b      	ldr	r3, [r7, #4]
- 80054fa:	681b      	ldr	r3, [r3, #0]
- 80054fc:	695b      	ldr	r3, [r3, #20]
- 80054fe:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 8005502:	2b00      	cmp	r3, #0
- 8005504:	f000 80b6 	beq.w	8005674 <HAL_UART_IRQHandler+0x3e4>
+ 8007014:	687b      	ldr	r3, [r7, #4]
+ 8007016:	681b      	ldr	r3, [r3, #0]
+ 8007018:	695b      	ldr	r3, [r3, #20]
+ 800701a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 800701e:	2b00      	cmp	r3, #0
+ 8007020:	f000 80b6 	beq.w	8007190 <HAL_UART_IRQHandler+0x3e4>
     {
       /* DMA mode enabled */
       /* Check received length : If all expected data are received, do nothing,
          (DMA cplt callback will be called).
          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
       uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
- 8005508:	687b      	ldr	r3, [r7, #4]
- 800550a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 800550c:	681b      	ldr	r3, [r3, #0]
- 800550e:	685b      	ldr	r3, [r3, #4]
- 8005510:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
+ 8007024:	687b      	ldr	r3, [r7, #4]
+ 8007026:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8007028:	681b      	ldr	r3, [r3, #0]
+ 800702a:	685b      	ldr	r3, [r3, #4]
+ 800702c:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
       if ((nb_remaining_rx_data > 0U)
- 8005514:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
- 8005518:	2b00      	cmp	r3, #0
- 800551a:	f000 8145 	beq.w	80057a8 <HAL_UART_IRQHandler+0x518>
+ 8007030:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
+ 8007034:	2b00      	cmp	r3, #0
+ 8007036:	f000 8145 	beq.w	80072c4 <HAL_UART_IRQHandler+0x518>
           && (nb_remaining_rx_data < huart->RxXferSize))
- 800551e:	687b      	ldr	r3, [r7, #4]
- 8005520:	8d9b      	ldrh	r3, [r3, #44]	@ 0x2c
- 8005522:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
- 8005526:	429a      	cmp	r2, r3
- 8005528:	f080 813e 	bcs.w	80057a8 <HAL_UART_IRQHandler+0x518>
+ 800703a:	687b      	ldr	r3, [r7, #4]
+ 800703c:	8d9b      	ldrh	r3, [r3, #44]	@ 0x2c
+ 800703e:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
+ 8007042:	429a      	cmp	r2, r3
+ 8007044:	f080 813e 	bcs.w	80072c4 <HAL_UART_IRQHandler+0x518>
       {
         /* Reception is not complete */
         huart->RxXferCount = nb_remaining_rx_data;
- 800552c:	687b      	ldr	r3, [r7, #4]
- 800552e:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
- 8005532:	85da      	strh	r2, [r3, #46]	@ 0x2e
+ 8007048:	687b      	ldr	r3, [r7, #4]
+ 800704a:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
+ 800704e:	85da      	strh	r2, [r3, #46]	@ 0x2e
 
         /* In Normal mode, end DMA xfer and HAL UART Rx process*/
         if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
- 8005534:	687b      	ldr	r3, [r7, #4]
- 8005536:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 8005538:	699b      	ldr	r3, [r3, #24]
- 800553a:	2b20      	cmp	r3, #32
- 800553c:	f000 8088 	beq.w	8005650 <HAL_UART_IRQHandler+0x3c0>
+ 8007050:	687b      	ldr	r3, [r7, #4]
+ 8007052:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8007054:	699b      	ldr	r3, [r3, #24]
+ 8007056:	2b20      	cmp	r3, #32
+ 8007058:	f000 8088 	beq.w	800716c <HAL_UART_IRQHandler+0x3c0>
         {
           /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- 8005540:	687b      	ldr	r3, [r7, #4]
- 8005542:	681b      	ldr	r3, [r3, #0]
- 8005544:	330c      	adds	r3, #12
- 8005546:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+ 800705c:	687b      	ldr	r3, [r7, #4]
+ 800705e:	681b      	ldr	r3, [r3, #0]
+ 8007060:	330c      	adds	r3, #12
+ 8007062:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 800554a:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
- 800554e:	e853 3f00 	ldrex	r3, [r3]
- 8005552:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+ 8007066:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
+ 800706a:	e853 3f00 	ldrex	r3, [r3]
+ 800706e:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
    return(result);
- 8005556:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
- 800555a:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
- 800555e:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
- 8005562:	687b      	ldr	r3, [r7, #4]
- 8005564:	681b      	ldr	r3, [r3, #0]
- 8005566:	330c      	adds	r3, #12
- 8005568:	f8d7 20b8 	ldr.w	r2, [r7, #184]	@ 0xb8
- 800556c:	f8c7 2094 	str.w	r2, [r7, #148]	@ 0x94
- 8005570:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
+ 8007072:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
+ 8007076:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 800707a:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
+ 800707e:	687b      	ldr	r3, [r7, #4]
+ 8007080:	681b      	ldr	r3, [r3, #0]
+ 8007082:	330c      	adds	r3, #12
+ 8007084:	f8d7 20b8 	ldr.w	r2, [r7, #184]	@ 0xb8
+ 8007088:	f8c7 2094 	str.w	r2, [r7, #148]	@ 0x94
+ 800708c:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005574:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
- 8005578:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
- 800557c:	e841 2300 	strex	r3, r2, [r1]
- 8005580:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
+ 8007090:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
+ 8007094:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
+ 8007098:	e841 2300 	strex	r3, r2, [r1]
+ 800709c:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
    return(result);
- 8005584:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
- 8005588:	2b00      	cmp	r3, #0
- 800558a:	d1d9      	bne.n	8005540 <HAL_UART_IRQHandler+0x2b0>
+ 80070a0:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
+ 80070a4:	2b00      	cmp	r3, #0
+ 80070a6:	d1d9      	bne.n	800705c <HAL_UART_IRQHandler+0x2b0>
           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800558c:	687b      	ldr	r3, [r7, #4]
- 800558e:	681b      	ldr	r3, [r3, #0]
- 8005590:	3314      	adds	r3, #20
- 8005592:	677b      	str	r3, [r7, #116]	@ 0x74
+ 80070a8:	687b      	ldr	r3, [r7, #4]
+ 80070aa:	681b      	ldr	r3, [r3, #0]
+ 80070ac:	3314      	adds	r3, #20
+ 80070ae:	677b      	str	r3, [r7, #116]	@ 0x74
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005594:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
- 8005596:	e853 3f00 	ldrex	r3, [r3]
- 800559a:	673b      	str	r3, [r7, #112]	@ 0x70
+ 80070b0:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 80070b2:	e853 3f00 	ldrex	r3, [r3]
+ 80070b6:	673b      	str	r3, [r7, #112]	@ 0x70
    return(result);
- 800559c:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
- 800559e:	f023 0301 	bic.w	r3, r3, #1
- 80055a2:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
- 80055a6:	687b      	ldr	r3, [r7, #4]
- 80055a8:	681b      	ldr	r3, [r3, #0]
- 80055aa:	3314      	adds	r3, #20
- 80055ac:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
- 80055b0:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
- 80055b4:	67fb      	str	r3, [r7, #124]	@ 0x7c
+ 80070b8:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
+ 80070ba:	f023 0301 	bic.w	r3, r3, #1
+ 80070be:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+ 80070c2:	687b      	ldr	r3, [r7, #4]
+ 80070c4:	681b      	ldr	r3, [r3, #0]
+ 80070c6:	3314      	adds	r3, #20
+ 80070c8:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
+ 80070cc:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
+ 80070d0:	67fb      	str	r3, [r7, #124]	@ 0x7c
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 80055b6:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
- 80055b8:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
- 80055bc:	e841 2300 	strex	r3, r2, [r1]
- 80055c0:	67bb      	str	r3, [r7, #120]	@ 0x78
+ 80070d2:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
+ 80070d4:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
+ 80070d8:	e841 2300 	strex	r3, r2, [r1]
+ 80070dc:	67bb      	str	r3, [r7, #120]	@ 0x78
    return(result);
- 80055c2:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
- 80055c4:	2b00      	cmp	r3, #0
- 80055c6:	d1e1      	bne.n	800558c <HAL_UART_IRQHandler+0x2fc>
+ 80070de:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
+ 80070e0:	2b00      	cmp	r3, #0
+ 80070e2:	d1e1      	bne.n	80070a8 <HAL_UART_IRQHandler+0x2fc>
 
           /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
              in the UART CR3 register */
           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 80055c8:	687b      	ldr	r3, [r7, #4]
- 80055ca:	681b      	ldr	r3, [r3, #0]
- 80055cc:	3314      	adds	r3, #20
- 80055ce:	663b      	str	r3, [r7, #96]	@ 0x60
+ 80070e4:	687b      	ldr	r3, [r7, #4]
+ 80070e6:	681b      	ldr	r3, [r3, #0]
+ 80070e8:	3314      	adds	r3, #20
+ 80070ea:	663b      	str	r3, [r7, #96]	@ 0x60
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 80055d0:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
- 80055d2:	e853 3f00 	ldrex	r3, [r3]
- 80055d6:	65fb      	str	r3, [r7, #92]	@ 0x5c
+ 80070ec:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 80070ee:	e853 3f00 	ldrex	r3, [r3]
+ 80070f2:	65fb      	str	r3, [r7, #92]	@ 0x5c
    return(result);
- 80055d8:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
- 80055da:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
- 80055de:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
- 80055e2:	687b      	ldr	r3, [r7, #4]
- 80055e4:	681b      	ldr	r3, [r3, #0]
- 80055e6:	3314      	adds	r3, #20
- 80055e8:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
- 80055ec:	66fa      	str	r2, [r7, #108]	@ 0x6c
- 80055ee:	66bb      	str	r3, [r7, #104]	@ 0x68
+ 80070f4:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 80070f6:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
+ 80070fa:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
+ 80070fe:	687b      	ldr	r3, [r7, #4]
+ 8007100:	681b      	ldr	r3, [r3, #0]
+ 8007102:	3314      	adds	r3, #20
+ 8007104:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
+ 8007108:	66fa      	str	r2, [r7, #108]	@ 0x6c
+ 800710a:	66bb      	str	r3, [r7, #104]	@ 0x68
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 80055f0:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
- 80055f2:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
- 80055f4:	e841 2300 	strex	r3, r2, [r1]
- 80055f8:	667b      	str	r3, [r7, #100]	@ 0x64
+ 800710c:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
+ 800710e:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
+ 8007110:	e841 2300 	strex	r3, r2, [r1]
+ 8007114:	667b      	str	r3, [r7, #100]	@ 0x64
    return(result);
- 80055fa:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
- 80055fc:	2b00      	cmp	r3, #0
- 80055fe:	d1e3      	bne.n	80055c8 <HAL_UART_IRQHandler+0x338>
+ 8007116:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 8007118:	2b00      	cmp	r3, #0
+ 800711a:	d1e3      	bne.n	80070e4 <HAL_UART_IRQHandler+0x338>
 
           /* At end of Rx process, restore huart->RxState to Ready */
           huart->RxState = HAL_UART_STATE_READY;
- 8005600:	687b      	ldr	r3, [r7, #4]
- 8005602:	2220      	movs	r2, #32
- 8005604:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 800711c:	687b      	ldr	r3, [r7, #4]
+ 800711e:	2220      	movs	r2, #32
+ 8007120:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8005608:	687b      	ldr	r3, [r7, #4]
- 800560a:	2200      	movs	r2, #0
- 800560c:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8007124:	687b      	ldr	r3, [r7, #4]
+ 8007126:	2200      	movs	r2, #0
+ 8007128:	631a      	str	r2, [r3, #48]	@ 0x30
 
           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 800560e:	687b      	ldr	r3, [r7, #4]
- 8005610:	681b      	ldr	r3, [r3, #0]
- 8005612:	330c      	adds	r3, #12
- 8005614:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 800712a:	687b      	ldr	r3, [r7, #4]
+ 800712c:	681b      	ldr	r3, [r3, #0]
+ 800712e:	330c      	adds	r3, #12
+ 8007130:	64fb      	str	r3, [r7, #76]	@ 0x4c
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005616:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8005618:	e853 3f00 	ldrex	r3, [r3]
- 800561c:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8007132:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8007134:	e853 3f00 	ldrex	r3, [r3]
+ 8007138:	64bb      	str	r3, [r7, #72]	@ 0x48
    return(result);
- 800561e:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8005620:	f023 0310 	bic.w	r3, r3, #16
- 8005624:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
- 8005628:	687b      	ldr	r3, [r7, #4]
- 800562a:	681b      	ldr	r3, [r3, #0]
- 800562c:	330c      	adds	r3, #12
- 800562e:	f8d7 20ac 	ldr.w	r2, [r7, #172]	@ 0xac
- 8005632:	65ba      	str	r2, [r7, #88]	@ 0x58
- 8005634:	657b      	str	r3, [r7, #84]	@ 0x54
+ 800713a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 800713c:	f023 0310 	bic.w	r3, r3, #16
+ 8007140:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+ 8007144:	687b      	ldr	r3, [r7, #4]
+ 8007146:	681b      	ldr	r3, [r3, #0]
+ 8007148:	330c      	adds	r3, #12
+ 800714a:	f8d7 20ac 	ldr.w	r2, [r7, #172]	@ 0xac
+ 800714e:	65ba      	str	r2, [r7, #88]	@ 0x58
+ 8007150:	657b      	str	r3, [r7, #84]	@ 0x54
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005636:	6d79      	ldr	r1, [r7, #84]	@ 0x54
- 8005638:	6dba      	ldr	r2, [r7, #88]	@ 0x58
- 800563a:	e841 2300 	strex	r3, r2, [r1]
- 800563e:	653b      	str	r3, [r7, #80]	@ 0x50
+ 8007152:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 8007154:	6dba      	ldr	r2, [r7, #88]	@ 0x58
+ 8007156:	e841 2300 	strex	r3, r2, [r1]
+ 800715a:	653b      	str	r3, [r7, #80]	@ 0x50
    return(result);
- 8005640:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
- 8005642:	2b00      	cmp	r3, #0
- 8005644:	d1e3      	bne.n	800560e <HAL_UART_IRQHandler+0x37e>
+ 800715c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 800715e:	2b00      	cmp	r3, #0
+ 8007160:	d1e3      	bne.n	800712a <HAL_UART_IRQHandler+0x37e>
 
           /* Last bytes received, so no need as the abort is immediate */
           (void)HAL_DMA_Abort(huart->hdmarx);
- 8005646:	687b      	ldr	r3, [r7, #4]
- 8005648:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 800564a:	4618      	mov	r0, r3
- 800564c:	f7fd fdc9 	bl	80031e2 <HAL_DMA_Abort>
+ 8007162:	687b      	ldr	r3, [r7, #4]
+ 8007164:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8007166:	4618      	mov	r0, r3
+ 8007168:	f7fc ff1a 	bl	8003fa0 <HAL_DMA_Abort>
         }
 
         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
         In this case, Rx Event type is Idle Event */
         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
- 8005650:	687b      	ldr	r3, [r7, #4]
- 8005652:	2202      	movs	r2, #2
- 8005654:	635a      	str	r2, [r3, #52]	@ 0x34
+ 800716c:	687b      	ldr	r3, [r7, #4]
+ 800716e:	2202      	movs	r2, #2
+ 8007170:	635a      	str	r2, [r3, #52]	@ 0x34
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx Event callback*/
         huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 #else
         /*Call legacy weak Rx Event callback*/
         HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
- 8005656:	687b      	ldr	r3, [r7, #4]
- 8005658:	8d9a      	ldrh	r2, [r3, #44]	@ 0x2c
- 800565a:	687b      	ldr	r3, [r7, #4]
- 800565c:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
- 800565e:	b29b      	uxth	r3, r3
- 8005660:	1ad3      	subs	r3, r2, r3
- 8005662:	b29b      	uxth	r3, r3
- 8005664:	4619      	mov	r1, r3
- 8005666:	6878      	ldr	r0, [r7, #4]
- 8005668:	f000 f8bf 	bl	80057ea <HAL_UARTEx_RxEventCallback>
+ 8007172:	687b      	ldr	r3, [r7, #4]
+ 8007174:	8d9a      	ldrh	r2, [r3, #44]	@ 0x2c
+ 8007176:	687b      	ldr	r3, [r7, #4]
+ 8007178:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
+ 800717a:	b29b      	uxth	r3, r3
+ 800717c:	1ad3      	subs	r3, r2, r3
+ 800717e:	b29b      	uxth	r3, r3
+ 8007180:	4619      	mov	r1, r3
+ 8007182:	6878      	ldr	r0, [r7, #4]
+ 8007184:	f000 f8bf 	bl	8007306 <HAL_UARTEx_RxEventCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
       }
       return;
- 800566c:	e09c      	b.n	80057a8 <HAL_UART_IRQHandler+0x518>
- 800566e:	bf00      	nop
- 8005670:	08005977 	.word	0x08005977
+ 8007188:	e09c      	b.n	80072c4 <HAL_UART_IRQHandler+0x518>
+ 800718a:	bf00      	nop
+ 800718c:	08007493 	.word	0x08007493
     else
     {
       /* DMA mode not enabled */
       /* Check received length : If all expected data are received, do nothing.
          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
       uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
- 8005674:	687b      	ldr	r3, [r7, #4]
- 8005676:	8d9a      	ldrh	r2, [r3, #44]	@ 0x2c
- 8005678:	687b      	ldr	r3, [r7, #4]
- 800567a:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
- 800567c:	b29b      	uxth	r3, r3
- 800567e:	1ad3      	subs	r3, r2, r3
- 8005680:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
+ 8007190:	687b      	ldr	r3, [r7, #4]
+ 8007192:	8d9a      	ldrh	r2, [r3, #44]	@ 0x2c
+ 8007194:	687b      	ldr	r3, [r7, #4]
+ 8007196:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
+ 8007198:	b29b      	uxth	r3, r3
+ 800719a:	1ad3      	subs	r3, r2, r3
+ 800719c:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
       if ((huart->RxXferCount > 0U)
- 8005684:	687b      	ldr	r3, [r7, #4]
- 8005686:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
- 8005688:	b29b      	uxth	r3, r3
- 800568a:	2b00      	cmp	r3, #0
- 800568c:	f000 808e 	beq.w	80057ac <HAL_UART_IRQHandler+0x51c>
+ 80071a0:	687b      	ldr	r3, [r7, #4]
+ 80071a2:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
+ 80071a4:	b29b      	uxth	r3, r3
+ 80071a6:	2b00      	cmp	r3, #0
+ 80071a8:	f000 808e 	beq.w	80072c8 <HAL_UART_IRQHandler+0x51c>
           && (nb_rx_data > 0U))
- 8005690:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
- 8005694:	2b00      	cmp	r3, #0
- 8005696:	f000 8089 	beq.w	80057ac <HAL_UART_IRQHandler+0x51c>
+ 80071ac:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
+ 80071b0:	2b00      	cmp	r3, #0
+ 80071b2:	f000 8089 	beq.w	80072c8 <HAL_UART_IRQHandler+0x51c>
       {
         /* Disable the UART Parity Error Interrupt and RXNE interrupts */
         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 800569a:	687b      	ldr	r3, [r7, #4]
- 800569c:	681b      	ldr	r3, [r3, #0]
- 800569e:	330c      	adds	r3, #12
- 80056a0:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 80071b6:	687b      	ldr	r3, [r7, #4]
+ 80071b8:	681b      	ldr	r3, [r3, #0]
+ 80071ba:	330c      	adds	r3, #12
+ 80071bc:	63bb      	str	r3, [r7, #56]	@ 0x38
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 80056a2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80056a4:	e853 3f00 	ldrex	r3, [r3]
- 80056a8:	637b      	str	r3, [r7, #52]	@ 0x34
+ 80071be:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 80071c0:	e853 3f00 	ldrex	r3, [r3]
+ 80071c4:	637b      	str	r3, [r7, #52]	@ 0x34
    return(result);
- 80056aa:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80056ac:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
- 80056b0:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
- 80056b4:	687b      	ldr	r3, [r7, #4]
- 80056b6:	681b      	ldr	r3, [r3, #0]
- 80056b8:	330c      	adds	r3, #12
- 80056ba:	f8d7 20c8 	ldr.w	r2, [r7, #200]	@ 0xc8
- 80056be:	647a      	str	r2, [r7, #68]	@ 0x44
- 80056c0:	643b      	str	r3, [r7, #64]	@ 0x40
+ 80071c6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80071c8:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 80071cc:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+ 80071d0:	687b      	ldr	r3, [r7, #4]
+ 80071d2:	681b      	ldr	r3, [r3, #0]
+ 80071d4:	330c      	adds	r3, #12
+ 80071d6:	f8d7 20c8 	ldr.w	r2, [r7, #200]	@ 0xc8
+ 80071da:	647a      	str	r2, [r7, #68]	@ 0x44
+ 80071dc:	643b      	str	r3, [r7, #64]	@ 0x40
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 80056c2:	6c39      	ldr	r1, [r7, #64]	@ 0x40
- 80056c4:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
- 80056c6:	e841 2300 	strex	r3, r2, [r1]
- 80056ca:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 80071de:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 80071e0:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 80071e2:	e841 2300 	strex	r3, r2, [r1]
+ 80071e6:	63fb      	str	r3, [r7, #60]	@ 0x3c
    return(result);
- 80056cc:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80056ce:	2b00      	cmp	r3, #0
- 80056d0:	d1e3      	bne.n	800569a <HAL_UART_IRQHandler+0x40a>
+ 80071e8:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 80071ea:	2b00      	cmp	r3, #0
+ 80071ec:	d1e3      	bne.n	80071b6 <HAL_UART_IRQHandler+0x40a>
 
         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80056d2:	687b      	ldr	r3, [r7, #4]
- 80056d4:	681b      	ldr	r3, [r3, #0]
- 80056d6:	3314      	adds	r3, #20
- 80056d8:	627b      	str	r3, [r7, #36]	@ 0x24
+ 80071ee:	687b      	ldr	r3, [r7, #4]
+ 80071f0:	681b      	ldr	r3, [r3, #0]
+ 80071f2:	3314      	adds	r3, #20
+ 80071f4:	627b      	str	r3, [r7, #36]	@ 0x24
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 80056da:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80056dc:	e853 3f00 	ldrex	r3, [r3]
- 80056e0:	623b      	str	r3, [r7, #32]
+ 80071f6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80071f8:	e853 3f00 	ldrex	r3, [r3]
+ 80071fc:	623b      	str	r3, [r7, #32]
    return(result);
- 80056e2:	6a3b      	ldr	r3, [r7, #32]
- 80056e4:	f023 0301 	bic.w	r3, r3, #1
- 80056e8:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
- 80056ec:	687b      	ldr	r3, [r7, #4]
- 80056ee:	681b      	ldr	r3, [r3, #0]
- 80056f0:	3314      	adds	r3, #20
- 80056f2:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
- 80056f6:	633a      	str	r2, [r7, #48]	@ 0x30
- 80056f8:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80071fe:	6a3b      	ldr	r3, [r7, #32]
+ 8007200:	f023 0301 	bic.w	r3, r3, #1
+ 8007204:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
+ 8007208:	687b      	ldr	r3, [r7, #4]
+ 800720a:	681b      	ldr	r3, [r3, #0]
+ 800720c:	3314      	adds	r3, #20
+ 800720e:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
+ 8007212:	633a      	str	r2, [r7, #48]	@ 0x30
+ 8007214:	62fb      	str	r3, [r7, #44]	@ 0x2c
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 80056fa:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
- 80056fc:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
- 80056fe:	e841 2300 	strex	r3, r2, [r1]
- 8005702:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8007216:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 8007218:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 800721a:	e841 2300 	strex	r3, r2, [r1]
+ 800721e:	62bb      	str	r3, [r7, #40]	@ 0x28
    return(result);
- 8005704:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 8005706:	2b00      	cmp	r3, #0
- 8005708:	d1e3      	bne.n	80056d2 <HAL_UART_IRQHandler+0x442>
+ 8007220:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8007222:	2b00      	cmp	r3, #0
+ 8007224:	d1e3      	bne.n	80071ee <HAL_UART_IRQHandler+0x442>
 
         /* Rx process is completed, restore huart->RxState to Ready */
         huart->RxState = HAL_UART_STATE_READY;
- 800570a:	687b      	ldr	r3, [r7, #4]
- 800570c:	2220      	movs	r2, #32
- 800570e:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 8007226:	687b      	ldr	r3, [r7, #4]
+ 8007228:	2220      	movs	r2, #32
+ 800722a:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8005712:	687b      	ldr	r3, [r7, #4]
- 8005714:	2200      	movs	r2, #0
- 8005716:	631a      	str	r2, [r3, #48]	@ 0x30
+ 800722e:	687b      	ldr	r3, [r7, #4]
+ 8007230:	2200      	movs	r2, #0
+ 8007232:	631a      	str	r2, [r3, #48]	@ 0x30
 
         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 8005718:	687b      	ldr	r3, [r7, #4]
- 800571a:	681b      	ldr	r3, [r3, #0]
- 800571c:	330c      	adds	r3, #12
- 800571e:	613b      	str	r3, [r7, #16]
+ 8007234:	687b      	ldr	r3, [r7, #4]
+ 8007236:	681b      	ldr	r3, [r3, #0]
+ 8007238:	330c      	adds	r3, #12
+ 800723a:	613b      	str	r3, [r7, #16]
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005720:	693b      	ldr	r3, [r7, #16]
- 8005722:	e853 3f00 	ldrex	r3, [r3]
- 8005726:	60fb      	str	r3, [r7, #12]
+ 800723c:	693b      	ldr	r3, [r7, #16]
+ 800723e:	e853 3f00 	ldrex	r3, [r3]
+ 8007242:	60fb      	str	r3, [r7, #12]
    return(result);
- 8005728:	68fb      	ldr	r3, [r7, #12]
- 800572a:	f023 0310 	bic.w	r3, r3, #16
- 800572e:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
- 8005732:	687b      	ldr	r3, [r7, #4]
- 8005734:	681b      	ldr	r3, [r3, #0]
- 8005736:	330c      	adds	r3, #12
- 8005738:	f8d7 20c0 	ldr.w	r2, [r7, #192]	@ 0xc0
- 800573c:	61fa      	str	r2, [r7, #28]
- 800573e:	61bb      	str	r3, [r7, #24]
+ 8007244:	68fb      	ldr	r3, [r7, #12]
+ 8007246:	f023 0310 	bic.w	r3, r3, #16
+ 800724a:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
+ 800724e:	687b      	ldr	r3, [r7, #4]
+ 8007250:	681b      	ldr	r3, [r3, #0]
+ 8007252:	330c      	adds	r3, #12
+ 8007254:	f8d7 20c0 	ldr.w	r2, [r7, #192]	@ 0xc0
+ 8007258:	61fa      	str	r2, [r7, #28]
+ 800725a:	61bb      	str	r3, [r7, #24]
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005740:	69b9      	ldr	r1, [r7, #24]
- 8005742:	69fa      	ldr	r2, [r7, #28]
- 8005744:	e841 2300 	strex	r3, r2, [r1]
- 8005748:	617b      	str	r3, [r7, #20]
+ 800725c:	69b9      	ldr	r1, [r7, #24]
+ 800725e:	69fa      	ldr	r2, [r7, #28]
+ 8007260:	e841 2300 	strex	r3, r2, [r1]
+ 8007264:	617b      	str	r3, [r7, #20]
    return(result);
- 800574a:	697b      	ldr	r3, [r7, #20]
- 800574c:	2b00      	cmp	r3, #0
- 800574e:	d1e3      	bne.n	8005718 <HAL_UART_IRQHandler+0x488>
+ 8007266:	697b      	ldr	r3, [r7, #20]
+ 8007268:	2b00      	cmp	r3, #0
+ 800726a:	d1e3      	bne.n	8007234 <HAL_UART_IRQHandler+0x488>
 
         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
            In this case, Rx Event type is Idle Event */
         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
- 8005750:	687b      	ldr	r3, [r7, #4]
- 8005752:	2202      	movs	r2, #2
- 8005754:	635a      	str	r2, [r3, #52]	@ 0x34
+ 800726c:	687b      	ldr	r3, [r7, #4]
+ 800726e:	2202      	movs	r2, #2
+ 8007270:	635a      	str	r2, [r3, #52]	@ 0x34
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx complete callback*/
         huart->RxEventCallback(huart, nb_rx_data);
 #else
         /*Call legacy weak Rx Event callback*/
         HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
- 8005756:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
- 800575a:	4619      	mov	r1, r3
- 800575c:	6878      	ldr	r0, [r7, #4]
- 800575e:	f000 f844 	bl	80057ea <HAL_UARTEx_RxEventCallback>
+ 8007272:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
+ 8007276:	4619      	mov	r1, r3
+ 8007278:	6878      	ldr	r0, [r7, #4]
+ 800727a:	f000 f844 	bl	8007306 <HAL_UARTEx_RxEventCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
       }
       return;
- 8005762:	e023      	b.n	80057ac <HAL_UART_IRQHandler+0x51c>
+ 800727e:	e023      	b.n	80072c8 <HAL_UART_IRQHandler+0x51c>
     }
   }
 
   /* UART in mode Transmitter ------------------------------------------------*/
   if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- 8005764:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 8005768:	f003 0380 	and.w	r3, r3, #128	@ 0x80
- 800576c:	2b00      	cmp	r3, #0
- 800576e:	d009      	beq.n	8005784 <HAL_UART_IRQHandler+0x4f4>
- 8005770:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 8005774:	f003 0380 	and.w	r3, r3, #128	@ 0x80
- 8005778:	2b00      	cmp	r3, #0
- 800577a:	d003      	beq.n	8005784 <HAL_UART_IRQHandler+0x4f4>
+ 8007280:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 8007284:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 8007288:	2b00      	cmp	r3, #0
+ 800728a:	d009      	beq.n	80072a0 <HAL_UART_IRQHandler+0x4f4>
+ 800728c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 8007290:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 8007294:	2b00      	cmp	r3, #0
+ 8007296:	d003      	beq.n	80072a0 <HAL_UART_IRQHandler+0x4f4>
   {
     UART_Transmit_IT(huart);
- 800577c:	6878      	ldr	r0, [r7, #4]
- 800577e:	f000 f90e 	bl	800599e <UART_Transmit_IT>
+ 8007298:	6878      	ldr	r0, [r7, #4]
+ 800729a:	f000 f90e 	bl	80074ba <UART_Transmit_IT>
     return;
- 8005782:	e014      	b.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 800729e:	e014      	b.n	80072ca <HAL_UART_IRQHandler+0x51e>
   }
 
   /* UART in mode Transmitter end --------------------------------------------*/
   if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- 8005784:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
- 8005788:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 800578c:	2b00      	cmp	r3, #0
- 800578e:	d00e      	beq.n	80057ae <HAL_UART_IRQHandler+0x51e>
- 8005790:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
- 8005794:	f003 0340 	and.w	r3, r3, #64	@ 0x40
- 8005798:	2b00      	cmp	r3, #0
- 800579a:	d008      	beq.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 80072a0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 80072a4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 80072a8:	2b00      	cmp	r3, #0
+ 80072aa:	d00e      	beq.n	80072ca <HAL_UART_IRQHandler+0x51e>
+ 80072ac:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 80072b0:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 80072b4:	2b00      	cmp	r3, #0
+ 80072b6:	d008      	beq.n	80072ca <HAL_UART_IRQHandler+0x51e>
   {
     UART_EndTransmit_IT(huart);
- 800579c:	6878      	ldr	r0, [r7, #4]
- 800579e:	f000 f94d 	bl	8005a3c <UART_EndTransmit_IT>
+ 80072b8:	6878      	ldr	r0, [r7, #4]
+ 80072ba:	f000 f94d 	bl	8007558 <UART_EndTransmit_IT>
     return;
- 80057a2:	e004      	b.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 80072be:	e004      	b.n	80072ca <HAL_UART_IRQHandler+0x51e>
     return;
- 80057a4:	bf00      	nop
- 80057a6:	e002      	b.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 80072c0:	bf00      	nop
+ 80072c2:	e002      	b.n	80072ca <HAL_UART_IRQHandler+0x51e>
       return;
- 80057a8:	bf00      	nop
- 80057aa:	e000      	b.n	80057ae <HAL_UART_IRQHandler+0x51e>
+ 80072c4:	bf00      	nop
+ 80072c6:	e000      	b.n	80072ca <HAL_UART_IRQHandler+0x51e>
       return;
- 80057ac:	bf00      	nop
+ 80072c8:	bf00      	nop
   }
 }
- 80057ae:	37e8      	adds	r7, #232	@ 0xe8
- 80057b0:	46bd      	mov	sp, r7
- 80057b2:	bd80      	pop	{r7, pc}
+ 80072ca:	37e8      	adds	r7, #232	@ 0xe8
+ 80072cc:	46bd      	mov	sp, r7
+ 80072ce:	bd80      	pop	{r7, pc}
 
-080057b4 <HAL_UART_TxCpltCallback>:
+080072d0 <HAL_UART_TxCpltCallback>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
- 80057b4:	b480      	push	{r7}
- 80057b6:	b083      	sub	sp, #12
- 80057b8:	af00      	add	r7, sp, #0
- 80057ba:	6078      	str	r0, [r7, #4]
+ 80072d0:	b480      	push	{r7}
+ 80072d2:	b083      	sub	sp, #12
+ 80072d4:	af00      	add	r7, sp, #0
+ 80072d6:	6078      	str	r0, [r7, #4]
   /* Prevent unused argument(s) compilation warning */
   UNUSED(huart);
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_TxCpltCallback could be implemented in the user file
    */
 }
- 80057bc:	bf00      	nop
- 80057be:	370c      	adds	r7, #12
- 80057c0:	46bd      	mov	sp, r7
- 80057c2:	bc80      	pop	{r7}
- 80057c4:	4770      	bx	lr
+ 80072d8:	bf00      	nop
+ 80072da:	370c      	adds	r7, #12
+ 80072dc:	46bd      	mov	sp, r7
+ 80072de:	bc80      	pop	{r7}
+ 80072e0:	4770      	bx	lr
 
-080057c6 <HAL_UART_RxCpltCallback>:
+080072e2 <HAL_UART_RxCpltCallback>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
 {
- 80057c6:	b480      	push	{r7}
- 80057c8:	b083      	sub	sp, #12
- 80057ca:	af00      	add	r7, sp, #0
- 80057cc:	6078      	str	r0, [r7, #4]
+ 80072e2:	b480      	push	{r7}
+ 80072e4:	b083      	sub	sp, #12
+ 80072e6:	af00      	add	r7, sp, #0
+ 80072e8:	6078      	str	r0, [r7, #4]
   /* Prevent unused argument(s) compilation warning */
   UNUSED(huart);
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_RxCpltCallback could be implemented in the user file
    */
 }
- 80057ce:	bf00      	nop
- 80057d0:	370c      	adds	r7, #12
- 80057d2:	46bd      	mov	sp, r7
- 80057d4:	bc80      	pop	{r7}
- 80057d6:	4770      	bx	lr
+ 80072ea:	bf00      	nop
+ 80072ec:	370c      	adds	r7, #12
+ 80072ee:	46bd      	mov	sp, r7
+ 80072f0:	bc80      	pop	{r7}
+ 80072f2:	4770      	bx	lr
 
-080057d8 <HAL_UART_ErrorCallback>:
+080072f4 <HAL_UART_ErrorCallback>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
 {
- 80057d8:	b480      	push	{r7}
- 80057da:	b083      	sub	sp, #12
- 80057dc:	af00      	add	r7, sp, #0
- 80057de:	6078      	str	r0, [r7, #4]
+ 80072f4:	b480      	push	{r7}
+ 80072f6:	b083      	sub	sp, #12
+ 80072f8:	af00      	add	r7, sp, #0
+ 80072fa:	6078      	str	r0, [r7, #4]
   /* Prevent unused argument(s) compilation warning */
   UNUSED(huart);
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_ErrorCallback could be implemented in the user file
    */
 }
- 80057e0:	bf00      	nop
- 80057e2:	370c      	adds	r7, #12
- 80057e4:	46bd      	mov	sp, r7
- 80057e6:	bc80      	pop	{r7}
- 80057e8:	4770      	bx	lr
+ 80072fc:	bf00      	nop
+ 80072fe:	370c      	adds	r7, #12
+ 8007300:	46bd      	mov	sp, r7
+ 8007302:	bc80      	pop	{r7}
+ 8007304:	4770      	bx	lr
 
-080057ea <HAL_UARTEx_RxEventCallback>:
+08007306 <HAL_UARTEx_RxEventCallback>:
   * @param  Size  Number of data available in application reception buffer (indicates a position in
   *               reception buffer until which, data are available)
   * @retval None
   */
 __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
 {
- 80057ea:	b480      	push	{r7}
- 80057ec:	b083      	sub	sp, #12
- 80057ee:	af00      	add	r7, sp, #0
- 80057f0:	6078      	str	r0, [r7, #4]
- 80057f2:	460b      	mov	r3, r1
- 80057f4:	807b      	strh	r3, [r7, #2]
+ 8007306:	b480      	push	{r7}
+ 8007308:	b083      	sub	sp, #12
+ 800730a:	af00      	add	r7, sp, #0
+ 800730c:	6078      	str	r0, [r7, #4]
+ 800730e:	460b      	mov	r3, r1
+ 8007310:	807b      	strh	r3, [r7, #2]
   UNUSED(Size);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UARTEx_RxEventCallback can be implemented in the user file.
    */
 }
- 80057f6:	bf00      	nop
- 80057f8:	370c      	adds	r7, #12
- 80057fa:	46bd      	mov	sp, r7
- 80057fc:	bc80      	pop	{r7}
- 80057fe:	4770      	bx	lr
+ 8007312:	bf00      	nop
+ 8007314:	370c      	adds	r7, #12
+ 8007316:	46bd      	mov	sp, r7
+ 8007318:	bc80      	pop	{r7}
+ 800731a:	4770      	bx	lr
 
-08005800 <UART_WaitOnFlagUntilTimeout>:
+0800731c <UART_WaitOnFlagUntilTimeout>:
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                                      uint32_t Tickstart, uint32_t Timeout)
 {
- 8005800:	b580      	push	{r7, lr}
- 8005802:	b086      	sub	sp, #24
- 8005804:	af00      	add	r7, sp, #0
- 8005806:	60f8      	str	r0, [r7, #12]
- 8005808:	60b9      	str	r1, [r7, #8]
- 800580a:	603b      	str	r3, [r7, #0]
- 800580c:	4613      	mov	r3, r2
- 800580e:	71fb      	strb	r3, [r7, #7]
+ 800731c:	b580      	push	{r7, lr}
+ 800731e:	b086      	sub	sp, #24
+ 8007320:	af00      	add	r7, sp, #0
+ 8007322:	60f8      	str	r0, [r7, #12]
+ 8007324:	60b9      	str	r1, [r7, #8]
+ 8007326:	603b      	str	r3, [r7, #0]
+ 8007328:	4613      	mov	r3, r2
+ 800732a:	71fb      	strb	r3, [r7, #7]
   /* Wait until flag is set */
   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8005810:	e03b      	b.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
+ 800732c:	e03b      	b.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
   {
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 8005812:	6a3b      	ldr	r3, [r7, #32]
- 8005814:	f1b3 3fff 	cmp.w	r3, #4294967295
- 8005818:	d037      	beq.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
+ 800732e:	6a3b      	ldr	r3, [r7, #32]
+ 8007330:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8007334:	d037      	beq.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 800581a:	f7fd f995 	bl	8002b48 <HAL_GetTick>
- 800581e:	4602      	mov	r2, r0
- 8005820:	683b      	ldr	r3, [r7, #0]
- 8005822:	1ad3      	subs	r3, r2, r3
- 8005824:	6a3a      	ldr	r2, [r7, #32]
- 8005826:	429a      	cmp	r2, r3
- 8005828:	d302      	bcc.n	8005830 <UART_WaitOnFlagUntilTimeout+0x30>
- 800582a:	6a3b      	ldr	r3, [r7, #32]
- 800582c:	2b00      	cmp	r3, #0
- 800582e:	d101      	bne.n	8005834 <UART_WaitOnFlagUntilTimeout+0x34>
+ 8007336:	f7fb ffcd 	bl	80032d4 <HAL_GetTick>
+ 800733a:	4602      	mov	r2, r0
+ 800733c:	683b      	ldr	r3, [r7, #0]
+ 800733e:	1ad3      	subs	r3, r2, r3
+ 8007340:	6a3a      	ldr	r2, [r7, #32]
+ 8007342:	429a      	cmp	r2, r3
+ 8007344:	d302      	bcc.n	800734c <UART_WaitOnFlagUntilTimeout+0x30>
+ 8007346:	6a3b      	ldr	r3, [r7, #32]
+ 8007348:	2b00      	cmp	r3, #0
+ 800734a:	d101      	bne.n	8007350 <UART_WaitOnFlagUntilTimeout+0x34>
       {
 
         return HAL_TIMEOUT;
- 8005830:	2303      	movs	r3, #3
- 8005832:	e03a      	b.n	80058aa <UART_WaitOnFlagUntilTimeout+0xaa>
+ 800734c:	2303      	movs	r3, #3
+ 800734e:	e03a      	b.n	80073c6 <UART_WaitOnFlagUntilTimeout+0xaa>
       }
 
       if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
- 8005834:	68fb      	ldr	r3, [r7, #12]
- 8005836:	681b      	ldr	r3, [r3, #0]
- 8005838:	68db      	ldr	r3, [r3, #12]
- 800583a:	f003 0304 	and.w	r3, r3, #4
- 800583e:	2b00      	cmp	r3, #0
- 8005840:	d023      	beq.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
- 8005842:	68bb      	ldr	r3, [r7, #8]
- 8005844:	2b80      	cmp	r3, #128	@ 0x80
- 8005846:	d020      	beq.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
- 8005848:	68bb      	ldr	r3, [r7, #8]
- 800584a:	2b40      	cmp	r3, #64	@ 0x40
- 800584c:	d01d      	beq.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
+ 8007350:	68fb      	ldr	r3, [r7, #12]
+ 8007352:	681b      	ldr	r3, [r3, #0]
+ 8007354:	68db      	ldr	r3, [r3, #12]
+ 8007356:	f003 0304 	and.w	r3, r3, #4
+ 800735a:	2b00      	cmp	r3, #0
+ 800735c:	d023      	beq.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
+ 800735e:	68bb      	ldr	r3, [r7, #8]
+ 8007360:	2b80      	cmp	r3, #128	@ 0x80
+ 8007362:	d020      	beq.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
+ 8007364:	68bb      	ldr	r3, [r7, #8]
+ 8007366:	2b40      	cmp	r3, #64	@ 0x40
+ 8007368:	d01d      	beq.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
       {
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
- 800584e:	68fb      	ldr	r3, [r7, #12]
- 8005850:	681b      	ldr	r3, [r3, #0]
- 8005852:	681b      	ldr	r3, [r3, #0]
- 8005854:	f003 0308 	and.w	r3, r3, #8
- 8005858:	2b08      	cmp	r3, #8
- 800585a:	d116      	bne.n	800588a <UART_WaitOnFlagUntilTimeout+0x8a>
+ 800736a:	68fb      	ldr	r3, [r7, #12]
+ 800736c:	681b      	ldr	r3, [r3, #0]
+ 800736e:	681b      	ldr	r3, [r3, #0]
+ 8007370:	f003 0308 	and.w	r3, r3, #8
+ 8007374:	2b08      	cmp	r3, #8
+ 8007376:	d116      	bne.n	80073a6 <UART_WaitOnFlagUntilTimeout+0x8a>
         {
           /* Clear Overrun Error flag*/
           __HAL_UART_CLEAR_OREFLAG(huart);
- 800585c:	2300      	movs	r3, #0
- 800585e:	617b      	str	r3, [r7, #20]
- 8005860:	68fb      	ldr	r3, [r7, #12]
- 8005862:	681b      	ldr	r3, [r3, #0]
- 8005864:	681b      	ldr	r3, [r3, #0]
- 8005866:	617b      	str	r3, [r7, #20]
- 8005868:	68fb      	ldr	r3, [r7, #12]
- 800586a:	681b      	ldr	r3, [r3, #0]
- 800586c:	685b      	ldr	r3, [r3, #4]
- 800586e:	617b      	str	r3, [r7, #20]
- 8005870:	697b      	ldr	r3, [r7, #20]
+ 8007378:	2300      	movs	r3, #0
+ 800737a:	617b      	str	r3, [r7, #20]
+ 800737c:	68fb      	ldr	r3, [r7, #12]
+ 800737e:	681b      	ldr	r3, [r3, #0]
+ 8007380:	681b      	ldr	r3, [r3, #0]
+ 8007382:	617b      	str	r3, [r7, #20]
+ 8007384:	68fb      	ldr	r3, [r7, #12]
+ 8007386:	681b      	ldr	r3, [r3, #0]
+ 8007388:	685b      	ldr	r3, [r3, #4]
+ 800738a:	617b      	str	r3, [r7, #20]
+ 800738c:	697b      	ldr	r3, [r7, #20]
 
           /* Blocking error : transfer is aborted
           Set the UART state ready to be able to start again the process,
           Disable Rx Interrupts if ongoing */
           UART_EndRxTransfer(huart);
- 8005872:	68f8      	ldr	r0, [r7, #12]
- 8005874:	f000 f81d 	bl	80058b2 <UART_EndRxTransfer>
+ 800738e:	68f8      	ldr	r0, [r7, #12]
+ 8007390:	f000 f81d 	bl	80073ce <UART_EndRxTransfer>
 
           huart->ErrorCode = HAL_UART_ERROR_ORE;
- 8005878:	68fb      	ldr	r3, [r7, #12]
- 800587a:	2208      	movs	r2, #8
- 800587c:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8007394:	68fb      	ldr	r3, [r7, #12]
+ 8007396:	2208      	movs	r2, #8
+ 8007398:	645a      	str	r2, [r3, #68]	@ 0x44
 
           /* Process Unlocked */
           __HAL_UNLOCK(huart);
- 800587e:	68fb      	ldr	r3, [r7, #12]
- 8005880:	2200      	movs	r2, #0
- 8005882:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+ 800739a:	68fb      	ldr	r3, [r7, #12]
+ 800739c:	2200      	movs	r2, #0
+ 800739e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 
           return HAL_ERROR;
- 8005886:	2301      	movs	r3, #1
- 8005888:	e00f      	b.n	80058aa <UART_WaitOnFlagUntilTimeout+0xaa>
+ 80073a2:	2301      	movs	r3, #1
+ 80073a4:	e00f      	b.n	80073c6 <UART_WaitOnFlagUntilTimeout+0xaa>
   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 800588a:	68fb      	ldr	r3, [r7, #12]
- 800588c:	681b      	ldr	r3, [r3, #0]
- 800588e:	681a      	ldr	r2, [r3, #0]
- 8005890:	68bb      	ldr	r3, [r7, #8]
- 8005892:	4013      	ands	r3, r2
- 8005894:	68ba      	ldr	r2, [r7, #8]
- 8005896:	429a      	cmp	r2, r3
- 8005898:	bf0c      	ite	eq
- 800589a:	2301      	moveq	r3, #1
- 800589c:	2300      	movne	r3, #0
- 800589e:	b2db      	uxtb	r3, r3
- 80058a0:	461a      	mov	r2, r3
- 80058a2:	79fb      	ldrb	r3, [r7, #7]
- 80058a4:	429a      	cmp	r2, r3
- 80058a6:	d0b4      	beq.n	8005812 <UART_WaitOnFlagUntilTimeout+0x12>
+ 80073a6:	68fb      	ldr	r3, [r7, #12]
+ 80073a8:	681b      	ldr	r3, [r3, #0]
+ 80073aa:	681a      	ldr	r2, [r3, #0]
+ 80073ac:	68bb      	ldr	r3, [r7, #8]
+ 80073ae:	4013      	ands	r3, r2
+ 80073b0:	68ba      	ldr	r2, [r7, #8]
+ 80073b2:	429a      	cmp	r2, r3
+ 80073b4:	bf0c      	ite	eq
+ 80073b6:	2301      	moveq	r3, #1
+ 80073b8:	2300      	movne	r3, #0
+ 80073ba:	b2db      	uxtb	r3, r3
+ 80073bc:	461a      	mov	r2, r3
+ 80073be:	79fb      	ldrb	r3, [r7, #7]
+ 80073c0:	429a      	cmp	r2, r3
+ 80073c2:	d0b4      	beq.n	800732e <UART_WaitOnFlagUntilTimeout+0x12>
         }
       }
     }
   }
   return HAL_OK;
- 80058a8:	2300      	movs	r3, #0
+ 80073c4:	2300      	movs	r3, #0
 }
- 80058aa:	4618      	mov	r0, r3
- 80058ac:	3718      	adds	r7, #24
- 80058ae:	46bd      	mov	sp, r7
- 80058b0:	bd80      	pop	{r7, pc}
+ 80073c6:	4618      	mov	r0, r3
+ 80073c8:	3718      	adds	r7, #24
+ 80073ca:	46bd      	mov	sp, r7
+ 80073cc:	bd80      	pop	{r7, pc}
 
-080058b2 <UART_EndRxTransfer>:
+080073ce <UART_EndRxTransfer>:
   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
   * @param  huart UART handle.
   * @retval None
   */
 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
 {
- 80058b2:	b480      	push	{r7}
- 80058b4:	b095      	sub	sp, #84	@ 0x54
- 80058b6:	af00      	add	r7, sp, #0
- 80058b8:	6078      	str	r0, [r7, #4]
+ 80073ce:	b480      	push	{r7}
+ 80073d0:	b095      	sub	sp, #84	@ 0x54
+ 80073d2:	af00      	add	r7, sp, #0
+ 80073d4:	6078      	str	r0, [r7, #4]
   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80058ba:	687b      	ldr	r3, [r7, #4]
- 80058bc:	681b      	ldr	r3, [r3, #0]
- 80058be:	330c      	adds	r3, #12
- 80058c0:	637b      	str	r3, [r7, #52]	@ 0x34
+ 80073d6:	687b      	ldr	r3, [r7, #4]
+ 80073d8:	681b      	ldr	r3, [r3, #0]
+ 80073da:	330c      	adds	r3, #12
+ 80073dc:	637b      	str	r3, [r7, #52]	@ 0x34
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 80058c2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80058c4:	e853 3f00 	ldrex	r3, [r3]
- 80058c8:	633b      	str	r3, [r7, #48]	@ 0x30
+ 80073de:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80073e0:	e853 3f00 	ldrex	r3, [r3]
+ 80073e4:	633b      	str	r3, [r7, #48]	@ 0x30
    return(result);
- 80058ca:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 80058cc:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
- 80058d0:	64fb      	str	r3, [r7, #76]	@ 0x4c
- 80058d2:	687b      	ldr	r3, [r7, #4]
- 80058d4:	681b      	ldr	r3, [r3, #0]
- 80058d6:	330c      	adds	r3, #12
- 80058d8:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
- 80058da:	643a      	str	r2, [r7, #64]	@ 0x40
- 80058dc:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 80073e6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 80073e8:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 80073ec:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 80073ee:	687b      	ldr	r3, [r7, #4]
+ 80073f0:	681b      	ldr	r3, [r3, #0]
+ 80073f2:	330c      	adds	r3, #12
+ 80073f4:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
+ 80073f6:	643a      	str	r2, [r7, #64]	@ 0x40
+ 80073f8:	63fb      	str	r3, [r7, #60]	@ 0x3c
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 80058de:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
- 80058e0:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 80058e2:	e841 2300 	strex	r3, r2, [r1]
- 80058e6:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 80073fa:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
+ 80073fc:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 80073fe:	e841 2300 	strex	r3, r2, [r1]
+ 8007402:	63bb      	str	r3, [r7, #56]	@ 0x38
    return(result);
- 80058e8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80058ea:	2b00      	cmp	r3, #0
- 80058ec:	d1e5      	bne.n	80058ba <UART_EndRxTransfer+0x8>
+ 8007404:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8007406:	2b00      	cmp	r3, #0
+ 8007408:	d1e5      	bne.n	80073d6 <UART_EndRxTransfer+0x8>
   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80058ee:	687b      	ldr	r3, [r7, #4]
- 80058f0:	681b      	ldr	r3, [r3, #0]
- 80058f2:	3314      	adds	r3, #20
- 80058f4:	623b      	str	r3, [r7, #32]
+ 800740a:	687b      	ldr	r3, [r7, #4]
+ 800740c:	681b      	ldr	r3, [r3, #0]
+ 800740e:	3314      	adds	r3, #20
+ 8007410:	623b      	str	r3, [r7, #32]
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 80058f6:	6a3b      	ldr	r3, [r7, #32]
- 80058f8:	e853 3f00 	ldrex	r3, [r3]
- 80058fc:	61fb      	str	r3, [r7, #28]
+ 8007412:	6a3b      	ldr	r3, [r7, #32]
+ 8007414:	e853 3f00 	ldrex	r3, [r3]
+ 8007418:	61fb      	str	r3, [r7, #28]
    return(result);
- 80058fe:	69fb      	ldr	r3, [r7, #28]
- 8005900:	f023 0301 	bic.w	r3, r3, #1
- 8005904:	64bb      	str	r3, [r7, #72]	@ 0x48
- 8005906:	687b      	ldr	r3, [r7, #4]
- 8005908:	681b      	ldr	r3, [r3, #0]
- 800590a:	3314      	adds	r3, #20
- 800590c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
- 800590e:	62fa      	str	r2, [r7, #44]	@ 0x2c
- 8005910:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 800741a:	69fb      	ldr	r3, [r7, #28]
+ 800741c:	f023 0301 	bic.w	r3, r3, #1
+ 8007420:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8007422:	687b      	ldr	r3, [r7, #4]
+ 8007424:	681b      	ldr	r3, [r3, #0]
+ 8007426:	3314      	adds	r3, #20
+ 8007428:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 800742a:	62fa      	str	r2, [r7, #44]	@ 0x2c
+ 800742c:	62bb      	str	r3, [r7, #40]	@ 0x28
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005912:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
- 8005914:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
- 8005916:	e841 2300 	strex	r3, r2, [r1]
- 800591a:	627b      	str	r3, [r7, #36]	@ 0x24
+ 800742e:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 8007430:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 8007432:	e841 2300 	strex	r3, r2, [r1]
+ 8007436:	627b      	str	r3, [r7, #36]	@ 0x24
    return(result);
- 800591c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 800591e:	2b00      	cmp	r3, #0
- 8005920:	d1e5      	bne.n	80058ee <UART_EndRxTransfer+0x3c>
+ 8007438:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 800743a:	2b00      	cmp	r3, #0
+ 800743c:	d1e5      	bne.n	800740a <UART_EndRxTransfer+0x3c>
 
   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 8005922:	687b      	ldr	r3, [r7, #4]
- 8005924:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 8005926:	2b01      	cmp	r3, #1
- 8005928:	d119      	bne.n	800595e <UART_EndRxTransfer+0xac>
+ 800743e:	687b      	ldr	r3, [r7, #4]
+ 8007440:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8007442:	2b01      	cmp	r3, #1
+ 8007444:	d119      	bne.n	800747a <UART_EndRxTransfer+0xac>
   {
     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 800592a:	687b      	ldr	r3, [r7, #4]
- 800592c:	681b      	ldr	r3, [r3, #0]
- 800592e:	330c      	adds	r3, #12
- 8005930:	60fb      	str	r3, [r7, #12]
+ 8007446:	687b      	ldr	r3, [r7, #4]
+ 8007448:	681b      	ldr	r3, [r3, #0]
+ 800744a:	330c      	adds	r3, #12
+ 800744c:	60fb      	str	r3, [r7, #12]
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005932:	68fb      	ldr	r3, [r7, #12]
- 8005934:	e853 3f00 	ldrex	r3, [r3]
- 8005938:	60bb      	str	r3, [r7, #8]
+ 800744e:	68fb      	ldr	r3, [r7, #12]
+ 8007450:	e853 3f00 	ldrex	r3, [r3]
+ 8007454:	60bb      	str	r3, [r7, #8]
    return(result);
- 800593a:	68bb      	ldr	r3, [r7, #8]
- 800593c:	f023 0310 	bic.w	r3, r3, #16
- 8005940:	647b      	str	r3, [r7, #68]	@ 0x44
- 8005942:	687b      	ldr	r3, [r7, #4]
- 8005944:	681b      	ldr	r3, [r3, #0]
- 8005946:	330c      	adds	r3, #12
- 8005948:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
- 800594a:	61ba      	str	r2, [r7, #24]
- 800594c:	617b      	str	r3, [r7, #20]
+ 8007456:	68bb      	ldr	r3, [r7, #8]
+ 8007458:	f023 0310 	bic.w	r3, r3, #16
+ 800745c:	647b      	str	r3, [r7, #68]	@ 0x44
+ 800745e:	687b      	ldr	r3, [r7, #4]
+ 8007460:	681b      	ldr	r3, [r3, #0]
+ 8007462:	330c      	adds	r3, #12
+ 8007464:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 8007466:	61ba      	str	r2, [r7, #24]
+ 8007468:	617b      	str	r3, [r7, #20]
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 800594e:	6979      	ldr	r1, [r7, #20]
- 8005950:	69ba      	ldr	r2, [r7, #24]
- 8005952:	e841 2300 	strex	r3, r2, [r1]
- 8005956:	613b      	str	r3, [r7, #16]
+ 800746a:	6979      	ldr	r1, [r7, #20]
+ 800746c:	69ba      	ldr	r2, [r7, #24]
+ 800746e:	e841 2300 	strex	r3, r2, [r1]
+ 8007472:	613b      	str	r3, [r7, #16]
    return(result);
- 8005958:	693b      	ldr	r3, [r7, #16]
- 800595a:	2b00      	cmp	r3, #0
- 800595c:	d1e5      	bne.n	800592a <UART_EndRxTransfer+0x78>
+ 8007474:	693b      	ldr	r3, [r7, #16]
+ 8007476:	2b00      	cmp	r3, #0
+ 8007478:	d1e5      	bne.n	8007446 <UART_EndRxTransfer+0x78>
   }
 
   /* At end of Rx process, restore huart->RxState to Ready */
   huart->RxState = HAL_UART_STATE_READY;
- 800595e:	687b      	ldr	r3, [r7, #4]
- 8005960:	2220      	movs	r2, #32
- 8005962:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 800747a:	687b      	ldr	r3, [r7, #4]
+ 800747c:	2220      	movs	r2, #32
+ 800747e:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8005966:	687b      	ldr	r3, [r7, #4]
- 8005968:	2200      	movs	r2, #0
- 800596a:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8007482:	687b      	ldr	r3, [r7, #4]
+ 8007484:	2200      	movs	r2, #0
+ 8007486:	631a      	str	r2, [r3, #48]	@ 0x30
 }
- 800596c:	bf00      	nop
- 800596e:	3754      	adds	r7, #84	@ 0x54
- 8005970:	46bd      	mov	sp, r7
- 8005972:	bc80      	pop	{r7}
- 8005974:	4770      	bx	lr
+ 8007488:	bf00      	nop
+ 800748a:	3754      	adds	r7, #84	@ 0x54
+ 800748c:	46bd      	mov	sp, r7
+ 800748e:	bc80      	pop	{r7}
+ 8007490:	4770      	bx	lr
 
-08005976 <UART_DMAAbortOnError>:
+08007492 <UART_DMAAbortOnError>:
   * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 {
- 8005976:	b580      	push	{r7, lr}
- 8005978:	b084      	sub	sp, #16
- 800597a:	af00      	add	r7, sp, #0
- 800597c:	6078      	str	r0, [r7, #4]
+ 8007492:	b580      	push	{r7, lr}
+ 8007494:	b084      	sub	sp, #16
+ 8007496:	af00      	add	r7, sp, #0
+ 8007498:	6078      	str	r0, [r7, #4]
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- 800597e:	687b      	ldr	r3, [r7, #4]
- 8005980:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8005982:	60fb      	str	r3, [r7, #12]
+ 800749a:	687b      	ldr	r3, [r7, #4]
+ 800749c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800749e:	60fb      	str	r3, [r7, #12]
   huart->RxXferCount = 0x00U;
- 8005984:	68fb      	ldr	r3, [r7, #12]
- 8005986:	2200      	movs	r2, #0
- 8005988:	85da      	strh	r2, [r3, #46]	@ 0x2e
+ 80074a0:	68fb      	ldr	r3, [r7, #12]
+ 80074a2:	2200      	movs	r2, #0
+ 80074a4:	85da      	strh	r2, [r3, #46]	@ 0x2e
   huart->TxXferCount = 0x00U;
- 800598a:	68fb      	ldr	r3, [r7, #12]
- 800598c:	2200      	movs	r2, #0
- 800598e:	84da      	strh	r2, [r3, #38]	@ 0x26
+ 80074a6:	68fb      	ldr	r3, [r7, #12]
+ 80074a8:	2200      	movs	r2, #0
+ 80074aa:	84da      	strh	r2, [r3, #38]	@ 0x26
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered error callback*/
   huart->ErrorCallback(huart);
 #else
   /*Call legacy weak error callback*/
   HAL_UART_ErrorCallback(huart);
- 8005990:	68f8      	ldr	r0, [r7, #12]
- 8005992:	f7ff ff21 	bl	80057d8 <HAL_UART_ErrorCallback>
+ 80074ac:	68f8      	ldr	r0, [r7, #12]
+ 80074ae:	f7ff ff21 	bl	80072f4 <HAL_UART_ErrorCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
- 8005996:	bf00      	nop
- 8005998:	3710      	adds	r7, #16
- 800599a:	46bd      	mov	sp, r7
- 800599c:	bd80      	pop	{r7, pc}
+ 80074b2:	bf00      	nop
+ 80074b4:	3710      	adds	r7, #16
+ 80074b6:	46bd      	mov	sp, r7
+ 80074b8:	bd80      	pop	{r7, pc}
 
-0800599e <UART_Transmit_IT>:
+080074ba <UART_Transmit_IT>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
 {
- 800599e:	b480      	push	{r7}
- 80059a0:	b085      	sub	sp, #20
- 80059a2:	af00      	add	r7, sp, #0
- 80059a4:	6078      	str	r0, [r7, #4]
+ 80074ba:	b480      	push	{r7}
+ 80074bc:	b085      	sub	sp, #20
+ 80074be:	af00      	add	r7, sp, #0
+ 80074c0:	6078      	str	r0, [r7, #4]
   const uint16_t *tmp;
 
   /* Check that a Tx process is ongoing */
   if (huart->gState == HAL_UART_STATE_BUSY_TX)
- 80059a6:	687b      	ldr	r3, [r7, #4]
- 80059a8:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
- 80059ac:	b2db      	uxtb	r3, r3
- 80059ae:	2b21      	cmp	r3, #33	@ 0x21
- 80059b0:	d13e      	bne.n	8005a30 <UART_Transmit_IT+0x92>
+ 80074c2:	687b      	ldr	r3, [r7, #4]
+ 80074c4:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 80074c8:	b2db      	uxtb	r3, r3
+ 80074ca:	2b21      	cmp	r3, #33	@ 0x21
+ 80074cc:	d13e      	bne.n	800754c <UART_Transmit_IT+0x92>
   {
     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 80059b2:	687b      	ldr	r3, [r7, #4]
- 80059b4:	689b      	ldr	r3, [r3, #8]
- 80059b6:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
- 80059ba:	d114      	bne.n	80059e6 <UART_Transmit_IT+0x48>
- 80059bc:	687b      	ldr	r3, [r7, #4]
- 80059be:	691b      	ldr	r3, [r3, #16]
- 80059c0:	2b00      	cmp	r3, #0
- 80059c2:	d110      	bne.n	80059e6 <UART_Transmit_IT+0x48>
+ 80074ce:	687b      	ldr	r3, [r7, #4]
+ 80074d0:	689b      	ldr	r3, [r3, #8]
+ 80074d2:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 80074d6:	d114      	bne.n	8007502 <UART_Transmit_IT+0x48>
+ 80074d8:	687b      	ldr	r3, [r7, #4]
+ 80074da:	691b      	ldr	r3, [r3, #16]
+ 80074dc:	2b00      	cmp	r3, #0
+ 80074de:	d110      	bne.n	8007502 <UART_Transmit_IT+0x48>
     {
       tmp = (const uint16_t *) huart->pTxBuffPtr;
- 80059c4:	687b      	ldr	r3, [r7, #4]
- 80059c6:	6a1b      	ldr	r3, [r3, #32]
- 80059c8:	60fb      	str	r3, [r7, #12]
+ 80074e0:	687b      	ldr	r3, [r7, #4]
+ 80074e2:	6a1b      	ldr	r3, [r3, #32]
+ 80074e4:	60fb      	str	r3, [r7, #12]
       huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- 80059ca:	68fb      	ldr	r3, [r7, #12]
- 80059cc:	881b      	ldrh	r3, [r3, #0]
- 80059ce:	461a      	mov	r2, r3
- 80059d0:	687b      	ldr	r3, [r7, #4]
- 80059d2:	681b      	ldr	r3, [r3, #0]
- 80059d4:	f3c2 0208 	ubfx	r2, r2, #0, #9
- 80059d8:	605a      	str	r2, [r3, #4]
+ 80074e6:	68fb      	ldr	r3, [r7, #12]
+ 80074e8:	881b      	ldrh	r3, [r3, #0]
+ 80074ea:	461a      	mov	r2, r3
+ 80074ec:	687b      	ldr	r3, [r7, #4]
+ 80074ee:	681b      	ldr	r3, [r3, #0]
+ 80074f0:	f3c2 0208 	ubfx	r2, r2, #0, #9
+ 80074f4:	605a      	str	r2, [r3, #4]
       huart->pTxBuffPtr += 2U;
- 80059da:	687b      	ldr	r3, [r7, #4]
- 80059dc:	6a1b      	ldr	r3, [r3, #32]
- 80059de:	1c9a      	adds	r2, r3, #2
- 80059e0:	687b      	ldr	r3, [r7, #4]
- 80059e2:	621a      	str	r2, [r3, #32]
- 80059e4:	e008      	b.n	80059f8 <UART_Transmit_IT+0x5a>
+ 80074f6:	687b      	ldr	r3, [r7, #4]
+ 80074f8:	6a1b      	ldr	r3, [r3, #32]
+ 80074fa:	1c9a      	adds	r2, r3, #2
+ 80074fc:	687b      	ldr	r3, [r7, #4]
+ 80074fe:	621a      	str	r2, [r3, #32]
+ 8007500:	e008      	b.n	8007514 <UART_Transmit_IT+0x5a>
     }
     else
     {
       huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
- 80059e6:	687b      	ldr	r3, [r7, #4]
- 80059e8:	6a1b      	ldr	r3, [r3, #32]
- 80059ea:	1c59      	adds	r1, r3, #1
- 80059ec:	687a      	ldr	r2, [r7, #4]
- 80059ee:	6211      	str	r1, [r2, #32]
- 80059f0:	781a      	ldrb	r2, [r3, #0]
- 80059f2:	687b      	ldr	r3, [r7, #4]
- 80059f4:	681b      	ldr	r3, [r3, #0]
- 80059f6:	605a      	str	r2, [r3, #4]
+ 8007502:	687b      	ldr	r3, [r7, #4]
+ 8007504:	6a1b      	ldr	r3, [r3, #32]
+ 8007506:	1c59      	adds	r1, r3, #1
+ 8007508:	687a      	ldr	r2, [r7, #4]
+ 800750a:	6211      	str	r1, [r2, #32]
+ 800750c:	781a      	ldrb	r2, [r3, #0]
+ 800750e:	687b      	ldr	r3, [r7, #4]
+ 8007510:	681b      	ldr	r3, [r3, #0]
+ 8007512:	605a      	str	r2, [r3, #4]
     }
 
     if (--huart->TxXferCount == 0U)
- 80059f8:	687b      	ldr	r3, [r7, #4]
- 80059fa:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
- 80059fc:	b29b      	uxth	r3, r3
- 80059fe:	3b01      	subs	r3, #1
- 8005a00:	b29b      	uxth	r3, r3
- 8005a02:	687a      	ldr	r2, [r7, #4]
- 8005a04:	4619      	mov	r1, r3
- 8005a06:	84d1      	strh	r1, [r2, #38]	@ 0x26
- 8005a08:	2b00      	cmp	r3, #0
- 8005a0a:	d10f      	bne.n	8005a2c <UART_Transmit_IT+0x8e>
+ 8007514:	687b      	ldr	r3, [r7, #4]
+ 8007516:	8cdb      	ldrh	r3, [r3, #38]	@ 0x26
+ 8007518:	b29b      	uxth	r3, r3
+ 800751a:	3b01      	subs	r3, #1
+ 800751c:	b29b      	uxth	r3, r3
+ 800751e:	687a      	ldr	r2, [r7, #4]
+ 8007520:	4619      	mov	r1, r3
+ 8007522:	84d1      	strh	r1, [r2, #38]	@ 0x26
+ 8007524:	2b00      	cmp	r3, #0
+ 8007526:	d10f      	bne.n	8007548 <UART_Transmit_IT+0x8e>
     {
       /* Disable the UART Transmit Data Register Empty Interrupt */
       __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- 8005a0c:	687b      	ldr	r3, [r7, #4]
- 8005a0e:	681b      	ldr	r3, [r3, #0]
- 8005a10:	68da      	ldr	r2, [r3, #12]
- 8005a12:	687b      	ldr	r3, [r7, #4]
- 8005a14:	681b      	ldr	r3, [r3, #0]
- 8005a16:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
- 8005a1a:	60da      	str	r2, [r3, #12]
+ 8007528:	687b      	ldr	r3, [r7, #4]
+ 800752a:	681b      	ldr	r3, [r3, #0]
+ 800752c:	68da      	ldr	r2, [r3, #12]
+ 800752e:	687b      	ldr	r3, [r7, #4]
+ 8007530:	681b      	ldr	r3, [r3, #0]
+ 8007532:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
+ 8007536:	60da      	str	r2, [r3, #12]
 
       /* Enable the UART Transmit Complete Interrupt */
       __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
- 8005a1c:	687b      	ldr	r3, [r7, #4]
- 8005a1e:	681b      	ldr	r3, [r3, #0]
- 8005a20:	68da      	ldr	r2, [r3, #12]
- 8005a22:	687b      	ldr	r3, [r7, #4]
- 8005a24:	681b      	ldr	r3, [r3, #0]
- 8005a26:	f042 0240 	orr.w	r2, r2, #64	@ 0x40
- 8005a2a:	60da      	str	r2, [r3, #12]
+ 8007538:	687b      	ldr	r3, [r7, #4]
+ 800753a:	681b      	ldr	r3, [r3, #0]
+ 800753c:	68da      	ldr	r2, [r3, #12]
+ 800753e:	687b      	ldr	r3, [r7, #4]
+ 8007540:	681b      	ldr	r3, [r3, #0]
+ 8007542:	f042 0240 	orr.w	r2, r2, #64	@ 0x40
+ 8007546:	60da      	str	r2, [r3, #12]
     }
     return HAL_OK;
- 8005a2c:	2300      	movs	r3, #0
- 8005a2e:	e000      	b.n	8005a32 <UART_Transmit_IT+0x94>
+ 8007548:	2300      	movs	r3, #0
+ 800754a:	e000      	b.n	800754e <UART_Transmit_IT+0x94>
   }
   else
   {
     return HAL_BUSY;
- 8005a30:	2302      	movs	r3, #2
+ 800754c:	2302      	movs	r3, #2
   }
 }
- 8005a32:	4618      	mov	r0, r3
- 8005a34:	3714      	adds	r7, #20
- 8005a36:	46bd      	mov	sp, r7
- 8005a38:	bc80      	pop	{r7}
- 8005a3a:	4770      	bx	lr
+ 800754e:	4618      	mov	r0, r3
+ 8007550:	3714      	adds	r7, #20
+ 8007552:	46bd      	mov	sp, r7
+ 8007554:	bc80      	pop	{r7}
+ 8007556:	4770      	bx	lr
 
-08005a3c <UART_EndTransmit_IT>:
+08007558 <UART_EndTransmit_IT>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
 {
- 8005a3c:	b580      	push	{r7, lr}
- 8005a3e:	b082      	sub	sp, #8
- 8005a40:	af00      	add	r7, sp, #0
- 8005a42:	6078      	str	r0, [r7, #4]
+ 8007558:	b580      	push	{r7, lr}
+ 800755a:	b082      	sub	sp, #8
+ 800755c:	af00      	add	r7, sp, #0
+ 800755e:	6078      	str	r0, [r7, #4]
   /* Disable the UART Transmit Complete Interrupt */
   __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
- 8005a44:	687b      	ldr	r3, [r7, #4]
- 8005a46:	681b      	ldr	r3, [r3, #0]
- 8005a48:	68da      	ldr	r2, [r3, #12]
- 8005a4a:	687b      	ldr	r3, [r7, #4]
- 8005a4c:	681b      	ldr	r3, [r3, #0]
- 8005a4e:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
- 8005a52:	60da      	str	r2, [r3, #12]
+ 8007560:	687b      	ldr	r3, [r7, #4]
+ 8007562:	681b      	ldr	r3, [r3, #0]
+ 8007564:	68da      	ldr	r2, [r3, #12]
+ 8007566:	687b      	ldr	r3, [r7, #4]
+ 8007568:	681b      	ldr	r3, [r3, #0]
+ 800756a:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
+ 800756e:	60da      	str	r2, [r3, #12]
 
   /* Tx process is ended, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
- 8005a54:	687b      	ldr	r3, [r7, #4]
- 8005a56:	2220      	movs	r2, #32
- 8005a58:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8007570:	687b      	ldr	r3, [r7, #4]
+ 8007572:	2220      	movs	r2, #32
+ 8007574:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered Tx complete callback*/
   huart->TxCpltCallback(huart);
 #else
   /*Call legacy weak Tx complete callback*/
   HAL_UART_TxCpltCallback(huart);
- 8005a5c:	6878      	ldr	r0, [r7, #4]
- 8005a5e:	f7ff fea9 	bl	80057b4 <HAL_UART_TxCpltCallback>
+ 8007578:	6878      	ldr	r0, [r7, #4]
+ 800757a:	f7ff fea9 	bl	80072d0 <HAL_UART_TxCpltCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 
   return HAL_OK;
- 8005a62:	2300      	movs	r3, #0
+ 800757e:	2300      	movs	r3, #0
 }
- 8005a64:	4618      	mov	r0, r3
- 8005a66:	3708      	adds	r7, #8
- 8005a68:	46bd      	mov	sp, r7
- 8005a6a:	bd80      	pop	{r7, pc}
+ 8007580:	4618      	mov	r0, r3
+ 8007582:	3708      	adds	r7, #8
+ 8007584:	46bd      	mov	sp, r7
+ 8007586:	bd80      	pop	{r7, pc}
 
-08005a6c <UART_Receive_IT>:
+08007588 <UART_Receive_IT>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
 {
- 8005a6c:	b580      	push	{r7, lr}
- 8005a6e:	b08c      	sub	sp, #48	@ 0x30
- 8005a70:	af00      	add	r7, sp, #0
- 8005a72:	6078      	str	r0, [r7, #4]
+ 8007588:	b580      	push	{r7, lr}
+ 800758a:	b08c      	sub	sp, #48	@ 0x30
+ 800758c:	af00      	add	r7, sp, #0
+ 800758e:	6078      	str	r0, [r7, #4]
   uint8_t  *pdata8bits;
   uint16_t *pdata16bits;
 
   /* Check that a Rx process is ongoing */
   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 8005a74:	687b      	ldr	r3, [r7, #4]
- 8005a76:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
- 8005a7a:	b2db      	uxtb	r3, r3
- 8005a7c:	2b22      	cmp	r3, #34	@ 0x22
- 8005a7e:	f040 80ae 	bne.w	8005bde <UART_Receive_IT+0x172>
+ 8007590:	687b      	ldr	r3, [r7, #4]
+ 8007592:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
+ 8007596:	b2db      	uxtb	r3, r3
+ 8007598:	2b22      	cmp	r3, #34	@ 0x22
+ 800759a:	f040 80ae 	bne.w	80076fa <UART_Receive_IT+0x172>
   {
     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8005a82:	687b      	ldr	r3, [r7, #4]
- 8005a84:	689b      	ldr	r3, [r3, #8]
- 8005a86:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
- 8005a8a:	d117      	bne.n	8005abc <UART_Receive_IT+0x50>
- 8005a8c:	687b      	ldr	r3, [r7, #4]
- 8005a8e:	691b      	ldr	r3, [r3, #16]
- 8005a90:	2b00      	cmp	r3, #0
- 8005a92:	d113      	bne.n	8005abc <UART_Receive_IT+0x50>
+ 800759e:	687b      	ldr	r3, [r7, #4]
+ 80075a0:	689b      	ldr	r3, [r3, #8]
+ 80075a2:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 80075a6:	d117      	bne.n	80075d8 <UART_Receive_IT+0x50>
+ 80075a8:	687b      	ldr	r3, [r7, #4]
+ 80075aa:	691b      	ldr	r3, [r3, #16]
+ 80075ac:	2b00      	cmp	r3, #0
+ 80075ae:	d113      	bne.n	80075d8 <UART_Receive_IT+0x50>
     {
       pdata8bits  = NULL;
- 8005a94:	2300      	movs	r3, #0
- 8005a96:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80075b0:	2300      	movs	r3, #0
+ 80075b2:	62fb      	str	r3, [r7, #44]	@ 0x2c
       pdata16bits = (uint16_t *) huart->pRxBuffPtr;
- 8005a98:	687b      	ldr	r3, [r7, #4]
- 8005a9a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8005a9c:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 80075b4:	687b      	ldr	r3, [r7, #4]
+ 80075b6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80075b8:	62bb      	str	r3, [r7, #40]	@ 0x28
       *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- 8005a9e:	687b      	ldr	r3, [r7, #4]
- 8005aa0:	681b      	ldr	r3, [r3, #0]
- 8005aa2:	685b      	ldr	r3, [r3, #4]
- 8005aa4:	b29b      	uxth	r3, r3
- 8005aa6:	f3c3 0308 	ubfx	r3, r3, #0, #9
- 8005aaa:	b29a      	uxth	r2, r3
- 8005aac:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 8005aae:	801a      	strh	r2, [r3, #0]
+ 80075ba:	687b      	ldr	r3, [r7, #4]
+ 80075bc:	681b      	ldr	r3, [r3, #0]
+ 80075be:	685b      	ldr	r3, [r3, #4]
+ 80075c0:	b29b      	uxth	r3, r3
+ 80075c2:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 80075c6:	b29a      	uxth	r2, r3
+ 80075c8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80075ca:	801a      	strh	r2, [r3, #0]
       huart->pRxBuffPtr += 2U;
- 8005ab0:	687b      	ldr	r3, [r7, #4]
- 8005ab2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8005ab4:	1c9a      	adds	r2, r3, #2
- 8005ab6:	687b      	ldr	r3, [r7, #4]
- 8005ab8:	629a      	str	r2, [r3, #40]	@ 0x28
- 8005aba:	e026      	b.n	8005b0a <UART_Receive_IT+0x9e>
+ 80075cc:	687b      	ldr	r3, [r7, #4]
+ 80075ce:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80075d0:	1c9a      	adds	r2, r3, #2
+ 80075d2:	687b      	ldr	r3, [r7, #4]
+ 80075d4:	629a      	str	r2, [r3, #40]	@ 0x28
+ 80075d6:	e026      	b.n	8007626 <UART_Receive_IT+0x9e>
     }
     else
     {
       pdata8bits = (uint8_t *) huart->pRxBuffPtr;
- 8005abc:	687b      	ldr	r3, [r7, #4]
- 8005abe:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8005ac0:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80075d8:	687b      	ldr	r3, [r7, #4]
+ 80075da:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80075dc:	62fb      	str	r3, [r7, #44]	@ 0x2c
       pdata16bits  = NULL;
- 8005ac2:	2300      	movs	r3, #0
- 8005ac4:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 80075de:	2300      	movs	r3, #0
+ 80075e0:	62bb      	str	r3, [r7, #40]	@ 0x28
 
       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
- 8005ac6:	687b      	ldr	r3, [r7, #4]
- 8005ac8:	689b      	ldr	r3, [r3, #8]
- 8005aca:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
- 8005ace:	d007      	beq.n	8005ae0 <UART_Receive_IT+0x74>
- 8005ad0:	687b      	ldr	r3, [r7, #4]
- 8005ad2:	689b      	ldr	r3, [r3, #8]
- 8005ad4:	2b00      	cmp	r3, #0
- 8005ad6:	d10a      	bne.n	8005aee <UART_Receive_IT+0x82>
- 8005ad8:	687b      	ldr	r3, [r7, #4]
- 8005ada:	691b      	ldr	r3, [r3, #16]
- 8005adc:	2b00      	cmp	r3, #0
- 8005ade:	d106      	bne.n	8005aee <UART_Receive_IT+0x82>
+ 80075e2:	687b      	ldr	r3, [r7, #4]
+ 80075e4:	689b      	ldr	r3, [r3, #8]
+ 80075e6:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 80075ea:	d007      	beq.n	80075fc <UART_Receive_IT+0x74>
+ 80075ec:	687b      	ldr	r3, [r7, #4]
+ 80075ee:	689b      	ldr	r3, [r3, #8]
+ 80075f0:	2b00      	cmp	r3, #0
+ 80075f2:	d10a      	bne.n	800760a <UART_Receive_IT+0x82>
+ 80075f4:	687b      	ldr	r3, [r7, #4]
+ 80075f6:	691b      	ldr	r3, [r3, #16]
+ 80075f8:	2b00      	cmp	r3, #0
+ 80075fa:	d106      	bne.n	800760a <UART_Receive_IT+0x82>
       {
         *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
- 8005ae0:	687b      	ldr	r3, [r7, #4]
- 8005ae2:	681b      	ldr	r3, [r3, #0]
- 8005ae4:	685b      	ldr	r3, [r3, #4]
- 8005ae6:	b2da      	uxtb	r2, r3
- 8005ae8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 8005aea:	701a      	strb	r2, [r3, #0]
- 8005aec:	e008      	b.n	8005b00 <UART_Receive_IT+0x94>
+ 80075fc:	687b      	ldr	r3, [r7, #4]
+ 80075fe:	681b      	ldr	r3, [r3, #0]
+ 8007600:	685b      	ldr	r3, [r3, #4]
+ 8007602:	b2da      	uxtb	r2, r3
+ 8007604:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8007606:	701a      	strb	r2, [r3, #0]
+ 8007608:	e008      	b.n	800761c <UART_Receive_IT+0x94>
       }
       else
       {
         *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
- 8005aee:	687b      	ldr	r3, [r7, #4]
- 8005af0:	681b      	ldr	r3, [r3, #0]
- 8005af2:	685b      	ldr	r3, [r3, #4]
- 8005af4:	b2db      	uxtb	r3, r3
- 8005af6:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
- 8005afa:	b2da      	uxtb	r2, r3
- 8005afc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 8005afe:	701a      	strb	r2, [r3, #0]
+ 800760a:	687b      	ldr	r3, [r7, #4]
+ 800760c:	681b      	ldr	r3, [r3, #0]
+ 800760e:	685b      	ldr	r3, [r3, #4]
+ 8007610:	b2db      	uxtb	r3, r3
+ 8007612:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8007616:	b2da      	uxtb	r2, r3
+ 8007618:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 800761a:	701a      	strb	r2, [r3, #0]
       }
       huart->pRxBuffPtr += 1U;
- 8005b00:	687b      	ldr	r3, [r7, #4]
- 8005b02:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8005b04:	1c5a      	adds	r2, r3, #1
- 8005b06:	687b      	ldr	r3, [r7, #4]
- 8005b08:	629a      	str	r2, [r3, #40]	@ 0x28
+ 800761c:	687b      	ldr	r3, [r7, #4]
+ 800761e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8007620:	1c5a      	adds	r2, r3, #1
+ 8007622:	687b      	ldr	r3, [r7, #4]
+ 8007624:	629a      	str	r2, [r3, #40]	@ 0x28
     }
 
     if (--huart->RxXferCount == 0U)
- 8005b0a:	687b      	ldr	r3, [r7, #4]
- 8005b0c:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
- 8005b0e:	b29b      	uxth	r3, r3
- 8005b10:	3b01      	subs	r3, #1
- 8005b12:	b29b      	uxth	r3, r3
- 8005b14:	687a      	ldr	r2, [r7, #4]
- 8005b16:	4619      	mov	r1, r3
- 8005b18:	85d1      	strh	r1, [r2, #46]	@ 0x2e
- 8005b1a:	2b00      	cmp	r3, #0
- 8005b1c:	d15d      	bne.n	8005bda <UART_Receive_IT+0x16e>
+ 8007626:	687b      	ldr	r3, [r7, #4]
+ 8007628:	8ddb      	ldrh	r3, [r3, #46]	@ 0x2e
+ 800762a:	b29b      	uxth	r3, r3
+ 800762c:	3b01      	subs	r3, #1
+ 800762e:	b29b      	uxth	r3, r3
+ 8007630:	687a      	ldr	r2, [r7, #4]
+ 8007632:	4619      	mov	r1, r3
+ 8007634:	85d1      	strh	r1, [r2, #46]	@ 0x2e
+ 8007636:	2b00      	cmp	r3, #0
+ 8007638:	d15d      	bne.n	80076f6 <UART_Receive_IT+0x16e>
     {
       /* Disable the UART Data Register not empty Interrupt */
       __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- 8005b1e:	687b      	ldr	r3, [r7, #4]
- 8005b20:	681b      	ldr	r3, [r3, #0]
- 8005b22:	68da      	ldr	r2, [r3, #12]
- 8005b24:	687b      	ldr	r3, [r7, #4]
- 8005b26:	681b      	ldr	r3, [r3, #0]
- 8005b28:	f022 0220 	bic.w	r2, r2, #32
- 8005b2c:	60da      	str	r2, [r3, #12]
+ 800763a:	687b      	ldr	r3, [r7, #4]
+ 800763c:	681b      	ldr	r3, [r3, #0]
+ 800763e:	68da      	ldr	r2, [r3, #12]
+ 8007640:	687b      	ldr	r3, [r7, #4]
+ 8007642:	681b      	ldr	r3, [r3, #0]
+ 8007644:	f022 0220 	bic.w	r2, r2, #32
+ 8007648:	60da      	str	r2, [r3, #12]
 
       /* Disable the UART Parity Error Interrupt */
       __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- 8005b2e:	687b      	ldr	r3, [r7, #4]
- 8005b30:	681b      	ldr	r3, [r3, #0]
- 8005b32:	68da      	ldr	r2, [r3, #12]
- 8005b34:	687b      	ldr	r3, [r7, #4]
- 8005b36:	681b      	ldr	r3, [r3, #0]
- 8005b38:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
- 8005b3c:	60da      	str	r2, [r3, #12]
+ 800764a:	687b      	ldr	r3, [r7, #4]
+ 800764c:	681b      	ldr	r3, [r3, #0]
+ 800764e:	68da      	ldr	r2, [r3, #12]
+ 8007650:	687b      	ldr	r3, [r7, #4]
+ 8007652:	681b      	ldr	r3, [r3, #0]
+ 8007654:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 8007658:	60da      	str	r2, [r3, #12]
 
       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
       __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
- 8005b3e:	687b      	ldr	r3, [r7, #4]
- 8005b40:	681b      	ldr	r3, [r3, #0]
- 8005b42:	695a      	ldr	r2, [r3, #20]
- 8005b44:	687b      	ldr	r3, [r7, #4]
- 8005b46:	681b      	ldr	r3, [r3, #0]
- 8005b48:	f022 0201 	bic.w	r2, r2, #1
- 8005b4c:	615a      	str	r2, [r3, #20]
+ 800765a:	687b      	ldr	r3, [r7, #4]
+ 800765c:	681b      	ldr	r3, [r3, #0]
+ 800765e:	695a      	ldr	r2, [r3, #20]
+ 8007660:	687b      	ldr	r3, [r7, #4]
+ 8007662:	681b      	ldr	r3, [r3, #0]
+ 8007664:	f022 0201 	bic.w	r2, r2, #1
+ 8007668:	615a      	str	r2, [r3, #20]
 
       /* Rx process is completed, restore huart->RxState to Ready */
       huart->RxState = HAL_UART_STATE_READY;
- 8005b4e:	687b      	ldr	r3, [r7, #4]
- 8005b50:	2220      	movs	r2, #32
- 8005b52:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 800766a:	687b      	ldr	r3, [r7, #4]
+ 800766c:	2220      	movs	r2, #32
+ 800766e:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 
       /* Initialize type of RxEvent to Transfer Complete */
       huart->RxEventType = HAL_UART_RXEVENT_TC;
- 8005b56:	687b      	ldr	r3, [r7, #4]
- 8005b58:	2200      	movs	r2, #0
- 8005b5a:	635a      	str	r2, [r3, #52]	@ 0x34
+ 8007672:	687b      	ldr	r3, [r7, #4]
+ 8007674:	2200      	movs	r2, #0
+ 8007676:	635a      	str	r2, [r3, #52]	@ 0x34
 
       /* Check current reception Mode :
          If Reception till IDLE event has been selected : */
       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 8005b5c:	687b      	ldr	r3, [r7, #4]
- 8005b5e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 8005b60:	2b01      	cmp	r3, #1
- 8005b62:	d135      	bne.n	8005bd0 <UART_Receive_IT+0x164>
+ 8007678:	687b      	ldr	r3, [r7, #4]
+ 800767a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 800767c:	2b01      	cmp	r3, #1
+ 800767e:	d135      	bne.n	80076ec <UART_Receive_IT+0x164>
       {
         /* Set reception type to Standard */
         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8005b64:	687b      	ldr	r3, [r7, #4]
- 8005b66:	2200      	movs	r2, #0
- 8005b68:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8007680:	687b      	ldr	r3, [r7, #4]
+ 8007682:	2200      	movs	r2, #0
+ 8007684:	631a      	str	r2, [r3, #48]	@ 0x30
 
         /* Disable IDLE interrupt */
         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 8005b6a:	687b      	ldr	r3, [r7, #4]
- 8005b6c:	681b      	ldr	r3, [r3, #0]
- 8005b6e:	330c      	adds	r3, #12
- 8005b70:	617b      	str	r3, [r7, #20]
+ 8007686:	687b      	ldr	r3, [r7, #4]
+ 8007688:	681b      	ldr	r3, [r3, #0]
+ 800768a:	330c      	adds	r3, #12
+ 800768c:	617b      	str	r3, [r7, #20]
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- 8005b72:	697b      	ldr	r3, [r7, #20]
- 8005b74:	e853 3f00 	ldrex	r3, [r3]
- 8005b78:	613b      	str	r3, [r7, #16]
+ 800768e:	697b      	ldr	r3, [r7, #20]
+ 8007690:	e853 3f00 	ldrex	r3, [r3]
+ 8007694:	613b      	str	r3, [r7, #16]
    return(result);
- 8005b7a:	693b      	ldr	r3, [r7, #16]
- 8005b7c:	f023 0310 	bic.w	r3, r3, #16
- 8005b80:	627b      	str	r3, [r7, #36]	@ 0x24
- 8005b82:	687b      	ldr	r3, [r7, #4]
- 8005b84:	681b      	ldr	r3, [r3, #0]
- 8005b86:	330c      	adds	r3, #12
- 8005b88:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 8005b8a:	623a      	str	r2, [r7, #32]
- 8005b8c:	61fb      	str	r3, [r7, #28]
+ 8007696:	693b      	ldr	r3, [r7, #16]
+ 8007698:	f023 0310 	bic.w	r3, r3, #16
+ 800769c:	627b      	str	r3, [r7, #36]	@ 0x24
+ 800769e:	687b      	ldr	r3, [r7, #4]
+ 80076a0:	681b      	ldr	r3, [r3, #0]
+ 80076a2:	330c      	adds	r3, #12
+ 80076a4:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80076a6:	623a      	str	r2, [r7, #32]
+ 80076a8:	61fb      	str	r3, [r7, #28]
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- 8005b8e:	69f9      	ldr	r1, [r7, #28]
- 8005b90:	6a3a      	ldr	r2, [r7, #32]
- 8005b92:	e841 2300 	strex	r3, r2, [r1]
- 8005b96:	61bb      	str	r3, [r7, #24]
+ 80076aa:	69f9      	ldr	r1, [r7, #28]
+ 80076ac:	6a3a      	ldr	r2, [r7, #32]
+ 80076ae:	e841 2300 	strex	r3, r2, [r1]
+ 80076b2:	61bb      	str	r3, [r7, #24]
    return(result);
- 8005b98:	69bb      	ldr	r3, [r7, #24]
- 8005b9a:	2b00      	cmp	r3, #0
- 8005b9c:	d1e5      	bne.n	8005b6a <UART_Receive_IT+0xfe>
+ 80076b4:	69bb      	ldr	r3, [r7, #24]
+ 80076b6:	2b00      	cmp	r3, #0
+ 80076b8:	d1e5      	bne.n	8007686 <UART_Receive_IT+0xfe>
 
         /* Check if IDLE flag is set */
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
- 8005b9e:	687b      	ldr	r3, [r7, #4]
- 8005ba0:	681b      	ldr	r3, [r3, #0]
- 8005ba2:	681b      	ldr	r3, [r3, #0]
- 8005ba4:	f003 0310 	and.w	r3, r3, #16
- 8005ba8:	2b10      	cmp	r3, #16
- 8005baa:	d10a      	bne.n	8005bc2 <UART_Receive_IT+0x156>
+ 80076ba:	687b      	ldr	r3, [r7, #4]
+ 80076bc:	681b      	ldr	r3, [r3, #0]
+ 80076be:	681b      	ldr	r3, [r3, #0]
+ 80076c0:	f003 0310 	and.w	r3, r3, #16
+ 80076c4:	2b10      	cmp	r3, #16
+ 80076c6:	d10a      	bne.n	80076de <UART_Receive_IT+0x156>
         {
           /* Clear IDLE flag in ISR */
           __HAL_UART_CLEAR_IDLEFLAG(huart);
- 8005bac:	2300      	movs	r3, #0
- 8005bae:	60fb      	str	r3, [r7, #12]
- 8005bb0:	687b      	ldr	r3, [r7, #4]
- 8005bb2:	681b      	ldr	r3, [r3, #0]
- 8005bb4:	681b      	ldr	r3, [r3, #0]
- 8005bb6:	60fb      	str	r3, [r7, #12]
- 8005bb8:	687b      	ldr	r3, [r7, #4]
- 8005bba:	681b      	ldr	r3, [r3, #0]
- 8005bbc:	685b      	ldr	r3, [r3, #4]
- 8005bbe:	60fb      	str	r3, [r7, #12]
- 8005bc0:	68fb      	ldr	r3, [r7, #12]
+ 80076c8:	2300      	movs	r3, #0
+ 80076ca:	60fb      	str	r3, [r7, #12]
+ 80076cc:	687b      	ldr	r3, [r7, #4]
+ 80076ce:	681b      	ldr	r3, [r3, #0]
+ 80076d0:	681b      	ldr	r3, [r3, #0]
+ 80076d2:	60fb      	str	r3, [r7, #12]
+ 80076d4:	687b      	ldr	r3, [r7, #4]
+ 80076d6:	681b      	ldr	r3, [r3, #0]
+ 80076d8:	685b      	ldr	r3, [r3, #4]
+ 80076da:	60fb      	str	r3, [r7, #12]
+ 80076dc:	68fb      	ldr	r3, [r7, #12]
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx Event callback*/
         huart->RxEventCallback(huart, huart->RxXferSize);
 #else
         /*Call legacy weak Rx Event callback*/
         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
- 8005bc2:	687b      	ldr	r3, [r7, #4]
- 8005bc4:	8d9b      	ldrh	r3, [r3, #44]	@ 0x2c
- 8005bc6:	4619      	mov	r1, r3
- 8005bc8:	6878      	ldr	r0, [r7, #4]
- 8005bca:	f7ff fe0e 	bl	80057ea <HAL_UARTEx_RxEventCallback>
- 8005bce:	e002      	b.n	8005bd6 <UART_Receive_IT+0x16a>
+ 80076de:	687b      	ldr	r3, [r7, #4]
+ 80076e0:	8d9b      	ldrh	r3, [r3, #44]	@ 0x2c
+ 80076e2:	4619      	mov	r1, r3
+ 80076e4:	6878      	ldr	r0, [r7, #4]
+ 80076e6:	f7ff fe0e 	bl	8007306 <HAL_UARTEx_RxEventCallback>
+ 80076ea:	e002      	b.n	80076f2 <UART_Receive_IT+0x16a>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx complete callback*/
         huart->RxCpltCallback(huart);
 #else
         /*Call legacy weak Rx complete callback*/
         HAL_UART_RxCpltCallback(huart);
- 8005bd0:	6878      	ldr	r0, [r7, #4]
- 8005bd2:	f7ff fdf8 	bl	80057c6 <HAL_UART_RxCpltCallback>
+ 80076ec:	6878      	ldr	r0, [r7, #4]
+ 80076ee:	f7ff fdf8 	bl	80072e2 <HAL_UART_RxCpltCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
       }
 
       return HAL_OK;
- 8005bd6:	2300      	movs	r3, #0
- 8005bd8:	e002      	b.n	8005be0 <UART_Receive_IT+0x174>
+ 80076f2:	2300      	movs	r3, #0
+ 80076f4:	e002      	b.n	80076fc <UART_Receive_IT+0x174>
     }
     return HAL_OK;
- 8005bda:	2300      	movs	r3, #0
- 8005bdc:	e000      	b.n	8005be0 <UART_Receive_IT+0x174>
+ 80076f6:	2300      	movs	r3, #0
+ 80076f8:	e000      	b.n	80076fc <UART_Receive_IT+0x174>
   }
   else
   {
     return HAL_BUSY;
- 8005bde:	2302      	movs	r3, #2
+ 80076fa:	2302      	movs	r3, #2
   }
 }
- 8005be0:	4618      	mov	r0, r3
- 8005be2:	3730      	adds	r7, #48	@ 0x30
- 8005be4:	46bd      	mov	sp, r7
- 8005be6:	bd80      	pop	{r7, pc}
+ 80076fc:	4618      	mov	r0, r3
+ 80076fe:	3730      	adds	r7, #48	@ 0x30
+ 8007700:	46bd      	mov	sp, r7
+ 8007702:	bd80      	pop	{r7, pc}
 
-08005be8 <UART_SetConfig>:
+08007704 <UART_SetConfig>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 static void UART_SetConfig(UART_HandleTypeDef *huart)
 {
- 8005be8:	b580      	push	{r7, lr}
- 8005bea:	b084      	sub	sp, #16
- 8005bec:	af00      	add	r7, sp, #0
- 8005bee:	6078      	str	r0, [r7, #4]
+ 8007704:	b580      	push	{r7, lr}
+ 8007706:	b084      	sub	sp, #16
+ 8007708:	af00      	add	r7, sp, #0
+ 800770a:	6078      	str	r0, [r7, #4]
   assert_param(IS_UART_MODE(huart->Init.Mode));
 
   /*-------------------------- USART CR2 Configuration -----------------------*/
   /* Configure the UART Stop Bits: Set STOP[13:12] bits
      according to huart->Init.StopBits value */
   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8005bf0:	687b      	ldr	r3, [r7, #4]
- 8005bf2:	681b      	ldr	r3, [r3, #0]
- 8005bf4:	691b      	ldr	r3, [r3, #16]
- 8005bf6:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
- 8005bfa:	687b      	ldr	r3, [r7, #4]
- 8005bfc:	68da      	ldr	r2, [r3, #12]
- 8005bfe:	687b      	ldr	r3, [r7, #4]
- 8005c00:	681b      	ldr	r3, [r3, #0]
- 8005c02:	430a      	orrs	r2, r1
- 8005c04:	611a      	str	r2, [r3, #16]
+ 800770c:	687b      	ldr	r3, [r7, #4]
+ 800770e:	681b      	ldr	r3, [r3, #0]
+ 8007710:	691b      	ldr	r3, [r3, #16]
+ 8007712:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
+ 8007716:	687b      	ldr	r3, [r7, #4]
+ 8007718:	68da      	ldr	r2, [r3, #12]
+ 800771a:	687b      	ldr	r3, [r7, #4]
+ 800771c:	681b      	ldr	r3, [r3, #0]
+ 800771e:	430a      	orrs	r2, r1
+ 8007720:	611a      	str	r2, [r3, #16]
   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
   MODIFY_REG(huart->Instance->CR1,
              (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
              tmpreg);
 #else
   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
- 8005c06:	687b      	ldr	r3, [r7, #4]
- 8005c08:	689a      	ldr	r2, [r3, #8]
- 8005c0a:	687b      	ldr	r3, [r7, #4]
- 8005c0c:	691b      	ldr	r3, [r3, #16]
- 8005c0e:	431a      	orrs	r2, r3
- 8005c10:	687b      	ldr	r3, [r7, #4]
- 8005c12:	695b      	ldr	r3, [r3, #20]
- 8005c14:	4313      	orrs	r3, r2
- 8005c16:	60bb      	str	r3, [r7, #8]
+ 8007722:	687b      	ldr	r3, [r7, #4]
+ 8007724:	689a      	ldr	r2, [r3, #8]
+ 8007726:	687b      	ldr	r3, [r7, #4]
+ 8007728:	691b      	ldr	r3, [r3, #16]
+ 800772a:	431a      	orrs	r2, r3
+ 800772c:	687b      	ldr	r3, [r7, #4]
+ 800772e:	695b      	ldr	r3, [r3, #20]
+ 8007730:	4313      	orrs	r3, r2
+ 8007732:	60bb      	str	r3, [r7, #8]
   MODIFY_REG(huart->Instance->CR1,
- 8005c18:	687b      	ldr	r3, [r7, #4]
- 8005c1a:	681b      	ldr	r3, [r3, #0]
- 8005c1c:	68db      	ldr	r3, [r3, #12]
- 8005c1e:	f423 53b0 	bic.w	r3, r3, #5632	@ 0x1600
- 8005c22:	f023 030c 	bic.w	r3, r3, #12
- 8005c26:	687a      	ldr	r2, [r7, #4]
- 8005c28:	6812      	ldr	r2, [r2, #0]
- 8005c2a:	68b9      	ldr	r1, [r7, #8]
- 8005c2c:	430b      	orrs	r3, r1
- 8005c2e:	60d3      	str	r3, [r2, #12]
+ 8007734:	687b      	ldr	r3, [r7, #4]
+ 8007736:	681b      	ldr	r3, [r3, #0]
+ 8007738:	68db      	ldr	r3, [r3, #12]
+ 800773a:	f423 53b0 	bic.w	r3, r3, #5632	@ 0x1600
+ 800773e:	f023 030c 	bic.w	r3, r3, #12
+ 8007742:	687a      	ldr	r2, [r7, #4]
+ 8007744:	6812      	ldr	r2, [r2, #0]
+ 8007746:	68b9      	ldr	r1, [r7, #8]
+ 8007748:	430b      	orrs	r3, r1
+ 800774a:	60d3      	str	r3, [r2, #12]
              tmpreg);
 #endif /* USART_CR1_OVER8 */
 
   /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
- 8005c30:	687b      	ldr	r3, [r7, #4]
- 8005c32:	681b      	ldr	r3, [r3, #0]
- 8005c34:	695b      	ldr	r3, [r3, #20]
- 8005c36:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
- 8005c3a:	687b      	ldr	r3, [r7, #4]
- 8005c3c:	699a      	ldr	r2, [r3, #24]
- 8005c3e:	687b      	ldr	r3, [r7, #4]
- 8005c40:	681b      	ldr	r3, [r3, #0]
- 8005c42:	430a      	orrs	r2, r1
- 8005c44:	615a      	str	r2, [r3, #20]
+ 800774c:	687b      	ldr	r3, [r7, #4]
+ 800774e:	681b      	ldr	r3, [r3, #0]
+ 8007750:	695b      	ldr	r3, [r3, #20]
+ 8007752:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
+ 8007756:	687b      	ldr	r3, [r7, #4]
+ 8007758:	699a      	ldr	r2, [r3, #24]
+ 800775a:	687b      	ldr	r3, [r7, #4]
+ 800775c:	681b      	ldr	r3, [r3, #0]
+ 800775e:	430a      	orrs	r2, r1
+ 8007760:	615a      	str	r2, [r3, #20]
 
 
   if(huart->Instance == USART1)
- 8005c46:	687b      	ldr	r3, [r7, #4]
- 8005c48:	681b      	ldr	r3, [r3, #0]
- 8005c4a:	4a2c      	ldr	r2, [pc, #176]	@ (8005cfc <UART_SetConfig+0x114>)
- 8005c4c:	4293      	cmp	r3, r2
- 8005c4e:	d103      	bne.n	8005c58 <UART_SetConfig+0x70>
+ 8007762:	687b      	ldr	r3, [r7, #4]
+ 8007764:	681b      	ldr	r3, [r3, #0]
+ 8007766:	4a2c      	ldr	r2, [pc, #176]	@ (8007818 <UART_SetConfig+0x114>)
+ 8007768:	4293      	cmp	r3, r2
+ 800776a:	d103      	bne.n	8007774 <UART_SetConfig+0x70>
   {
     pclk = HAL_RCC_GetPCLK2Freq();
- 8005c50:	f7ff f95a 	bl	8004f08 <HAL_RCC_GetPCLK2Freq>
- 8005c54:	60f8      	str	r0, [r7, #12]
- 8005c56:	e002      	b.n	8005c5e <UART_SetConfig+0x76>
+ 800776c:	f7fe fde0 	bl	8006330 <HAL_RCC_GetPCLK2Freq>
+ 8007770:	60f8      	str	r0, [r7, #12]
+ 8007772:	e002      	b.n	800777a <UART_SetConfig+0x76>
   }
   else
   {
     pclk = HAL_RCC_GetPCLK1Freq();
- 8005c58:	f7ff f942 	bl	8004ee0 <HAL_RCC_GetPCLK1Freq>
- 8005c5c:	60f8      	str	r0, [r7, #12]
+ 8007774:	f7fe fdc8 	bl	8006308 <HAL_RCC_GetPCLK1Freq>
+ 8007778:	60f8      	str	r0, [r7, #12]
   else
   {
     huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
   }
 #else
   huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
- 8005c5e:	68fa      	ldr	r2, [r7, #12]
- 8005c60:	4613      	mov	r3, r2
- 8005c62:	009b      	lsls	r3, r3, #2
- 8005c64:	4413      	add	r3, r2
- 8005c66:	009a      	lsls	r2, r3, #2
- 8005c68:	441a      	add	r2, r3
- 8005c6a:	687b      	ldr	r3, [r7, #4]
- 8005c6c:	685b      	ldr	r3, [r3, #4]
- 8005c6e:	009b      	lsls	r3, r3, #2
- 8005c70:	fbb2 f3f3 	udiv	r3, r2, r3
- 8005c74:	4a22      	ldr	r2, [pc, #136]	@ (8005d00 <UART_SetConfig+0x118>)
- 8005c76:	fba2 2303 	umull	r2, r3, r2, r3
- 8005c7a:	095b      	lsrs	r3, r3, #5
- 8005c7c:	0119      	lsls	r1, r3, #4
- 8005c7e:	68fa      	ldr	r2, [r7, #12]
- 8005c80:	4613      	mov	r3, r2
- 8005c82:	009b      	lsls	r3, r3, #2
- 8005c84:	4413      	add	r3, r2
- 8005c86:	009a      	lsls	r2, r3, #2
- 8005c88:	441a      	add	r2, r3
- 8005c8a:	687b      	ldr	r3, [r7, #4]
- 8005c8c:	685b      	ldr	r3, [r3, #4]
- 8005c8e:	009b      	lsls	r3, r3, #2
- 8005c90:	fbb2 f2f3 	udiv	r2, r2, r3
- 8005c94:	4b1a      	ldr	r3, [pc, #104]	@ (8005d00 <UART_SetConfig+0x118>)
- 8005c96:	fba3 0302 	umull	r0, r3, r3, r2
- 8005c9a:	095b      	lsrs	r3, r3, #5
- 8005c9c:	2064      	movs	r0, #100	@ 0x64
- 8005c9e:	fb00 f303 	mul.w	r3, r0, r3
- 8005ca2:	1ad3      	subs	r3, r2, r3
- 8005ca4:	011b      	lsls	r3, r3, #4
- 8005ca6:	3332      	adds	r3, #50	@ 0x32
- 8005ca8:	4a15      	ldr	r2, [pc, #84]	@ (8005d00 <UART_SetConfig+0x118>)
- 8005caa:	fba2 2303 	umull	r2, r3, r2, r3
- 8005cae:	095b      	lsrs	r3, r3, #5
- 8005cb0:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
- 8005cb4:	4419      	add	r1, r3
- 8005cb6:	68fa      	ldr	r2, [r7, #12]
- 8005cb8:	4613      	mov	r3, r2
- 8005cba:	009b      	lsls	r3, r3, #2
- 8005cbc:	4413      	add	r3, r2
- 8005cbe:	009a      	lsls	r2, r3, #2
- 8005cc0:	441a      	add	r2, r3
- 8005cc2:	687b      	ldr	r3, [r7, #4]
- 8005cc4:	685b      	ldr	r3, [r3, #4]
- 8005cc6:	009b      	lsls	r3, r3, #2
- 8005cc8:	fbb2 f2f3 	udiv	r2, r2, r3
- 8005ccc:	4b0c      	ldr	r3, [pc, #48]	@ (8005d00 <UART_SetConfig+0x118>)
- 8005cce:	fba3 0302 	umull	r0, r3, r3, r2
- 8005cd2:	095b      	lsrs	r3, r3, #5
- 8005cd4:	2064      	movs	r0, #100	@ 0x64
- 8005cd6:	fb00 f303 	mul.w	r3, r0, r3
- 8005cda:	1ad3      	subs	r3, r2, r3
- 8005cdc:	011b      	lsls	r3, r3, #4
- 8005cde:	3332      	adds	r3, #50	@ 0x32
- 8005ce0:	4a07      	ldr	r2, [pc, #28]	@ (8005d00 <UART_SetConfig+0x118>)
- 8005ce2:	fba2 2303 	umull	r2, r3, r2, r3
- 8005ce6:	095b      	lsrs	r3, r3, #5
- 8005ce8:	f003 020f 	and.w	r2, r3, #15
- 8005cec:	687b      	ldr	r3, [r7, #4]
- 8005cee:	681b      	ldr	r3, [r3, #0]
- 8005cf0:	440a      	add	r2, r1
- 8005cf2:	609a      	str	r2, [r3, #8]
+ 800777a:	68fa      	ldr	r2, [r7, #12]
+ 800777c:	4613      	mov	r3, r2
+ 800777e:	009b      	lsls	r3, r3, #2
+ 8007780:	4413      	add	r3, r2
+ 8007782:	009a      	lsls	r2, r3, #2
+ 8007784:	441a      	add	r2, r3
+ 8007786:	687b      	ldr	r3, [r7, #4]
+ 8007788:	685b      	ldr	r3, [r3, #4]
+ 800778a:	009b      	lsls	r3, r3, #2
+ 800778c:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8007790:	4a22      	ldr	r2, [pc, #136]	@ (800781c <UART_SetConfig+0x118>)
+ 8007792:	fba2 2303 	umull	r2, r3, r2, r3
+ 8007796:	095b      	lsrs	r3, r3, #5
+ 8007798:	0119      	lsls	r1, r3, #4
+ 800779a:	68fa      	ldr	r2, [r7, #12]
+ 800779c:	4613      	mov	r3, r2
+ 800779e:	009b      	lsls	r3, r3, #2
+ 80077a0:	4413      	add	r3, r2
+ 80077a2:	009a      	lsls	r2, r3, #2
+ 80077a4:	441a      	add	r2, r3
+ 80077a6:	687b      	ldr	r3, [r7, #4]
+ 80077a8:	685b      	ldr	r3, [r3, #4]
+ 80077aa:	009b      	lsls	r3, r3, #2
+ 80077ac:	fbb2 f2f3 	udiv	r2, r2, r3
+ 80077b0:	4b1a      	ldr	r3, [pc, #104]	@ (800781c <UART_SetConfig+0x118>)
+ 80077b2:	fba3 0302 	umull	r0, r3, r3, r2
+ 80077b6:	095b      	lsrs	r3, r3, #5
+ 80077b8:	2064      	movs	r0, #100	@ 0x64
+ 80077ba:	fb00 f303 	mul.w	r3, r0, r3
+ 80077be:	1ad3      	subs	r3, r2, r3
+ 80077c0:	011b      	lsls	r3, r3, #4
+ 80077c2:	3332      	adds	r3, #50	@ 0x32
+ 80077c4:	4a15      	ldr	r2, [pc, #84]	@ (800781c <UART_SetConfig+0x118>)
+ 80077c6:	fba2 2303 	umull	r2, r3, r2, r3
+ 80077ca:	095b      	lsrs	r3, r3, #5
+ 80077cc:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
+ 80077d0:	4419      	add	r1, r3
+ 80077d2:	68fa      	ldr	r2, [r7, #12]
+ 80077d4:	4613      	mov	r3, r2
+ 80077d6:	009b      	lsls	r3, r3, #2
+ 80077d8:	4413      	add	r3, r2
+ 80077da:	009a      	lsls	r2, r3, #2
+ 80077dc:	441a      	add	r2, r3
+ 80077de:	687b      	ldr	r3, [r7, #4]
+ 80077e0:	685b      	ldr	r3, [r3, #4]
+ 80077e2:	009b      	lsls	r3, r3, #2
+ 80077e4:	fbb2 f2f3 	udiv	r2, r2, r3
+ 80077e8:	4b0c      	ldr	r3, [pc, #48]	@ (800781c <UART_SetConfig+0x118>)
+ 80077ea:	fba3 0302 	umull	r0, r3, r3, r2
+ 80077ee:	095b      	lsrs	r3, r3, #5
+ 80077f0:	2064      	movs	r0, #100	@ 0x64
+ 80077f2:	fb00 f303 	mul.w	r3, r0, r3
+ 80077f6:	1ad3      	subs	r3, r2, r3
+ 80077f8:	011b      	lsls	r3, r3, #4
+ 80077fa:	3332      	adds	r3, #50	@ 0x32
+ 80077fc:	4a07      	ldr	r2, [pc, #28]	@ (800781c <UART_SetConfig+0x118>)
+ 80077fe:	fba2 2303 	umull	r2, r3, r2, r3
+ 8007802:	095b      	lsrs	r3, r3, #5
+ 8007804:	f003 020f 	and.w	r2, r3, #15
+ 8007808:	687b      	ldr	r3, [r7, #4]
+ 800780a:	681b      	ldr	r3, [r3, #0]
+ 800780c:	440a      	add	r2, r1
+ 800780e:	609a      	str	r2, [r3, #8]
 #endif /* USART_CR1_OVER8 */
 }
- 8005cf4:	bf00      	nop
- 8005cf6:	3710      	adds	r7, #16
- 8005cf8:	46bd      	mov	sp, r7
- 8005cfa:	bd80      	pop	{r7, pc}
- 8005cfc:	40013800 	.word	0x40013800
- 8005d00:	51eb851f 	.word	0x51eb851f
+ 8007810:	bf00      	nop
+ 8007812:	3710      	adds	r7, #16
+ 8007814:	46bd      	mov	sp, r7
+ 8007816:	bd80      	pop	{r7, pc}
+ 8007818:	40013800 	.word	0x40013800
+ 800781c:	51eb851f 	.word	0x51eb851f
 
-08005d04 <memset>:
- 8005d04:	4603      	mov	r3, r0
- 8005d06:	4402      	add	r2, r0
- 8005d08:	4293      	cmp	r3, r2
- 8005d0a:	d100      	bne.n	8005d0e <memset+0xa>
- 8005d0c:	4770      	bx	lr
- 8005d0e:	f803 1b01 	strb.w	r1, [r3], #1
- 8005d12:	e7f9      	b.n	8005d08 <memset+0x4>
+08007820 <memset>:
+ 8007820:	4603      	mov	r3, r0
+ 8007822:	4402      	add	r2, r0
+ 8007824:	4293      	cmp	r3, r2
+ 8007826:	d100      	bne.n	800782a <memset+0xa>
+ 8007828:	4770      	bx	lr
+ 800782a:	f803 1b01 	strb.w	r1, [r3], #1
+ 800782e:	e7f9      	b.n	8007824 <memset+0x4>
 
-08005d14 <__errno>:
- 8005d14:	4b01      	ldr	r3, [pc, #4]	@ (8005d1c <__errno+0x8>)
- 8005d16:	6818      	ldr	r0, [r3, #0]
- 8005d18:	4770      	bx	lr
- 8005d1a:	bf00      	nop
- 8005d1c:	20000028 	.word	0x20000028
+08007830 <__errno>:
+ 8007830:	4b01      	ldr	r3, [pc, #4]	@ (8007838 <__errno+0x8>)
+ 8007832:	6818      	ldr	r0, [r3, #0]
+ 8007834:	4770      	bx	lr
+ 8007836:	bf00      	nop
+ 8007838:	20000030 	.word	0x20000030
 
-08005d20 <__libc_init_array>:
- 8005d20:	b570      	push	{r4, r5, r6, lr}
- 8005d22:	2600      	movs	r6, #0
- 8005d24:	4d0c      	ldr	r5, [pc, #48]	@ (8005d58 <__libc_init_array+0x38>)
- 8005d26:	4b0d      	ldr	r3, [pc, #52]	@ (8005d5c <__libc_init_array+0x3c>)
- 8005d28:	1b5b      	subs	r3, r3, r5
- 8005d2a:	109c      	asrs	r4, r3, #2
- 8005d2c:	42a6      	cmp	r6, r4
- 8005d2e:	d109      	bne.n	8005d44 <__libc_init_array+0x24>
- 8005d30:	2600      	movs	r6, #0
- 8005d32:	f000 f8cd 	bl	8005ed0 <_init>
- 8005d36:	4d0a      	ldr	r5, [pc, #40]	@ (8005d60 <__libc_init_array+0x40>)
- 8005d38:	4b0a      	ldr	r3, [pc, #40]	@ (8005d64 <__libc_init_array+0x44>)
- 8005d3a:	1b5b      	subs	r3, r3, r5
- 8005d3c:	109c      	asrs	r4, r3, #2
- 8005d3e:	42a6      	cmp	r6, r4
- 8005d40:	d105      	bne.n	8005d4e <__libc_init_array+0x2e>
- 8005d42:	bd70      	pop	{r4, r5, r6, pc}
- 8005d44:	f855 3b04 	ldr.w	r3, [r5], #4
- 8005d48:	4798      	blx	r3
- 8005d4a:	3601      	adds	r6, #1
- 8005d4c:	e7ee      	b.n	8005d2c <__libc_init_array+0xc>
- 8005d4e:	f855 3b04 	ldr.w	r3, [r5], #4
- 8005d52:	4798      	blx	r3
- 8005d54:	3601      	adds	r6, #1
- 8005d56:	e7f2      	b.n	8005d3e <__libc_init_array+0x1e>
- 8005d58:	08005f70 	.word	0x08005f70
- 8005d5c:	08005f70 	.word	0x08005f70
- 8005d60:	08005f70 	.word	0x08005f70
- 8005d64:	08005f74 	.word	0x08005f74
+0800783c <__libc_init_array>:
+ 800783c:	b570      	push	{r4, r5, r6, lr}
+ 800783e:	2600      	movs	r6, #0
+ 8007840:	4d0c      	ldr	r5, [pc, #48]	@ (8007874 <__libc_init_array+0x38>)
+ 8007842:	4b0d      	ldr	r3, [pc, #52]	@ (8007878 <__libc_init_array+0x3c>)
+ 8007844:	1b5b      	subs	r3, r3, r5
+ 8007846:	109c      	asrs	r4, r3, #2
+ 8007848:	42a6      	cmp	r6, r4
+ 800784a:	d109      	bne.n	8007860 <__libc_init_array+0x24>
+ 800784c:	2600      	movs	r6, #0
+ 800784e:	f000 f8db 	bl	8007a08 <_init>
+ 8007852:	4d0a      	ldr	r5, [pc, #40]	@ (800787c <__libc_init_array+0x40>)
+ 8007854:	4b0a      	ldr	r3, [pc, #40]	@ (8007880 <__libc_init_array+0x44>)
+ 8007856:	1b5b      	subs	r3, r3, r5
+ 8007858:	109c      	asrs	r4, r3, #2
+ 800785a:	42a6      	cmp	r6, r4
+ 800785c:	d105      	bne.n	800786a <__libc_init_array+0x2e>
+ 800785e:	bd70      	pop	{r4, r5, r6, pc}
+ 8007860:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8007864:	4798      	blx	r3
+ 8007866:	3601      	adds	r6, #1
+ 8007868:	e7ee      	b.n	8007848 <__libc_init_array+0xc>
+ 800786a:	f855 3b04 	ldr.w	r3, [r5], #4
+ 800786e:	4798      	blx	r3
+ 8007870:	3601      	adds	r6, #1
+ 8007872:	e7f2      	b.n	800785a <__libc_init_array+0x1e>
+ 8007874:	08007ab0 	.word	0x08007ab0
+ 8007878:	08007ab0 	.word	0x08007ab0
+ 800787c:	08007ab0 	.word	0x08007ab0
+ 8007880:	08007ab4 	.word	0x08007ab4
 
-08005d68 <sqrtf>:
- 8005d68:	b538      	push	{r3, r4, r5, lr}
- 8005d6a:	4604      	mov	r4, r0
- 8005d6c:	f000 f81a 	bl	8005da4 <__ieee754_sqrtf>
- 8005d70:	4621      	mov	r1, r4
- 8005d72:	4605      	mov	r5, r0
- 8005d74:	4620      	mov	r0, r4
- 8005d76:	f7fa ffd3 	bl	8000d20 <__aeabi_fcmpun>
- 8005d7a:	b920      	cbnz	r0, 8005d86 <sqrtf+0x1e>
- 8005d7c:	4620      	mov	r0, r4
- 8005d7e:	2100      	movs	r1, #0
- 8005d80:	f7fa ffa6 	bl	8000cd0 <__aeabi_fcmplt>
- 8005d84:	b908      	cbnz	r0, 8005d8a <sqrtf+0x22>
- 8005d86:	4628      	mov	r0, r5
- 8005d88:	bd38      	pop	{r3, r4, r5, pc}
- 8005d8a:	f7ff ffc3 	bl	8005d14 <__errno>
- 8005d8e:	2221      	movs	r2, #33	@ 0x21
- 8005d90:	4603      	mov	r3, r0
- 8005d92:	2100      	movs	r1, #0
- 8005d94:	601a      	str	r2, [r3, #0]
- 8005d96:	4608      	mov	r0, r1
- 8005d98:	f7fa feb0 	bl	8000afc <__aeabi_fdiv>
- 8005d9c:	4605      	mov	r5, r0
- 8005d9e:	4628      	mov	r0, r5
- 8005da0:	bd38      	pop	{r3, r4, r5, pc}
- 8005da2:	bf00      	nop
+08007884 <memcpy>:
+ 8007884:	440a      	add	r2, r1
+ 8007886:	4291      	cmp	r1, r2
+ 8007888:	f100 33ff 	add.w	r3, r0, #4294967295
+ 800788c:	d100      	bne.n	8007890 <memcpy+0xc>
+ 800788e:	4770      	bx	lr
+ 8007890:	b510      	push	{r4, lr}
+ 8007892:	f811 4b01 	ldrb.w	r4, [r1], #1
+ 8007896:	4291      	cmp	r1, r2
+ 8007898:	f803 4f01 	strb.w	r4, [r3, #1]!
+ 800789c:	d1f9      	bne.n	8007892 <memcpy+0xe>
+ 800789e:	bd10      	pop	{r4, pc}
 
-08005da4 <__ieee754_sqrtf>:
- 8005da4:	f020 4200 	bic.w	r2, r0, #2147483648	@ 0x80000000
- 8005da8:	f1b2 4fff 	cmp.w	r2, #2139095040	@ 0x7f800000
- 8005dac:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
- 8005db0:	4604      	mov	r4, r0
- 8005db2:	d24f      	bcs.n	8005e54 <__ieee754_sqrtf+0xb0>
- 8005db4:	2a00      	cmp	r2, #0
- 8005db6:	d04b      	beq.n	8005e50 <__ieee754_sqrtf+0xac>
- 8005db8:	2800      	cmp	r0, #0
- 8005dba:	4603      	mov	r3, r0
- 8005dbc:	db54      	blt.n	8005e68 <__ieee754_sqrtf+0xc4>
- 8005dbe:	f010 42ff 	ands.w	r2, r0, #2139095040	@ 0x7f800000
- 8005dc2:	d14f      	bne.n	8005e64 <__ieee754_sqrtf+0xc0>
- 8005dc4:	005b      	lsls	r3, r3, #1
- 8005dc6:	0218      	lsls	r0, r3, #8
- 8005dc8:	4611      	mov	r1, r2
- 8005dca:	f102 0201 	add.w	r2, r2, #1
- 8005dce:	d5f9      	bpl.n	8005dc4 <__ieee754_sqrtf+0x20>
- 8005dd0:	4249      	negs	r1, r1
- 8005dd2:	2400      	movs	r4, #0
- 8005dd4:	f3c3 0216 	ubfx	r2, r3, #0, #23
- 8005dd8:	f1a1 057f 	sub.w	r5, r1, #127	@ 0x7f
- 8005ddc:	07cb      	lsls	r3, r1, #31
- 8005dde:	f04f 0e19 	mov.w	lr, #25
- 8005de2:	f04f 7c80 	mov.w	ip, #16777216	@ 0x1000000
- 8005de6:	4621      	mov	r1, r4
- 8005de8:	f442 0200 	orr.w	r2, r2, #8388608	@ 0x800000
- 8005dec:	bf58      	it	pl
- 8005dee:	0052      	lslpl	r2, r2, #1
- 8005df0:	106d      	asrs	r5, r5, #1
- 8005df2:	0052      	lsls	r2, r2, #1
- 8005df4:	eb01 030c 	add.w	r3, r1, ip
- 8005df8:	4293      	cmp	r3, r2
- 8005dfa:	bfcf      	iteee	gt
- 8005dfc:	4613      	movgt	r3, r2
- 8005dfe:	eb03 010c 	addle.w	r1, r3, ip
- 8005e02:	4464      	addle	r4, ip
- 8005e04:	1ad3      	suble	r3, r2, r3
- 8005e06:	f1be 0e01 	subs.w	lr, lr, #1
- 8005e0a:	ea4f 0243 	mov.w	r2, r3, lsl #1
- 8005e0e:	ea4f 0c5c 	mov.w	ip, ip, lsr #1
- 8005e12:	d1ef      	bne.n	8005df4 <__ieee754_sqrtf+0x50>
- 8005e14:	b1bb      	cbz	r3, 8005e46 <__ieee754_sqrtf+0xa2>
- 8005e16:	4e1a      	ldr	r6, [pc, #104]	@ (8005e80 <__ieee754_sqrtf+0xdc>)
- 8005e18:	4f1a      	ldr	r7, [pc, #104]	@ (8005e84 <__ieee754_sqrtf+0xe0>)
- 8005e1a:	6830      	ldr	r0, [r6, #0]
- 8005e1c:	6839      	ldr	r1, [r7, #0]
- 8005e1e:	f7fa fcaf 	bl	8000780 <__aeabi_fsub>
- 8005e22:	f8d6 8000 	ldr.w	r8, [r6]
- 8005e26:	4601      	mov	r1, r0
- 8005e28:	4640      	mov	r0, r8
- 8005e2a:	f7fa ff5b 	bl	8000ce4 <__aeabi_fcmple>
- 8005e2e:	b150      	cbz	r0, 8005e46 <__ieee754_sqrtf+0xa2>
- 8005e30:	6830      	ldr	r0, [r6, #0]
- 8005e32:	6839      	ldr	r1, [r7, #0]
- 8005e34:	f7fa fca6 	bl	8000784 <__addsf3>
- 8005e38:	6836      	ldr	r6, [r6, #0]
- 8005e3a:	4601      	mov	r1, r0
- 8005e3c:	4630      	mov	r0, r6
- 8005e3e:	f7fa ff47 	bl	8000cd0 <__aeabi_fcmplt>
- 8005e42:	b1c8      	cbz	r0, 8005e78 <__ieee754_sqrtf+0xd4>
- 8005e44:	3402      	adds	r4, #2
- 8005e46:	1060      	asrs	r0, r4, #1
- 8005e48:	f100 507c 	add.w	r0, r0, #1056964608	@ 0x3f000000
- 8005e4c:	eb00 50c5 	add.w	r0, r0, r5, lsl #23
- 8005e50:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
- 8005e54:	4601      	mov	r1, r0
- 8005e56:	f7fa fd9d 	bl	8000994 <__aeabi_fmul>
- 8005e5a:	4621      	mov	r1, r4
- 8005e5c:	f7fa fc92 	bl	8000784 <__addsf3>
- 8005e60:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
- 8005e64:	15c1      	asrs	r1, r0, #23
- 8005e66:	e7b4      	b.n	8005dd2 <__ieee754_sqrtf+0x2e>
- 8005e68:	4601      	mov	r1, r0
- 8005e6a:	f7fa fc89 	bl	8000780 <__aeabi_fsub>
- 8005e6e:	4601      	mov	r1, r0
- 8005e70:	f7fa fe44 	bl	8000afc <__aeabi_fdiv>
- 8005e74:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
- 8005e78:	3401      	adds	r4, #1
- 8005e7a:	f024 0401 	bic.w	r4, r4, #1
- 8005e7e:	e7e2      	b.n	8005e46 <__ieee754_sqrtf+0xa2>
- 8005e80:	08005f64 	.word	0x08005f64
- 8005e84:	08005f60 	.word	0x08005f60
+080078a0 <sqrtf>:
+ 80078a0:	b538      	push	{r3, r4, r5, lr}
+ 80078a2:	4604      	mov	r4, r0
+ 80078a4:	f000 f81a 	bl	80078dc <__ieee754_sqrtf>
+ 80078a8:	4621      	mov	r1, r4
+ 80078aa:	4605      	mov	r5, r0
+ 80078ac:	4620      	mov	r0, r4
+ 80078ae:	f7f9 fbf9 	bl	80010a4 <__aeabi_fcmpun>
+ 80078b2:	b920      	cbnz	r0, 80078be <sqrtf+0x1e>
+ 80078b4:	4620      	mov	r0, r4
+ 80078b6:	2100      	movs	r1, #0
+ 80078b8:	f7f9 fbcc 	bl	8001054 <__aeabi_fcmplt>
+ 80078bc:	b908      	cbnz	r0, 80078c2 <sqrtf+0x22>
+ 80078be:	4628      	mov	r0, r5
+ 80078c0:	bd38      	pop	{r3, r4, r5, pc}
+ 80078c2:	f7ff ffb5 	bl	8007830 <__errno>
+ 80078c6:	2221      	movs	r2, #33	@ 0x21
+ 80078c8:	4603      	mov	r3, r0
+ 80078ca:	2100      	movs	r1, #0
+ 80078cc:	601a      	str	r2, [r3, #0]
+ 80078ce:	4608      	mov	r0, r1
+ 80078d0:	f7f9 fad6 	bl	8000e80 <__aeabi_fdiv>
+ 80078d4:	4605      	mov	r5, r0
+ 80078d6:	4628      	mov	r0, r5
+ 80078d8:	bd38      	pop	{r3, r4, r5, pc}
+ 80078da:	bf00      	nop
 
-08005e88 <roundf>:
- 8005e88:	b508      	push	{r3, lr}
- 8005e8a:	f3c0 53c7 	ubfx	r3, r0, #23, #8
- 8005e8e:	3b7f      	subs	r3, #127	@ 0x7f
- 8005e90:	2b16      	cmp	r3, #22
- 8005e92:	4601      	mov	r1, r0
- 8005e94:	dc0e      	bgt.n	8005eb4 <roundf+0x2c>
- 8005e96:	2b00      	cmp	r3, #0
- 8005e98:	4602      	mov	r2, r0
- 8005e9a:	db10      	blt.n	8005ebe <roundf+0x36>
- 8005e9c:	480b      	ldr	r0, [pc, #44]	@ (8005ecc <roundf+0x44>)
- 8005e9e:	4118      	asrs	r0, r3
- 8005ea0:	4201      	tst	r1, r0
- 8005ea2:	d005      	beq.n	8005eb0 <roundf+0x28>
- 8005ea4:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
- 8005ea8:	4119      	asrs	r1, r3
- 8005eaa:	4411      	add	r1, r2
- 8005eac:	ea21 0100 	bic.w	r1, r1, r0
- 8005eb0:	4608      	mov	r0, r1
- 8005eb2:	bd08      	pop	{r3, pc}
- 8005eb4:	2b80      	cmp	r3, #128	@ 0x80
- 8005eb6:	d1fb      	bne.n	8005eb0 <roundf+0x28>
- 8005eb8:	f7fa fc64 	bl	8000784 <__addsf3>
- 8005ebc:	bd08      	pop	{r3, pc}
- 8005ebe:	3301      	adds	r3, #1
- 8005ec0:	f000 4100 	and.w	r1, r0, #2147483648	@ 0x80000000
- 8005ec4:	d1f4      	bne.n	8005eb0 <roundf+0x28>
- 8005ec6:	f041 517e 	orr.w	r1, r1, #1065353216	@ 0x3f800000
- 8005eca:	e7f1      	b.n	8005eb0 <roundf+0x28>
- 8005ecc:	007fffff 	.word	0x007fffff
+080078dc <__ieee754_sqrtf>:
+ 80078dc:	f020 4200 	bic.w	r2, r0, #2147483648	@ 0x80000000
+ 80078e0:	f1b2 4fff 	cmp.w	r2, #2139095040	@ 0x7f800000
+ 80078e4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 80078e8:	4604      	mov	r4, r0
+ 80078ea:	d24f      	bcs.n	800798c <__ieee754_sqrtf+0xb0>
+ 80078ec:	2a00      	cmp	r2, #0
+ 80078ee:	d04b      	beq.n	8007988 <__ieee754_sqrtf+0xac>
+ 80078f0:	2800      	cmp	r0, #0
+ 80078f2:	4603      	mov	r3, r0
+ 80078f4:	db54      	blt.n	80079a0 <__ieee754_sqrtf+0xc4>
+ 80078f6:	f010 42ff 	ands.w	r2, r0, #2139095040	@ 0x7f800000
+ 80078fa:	d14f      	bne.n	800799c <__ieee754_sqrtf+0xc0>
+ 80078fc:	005b      	lsls	r3, r3, #1
+ 80078fe:	0218      	lsls	r0, r3, #8
+ 8007900:	4611      	mov	r1, r2
+ 8007902:	f102 0201 	add.w	r2, r2, #1
+ 8007906:	d5f9      	bpl.n	80078fc <__ieee754_sqrtf+0x20>
+ 8007908:	4249      	negs	r1, r1
+ 800790a:	2400      	movs	r4, #0
+ 800790c:	f3c3 0216 	ubfx	r2, r3, #0, #23
+ 8007910:	f1a1 057f 	sub.w	r5, r1, #127	@ 0x7f
+ 8007914:	07cb      	lsls	r3, r1, #31
+ 8007916:	f04f 0e19 	mov.w	lr, #25
+ 800791a:	f04f 7c80 	mov.w	ip, #16777216	@ 0x1000000
+ 800791e:	4621      	mov	r1, r4
+ 8007920:	f442 0200 	orr.w	r2, r2, #8388608	@ 0x800000
+ 8007924:	bf58      	it	pl
+ 8007926:	0052      	lslpl	r2, r2, #1
+ 8007928:	106d      	asrs	r5, r5, #1
+ 800792a:	0052      	lsls	r2, r2, #1
+ 800792c:	eb01 030c 	add.w	r3, r1, ip
+ 8007930:	4293      	cmp	r3, r2
+ 8007932:	bfcf      	iteee	gt
+ 8007934:	4613      	movgt	r3, r2
+ 8007936:	eb03 010c 	addle.w	r1, r3, ip
+ 800793a:	4464      	addle	r4, ip
+ 800793c:	1ad3      	suble	r3, r2, r3
+ 800793e:	f1be 0e01 	subs.w	lr, lr, #1
+ 8007942:	ea4f 0243 	mov.w	r2, r3, lsl #1
+ 8007946:	ea4f 0c5c 	mov.w	ip, ip, lsr #1
+ 800794a:	d1ef      	bne.n	800792c <__ieee754_sqrtf+0x50>
+ 800794c:	b1bb      	cbz	r3, 800797e <__ieee754_sqrtf+0xa2>
+ 800794e:	4e1a      	ldr	r6, [pc, #104]	@ (80079b8 <__ieee754_sqrtf+0xdc>)
+ 8007950:	4f1a      	ldr	r7, [pc, #104]	@ (80079bc <__ieee754_sqrtf+0xe0>)
+ 8007952:	6830      	ldr	r0, [r6, #0]
+ 8007954:	6839      	ldr	r1, [r7, #0]
+ 8007956:	f7f9 f8d5 	bl	8000b04 <__aeabi_fsub>
+ 800795a:	f8d6 8000 	ldr.w	r8, [r6]
+ 800795e:	4601      	mov	r1, r0
+ 8007960:	4640      	mov	r0, r8
+ 8007962:	f7f9 fb81 	bl	8001068 <__aeabi_fcmple>
+ 8007966:	b150      	cbz	r0, 800797e <__ieee754_sqrtf+0xa2>
+ 8007968:	6830      	ldr	r0, [r6, #0]
+ 800796a:	6839      	ldr	r1, [r7, #0]
+ 800796c:	f7f9 f8cc 	bl	8000b08 <__addsf3>
+ 8007970:	6836      	ldr	r6, [r6, #0]
+ 8007972:	4601      	mov	r1, r0
+ 8007974:	4630      	mov	r0, r6
+ 8007976:	f7f9 fb6d 	bl	8001054 <__aeabi_fcmplt>
+ 800797a:	b1c8      	cbz	r0, 80079b0 <__ieee754_sqrtf+0xd4>
+ 800797c:	3402      	adds	r4, #2
+ 800797e:	1060      	asrs	r0, r4, #1
+ 8007980:	f100 507c 	add.w	r0, r0, #1056964608	@ 0x3f000000
+ 8007984:	eb00 50c5 	add.w	r0, r0, r5, lsl #23
+ 8007988:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 800798c:	4601      	mov	r1, r0
+ 800798e:	f7f9 f9c3 	bl	8000d18 <__aeabi_fmul>
+ 8007992:	4621      	mov	r1, r4
+ 8007994:	f7f9 f8b8 	bl	8000b08 <__addsf3>
+ 8007998:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 800799c:	15c1      	asrs	r1, r0, #23
+ 800799e:	e7b4      	b.n	800790a <__ieee754_sqrtf+0x2e>
+ 80079a0:	4601      	mov	r1, r0
+ 80079a2:	f7f9 f8af 	bl	8000b04 <__aeabi_fsub>
+ 80079a6:	4601      	mov	r1, r0
+ 80079a8:	f7f9 fa6a 	bl	8000e80 <__aeabi_fdiv>
+ 80079ac:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80079b0:	3401      	adds	r4, #1
+ 80079b2:	f024 0401 	bic.w	r4, r4, #1
+ 80079b6:	e7e2      	b.n	800797e <__ieee754_sqrtf+0xa2>
+ 80079b8:	08007aa4 	.word	0x08007aa4
+ 80079bc:	08007aa0 	.word	0x08007aa0
 
-08005ed0 <_init>:
- 8005ed0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8005ed2:	bf00      	nop
- 8005ed4:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8005ed6:	bc08      	pop	{r3}
- 8005ed8:	469e      	mov	lr, r3
- 8005eda:	4770      	bx	lr
+080079c0 <roundf>:
+ 80079c0:	b508      	push	{r3, lr}
+ 80079c2:	f3c0 53c7 	ubfx	r3, r0, #23, #8
+ 80079c6:	3b7f      	subs	r3, #127	@ 0x7f
+ 80079c8:	2b16      	cmp	r3, #22
+ 80079ca:	4601      	mov	r1, r0
+ 80079cc:	dc0e      	bgt.n	80079ec <roundf+0x2c>
+ 80079ce:	2b00      	cmp	r3, #0
+ 80079d0:	4602      	mov	r2, r0
+ 80079d2:	db10      	blt.n	80079f6 <roundf+0x36>
+ 80079d4:	480b      	ldr	r0, [pc, #44]	@ (8007a04 <roundf+0x44>)
+ 80079d6:	4118      	asrs	r0, r3
+ 80079d8:	4201      	tst	r1, r0
+ 80079da:	d005      	beq.n	80079e8 <roundf+0x28>
+ 80079dc:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
+ 80079e0:	4119      	asrs	r1, r3
+ 80079e2:	4411      	add	r1, r2
+ 80079e4:	ea21 0100 	bic.w	r1, r1, r0
+ 80079e8:	4608      	mov	r0, r1
+ 80079ea:	bd08      	pop	{r3, pc}
+ 80079ec:	2b80      	cmp	r3, #128	@ 0x80
+ 80079ee:	d1fb      	bne.n	80079e8 <roundf+0x28>
+ 80079f0:	f7f9 f88a 	bl	8000b08 <__addsf3>
+ 80079f4:	bd08      	pop	{r3, pc}
+ 80079f6:	3301      	adds	r3, #1
+ 80079f8:	f000 4100 	and.w	r1, r0, #2147483648	@ 0x80000000
+ 80079fc:	d1f4      	bne.n	80079e8 <roundf+0x28>
+ 80079fe:	f041 517e 	orr.w	r1, r1, #1065353216	@ 0x3f800000
+ 8007a02:	e7f1      	b.n	80079e8 <roundf+0x28>
+ 8007a04:	007fffff 	.word	0x007fffff
 
-08005edc <_fini>:
- 8005edc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8005ede:	bf00      	nop
- 8005ee0:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8005ee2:	bc08      	pop	{r3}
- 8005ee4:	469e      	mov	lr, r3
- 8005ee6:	4770      	bx	lr
+08007a08 <_init>:
+ 8007a08:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8007a0a:	bf00      	nop
+ 8007a0c:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8007a0e:	bc08      	pop	{r3}
+ 8007a10:	469e      	mov	lr, r3
+ 8007a12:	4770      	bx	lr
+
+08007a14 <_fini>:
+ 8007a14:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8007a16:	bf00      	nop
+ 8007a18:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8007a1a:	bc08      	pop	{r3}
+ 8007a1c:	469e      	mov	lr, r3
+ 8007a1e:	4770      	bx	lr
diff --git a/Fertirrega_v6/Debug/Fertirrega_v6.map b/Fertirrega_v6/Debug/Fertirrega_v6.map
index 99ca259..61da399 100644
--- a/Fertirrega_v6/Debug/Fertirrega_v6.map
+++ b/Fertirrega_v6/Debug/Fertirrega_v6.map
@@ -54,8 +54,14 @@ C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externalt
                               ./Core/Src/ad5934_driver.o (__aeabi_fmul)
 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubdf3.o)
                               ./Core/Src/main.o (__aeabi_dsub)
+C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldivdf3.o)
+                              ./Core/Src/main.o (__aeabi_ddiv)
+C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_cmpdf2.o)
+                              ./Core/Src/main.o (__aeabi_dcmplt)
 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_fixdfsi.o)
                               ./Core/Src/main.o (__aeabi_d2iz)
+C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_truncdfsf2.o)
+                              ./Core/Src/main.o (__aeabi_d2f)
 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubsf3.o)
                               ./Core/Src/ad5934_driver.o (__aeabi_fsub)
 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldivsf3.o)
@@ -138,6 +144,12 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
  .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
  .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
+ .group         0x00000000        0xc ./Core/Src/ad5934_driver.o
  .text          0x00000000        0x0 ./Core/Src/ad5934_driver.o
  .data          0x00000000        0x0 ./Core/Src/ad5934_driver.o
  .bss           0x00000000        0x0 ./Core/Src/ad5934_driver.o
@@ -184,13 +196,14 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/adc.o
  .group         0x00000000        0xc ./Core/Src/adc.o
  .group         0x00000000        0xc ./Core/Src/adc.o
+ .group         0x00000000        0xc ./Core/Src/adc.o
  .text          0x00000000        0x0 ./Core/Src/adc.o
  .data          0x00000000        0x0 ./Core/Src/adc.o
  .bss           0x00000000        0x0 ./Core/Src/adc.o
  .text.HAL_ADC_MspDeInit
-                0x00000000       0x60 ./Core/Src/adc.o
+                0x00000000       0x68 ./Core/Src/adc.o
  .debug_macro   0x00000000      0xacc ./Core/Src/adc.o
- .debug_macro   0x00000000      0x221 ./Core/Src/adc.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/adc.o
  .debug_macro   0x00000000       0x2e ./Core/Src/adc.o
  .debug_macro   0x00000000       0x22 ./Core/Src/adc.o
  .debug_macro   0x00000000       0x22 ./Core/Src/adc.o
@@ -225,6 +238,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/adc.o
  .debug_macro   0x00000000      0x287 ./Core/Src/adc.o
  .debug_macro   0x00000000      0x140 ./Core/Src/adc.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/adc.o
  .debug_macro   0x00000000      0x28e ./Core/Src/adc.o
  .debug_macro   0x00000000       0x83 ./Core/Src/adc.o
  .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
@@ -267,6 +281,25 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
  .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
  .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/ads1015_driver.o
  .text          0x00000000        0x0 ./Core/Src/ads1015_driver.o
  .data          0x00000000        0x0 ./Core/Src/ads1015_driver.o
  .bss           0x00000000        0x0 ./Core/Src/ads1015_driver.o
@@ -289,7 +322,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x103 ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000       0x6a ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000      0x1df ./Core/Src/ads1015_driver.o
- .debug_macro   0x00000000      0x221 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000       0x2e ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000       0x1c ./Core/Src/ads1015_driver.o
@@ -318,8 +351,29 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000      0x287 ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000      0x140 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000      0x28e ./Core/Src/ads1015_driver.o
  .debug_macro   0x00000000       0x83 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x61 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x24 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x43 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x34 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000      0x364 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x16 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x4a ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x34 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x58 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x8e ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x1c ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000      0x17e ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x3c ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x20 ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/ads1015_driver.o
+ .group         0x00000000        0xc ./Core/Src/analog_loop_driver.o
  .group         0x00000000        0xc ./Core/Src/analog_loop_driver.o
  .group         0x00000000        0xc ./Core/Src/analog_loop_driver.o
  .group         0x00000000        0xc ./Core/Src/analog_loop_driver.o
@@ -385,9 +439,9 @@ Discarded input sections
                 0x00000000       0x40 ./Core/Src/analog_loop_driver.o
  .debug_rnglists
                 0x00000000       0x2c ./Core/Src/analog_loop_driver.o
- .debug_macro   0x00000000      0x1bb ./Core/Src/analog_loop_driver.o
+ .debug_macro   0x00000000      0x1d0 ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000      0xacc ./Core/Src/analog_loop_driver.o
- .debug_macro   0x00000000      0x221 ./Core/Src/analog_loop_driver.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000       0x2e ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/analog_loop_driver.o
@@ -422,11 +476,12 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000      0x287 ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000      0x140 ./Core/Src/analog_loop_driver.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000      0x28e ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000       0x83 ./Core/Src/analog_loop_driver.o
  .debug_macro   0x00000000       0x34 ./Core/Src/analog_loop_driver.o
- .debug_line    0x00000000      0x7e3 ./Core/Src/analog_loop_driver.o
- .debug_str     0x00000000    0x831df ./Core/Src/analog_loop_driver.o
+ .debug_line    0x00000000      0x814 ./Core/Src/analog_loop_driver.o
+ .debug_str     0x00000000    0x89f28 ./Core/Src/analog_loop_driver.o
  .comment       0x00000000       0x44 ./Core/Src/analog_loop_driver.o
  .debug_frame   0x00000000       0xbc ./Core/Src/analog_loop_driver.o
  .ARM.attributes
@@ -470,6 +525,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/digital_outputs_driver.o
  .group         0x00000000        0xc ./Core/Src/digital_outputs_driver.o
  .group         0x00000000        0xc ./Core/Src/digital_outputs_driver.o
+ .group         0x00000000        0xc ./Core/Src/digital_outputs_driver.o
  .text          0x00000000        0x0 ./Core/Src/digital_outputs_driver.o
  .data          0x00000000        0x0 ./Core/Src/digital_outputs_driver.o
  .bss           0x00000000        0x0 ./Core/Src/digital_outputs_driver.o
@@ -482,7 +538,7 @@ Discarded input sections
  .text.digital_outputs_reset_all
                 0x00000000       0x2e ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000      0xacc ./Core/Src/digital_outputs_driver.o
- .debug_macro   0x00000000      0x221 ./Core/Src/digital_outputs_driver.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000       0x2e ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/digital_outputs_driver.o
@@ -517,9 +573,94 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000      0x287 ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000      0x140 ./Core/Src/digital_outputs_driver.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000      0x28e ./Core/Src/digital_outputs_driver.o
  .debug_macro   0x00000000       0x83 ./Core/Src/digital_outputs_driver.o
- .debug_macro   0x00000000      0x196 ./Core/Src/digital_outputs_driver.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/digital_outputs_driver.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/dma.o
+ .text          0x00000000        0x0 ./Core/Src/dma.o
+ .data          0x00000000        0x0 ./Core/Src/dma.o
+ .bss           0x00000000        0x0 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0xacc ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x2e ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x8e ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x51 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x103 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x6a ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1df ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x1c ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0xbd ./Core/Src/dma.o
+ .debug_macro   0x00000000      0xd23 ./Core/Src/dma.o
+ .debug_macro   0x00000000     0xe09e ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x6d ./Core/Src/dma.o
+ .debug_macro   0x00000000     0x34a2 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x190 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x5c ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x5bc ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x289 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1cb ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x114 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1b2 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x27 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x136 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1bc ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x34 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x3c ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x57 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x46a ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1b5 ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x87 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x240 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x287 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x140 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x28e ./Core/Src/dma.o
+ .debug_macro   0x00000000       0x83 ./Core/Src/dma.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/dma.o
+ .group         0x00000000        0xc ./Core/Src/flash_manager.o
  .group         0x00000000        0xc ./Core/Src/flash_manager.o
  .group         0x00000000        0xc ./Core/Src/flash_manager.o
  .group         0x00000000        0xc ./Core/Src/flash_manager.o
@@ -579,20 +720,9 @@ Discarded input sections
  .text          0x00000000        0x0 ./Core/Src/flash_manager.o
  .data          0x00000000        0x0 ./Core/Src/flash_manager.o
  .bss           0x00000000        0x0 ./Core/Src/flash_manager.o
- .text.Flash_Save_Page
-                0x00000000       0xb4 ./Core/Src/flash_manager.o
- .text.Flash_Load_Page
-                0x00000000       0x40 ./Core/Src/flash_manager.o
- .debug_info    0x00000000      0x31b ./Core/Src/flash_manager.o
- .debug_abbrev  0x00000000      0x195 ./Core/Src/flash_manager.o
- .debug_aranges
-                0x00000000       0x28 ./Core/Src/flash_manager.o
- .debug_rnglists
-                0x00000000       0x1a ./Core/Src/flash_manager.o
- .debug_macro   0x00000000      0x288 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000      0xacc ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x10 ./Core/Src/flash_manager.o
- .debug_macro   0x00000000      0x221 ./Core/Src/flash_manager.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x2e ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x22 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x22 ./Core/Src/flash_manager.o
@@ -627,6 +757,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000      0x287 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000      0x140 ./Core/Src/flash_manager.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/flash_manager.o
  .debug_macro   0x00000000      0x28e ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x83 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x61 ./Core/Src/flash_manager.o
@@ -646,12 +777,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x3c ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x20 ./Core/Src/flash_manager.o
  .debug_macro   0x00000000       0x10 ./Core/Src/flash_manager.o
- .debug_line    0x00000000      0x917 ./Core/Src/flash_manager.o
- .debug_str     0x00000000    0x85ffa ./Core/Src/flash_manager.o
- .comment       0x00000000       0x44 ./Core/Src/flash_manager.o
- .debug_frame   0x00000000       0x5c ./Core/Src/flash_manager.o
- .ARM.attributes
-                0x00000000       0x2d ./Core/Src/flash_manager.o
+ .group         0x00000000        0xc ./Core/Src/gpio.o
  .group         0x00000000        0xc ./Core/Src/gpio.o
  .group         0x00000000        0xc ./Core/Src/gpio.o
  .group         0x00000000        0xc ./Core/Src/gpio.o
@@ -696,7 +822,7 @@ Discarded input sections
  .data          0x00000000        0x0 ./Core/Src/gpio.o
  .bss           0x00000000        0x0 ./Core/Src/gpio.o
  .debug_macro   0x00000000      0xacc ./Core/Src/gpio.o
- .debug_macro   0x00000000      0x221 ./Core/Src/gpio.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/gpio.o
  .debug_macro   0x00000000       0x2e ./Core/Src/gpio.o
  .debug_macro   0x00000000       0x22 ./Core/Src/gpio.o
  .debug_macro   0x00000000       0x22 ./Core/Src/gpio.o
@@ -731,9 +857,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/gpio.o
  .debug_macro   0x00000000      0x287 ./Core/Src/gpio.o
  .debug_macro   0x00000000      0x140 ./Core/Src/gpio.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/gpio.o
  .debug_macro   0x00000000      0x28e ./Core/Src/gpio.o
  .debug_macro   0x00000000       0x83 ./Core/Src/gpio.o
- .debug_macro   0x00000000      0x196 ./Core/Src/gpio.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/gpio.o
+ .group         0x00000000        0xc ./Core/Src/i2c.o
  .group         0x00000000        0xc ./Core/Src/i2c.o
  .group         0x00000000        0xc ./Core/Src/i2c.o
  .group         0x00000000        0xc ./Core/Src/i2c.o
@@ -779,7 +907,7 @@ Discarded input sections
  .text.HAL_I2C_MspDeInit
                 0x00000000       0x74 ./Core/Src/i2c.o
  .debug_macro   0x00000000      0xacc ./Core/Src/i2c.o
- .debug_macro   0x00000000      0x221 ./Core/Src/i2c.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/i2c.o
  .debug_macro   0x00000000       0x2e ./Core/Src/i2c.o
  .debug_macro   0x00000000       0x22 ./Core/Src/i2c.o
  .debug_macro   0x00000000       0x22 ./Core/Src/i2c.o
@@ -814,9 +942,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/i2c.o
  .debug_macro   0x00000000      0x287 ./Core/Src/i2c.o
  .debug_macro   0x00000000      0x140 ./Core/Src/i2c.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/i2c.o
  .debug_macro   0x00000000      0x28e ./Core/Src/i2c.o
  .debug_macro   0x00000000       0x83 ./Core/Src/i2c.o
- .debug_macro   0x00000000      0x196 ./Core/Src/i2c.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/i2c.o
+ .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
@@ -907,7 +1039,7 @@ Discarded input sections
  .text.intToStr
                 0x00000000       0xd8 ./Core/Src/main.o
  .debug_macro   0x00000000      0xacc ./Core/Src/main.o
- .debug_macro   0x00000000      0x221 ./Core/Src/main.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/main.o
  .debug_macro   0x00000000       0x2e ./Core/Src/main.o
  .debug_macro   0x00000000       0x22 ./Core/Src/main.o
  .debug_macro   0x00000000       0x22 ./Core/Src/main.o
@@ -942,9 +1074,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/main.o
  .debug_macro   0x00000000      0x287 ./Core/Src/main.o
  .debug_macro   0x00000000      0x140 ./Core/Src/main.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/main.o
  .debug_macro   0x00000000      0x28e ./Core/Src/main.o
  .debug_macro   0x00000000       0x83 ./Core/Src/main.o
- .debug_macro   0x00000000      0x196 ./Core/Src/main.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/main.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/main.o
  .debug_macro   0x00000000       0x61 ./Core/Src/main.o
  .debug_macro   0x00000000       0x24 ./Core/Src/main.o
  .debug_macro   0x00000000       0x43 ./Core/Src/main.o
@@ -958,13 +1092,17 @@ Discarded input sections
  .debug_macro   0x00000000       0x8e ./Core/Src/main.o
  .debug_macro   0x00000000       0x1c ./Core/Src/main.o
  .debug_macro   0x00000000      0x17e ./Core/Src/main.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/main.o
+ .debug_macro   0x00000000       0x3c ./Core/Src/main.o
+ .debug_macro   0x00000000       0x20 ./Core/Src/main.o
+ .debug_macro   0x00000000       0x10 ./Core/Src/main.o
+ .debug_macro   0x00000000      0x16e ./Core/Src/main.o
  .debug_macro   0x00000000      0x19b ./Core/Src/main.o
  .debug_macro   0x00000000       0x16 ./Core/Src/main.o
- .debug_macro   0x00000000       0x3c ./Core/Src/main.o
  .debug_macro   0x00000000       0x16 ./Core/Src/main.o
  .debug_macro   0x00000000       0x29 ./Core/Src/main.o
- .debug_macro   0x00000000      0x1b8 ./Core/Src/main.o
- .debug_macro   0x00000000       0x20 ./Core/Src/main.o
+ .debug_macro   0x00000000      0x23f ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/rs485_driver.o
  .group         0x00000000        0xc ./Core/Src/rs485_driver.o
  .group         0x00000000        0xc ./Core/Src/rs485_driver.o
  .group         0x00000000        0xc ./Core/Src/rs485_driver.o
@@ -1019,7 +1157,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x103 ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000       0x6a ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000      0x1df ./Core/Src/rs485_driver.o
- .debug_macro   0x00000000      0x221 ./Core/Src/rs485_driver.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000       0x2e ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000       0x22 ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000       0x1c ./Core/Src/rs485_driver.o
@@ -1048,6 +1186,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000      0x287 ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000      0x140 ./Core/Src/rs485_driver.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000      0x28e ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000       0x83 ./Core/Src/rs485_driver.o
  .debug_macro   0x00000000      0x229 ./Core/Src/rs485_driver.o
@@ -1091,11 +1230,12 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32f1xx_hal_msp.o
  .text          0x00000000        0x0 ./Core/Src/stm32f1xx_hal_msp.o
  .data          0x00000000        0x0 ./Core/Src/stm32f1xx_hal_msp.o
  .bss           0x00000000        0x0 ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000      0xacc ./Core/Src/stm32f1xx_hal_msp.o
- .debug_macro   0x00000000      0x221 ./Core/Src/stm32f1xx_hal_msp.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32f1xx_hal_msp.o
@@ -1130,9 +1270,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000      0x287 ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000      0x140 ./Core/Src/stm32f1xx_hal_msp.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000      0x28e ./Core/Src/stm32f1xx_hal_msp.o
  .debug_macro   0x00000000       0x83 ./Core/Src/stm32f1xx_hal_msp.o
- .debug_macro   0x00000000      0x196 ./Core/Src/stm32f1xx_hal_msp.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/stm32f1xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32f1xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32f1xx_it.o
@@ -1176,7 +1318,7 @@ Discarded input sections
  .data          0x00000000        0x0 ./Core/Src/stm32f1xx_it.o
  .bss           0x00000000        0x0 ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000      0xacc ./Core/Src/stm32f1xx_it.o
- .debug_macro   0x00000000      0x221 ./Core/Src/stm32f1xx_it.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32f1xx_it.o
@@ -1211,9 +1353,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000      0x287 ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000      0x140 ./Core/Src/stm32f1xx_it.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000      0x28e ./Core/Src/stm32f1xx_it.o
  .debug_macro   0x00000000       0x83 ./Core/Src/stm32f1xx_it.o
- .debug_macro   0x00000000      0x196 ./Core/Src/stm32f1xx_it.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/stm32f1xx_it.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
@@ -1452,6 +1595,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/system_stm32f1xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32f1xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32f1xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32f1xx.o
  .text          0x00000000        0x0 ./Core/Src/system_stm32f1xx.o
  .data          0x00000000        0x0 ./Core/Src/system_stm32f1xx.o
  .bss           0x00000000        0x0 ./Core/Src/system_stm32f1xx.o
@@ -1472,7 +1616,7 @@ Discarded input sections
  .debug_macro   0x00000000      0xd23 ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000     0xe09e ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000       0x6d ./Core/Src/system_stm32f1xx.o
- .debug_macro   0x00000000      0x221 ./Core/Src/system_stm32f1xx.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000     0x34a2 ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000      0x190 ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000       0x5c ./Core/Src/system_stm32f1xx.o
@@ -1493,8 +1637,95 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000      0x287 ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000      0x140 ./Core/Src/system_stm32f1xx.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000      0x28e ./Core/Src/system_stm32f1xx.o
  .debug_macro   0x00000000       0x83 ./Core/Src/system_stm32f1xx.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/tim.o
+ .text          0x00000000        0x0 ./Core/Src/tim.o
+ .data          0x00000000        0x0 ./Core/Src/tim.o
+ .bss           0x00000000        0x0 ./Core/Src/tim.o
+ .text.HAL_TIM_Base_MspDeInit
+                0x00000000       0x30 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0xacc ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x2e ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x8e ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x51 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x103 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x6a ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1df ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x1c ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x22 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0xbd ./Core/Src/tim.o
+ .debug_macro   0x00000000      0xd23 ./Core/Src/tim.o
+ .debug_macro   0x00000000     0xe09e ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x6d ./Core/Src/tim.o
+ .debug_macro   0x00000000     0x34a2 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x190 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x5c ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x5bc ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x289 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1cb ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x114 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1b2 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x27 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x136 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1bc ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x34 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x3c ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x57 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x46a ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1b5 ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x87 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x240 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x287 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x140 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x28e ./Core/Src/tim.o
+ .debug_macro   0x00000000       0x83 ./Core/Src/tim.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/tim.o
+ .group         0x00000000        0xc ./Core/Src/usart.o
  .group         0x00000000        0xc ./Core/Src/usart.o
  .group         0x00000000        0xc ./Core/Src/usart.o
  .group         0x00000000        0xc ./Core/Src/usart.o
@@ -1540,7 +1771,7 @@ Discarded input sections
  .text.HAL_UART_MspDeInit
                 0x00000000       0x44 ./Core/Src/usart.o
  .debug_macro   0x00000000      0xacc ./Core/Src/usart.o
- .debug_macro   0x00000000      0x221 ./Core/Src/usart.o
+ .debug_macro   0x00000000      0x22d ./Core/Src/usart.o
  .debug_macro   0x00000000       0x2e ./Core/Src/usart.o
  .debug_macro   0x00000000       0x22 ./Core/Src/usart.o
  .debug_macro   0x00000000       0x22 ./Core/Src/usart.o
@@ -1575,9 +1806,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Core/Src/usart.o
  .debug_macro   0x00000000      0x287 ./Core/Src/usart.o
  .debug_macro   0x00000000      0x140 ./Core/Src/usart.o
+ .debug_macro   0x00000000      0x8ed ./Core/Src/usart.o
  .debug_macro   0x00000000      0x28e ./Core/Src/usart.o
  .debug_macro   0x00000000       0x83 ./Core/Src/usart.o
- .debug_macro   0x00000000      0x196 ./Core/Src/usart.o
+ .debug_macro   0x00000000      0x1c7 ./Core/Src/usart.o
  .text          0x00000000       0x14 ./Core/Startup/startup_stm32f103c8tx.o
  .data          0x00000000        0x0 ./Core/Startup/startup_stm32f103c8tx.o
  .bss           0x00000000        0x0 ./Core/Startup/startup_stm32f103c8tx.o
@@ -1619,6 +1851,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
@@ -1663,7 +1896,7 @@ Discarded input sections
  .text.HAL_DBGMCU_DisableDBGStandbyMode
                 0x00000000       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
@@ -1698,6 +1931,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
@@ -1738,6 +1972,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
@@ -1759,8 +1994,6 @@ Discarded input sections
                 0x00000000      0x16c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_Stop_IT
                 0x00000000       0x68 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.HAL_ADC_Start_DMA
-                0x00000000      0x1bc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_Stop_DMA
                 0x00000000       0x98 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_GetValue
@@ -1769,28 +2002,16 @@ Discarded input sections
                 0x00000000      0x17e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_ConvCpltCallback
                 0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.HAL_ADC_ConvHalfCpltCallback
-                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_LevelOutOfWindowCallback
                 0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.HAL_ADC_ErrorCallback
-                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_AnalogWDGConfig
                 0x00000000       0xac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_GetState
                 0x00000000       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .text.HAL_ADC_GetError
                 0x00000000       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.ADC_Enable
-                0x00000000       0xb4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.ADC_DMAConvCplt
-                0x00000000       0x7c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.ADC_DMAHalfConvCplt
-                0x00000000       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .text.ADC_DMAError
-                0x00000000       0x34 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
@@ -1825,6 +2046,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
@@ -1865,11 +2087,10 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .text.HAL_ADCEx_Calibration_Start
-                0x00000000      0x15c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .text.HAL_ADCEx_InjectedStart
                 0x00000000      0x10c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .text.HAL_ADCEx_InjectedStop
@@ -1894,15 +2115,8 @@ Discarded input sections
                 0x00000000      0x334 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .text.HAL_ADCEx_MultiModeConfigChannel
                 0x00000000       0xa4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_info    0x00000000      0xa10 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_abbrev  0x00000000      0x249 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_aranges
-                0x00000000       0x80 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_rnglists
-                0x00000000       0x65 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_macro   0x00000000      0x1be ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
@@ -1937,14 +2151,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_line    0x00000000      0xd0e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_str     0x00000000    0x833e4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .debug_frame   0x00000000      0x1f4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
- .ARM.attributes
-                0x00000000       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
@@ -2025,7 +2235,7 @@ Discarded input sections
  .text.HAL_SYSTICK_Callback
                 0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
@@ -2060,6 +2270,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
@@ -2100,21 +2311,16 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .text.HAL_DMA_Init
-                0x00000000       0xb4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_DeInit
                 0x00000000       0xb8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_Start
                 0x00000000       0x86 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .text.HAL_DMA_Start_IT
-                0x00000000       0xc0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_PollForTransfer
                 0x00000000      0x324 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .text.HAL_DMA_IRQHandler
-                0x00000000      0x20c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_RegisterCallback
                 0x00000000       0x90 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_UnRegisterCallback
@@ -2123,10 +2329,8 @@ Discarded input sections
                 0x00000000       0x1a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .text.HAL_DMA_GetError
                 0x00000000       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .text.DMA_SetConfig
-                0x00000000       0x5a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
@@ -2161,6 +2365,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
@@ -2201,6 +2406,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
@@ -2228,9 +2434,9 @@ Discarded input sections
                 0x00000000       0x60 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_rnglists
                 0x00000000       0x46 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
- .debug_macro   0x00000000      0x1ac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .debug_macro   0x00000000      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
@@ -2265,10 +2471,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
- .debug_line    0x00000000      0xa11 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
- .debug_str     0x00000000    0x82eb2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .debug_line    0x00000000      0xa42 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
+ .debug_str     0x00000000    0x89bfb ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .debug_frame   0x00000000      0x154 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o
  .ARM.attributes
@@ -2311,12 +2518,10 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .bss.pFlash    0x00000000       0x20 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.HAL_FLASH_Program
-                0x00000000       0xe0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_Program_IT
                 0x00000000       0x80 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_IRQHandler
@@ -2325,10 +2530,6 @@ Discarded input sections
                 0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_OperationErrorCallback
                 0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.HAL_FLASH_Unlock
-                0x00000000       0x4c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.HAL_FLASH_Lock
-                0x00000000       0x20 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_OB_Unlock
                 0x00000000       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_OB_Lock
@@ -2337,21 +2538,8 @@ Discarded input sections
                 0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .text.HAL_FLASH_GetError
                 0x00000000       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.FLASH_Program_HalfWord
-                0x00000000       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.FLASH_WaitForLastOperation
-                0x00000000       0x8c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .text.FLASH_SetErrorCode
-                0x00000000       0xa0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_info    0x00000000      0x4f8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_abbrev  0x00000000      0x250 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_aranges
-                0x00000000       0x88 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_rnglists
-                0x00000000       0x66 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_macro   0x00000000      0x1ac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
@@ -2386,14 +2574,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_line    0x00000000      0xa81 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_str     0x00000000    0x8300b ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .debug_frame   0x00000000      0x1e8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
- .ARM.attributes
-                0x00000000       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
@@ -2435,8 +2619,6 @@ Discarded input sections
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .text.HAL_FLASHEx_Erase
-                0x00000000       0xd8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.HAL_FLASHEx_Erase_IT
                 0x00000000       0x74 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.HAL_FLASHEx_OBErase
@@ -2447,8 +2629,6 @@ Discarded input sections
                 0x00000000       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.HAL_FLASHEx_OBGetUserData
                 0x00000000       0x40 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .text.FLASH_MassErase
-                0x00000000       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.FLASH_OB_EnableWRP
                 0x00000000      0x144 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.FLASH_OB_DisableWRP
@@ -2465,17 +2645,8 @@ Discarded input sections
                 0x00000000       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .text.FLASH_OB_GetUser
                 0x00000000       0x20 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .text.FLASH_PageErase
-                0x00000000       0x40 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_info    0x00000000      0x777 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_abbrev  0x00000000      0x247 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_aranges
-                0x00000000       0x98 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_rnglists
-                0x00000000       0x73 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_macro   0x00000000      0x1be ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
@@ -2510,14 +2681,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_line    0x00000000      0xb8e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_str     0x00000000    0x831b9 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .debug_frame   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
- .ARM.attributes
-                0x00000000       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
@@ -2568,7 +2735,7 @@ Discarded input sections
  .text.HAL_GPIO_EXTI_Callback
                 0x00000000       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
@@ -2603,6 +2770,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
@@ -2643,6 +2811,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
@@ -2658,9 +2827,9 @@ Discarded input sections
                 0x00000000       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_rnglists
                 0x00000000       0x1f ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
- .debug_macro   0x00000000      0x1ac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .debug_macro   0x00000000      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
@@ -2695,10 +2864,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
- .debug_line    0x00000000      0x759 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
- .debug_str     0x00000000    0x82d33 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .debug_line    0x00000000      0x78a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
+ .debug_str     0x00000000    0x89a7c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .debug_frame   0x00000000       0x6c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o
  .ARM.attributes
@@ -2741,6 +2911,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
@@ -2887,7 +3058,7 @@ Discarded input sections
  .text.I2C_ConvertOtherXferOptions
                 0x00000000       0x34 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
@@ -2922,6 +3093,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
@@ -2962,6 +3134,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
@@ -3007,9 +3180,9 @@ Discarded input sections
                 0x00000000       0xa8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_rnglists
                 0x00000000       0x7a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
- .debug_macro   0x00000000      0x20c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
- .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
@@ -3044,10 +3217,11 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
- .debug_line    0x00000000      0x96b ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
- .debug_str     0x00000000    0x83267 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .debug_line    0x00000000      0x99c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
+ .debug_str     0x00000000    0x89fb0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .comment       0x00000000       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .debug_frame   0x00000000      0x230 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
  .ARM.attributes
@@ -3090,6 +3264,7 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
@@ -3110,7 +3285,7 @@ Discarded input sections
  .text.HAL_RCC_CSSCallback
                 0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
@@ -3145,6 +3320,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
@@ -3185,19 +3361,14 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetPeriphCLKConfig
                 0x00000000       0x60 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPeriphCLKFreq
-                0x00000000      0x16c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .rodata.aPLLMULFactorTable.1
-                0x00000000       0x10 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .rodata.aPredivFactorTable.0
-                0x00000000        0x2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
@@ -3232,8 +3403,476 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .data          0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .bss           0x00000000        0x0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_DeInit
+                0x00000000       0xa8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_Stop
+                0x00000000       0x4c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_Start_IT
+                0x00000000       0xa4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_Stop_IT
+                0x00000000       0x5c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_Start_DMA
+                0x00000000      0x10c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Base_Stop_DMA
+                0x00000000       0x64 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Init
+                0x00000000       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_DeInit
+                0x00000000       0xa8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Start
+                0x00000000      0x144 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop
+                0x00000000       0xc8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Start_IT
+                0x00000000      0x1e0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop_IT
+                0x00000000      0x164 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Start_DMA
+                0x00000000      0x344 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop_DMA
+                0x00000000      0x18c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Init
+                0x00000000       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_DeInit
+                0x00000000       0xa8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Start
+                0x00000000      0x144 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Stop
+                0x00000000       0xc8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Start_IT
+                0x00000000      0x1e0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Stop_IT
+                0x00000000      0x164 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Start_DMA
+                0x00000000      0x344 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_PWM_Stop_DMA
+                0x00000000      0x18c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Init
+                0x00000000       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_DeInit
+                0x00000000       0xa8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Start
+                0x00000000      0x180 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop
+                0x00000000       0xc2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Start_IT
+                0x00000000      0x218 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop_IT
+                0x00000000      0x15c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Start_DMA
+                0x00000000      0x31c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop_DMA
+                0x00000000      0x184 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Init
+                0x00000000       0xa0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_DeInit
+                0x00000000       0x88 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Start
+                0x00000000       0xac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Stop
+                0x00000000       0xc0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Start_IT
+                0x00000000       0xcc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Stop_IT
+                0x00000000       0xe0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Init
+                0x00000000      0x144 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_DeInit
+                0x00000000       0x88 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_MspInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_MspDeInit
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Start
+                0x00000000      0x11c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop
+                0x00000000      0x12e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Start_IT
+                0x00000000      0x15c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop_IT
+                0x00000000      0x16a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Start_DMA
+                0x00000000      0x2d8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop_DMA
+                0x00000000      0x192 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.HAL_TIM_IRQHandler
+                0x00000000      0x1e0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
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+ .text.HAL_TIM_IC_ConfigChannel
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+ .text.HAL_TIM_PWM_ConfigChannel
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+ .text.HAL_TIM_OnePulse_ConfigChannel
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+ .text.HAL_TIM_PeriodElapsedCallback
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+ .text.HAL_TIM_PeriodElapsedHalfCpltCallback
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+ .text.HAL_TIM_OC_DelayElapsedCallback
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+ .text.HAL_TIM_IC_CaptureCallback
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+ .text.HAL_TIM_IC_CaptureHalfCpltCallback
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+ .text.HAL_TIM_PWM_PulseFinishedCallback
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+ .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback
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+ .text.HAL_TIM_TriggerCallback
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+ .text.HAL_TIM_TriggerHalfCpltCallback
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+ .text.HAL_TIM_ErrorCallback
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+ .text.HAL_TIM_OnePulse_GetState
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+ .text.HAL_TIM_Encoder_GetState
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+ .text.HAL_TIM_GetActiveChannel
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+ .text.HAL_TIM_GetChannelState
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+ .text.HAL_TIM_DMABurstState
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+ .text.TIM_TI4_SetConfig
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+ .text.TIM_CCxChannelCmd
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+ .text.HAL_TIMEx_ConfigBreakDeadTime
+                0x00000000       0xa2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_RemapConfig
+                0x00000000       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_CommutCallback
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_CommutHalfCpltCallback
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_BreakCallback
+                0x00000000       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_GetState
+                0x00000000       0x1a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_GetChannelNState
+                0x00000000       0x50 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationCplt
+                0x00000000       0x24 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationHalfCplt
+                0x00000000       0x24 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.TIM_DMADelayPulseNCplt
+                0x00000000       0x86 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.TIM_DMAErrorCCxN
+                0x00000000       0x6e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .text.TIM_CCxNChannelCmd
+                0x00000000       0x48 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x8e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x51 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x103 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x6a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1df ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0xbd ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xd23 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000     0xe09e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x6d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000     0x34a2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x190 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x5c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x5bc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x289 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1cb ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x114 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1b2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x27 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x136 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1bc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x34 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x3c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x57 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x46a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1b5 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x87 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
@@ -3372,7 +4011,7 @@ Discarded input sections
  .text.UART_DMARxOnlyAbortCallback
                 0x00000000       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
- .debug_macro   0x00000000      0x221 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+ .debug_macro   0x00000000      0x22d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
@@ -3407,6 +4046,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000      0x287 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+ .debug_macro   0x00000000      0x8ed ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000      0x28e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .debug_macro   0x00000000       0x83 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-exit.o)
@@ -3562,10 +4202,6 @@ Discarded input sections
  .text          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
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- .text.memcpy   0x00000000       0x1c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
- .debug_frame   0x00000000       0x28 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
- .ARM.attributes
-                0x00000000       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
  .ARM.extab     0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
@@ -3627,8 +4263,12 @@ Discarded input sections
  .text          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
+ .text          0x00000000      0x254 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
+ .debug_frame   0x00000000       0x30 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
+ .ARM.attributes
+                0x00000000       0x1d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
  .text          0x00000000      0x168 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_mulsf3.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_mulsf3.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_mulsf3.o)
@@ -3637,8 +4277,14 @@ Discarded input sections
                 0x00000000       0x1d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_mulsf3.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubdf3.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubdf3.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldivdf3.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldivdf3.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_cmpdf2.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_cmpdf2.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_fixdfsi.o)
  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_fixdfsi.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_truncdfsf2.o)
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  .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubsf3.o)
  .data          0x00000000        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldivsf3.o)
@@ -3677,6 +4323,7 @@ LOAD ./Core/Src/adc.o
 LOAD ./Core/Src/ads1015_driver.o
 LOAD ./Core/Src/analog_loop_driver.o
 LOAD ./Core/Src/digital_outputs_driver.o
+LOAD ./Core/Src/dma.o
 LOAD ./Core/Src/flash_manager.o
 LOAD ./Core/Src/gpio.o
 LOAD ./Core/Src/i2c.o
@@ -3687,6 +4334,7 @@ LOAD ./Core/Src/stm32f1xx_it.o
 LOAD ./Core/Src/syscalls.o
 LOAD ./Core/Src/sysmem.o
 LOAD ./Core/Src/system_stm32f1xx.o
+LOAD ./Core/Src/tim.o
 LOAD ./Core/Src/usart.o
 LOAD ./Core/Startup/startup_stm32f103c8tx.o
 LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
@@ -3703,6 +4351,8 @@ LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
 LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o
 LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
 LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
 LOAD ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
 START GROUP
 LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a
@@ -3735,553 +4385,690 @@ LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.exte
                 0x08000000                g_pfnVectors
                 0x0800010c                        . = ALIGN (0x4)
 
-.text           0x0800010c     0x5ddc
-                0x0800010c                        . = ALIGN (0x4)
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  *(.text*)
  .text.AD5934_SetRegisterValue
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  .text.AD5934_Init
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  .text.AD5934_GetImpedance
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  .text.HAL_ADC_MspInit
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+                0x08001bb0      0x124 ./Core/Src/adc.o
+                0x08001bb0                HAL_ADC_MspInit
  .text.writeRegister
-                0x08001ae8       0x42 ./Core/Src/ads1015_driver.o
+                0x08001cd4       0x42 ./Core/Src/ads1015_driver.o
  .text.readRegister
-                0x08001b2a       0x54 ./Core/Src/ads1015_driver.o
- .text.ADS1015  0x08001b7e       0x3c ./Core/Src/ads1015_driver.o
-                0x08001b7e                ADS1015
+                0x08001d16       0x54 ./Core/Src/ads1015_driver.o
+ .text.ADS1015  0x08001d6a       0x3c ./Core/Src/ads1015_driver.o
+                0x08001d6a                ADS1015
  .text.ADSsetGain
-                0x08001bba       0x1c ./Core/Src/ads1015_driver.o
-                0x08001bba                ADSsetGain
+                0x08001da6       0x1c ./Core/Src/ads1015_driver.o
+                0x08001da6                ADSsetGain
  .text.ADSreadADC_Differential_0_1
-                0x08001bd6       0x7e ./Core/Src/ads1015_driver.o
-                0x08001bd6                ADSreadADC_Differential_0_1
+                0x08001dc2       0x7e ./Core/Src/ads1015_driver.o
+                0x08001dc2                ADSreadADC_Differential_0_1
  .text.ADSCalculate_ph_Volts
-                0x08001c54       0x3c ./Core/Src/ads1015_driver.o
-                0x08001c54                ADSCalculate_ph_Volts
+                0x08001e40       0xac ./Core/Src/ads1015_driver.o
+                0x08001e40                ADSCalculate_ph_Volts
  .text.ADSCalculate_ph_Compensated
-                0x08001c90      0x114 ./Core/Src/ads1015_driver.o
-                0x08001c90                ADSCalculate_ph_Compensated
+                0x08001eec      0x10c ./Core/Src/ads1015_driver.o
+                0x08001eec                ADSCalculate_ph_Compensated
  .text.digital_outputs_init
-                0x08001da4       0x84 ./Core/Src/digital_outputs_driver.o
-                0x08001da4                digital_outputs_init
+                0x08001ff8       0x84 ./Core/Src/digital_outputs_driver.o
+                0x08001ff8                digital_outputs_init
+ .text.MX_DMA_Init
+                0x0800207c       0x3c ./Core/Src/dma.o
+                0x0800207c                MX_DMA_Init
+ .text.Flash_Save_Page
+                0x080020b8       0xb4 ./Core/Src/flash_manager.o
+                0x080020b8                Flash_Save_Page
+ .text.Flash_Load_Page
+                0x0800216c       0x40 ./Core/Src/flash_manager.o
+                0x0800216c                Flash_Load_Page
  .text.MX_GPIO_Init
-                0x08001e28      0x16c ./Core/Src/gpio.o
-                0x08001e28                MX_GPIO_Init
+                0x080021ac      0x16c ./Core/Src/gpio.o
+                0x080021ac                MX_GPIO_Init
  .text.HAL_GPIO_EXTI_Callback
-                0x08001f94       0xa8 ./Core/Src/gpio.o
-                0x08001f94                HAL_GPIO_EXTI_Callback
+                0x08002318       0xb4 ./Core/Src/gpio.o
+                0x08002318                HAL_GPIO_EXTI_Callback
  .text.MX_I2C1_Init
-                0x0800203c       0x5c ./Core/Src/i2c.o
-                0x0800203c                MX_I2C1_Init
+                0x080023cc       0x5c ./Core/Src/i2c.o
+                0x080023cc                MX_I2C1_Init
  .text.MX_I2C2_Init
-                0x08002098       0x5c ./Core/Src/i2c.o
-                0x08002098                MX_I2C2_Init
+                0x08002428       0x5c ./Core/Src/i2c.o
+                0x08002428                MX_I2C2_Init
  .text.HAL_I2C_MspInit
-                0x080020f4       0xd8 ./Core/Src/i2c.o
-                0x080020f4                HAL_I2C_MspInit
- .text.main     0x080021cc      0x258 ./Core/Src/main.o
-                0x080021cc                main
+                0x08002484       0xd8 ./Core/Src/i2c.o
+                0x08002484                HAL_I2C_MspInit
+ *fill*         0x0800255c        0x4 
+ .text.main     0x08002560      0x4b4 ./Core/Src/main.o
+                0x08002560                main
  .text.SystemClock_Config
-                0x08002424       0xb6 ./Core/Src/main.o
-                0x08002424                SystemClock_Config
- *fill*         0x080024da        0x2 
+                0x08002a14       0xb6 ./Core/Src/main.o
+                0x08002a14                SystemClock_Config
+ *fill*         0x08002aca        0x2 
  .text.FloatToString
-                0x080024dc      0x194 ./Core/Src/main.o
-                0x080024dc                FloatToString
+                0x08002acc      0x228 ./Core/Src/main.o
+                0x08002acc                FloatToString
+ .text.HAL_ADC_ConvCpltCallback
+                0x08002cf4       0x1c ./Core/Src/main.o
+                0x08002cf4                HAL_ADC_ConvCpltCallback
  .text.Error_Handler
-                0x08002670        0xc ./Core/Src/main.o
-                0x08002670                Error_Handler
+                0x08002d10        0xc ./Core/Src/main.o
+                0x08002d10                Error_Handler
  .text.LL_GPIO_ReadInputPort
-                0x0800267c       0x16 ./Core/Src/rs485_driver.o
- *fill*         0x08002692        0x2 
+                0x08002d1c       0x16 ./Core/Src/rs485_driver.o
+ *fill*         0x08002d32        0x2 
  .text.rs485_init
-                0x08002694       0x20 ./Core/Src/rs485_driver.o
-                0x08002694                rs485_init
+                0x08002d34       0x20 ./Core/Src/rs485_driver.o
+                0x08002d34                rs485_init
  .text.rs485_get_address
-                0x080026b4       0x38 ./Core/Src/rs485_driver.o
-                0x080026b4                rs485_get_address
+                0x08002d54       0x38 ./Core/Src/rs485_driver.o
+                0x08002d54                rs485_get_address
  .text.rs485_send_broadcast
-                0x080026ec       0x48 ./Core/Src/rs485_driver.o
-                0x080026ec                rs485_send_broadcast
+                0x08002d8c       0x48 ./Core/Src/rs485_driver.o
+                0x08002d8c                rs485_send_broadcast
  .text.rs485_enable_tx
-                0x08002734       0x18 ./Core/Src/rs485_driver.o
-                0x08002734                rs485_enable_tx
+                0x08002dd4       0x18 ./Core/Src/rs485_driver.o
+                0x08002dd4                rs485_enable_tx
  .text.rs485_disable_tx
-                0x0800274c       0x18 ./Core/Src/rs485_driver.o
-                0x0800274c                rs485_disable_tx
+                0x08002dec       0x18 ./Core/Src/rs485_driver.o
+                0x08002dec                rs485_disable_tx
  .text.rs485_configure_gpio_address
-                0x08002764       0x8c ./Core/Src/rs485_driver.o
+                0x08002e04       0x8c ./Core/Src/rs485_driver.o
  .text.rs485_configure_usart1
-                0x080027f0       0x74 ./Core/Src/rs485_driver.o
+                0x08002e90       0x74 ./Core/Src/rs485_driver.o
  .text.HAL_MspInit
-                0x08002864       0x64 ./Core/Src/stm32f1xx_hal_msp.o
-                0x08002864                HAL_MspInit
+                0x08002f04       0x64 ./Core/Src/stm32f1xx_hal_msp.o
+                0x08002f04                HAL_MspInit
  .text.NMI_Handler
-                0x080028c8        0x8 ./Core/Src/stm32f1xx_it.o
-                0x080028c8                NMI_Handler
+                0x08002f68        0x8 ./Core/Src/stm32f1xx_it.o
+                0x08002f68                NMI_Handler
  .text.HardFault_Handler
-                0x080028d0        0x8 ./Core/Src/stm32f1xx_it.o
-                0x080028d0                HardFault_Handler
+                0x08002f70        0x8 ./Core/Src/stm32f1xx_it.o
+                0x08002f70                HardFault_Handler
  .text.MemManage_Handler
-                0x080028d8        0x8 ./Core/Src/stm32f1xx_it.o
-                0x080028d8                MemManage_Handler
+                0x08002f78        0x8 ./Core/Src/stm32f1xx_it.o
+                0x08002f78                MemManage_Handler
  .text.BusFault_Handler
-                0x080028e0        0x8 ./Core/Src/stm32f1xx_it.o
-                0x080028e0                BusFault_Handler
+                0x08002f80        0x8 ./Core/Src/stm32f1xx_it.o
+                0x08002f80                BusFault_Handler
  .text.UsageFault_Handler
-                0x080028e8        0x8 ./Core/Src/stm32f1xx_it.o
-                0x080028e8                UsageFault_Handler
+                0x08002f88        0x8 ./Core/Src/stm32f1xx_it.o
+                0x08002f88                UsageFault_Handler
  .text.SVC_Handler
-                0x080028f0        0xc ./Core/Src/stm32f1xx_it.o
-                0x080028f0                SVC_Handler
+                0x08002f90        0xc ./Core/Src/stm32f1xx_it.o
+                0x08002f90                SVC_Handler
  .text.DebugMon_Handler
-                0x080028fc        0xc ./Core/Src/stm32f1xx_it.o
-                0x080028fc                DebugMon_Handler
+                0x08002f9c        0xc ./Core/Src/stm32f1xx_it.o
+                0x08002f9c                DebugMon_Handler
  .text.PendSV_Handler
-                0x08002908        0xc ./Core/Src/stm32f1xx_it.o
-                0x08002908                PendSV_Handler
+                0x08002fa8        0xc ./Core/Src/stm32f1xx_it.o
+                0x08002fa8                PendSV_Handler
  .text.SysTick_Handler
-                0x08002914        0xc ./Core/Src/stm32f1xx_it.o
-                0x08002914                SysTick_Handler
+                0x08002fb4        0xc ./Core/Src/stm32f1xx_it.o
+                0x08002fb4                SysTick_Handler
  .text.EXTI3_IRQHandler
-                0x08002920        0xe ./Core/Src/stm32f1xx_it.o
-                0x08002920                EXTI3_IRQHandler
- *fill*         0x0800292e        0x2 
+                0x08002fc0        0xe ./Core/Src/stm32f1xx_it.o
+                0x08002fc0                EXTI3_IRQHandler
+ *fill*         0x08002fce        0x2 
+ .text.DMA1_Channel1_IRQHandler
+                0x08002fd0       0x14 ./Core/Src/stm32f1xx_it.o
+                0x08002fd0                DMA1_Channel1_IRQHandler
  .text.USART1_IRQHandler
-                0x08002930       0x14 ./Core/Src/stm32f1xx_it.o
-                0x08002930                USART1_IRQHandler
+                0x08002fe4       0x14 ./Core/Src/stm32f1xx_it.o
+                0x08002fe4                USART1_IRQHandler
  .text.SystemInit
-                0x08002944        0xc ./Core/Src/system_stm32f1xx.o
-                0x08002944                SystemInit
+                0x08002ff8        0xc ./Core/Src/system_stm32f1xx.o
+                0x08002ff8                SystemInit
+ .text.MX_TIM3_Init
+                0x08003004       0x9c ./Core/Src/tim.o
+                0x08003004                MX_TIM3_Init
+ .text.HAL_TIM_Base_MspInit
+                0x080030a0       0x3c ./Core/Src/tim.o
+                0x080030a0                HAL_TIM_Base_MspInit
  .text.MX_USART1_UART_Init
-                0x08002950       0x54 ./Core/Src/usart.o
-                0x08002950                MX_USART1_UART_Init
+                0x080030dc       0x54 ./Core/Src/usart.o
+                0x080030dc                MX_USART1_UART_Init
  .text.HAL_UART_MspInit
-                0x080029a4       0xa8 ./Core/Src/usart.o
-                0x080029a4                HAL_UART_MspInit
+                0x08003130       0xa8 ./Core/Src/usart.o
+                0x08003130                HAL_UART_MspInit
  .text.Reset_Handler
-                0x08002a4c       0x48 ./Core/Startup/startup_stm32f103c8tx.o
-                0x08002a4c                Reset_Handler
+                0x080031d8       0x48 ./Core/Startup/startup_stm32f103c8tx.o
+                0x080031d8                Reset_Handler
  .text.Default_Handler
-                0x08002a94        0x2 ./Core/Startup/startup_stm32f103c8tx.o
-                0x08002a94                RTC_Alarm_IRQHandler
-                0x08002a94                EXTI2_IRQHandler
-                0x08002a94                TIM1_CC_IRQHandler
-                0x08002a94                PVD_IRQHandler
-                0x08002a94                EXTI0_IRQHandler
-                0x08002a94                I2C2_EV_IRQHandler
-                0x08002a94                ADC1_2_IRQHandler
-                0x08002a94                SPI1_IRQHandler
-                0x08002a94                TAMPER_IRQHandler
-                0x08002a94                DMA1_Channel4_IRQHandler
-                0x08002a94                USART3_IRQHandler
-                0x08002a94                RTC_IRQHandler
-                0x08002a94                DMA1_Channel7_IRQHandler
-                0x08002a94                CAN1_RX1_IRQHandler
-                0x08002a94                TIM4_IRQHandler
-                0x08002a94                I2C1_EV_IRQHandler
-                0x08002a94                DMA1_Channel6_IRQHandler
-                0x08002a94                TIM3_IRQHandler
-                0x08002a94                RCC_IRQHandler
-                0x08002a94                TIM1_TRG_COM_IRQHandler
-                0x08002a94                DMA1_Channel1_IRQHandler
-                0x08002a94                Default_Handler
-                0x08002a94                EXTI15_10_IRQHandler
-                0x08002a94                EXTI9_5_IRQHandler
-                0x08002a94                SPI2_IRQHandler
-                0x08002a94                DMA1_Channel5_IRQHandler
-                0x08002a94                EXTI4_IRQHandler
-                0x08002a94                USB_LP_CAN1_RX0_IRQHandler
-                0x08002a94                USB_HP_CAN1_TX_IRQHandler
-                0x08002a94                DMA1_Channel3_IRQHandler
-                0x08002a94                TIM1_UP_IRQHandler
-                0x08002a94                WWDG_IRQHandler
-                0x08002a94                TIM2_IRQHandler
-                0x08002a94                TIM1_BRK_IRQHandler
-                0x08002a94                EXTI1_IRQHandler
-                0x08002a94                USART2_IRQHandler
-                0x08002a94                I2C2_ER_IRQHandler
-                0x08002a94                DMA1_Channel2_IRQHandler
-                0x08002a94                CAN1_SCE_IRQHandler
-                0x08002a94                FLASH_IRQHandler
-                0x08002a94                I2C1_ER_IRQHandler
-                0x08002a94                USBWakeUp_IRQHandler
- *fill*         0x08002a96        0x2 
+                0x08003220        0x2 ./Core/Startup/startup_stm32f103c8tx.o
+                0x08003220                RTC_Alarm_IRQHandler
+                0x08003220                EXTI2_IRQHandler
+                0x08003220                TIM1_CC_IRQHandler
+                0x08003220                PVD_IRQHandler
+                0x08003220                EXTI0_IRQHandler
+                0x08003220                I2C2_EV_IRQHandler
+                0x08003220                ADC1_2_IRQHandler
+                0x08003220                SPI1_IRQHandler
+                0x08003220                TAMPER_IRQHandler
+                0x08003220                DMA1_Channel4_IRQHandler
+                0x08003220                USART3_IRQHandler
+                0x08003220                RTC_IRQHandler
+                0x08003220                DMA1_Channel7_IRQHandler
+                0x08003220                CAN1_RX1_IRQHandler
+                0x08003220                TIM4_IRQHandler
+                0x08003220                I2C1_EV_IRQHandler
+                0x08003220                DMA1_Channel6_IRQHandler
+                0x08003220                TIM3_IRQHandler
+                0x08003220                RCC_IRQHandler
+                0x08003220                TIM1_TRG_COM_IRQHandler
+                0x08003220                Default_Handler
+                0x08003220                EXTI15_10_IRQHandler
+                0x08003220                EXTI9_5_IRQHandler
+                0x08003220                SPI2_IRQHandler
+                0x08003220                DMA1_Channel5_IRQHandler
+                0x08003220                EXTI4_IRQHandler
+                0x08003220                USB_LP_CAN1_RX0_IRQHandler
+                0x08003220                USB_HP_CAN1_TX_IRQHandler
+                0x08003220                DMA1_Channel3_IRQHandler
+                0x08003220                TIM1_UP_IRQHandler
+                0x08003220                WWDG_IRQHandler
+                0x08003220                TIM2_IRQHandler
+                0x08003220                TIM1_BRK_IRQHandler
+                0x08003220                EXTI1_IRQHandler
+                0x08003220                USART2_IRQHandler
+                0x08003220                I2C2_ER_IRQHandler
+                0x08003220                DMA1_Channel2_IRQHandler
+                0x08003220                CAN1_SCE_IRQHandler
+                0x08003220                FLASH_IRQHandler
+                0x08003220                I2C1_ER_IRQHandler
+                0x08003220                USBWakeUp_IRQHandler
+ *fill*         0x08003222        0x2 
  .text.HAL_Init
-                0x08002a98       0x2c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x08002a98                HAL_Init
+                0x08003224       0x2c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x08003224                HAL_Init
  .text.HAL_InitTick
-                0x08002ac4       0x60 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x08002ac4                HAL_InitTick
+                0x08003250       0x60 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x08003250                HAL_InitTick
  .text.HAL_IncTick
-                0x08002b24       0x24 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x08002b24                HAL_IncTick
+                0x080032b0       0x24 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x080032b0                HAL_IncTick
  .text.HAL_GetTick
-                0x08002b48       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x08002b48                HAL_GetTick
+                0x080032d4       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x080032d4                HAL_GetTick
  .text.HAL_Delay
-                0x08002b5c       0x48 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x08002b5c                HAL_Delay
+                0x080032e8       0x48 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x080032e8                HAL_Delay
  .text.HAL_ADC_Init
-                0x08002ba4      0x1b0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
-                0x08002ba4                HAL_ADC_Init
+                0x08003330      0x1b0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x08003330                HAL_ADC_Init
+ .text.HAL_ADC_Start_DMA
+                0x080034e0      0x1bc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x080034e0                HAL_ADC_Start_DMA
+ .text.HAL_ADC_ConvHalfCpltCallback
+                0x0800369c       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x0800369c                HAL_ADC_ConvHalfCpltCallback
+ .text.HAL_ADC_ErrorCallback
+                0x080036ae       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x080036ae                HAL_ADC_ErrorCallback
  .text.HAL_ADC_ConfigChannel
-                0x08002d54      0x1f0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
-                0x08002d54                HAL_ADC_ConfigChannel
+                0x080036c0      0x1f0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x080036c0                HAL_ADC_ConfigChannel
+ .text.ADC_Enable
+                0x080038b0       0xb4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x080038b0                ADC_Enable
  .text.ADC_ConversionStop_Disable
-                0x08002f44       0x82 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
-                0x08002f44                ADC_ConversionStop_Disable
- *fill*         0x08002fc6        0x2 
+                0x08003964       0x82 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x08003964                ADC_ConversionStop_Disable
+ .text.ADC_DMAConvCplt
+                0x080039e6       0x7c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x080039e6                ADC_DMAConvCplt
+ .text.ADC_DMAHalfConvCplt
+                0x08003a62       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x08003a62                ADC_DMAHalfConvCplt
+ .text.ADC_DMAError
+                0x08003a7e       0x34 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x08003a7e                ADC_DMAError
+ *fill*         0x08003ab2        0x2 
+ .text.HAL_ADCEx_Calibration_Start
+                0x08003ab4      0x15c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+                0x08003ab4                HAL_ADCEx_Calibration_Start
  .text.__NVIC_SetPriorityGrouping
-                0x08002fc8       0x48 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003c10       0x48 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.__NVIC_GetPriorityGrouping
-                0x08003010       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003c58       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.__NVIC_EnableIRQ
-                0x0800302c       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003c74       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.__NVIC_SetPriority
-                0x08003064       0x54 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003cac       0x54 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.NVIC_EncodePriority
-                0x080030b8       0x64 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003d00       0x64 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.SysTick_Config
-                0x0800311c       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003d64       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .text.HAL_NVIC_SetPriorityGrouping
-                0x08003160       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
-                0x08003160                HAL_NVIC_SetPriorityGrouping
+                0x08003da8       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003da8                HAL_NVIC_SetPriorityGrouping
  .text.HAL_NVIC_SetPriority
-                0x08003176       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
-                0x08003176                HAL_NVIC_SetPriority
+                0x08003dbe       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003dbe                HAL_NVIC_SetPriority
  .text.HAL_NVIC_EnableIRQ
-                0x080031ae       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
-                0x080031ae                HAL_NVIC_EnableIRQ
+                0x08003df6       0x1c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003df6                HAL_NVIC_EnableIRQ
  .text.HAL_SYSTICK_Config
-                0x080031ca       0x18 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
-                0x080031ca                HAL_SYSTICK_Config
+                0x08003e12       0x18 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x08003e12                HAL_SYSTICK_Config
+ *fill*         0x08003e2a        0x2 
+ .text.HAL_DMA_Init
+                0x08003e2c       0xb4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x08003e2c                HAL_DMA_Init
+ .text.HAL_DMA_Start_IT
+                0x08003ee0       0xc0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x08003ee0                HAL_DMA_Start_IT
  .text.HAL_DMA_Abort
-                0x080031e2       0x76 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
-                0x080031e2                HAL_DMA_Abort
+                0x08003fa0       0x76 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x08003fa0                HAL_DMA_Abort
+ *fill*         0x08004016        0x2 
  .text.HAL_DMA_Abort_IT
-                0x08003258       0xf0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
-                0x08003258                HAL_DMA_Abort_IT
+                0x08004018       0xf0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x08004018                HAL_DMA_Abort_IT
+ .text.HAL_DMA_IRQHandler
+                0x08004108      0x20c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x08004108                HAL_DMA_IRQHandler
+ .text.DMA_SetConfig
+                0x08004314       0x5a ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ *fill*         0x0800436e        0x2 
+ .text.HAL_FLASH_Program
+                0x08004370       0xe0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+                0x08004370                HAL_FLASH_Program
+ .text.HAL_FLASH_Unlock
+                0x08004450       0x4c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+                0x08004450                HAL_FLASH_Unlock
+ .text.HAL_FLASH_Lock
+                0x0800449c       0x20 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+                0x0800449c                HAL_FLASH_Lock
+ .text.FLASH_Program_HalfWord
+                0x080044bc       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .text.FLASH_WaitForLastOperation
+                0x080044f4       0x8c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+                0x080044f4                FLASH_WaitForLastOperation
+ .text.FLASH_SetErrorCode
+                0x08004580       0xa0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .text.HAL_FLASHEx_Erase
+                0x08004620       0xd8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+                0x08004620                HAL_FLASHEx_Erase
+ .text.FLASH_MassErase
+                0x080046f8       0x38 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .text.FLASH_PageErase
+                0x08004730       0x40 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+                0x08004730                FLASH_PageErase
  .text.HAL_GPIO_Init
-                0x08003348      0x308 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
-                0x08003348                HAL_GPIO_Init
+                0x08004770      0x308 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+                0x08004770                HAL_GPIO_Init
  .text.HAL_GPIO_ReadPin
-                0x08003650       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
-                0x08003650                HAL_GPIO_ReadPin
+                0x08004a78       0x2e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+                0x08004a78                HAL_GPIO_ReadPin
  .text.HAL_GPIO_WritePin
-                0x0800367e       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
-                0x0800367e                HAL_GPIO_WritePin
- *fill*         0x080036ae        0x2 
+                0x08004aa6       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+                0x08004aa6                HAL_GPIO_WritePin
+ *fill*         0x08004ad6        0x2 
  .text.HAL_GPIO_EXTI_IRQHandler
-                0x080036b0       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
-                0x080036b0                HAL_GPIO_EXTI_IRQHandler
+                0x08004ad8       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+                0x08004ad8                HAL_GPIO_EXTI_IRQHandler
  .text.HAL_I2C_Init
-                0x080036e0      0x288 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
-                0x080036e0                HAL_I2C_Init
+                0x08004b08      0x288 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08004b08                HAL_I2C_Init
  .text.HAL_I2C_Master_Transmit
-                0x08003968      0x1fc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
-                0x08003968                HAL_I2C_Master_Transmit
+                0x08004d90      0x1fc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08004d90                HAL_I2C_Master_Transmit
  .text.HAL_I2C_Master_Receive
-                0x08003b64      0x4d8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
-                0x08003b64                HAL_I2C_Master_Receive
+                0x08004f8c      0x4d8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08004f8c                HAL_I2C_Master_Receive
  .text.I2C_MasterRequestWrite
-                0x0800403c      0x104 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08005464      0x104 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_MasterRequestRead
-                0x08004140      0x19c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08005568      0x19c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_WaitOnFlagUntilTimeout
-                0x080042dc       0xf4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08005704       0xf4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_WaitOnMasterAddressFlagUntilTimeout
-                0x080043d0      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x080057f8      0x140 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_WaitOnTXEFlagUntilTimeout
-                0x08004510       0x90 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08005938       0x90 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_WaitOnBTFFlagUntilTimeout
-                0x080045a0       0x90 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x080059c8       0x90 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_WaitOnRXNEFlagUntilTimeout
-                0x08004630       0xba ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x08005a58       0xba ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .text.I2C_IsAcknowledgeFailed
-                0x080046ea       0x5c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
- *fill*         0x08004746        0x2 
+                0x08005b12       0x5c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ *fill*         0x08005b6e        0x2 
  .text.HAL_RCC_OscConfig
-                0x08004748      0x504 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004748                HAL_RCC_OscConfig
+                0x08005b70      0x504 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08005b70                HAL_RCC_OscConfig
  .text.HAL_RCC_ClockConfig
-                0x08004c4c      0x1d4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004c4c                HAL_RCC_ClockConfig
+                0x08006074      0x1d4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08006074                HAL_RCC_ClockConfig
  .text.HAL_RCC_GetSysClockFreq
-                0x08004e20       0xac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004e20                HAL_RCC_GetSysClockFreq
+                0x08006248       0xac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08006248                HAL_RCC_GetSysClockFreq
  .text.HAL_RCC_GetHCLKFreq
-                0x08004ecc       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004ecc                HAL_RCC_GetHCLKFreq
+                0x080062f4       0x14 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x080062f4                HAL_RCC_GetHCLKFreq
  .text.HAL_RCC_GetPCLK1Freq
-                0x08004ee0       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004ee0                HAL_RCC_GetPCLK1Freq
+                0x08006308       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08006308                HAL_RCC_GetPCLK1Freq
  .text.HAL_RCC_GetPCLK2Freq
-                0x08004f08       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
-                0x08004f08                HAL_RCC_GetPCLK2Freq
+                0x08006330       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08006330                HAL_RCC_GetPCLK2Freq
  .text.RCC_Delay
-                0x08004f30       0x3c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08006358       0x3c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .text.HAL_RCCEx_PeriphCLKConfig
-                0x08004f6c      0x16c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
-                0x08004f6c                HAL_RCCEx_PeriphCLKConfig
+                0x08006394      0x16c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+                0x08006394                HAL_RCCEx_PeriphCLKConfig
+ .text.HAL_RCCEx_GetPeriphCLKFreq
+                0x08006500      0x16c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+                0x08006500                HAL_RCCEx_GetPeriphCLKFreq
+ .text.HAL_TIM_Base_Init
+                0x0800666c       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+                0x0800666c                HAL_TIM_Base_Init
+ *fill*         0x0800670a        0x2 
+ .text.HAL_TIM_Base_Start
+                0x0800670c       0x94 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+                0x0800670c                HAL_TIM_Base_Start
+ .text.HAL_TIM_ConfigClockSource
+                0x080067a0      0x18e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+                0x080067a0                HAL_TIM_ConfigClockSource
+ *fill*         0x0800692e        0x2 
+ .text.TIM_Base_SetConfig
+                0x08006930       0xdc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+                0x08006930                TIM_Base_SetConfig
+ .text.TIM_TI1_ConfigInputStage
+                0x08006a0c       0x5c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.TIM_TI2_ConfigInputStage
+                0x08006a68       0x5e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.TIM_ITRx_SetConfig
+                0x08006ac6       0x34 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .text.TIM_ETR_SetConfig
+                0x08006afa       0x3e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+                0x08006afa                TIM_ETR_SetConfig
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x08006b38       0xbc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+                0x08006b38                HAL_TIMEx_MasterConfigSynchronization
  .text.HAL_UART_Init
-                0x080050d8       0xa0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x080050d8                HAL_UART_Init
+                0x08006bf4       0xa0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08006bf4                HAL_UART_Init
  .text.HAL_UART_Transmit
-                0x08005178      0x116 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x08005178                HAL_UART_Transmit
- *fill*         0x0800528e        0x2 
+                0x08006c94      0x116 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08006c94                HAL_UART_Transmit
+ *fill*         0x08006daa        0x2 
  .text.HAL_UART_IRQHandler
-                0x08005290      0x524 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x08005290                HAL_UART_IRQHandler
+                0x08006dac      0x524 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08006dac                HAL_UART_IRQHandler
  .text.HAL_UART_TxCpltCallback
-                0x080057b4       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x080057b4                HAL_UART_TxCpltCallback
+                0x080072d0       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x080072d0                HAL_UART_TxCpltCallback
  .text.HAL_UART_RxCpltCallback
-                0x080057c6       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x080057c6                HAL_UART_RxCpltCallback
+                0x080072e2       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x080072e2                HAL_UART_RxCpltCallback
  .text.HAL_UART_ErrorCallback
-                0x080057d8       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x080057d8                HAL_UART_ErrorCallback
+                0x080072f4       0x12 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x080072f4                HAL_UART_ErrorCallback
  .text.HAL_UARTEx_RxEventCallback
-                0x080057ea       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
-                0x080057ea                HAL_UARTEx_RxEventCallback
+                0x08007306       0x16 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08007306                HAL_UARTEx_RxEventCallback
  .text.UART_WaitOnFlagUntilTimeout
-                0x08005800       0xb2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x0800731c       0xb2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_EndRxTransfer
-                0x080058b2       0xc4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x080073ce       0xc4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_DMAAbortOnError
-                0x08005976       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08007492       0x28 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_Transmit_IT
-                0x0800599e       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x080074ba       0x9e ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_EndTransmit_IT
-                0x08005a3c       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08007558       0x30 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_Receive_IT
-                0x08005a6c      0x17c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x08007588      0x17c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .text.UART_SetConfig
-                0x08005be8      0x11c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
- .text.memset   0x08005d04       0x10 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memset.o)
-                0x08005d04                memset
- .text.__errno  0x08005d14        0xc C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-errno.o)
-                0x08005d14                __errno
+                0x08007704      0x11c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+ .text.memset   0x08007820       0x10 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memset.o)
+                0x08007820                memset
+ .text.__errno  0x08007830        0xc C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-errno.o)
+                0x08007830                __errno
  .text.__libc_init_array
-                0x08005d20       0x48 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-init.o)
-                0x08005d20                __libc_init_array
- .text.sqrtf    0x08005d68       0x3c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-wf_sqrt.o)
-                0x08005d68                sqrtf
+                0x0800783c       0x48 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-init.o)
+                0x0800783c                __libc_init_array
+ .text.memcpy   0x08007884       0x1c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
+                0x08007884                memcpy
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+                0x080078a0                sqrtf
  .text.__ieee754_sqrtf
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-                0x08005da4                __ieee754_sqrtf
- .text.roundf   0x08005e88       0x48 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
-                0x08005e88                roundf
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+                0x080078dc                __ieee754_sqrtf
+ .text.roundf   0x080079c0       0x48 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
+                0x080079c0                roundf
  *(.glue_7)
- .glue_7        0x08005ed0        0x0 linker stubs
+ .glue_7        0x08007a08        0x0 linker stubs
  *(.glue_7t)
- .glue_7t       0x08005ed0        0x0 linker stubs
+ .glue_7t       0x08007a08        0x0 linker stubs
  *(.eh_frame)
- .eh_frame      0x08005ed0        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+ .eh_frame      0x08007a08        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
  *(.init)
- .init          0x08005ed0        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crti.o
-                0x08005ed0                _init
- .init          0x08005ed4        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtn.o
+ .init          0x08007a08        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crti.o
+                0x08007a08                _init
+ .init          0x08007a0c        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtn.o
  *(.fini)
- .fini          0x08005edc        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crti.o
-                0x08005edc                _fini
- .fini          0x08005ee0        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtn.o
-                0x08005ee8                        . = ALIGN (0x4)
-                0x08005ee8                        _etext = .
+ .fini          0x08007a14        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crti.o
+                0x08007a14                _fini
+ .fini          0x08007a18        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtn.o
+                0x08007a20                        . = ALIGN (0x4)
+                0x08007a20                        _etext = .
 
-.vfp11_veneer   0x08005ee8        0x0
- .vfp11_veneer  0x08005ee8        0x0 linker stubs
+.vfp11_veneer   0x08007a20        0x0
+ .vfp11_veneer  0x08007a20        0x0 linker stubs
 
-.v4_bx          0x08005ee8        0x0
- .v4_bx         0x08005ee8        0x0 linker stubs
+.v4_bx          0x08007a20        0x0
+ .v4_bx         0x08007a20        0x0 linker stubs
 
-.iplt           0x08005ee8        0x0
- .iplt          0x08005ee8        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+.iplt           0x08007a20        0x0
+ .iplt          0x08007a20        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
 
-.rodata         0x08005ee8       0x80
-                0x08005ee8                        . = ALIGN (0x4)
+.rodata         0x08007a20       0x88
+                0x08007a20                        . = ALIGN (0x4)
  *(.rodata)
  *(.rodata*)
- .rodata.calibrationResistance
-                0x08005ee8        0xc ./Core/Src/ad5934_driver.o
-                0x08005ee8                calibrationResistance
  .rodata.output_pins
-                0x08005ef4       0x40 ./Core/Src/digital_outputs_driver.o
+                0x08007a20       0x40 ./Core/Src/digital_outputs_driver.o
  .rodata.AHBPrescTable
-                0x08005f34       0x10 ./Core/Src/system_stm32f1xx.o
-                0x08005f34                AHBPrescTable
+                0x08007a60       0x10 ./Core/Src/system_stm32f1xx.o
+                0x08007a60                AHBPrescTable
  .rodata.APBPrescTable
-                0x08005f44        0x8 ./Core/Src/system_stm32f1xx.o
-                0x08005f44                APBPrescTable
+                0x08007a70        0x8 ./Core/Src/system_stm32f1xx.o
+                0x08007a70                APBPrescTable
  .rodata.aPLLMULFactorTable.1
-                0x08005f4c       0x10 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x08007a78       0x10 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .rodata.aPredivFactorTable.0
-                0x08005f5c        0x2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
- *fill*         0x08005f5e        0x2 
- .rodata.tiny   0x08005f60        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-ef_sqrt.o)
- .rodata.one    0x08005f64        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-ef_sqrt.o)
-                0x08005f68                        . = ALIGN (0x4)
+                0x08007a88        0x2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ *fill*         0x08007a8a        0x2 
+ .rodata.aPLLMULFactorTable.1
+                0x08007a8c       0x10 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .rodata.aPredivFactorTable.0
+                0x08007a9c        0x2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ *fill*         0x08007a9e        0x2 
+ .rodata.tiny   0x08007aa0        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-ef_sqrt.o)
+ .rodata.one    0x08007aa4        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-ef_sqrt.o)
+                0x08007aa8                        . = ALIGN (0x4)
 
-.ARM.extab      0x08005f68        0x0
-                0x08005f68                        . = ALIGN (0x4)
+.ARM.extab      0x08007aa8        0x0
+                0x08007aa8                        . = ALIGN (0x4)
  *(.ARM.extab* .gnu.linkonce.armextab.*)
-                0x08005f68                        . = ALIGN (0x4)
+                0x08007aa8                        . = ALIGN (0x4)
 
-.ARM            0x08005f68        0x8
-                0x08005f68                        . = ALIGN (0x4)
-                0x08005f68                        __exidx_start = .
+.ARM            0x08007aa8        0x8
+                0x08007aa8                        . = ALIGN (0x4)
+                0x08007aa8                        __exidx_start = .
  *(.ARM.exidx*)
- .ARM.exidx     0x08005f68        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
-                0x08005f70                        __exidx_end = .
-                0x08005f70                        . = ALIGN (0x4)
+ .ARM.exidx     0x08007aa8        0x8 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
+                0x08007ab0                        __exidx_end = .
+                0x08007ab0                        . = ALIGN (0x4)
 
-.preinit_array  0x08005f70        0x0
-                0x08005f70                        . = ALIGN (0x4)
-                0x08005f70                        PROVIDE (__preinit_array_start = .)
+.preinit_array  0x08007ab0        0x0
+                0x08007ab0                        . = ALIGN (0x4)
+                0x08007ab0                        PROVIDE (__preinit_array_start = .)
  *(.preinit_array*)
-                0x08005f70                        PROVIDE (__preinit_array_end = .)
-                0x08005f70                        . = ALIGN (0x4)
+                0x08007ab0                        PROVIDE (__preinit_array_end = .)
+                0x08007ab0                        . = ALIGN (0x4)
 
-.init_array     0x08005f70        0x4
-                0x08005f70                        . = ALIGN (0x4)
-                0x08005f70                        PROVIDE (__init_array_start = .)
+.init_array     0x08007ab0        0x4
+                0x08007ab0                        . = ALIGN (0x4)
+                0x08007ab0                        PROVIDE (__init_array_start = .)
  *(SORT_BY_NAME(.init_array.*))
  *(.init_array*)
- .init_array    0x08005f70        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
-                0x08005f74                        PROVIDE (__init_array_end = .)
-                0x08005f74                        . = ALIGN (0x4)
+ .init_array    0x08007ab0        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+                0x08007ab4                        PROVIDE (__init_array_end = .)
+                0x08007ab4                        . = ALIGN (0x4)
 
-.fini_array     0x08005f74        0x4
-                0x08005f74                        . = ALIGN (0x4)
+.fini_array     0x08007ab4        0x4
+                0x08007ab4                        . = ALIGN (0x4)
                 [!provide]                        PROVIDE (__fini_array_start = .)
  *(SORT_BY_NAME(.fini_array.*))
  *(.fini_array*)
- .fini_array    0x08005f74        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+ .fini_array    0x08007ab4        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
                 [!provide]                        PROVIDE (__fini_array_end = .)
-                0x08005f78                        . = ALIGN (0x4)
-                0x08005f78                        _sidata = LOADADDR (.data)
+                0x08007ab8                        . = ALIGN (0x4)
+                0x08007ab8                        _sidata = LOADADDR (.data)
 
-.rel.dyn        0x08005f78        0x0
- .rel.iplt      0x08005f78        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+.rel.dyn        0x08007ab8        0x0
+ .rel.iplt      0x08007ab8        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
 
-.data           0x20000000       0x78 load address 0x08005f78
+.data           0x20000000       0x80 load address 0x08007ab8
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _sdata = .
  *(.data)
@@ -4301,117 +5088,140 @@ LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.exte
                 0x2000000c        0x5 ./Core/Src/main.o
                 0x2000000c                newline_admi
  *fill*         0x20000011        0x3 
- .data.newline_real
+ .data.newline_temp
                 0x20000014        0x5 ./Core/Src/main.o
-                0x20000014                newline_real
+                0x20000014                newline_temp
  *fill*         0x20000019        0x3 
+ .data.newline_real
+                0x2000001c        0x5 ./Core/Src/main.o
+                0x2000001c                newline_real
+ *fill*         0x20000021        0x3 
  .data.SystemCoreClock
-                0x2000001c        0x4 ./Core/Src/system_stm32f1xx.o
-                0x2000001c                SystemCoreClock
+                0x20000024        0x4 ./Core/Src/system_stm32f1xx.o
+                0x20000024                SystemCoreClock
  .data.uwTickPrio
-                0x20000020        0x4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x20000020                uwTickPrio
+                0x20000028        0x4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x20000028                uwTickPrio
  .data.uwTickFreq
-                0x20000024        0x1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x20000024                uwTickFreq
- *fill*         0x20000025        0x3 
+                0x2000002c        0x1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x2000002c                uwTickFreq
+ *fill*         0x2000002d        0x3 
  .data._impure_ptr
-                0x20000028        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
-                0x20000028                _impure_ptr
+                0x20000030        0x4 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
+                0x20000030                _impure_ptr
  .data._impure_data
-                0x2000002c       0x4c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
-                0x2000002c                _impure_data
+                0x20000034       0x4c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
+                0x20000034                _impure_data
  *(.RamFunc)
  *(.RamFunc*)
-                0x20000078                        . = ALIGN (0x4)
-                0x20000078                        _edata = .
+                0x20000080                        . = ALIGN (0x4)
+                0x20000080                        _edata = .
 
-.igot.plt       0x20000078        0x0 load address 0x08005ff0
- .igot.plt      0x20000078        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
-                0x20000078                        . = ALIGN (0x4)
+.igot.plt       0x20000080        0x0 load address 0x08007b38
+ .igot.plt      0x20000080        0x0 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+                0x20000080                        . = ALIGN (0x4)
 
-.bss            0x20000078      0x3e4 load address 0x08005ff0
-                0x20000078                        _sbss = .
-                0x20000078                        __bss_start__ = _sbss
+.bss            0x20000080      0x890 load address 0x08007b38
+                0x20000080                        _sbss = .
+                0x20000080                        __bss_start__ = _sbss
  *(.bss)
- .bss           0x20000078       0x1c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
+ .bss           0x20000080       0x1c C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp/crtbegin.o
  *(.bss*)
  .bss.temperature_dut_samples
-                0x20000094       0x20 ./Core/Src/ad5934_driver.o
-                0x20000094                temperature_dut_samples
+                0x2000009c       0x20 ./Core/Src/ad5934_driver.o
+                0x2000009c                temperature_dut_samples
  .bss.temperature_ref_samples
-                0x200000b4       0x20 ./Core/Src/ad5934_driver.o
-                0x200000b4                temperature_ref_samples
+                0x200000bc       0x20 ./Core/Src/ad5934_driver.o
+                0x200000bc                temperature_ref_samples
  .bss.temperature_display
-                0x200000d4       0x20 ./Core/Src/ad5934_driver.o
-                0x200000d4                temperature_display
+                0x200000dc       0x20 ./Core/Src/ad5934_driver.o
+                0x200000dc                temperature_display
  .bss.ec_dut_samples
-                0x200000f4       0x20 ./Core/Src/ad5934_driver.o
-                0x200000f4                ec_dut_samples
- .bss.ec_ref_samples_H
-                0x20000114       0x20 ./Core/Src/ad5934_driver.o
-                0x20000114                ec_ref_samples_H
- .bss.ec_ref_samples_L
-                0x20000134       0x20 ./Core/Src/ad5934_driver.o
-                0x20000134                ec_ref_samples_L
- .bss.hadc1     0x20000154       0x30 ./Core/Src/adc.o
-                0x20000154                hadc1
- .bss.hadc2     0x20000184       0x30 ./Core/Src/adc.o
-                0x20000184                hadc2
- .bss.temp_calib
-                0x200001b4        0x4 ./Core/Src/ads1015_driver.o
-                0x200001b4                temp_calib
- .bss.ph_compensated
-                0x200001b8        0x4 ./Core/Src/ads1015_driver.o
-                0x200001b8                ph_compensated
- .bss.v_ph4     0x200001bc        0x4 ./Core/Src/ads1015_driver.o
-                0x200001bc                v_ph4
- .bss.v_ph7     0x200001c0        0x4 ./Core/Src/ads1015_driver.o
-                0x200001c0                v_ph7
+                0x200000fc       0x20 ./Core/Src/ad5934_driver.o
+                0x200000fc                ec_dut_samples
+ .bss.hadc1     0x2000011c       0x30 ./Core/Src/adc.o
+                0x2000011c                hadc1
+ .bss.hadc2     0x2000014c       0x30 ./Core/Src/adc.o
+                0x2000014c                hadc2
+ .bss.hdma_adc1
+                0x2000017c       0x44 ./Core/Src/adc.o
+                0x2000017c                hdma_adc1
+ .bss.i2c       0x200001c0       0x10 ./Core/Src/ads1015_driver.o
+                0x200001c0                i2c
+ .bss.ph_dut_samples
+                0x200001d0       0x20 ./Core/Src/ads1015_driver.o
+                0x200001d0                ph_dut_samples
  .bss.pin_states
-                0x200001c4        0x8 ./Core/Src/digital_outputs_driver.o
+                0x200001f0        0x8 ./Core/Src/digital_outputs_driver.o
+ .bss.flash_data
+                0x200001f8      0x400 ./Core/Src/flash_manager.o
+                0x200001f8                flash_data
  .bss.last_interrupt_time
-                0x200001cc        0x4 ./Core/Src/gpio.o
-                0x200001cc                last_interrupt_time
+                0x200005f8        0x4 ./Core/Src/gpio.o
+                0x200005f8                last_interrupt_time
  .bss.original_pin_state
-                0x200001d0        0x1 ./Core/Src/gpio.o
-                0x200001d0                original_pin_state
+                0x200005fc        0x1 ./Core/Src/gpio.o
+                0x200005fc                original_pin_state
  .bss.edge_state
-                0x200001d1        0x1 ./Core/Src/gpio.o
-                0x200001d1                edge_state
- *fill*         0x200001d2        0x2 
- .bss.hi2c1     0x200001d4       0x54 ./Core/Src/i2c.o
-                0x200001d4                hi2c1
- .bss.hi2c2     0x20000228       0x54 ./Core/Src/i2c.o
-                0x20000228                hi2c2
- .bss.i2c       0x2000027c       0x10 ./Core/Src/main.o
-                0x2000027c                i2c
+                0x200005fd        0x1 ./Core/Src/gpio.o
+                0x200005fd                edge_state
+ *fill*         0x200005fe        0x2 
+ .bss.hi2c1     0x20000600       0x54 ./Core/Src/i2c.o
+                0x20000600                hi2c1
+ .bss.hi2c2     0x20000654       0x54 ./Core/Src/i2c.o
+                0x20000654                hi2c2
+ .bss.main_state
+                0x200006a8        0x1 ./Core/Src/main.o
+                0x200006a8                main_state
+ *fill*         0x200006a9        0x3 
+ .bss.AD_RES    0x200006ac        0x4 ./Core/Src/main.o
+                0x200006ac                AD_RES
+ .bss.UpdateEvent
+                0x200006b0        0x1 ./Core/Src/main.o
+                0x200006b0                UpdateEvent
+ *fill*         0x200006b1        0x3 
+ .bss.Temperature
+                0x200006b4        0x4 ./Core/Src/main.o
+                0x200006b4                Temperature
+ .bss.Temp_Sum  0x200006b8        0x4 ./Core/Src/main.o
+                0x200006b8                Temp_Sum
+ .bss.V_Sense   0x200006bc        0x4 ./Core/Src/main.o
+                0x200006bc                V_Sense
+ .bss.V_Ref     0x200006c0        0x4 ./Core/Src/main.o
+                0x200006c0                V_Ref
+ .bss.Temp_Samples
+                0x200006c4       0x10 ./Core/Src/main.o
+                0x200006c4                Temp_Samples
  .bss.device_address
-                0x2000028c        0x3 ./Core/Src/rs485_driver.o
- *fill*         0x2000028f        0x1 
- .bss.huart1    0x20000290       0x48 ./Core/Src/rs485_driver.o
- .bss.huart1    0x200002d8       0x48 ./Core/Src/usart.o
-                0x200002d8                huart1
- .bss.uwTick    0x20000320        0x4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
-                0x20000320                uwTick
- .bss.__sf      0x20000324      0x138 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-findfp.o)
-                0x20000324                __sf
+                0x200006d4        0x3 ./Core/Src/rs485_driver.o
+ *fill*         0x200006d7        0x1 
+ .bss.huart1    0x200006d8       0x48 ./Core/Src/rs485_driver.o
+ .bss.htim3     0x20000720       0x48 ./Core/Src/tim.o
+                0x20000720                htim3
+ .bss.huart1    0x20000768       0x48 ./Core/Src/usart.o
+                0x20000768                huart1
+ .bss.uwTick    0x200007b0        0x4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x200007b0                uwTick
+ *fill*         0x200007b4        0x4 
+ .bss.pFlash    0x200007b8       0x20 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+                0x200007b8                pFlash
+ .bss.__sf      0x200007d8      0x138 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-findfp.o)
+                0x200007d8                __sf
  *(COMMON)
-                0x2000045c                        . = ALIGN (0x4)
-                0x2000045c                        _ebss = .
-                0x2000045c                        __bss_end__ = _ebss
+                0x20000910                        . = ALIGN (0x4)
+                0x20000910                        _ebss = .
+                0x20000910                        __bss_end__ = _ebss
 
 ._user_heap_stack
-                0x2000045c      0x604 load address 0x08005ff0
-                0x20000460                        . = ALIGN (0x8)
- *fill*         0x2000045c        0x4 
+                0x20000910      0x600 load address 0x08007b38
+                0x20000910                        . = ALIGN (0x8)
                 [!provide]                        PROVIDE (end = .)
-                0x20000460                        PROVIDE (_end = .)
-                0x20000660                        . = (. + _Min_Heap_Size)
- *fill*         0x20000460      0x200 
-                0x20000a60                        . = (. + _Min_Stack_Size)
- *fill*         0x20000660      0x400 
-                0x20000a60                        . = ALIGN (0x8)
+                0x20000910                        PROVIDE (_end = .)
+                0x20000b10                        . = (. + _Min_Heap_Size)
+ *fill*         0x20000910      0x200 
+                0x20000f10                        . = (. + _Min_Stack_Size)
+ *fill*         0x20000b10      0x400 
+                0x20000f10                        . = ALIGN (0x8)
 
 /DISCARD/
  libc.a(*)
@@ -4434,132 +5244,170 @@ LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.exte
  .ARM.attributes
                 0x000000d1       0x2d ./Core/Src/digital_outputs_driver.o
  .ARM.attributes
-                0x000000fe       0x2d ./Core/Src/gpio.o
+                0x000000fe       0x2d ./Core/Src/dma.o
  .ARM.attributes
-                0x0000012b       0x2d ./Core/Src/i2c.o
+                0x0000012b       0x2d ./Core/Src/flash_manager.o
  .ARM.attributes
-                0x00000158       0x2d ./Core/Src/main.o
+                0x00000158       0x2d ./Core/Src/gpio.o
  .ARM.attributes
-                0x00000185       0x2d ./Core/Src/rs485_driver.o
+                0x00000185       0x2d ./Core/Src/i2c.o
  .ARM.attributes
-                0x000001b2       0x2d ./Core/Src/stm32f1xx_hal_msp.o
+                0x000001b2       0x2d ./Core/Src/main.o
  .ARM.attributes
-                0x000001df       0x2d ./Core/Src/stm32f1xx_it.o
+                0x000001df       0x2d ./Core/Src/rs485_driver.o
  .ARM.attributes
-                0x0000020c       0x2d ./Core/Src/system_stm32f1xx.o
+                0x0000020c       0x2d ./Core/Src/stm32f1xx_hal_msp.o
  .ARM.attributes
-                0x00000239       0x2d ./Core/Src/usart.o
+                0x00000239       0x2d ./Core/Src/stm32f1xx_it.o
  .ARM.attributes
-                0x00000266       0x21 ./Core/Startup/startup_stm32f103c8tx.o
+                0x00000266       0x2d ./Core/Src/system_stm32f1xx.o
  .ARM.attributes
-                0x00000287       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+                0x00000293       0x2d ./Core/Src/tim.o
  .ARM.attributes
-                0x000002b4       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+                0x000002c0       0x2d ./Core/Src/usart.o
  .ARM.attributes
-                0x000002e1       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+                0x000002ed       0x21 ./Core/Startup/startup_stm32f103c8tx.o
  .ARM.attributes
-                0x0000030e       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+                0x0000030e       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .ARM.attributes
-                0x0000033b       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+                0x0000033b       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
  .ARM.attributes
-                0x00000368       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+                0x00000368       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .ARM.attributes
-                0x00000395       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+                0x00000395       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .ARM.attributes
-                0x000003c2       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+                0x000003c2       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
  .ARM.attributes
-                0x000003ef       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+                0x000003ef       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
  .ARM.attributes
-                0x0000041c       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-findfp.o)
+                0x0000041c       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .ARM.attributes
-                0x00000449       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memset.o)
+                0x00000449       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .ARM.attributes
-                0x00000476       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
+                0x00000476       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .ARM.attributes
-                0x000004a3       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-errno.o)
+                0x000004a3       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .ARM.attributes
-                0x000004d0       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-init.o)
+                0x000004d0       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
  .ARM.attributes
-                0x000004fd       0x17 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-strlen.o)
+                0x000004fd       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
  .ARM.attributes
-                0x00000514       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-wf_sqrt.o)
+                0x0000052a       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
  .ARM.attributes
-                0x00000541       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-ef_sqrt.o)
+                0x00000557       0x2d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  .ARM.attributes
-                0x0000056e       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a(libm_a-sf_round.o)
+                0x00000584       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-findfp.o)
  .ARM.attributes
-                0x0000059b       0x1d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_muldf3.o)
+                0x000005b1       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memset.o)
  .ARM.attributes
-                0x000005b8       0x1d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_addsubdf3.o)
+                0x000005de       0x2d C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-impure.o)
  .ARM.attributes
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  .debug_aranges
                 0x00000148       0x40 ./Core/Src/digital_outputs_driver.o
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  .debug_rnglists
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+.debug_macro    0x00000000    0x1ae5b
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+ .debug_macro   0x00016bba      0x1cd ./Core/Src/ad5934_driver.o
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+ .debug_macro   0x00016f77      0x23f ./Core/Src/ad5934_driver.o
+ .debug_macro   0x000171b6      0x1da ./Core/Src/adc.o
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+ .debug_macro   0x00017557      0x2bb ./Core/Src/ads1015_driver.o
+ .debug_macro   0x00017812      0x16e ./Core/Src/ads1015_driver.o
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+ .debug_macro   0x00017d38      0x29d ./Core/Src/flash_manager.o
+ .debug_macro   0x00017fd5      0x1df ./Core/Src/gpio.o
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+ .debug_macro   0x000181ca      0x1da ./Core/Src/i2c.o
+ .debug_macro   0x000183a4      0x392 ./Core/Src/main.o
+ .debug_macro   0x00018736       0x1c ./Core/Src/main.o
+ .debug_macro   0x00018752      0x229 ./Core/Src/main.o
+ .debug_macro   0x0001897b       0x28 ./Core/Src/main.o
+ .debug_macro   0x000189a3      0x1d9 ./Core/Src/rs485_driver.o
+ .debug_macro   0x00018b7c      0x1d0 ./Core/Src/stm32f1xx_hal_msp.o
+ .debug_macro   0x00018d4c      0x1da ./Core/Src/stm32f1xx_it.o
+ .debug_macro   0x00018f26      0x1c1 ./Core/Src/system_stm32f1xx.o
+ .debug_macro   0x000190e7      0x1da ./Core/Src/tim.o
+ .debug_macro   0x000192c1      0x1da ./Core/Src/usart.o
+ .debug_macro   0x0001949b      0x1e5 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_macro   0x00019680      0x1de ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_macro   0x0001985e      0x1d3 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_macro   0x00019a31      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
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+ .debug_macro   0x00019db3      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_macro   0x00019f74      0x1d3 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .debug_macro   0x0001a147      0x22c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+ .debug_macro   0x0001a373      0x20f ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .debug_macro   0x0001a582      0x1d3 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .debug_macro   0x0001a755      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .debug_macro   0x0001a916      0x1c2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .debug_macro   0x0001aad8      0x1c1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_macro   0x0001ac99      0x1c2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
 
-.debug_line     0x00000000    0x12131
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- .debug_line    0x0000540d      0x7f6 ./Core/Src/stm32f1xx_it.o
- .debug_line    0x00005c03      0x796 ./Core/Src/system_stm32f1xx.o
- .debug_line    0x00006399      0x78e ./Core/Src/usart.o
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- .debug_line    0x00006b9f      0x9ca ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
- .debug_line    0x00007569      0xfec ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .debug_line    0x00008555      0xb91 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
- .debug_line    0x000090e6      0xdd1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .debug_line    0x00009eb7      0xa21 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
- .debug_line    0x0000a8d8     0x3bc4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
- .debug_line    0x0000e49c      0xe80 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
- .debug_line    0x0000f31c      0x932 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .debug_line    0x0000fc4e     0x24e3 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
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+ .debug_line    0x0000172a      0xbf5 ./Core/Src/ads1015_driver.o
+ .debug_line    0x0000231f      0x850 ./Core/Src/digital_outputs_driver.o
+ .debug_line    0x00002b6f      0x744 ./Core/Src/dma.o
+ .debug_line    0x000032b3      0x948 ./Core/Src/flash_manager.o
+ .debug_line    0x00003bfb      0x7fd ./Core/Src/gpio.o
+ .debug_line    0x000043f8      0x820 ./Core/Src/i2c.o
+ .debug_line    0x00004c18      0xd3c ./Core/Src/main.o
+ .debug_line    0x00005954      0x8cd ./Core/Src/rs485_driver.o
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+ .debug_line    0x0000696a      0x83f ./Core/Src/stm32f1xx_it.o
+ .debug_line    0x000071a9      0x7c7 ./Core/Src/system_stm32f1xx.o
+ .debug_line    0x00007970      0x7bf ./Core/Src/tim.o
+ .debug_line    0x0000812f      0x7bf ./Core/Src/usart.o
+ .debug_line    0x000088ee       0x78 ./Core/Startup/startup_stm32f103c8tx.o
+ .debug_line    0x00008966      0x9fb ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_line    0x00009361     0x101d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_line    0x0000a37e      0xd3f ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_line    0x0000b0bd      0xbc2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+ .debug_line    0x0000bc7f      0xe02 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .debug_line    0x0000ca81      0xab2 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_line    0x0000d533      0xbbf ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .debug_line    0x0000e0f2      0xa52 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+ .debug_line    0x0000eb44     0x3bf5 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .debug_line    0x00012739      0xeb1 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .debug_line    0x000135ea      0x963 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .debug_line    0x00013f4d     0x34ec ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .debug_line    0x00017439     0x18bc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_line    0x00018cf5     0x2514 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
 
-.debug_str      0x00000000    0x8c894
- .debug_str     0x00000000    0x8c894 ./Core/Src/ad5934_driver.o
-                              0x876d8 (size before relaxing)
- .debug_str     0x0008c894    0x837f3 ./Core/Src/adc.o
- .debug_str     0x0008c894    0x84373 ./Core/Src/ads1015_driver.o
- .debug_str     0x0008c894    0x8356a ./Core/Src/digital_outputs_driver.o
- .debug_str     0x0008c894    0x83837 ./Core/Src/gpio.o
- .debug_str     0x0008c894    0x83908 ./Core/Src/i2c.o
- .debug_str     0x0008c894    0x898d1 ./Core/Src/main.o
- .debug_str     0x0008c894    0x8436d ./Core/Src/rs485_driver.o
- .debug_str     0x0008c894    0x833c3 ./Core/Src/stm32f1xx_hal_msp.o
- .debug_str     0x0008c894    0x8383d ./Core/Src/stm32f1xx_it.o
- .debug_str     0x0008c894    0x82d30 ./Core/Src/system_stm32f1xx.o
- .debug_str     0x0008c894    0x83b9e ./Core/Src/usart.o
- .debug_str     0x0008c894       0x6e ./Core/Startup/startup_stm32f103c8tx.o
- .debug_str     0x0008c894    0x83463 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
- .debug_str     0x0008c894    0x83414 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .debug_str     0x0008c894    0x833af ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
- .debug_str     0x0008c894    0x830d9 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .debug_str     0x0008c894    0x830b6 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
- .debug_str     0x0008c894    0x83df7 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
- .debug_str     0x0008c894    0x8315f ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
- .debug_str     0x0008c894    0x82eaf ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
- .debug_str     0x0008c894    0x837d0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
+.debug_str      0x00000000    0x9592c
+ .debug_str     0x00000000    0x9592c ./Core/Src/ad5934_driver.o
+                              0x8eeb0 (size before relaxing)
+ .debug_str     0x0009592c    0x8a631 ./Core/Src/adc.o
+ .debug_str     0x0009592c    0x8e3d4 ./Core/Src/ads1015_driver.o
+ .debug_str     0x0009592c    0x8a382 ./Core/Src/digital_outputs_driver.o
+ .debug_str     0x0009592c    0x8a4b1 ./Core/Src/dma.o
+ .debug_str     0x0009592c    0x8cd4b ./Core/Src/flash_manager.o
+ .debug_str     0x0009592c    0x8a65a ./Core/Src/gpio.o
+ .debug_str     0x0009592c    0x8a720 ./Core/Src/i2c.o
+ .debug_str     0x0009592c    0x90f47 ./Core/Src/main.o
+ .debug_str     0x0009592c    0x8b0b6 ./Core/Src/rs485_driver.o
+ .debug_str     0x0009592c    0x8a1db ./Core/Src/stm32f1xx_hal_msp.o
+ .debug_str     0x0009592c    0x8a68b ./Core/Src/stm32f1xx_it.o
+ .debug_str     0x0009592c    0x89a79 ./Core/Src/system_stm32f1xx.o
+ .debug_str     0x0009592c    0x8a7e1 ./Core/Src/tim.o
+ .debug_str     0x0009592c    0x8a9b6 ./Core/Src/usart.o
+ .debug_str     0x0009592c       0x6e ./Core/Startup/startup_stm32f103c8tx.o
+ .debug_str     0x0009592c    0x8a1ac ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_str     0x0009592c    0x8a15d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_str     0x0009592c    0x8a12d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_str     0x0009592c    0x8a0f8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
+ .debug_str     0x0009592c    0x89e22 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .debug_str     0x0009592c    0x89d54 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_str     0x0009592c    0x89f02 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
+ .debug_str     0x0009592c    0x89dff ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
+ .debug_str     0x0009592c    0x8ab40 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
+ .debug_str     0x0009592c    0x89ea8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
+ .debug_str     0x0009592c    0x89bf8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .debug_str     0x0009592c    0x8aeaa ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .debug_str     0x0009592c    0x8a6b6 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_str     0x0009592c    0x8a519 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
 
 .comment        0x00000000       0x43
  .comment       0x00000000       0x43 ./Core/Src/ad5934_driver.o
@@ -4796,6 +5703,8 @@ LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.exte
  .comment       0x00000043       0x44 ./Core/Src/adc.o
  .comment       0x00000043       0x44 ./Core/Src/ads1015_driver.o
  .comment       0x00000043       0x44 ./Core/Src/digital_outputs_driver.o
+ .comment       0x00000043       0x44 ./Core/Src/dma.o
+ .comment       0x00000043       0x44 ./Core/Src/flash_manager.o
  .comment       0x00000043       0x44 ./Core/Src/gpio.o
  .comment       0x00000043       0x44 ./Core/Src/i2c.o
  .comment       0x00000043       0x44 ./Core/Src/main.o
@@ -4803,55 +5712,72 @@ LOAD C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.exte
  .comment       0x00000043       0x44 ./Core/Src/stm32f1xx_hal_msp.o
  .comment       0x00000043       0x44 ./Core/Src/stm32f1xx_it.o
  .comment       0x00000043       0x44 ./Core/Src/system_stm32f1xx.o
+ .comment       0x00000043       0x44 ./Core/Src/tim.o
  .comment       0x00000043       0x44 ./Core/Src/usart.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
+ .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
+ .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
+ .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
  .comment       0x00000043       0x44 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
 
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  .debug_frame   0x00000224       0xa0 ./Core/Src/adc.o
  .debug_frame   0x000002c4      0x1e8 ./Core/Src/ads1015_driver.o
  .debug_frame   0x000004ac       0xc4 ./Core/Src/digital_outputs_driver.o
- .debug_frame   0x00000570       0x58 ./Core/Src/gpio.o
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- .debug_frame   0x00000658       0xb4 ./Core/Src/main.o
- .debug_frame   0x0000070c      0x15c ./Core/Src/rs485_driver.o
- .debug_frame   0x00000868       0x34 ./Core/Src/stm32f1xx_hal_msp.o
- .debug_frame   0x0000089c      0x130 ./Core/Src/stm32f1xx_it.o
- .debug_frame   0x000009cc       0x50 ./Core/Src/system_stm32f1xx.o
- .debug_frame   0x00000a1c       0x74 ./Core/Src/usart.o
- .debug_frame   0x00000a90      0x2e4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
- .debug_frame   0x00000d74      0x3e0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
- .debug_frame   0x00001154      0x3f0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
- .debug_frame   0x00001544      0x1e8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o
- .debug_frame   0x0000172c      0x130 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o
- .debug_frame   0x0000185c      0xbf4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o
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- .debug_frame   0x00002648       0x7c ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o
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- .debug_frame   0x00002fa0      0x144 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-findfp.o)
- .debug_frame   0x000030e4       0x20 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc_nano.a(libc_a-memset.o)
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+ .debug_frame   0x000005a4       0x5c ./Core/Src/flash_manager.o
+ .debug_frame   0x00000600       0x58 ./Core/Src/gpio.o
+ .debug_frame   0x00000658       0x90 ./Core/Src/i2c.o
+ .debug_frame   0x000006e8       0xe0 ./Core/Src/main.o
+ .debug_frame   0x000007c8      0x15c ./Core/Src/rs485_driver.o
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+ .debug_frame   0x00000be4      0x2e4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o
+ .debug_frame   0x00000ec8      0x3e0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o
+ .debug_frame   0x000012a8      0x1f4 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o
+ .debug_frame   0x0000149c      0x3f0 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o
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+ .debug_frame   0x00001a74      0x1e8 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o
+ .debug_frame   0x00001c5c      0x240 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o
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+ .debug_frame   0x00003f1c      0x600 ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
+ .debug_frame   0x0000451c      0x8dc ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
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+ .debug_frame   0x000053ec       0x24 C:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7-m/nofp\libgcc.a(_arm_fixsfsi.o)
 
 .debug_line_str
                 0x00000000       0x52
diff --git a/Fertirrega_v6/Debug/objects.list b/Fertirrega_v6/Debug/objects.list
index f9c78b7..fbb812a 100644
--- a/Fertirrega_v6/Debug/objects.list
+++ b/Fertirrega_v6/Debug/objects.list
@@ -3,6 +3,7 @@
 "./Core/Src/ads1015_driver.o"
 "./Core/Src/analog_loop_driver.o"
 "./Core/Src/digital_outputs_driver.o"
+"./Core/Src/dma.o"
 "./Core/Src/flash_manager.o"
 "./Core/Src/gpio.o"
 "./Core/Src/i2c.o"
@@ -13,6 +14,7 @@
 "./Core/Src/syscalls.o"
 "./Core/Src/sysmem.o"
 "./Core/Src/system_stm32f1xx.o"
+"./Core/Src/tim.o"
 "./Core/Src/usart.o"
 "./Core/Startup/startup_stm32f103c8tx.o"
 "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o"
@@ -29,4 +31,6 @@
 "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o"
 "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o"
 "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o"
+"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o"
+"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o"
 "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o"
diff --git a/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
new file mode 100644
index 0000000..ac72075
--- /dev/null
+++ b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
@@ -0,0 +1,2153 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_TIM_H
+#define STM32F1xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__HANDLE__)->Instance->CCR4))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_PERIOD(__PERIOD__)      (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   (__HANDLE__)->ChannelState[3])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                       (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \
+                                                                     } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+   (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32f1xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
+                                              uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_TIM_H */
diff --git a/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
new file mode 100644
index 0000000..3edc9d3
--- /dev/null
+++ b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
@@ -0,0 +1,261 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_TIM_EX_H
+#define STM32F1xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F1xx_HAL_TIM_EX_H */
diff --git a/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
new file mode 100644
index 0000000..d54a00e
--- /dev/null
+++ b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
@@ -0,0 +1,3901 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_TIM_H
+#define __STM32F1xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U    /* 6: TIMx_CH4  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U             /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U             /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U            /* 6: CC4P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U             /* 6: OIS4 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS1N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS1N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+  __IO uint32_t tmpreg;
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+  /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_TIM_H */
diff --git a/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
new file mode 100644
index 0000000..c00a9de
--- /dev/null
+++ b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
@@ -0,0 +1,7629 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData1 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData2 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  uint32_t itsource = htim->Instance->DIER;
+  uint32_t itflag   = htim->Instance->SR;
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+  {
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                              uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
+  *         supporting a break input.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+  }
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P);
+  tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P);
+  tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
new file mode 100644
index 0000000..8a565a6
--- /dev/null
+++ b/Fertirrega_v6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
@@ -0,0 +1,2359 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Timer remapping capabilities configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+  *         timer channels 1 and channel 2 are reserved and cannot be used for
+  *         other purpose.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_PERIOD(htim->Init.Period));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+  UNUSED(Remap);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Commutation callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Commutation half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return actual state of the TIM complementary channel.
+  * @param  htim TIM handle
+  * @param  ChannelN TIM Complementary channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @retval TIM Complementary channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+  return channel_state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA error callback (complementary channel)
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Fertirrega_v6/Fertirrega_v6.ioc b/Fertirrega_v6/Fertirrega_v6.ioc
index 9109494..4b2a143 100644
--- a/Fertirrega_v6/Fertirrega_v6.ioc
+++ b/Fertirrega_v6/Fertirrega_v6.ioc
@@ -1,18 +1,36 @@
 #MicroXplorer Configuration settings - do not modify
-ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_0
-ADC1.IPParameters=Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_VREFINT
+ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_TEMPSENSOR
+ADC1.ContinuousConvMode=DISABLE
+ADC1.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T3_TRGO
+ADC1.IPParameters=Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode,master,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,NbrOfConversion,ExternalTrigConv
+ADC1.NbrOfConversion=2
 ADC1.NbrOfConversionFlag=1
 ADC1.Rank-4\#ChannelRegularConversion=1
-ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.Rank-5\#ChannelRegularConversion=2
+ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
+ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
 ADC1.master=1
 ADC2.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_1
-ADC2.IPParameters=Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversionFlag
+ADC2.ContinuousConvMode=DISABLE
+ADC2.IPParameters=Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode
 ADC2.NbrOfConversionFlag=1
 ADC2.Rank-3\#ChannelRegularConversion=1
 ADC2.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
 CAD.formats=[]
 CAD.pinconfig=Dual
 CAD.provider=Component Search Engine
+Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.ADC1.0.Instance=DMA1_Channel1
+Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
+Dma.ADC1.0.MemInc=DMA_MINC_ENABLE
+Dma.ADC1.0.Mode=DMA_CIRCULAR
+Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
+Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE
+Dma.ADC1.0.Priority=DMA_PRIORITY_LOW
+Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
+Dma.Request0=ADC1
+Dma.RequestsNb=1
 File.Version=6
 GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
@@ -20,13 +38,15 @@ Mcu.CPN=STM32F103C8T6
 Mcu.Family=STM32F1
 Mcu.IP0=ADC1
 Mcu.IP1=ADC2
-Mcu.IP2=I2C1
-Mcu.IP3=I2C2
-Mcu.IP4=NVIC
-Mcu.IP5=RCC
-Mcu.IP6=SYS
-Mcu.IP7=USART1
-Mcu.IPNb=8
+Mcu.IP2=DMA
+Mcu.IP3=I2C1
+Mcu.IP4=I2C2
+Mcu.IP5=NVIC
+Mcu.IP6=RCC
+Mcu.IP7=SYS
+Mcu.IP8=TIM3
+Mcu.IP9=USART1
+Mcu.IPNb=10
 Mcu.Name=STM32F103C(8-B)Tx
 Mcu.Package=LQFP48
 Mcu.Pin0=PC13-TAMPER-RTC
@@ -60,20 +80,24 @@ Mcu.Pin33=PB6
 Mcu.Pin34=PB7
 Mcu.Pin35=PB8
 Mcu.Pin36=PB9
-Mcu.Pin37=VP_SYS_VS_Systick
+Mcu.Pin37=VP_ADC1_TempSens_Input
+Mcu.Pin38=VP_ADC1_Vref_Input
+Mcu.Pin39=VP_SYS_VS_Systick
 Mcu.Pin4=PD1-OSC_OUT
+Mcu.Pin40=VP_TIM3_VS_ClockSourceINT
 Mcu.Pin5=PA0-WKUP
 Mcu.Pin6=PA1
 Mcu.Pin7=PA2
 Mcu.Pin8=PA3
 Mcu.Pin9=PA4
-Mcu.PinsNb=38
+Mcu.PinsNb=41
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103C8Tx
 MxCube.Version=6.17.0
 MxDb.Version=DB.6.0.170
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.EXTI3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
@@ -311,41 +335,50 @@ ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_ADC2_Init-ADC2-false-HAL-true,5-MX_I2C1_Init-I2C1-false-HAL-true,6-MX_I2C2_Init-I2C2-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_I2C2_Init-I2C2-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true
 RCC.ADCFreqValue=1500000
 RCC.ADCPresc=RCC_ADCPCLK2_DIV8
-RCC.AHBFreq_Value=24000000
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.AHBFreq_Value=12000000
 RCC.APB1Freq_Value=12000000
-RCC.APB1TimFreq_Value=24000000
-RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB1TimFreq_Value=12000000
 RCC.APB2Freq_Value=12000000
-RCC.APB2TimFreq_Value=24000000
-RCC.FCLKCortexFreq_Value=24000000
+RCC.APB2TimFreq_Value=12000000
+RCC.FCLKCortexFreq_Value=12000000
 RCC.FamilyName=M
-RCC.HCLKFreq_Value=24000000
+RCC.HCLKFreq_Value=12000000
 RCC.HSE_VALUE=12000000
-RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,TimSys_Div,USBFreq_Value,VCOOutput2Freq_Value
-RCC.MCOFreq_Value=24000000
+RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.MCOFreq_Value=12000000
 RCC.PLLCLKFreq_Value=24000000
 RCC.PLLMCOFreq_Value=12000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.PREFETCH_ENABLE=1
-RCC.SYSCLKFreq_VALUE=24000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.TimSysFreq_Value=3000000
-RCC.TimSys_Div=SYSTICK_CLKSOURCE_HCLK_DIV8
+RCC.SYSCLKFreq_VALUE=12000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSE
+RCC.TimSysFreq_Value=12000000
 RCC.USBFreq_Value=24000000
 RCC.VCOOutput2Freq_Value=12000000
-SH.ADCx_IN0.0=ADC1_IN0,IN0
-SH.ADCx_IN0.ConfNb=1
+SH.ADCx_IN0.0=ADC1_IN0
+SH.ADCx_IN0.1=ADC2_IN0,IN0
+SH.ADCx_IN0.ConfNb=2
 SH.ADCx_IN1.0=ADC2_IN1,IN1
 SH.ADCx_IN1.1=ADC1_IN1
 SH.ADCx_IN1.ConfNb=2
 SH.GPXTI3.0=GPIO_EXTI3
 SH.GPXTI3.ConfNb=1
+TIM3.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
+TIM3.IPParameters=Prescaler,Period,AutoReloadPreload,TIM_MasterOutputTrigger
+TIM3.Period=59999
+TIM3.Prescaler=3
+TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
 USART1.IPParameters=VirtualMode
 USART1.VirtualMode=VM_ASYNC
+VP_ADC1_TempSens_Input.Mode=IN-TempSens
+VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
+VP_ADC1_Vref_Input.Mode=IN-Vrefint
+VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM3_VS_ClockSourceINT.Mode=Internal
+VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
 board=custom